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Annotation of driverkit/doc/OLD_NRW/HWGotchas.wn, revision 1.1

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        !             2: Z&�0���NRW Hardware�� "Gotchas"

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        !             3: Q&�@�`0�*       Mach vm calls (vm_allocate(), vm_copy(), etc.) made in the kernel need to cast the return from IOTaskSelf() to a 
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        !             4: Z&�0���NRW Hardware�� "Gotchas"

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        !             5: Q&�@�`0�*       The transfer engine should write out completed descriptors regardless of the direction of DMA transfer. It's currently impossible to determine whether or not a given descriptor was completed if

     a) The channel stopped due to a device-level error, and
        b) the transfer was a DMA write. 
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        !             6: Z&�0���NRW Hardware�� "Gotchas"

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        !             7: Q&�@�`0�*       The transfer engine should write out completed descriptors regardless of the direction of DMA transfer. It's currently impossible to determine whether or not a given descriptor was completed if

     a) The channel stopped due to a device-level error, and
        b) the transfer was a DMA write.

      In addition, it's really cumbersome to figure out which descriptors have been completed in other "DMA Write" cases. The DMA Read case is handled by a hack which determines whether or no a descriptor has been written back by the TE (its remaining byte count field is initialized to -1 when it's enqueued; if this changes, we assume the TE has completed the descriptor).

*     Having the same device index number for two devices (SCSI and Floppy) is brain damaged. This defeats the whole point of having device indices, which is to facilitate autoconfiguration and to avoid having the kernel to know about details of devices.  
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        !             8: Z&�0���NRW Hardware�� "Gotchas"

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        !             9: Q&�@�`0�*       The transfer engine should write out completed descriptors regardless of the direction of DMA transfer. It's currently impossible to determine whether or not a given descriptor was completed if

     a) The channel stopped due to a device-level error, and
        b) the transfer was a DMA write.

      In addition, it's really cumbersome to figure out which descriptors have been completed in other "DMA Write" cases. The DMA Read case is handled by a hack which determines whether or no a descriptor has been written back by the TE (its remaining byte count field is initialized to -1 when it's enqueued; if this changes, we assume the TE has completed the descriptor).
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    Also, there is an ambiguity in the hardware state which makes figuring out if the current descriptor has completed tricky. This is the fact that in a channel which is not running, we can't tell the difference between the last completed descriptor (for DMA write) and the first and only enqueued descriptor which has not been processed (hw_curr_desc is the same in both cases). We do another hack here, writing -1 to the count register to detect if it's changed later on.

        All of these hacks would go away if we could just look at a descriptor in memory and see a bit which says "completed".
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*     Having the same device index number for two devices (SCSI and Floppy) is brain damaged. This defeats the whole point of having device indices, which is to facilitate autoconfiguration and to avoid having the kernel to know about details of devices.

*     The procedure for enqueueing a DMA frame on a (possibly) running channel is way too complicated. This is due to the fact that updates to the descriptor list not empty bit (DNLE) are not atomic WRT updates of the TE register.   
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*    Having the same device index number for two devices (SCSI and Floppy) is brain damaged. This defeats the whole point of having device indices, which is to facilitate autoconfiguration and to avoid having the kernel to know about details of devices.

*     The procedure for enqueueing a DMA frame on a (possibly) running channel is way too complicated. This is due to the fact that updates to the descriptor list not empty bit (DNLE) are not atomic WRT updates of the TE register.   

*  Need to do serialize() (flush out write instructions before doing reads) in some critical code - when you are depending on the result of a previous write to a register during a read. 
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