File:  [Apple Darwin 0.x] / driverkit / doc / OLD_NRW / KernelLevelSupport.frame.backup
Revision 1.1.1.1 (vendor branch): download - view: text, annotated - select for diffs
Tue Apr 24 17:37:51 2018 UTC (8 years, 3 months ago) by root
Branches: MAIN, Apple
CVS tags: HEAD, Darwin03, Darwin02
Darwin 0.2 Driver Kit

<MakerFile 2.0J>
	

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ULAn  NRW DMA device driver can map in the first 0xf00000 (15 M) bytes of its �XUMUR��8
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oT�UR�� A
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V #import <Devices/user_driver.h>
 r�T�UR��`T
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 po�T�UR��`V
Ue int 
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 7d*�or++�to$6�+�*R$6�)-|chURUR�� b
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 #import <Devices/user_driver.h>
 mlUUR��`�
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aDESCRIPTION
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s$chan_return_t 
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U
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ar ;dev_port
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UT�T�UR��`�
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Ut 4CC_INTR_ENABLE -- enable interrupts on the channel
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[blRegister Mapping
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U�[This interface provides various mechanisms for device drivers to map the physical register SAB�U+UR��%
Urr[space associated with their devices into their local address space. Which mechanism(s) can ��U&UR��%
U
Zbe used by a particular device driver are determined by the machine architecture, whether U!UR��@%
U��_the device is a native device or a NextBus device, and the Slot ID in which the device lives. 
rog"UUR�� &
Ul,_For the purposes of the following discussion, an 
VNRW DMA Device
U is defined as a device ght/UUR��&
Upo[in an m88k machine which resides in a slot with whose NextBus slot Id bits 9 through 7 are que<UUR��@&
Uv_\'111'.  A 
Vnative device
U is a device which is an integral part of an m68k-based CPU.
deVU
UR�� '
Ure[There are three kinds of device register space which can be mapped in to a device driver's evicUUR��@'
Uoclocal address space:
e}UUR�� )
VUT\Register Space
U consists of one page (the size of which is machine dependent but can for or�T�UR��)
U mZnow be assumed to be 8k bytes) consisting of device-specific registers. For m88k devices, �T�UR��)
U sYthe format of a device page is defined in the NRW system spec, section 5.2.8.2. For m68k  �T�UR��)
Uth\devices, a device page is the physical memory region comprising all of the registers in one us�T�UR��@)
UloUnative device; the start of the register space may not be page-aligned in this case.
w�T�UR��`+
] m88k devices:
�T�UR�� /
Us TA driver can map in a register page if and only if it is associated with an NRW DMA e �T�UR��@/
Uts	Device. 
7T�UR��`(
]��m68k devices:
&T�UR��`1
Uic_A driver can map in a register page if and only if it is associated with a native device.
S 
re @T�UR��`4
SicP
VSlot Space 
Uconsists of up to 16 MB of memory, starting at 0xfs000000. 
ocZT�UR��`
]acm88k devices:
d6�st78�e $6�7�86ca$6�} ed 8URUR��`
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8�76 dH��X�
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_n O1--#./Running H/F 10:  2Running H/F 2;3PRELIMINARY4devd9�gi::�he$6�:�9)$6�3<| st(ceURUR�� �
UliDAll commands may be or'ed with CC_INTR_ENABLE or CC_INTR_DISABLE to /UMUR���
U m;form compound commands (e.g. CC_ABORT | CC_INTR_DISABLE or  NR!UHUR���
U��CCC_START_READ | CC_INTR_ENABLE).  Note than on NRW, CC_START_READ, `1.UCUR���
U mNCC_START_WRITE, and CC_ABORT are done by the driver by directly accessing the ;U>UR��@�
U4channel command register.
p����UT`
[chan_dma_enqueue()
 at�U5UR��`�
UT�*Add a DMA Frame to the current DMA queue.
�U0UR��`�
U
t�U+UR��`�
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 �U&UR��`�
V� #import <Devices/user_driver.h>
�U!UR��`
U(chan_return_t 
Vchan_dma_enqueue
U(
�X�UUR��`
Uport_t 
adev_port
U,
UUR��`
Uf int  
achan_num
U,
 UUR��`
URutask_t 
atask_port
U,
H/U
UR��`	
UMIvm_offset_t 
aaddr
U,
�(UUR��`

Uvm_size_t 
alen
U,
5UUR��`
Udirection_t 
arw
U,
BT�UR��`
Uchan_desc_cmd_t 
acmd
U,
DAlOT�UR��`

Uorunsigned char 
aindex
U,
R_D\T�UR��`
UUR$chan_enqueue_opts_t 
aopts
U,
e.iT�UR��`
UNTunsigned 
adma_id
U,
�vT�UR��`
UD boolean_t *
arunning
U);
NRW�T�UR��`
U1
C�T�UR�� 
VCCWchan_dma_enqueue
U  builds and enqueues a list of dma descriptors describing a block @��T�UR��
Uan]of memory.  This block of memory is referred to as a 
Vframe
U. The frame may cross page o�T�UR��
UueVboundaries in most cases. The exception is for channels which have been configured as �T�UR��
UX"streaming mode" channels per 
Vdev_chan_attach
U(). Frames for DMA read operations rt�T�UR��
U,S(device to memory) for streaming mode channels must not cross page boundaries. The at�T�UR��
UU
\reason for this restriction is that when the device-specific logic signals "End of record", 
�T�UR��
UWthe DMA hardware will advance to the next buffer descriptor, not the next frame. There UR�T�UR��
UsiOis no way for the hardware to advance to the next frame; frames are a software 
U�T�UR��
UTconstruct. Therefor for such channels, we force one frame to consist of exactly one );	T�UR��@
UDMA descriptor.
��#T�UR�� 
U_eRThere are system dependent limits to the amount of memory that may be queued with 0T�UR��
VofYchan_dma_enqueue
U; exceeding this limit will return an error and the data will not be o=T�UR��@
Uue
enqueued.
WT�UR�� 
ae baddr
U must be aligned to the size of the device buffer.  On m68K machines, 
alen
U must be dT�UR��
UanWa multiple of the device buffer length for all descriptors with CEO_EOR not set in the forqT�UR��
aan`opts
U argument. On m88k machines, 
alen
U must be a multiple of the device buffer length ha~T�UR��@
Uspfor DMA read operations.
fd;�th<<�va$6�<�; n$6�:>| isURUR��`
UrdCChains of DMA frames will be limited to some length by the kernel.
��!UMUR��`�
at.;dev_port
U is the kernel provided handle for the device.
 ex;UHUR��`
aUR(chan_num
U is a local channel number.
��UUCUR��`
ae :task_port
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oU>UR��`!
aURHaddr
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ro�U9UR��`#
al Dlen
U is the length of the dma in the target tasks address space.
 m�U4UR�� &
athTrw
U is the direction of the dma, either DMA_DIR_READ (from the device to memory) an�U/UR��@&
Ue .or DMA_DIR_WRITE (from memory to the device).
�U*UR��`(
ahe8cmd
U is a NRW channel descriptor command (m88k only)
ne�U%UR��`*
at \index
U  contains the region and register index to which cmd will be written (m88k only).
�U UR��`,
a[opts
U are channel options that should apply to the frame being enqueued. These include:
UUR�� -
UGCEO_EOR -- the last descriptor in the frame should be indicated as the e l%UUR��@-
Ul.end-of-record.
`�?UUR��`.
U i9CEO_DESC_INTR -- interrupt when this frame is completed.
�YUUR��`/
U
3CEO_ENABLE_INTR -- enable interrupt notification.
:tasUUR��`0
U tACEO_ENABLE_CHAN -- enable DMA channel after enqueue (m68k only).
i�UUR��`1
UUT?CEO_DESC_CMD -- enable channel descriptor command (m88k only)
Dle�T�UR�� 5
ah ^dma_id
U is an integer, uninterpreted by the kernel, whose sole purpose is to identify this �T�UR��@5
UMAZframe when 
Vchan_dma_dequeue
U()'d. 
adma_id
U must not be equal to DMA_ID_NULL.
�T�UR�� 7
aU*[running
U is returned; on the m68k this indicates whether the channel was enabled at the at �T�UR��7
UinStime of the enqueue (if not, a channel enable will be required). On the m88k, this ���T�UR��7
U aYindicates whetehr or not the transfer engine had a non-empty descriptor list at the time R�T�UR��7
UEO]of the enqueue. If on the m88k 
arunning
U is FALSE, a Load Descriptor operation will be fT�UR��@7
UUR necessary to start the channel.
erd=�
�>>�C$6�>�= n$6�<F|EN"HA����UT`9
[anchan_dma_dequeue()
8k &UNUR��`�
U��/Dequeue DMA frames from the current DMA queue.
tor=UIUR��`�
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Uh 
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Veg #import <Devices/user_driver.h>
hoU:UR��`;
U t(chan_return_t 
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U(
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Udeport_t 
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U,
 mu�U0UR��`=
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7�U+UR��`>
Uis#chan_dequeue_opt_t 
aopts
U,
 wh�U&UR��`?
Uwavm_size_t *
abcount
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��U!UR��`@
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U nboolean_t *
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U);
�U
UR��`D
UnqDESCRIPTION
e UUR�� J
VUGchan_dma_dequeue
U dequeues a single DMA frame which was enqueued by ess%UUR��J
VhaWchan_dma_enqueue
U.  It will only dequeue frames that meet the criteria specified in 2T�UR��J
a]opts
U. It unlocks the associated memory. It returns an indication if more descriptors are R?T�UR��@J
UUT8available to dequeue by the criteria specified in opts.
�YT�UR�� P
V��Mchan_dma_dequeue
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UurTspecified, the channel is running , and no completed frames are available. In other U0sT�UR��P
UTwords, it is not possible to dequeue non-completed descriptors while the channel is U&�T�UR��@P
U	running.
�T�UR��`R
aU!;dev_port
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UR�T�UR��`�
aa_*chan_num
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�T�UR��`�
an_Aopts
U are options to 
Vchan_dma_dequeue
U, these include:
��T�UR��`�
Unq+CDO_DONE -- dequeue only completed frames.
a_dT�UR��`�
Us CDO_ALL -- dequeue all frames.
eueT�UR��`�
U��*CDO_ENABLE_INTR -- enable interrupt msgs.
6T�UR�� �
UhaNCDO_EI_IF_MT -- reenables device interrupts for the device if  no more frames CT�UR��@�
Urymay be dequeued.
i]T�UR��`�
Ucr!The flags may be or'ed together.
vwT�UR�� �
a b\bcount
U(returned)  is the byte count of actually transferred data.  It is only valid for er�T�UR��@�
UheQtransfer from the device into memory (i.e. DMA reads).  Zero returned on writes.
od?�n @@�P$6�@�? d$6�H| c idE�
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Us.*meaning of this field is device-specific.
;UCUR�� �
ams\dma_status
U is machine-independent and indicates the current state of the channel (e.g., reHU>UR��@�
U��/running, idle, underrun). Only valid for m68k.
!ThbU9UR�� �
aed]eor
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e �U/UR�� �
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U]frame to the device driver. 
adma_id
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U]via 
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U. If 
adma_id 
Uis DMA_ID_NULL, no descriptors are available �U UR���
UURVfor dequeueing. (This is not an error - that is, 
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