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Annotation of drvEIDE/EIDE.drvproj/EIDE.lksproj/PIIX.h, revision 1.1

1.1     ! root        1: /*
        !             2:  * Copyright (c) 1999 Apple Computer, Inc. All rights reserved.
        !             3:  *
        !             4:  * @APPLE_LICENSE_HEADER_START@
        !             5:  * 
        !             6:  * "Portions Copyright (c) 1999 Apple Computer, Inc.  All Rights
        !             7:  * Reserved.  This file contains Original Code and/or Modifications of
        !             8:  * Original Code as defined in and that are subject to the Apple Public
        !             9:  * Source License Version 1.0 (the 'License').  You may not use this file
        !            10:  * except in compliance with the License.  Please obtain a copy of the
        !            11:  * License at http://www.apple.com/publicsource and read it before using
        !            12:  * this file.
        !            13:  * 
        !            14:  * The Original Code and all software distributed under the License are
        !            15:  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
        !            16:  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
        !            17:  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
        !            18:  * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
        !            19:  * License for the specific language governing rights and limitations
        !            20:  * under the License."
        !            21:  * 
        !            22:  * @APPLE_LICENSE_HEADER_END@
        !            23:  */
        !            24: /*
        !            25:  * Copyright 1998 by Apple Computer, Inc., All rights reserved.
        !            26:  *
        !            27:  * Intel PIIX/PIIX3/PIIX4 PCI IDE controller.
        !            28:  * PIIX = PCI-ISA-IDE-Xelerator. (USB also on newer controllers)
        !            29:  *
        !            30:  * Notes:
        !            31:  * 
        !            32:  * PIIX  introduced in the "Triton" chipset.
        !            33:  * PIIX3 supports different timings for Master/Slave devices on both channels.
        !            34:  * PIIX4 adds support for Ultra DMA/33.
        !            35:  *
        !            36:  * Be sure to download and read the PIIX errata from Intel's web site at
        !            37:  * developer.intel.com. Even then, don't trust everything you read.
        !            38:  *
        !            39:  * HISTORY:
        !            40:  * 1-Feb-1998  Joe Liu at Apple
        !            41:  *     Created.
        !            42:  */
        !            43: 
        !            44: /*
        !            45:  * PCI ID's.
        !            46:  */
        !            47: #define PCI_ID_PIIX            0x12308086
        !            48: #define PCI_ID_PIIX3   0x70108086
        !            49: #define PCI_ID_PIIX4   0x71118086
        !            50: #define PCI_ID_NONE            0xffffffff
        !            51: 
        !            52: /*
        !            53:  * Decoded port addresses. Seems to be hardcoded and it does not
        !            54:  * show up in the PCI configuration space memory ranges.
        !            55:  */
        !            56: #define PIIX_P_CMD_ADDR                0x1f0
        !            57: #define PIIX_P_CTL_ADDR                0x3f4
        !            58: #define PIIX_S_CMD_ADDR                0x170
        !            59: #define PIIX_S_CTL_ADDR                0x374
        !            60: #define PIIX_CMD_SIZE          8
        !            61: #define PIIX_CTL_SIZE          4
        !            62: 
        !            63: /*
        !            64:  * IRQ assignment.
        !            65:  */
        !            66: #define PIIX_P_IRQ                     14
        !            67: #define PIIX_S_IRQ                     15
        !            68: 
        !            69: /*
        !            70:  * PIIX PCI configuration space registers.
        !            71:  * Register size (bits) in parenthesis.
        !            72:  */
        !            73: #define PIIX_PCICMD            0x04    // (16) PCI command register
        !            74: #define PIIX_PCISTS            0x06    // (16) PCI device status register
        !            75: #define PIIX_RID               0x08    // (8)  Revision identification register
        !            76: #define PIIX_CLASSC            0x09    // (24) Class code register
        !            77: #define PIIX_MLT               0x0d    // (8)  Master latency timer register
        !            78: #define PIIX_HEDT              0x0e    // (8)  Header type register
        !            79: #define PIIX_BMIBA             0x20    // (32) Bus-Master interface base address
        !            80: #define PIIX_IDETIM            0x40    // (16) IDE timing registers (primary)
        !            81: #define PIIX_IDETIM_S  0x42    // (16) IDE timing registers (secondary)
        !            82: #define PIIX_SIDETIM   0x44    // (8)  Slave IDE timing register
        !            83: #define PIIX_UDMACTL   0x48    // (8)  Ultra DMA/33 control register
        !            84: #define PIIX_UDMATIM   0x4a    // (16) Ultra DMA/33 timing register
        !            85: 
        !            86: /*
        !            87:  * PIIX PCI configuration space register definition.
        !            88:  *
        !            89:  * PIIX_IDETIM - IDE timing register.
        !            90:  *
        !            91:  * Address:
        !            92:  * 0x40:0x41 - Primary channel
        !            93:  * 0x42:0x43 - Secondary channel
        !            94:  */
        !            95: typedef union {
        !            96:        struct {
        !            97:                u_short
        !            98:                        time0   :1,             // fast timing bank drive select 0
        !            99:                        ie0             :1,             // IORDY sample point enable driver select 0
        !           100:                        ppe0    :1,             // prefetch and posting enable
        !           101:                        dte0    :1,             // DMA timing enable only
        !           102:                        time1   :1,             // fast timing bank driver select 1
        !           103:                        ie1             :1,             // IORDY sample point enable driver select 1
        !           104:                        ppe1    :1,             // prefetch and posting enable
        !           105:                        dte1    :1,             // DMA timing enable only
        !           106:                        rct             :2,             // recovery time
        !           107:                        rsvd    :2,             // RESERVED
        !           108:                        isp             :2,             // IORDY sample point
        !           109:                        sitre   :1,             // slave IDE timing register enable
        !           110:                        ide             :1;             // IDE decode enable
        !           111:        } bits;
        !           112:        u_short word;
        !           113: } piix_idetim_u;
        !           114: 
        !           115: /*
        !           116:  * Convert the "isp" and "rct" fields in PIIX_IDETIM register from
        !           117:  * PCI clocks to their respective values, and vice-versa.
        !           118:  */
        !           119: #define PIIX_CLK_TO_ISP(x)             (5 - (x))
        !           120: #define PIIX_ISP_TO_CLK(x)             PIIX_CLK_TO_ISP(x)
        !           121: #define PIIX_CLK_TO_RCT(x)             (4 - (x))
        !           122: #define PIIX_RCT_TO_CLK(x)             PIIX_CLK_TO_RCT(x)
        !           123: 
        !           124: /*
        !           125:  * PIIX PCI configuration space register definition.
        !           126:  *
        !           127:  * PIIX_SIDETIM - Slave IDE timing register.
        !           128:  *
        !           129:  * Address: 0x44
        !           130:  */
        !           131: typedef union {
        !           132:        struct {
        !           133:                u_char
        !           134:                        prct1   :2,             // primary drive 1 recovery time
        !           135:                        pisp1   :2,             // primary drive 1 IORDY sample point
        !           136:                        srct1   :2,             // secondary drive 1 recovery time
        !           137:                        sisp1   :2;             // secondary drive 1 IORDY sample point
        !           138:        } bits;
        !           139:        u_char byte;
        !           140: } piix_sidetim_u;
        !           141: 
        !           142: /*
        !           143:  * PIIX PCI configuration space register definition.
        !           144:  *
        !           145:  * PIIX_UDMACTL - Ultra DMA/33 control register
        !           146:  *
        !           147:  * Address: 0x48
        !           148:  */
        !           149: typedef union {
        !           150:        struct {
        !           151:                u_char
        !           152:                        psde0   :1,             // enable Ultra DMA/33 for primary drive 0
        !           153:                        psde1   :1,             // enable Ultra DMA/33 for primary drive 1
        !           154:                        ssde0   :1,             // enable Ultra DMA/33 for secondary drive 0
        !           155:                        ssde1   :1,             // enable Ultra DMA/33 for secondary drive 1
        !           156:                        rsvd    :4;             // RESERVED
        !           157:        } bits;
        !           158:        u_char byte;
        !           159: } piix_udmactl_u;
        !           160: 
        !           161: /*
        !           162:  * PIIX PCI configuration space register definition.
        !           163:  *
        !           164:  * PIIX_UDMATIM - Ultra DMA/33 timing register
        !           165:  *
        !           166:  * Address: 0x4a-0x4b
        !           167:  */
        !           168: typedef union {
        !           169:        struct {
        !           170:                u_short
        !           171:                        pct0    :2,             // primary drive 0 cycle time
        !           172:                        rsvd1   :2,             // RESERVED
        !           173:                        pct1    :2,             // primary drive 1 cycle time
        !           174:                        rsvd2   :2,             // RESERVED
        !           175:                        sct0    :2,             // secondary drive 0 cycle time
        !           176:                        rsvd3   :2,             // RESERVED
        !           177:                        sct1    :2,             // secondary drive 1 cycle time
        !           178:                        rsvd4   :2;             // RESERVED
        !           179:        } bits;
        !           180:        u_short word;
        !           181: } piix_udmatim_u;
        !           182: 
        !           183: /*
        !           184:  * PIIX IO space register offsets. Base address is set in PIIX_BMIBA.
        !           185:  * Register size (bits) in parenthesis.
        !           186:  *
        !           187:  * Note:
        !           188:  * For the primary channel, the base address is stored in PIIX_BMIBA.
        !           189:  * For the secondary channel, the base address is equal to
        !           190:  * (PIIX_BMIBA + PIIX_BM_OFFSET).
        !           191:  */
        !           192: #define PIIX_BMICX             0x00    // (8) Bus master IDE command register
        !           193: #define PIIX_BMISX             0x02    // (8) Bus master IDE status register
        !           194: #define PIIX_BMIDTPX   0x04    // (32) Descriptor table pointer register
        !           195: #define PIIX_BM_OFFSET 0x08    // offset to secondary channel registers
        !           196: #define PIIX_BM_SIZE   0x08    // size of the BM registers for each channel
        !           197: #define PIIX_BM_MASK   0xfff0  // mask BMIBA to get register base address
        !           198: 
        !           199: /*
        !           200:  * PIIX IO space register definition.
        !           201:  *
        !           202:  * BMICX - Bus master IDE command register
        !           203:  */
        !           204: typedef union {
        !           205:        struct {
        !           206:                u_char
        !           207:                        ssbm    :1,             // start/stop bus master
        !           208:                        rsvd1   :2,             // RESERVED
        !           209:                        rwcon   :1,             // Bus master read/write control
        !           210:                        rsvd2   :4;             // RESERVED
        !           211:        } bits;
        !           212:        u_char byte;
        !           213: } piix_bmicx_u;
        !           214: 
        !           215: /*
        !           216:  * PIIX IO space register definition.
        !           217:  *
        !           218:  * PIIX_BMISX - Bus master IDE status register
        !           219:  */
        !           220: typedef union {
        !           221:        struct {
        !           222:                u_char
        !           223:                        bmidea  :1,             // Bus master IDE active
        !           224:                        err             :1,             // IDE DMA error
        !           225:                        ideints :1,             // IDE interrupt status
        !           226:                        rsvd1   :2,             // RESERVED
        !           227:                        dma0cap :1,             // drive 0 DMA capable
        !           228:                        dma1cap :1,             // drive 1 DMA capable
        !           229:                        rsvd2   :1;             // RESERVED (hardwired to 0)
        !           230:        } bits;
        !           231:        u_char byte;
        !           232: } piix_bmisx_u;
        !           233: 
        !           234: #define PIIX_STATUS_MASK       0x07
        !           235: #define PIIX_STATUS_OK         0x04
        !           236: #define PIIX_STATUS_ERROR      0x02
        !           237: #define PIIX_STATUS_ACTIVE     0x01
        !           238: 
        !           239: /*
        !           240:  * PIIX Bus Master alignment/boundary requirements.
        !           241:  *
        !           242:  * Intel nomemclature:
        !           243:  * WORD  - 16-bit
        !           244:  * DWord - 32-bit
        !           245:  *
        !           246:  * NOTE:
        !           247:  * Boundary limit implies that the entire region is physically
        !           248:  * contiguous.
        !           249:  *
        !           250:  * There is an error in the manual regarding DT alignment and boundary
        !           251:  * restrictions. The "Intel 82371AB (PIIX4) Specification Update" has a
        !           252:  * clarification to this issue.
        !           253:  */
        !           254: #define PIIX_DT_ALIGN  4                       // descriptor table must be DWord aligned.
        !           255: #define PIIX_DT_BOUND  (4 * 1024)      // cannot cross 4K boundary. (or 64K ?)
        !           256: 
        !           257: #define PIIX_BUF_ALIGN 4                       // memory buffer must be DWord aligned.
        !           258: #define PIIX_BUF_BOUND (64 * 1024)     // cannot cross 64K boundary.
        !           259: #define PIIX_BUF_LIMIT (64 * 1024) // limited to 64K in size
        !           260: 
        !           261: /*
        !           262:  * PIIX Bus Master Physical Region Descriptor (PRD) format.
        !           263:  *
        !           264:  */
        !           265: typedef struct {
        !           266:        u_int   base;                           // base address
        !           267:        u_int   count   :16,            // byte count
        !           268:                        rsvd    :15,
        !           269:                        eot             :1;                     // final PRD indication bit
        !           270: } piix_prd_t;

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