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1.1 root 1: /*
2: * UAE - The Un*x Amiga Emulator - CPU core
3: *
4: * MC68000 emulation
5: *
6: * (c) 1995 Bernd Schmidt
7: *
8: * Adaptation to Hatari by Thomas Huth
9: *
10: * This file is distributed under the GNU Public License, version 2 or at
11: * your option any later version. Read the file gpl.txt for details.
12: */
13: static char rcsid[] = "Hatari $Id: newcpu.c,v 1.25 2003/07/04 12:40:13 thothy Exp $";
14:
15: #include <SDL/SDL.h>
16: #include "sysdeps.h"
17: #include "hatari-glue.h"
18: #include "maccess.h"
19: #include "memory.h"
20: #include "newcpu.h"
21: #include "events.h"
22: #include "../hardware/disasm.h"
23: #include "../hardware/main.h"
24: #include "../hardware/m68000.h"
25: #include "../hardware/hostcall.h"
26: #include "../hardware/video.h"
27: #include "../hardware/screen.h"
28:
29: //#define DEBUG_PROFILE
30:
31: #ifdef DEBUG_PROFILE
32: #include "../hardware/loadfe2.h"
33: static int profile_runs[0x50000];
34: static int profile_total;
35: #endif /* DEBUG_PROFILE */
36:
37: struct flag_struct regflags;
38:
39: int lastInstructionCycles; /* how many cycles last instruction took to execute */
40:
41: /* Opcode of faulting instruction */
42: uae_u16 last_op_for_exception_3;
43: /* PC at fault time */
44: uaecptr last_addr_for_exception_3;
45: /* Address that generated the exception */
46: uaecptr last_fault_for_exception_3;
47:
48: int areg_byteinc[] = { 1,1,1,1,1,1,1,2 };
49: int imm8_table[] = { 8,1,2,3,4,5,6,7 };
50:
51: int movem_index1[256];
52: int movem_index2[256];
53: int movem_next[256];
54:
55: int fpp_movem_index1[256];
56: int fpp_movem_index2[256];
57: int fpp_movem_next[256];
58:
59: cpuop_func *cpufunctbl[65536];
60:
61:
62: #define COUNT_INSTRS 0
63:
64: #if COUNT_INSTRS
65: static unsigned long int instrcount[65536];
66: static uae_u16 opcodenums[65536];
67:
68: static int compfn (const void *el1, const void *el2)
69: {
70: return instrcount[*(const uae_u16 *)el1] < instrcount[*(const uae_u16 *)el2];
71: }
72:
73: static char *icountfilename (void)
74: {
75: char *name = getenv ("INSNCOUNT");
76: if (name)
77: return name;
78: return COUNT_INSTRS == 2 ? "frequent.68k" : "insncount";
79: }
80:
81: void dump_counts (void)
82: {
83: FILE *f = fopen (icountfilename (), "w");
84: unsigned long int total;
85: int i;
86:
87: write_log ("Writing instruction count file...\n");
88: for (i = 0; i < 65536; i++) {
89: opcodenums[i] = i;
90: total += instrcount[i];
91: }
92: qsort (opcodenums, 65536, sizeof(uae_u16), compfn);
93:
94: fprintf (f, "Total: %lu\n", total);
95: for (i=0; i < 65536; i++) {
96: unsigned long int cnt = instrcount[opcodenums[i]];
97: struct instr *dp;
98: struct mnemolookup *lookup;
99: if (!cnt)
100: break;
101: dp = table68k + opcodenums[i];
102: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
103: ;
104: fprintf (f, "%04x: %lu %s\n", opcodenums[i], cnt, lookup->name);
105: }
106: fclose (f);
107: }
108: #else
109: void dump_counts (void)
110: {
111: }
112: #endif
113:
114: int broken_in;
115:
116: static unsigned long op_illg_1 (uae_u32 opcode) REGPARAM;
117:
118: static unsigned long REGPARAM2 op_illg_1 (uae_u32 opcode)
119: {
120: op_illg (opcode);
121: return 4;
122: }
123:
124:
125: void build_cpufunctbl(void)
126: {
127: int i;
128: unsigned long opcode;
129: struct cputbl *tbl = (cpu_level == 4 ? op_smalltbl_0_ff
130: : cpu_level == 3 ? op_smalltbl_1_ff
131: : cpu_level == 2 ? op_smalltbl_2_ff
132: : cpu_level == 1 ? op_smalltbl_3_ff
133: : ! cpu_compatible ? op_smalltbl_4_ff
134: : op_smalltbl_5_ff);
135:
136: write_log ("Building CPU function table (%d %d %d).\n",
137: cpu_level, cpu_compatible, address_space_24);
138:
139: for (opcode = 0; opcode < 65536; opcode++)
140: cpufunctbl[opcode] = op_illg_1;
141: for (i = 0; tbl[i].handler != NULL; i++) {
142: if (! tbl[i].specific)
143: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
144: }
145: for (opcode = 0; opcode < 65536; opcode++) {
146: cpuop_func *f;
147:
148: if (table68k[opcode].mnemo == i_ILLG || table68k[opcode].clev > cpu_level)
149: continue;
150:
151: if (table68k[opcode].handler != -1) {
152: f = cpufunctbl[table68k[opcode].handler];
153: if (f == op_illg_1)
154: abort();
155: cpufunctbl[opcode] = f;
156: }
157: }
158: for (i = 0; tbl[i].handler != NULL; i++) {
159: if (tbl[i].specific)
160: cpufunctbl[tbl[i].opcode] = tbl[i].handler;
161: }
162:
163: /* Hatari's illegal opcodes: */
164: cpufunctbl[HOSTCALL_OPCODE] = HostCall_OpCode;
165: cpufunctbl[HCALL_OPCODE] = HCall_OpCode;
166: }
167:
168:
169:
170: void init_m68k (void)
171: {
172: int i;
173:
174: for (i = 0 ; i < 256 ; i++) {
175: int j;
176: for (j = 0 ; j < 8 ; j++) {
177: if (i & (1 << j)) break;
178: }
179: movem_index1[i] = j;
180: movem_index2[i] = 7-j;
181: movem_next[i] = i & (~(1 << j));
182: }
183: for (i = 0 ; i < 256 ; i++) {
184: int j;
185: for (j = 7 ; j >= 0 ; j--) {
186: if (i & (1 << j)) break;
187: }
188: fpp_movem_index1[i] = 7-j;
189: fpp_movem_index2[i] = j;
190: fpp_movem_next[i] = i & (~(1 << j));
191: }
192: #if COUNT_INSTRS
193: {
194: FILE *f = fopen (icountfilename (), "r");
195: memset (instrcount, 0, sizeof instrcount);
196: if (f) {
197: uae_u32 opcode, count, total;
198: char name[20];
199: write_log ("Reading instruction count file...\n");
200: fscanf (f, "Total: %lu\n", &total);
201: while (fscanf (f, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
202: instrcount[opcode] = count;
203: }
204: fclose(f);
205: }
206: }
207: #endif
208: write_log ("Building CPU table for configuration: 68");
209: if (address_space_24 && cpu_level > 1)
210: write_log ("EC");
211: switch (cpu_level) {
212: case 1:
213: write_log ("010");
214: break;
215: case 2:
216: write_log ("020");
217: break;
218: case 3:
219: write_log ("020/881");
220: break;
221: case 4:
222: /* Who is going to miss the MMU anyway...? :-) */
223: write_log ("040");
224: break;
225: default:
226: write_log ("000");
227: break;
228: }
229: if (cpu_compatible)
230: write_log (" (compatible mode)");
231: write_log ("\n");
232:
233: read_table68k ();
234: do_merges ();
235:
236: write_log ("%d CPU functions\n", nr_cpuop_funcs);
237:
238: build_cpufunctbl ();
239: }
240:
241:
242: struct regstruct regs, lastint_regs;
243: static struct regstruct regs_backup[16];
244: static int backup_pointer = 0;
245: static long int m68kpc_offset;
246: int lastint_no;
247:
248: #define get_ibyte_1(o) get_byte(regs.pc + (regs.pc_p - regs.pc_oldp) + (o) + 1)
249: #define get_iword_1(o) get_word(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
250: #define get_ilong_1(o) get_long(regs.pc + (regs.pc_p - regs.pc_oldp) + (o))
251:
252: uae_s32 ShowEA (FILE *f, int reg, amodes mode, wordsizes size, char *buf)
253: {
254: uae_u16 dp;
255: uae_s8 disp8;
256: uae_s16 disp16;
257: int r;
258: uae_u32 dispreg;
259: uaecptr addr;
260: uae_s32 offset = 0;
261: char buffer[80];
262:
263: switch (mode){
264: case Dreg:
265: sprintf (buffer,"D%d", reg);
266: break;
267: case Areg:
268: sprintf (buffer,"A%d", reg);
269: break;
270: case Aind:
271: sprintf (buffer,"(A%d)", reg);
272: break;
273: case Aipi:
274: sprintf (buffer,"(A%d)+", reg);
275: break;
276: case Apdi:
277: sprintf (buffer,"-(A%d)", reg);
278: break;
279: case Ad16:
280: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
281: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
282: sprintf (buffer,"(A%d,$%04x) == $%08lx", reg, disp16 & 0xffff,
283: (unsigned long)addr);
284: break;
285: case Ad8r:
286: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
287: disp8 = dp & 0xFF;
288: r = (dp & 0x7000) >> 12;
289: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
290: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
291: dispreg <<= (dp >> 9) & 3;
292:
293: if (dp & 0x100) {
294: uae_s32 outer = 0, disp = 0;
295: uae_s32 base = m68k_areg(regs,reg);
296: char name[10];
297: sprintf (name,"A%d, ",reg);
298: if (dp & 0x80) { base = 0; name[0] = 0; }
299: if (dp & 0x40) dispreg = 0;
300: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
301: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
302: base += disp;
303:
304: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
305: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
306:
307: if (!(dp & 4)) base += dispreg;
308: if (dp & 3) base = get_long (base);
309: if (dp & 4) base += dispreg;
310:
311: addr = base + outer;
312: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
313: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
314: 1 << ((dp >> 9) & 3),
315: (long)disp, (long)outer, (unsigned long)addr);
316: } else {
317: addr = m68k_areg(regs,reg) + (uae_s32)((uae_s8)disp8) + dispreg;
318: sprintf (buffer,"(A%d, %c%d.%c*%d, $%02x) == $%08lx", reg,
319: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
320: 1 << ((dp >> 9) & 3), disp8,
321: (unsigned long)addr);
322: }
323: break;
324: case PC16:
325: addr = m68k_getpc () + m68kpc_offset;
326: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
327: addr += (uae_s16)disp16;
328: sprintf (buffer,"(PC,$%04x) == $%08lx", disp16 & 0xffff,(unsigned long)addr);
329: break;
330: case PC8r:
331: addr = m68k_getpc () + m68kpc_offset;
332: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
333: disp8 = dp & 0xFF;
334: r = (dp & 0x7000) >> 12;
335: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
336: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
337: dispreg <<= (dp >> 9) & 3;
338:
339: if (dp & 0x100) {
340: uae_s32 outer = 0,disp = 0;
341: uae_s32 base = addr;
342: char name[10];
343: sprintf (name,"PC, ");
344: if (dp & 0x80) { base = 0; name[0] = 0; }
345: if (dp & 0x40) dispreg = 0;
346: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
347: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
348: base += disp;
349:
350: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
351: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
352:
353: if (!(dp & 4)) base += dispreg;
354: if (dp & 3) base = get_long (base);
355: if (dp & 4) base += dispreg;
356:
357: addr = base + outer;
358: sprintf (buffer,"(%s%c%d.%c*%d+%ld)+%ld == $%08lx", name,
359: dp & 0x8000 ? 'A' : 'D', (int)r, dp & 0x800 ? 'L' : 'W',
360: 1 << ((dp >> 9) & 3),
361: (long)disp, (long)outer, (unsigned long)addr);
362: } else {
363: addr += (uae_s32)((uae_s8)disp8) + dispreg;
364: sprintf (buffer,"(PC, %c%d.%c*%d, $%02x) == $%08lx", dp & 0x8000 ? 'A' : 'D',
365: (int)r, dp & 0x800 ? 'L' : 'W', 1 << ((dp >> 9) & 3),
366: disp8, (unsigned long)addr);
367: }
368: break;
369: case absw:
370: sprintf (buffer,"$%08lx", (unsigned long)(uae_s32)(uae_s16)get_iword_1 (m68kpc_offset));
371: m68kpc_offset += 2;
372: break;
373: case absl:
374: sprintf (buffer,"$%08lx", (unsigned long)get_ilong_1 (m68kpc_offset));
375: m68kpc_offset += 4;
376: break;
377: case imm:
378: switch (size){
379: case sz_byte:
380: sprintf (buffer,"#$%02x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xff));
381: m68kpc_offset += 2;
382: break;
383: case sz_word:
384: sprintf (buffer,"#$%04x", (unsigned int)(get_iword_1 (m68kpc_offset) & 0xffff));
385: m68kpc_offset += 2;
386: break;
387: case sz_long:
388: sprintf (buffer,"#$%08lx", (unsigned long)(get_ilong_1 (m68kpc_offset)));
389: m68kpc_offset += 4;
390: break;
391: default:
392: break;
393: }
394: break;
395: case imm0:
396: offset = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
397: m68kpc_offset += 2;
398: sprintf (buffer,"#$%02x", (unsigned int)(offset & 0xff));
399: break;
400: case imm1:
401: offset = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
402: m68kpc_offset += 2;
403: sprintf (buffer,"#$%04x", (unsigned int)(offset & 0xffff));
404: break;
405: case imm2:
406: offset = (uae_s32)get_ilong_1 (m68kpc_offset);
407: m68kpc_offset += 4;
408: sprintf (buffer,"#$%08lx", (unsigned long)offset);
409: break;
410: case immi:
411: offset = (uae_s32)(uae_s8)(reg & 0xff);
412: sprintf (buffer,"#$%08lx", (unsigned long)offset);
413: break;
414: default:
415: break;
416: }
417: if (buf == 0)
418: fprintf (f, "%s", buffer);
419: else
420: strcat (buf, buffer);
421: return offset;
422: }
423:
424: /* The plan is that this will take over the job of exception 3 handling -
425: * the CPU emulation functions will just do a longjmp to m68k_go whenever
426: * they hit an odd address. */
427: static int verify_ea (int reg, amodes mode, wordsizes size, uae_u32 *val)
428: {
429: uae_u16 dp;
430: uae_s8 disp8;
431: uae_s16 disp16;
432: int r;
433: uae_u32 dispreg;
434: uaecptr addr;
435: /*uae_s32 offset = 0;*/
436:
437: switch (mode){
438: case Dreg:
439: *val = m68k_dreg (regs, reg);
440: return 1;
441: case Areg:
442: *val = m68k_areg (regs, reg);
443: return 1;
444:
445: case Aind:
446: case Aipi:
447: addr = m68k_areg (regs, reg);
448: break;
449: case Apdi:
450: addr = m68k_areg (regs, reg);
451: break;
452: case Ad16:
453: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
454: addr = m68k_areg(regs,reg) + (uae_s16)disp16;
455: break;
456: case Ad8r:
457: addr = m68k_areg (regs, reg);
458: d8r_common:
459: dp = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
460: disp8 = dp & 0xFF;
461: r = (dp & 0x7000) >> 12;
462: dispreg = dp & 0x8000 ? m68k_areg(regs,r) : m68k_dreg(regs,r);
463: if (!(dp & 0x800)) dispreg = (uae_s32)(uae_s16)(dispreg);
464: dispreg <<= (dp >> 9) & 3;
465:
466: if (dp & 0x100) {
467: uae_s32 outer = 0, disp = 0;
468: uae_s32 base = addr;
469: if (dp & 0x80) base = 0;
470: if (dp & 0x40) dispreg = 0;
471: if ((dp & 0x30) == 0x20) { disp = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
472: if ((dp & 0x30) == 0x30) { disp = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
473: base += disp;
474:
475: if ((dp & 0x3) == 0x2) { outer = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset); m68kpc_offset += 2; }
476: if ((dp & 0x3) == 0x3) { outer = get_ilong_1 (m68kpc_offset); m68kpc_offset += 4; }
477:
478: if (!(dp & 4)) base += dispreg;
479: if (dp & 3) base = get_long (base);
480: if (dp & 4) base += dispreg;
481:
482: addr = base + outer;
483: } else {
484: addr += (uae_s32)((uae_s8)disp8) + dispreg;
485: }
486: break;
487: case PC16:
488: addr = m68k_getpc () + m68kpc_offset;
489: disp16 = get_iword_1 (m68kpc_offset); m68kpc_offset += 2;
490: addr += (uae_s16)disp16;
491: break;
492: case PC8r:
493: addr = m68k_getpc () + m68kpc_offset;
494: goto d8r_common;
495: case absw:
496: addr = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
497: m68kpc_offset += 2;
498: break;
499: case absl:
500: addr = get_ilong_1 (m68kpc_offset);
501: m68kpc_offset += 4;
502: break;
503: case imm:
504: switch (size){
505: case sz_byte:
506: *val = get_iword_1 (m68kpc_offset) & 0xff;
507: m68kpc_offset += 2;
508: break;
509: case sz_word:
510: *val = get_iword_1 (m68kpc_offset) & 0xffff;
511: m68kpc_offset += 2;
512: break;
513: case sz_long:
514: *val = get_ilong_1 (m68kpc_offset);
515: m68kpc_offset += 4;
516: break;
517: default:
518: break;
519: }
520: return 1;
521: case imm0:
522: *val = (uae_s32)(uae_s8)get_iword_1 (m68kpc_offset);
523: m68kpc_offset += 2;
524: return 1;
525: case imm1:
526: *val = (uae_s32)(uae_s16)get_iword_1 (m68kpc_offset);
527: m68kpc_offset += 2;
528: return 1;
529: case imm2:
530: *val = get_ilong_1 (m68kpc_offset);
531: m68kpc_offset += 4;
532: return 1;
533: case immi:
534: *val = (uae_s32)(uae_s8)(reg & 0xff);
535: return 1;
536: default:
537: addr = 0;
538: break;
539: }
540: if ((addr & 1) == 0)
541: return 1;
542:
543: last_addr_for_exception_3 = m68k_getpc () + m68kpc_offset;
544: last_fault_for_exception_3 = addr;
545: return 0;
546: }
547:
548: uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp)
549: {
550: int reg = (dp >> 12) & 15;
551: uae_s32 regd = regs.regs[reg];
552: if ((dp & 0x800) == 0)
553: regd = (uae_s32)(uae_s16)regd;
554: regd <<= (dp >> 9) & 3;
555: if (dp & 0x100) {
556: uae_s32 outer = 0;
557: if (dp & 0x80) base = 0;
558: if (dp & 0x40) regd = 0;
559:
560: if ((dp & 0x30) == 0x20) base += (uae_s32)(uae_s16)next_iword();
561: if ((dp & 0x30) == 0x30) base += next_ilong();
562:
563: if ((dp & 0x3) == 0x2) outer = (uae_s32)(uae_s16)next_iword();
564: if ((dp & 0x3) == 0x3) outer = next_ilong();
565:
566: if ((dp & 0x4) == 0) base += regd;
567: if (dp & 0x3) base = get_long (base);
568: if (dp & 0x4) base += regd;
569:
570: return base + outer;
571: } else {
572: return base + (uae_s32)((uae_s8)dp) + regd;
573: }
574: }
575:
576: uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
577: {
578: int reg = (dp >> 12) & 15;
579: uae_s32 regd = regs.regs[reg];
580: #if 1
581: if ((dp & 0x800) == 0)
582: regd = (uae_s32)(uae_s16)regd;
583: return base + (uae_s8)dp + regd;
584: #else
585: /* Branch-free code... benchmark this again now that
586: * things are no longer inline. */
587: uae_s32 regd16;
588: uae_u32 mask;
589: mask = ((dp & 0x800) >> 11) - 1;
590: regd16 = (uae_s32)(uae_s16)regd;
591: regd16 &= mask;
592: mask = ~mask;
593: base += (uae_s8)dp;
594: regd &= mask;
595: regd |= regd16;
596: return base + regd;
597: #endif
598: }
599:
600: void MakeSR (void)
601: {
602: #if 0
603: assert((regs.t1 & 1) == regs.t1);
604: assert((regs.t0 & 1) == regs.t0);
605: assert((regs.s & 1) == regs.s);
606: assert((regs.m & 1) == regs.m);
607: assert((XFLG & 1) == XFLG);
608: assert((NFLG & 1) == NFLG);
609: assert((ZFLG & 1) == ZFLG);
610: assert((VFLG & 1) == VFLG);
611: assert((CFLG & 1) == CFLG);
612: #endif
613: regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
614: | (regs.s << 13) | (regs.m << 12) | (regs.intmask << 8)
615: | (GET_XFLG << 4) | (GET_NFLG << 3) | (GET_ZFLG << 2) | (GET_VFLG << 1)
616: | GET_CFLG);
617: }
618:
619: void MakeFromSR (void)
620: {
621: int oldm = regs.m;
622: int olds = regs.s;
623:
624: regs.t1 = (regs.sr >> 15) & 1;
625: regs.t0 = (regs.sr >> 14) & 1;
626: regs.s = (regs.sr >> 13) & 1;
627: regs.m = (regs.sr >> 12) & 1;
628: regs.intmask = (regs.sr >> 8) & 7;
629: SET_XFLG ((regs.sr >> 4) & 1);
630: SET_NFLG ((regs.sr >> 3) & 1);
631: SET_ZFLG ((regs.sr >> 2) & 1);
632: SET_VFLG ((regs.sr >> 1) & 1);
633: SET_CFLG (regs.sr & 1);
634: if (cpu_level >= 2) {
635: if (olds != regs.s) {
636: if (olds) {
637: if (oldm)
638: regs.msp = m68k_areg(regs, 7);
639: else
640: regs.isp = m68k_areg(regs, 7);
641: m68k_areg(regs, 7) = regs.usp;
642: } else {
643: regs.usp = m68k_areg(regs, 7);
644: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
645: }
646: } else if (olds && oldm != regs.m) {
647: if (oldm) {
648: regs.msp = m68k_areg(regs, 7);
649: m68k_areg(regs, 7) = regs.isp;
650: } else {
651: regs.isp = m68k_areg(regs, 7);
652: m68k_areg(regs, 7) = regs.msp;
653: }
654: }
655: } else {
656: if (olds != regs.s) {
657: if (olds) {
658: regs.isp = m68k_areg(regs, 7);
659: m68k_areg(regs, 7) = regs.usp;
660: } else {
661: regs.usp = m68k_areg(regs, 7);
662: m68k_areg(regs, 7) = regs.isp;
663: }
664: }
665: }
666:
667: set_special (SPCFLAG_INT);
668: if (regs.t1 || regs.t0)
669: set_special (SPCFLAG_TRACE);
670: else
671: /* Keep SPCFLAG_DOTRACE, we still want a trace exception for
672: SR-modifying instructions (including STOP). */
673: unset_special (SPCFLAG_TRACE);
674: }
675:
676:
677: void Exception(int nr, uaecptr oldpc)
678: {
679: uae_u32 currpc = m68k_getpc ();
680:
681: if( nr>=2 && nr<10 ) {
682: M68000_Crash (nr);
683: }
684:
685: MakeSR();
686:
687: if (!regs.s) {
688: regs.usp = m68k_areg(regs, 7);
689: if (cpu_level >= 2)
690: m68k_areg(regs, 7) = regs.m ? regs.msp : regs.isp;
691: else
692: m68k_areg(regs, 7) = regs.isp;
693: regs.s = 1;
694: }
695: if (cpu_level > 0) {
696: if (nr == 2 || nr == 3) {
697: int i;
698: /* @@@ this is probably wrong (?) */
699: for (i = 0 ; i < 12 ; i++) {
700: m68k_areg(regs, 7) -= 2;
701: put_word (m68k_areg(regs, 7), 0);
702: }
703: m68k_areg(regs, 7) -= 2;
704: put_word (m68k_areg(regs, 7), 0xa000 + nr * 4);
705: } else if (nr ==5 || nr == 6 || nr == 7 || nr == 9) {
706: m68k_areg(regs, 7) -= 4;
707: put_long (m68k_areg(regs, 7), oldpc);
708: m68k_areg(regs, 7) -= 2;
709: put_word (m68k_areg(regs, 7), 0x2000 + nr * 4);
710: } else if (regs.m && nr >= 24 && nr < 32) {
711: m68k_areg(regs, 7) -= 2;
712: put_word (m68k_areg(regs, 7), nr * 4);
713: m68k_areg(regs, 7) -= 4;
714: put_long (m68k_areg(regs, 7), currpc);
715: m68k_areg(regs, 7) -= 2;
716: put_word (m68k_areg(regs, 7), regs.sr);
717: regs.sr |= (1 << 13);
718: regs.msp = m68k_areg(regs, 7);
719: m68k_areg(regs, 7) = regs.isp;
720: m68k_areg(regs, 7) -= 2;
721: put_word (m68k_areg(regs, 7), 0x1000 + nr * 4);
722: } else {
723: m68k_areg(regs, 7) -= 2;
724: put_word (m68k_areg(regs, 7), nr * 4);
725: }
726: }
727:
728: /* Push PC on stack: */
729: m68k_areg(regs, 7) -= 4;
730: put_long (m68k_areg(regs, 7), currpc);
731: /* Push SR on stack: */
732: m68k_areg(regs, 7) -= 2;
733: put_word (m68k_areg(regs, 7), regs.sr);
734:
735: /* 68000 bus/address errors: */
736: /* Well these 8 more bytes are not here just for debuging.
737: It seems adebug expects them to be on the stack when it receives
738: a bus error... */
739: if (cpu_level==0 && (nr==2 || nr==3)) {
740: m68k_areg(regs, 7) -= 8;
741: if (nr == 3) { /* Address error */
742: put_word (m68k_areg(regs, 7), 0); /* FIXME: Add real function code value */
743: put_long (m68k_areg(regs, 7)+2, last_fault_for_exception_3);
744: put_word (m68k_areg(regs, 7)+6, last_op_for_exception_3);
745: put_long (m68k_areg(regs, 7)+10, last_addr_for_exception_3);
746: fprintf(stderr,"Address Error at address $%x, PC=$%x\n",last_fault_for_exception_3,currpc);
747: }
748: else { /* Bus error */
749: put_word (m68k_areg(regs, 7), 0); /* FIXME: Add real function code value */
750: put_long (m68k_areg(regs, 7)+2, BusAddressLocation);
751: put_word (m68k_areg(regs, 7)+6, BusErrorOpcode);
752: fprintf(stderr,"Bus Error at address $%x, PC=$%lx\n",BusAddressLocation,(long)currpc);
753: }
754: }
755:
756: m68k_setpc (get_long (regs.vbr + 4*nr));
757: fill_prefetch_0 ();
758: regs.t1 = regs.t0 = regs.m = 0;
759: unset_special (SPCFLAG_TRACE | SPCFLAG_DOTRACE);
760:
761: /* Handle exception cycles: */
762: if(nr >= 24 && nr <= 31)
763: {
764: ADD_CYCLES(44+4, 5, 3); /* Interrupt */
765: }
766: else if(nr >= 32 && nr <= 47)
767: {
768: ADD_CYCLES(34, 5, 3); /* Trap */
769: }
770: else switch(nr)
771: {
772: case 2: ADD_CYCLES(50, 4, 7); break; /* Bus error */
773: case 3: ADD_CYCLES(50, 4, 7); break; /* Address error */
774: case 4: ADD_CYCLES(34, 4, 3); break; /* Illegal instruction */
775: case 5: ADD_CYCLES(38, 4, 3); break; /* Div by zero */
776: case 6: ADD_CYCLES(40, 4, 3); break; /* CHK */
777: case 7: ADD_CYCLES(34, 5, 3); break; /* TRAPV */
778: case 8: ADD_CYCLES(34, 4, 3); break; /* Privilege violation */
779: case 9: ADD_CYCLES(34, 4, 3); break; /* Trace */
780: case 10: ADD_CYCLES(34, 4, 3); break; /* Line-A - probably wrong */
781: case 11: ADD_CYCLES(34, 4, 3); break; /* Line-F - probably wrong */
782: default:
783: #if 0 /* Hatari currently seems to run more instable when adding MFP cycles */
784: if(nr < 64)
785: ADD_CYCLES(0, 0, 0); /* Coprocessor and unassigned exceptions (???) */
786: else
787: ADD_CYCLES(44+4, 5, 3); /* Must be a MFP interrupt */
788: #endif
789: break;
790: }
791: }
792:
793:
794: static void Interrupt(int nr)
795: {
796: assert(nr < 8 && nr >= 0);
797: lastint_regs = regs;
798: lastint_no = nr;
799: Exception(nr+24, 0);
800:
801: regs.intmask = nr;
802: set_special (SPCFLAG_INT);
803: }
804:
805:
806: static uae_u32 caar, cacr, itt0, itt1, dtt0, dtt1, tc, mmusr, urp, srp;
807:
808:
809: int m68k_move2c (int regno, uae_u32 *regp)
810: {
811: if ((cpu_level == 1 && (regno & 0x7FF) > 1)
812: || (cpu_level < 4 && (regno & 0x7FF) > 2)
813: || (cpu_level == 4 && regno == 0x802))
814: {
815: op_illg (0x4E7B);
816: return 0;
817: } else {
818: switch (regno) {
819: case 0: regs.sfc = *regp & 7; break;
820: case 1: regs.dfc = *regp & 7; break;
821: case 2: cacr = *regp & (cpu_level < 4 ? 0x3 : 0x80008000); break;
822: case 3: tc = *regp & 0xc000; break;
823: /* Mask out fields that should be zero. */
824: case 4: itt0 = *regp & 0xffffe364; break;
825: case 5: itt1 = *regp & 0xffffe364; break;
826: case 6: dtt0 = *regp & 0xffffe364; break;
827: case 7: dtt1 = *regp & 0xffffe364; break;
828:
829: case 0x800: regs.usp = *regp; break;
830: case 0x801: regs.vbr = *regp; break;
831: case 0x802: caar = *regp & 0xfc; break;
832: case 0x803: regs.msp = *regp; if (regs.m == 1) m68k_areg(regs, 7) = regs.msp; break;
833: case 0x804: regs.isp = *regp; if (regs.m == 0) m68k_areg(regs, 7) = regs.isp; break;
834: case 0x805: mmusr = *regp; break;
835: case 0x806: urp = *regp; break;
836: case 0x807: srp = *regp; break;
837: default:
838: op_illg (0x4E7B);
839: return 0;
840: }
841: }
842: return 1;
843: }
844:
845: int m68k_movec2 (int regno, uae_u32 *regp)
846: {
847: if ((cpu_level == 1 && (regno & 0x7FF) > 1)
848: || (cpu_level < 4 && (regno & 0x7FF) > 2)
849: || (cpu_level == 4 && regno == 0x802))
850: {
851: op_illg (0x4E7A);
852: return 0;
853: } else {
854: switch (regno) {
855: case 0: *regp = regs.sfc; break;
856: case 1: *regp = regs.dfc; break;
857: case 2: *regp = cacr; break;
858: case 3: *regp = tc; break;
859: case 4: *regp = itt0; break;
860: case 5: *regp = itt1; break;
861: case 6: *regp = dtt0; break;
862: case 7: *regp = dtt1; break;
863: case 0x800: *regp = regs.usp; break;
864: case 0x801: *regp = regs.vbr; break;
865: case 0x802: *regp = caar; break;
866: case 0x803: *regp = regs.m == 1 ? m68k_areg(regs, 7) : regs.msp; break;
867: case 0x804: *regp = regs.m == 0 ? m68k_areg(regs, 7) : regs.isp; break;
868: case 0x805: *regp = mmusr; break;
869: case 0x806: *regp = urp; break;
870: case 0x807: *regp = srp; break;
871: default:
872: op_illg (0x4E7A);
873: return 0;
874: }
875: }
876: return 1;
877: }
878:
879: STATIC_INLINE int
880: div_unsigned(uae_u32 src_hi, uae_u32 src_lo, uae_u32 div, uae_u32 *quot, uae_u32 *rem)
881: {
882: uae_u32 q = 0, cbit = 0;
883: int i;
884:
885: if (div <= src_hi) {
886: return 1;
887: }
888: for (i = 0 ; i < 32 ; i++) {
889: cbit = src_hi & 0x80000000ul;
890: src_hi <<= 1;
891: if (src_lo & 0x80000000ul) src_hi++;
892: src_lo <<= 1;
893: q = q << 1;
894: if (cbit || div <= src_hi) {
895: q |= 1;
896: src_hi -= div;
897: }
898: }
899: *quot = q;
900: *rem = src_hi;
901: return 0;
902: }
903:
904: void m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra, uaecptr oldpc)
905: {
906: #if defined(uae_s64)
907: if (src == 0) {
908: Exception (5, oldpc);
909: return;
910: }
911: if (extra & 0x800) {
912: /* signed variant */
913: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
914: uae_s64 quot, rem;
915:
916: if (extra & 0x400) {
917: a &= 0xffffffffu;
918: a |= (uae_s64)m68k_dreg(regs, extra & 7) << 32;
919: }
920: rem = a % (uae_s64)(uae_s32)src;
921: quot = a / (uae_s64)(uae_s32)src;
922: if ((quot & UVAL64(0xffffffff80000000)) != 0
923: && (quot & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
924: {
925: SET_VFLG (1);
926: SET_NFLG (1);
927: SET_CFLG (0);
928: } else {
929: if (((uae_s32)rem < 0) != ((uae_s64)a < 0)) rem = -rem;
930: SET_VFLG (0);
931: SET_CFLG (0);
932: SET_ZFLG (((uae_s32)quot) == 0);
933: SET_NFLG (((uae_s32)quot) < 0);
934: m68k_dreg(regs, extra & 7) = rem;
935: m68k_dreg(regs, (extra >> 12) & 7) = quot;
936: }
937: } else {
938: /* unsigned */
939: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
940: uae_u64 quot, rem;
941:
942: if (extra & 0x400) {
943: a &= 0xffffffffu;
944: a |= (uae_u64)m68k_dreg(regs, extra & 7) << 32;
945: }
946: rem = a % (uae_u64)src;
947: quot = a / (uae_u64)src;
948: if (quot > 0xffffffffu) {
949: SET_VFLG (1);
950: SET_NFLG (1);
951: SET_CFLG (0);
952: } else {
953: SET_VFLG (0);
954: SET_CFLG (0);
955: SET_ZFLG (((uae_s32)quot) == 0);
956: SET_NFLG (((uae_s32)quot) < 0);
957: m68k_dreg(regs, extra & 7) = rem;
958: m68k_dreg(regs, (extra >> 12) & 7) = quot;
959: }
960: }
961: #else
962: if (src == 0) {
963: Exception (5, oldpc);
964: return;
965: }
966: if (extra & 0x800) {
967: /* signed variant */
968: uae_s32 lo = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
969: uae_s32 hi = lo < 0 ? -1 : 0;
970: uae_s32 save_high;
971: uae_u32 quot, rem;
972: uae_u32 sign;
973:
974: if (extra & 0x400) {
975: hi = (uae_s32)m68k_dreg(regs, extra & 7);
976: }
977: save_high = hi;
978: sign = (hi ^ src);
979: if (hi < 0) {
980: hi = ~hi;
981: lo = -lo;
982: if (lo == 0) hi++;
983: }
984: if ((uae_s32)src < 0) src = -src;
985: if (div_unsigned(hi, lo, src, ", &rem) ||
986: (sign & 0x80000000) ? quot > 0x80000000 : quot > 0x7fffffff) {
987: SET_VFLG (1);
988: SET_NFLG (1);
989: SET_CFLG (0);
990: } else {
991: if (sign & 0x80000000) quot = -quot;
992: if (((uae_s32)rem < 0) != (save_high < 0)) rem = -rem;
993: SET_VFLG (0);
994: SET_CFLG (0);
995: SET_ZFLG (((uae_s32)quot) == 0);
996: SET_NFLG (((uae_s32)quot) < 0);
997: m68k_dreg(regs, extra & 7) = rem;
998: m68k_dreg(regs, (extra >> 12) & 7) = quot;
999: }
1000: } else {
1001: /* unsigned */
1002: uae_u32 lo = (uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1003: uae_u32 hi = 0;
1004: uae_u32 quot, rem;
1005:
1006: if (extra & 0x400) {
1007: hi = (uae_u32)m68k_dreg(regs, extra & 7);
1008: }
1009: if (div_unsigned(hi, lo, src, ", &rem)) {
1010: SET_VFLG (1);
1011: SET_NFLG (1);
1012: SET_CFLG (0);
1013: } else {
1014: SET_VFLG (0);
1015: SET_CFLG (0);
1016: SET_ZFLG (((uae_s32)quot) == 0);
1017: SET_NFLG (((uae_s32)quot) < 0);
1018: m68k_dreg(regs, extra & 7) = rem;
1019: m68k_dreg(regs, (extra >> 12) & 7) = quot;
1020: }
1021: }
1022: #endif
1023: }
1024:
1025: STATIC_INLINE void
1026: mul_unsigned(uae_u32 src1, uae_u32 src2, uae_u32 *dst_hi, uae_u32 *dst_lo)
1027: {
1028: uae_u32 r0 = (src1 & 0xffff) * (src2 & 0xffff);
1029: uae_u32 r1 = ((src1 >> 16) & 0xffff) * (src2 & 0xffff);
1030: uae_u32 r2 = (src1 & 0xffff) * ((src2 >> 16) & 0xffff);
1031: uae_u32 r3 = ((src1 >> 16) & 0xffff) * ((src2 >> 16) & 0xffff);
1032: uae_u32 lo;
1033:
1034: lo = r0 + ((r1 << 16) & 0xffff0000ul);
1035: if (lo < r0) r3++;
1036: r0 = lo;
1037: lo = r0 + ((r2 << 16) & 0xffff0000ul);
1038: if (lo < r0) r3++;
1039: r3 += ((r1 >> 16) & 0xffff) + ((r2 >> 16) & 0xffff);
1040: *dst_lo = lo;
1041: *dst_hi = r3;
1042: }
1043:
1044: void m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra)
1045: {
1046: #if defined(uae_s64)
1047: if (extra & 0x800) {
1048: /* signed variant */
1049: uae_s64 a = (uae_s64)(uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1050:
1051: a *= (uae_s64)(uae_s32)src;
1052: SET_VFLG (0);
1053: SET_CFLG (0);
1054: SET_ZFLG (a == 0);
1055: SET_NFLG (a < 0);
1056: if (extra & 0x400)
1057: m68k_dreg(regs, extra & 7) = a >> 32;
1058: else if ((a & UVAL64(0xffffffff80000000)) != 0
1059: && (a & UVAL64(0xffffffff80000000)) != UVAL64(0xffffffff80000000))
1060: {
1061: SET_VFLG (1);
1062: }
1063: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1064: } else {
1065: /* unsigned */
1066: uae_u64 a = (uae_u64)(uae_u32)m68k_dreg(regs, (extra >> 12) & 7);
1067:
1068: a *= (uae_u64)src;
1069: SET_VFLG (0);
1070: SET_CFLG (0);
1071: SET_ZFLG (a == 0);
1072: SET_NFLG (((uae_s64)a) < 0);
1073: if (extra & 0x400)
1074: m68k_dreg(regs, extra & 7) = a >> 32;
1075: else if ((a & UVAL64(0xffffffff00000000)) != 0) {
1076: SET_VFLG (1);
1077: }
1078: m68k_dreg(regs, (extra >> 12) & 7) = (uae_u32)a;
1079: }
1080: #else
1081: if (extra & 0x800) {
1082: /* signed variant */
1083: uae_s32 src1,src2;
1084: uae_u32 dst_lo,dst_hi;
1085: uae_u32 sign;
1086:
1087: src1 = (uae_s32)src;
1088: src2 = (uae_s32)m68k_dreg(regs, (extra >> 12) & 7);
1089: sign = (src1 ^ src2);
1090: if (src1 < 0) src1 = -src1;
1091: if (src2 < 0) src2 = -src2;
1092: mul_unsigned((uae_u32)src1,(uae_u32)src2,&dst_hi,&dst_lo);
1093: if (sign & 0x80000000) {
1094: dst_hi = ~dst_hi;
1095: dst_lo = -dst_lo;
1096: if (dst_lo == 0) dst_hi++;
1097: }
1098: SET_VFLG (0);
1099: SET_CFLG (0);
1100: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1101: SET_NFLG (((uae_s32)dst_hi) < 0);
1102: if (extra & 0x400)
1103: m68k_dreg(regs, extra & 7) = dst_hi;
1104: else if ((dst_hi != 0 || (dst_lo & 0x80000000) != 0)
1105: && ((dst_hi & 0xffffffff) != 0xffffffff
1106: || (dst_lo & 0x80000000) != 0x80000000))
1107: {
1108: SET_VFLG (1);
1109: }
1110: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1111: } else {
1112: /* unsigned */
1113: uae_u32 dst_lo,dst_hi;
1114:
1115: mul_unsigned(src,(uae_u32)m68k_dreg(regs, (extra >> 12) & 7),&dst_hi,&dst_lo);
1116:
1117: SET_VFLG (0);
1118: SET_CFLG (0);
1119: SET_ZFLG (dst_hi == 0 && dst_lo == 0);
1120: SET_NFLG (((uae_s32)dst_hi) < 0);
1121: if (extra & 0x400)
1122: m68k_dreg(regs, extra & 7) = dst_hi;
1123: else if (dst_hi != 0) {
1124: SET_VFLG (1);
1125: }
1126: m68k_dreg(regs, (extra >> 12) & 7) = dst_lo;
1127: }
1128: #endif
1129: }
1130:
1131: static char* ccnames[] =
1132: { "T ","F ","HI","LS","CC","CS","NE","EQ",
1133: "VC","VS","PL","MI","GE","LT","GT","LE" };
1134:
1135: void m68k_reset (void)
1136: {
1137: regs.s = 1;
1138: regs.m = 0;
1139: regs.stopped = 0;
1140: regs.t1 = 0;
1141: regs.t0 = 0;
1142: SET_ZFLG (0);
1143: SET_XFLG (0);
1144: SET_CFLG (0);
1145: SET_VFLG (0);
1146: SET_NFLG (0);
1147: regs.spcflags &= SPCFLAG_MODE_CHANGE; /* Clear specialflags except mode-change */
1148: regs.intmask = 7;
1149: regs.vbr = regs.sfc = regs.dfc = 0;
1150: regs.fpcr = regs.fpsr = regs.fpiar = 0;
1151:
1152: m68k_areg(regs, 7) = get_long(0);
1153: m68k_setpc(get_long(4));
1154: refill_prefetch (m68k_getpc(), 0);
1155: }
1156:
1157: unsigned long REGPARAM2 op_illg (uae_u32 opcode)
1158: {
1159: uaecptr pc = m68k_getpc ();
1160:
1161: if (opcode == 0x4E7B && get_long (0x10) == 0 ) {
1162: write_log ("This program requires a 68020 CPU!\n");
1163: broken_in = 1;
1164: set_special (SPCFLAG_BRK);
1165: bQuitProgram = 1;
1166: }
1167:
1168: if ((opcode & 0xF000) == 0xF000) {
1169: Exception(0xB,0);
1170: return 4;
1171: }
1172: if ((opcode & 0xF000) == 0xA000) {
1173: Exception(0xA,0);
1174: return 4;
1175: }
1176:
1177: #if 0
1178: write_log ("Illegal instruction: %04x at %08lx\n", opcode, (long)pc);
1179: #endif
1180: Exception (4,0);
1181: return 4;
1182: }
1183:
1184: void mmu_op(uae_u32 opcode, uae_u16 extra)
1185: {
1186: if ((opcode & 0xFE0) == 0x0500) {
1187: /* PFLUSH */
1188: mmusr = 0;
1189: write_log ("PFLUSH\n");
1190: } else if ((opcode & 0x0FD8) == 0x548) {
1191: /* PTEST */
1192: write_log ("PTEST\n");
1193: } else
1194: op_illg (opcode);
1195: }
1196:
1197:
1198: static uaecptr last_trace_ad = 0;
1199:
1200: static void do_trace (void)
1201: {
1202: if (regs.t0 && cpu_level >= 2) {
1203: uae_u16 opcode;
1204: /* should also include TRAP, CHK, SR modification FPcc */
1205: /* probably never used so why bother */
1206: /* We can afford this to be inefficient... */
1207: m68k_setpc (m68k_getpc ());
1208: fill_prefetch_0 ();
1209: opcode = get_word (regs.pc);
1210: if (opcode == 0x4e72 /* RTE */
1211: || opcode == 0x4e74 /* RTD */
1212: || opcode == 0x4e75 /* RTS */
1213: || opcode == 0x4e77 /* RTR */
1214: || opcode == 0x4e76 /* TRAPV */
1215: || (opcode & 0xffc0) == 0x4e80 /* JSR */
1216: || (opcode & 0xffc0) == 0x4ec0 /* JMP */
1217: || (opcode & 0xff00) == 0x6100 /* BSR */
1218: || ((opcode & 0xf000) == 0x6000 /* Bcc */
1219: && cctrue((opcode >> 8) & 0xf))
1220: || ((opcode & 0xf0f0) == 0x5050 /* DBcc */
1221: && !cctrue((opcode >> 8) & 0xf)
1222: && (uae_s16)m68k_dreg(regs, opcode & 7) != 0))
1223: {
1224: last_trace_ad = m68k_getpc ();
1225: unset_special (SPCFLAG_TRACE);
1226: set_special (SPCFLAG_DOTRACE);
1227: }
1228: } else if (regs.t1) {
1229: last_trace_ad = m68k_getpc ();
1230: unset_special (SPCFLAG_TRACE);
1231: set_special (SPCFLAG_DOTRACE);
1232: }
1233: }
1234:
1235:
1236: static int do_specialties (void)
1237: {
1238: if(regs.spcflags & SPCFLAG_BUSERROR) {
1239: /* We can not execute bus errors directly in the memory handler
1240: * functions since the PC should point to the address of the next
1241: * instruction, so we're executing the bus errors here: */
1242: unset_special(SPCFLAG_BUSERROR);
1243: Exception(2,0);
1244: }
1245:
1246: if (regs.spcflags & SPCFLAG_DOTRACE) {
1247: Exception (9,last_trace_ad);
1248: }
1249: while (regs.spcflags & SPCFLAG_STOP) {
1250: do_cycles (8);
1251: if (regs.intmask>5) {
1252: /* We still have to care about events when IPL==7 ! */
1253: Main_EventHandler();
1254: if(bQuitProgram) unset_special(SPCFLAG_STOP);
1255: }
1256: if (regs.spcflags & (SPCFLAG_INT | SPCFLAG_DOINT)) {
1257: int intr = intlev ();
1258: unset_special (SPCFLAG_INT | SPCFLAG_DOINT);
1259: if (intr != -1 && intr > regs.intmask) {
1260: Interrupt (intr);
1261: regs.stopped = 0;
1262: unset_special (SPCFLAG_STOP);
1263: }
1264: }
1265: }
1266: if (regs.spcflags & SPCFLAG_TRACE)
1267: do_trace ();
1268:
1269: if (regs.spcflags & SPCFLAG_DOINT) {
1270: int intr = intlev ();
1271: unset_special (SPCFLAG_DOINT);
1272: if (intr != -1 && intr > regs.intmask) {
1273: Interrupt (intr);
1274: regs.stopped = 0;
1275: }
1276: }
1277: if (regs.spcflags & SPCFLAG_INT) {
1278: unset_special (SPCFLAG_INT);
1279: set_special (SPCFLAG_DOINT);
1280: }
1281: if (regs.spcflags & (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE)) {
1282: unset_special (SPCFLAG_BRK | SPCFLAG_MODE_CHANGE);
1283: return 1;
1284: }
1285: return 0;
1286: }
1287:
1288:
1289: /* It's really sad to have two almost identical functions for this, but we
1290: do it all for performance... :( */
1291: static void m68k_run_1 (void)
1292: {
1293: #ifdef DEBUG_PREFETCH
1294: uae_u8 saved_bytes[20];
1295: uae_u16 *oldpcp;
1296: #endif
1297: while(!bQuitProgram) {
1298: int cycles;
1299: uae_u32 opcode = get_iword_prefetch (0);
1300: #ifdef DEBUG_PREFETCH
1301: if (get_ilong (0) != do_get_mem_long (®s.prefetch)) {
1302: fprintf (stderr, "Prefetch differs from memory.\n");
1303: debugging = 1;
1304: return;
1305: }
1306: oldpcp = regs.pc_p;
1307: memcpy (saved_bytes, regs.pc_p, 20);
1308: #endif
1309:
1310: /*m68k_dumpstate(stderr, NULL);*/
1311: /*m68k_disasm(stderr, m68k_getpc (), NULL, 1);*/
1312:
1313: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1314: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1315: #if COUNT_INSTRS == 2
1316: if (table68k[opcode].handler != -1)
1317: instrcount[table68k[opcode].handler]++;
1318: #elif COUNT_INSTRS == 1
1319: instrcount[opcode]++;
1320: #endif
1321:
1322: cycles = (*cpufunctbl[opcode])(opcode);
1323:
1324: #ifdef DEBUG_PREFETCH
1325: if (memcmp (saved_bytes, oldpcp, 20) != 0) {
1326: fprintf (stderr, "Self-modifying code detected.\n");
1327: set_special (SPCFLAG_BRK);
1328: debugging = 1;
1329: }
1330: #endif
1331:
1332: do_cycles (cycles);
1333: if (regs.spcflags) {
1334: if (do_specialties ())
1335: return;
1336: }
1337: }
1338: }
1339:
1340:
1341: /* Same thing, but don't use prefetch to get opcode. */
1342: static void m68k_run_2 (void)
1343: {
1344: /* VBL every 20ms (50Hz) */
1345: Uint32 now;
1346: Uint32 last_vbl = 0;
1347: Uint32 last_eventpoll = 0;
1348: int iters_this_frame = 0;
1349: int lag = 0;
1350:
1351: while(!bQuitProgram) {
1352: int cycles;
1353:
1354: #ifdef DEBUG_PROFILE
1355: profile_runs [ m68k_getpc() >> 1 ] += 1;
1356: profile_total++;
1357: #endif /* DEBUG_PROFILE */
1358:
1359: uae_u32 opcode = get_iword (0);
1360:
1361: /*m68k_dumpstate(stderr, NULL);*/
1362: /*m68k_disasm(stderr, m68k_getpc (), NULL, 1);*/
1363:
1364: /* assert (!regs.stopped && !(regs.spcflags & SPCFLAG_STOP)); */
1365: /* regs_backup[backup_pointer = (backup_pointer + 1) % 16] = regs;*/
1366: #if COUNT_INSTRS == 2
1367: if (table68k[opcode].handler != -1)
1368: instrcount[table68k[opcode].handler]++;
1369: #elif COUNT_INSTRS == 1
1370: instrcount[opcode]++;
1371: #endif
1372:
1373: cycles = (*cpufunctbl[opcode])(opcode);
1374: do_cycles (cycles);
1375: iters_this_frame++;
1376:
1377: if (regs.spcflags) {
1378: do_specialties ();
1379: }
1380:
1381: /* check if 20ms has elapsed and if so do a VBL (50fps).
1382: * this test is done every now and again... */
1383: if ((iters_this_frame & 0xffff) == 0) {
1384: now = SDL_GetTicks ();
1385:
1386: /* poll events every ms */
1387: if (now - last_eventpoll) {
1388: last_eventpoll = now;
1389: Main_EventHandler ();
1390: }
1391:
1392: /* some jitter present which fucks audio a little */
1393: if (now - last_vbl + lag >= 20) {
1394: lag = now - last_vbl + lag - 20;
1395: /* crap pooter that can't keep up */
1396: if (lag > 20) {
1397: lag -= 20;
1398: bTooSlowSoSkipAFlip = TRUE;
1399: }
1400: //printf ("VBL (%dms, %d cycles, %d lag)\n", now-last_vbl, iters_this_frame, lag);
1401: last_vbl = now;
1402: Video_InterruptHandler_VBL ();
1403: iters_this_frame = 0;
1404: }
1405: }
1406: }
1407: }
1408:
1409:
1410: int in_m68k_go = 0;
1411:
1412: void m68k_go (int may_quit)
1413: {
1414: #ifdef DEBUG_PROFILE
1415: int i;
1416: int start_sec = 0;
1417: int last_runs = 0;
1418: int num;
1419: #endif
1420:
1421: if (in_m68k_go || !may_quit) {
1422: write_log ("Bug! m68k_go is not reentrant.\n");
1423: abort ();
1424: }
1425:
1426: in_m68k_go++;
1427: while(!bQuitProgram) {
1428: if(cpu_compatible)
1429: m68k_run_1();
1430: else
1431: m68k_run_2();
1432: }
1433: #ifdef DEBUG_PROFILE
1434: for (i=0; i<0x50000; i++) {
1435: if (profile_runs[i] != last_runs) {
1436: num = i - start_sec;
1437: if (start_sec == i-1) {
1438: printf ("0x%x:\t\t\(%d inst)\t%d cycles\t(%.4f%%)\n", (start_sec*2)-FE2BASE, num, num*last_runs, 100.0*num*last_runs/(float)profile_total);
1439: } else {
1440: printf ("0x%x - 0x%x:\t(%d inst)\t%d cycles\t(%.4f%%)\n", (start_sec*2)-FE2BASE, ((i-1)*2)-FE2BASE, num, num*last_runs, 100.0*num*last_runs/(float)profile_total);
1441: }
1442: start_sec = i;
1443: last_runs = profile_runs[i];
1444: }
1445: }
1446: #endif
1447:
1448: in_m68k_go--;
1449: }
1450:
1451: static void m68k_verify (uaecptr addr, uaecptr *nextpc)
1452: {
1453: uae_u32 opcode, val;
1454: struct instr *dp;
1455:
1456: opcode = get_iword_1(0);
1457: last_op_for_exception_3 = opcode;
1458: m68kpc_offset = 2;
1459:
1460: if (cpufunctbl[opcode] == op_illg_1) {
1461: opcode = 0x4AFC;
1462: }
1463: dp = table68k + opcode;
1464:
1465: if (dp->suse) {
1466: if (!verify_ea (dp->sreg, dp->smode, dp->size, &val)) {
1467: Exception (3, 0);
1468: return;
1469: }
1470: }
1471: if (dp->duse) {
1472: if (!verify_ea (dp->dreg, dp->dmode, dp->size, &val)) {
1473: Exception (3, 0);
1474: return;
1475: }
1476: }
1477: }
1478:
1479: void m68k_disasm (FILE *f, uaecptr addr, uaecptr *nextpc, int cnt)
1480: {
1481: uaecptr newpc = 0;
1482: m68kpc_offset = addr - m68k_getpc ();
1483: while (cnt-- > 0) {
1484: char instrname[20],*ccpt;
1485: int opwords;
1486: uae_u32 opcode;
1487: struct mnemolookup *lookup;
1488: struct instr *dp;
1489: fprintf (f, "%08lx: ", m68k_getpc () + m68kpc_offset);
1490: for (opwords = 0; opwords < 5; opwords++){
1491: fprintf (f, "%04x ", get_iword_1 (m68kpc_offset + opwords*2));
1492: }
1493: opcode = get_iword_1 (m68kpc_offset);
1494: m68kpc_offset += 2;
1495: if (cpufunctbl[opcode] == op_illg_1) {
1496: opcode = 0x4AFC;
1497: }
1498: dp = table68k + opcode;
1499: for (lookup = lookuptab;lookup->mnemo != dp->mnemo; lookup++)
1500: ;
1501:
1502: strcpy (instrname, lookup->name);
1503: ccpt = strstr (instrname, "cc");
1504: if (ccpt != 0) {
1505: strncpy (ccpt, ccnames[dp->cc], 2);
1506: }
1507: fprintf (f, "%s", instrname);
1508: switch (dp->size){
1509: case sz_byte: fprintf (f, ".B "); break;
1510: case sz_word: fprintf (f, ".W "); break;
1511: case sz_long: fprintf (f, ".L "); break;
1512: default: fprintf (f, " "); break;
1513: }
1514:
1515: if (dp->suse) {
1516: newpc = m68k_getpc () + m68kpc_offset;
1517: newpc += ShowEA (f, dp->sreg, dp->smode, dp->size, 0);
1518: }
1519: if (dp->suse && dp->duse)
1520: fprintf (f, ",");
1521: if (dp->duse) {
1522: newpc = m68k_getpc () + m68kpc_offset;
1523: newpc += ShowEA (f, dp->dreg, dp->dmode, dp->size, 0);
1524: }
1525: if (ccpt != 0) {
1526: if (cctrue(dp->cc))
1527: fprintf (f, " == %08lx (TRUE)", (long)newpc);
1528: else
1529: fprintf (f, " == %08lx (FALSE)", (long)newpc);
1530: } else if ((opcode & 0xff00) == 0x6100) /* BSR */
1531: fprintf (f, " == %08lx", (long)newpc);
1532: fprintf (f, "\n");
1533: }
1534: if (nextpc)
1535: *nextpc = m68k_getpc () + m68kpc_offset;
1536: }
1537:
1538: void m68k_dumpstate (FILE *f, uaecptr *nextpc)
1539: {
1540: int i;
1541: for (i = 0; i < 8; i++){
1542: fprintf (f, "D%d: %08lx ", i, (long)m68k_dreg(regs, i));
1543: if ((i & 3) == 3) fprintf (f, "\n");
1544: }
1545: for (i = 0; i < 8; i++){
1546: fprintf (f, "A%d: %08lx ", i, (long)m68k_areg(regs, i));
1547: if ((i & 3) == 3) fprintf (f, "\n");
1548: }
1549: if (regs.s == 0) regs.usp = m68k_areg(regs, 7);
1550: if (regs.s && regs.m) regs.msp = m68k_areg(regs, 7);
1551: if (regs.s && regs.m == 0) regs.isp = m68k_areg(regs, 7);
1552: fprintf (f, "USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n",
1553: (long)regs.usp,(long)regs.isp,(long)regs.msp,(long)regs.vbr);
1554: fprintf (f, "T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d\n",
1555: regs.t1, regs.t0, regs.s, regs.m,
1556: GET_XFLG, GET_NFLG, GET_ZFLG, GET_VFLG, GET_CFLG, regs.intmask);
1557: for (i = 0; i < 8; i++){
1558: fprintf (f, "FP%d: %g ", i, regs.fp[i]);
1559: if ((i & 3) == 3) fprintf (f, "\n");
1560: }
1561: fprintf (f, "N=%d Z=%d I=%d NAN=%d\n",
1562: (regs.fpsr & 0x8000000) != 0,
1563: (regs.fpsr & 0x4000000) != 0,
1564: (regs.fpsr & 0x2000000) != 0,
1565: (regs.fpsr & 0x1000000) != 0);
1566: if (cpu_compatible)
1567: fprintf (f, "prefetch %08lx\n", (unsigned long)do_get_mem_long(®s.prefetch));
1568:
1569: m68k_disasm (f, m68k_getpc (), nextpc, 1);
1570: if (nextpc)
1571: fprintf (f, "next PC: %08lx\n", (long)*nextpc);
1572: }
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