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1.1 root 1: % 0: bit 0
2: % 1: bit 1
3: % c: condition code
4: % C: condition codes, except F
5: % f: direction
6: % i: immediate
7: % I: immediate, except 00 and ff
8: % j: immediate 1..8
9: % J: immediate 0..15
10: % k: immediate 0..7
11: % K: immediate 0..63
12: % p: immediate 0..3 (CINV and CPUSH: cache field)
13: % s: source mode
14: % S: source reg
15: % d: dest mode
16: % D: dest reg
17: % r: reg
18: % z: size
19: %
20: % Actually, a sssSSS may appear as a destination, and
21: % vice versa. The only difference between sssSSS and
22: % dddDDD are the valid addressing modes. There is
23: % no match for immediate and pc-rel. addressing modes
24: % in case of dddDDD.
25: %
26: % Arp: --> -(Ar)
27: % ArP: --> (Ar)+
28: % L: (xxx.L)
29: %
30: % Fields on a line:
31: % 16 chars bitpattern :
32: % CPU level / privildge level :
33: % CPU level 0: 68000
34: % 1: 68010
35: % 2: 68020
36: % privilege level 0: not privileged
37: % 1: unprivileged only on 68000 (check regs.s)
38: % 2: privileged (check regs.s)
39: % 3: privileged if size == word (check regs.s)
40: % Flags set by instruction: XNZVC :
41: % Flags used by instruction: XNZVC :
42: % - means flag unaffected / unused
43: % 0 means flag reset
44: % 1 means flag set
45: % ? means programmer was too lazy to check or instruction may trap
46: % + means instruction is conditional branch
47: % everything else means flag set/used
48: % / means instruction is unconditional branch/call
49: % x means flag is unknown and well-behaved programs shouldn't check it
50: % srcaddr status destaddr status :
51: % bitmasks of
52: % 1 means fetched
53: % 2 means stored
54: % 4 means jump offset
55: % 8 means jump address
56: % instruction
57: %
58:
59: 0000 0000 0011 1100:00:XNZVC:XNZVC:10: ORSR.B #1
60: 0000 0000 0111 1100:02:?????:?????:10: ORSR.W #1
61: 0000 0000 zzdd dDDD:00:-NZ00:-----:13: OR.z #z,d[!Areg]
62: 0000 0010 0011 1100:00:XNZVC:XNZVC:10: ANDSR.B #1
63: 0000 0010 0111 1100:02:?????:?????:10: ANDSR.W #1
64: 0000 0010 zzdd dDDD:00:-NZ00:-----:13: AND.z #z,d[!Areg]
65: 0000 0100 zzdd dDDD:00:XNZVC:-----:13: SUB.z #z,d[!Areg]
66: 0000 0110 zzdd dDDD:00:XNZVC:-----:13: ADD.z #z,d[!Areg]
67: 0000 1000 00ss sSSS:00:--Z--:-----:11: BTST #1,s[!Areg]
68: 0000 1000 01ss sSSS:00:--Z--:-----:13: BCHG #1,s[!Areg,Immd]
69: 0000 1000 10ss sSSS:00:--Z--:-----:13: BCLR #1,s[!Areg,Immd]
70: 0000 1000 11ss sSSS:00:--Z--:-----:13: BSET #1,s[!Areg,Immd]
71: 0000 1010 0011 1100:00:XNZVC:XNZVC:10: EORSR.B #1
72: 0000 1010 0111 1100:02:?????:?????:10: EORSR.W #1
73: 0000 1010 zzdd dDDD:00:-NZ00:-----:13: EOR.z #z,d[!Areg]
74: 0000 1100 zzss sSSS:00:-NZVC:-----:11: CMP.z #z,s[!Areg,Immd]
75:
76: 0000 rrr1 00dd dDDD:00:-----:-----:12: MVPMR.W d[Areg-Ad16],Dr
77: 0000 rrr1 01dd dDDD:00:-----:-----:12: MVPMR.L d[Areg-Ad16],Dr
78: 0000 rrr1 10dd dDDD:00:-----:-----:12: MVPRM.W Dr,d[Areg-Ad16]
79: 0000 rrr1 11dd dDDD:00:-----:-----:12: MVPRM.L Dr,d[Areg-Ad16]
80: 0000 rrr1 00ss sSSS:00:--Z--:-----:11: BTST Dr,s[!Areg]
81: 0000 rrr1 01ss sSSS:00:--Z--:-----:13: BCHG Dr,s[!Areg,Immd]
82: 0000 rrr1 10ss sSSS:00:--Z--:-----:13: BCLR Dr,s[!Areg,Immd]
83: 0000 rrr1 11ss sSSS:00:--Z--:-----:13: BSET Dr,s[!Areg,Immd]
84:
85: 0001 DDDd ddss sSSS:00:-NZ00:-----:12: MOVE.B s,d[!Areg]
86: 0010 DDDd ddss sSSS:00:-----:-----:12: MOVEA.L s,d[Areg]
87: 0010 DDDd ddss sSSS:00:-NZ00:-----:12: MOVE.L s,d[!Areg]
88: 0011 DDDd ddss sSSS:00:-----:-----:12: MOVEA.W s,d[Areg]
89: 0011 DDDd ddss sSSS:00:-NZ00:-----:12: MOVE.W s,d[!Areg]
90:
91: 0100 0000 zzdd dDDD:00:XxZxC:X-Z--:30: NEGX.z d[!Areg]
92: 0100 0000 11dd dDDD:01:?????:?????:10: MVSR2.W d[!Areg]
93: 0100 0010 zzdd dDDD:00:-0100:-----:20: CLR.z d[!Areg]
94: 0100 0010 11dd dDDD:10:?????:?????:10: MVSR2.B d[!Areg]
95: 0100 0100 zzdd dDDD:00:XNZVC:-----:30: NEG.z d[!Areg]
96: 0100 0100 11ss sSSS:00:XNZVC:-----:10: MV2SR.B s[!Areg]
97: 0100 0110 zzdd dDDD:00:-NZ00:-----:30: NOT.z d[!Areg]
98: 0100 0110 11ss sSSS:02:?????:?????:10: MV2SR.W s[!Areg]
99: 0100 1000 00dd dDDD:00:X?Z?C:X-Z--:30: NBCD.B d[!Areg]
100: 0100 1000 01ss sSSS:00:-NZ00:-----:30: SWAP.W s[Dreg]
101: 0100 1000 01ss sSSS:00:-----:-----:00: PEA.L s[!Dreg,Areg,Aipi,Apdi,Immd]
102: 0100 1000 10dd dDDD:00:-NZ00:-----:30: EXT.W d[Dreg]
103: 0100 1000 10dd dDDD:00:-----:-----:02: MVMLE.W #1,d[!Dreg,Areg,Aipi]
104: 0100 1000 11dd dDDD:00:-NZ00:-----:30: EXT.L d[Dreg]
105: 0100 1000 11dd dDDD:00:-----:-----:02: MVMLE.L #1,d[!Dreg,Areg,Aipi]
106: 0100 1001 11dd dDDD:00:-NZ00:-----:30: EXT.B d[Dreg]
107: 0100 1010 zzss sSSS:00:-NZ00:-----:10: TST.z s
108: 0100 1010 11dd dDDD:00:?????:?????:30: TAS.B d[!Areg]
109: 0100 1010 1111 1100:00:?????:?????:00: ILLEGAL
110: 0100 1100 10ss sSSS:00:-----:-----:01: MVMEL.W #1,s[!Dreg,Areg,Apdi,Immd]
111: 0100 1100 11ss sSSS:00:-----:-----:01: MVMEL.L #1,s[!Dreg,Areg,Apdi,Immd]
112: 0100 1110 0100 JJJJ:00:-----:XNZVC:10: TRAP #J
113: 0100 1110 0101 0rrr:00:-----:-----:31: LINK.W Ar,#1
114: 0100 1110 0101 1rrr:00:-----:-----:30: UNLK.L Ar
115: 0100 1110 0110 0rrr:02:-----:-----:10: MVR2USP.L Ar
116: 0100 1110 0110 1rrr:02:-----:-----:20: MVUSP2R.L Ar
117: 0100 1110 0111 0000:02:-----:-----:00: RESET
118: 0100 1110 0111 0001:00:-----:-----:00: NOP
119: 0100 1110 0111 0010:02:XNZVC:-----:10: STOP #1
120: 0100 1110 0111 0011:02:XNZVC:-----:00: RTE
121: 0100 1110 0111 0100:00:?????:?????:10: RTD #1
122: 0100 1110 0111 0101:00:-----:-----:00: RTS
123: 0100 1110 0111 0110:00:-----:XNZVC:00: TRAPV
124: 0100 1110 0111 0111:00:XNZVC:-----:00: RTR
125: 0100 1110 0111 1010:12:?????:?????:10: MOVEC2 #1
126: 0100 1110 0111 1011:12:?????:?????:10: MOVE2C #1
127: 0100 1110 10ss sSSS:00://///://///:80: JSR.L s[!Dreg,Areg,Aipi,Apdi,Immd]
128: 0100 rrr1 00ss sSSS:00:?????:?????:11: CHK.L s[!Areg],Dr
129: 0100 rrr1 10ss sSSS:00:?????:?????:11: CHK.W s[!Areg],Dr
130: 0100 1110 11ss sSSS:00://///://///:80: JMP.L s[!Dreg,Areg,Aipi,Apdi,Immd]
131: 0100 rrr1 11ss sSSS:00:-----:-----:02: LEA.L s[!Dreg,Areg,Aipi,Apdi,Immd],Ar
132:
133: 0101 jjj0 01dd dDDD:00:-----:-----:13: ADDA.W #j,d[Areg]
134: 0101 jjj0 10dd dDDD:00:-----:-----:13: ADDA.L #j,d[Areg]
135: 0101 jjj0 zzdd dDDD:00:XNZVC:-----:13: ADD.z #j,d[!Areg]
136: 0101 jjj1 01dd dDDD:00:-----:-----:13: SUBA.W #j,d[Areg]
137: 0101 jjj1 10dd dDDD:00:-----:-----:13: SUBA.L #j,d[Areg]
138: 0101 jjj1 zzdd dDDD:00:XNZVC:-----:13: SUB.z #j,d[!Areg]
139: 0101 cccc 1100 1rrr:00:-----:-++++:31: DBcc.W Dr,#1
140: 0101 cccc 11dd dDDD:00:-----:-++++:20: Scc.B d[!Areg]
141:
142: % Bxx.L is 68020 only, but setting the CPU level to 2 would give illegal
143: % instruction exceptions when compiling a 68000 only emulation, which isn't
144: % what we want either.
145: 0110 0001 0000 0000:00://///://///:40: BSR.W #1
146: 0110 0001 IIII IIII:00://///://///:40: BSR.B #i
147: 0110 0001 1111 1111:00://///://///:40: BSR.L #2
148: 0110 CCCC 0000 0000:00:-----:-++++:40: Bcc.W #1
149: 0110 CCCC IIII IIII:00:-----:-++++:40: Bcc.B #i
150: 0110 CCCC 1111 1111:00:-----:-++++:40: Bcc.L #2
151:
152: 0111 rrr0 iiii iiii:00:-NZ00:-----:12: MOVE.L #i,Dr
153:
154: 1000 rrr0 zzss sSSS:00:-NZ00:-----:13: OR.z s[!Areg],Dr
155: 1000 rrr0 11ss sSSS:00:?????:?????:13: DIVU.W s[!Areg],Dr
156: 1000 rrr1 00dd dDDD:00:XxZxC:X-Z--:13: SBCD.B d[Dreg],Dr
157: 1000 rrr1 00dd dDDD:00:XxZxC:X-Z--:13: SBCD.B d[Areg-Apdi],Arp
158: 1000 rrr1 zzdd dDDD:00:-NZ00:-----:13: OR.z Dr,d[!Areg,Dreg]
159: 1000 rrr1 11ss sSSS:00:?????:?????:13: DIVS.W s[!Areg],Dr
160:
161: 1001 rrr0 zzss sSSS:00:XNZVC:-----:13: SUB.z s,Dr
162: 1001 rrr0 11ss sSSS:00:-----:-----:13: SUBA.W s,Ar
163: 1001 rrr1 zzdd dDDD:00:XNZVC:X-Z--:13: SUBX.z d[Dreg],Dr
164: 1001 rrr1 zzdd dDDD:00:XNZVC:X-Z--:13: SUBX.z d[Areg-Apdi],Arp
165: 1001 rrr1 zzdd dDDD:00:XNZVC:-----:13: SUB.z Dr,d[!Areg,Dreg]
166: 1001 rrr1 11ss sSSS:00:-----:-----:13: SUBA.L s,Ar
167:
168: 1011 rrr0 zzss sSSS:00:-NZVC:-----:11: CMP.z s,Dr
169: 1011 rrr0 11ss sSSS:00:-NZVC:-----:11: CMPA.W s,Ar
170: 1011 rrr1 11ss sSSS:00:-NZVC:-----:11: CMPA.L s,Ar
171: 1011 rrr1 zzdd dDDD:00:-NZVC:-----:11: CMPM.z d[Areg-Aipi],ArP
172: 1011 rrr1 zzdd dDDD:00:-NZ00:-----:13: EOR.z Dr,d[!Areg]
173:
174: 1100 rrr0 zzss sSSS:00:-NZ00:-----:13: AND.z s[!Areg],Dr
175: 1100 rrr0 11ss sSSS:00:-NZ00:-----:13: MULU.W s[!Areg],Dr
176: 1100 rrr1 00dd dDDD:00:XxZxC:X-Z--:13: ABCD.B d[Dreg],Dr
177: 1100 rrr1 00dd dDDD:00:XxZxC:X-Z--:13: ABCD.B d[Areg-Apdi],Arp
178: 1100 rrr1 zzdd dDDD:00:-NZ00:-----:13: AND.z Dr,d[!Areg,Dreg]
179: 1100 rrr1 01dd dDDD:00:-----:-----:33: EXG.L Dr,d[Dreg]
180: 1100 rrr1 01dd dDDD:00:-----:-----:33: EXG.L Ar,d[Areg]
181: 1100 rrr1 10dd dDDD:00:-----:-----:33: EXG.L Dr,d[Areg]
182: 1100 rrr1 11ss sSSS:00:-NZ00:-----:13: MULS.W s[!Areg],Dr
183:
184: 1101 rrr0 zzss sSSS:00:XNZVC:-----:13: ADD.z s,Dr
185: 1101 rrr0 11ss sSSS:00:-----:-----:13: ADDA.W s,Ar
186: 1101 rrr1 zzdd dDDD:00:XNZVC:X-Z--:13: ADDX.z d[Dreg],Dr
187: 1101 rrr1 zzdd dDDD:00:XNZVC:X-Z--:13: ADDX.z d[Areg-Apdi],Arp
188: 1101 rrr1 zzdd dDDD:00:XNZVC:-----:13: ADD.z Dr,d[!Areg,Dreg]
189: 1101 rrr1 11ss sSSS:00:-----:-----:13: ADDA.L s,Ar
190:
191: 1110 jjjf zz00 0RRR:00:XNZVC:-----:13: ASf.z #j,DR
192: 1110 jjjf zz00 1RRR:00:XNZ0C:-----:13: LSf.z #j,DR
193: 1110 jjjf zz01 0RRR:00:XNZ0C:X----:13: ROXf.z #j,DR
194: 1110 jjjf zz01 1RRR:00:-NZ0C:-----:13: ROf.z #j,DR
195: 1110 rrrf zz10 0RRR:00:XNZVC:X----:13: ASf.z Dr,DR
196: 1110 rrrf zz10 1RRR:00:XNZ0C:X----:13: LSf.z Dr,DR
197: 1110 rrrf zz11 0RRR:00:XNZ0C:X----:13: ROXf.z Dr,DR
198: 1110 rrrf zz11 1RRR:00:-NZ0C:-----:13: ROf.z Dr,DR
199: 1110 000f 11dd dDDD:00:XNZVC:-----:13: ASfW.W d[!Dreg,Areg]
200: 1110 001f 11dd dDDD:00:XNZ0C:-----:13: LSfW.W d[!Dreg,Areg]
201: 1110 010f 11dd dDDD:00:XNZ0C:X----:13: ROXfW.W d[!Dreg,Areg]
202: 1110 011f 11dd dDDD:00:-NZ0C:-----:13: ROfW.W d[!Dreg,Areg]
203:
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