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1.1 root 1: /* Optimize by combining instructions for GNU compiler.
2: Copyright (C) 1987, 1988, 1992 Free Software Foundation, Inc.
3:
4: This file is part of GNU CC.
5:
6: GNU CC is free software; you can redistribute it and/or modify
7: it under the terms of the GNU General Public License as published by
8: the Free Software Foundation; either version 2, or (at your option)
9: any later version.
10:
11: GNU CC is distributed in the hope that it will be useful,
12: but WITHOUT ANY WARRANTY; without even the implied warranty of
13: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14: GNU General Public License for more details.
15:
16: You should have received a copy of the GNU General Public License
17: along with GNU CC; see the file COPYING. If not, write to
18: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
19:
20:
21: /* This module is essentially the "combiner" phase of the U. of Arizona
22: Portable Optimizer, but redone to work on our list-structured
23: representation for RTL instead of their string representation.
24:
25: The LOG_LINKS of each insn identify the most recent assignment
26: to each REG used in the insn. It is a list of previous insns,
27: each of which contains a SET for a REG that is used in this insn
28: and not used or set in between. LOG_LINKs never cross basic blocks.
29: They were set up by the preceding pass (lifetime analysis).
30:
31: We try to combine each pair of insns joined by a logical link.
32: We also try to combine triples of insns A, B and C when
33: C has a link back to B and B has a link back to A.
34:
35: LOG_LINKS does not have links for use of the CC0. They don't
36: need to, because the insn that sets the CC0 is always immediately
37: before the insn that tests it. So we always regard a branch
38: insn as having a logical link to the preceding insn. The same is true
39: for an insn explicitly using CC0.
40:
41: We check (with use_crosses_set_p) to avoid combining in such a way
42: as to move a computation to a place where its value would be different.
43:
44: Combination is done by mathematically substituting the previous
45: insn(s) values for the regs they set into the expressions in
46: the later insns that refer to these regs. If the result is a valid insn
47: for our target machine, according to the machine description,
48: we install it, delete the earlier insns, and update the data flow
49: information (LOG_LINKS and REG_NOTES) for what we did.
50:
51: There are a few exceptions where the dataflow information created by
52: flow.c aren't completely updated:
53:
54: - reg_live_length is not updated
55: - reg_n_refs is not adjusted in the rare case when a register is
56: no longer required in a computation
57: - there are extremely rare cases (see distribute_regnotes) when a
58: REG_DEAD note is lost
59: - a LOG_LINKS entry that refers to an insn with multiple SETs may be
60: removed because there is no way to know which register it was
61: linking
62:
63: To simplify substitution, we combine only when the earlier insn(s)
64: consist of only a single assignment. To simplify updating afterward,
65: we never combine when a subroutine call appears in the middle.
66:
67: Since we do not represent assignments to CC0 explicitly except when that
68: is all an insn does, there is no LOG_LINKS entry in an insn that uses
69: the condition code for the insn that set the condition code.
70: Fortunately, these two insns must be consecutive.
71: Therefore, every JUMP_INSN is taken to have an implicit logical link
72: to the preceding insn. This is not quite right, since non-jumps can
73: also use the condition code; but in practice such insns would not
74: combine anyway. */
75:
76: #include <stdio.h>
77:
78: #include "config.h"
79: #include "gvarargs.h"
80: #include "rtl.h"
81: #include "flags.h"
82: #include "regs.h"
83: #include "expr.h"
84: #include "basic-block.h"
85: #include "insn-config.h"
86: #include "insn-flags.h"
87: #include "insn-codes.h"
88: #include "insn-attr.h"
89: #include "recog.h"
90: #include "real.h"
91:
92: /* It is not safe to use ordinary gen_lowpart in combine.
93: Use gen_lowpart_for_combine instead. See comments there. */
94: #define gen_lowpart dont_use_gen_lowpart_you_dummy
95:
96: /* Number of attempts to combine instructions in this function. */
97:
98: static int combine_attempts;
99:
100: /* Number of attempts that got as far as substitution in this function. */
101:
102: static int combine_merges;
103:
104: /* Number of instructions combined with added SETs in this function. */
105:
106: static int combine_extras;
107:
108: /* Number of instructions combined in this function. */
109:
110: static int combine_successes;
111:
112: /* Totals over entire compilation. */
113:
114: static int total_attempts, total_merges, total_extras, total_successes;
115:
116: /* Vector mapping INSN_UIDs to cuids.
1.1.1.2 ! root 117: The cuids are like uids but increase monotonically always.
1.1 root 118: Combine always uses cuids so that it can compare them.
119: But actually renumbering the uids, which we used to do,
120: proves to be a bad idea because it makes it hard to compare
121: the dumps produced by earlier passes with those from later passes. */
122:
123: static int *uid_cuid;
124:
125: /* Get the cuid of an insn. */
126:
127: #define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)])
128:
129: /* Maximum register number, which is the size of the tables below. */
130:
131: static int combine_max_regno;
132:
133: /* Record last point of death of (hard or pseudo) register n. */
134:
135: static rtx *reg_last_death;
136:
137: /* Record last point of modification of (hard or pseudo) register n. */
138:
139: static rtx *reg_last_set;
140:
141: /* Record the cuid of the last insn that invalidated memory
142: (anything that writes memory, and subroutine calls, but not pushes). */
143:
144: static int mem_last_set;
145:
146: /* Record the cuid of the last CALL_INSN
147: so we can tell whether a potential combination crosses any calls. */
148:
149: static int last_call_cuid;
150:
151: /* When `subst' is called, this is the insn that is being modified
152: (by combining in a previous insn). The PATTERN of this insn
153: is still the old pattern partially modified and it should not be
154: looked at, but this may be used to examine the successors of the insn
155: to judge whether a simplification is valid. */
156:
157: static rtx subst_insn;
158:
159: /* This is the lowest CUID that `subst' is currently dealing with.
160: get_last_value will not return a value if the register was set at or
161: after this CUID. If not for this mechanism, we could get confused if
162: I2 or I1 in try_combine were an insn that used the old value of a register
163: to obtain a new value. In that case, we might erroneously get the
164: new value of the register when we wanted the old one. */
165:
166: static int subst_low_cuid;
167:
168: /* This is the value of undobuf.num_undo when we started processing this
169: substitution. This will prevent gen_rtx_combine from re-used a piece
170: from the previous expression. Doing so can produce circular rtl
171: structures. */
172:
173: static int previous_num_undos;
174:
175: /* The next group of arrays allows the recording of the last value assigned
176: to (hard or pseudo) register n. We use this information to see if a
1.1.1.2 ! root 177: operation being processed is redundant given a prior operation performed
1.1 root 178: on the register. For example, an `and' with a constant is redundant if
179: all the zero bits are already known to be turned off.
180:
181: We use an approach similar to that used by cse, but change it in the
182: following ways:
183:
184: (1) We do not want to reinitialize at each label.
185: (2) It is useful, but not critical, to know the actual value assigned
186: to a register. Often just its form is helpful.
187:
188: Therefore, we maintain the following arrays:
189:
190: reg_last_set_value the last value assigned
191: reg_last_set_label records the value of label_tick when the
192: register was assigned
193: reg_last_set_table_tick records the value of label_tick when a
194: value using the register is assigned
195: reg_last_set_invalid set to non-zero when it is not valid
196: to use the value of this register in some
197: register's value
198:
199: To understand the usage of these tables, it is important to understand
200: the distinction between the value in reg_last_set_value being valid
201: and the register being validly contained in some other expression in the
202: table.
203:
204: Entry I in reg_last_set_value is valid if it is non-zero, and either
205: reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
206:
207: Register I may validly appear in any expression returned for the value
208: of another register if reg_n_sets[i] is 1. It may also appear in the
209: value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
210: reg_last_set_invalid[j] is zero.
211:
212: If an expression is found in the table containing a register which may
213: not validly appear in an expression, the register is replaced by
214: something that won't match, (clobber (const_int 0)).
215:
216: reg_last_set_invalid[i] is set non-zero when register I is being assigned
217: to and reg_last_set_table_tick[i] == label_tick. */
218:
219: /* Record last value assigned to (hard or pseudo) register n. */
220:
221: static rtx *reg_last_set_value;
222:
223: /* Record the value of label_tick when the value for register n is placed in
224: reg_last_set_value[n]. */
225:
226: static short *reg_last_set_label;
227:
228: /* Record the value of label_tick when an expression involving register n
229: is placed in reg_last_set_value. */
230:
231: static short *reg_last_set_table_tick;
232:
233: /* Set non-zero if references to register n in expressions should not be
234: used. */
235:
236: static char *reg_last_set_invalid;
237:
238: /* Incremented for each label. */
239:
240: static short label_tick;
241:
242: /* Some registers that are set more than once and used in more than one
243: basic block are nevertheless always set in similar ways. For example,
244: a QImode register may be loaded from memory in two places on a machine
245: where byte loads zero extend.
246:
247: We record in the following array what we know about the significant
248: bits of a register, specifically which bits are known to be zero.
249:
250: If an entry is zero, it means that we don't know anything special. */
251:
252: static int *reg_significant;
253:
254: /* Mode used to compute significance in reg_significant. It is the largest
255: integer mode that can fit in HOST_BITS_PER_INT. */
256:
257: static enum machine_mode significant_mode;
258:
259: /* Nonzero when reg_significant can be safely used. It is zero while
260: computing reg_significant. This prevents propagating values based
261: on previously set values, which can be incorrect if a variable
262: is modified in a loop. */
263:
264: static int significant_valid;
265:
266: /* Record one modification to rtl structure
267: to be undone by storing old_contents into *where.
268: is_int is 1 if the contents are an int. */
269:
270: struct undo
271: {
272: rtx *where;
273: rtx old_contents;
274: int is_int;
275: };
276:
277: struct undo_int
278: {
279: int *where;
280: int old_contents;
281: int is_int;
282: };
283:
284: /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
285: num_undo says how many are currently recorded.
286:
287: storage is nonzero if we must undo the allocation of new storage.
288: The value of storage is what to pass to obfree.
289:
290: other_insn is nonzero if we have modified some other insn in the process
291: of working on subst_insn. It must be verified too. */
292:
293: #define MAX_UNDO 50
294:
295: struct undobuf
296: {
297: int num_undo;
298: char *storage;
299: struct undo undo[MAX_UNDO];
300: rtx other_insn;
301: };
302:
303: static struct undobuf undobuf;
304:
305: /* Substitute NEWVAL, an rtx expression, into INTO, a place in a some
306: insn. The substitution can be undone by undo_all. If INTO is already
307: set to NEWVAL, do not record this change. */
308:
309: #define SUBST(INTO, NEWVAL) \
310: do { if (undobuf.num_undo < MAX_UNDO) \
311: { \
312: undobuf.undo[undobuf.num_undo].where = &INTO; \
313: undobuf.undo[undobuf.num_undo].old_contents = INTO; \
314: undobuf.undo[undobuf.num_undo].is_int = 0; \
315: INTO = NEWVAL; \
316: if (undobuf.undo[undobuf.num_undo].old_contents != INTO) \
317: undobuf.num_undo++; \
318: } \
319: } while (0)
320:
321: /* Similar to SUBST, but NEWVAL is an int. INTO will normally be an XINT
322: expression.
323: Note that substitution for the value of a CONST_INT is not safe. */
324:
325: #define SUBST_INT(INTO, NEWVAL) \
326: do { if (undobuf.num_undo < MAX_UNDO) \
327: { \
328: struct undo_int *u \
329: = (struct undo_int *)&undobuf.undo[undobuf.num_undo]; \
330: u->where = (int *) &INTO; \
331: u->old_contents = INTO; \
332: u->is_int = 1; \
333: INTO = NEWVAL; \
334: if (u->old_contents != INTO) \
335: undobuf.num_undo++; \
336: } \
337: } while (0)
338:
339: /* Number of times the pseudo being substituted for
340: was found and replaced. */
341:
342: static int n_occurrences;
343:
344: static void set_significant ();
345: static void move_deaths ();
346: rtx remove_death ();
347: static void record_value_for_reg ();
348: static void record_dead_and_set_regs ();
349: static int use_crosses_set_p ();
350: static rtx try_combine ();
351: static rtx *find_split_point ();
352: static rtx subst ();
353: static void undo_all ();
354: static int reg_dead_at_p ();
355: static rtx expand_compound_operation ();
356: static rtx expand_field_assignment ();
357: static rtx make_extraction ();
358: static int get_pos_from_mask ();
359: static rtx make_field_assignment ();
360: static rtx make_compound_operation ();
361: static rtx apply_distributive_law ();
362: static rtx simplify_and_const_int ();
363: static unsigned significant_bits ();
364: static int merge_outer_ops ();
365: static rtx simplify_shift_const ();
366: static int recog_for_combine ();
367: static rtx gen_lowpart_for_combine ();
368: static rtx gen_rtx_combine ();
369: static rtx gen_binary ();
370: static rtx gen_unary ();
371: static enum rtx_code simplify_comparison ();
372: static int reversible_comparison_p ();
373: static int get_last_value_validate ();
374: static rtx get_last_value ();
375: static void distribute_notes ();
376: static void distribute_links ();
377:
378: /* Main entry point for combiner. F is the first insn of the function.
379: NREGS is the first unused pseudo-reg number. */
380:
381: void
382: combine_instructions (f, nregs)
383: rtx f;
384: int nregs;
385: {
386: register rtx insn, next, prev;
387: register int i;
388: register rtx links, nextlinks;
389:
390: combine_attempts = 0;
391: combine_merges = 0;
392: combine_extras = 0;
393: combine_successes = 0;
394:
395: combine_max_regno = nregs;
396:
397: reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
398: reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
399: reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
400: reg_last_set_table_tick = (short *) alloca (nregs * sizeof (short));
401: reg_last_set_label = (short *) alloca (nregs * sizeof (short));
402: reg_last_set_invalid = (char *) alloca (nregs * sizeof (short));
403: reg_significant = (int *) alloca (nregs * sizeof (int));
404:
405: bzero (reg_last_death, nregs * sizeof (rtx));
406: bzero (reg_last_set, nregs * sizeof (rtx));
407: bzero (reg_last_set_value, nregs * sizeof (rtx));
408: bzero (reg_last_set_table_tick, nregs * sizeof (short));
409: bzero (reg_last_set_invalid, nregs * sizeof (char));
410: bzero (reg_significant, nregs * sizeof (int));
411:
412: init_recog_no_volatile ();
413:
414: /* Compute maximum uid value so uid_cuid can be allocated. */
415:
416: for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
417: if (INSN_UID (insn) > i)
418: i = INSN_UID (insn);
419:
420: uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
421:
422: significant_mode = mode_for_size (HOST_BITS_PER_INT, MODE_INT, 0);
423:
424: /* Don't use reg_significant when computing it. This can cause problems
425: when, for example, we have j <<= 1 in a loop. */
426:
427: significant_valid = 0;
428:
429: /* Compute the mapping from uids to cuids.
430: Cuids are numbers assigned to insns, like uids,
431: except that cuids increase monotonically through the code.
432:
433: Scan all SETs and see if we can deduce anything about what
434: bits are significant for some registers. */
435:
436: for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
437: {
438: INSN_CUID (insn) = ++i;
439: if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
440: note_stores (PATTERN (insn), set_significant);
441: }
442:
443: significant_valid = 1;
444:
445: /* Now scan all the insns in forward order. */
446:
447: label_tick = 1;
448: last_call_cuid = 0;
449: mem_last_set = 0;
450:
451: for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
452: {
453: next = 0;
454:
455: if (GET_CODE (insn) == CODE_LABEL)
456: label_tick++;
457:
458: else if (GET_CODE (insn) == INSN
459: || GET_CODE (insn) == CALL_INSN
460: || GET_CODE (insn) == JUMP_INSN)
461: {
462: /* Try this insn with each insn it links back to. */
463:
464: for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
465: if ((next = try_combine (insn, XEXP (links, 0), 0)) != 0)
466: goto retry;
467:
468: /* Try each sequence of three linked insns ending with this one. */
469:
470: for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
471: for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
472: nextlinks = XEXP (nextlinks, 1))
473: if ((next = try_combine (insn, XEXP (links, 0),
474: XEXP (nextlinks, 0))) != 0)
475: goto retry;
476:
477: #ifdef HAVE_cc0
478: /* Try to combine a jump insn that uses CC0
479: with a preceding insn that sets CC0, and maybe with its
480: logical predecessor as well.
481: This is how we make decrement-and-branch insns.
482: We need this special code because data flow connections
483: via CC0 do not get entered in LOG_LINKS. */
484:
485: if (GET_CODE (insn) == JUMP_INSN
486: && (prev = prev_nonnote_insn (insn)) != 0
487: && GET_CODE (prev) == INSN
488: && sets_cc0_p (PATTERN (prev)))
489: {
490: if ((next = try_combine (insn, prev, 0)) != 0)
491: goto retry;
492:
493: for (nextlinks = LOG_LINKS (prev); nextlinks;
494: nextlinks = XEXP (nextlinks, 1))
495: if ((next = try_combine (insn, prev,
496: XEXP (nextlinks, 0))) != 0)
497: goto retry;
498: }
499:
500: /* Do the same for an insn that explicitly references CC0. */
501: if (GET_CODE (insn) == INSN
502: && (prev = prev_nonnote_insn (insn)) != 0
503: && GET_CODE (prev) == INSN
504: && sets_cc0_p (PATTERN (prev))
505: && GET_CODE (PATTERN (insn)) == SET
506: && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
507: {
508: if ((next = try_combine (insn, prev, 0)) != 0)
509: goto retry;
510:
511: for (nextlinks = LOG_LINKS (prev); nextlinks;
512: nextlinks = XEXP (nextlinks, 1))
513: if ((next = try_combine (insn, prev,
514: XEXP (nextlinks, 0))) != 0)
515: goto retry;
516: }
517:
518: /* Finally, see if any of the insns that this insn links to
519: explicitly references CC0. If so, try this insn, that insn,
1.1.1.2 ! root 520: and its predecessor if it sets CC0. */
1.1 root 521: for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
522: if (GET_CODE (XEXP (links, 0)) == INSN
523: && GET_CODE (PATTERN (XEXP (links, 0))) == SET
524: && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
525: && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
526: && GET_CODE (prev) == INSN
527: && sets_cc0_p (PATTERN (prev))
528: && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
529: goto retry;
530: #endif
531:
532: /* Try combining an insn with two different insns whose results it
533: uses. */
534: for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
535: for (nextlinks = XEXP (links, 1); nextlinks;
536: nextlinks = XEXP (nextlinks, 1))
537: if ((next = try_combine (insn, XEXP (links, 0),
538: XEXP (nextlinks, 0))) != 0)
539: goto retry;
540:
541: if (GET_CODE (insn) != NOTE)
542: record_dead_and_set_regs (insn);
543:
544: retry:
545: ;
546: }
547: }
548:
549: total_attempts += combine_attempts;
550: total_merges += combine_merges;
551: total_extras += combine_extras;
552: total_successes += combine_successes;
553: }
554:
555: /* Called via note_stores. If X is a pseudo that is used in more than
556: one basic block, is narrower that HOST_BITS_PER_INT, and is being
557: set, record what bits are significant. If we are clobbering X,
558: ignore this "set" because the clobbered value won't be used.
559:
560: If we are setting only a portion of X and we can't figure out what
561: portion, assume all bits will be used since we don't know what will
562: be happening. */
563:
564: static void
565: set_significant (x, set)
566: rtx x;
567: rtx set;
568: {
569: if (GET_CODE (x) == REG
570: && REGNO (x) >= FIRST_PSEUDO_REGISTER
571: && reg_n_sets[REGNO (x)] > 1
572: && reg_basic_block[REGNO (x)] < 0
573: && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_INT)
574: {
575: if (GET_CODE (set) == CLOBBER)
576: return;
577:
578: /* If this is a complex assignment, see if we can convert it into a
1.1.1.2 ! root 579: simple assignment. */
1.1 root 580: set = expand_field_assignment (set);
581: if (SET_DEST (set) == x)
582: reg_significant[REGNO (x)]
583: |= significant_bits (SET_SRC (set), significant_mode);
584: else
585: reg_significant[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
586: }
587: }
588:
589: /* See if INSN can be combined into I3. PRED and SUCC are optionally
590: insns that were previously combined into I3 or that will be combined
591: into the merger of INSN and I3.
592:
593: Return 0 if the combination is not allowed for any reason.
594:
595: If the combination is allowed, *PDEST will be set to the single
596: destination of INSN and *PSRC to the single source, and this function
597: will return 1. */
598:
599: static int
600: can_combine_p (insn, i3, pred, succ, pdest, psrc)
601: rtx insn;
602: rtx i3;
603: rtx pred, succ;
604: rtx *pdest, *psrc;
605: {
606: int i;
607: rtx set = 0, src, dest;
608: rtx p, link;
609: int all_adjacent = (succ ? (next_active_insn (insn) == succ
610: && next_active_insn (succ) == i3)
611: : next_active_insn (insn) == i3);
612:
613: /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
614: or a PARALLEL consisting of such a SET and CLOBBERs.
615:
616: If INSN has CLOBBER parallel parts, ignore them for our processing.
617: By definition, these happen during the execution of the insn. When it
618: is merged with another insn, all bets are off. If they are, in fact,
619: needed and aren't also supplied in I3, they may be added by
620: recog_for_combine. Otherwise, it won't match.
621:
622: We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
623: note.
624:
625: Get the source and destination of INSN. If more than one, can't
626: combine. */
627:
628: if (GET_CODE (PATTERN (insn)) == SET)
629: set = PATTERN (insn);
630: else if (GET_CODE (PATTERN (insn)) == PARALLEL
631: && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
632: {
633: for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
634: {
635: rtx elt = XVECEXP (PATTERN (insn), 0, i);
636:
637: switch (GET_CODE (elt))
638: {
639: /* We can ignore CLOBBERs. */
640: case CLOBBER:
641: break;
642:
643: case SET:
644: /* Ignore SETs whose result isn't used but not those that
645: have side-effects. */
646: if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
647: && ! side_effects_p (elt))
648: break;
649:
650: /* If we have already found a SET, this is a second one and
651: so we cannot combine with this insn. */
652: if (set)
653: return 0;
654:
655: set = elt;
656: break;
657:
658: default:
659: /* Anything else means we can't combine. */
660: return 0;
661: }
662: }
663:
664: if (set == 0
665: /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
666: so don't do anything with it. */
667: || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
668: return 0;
669: }
670: else
671: return 0;
672:
673: if (set == 0)
674: return 0;
675:
676: set = expand_field_assignment (set);
677: src = SET_SRC (set), dest = SET_DEST (set);
678:
679: /* Don't eliminate a store in the stack pointer. */
680: if (dest == stack_pointer_rtx
681: /* Don't install a subreg involving two modes not tieable.
682: It can worsen register allocation, and can even make invalid reload
683: insns, since the reg inside may need to be copied from in the
684: outside mode, and that may be invalid if it is an fp reg copied in
1.1.1.2 ! root 685: integer mode. As a special exception, we can allow this if
! 686: I3 is simply copying DEST, a REG, to CC0. */
1.1 root 687: || (GET_CODE (src) == SUBREG
1.1.1.2 ! root 688: && ! MODES_TIEABLE_P (GET_MODE (src), GET_MODE (SUBREG_REG (src)))
! 689: #ifdef HAVE_cc0
! 690: && ! (GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
! 691: && SET_DEST (PATTERN (i3)) == cc0_rtx
! 692: && GET_CODE (dest) == REG && dest == SET_SRC (PATTERN (i3)))
! 693: #endif
! 694: )
1.1 root 695: /* If we couldn't eliminate a field assignment, we can't combine. */
696: || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
697: /* Don't combine with an insn that sets a register to itself if it has
698: a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
699: || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, 0))
700: /* Can't merge a function call. */
701: || GET_CODE (src) == CALL
702: /* Don't substitute into an incremented register. */
703: || FIND_REG_INC_NOTE (i3, dest)
704: || (succ && FIND_REG_INC_NOTE (succ, dest))
705: /* Don't combine the end of a libcall into anything. */
706: || find_reg_note (insn, REG_RETVAL, 0)
707: /* Make sure that DEST is not used after SUCC but before I3. */
708: || (succ && ! all_adjacent
709: && reg_used_between_p (dest, succ, i3))
710: /* Make sure that the value that is to be substituted for the register
711: does not use any registers whose values alter in between. However,
712: If the insns are adjacent, a use can't cross a set even though we
713: think it might (this can happen for a sequence of insns each setting
714: the same destination; reg_last_set of that register might point to
715: a NOTE). Also, don't move a volatile asm across any other insns. */
716: || (! all_adjacent
717: && (use_crosses_set_p (src, INSN_CUID (insn))
718: || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))))
719: /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
720: better register allocation by not doing the combine. */
721: || find_reg_note (i3, REG_NO_CONFLICT, dest)
722: || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
723: /* Don't combine across a CALL_INSN, because that would possibly
724: change whether the life span of some REGs crosses calls or not,
725: and it is a pain to update that information.
726: Exception: if source is a constant, moving it later can't hurt.
727: Accept that special case, because it helps -fforce-addr a lot. */
728: || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
729: return 0;
730:
731: /* DEST must either be a REG or CC0. */
732: if (GET_CODE (dest) == REG)
733: {
734: /* If register alignment is being enforced for multi-word items in all
735: cases except for parameters, it is possible to have a register copy
736: insn referencing a hard register that is not allowed to contain the
737: mode being copied and which would not be valid as an operand of most
738: insns. Eliminate this problem by not combining with such an insn.
739:
740: Also, on some machines we don't want to extend the life of a hard
741: register. */
742:
743: if (GET_CODE (src) == REG
744: && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
745: && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
746: #ifdef SMALL_REGISTER_CLASSES
747: /* Don't extend the life of a hard register. */
748: || REGNO (src) < FIRST_PSEUDO_REGISTER
749: #else
750: || (REGNO (src) < FIRST_PSEUDO_REGISTER
751: && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))
752: #endif
753: ))
754: return 0;
755: }
756: else if (GET_CODE (dest) != CC0)
757: return 0;
758:
759: /* Don't substitute for a register intended as a clobberable operand. */
760: if (GET_CODE (PATTERN (i3)) == PARALLEL)
761: for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
762: if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
763: && rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest))
764: return 0;
765:
766: /* If INSN contains anything volatile, or is an `asm' (whether volatile
767: or not), reject, unless nothing volatile comes between it and I3,
768: with the exception of SUCC. */
769:
770: if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
771: for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
772: if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
773: && p != succ && volatile_refs_p (PATTERN (p)))
774: return 0;
775:
776: /* If INSN or I2 contains an autoincrement or autodecrement,
777: make sure that register is not used between there and I3,
778: and not already used in I3 either.
779: Also insist that I3 not be a jump; if it were one
780: and the incremented register were spilled, we would lose. */
781:
782: #ifdef AUTO_INC_DEC
783: for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
784: if (REG_NOTE_KIND (link) == REG_INC
785: && (GET_CODE (i3) == JUMP_INSN
786: || reg_used_between_p (XEXP (link, 0), insn, i3)
787: || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
788: return 0;
789: #endif
790:
791: #ifdef HAVE_cc0
792: /* Don't combine an insn that follows a CC0-setting insn.
793: An insn that uses CC0 must not be separated from the one that sets it.
794: We do, however, allow I2 to follow a CC0-setting insn if that insn
795: is passed as I1; in that case it will be deleted also.
796: We also allow combining in this case if all the insns are adjacent
797: because that would leave the two CC0 insns adjacent as well.
798: It would be more logical to test whether CC0 occurs inside I1 or I2,
799: but that would be much slower, and this ought to be equivalent. */
800:
801: p = prev_nonnote_insn (insn);
802: if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
803: && ! all_adjacent)
804: return 0;
805: #endif
806:
807: /* If we get here, we have passed all the tests and the combination is
808: to be allowed. */
809:
810: *pdest = dest;
811: *psrc = src;
812:
813: return 1;
814: }
815:
816: /* LOC is the location within I3 that contains its pattern or the component
817: of a PARALLEL of the pattern. We validate that it is valid for combining.
818:
819: One problem is if I3 modifies its output, as opposed to replacing it
820: entirely, we can't allow the output to contain I2DEST or I1DEST as doing
821: so would produce an insn that is not equivalent to the original insns.
822:
823: Consider:
824:
825: (set (reg:DI 101) (reg:DI 100))
826: (set (subreg:SI (reg:DI 101) 0) <foo>)
827:
828: This is NOT equivalent to:
829:
830: (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
831: (set (reg:DI 101) (reg:DI 100))])
832:
833: Not only does this modify 100 (in which case it might still be valid
834: if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
835:
836: We can also run into a problem if I2 sets a register that I1
837: uses and I1 gets directly substituted into I3 (not via I2). In that
838: case, we would be getting the wrong value of I2DEST into I3, so we
839: must reject the combination. This case occurs when I2 and I1 both
840: feed into I3, rather than when I1 feeds into I2, which feeds into I3.
841: If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
842: of a SET must prevent combination from occurring.
843:
844: On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
845: if the destination of a SET is a hard register.
846:
847: Before doing the above check, we first try to expand a field assignment
848: into a set of logical operations.
849:
850: If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
851: we place a register that is both set and used within I3. If more than one
852: such register is detected, we fail.
853:
854: Return 1 if the combination is valid, zero otherwise. */
855:
856: static int
857: combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
858: rtx i3;
859: rtx *loc;
860: rtx i2dest;
861: rtx i1dest;
862: int i1_not_in_src;
863: rtx *pi3dest_killed;
864: {
865: rtx x = *loc;
866:
867: if (GET_CODE (x) == SET)
868: {
869: rtx set = expand_field_assignment (x);
870: rtx dest = SET_DEST (set);
871: rtx src = SET_SRC (set);
872: rtx inner_dest = dest, inner_src = src;
873:
874: SUBST (*loc, set);
875:
876: while (GET_CODE (inner_dest) == STRICT_LOW_PART
877: || GET_CODE (inner_dest) == SUBREG
878: || GET_CODE (inner_dest) == ZERO_EXTRACT)
879: inner_dest = XEXP (inner_dest, 0);
880:
881: /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
882: was added. */
883: #if 0
884: while (GET_CODE (inner_src) == STRICT_LOW_PART
885: || GET_CODE (inner_src) == SUBREG
886: || GET_CODE (inner_src) == ZERO_EXTRACT)
887: inner_src = XEXP (inner_src, 0);
888:
889: /* If it is better that two different modes keep two different pseudos,
890: avoid combining them. This avoids producing the following pattern
891: on a 386:
892: (set (subreg:SI (reg/v:QI 21) 0)
893: (lshiftrt:SI (reg/v:SI 20)
894: (const_int 24)))
895: If that were made, reload could not handle the pair of
896: reg 20/21, since it would try to get any GENERAL_REGS
897: but some of them don't handle QImode. */
898:
899: if (rtx_equal_p (inner_src, i2dest)
900: && GET_CODE (inner_dest) == REG
901: && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
902: return 0;
903: #endif
904:
905: /* Check for the case where I3 modifies its output, as
906: discussed above. */
907: if ((inner_dest != dest
908: && (reg_overlap_mentioned_p (i2dest, inner_dest)
909: || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1.1.1.2 ! root 910: /* This is the same test done in can_combine_p. */
1.1 root 911: || (GET_CODE (inner_dest) == REG
1.1.1.2 ! root 912: && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
! 913: #ifndef SMALL_REGISTER_CLASSES
! 914: && ! HARD_REGNO_MODE_OK (REGNO (inner_dest),
! 915: GET_MODE (inner_dest))
1.1 root 916: #endif
1.1.1.2 ! root 917: )
! 918:
1.1 root 919: || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
920: return 0;
921:
922: /* If DEST is used in I3, it is being killed in this insn,
923: so record that for later. */
924: if (pi3dest_killed && GET_CODE (dest) == REG
925: && reg_referenced_p (dest, PATTERN (i3)))
926: {
927: if (*pi3dest_killed)
928: return 0;
929:
930: *pi3dest_killed = dest;
931: }
932: }
933:
934: else if (GET_CODE (x) == PARALLEL)
935: {
936: int i;
937:
938: for (i = 0; i < XVECLEN (x, 0); i++)
939: if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
940: i1_not_in_src, pi3dest_killed))
941: return 0;
942: }
943:
944: return 1;
945: }
946:
947: /* Try to combine the insns I1 and I2 into I3.
948: Here I1 and I2 appear earlier than I3.
949: I1 can be zero; then we combine just I2 into I3.
950:
951: It we are combining three insns and the resulting insn is not recognized,
952: try splitting it into two insns. If that happens, I2 and I3 are retained
953: and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
954: are pseudo-deleted.
955:
956: If we created two insns, return I2; otherwise return I3.
957: Return 0 if the combination does not work. Then nothing is changed. */
958:
959: static rtx
960: try_combine (i3, i2, i1)
961: register rtx i3, i2, i1;
962: {
963: /* New patterns for I3 and I3, respectively. */
964: rtx newpat, newi2pat = 0;
965: /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
966: int added_sets_1, added_sets_2;
967: /* Total number of SETs to put into I3. */
968: int total_sets;
969: /* Nonzero is I2's body now appears in I3. */
970: int i2_is_used;
971: /* INSN_CODEs for new I3, new I2, and user of condition code. */
972: int insn_code_number, i2_code_number, other_code_number;
973: /* Contains I3 if the destination of I3 is used in its source, which means
974: that the old life of I3 is being killed. If that usage is placed into
975: I2 and not in I3, a REG_DEAD note must be made. */
976: rtx i3dest_killed = 0;
977: /* SET_DEST and SET_SRC of I2 and I1. */
978: rtx i2dest, i2src, i1dest = 0, i1src = 0;
979: /* PATTERN (I2), or a copy of it in certain cases. */
980: rtx i2pat;
981: /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
982: int i2dest_in_i2src, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
983: int i1_feeds_i3 = 0;
984: /* Notes that must be added to REG_NOTES in I3 and I2. */
985: rtx new_i3_notes, new_i2_notes;
986:
987: int maxreg;
988: rtx temp;
989: register rtx link;
990: int i;
991:
992: /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
993: This can occur when flow deletes an insn that it has merged into an
994: auto-increment address. We also can't do anything if I3 has a
995: REG_LIBCALL note since we don't want to disrupt the contiguity of a
996: libcall. */
997:
998: if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
999: || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1000: || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1001: || find_reg_note (i3, REG_LIBCALL, 0))
1002: return 0;
1003:
1004: combine_attempts++;
1005:
1006: undobuf.num_undo = previous_num_undos = 0;
1007: undobuf.other_insn = 0;
1008:
1009: /* Save the current high-water-mark so we can free storage if we didn't
1010: accept this combination. */
1011: undobuf.storage = (char *) oballoc (0);
1012:
1013: /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1014: code below, set I1 to be the earlier of the two insns. */
1015: if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1016: temp = i1, i1 = i2, i2 = temp;
1017:
1018: /* First check for one important special-case that the code below will
1019: not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1020: and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1021: we may be able to replace that destination with the destination of I3.
1022: This occurs in the common code where we compute both a quotient and
1023: remainder into a structure, in which case we want to do the computation
1024: directly into the structure to avoid register-register copies.
1025:
1026: We make very conservative checks below and only try to handle the
1027: most common cases of this. For example, we only handle the case
1028: where I2 and I3 are adjacent to avoid making difficult register
1029: usage tests. */
1030:
1031: if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1032: && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1033: && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1034: #ifdef SMALL_REGISTER_CLASSES
1035: && (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1036: || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER)
1037: #endif
1038: && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1039: && GET_CODE (PATTERN (i2)) == PARALLEL
1040: && ! side_effects_p (SET_DEST (PATTERN (i3)))
1.1.1.2 ! root 1041: /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
! 1042: below would need to check what is inside (and reg_overlap_mentioned_p
! 1043: doesn't support those codes anyway). Don't allow those destinations;
! 1044: the resulting insn isn't likely to be recognized anyway. */
! 1045: && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
! 1046: && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1.1 root 1047: && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1048: SET_DEST (PATTERN (i3)))
1049: && next_real_insn (i2) == i3)
1.1.1.2 ! root 1050: {
! 1051: rtx p2 = PATTERN (i2);
1.1 root 1052:
1.1.1.2 ! root 1053: /* Make sure that the destination of I3,
! 1054: which we are going to substitute into one output of I2,
! 1055: is not used within another output of I2. We must avoid making this:
! 1056: (parallel [(set (mem (reg 69)) ...)
! 1057: (set (reg 69) ...)])
! 1058: which is not well-defined as to order of actions.
! 1059: (Besides, reload can't handle output reloads for this.)
! 1060:
! 1061: The problem can also happen if the dest of I3 is a memory ref,
! 1062: if another dest in I2 is an indirect memory ref. */
! 1063: for (i = 0; i < XVECLEN (p2, 0); i++)
! 1064: if (GET_CODE (XVECEXP (p2, 0, i)) == SET
! 1065: && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
! 1066: SET_DEST (XVECEXP (p2, 0, i))))
! 1067: break;
! 1068:
! 1069: if (i == XVECLEN (p2, 0))
! 1070: for (i = 0; i < XVECLEN (p2, 0); i++)
! 1071: if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
! 1072: {
! 1073: combine_merges++;
! 1074:
! 1075: subst_insn = i3;
! 1076: subst_low_cuid = INSN_CUID (i2);
! 1077:
! 1078: added_sets_2 = 0;
! 1079: i2dest = SET_SRC (PATTERN (i3));
! 1080:
! 1081: /* Replace the dest in I2 with our dest and make the resulting
! 1082: insn the new pattern for I3. Then skip to where we
! 1083: validate the pattern. Everything was set up above. */
! 1084: SUBST (SET_DEST (XVECEXP (p2, 0, i)),
! 1085: SET_DEST (PATTERN (i3)));
1.1 root 1086:
1.1.1.2 ! root 1087: newpat = p2;
! 1088: goto validate_replacement;
! 1089: }
! 1090: }
1.1 root 1091:
1092: #ifndef HAVE_cc0
1093: /* If we have no I1 and I2 looks like:
1094: (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1095: (set Y OP)])
1096: make up a dummy I1 that is
1097: (set Y OP)
1098: and change I2 to be
1099: (set (reg:CC X) (compare:CC Y (const_int 0)))
1100:
1101: (We can ignore any trailing CLOBBERs.)
1102:
1103: This undoes a previous combination and allows us to match a branch-and-
1104: decrement insn. */
1105:
1106: if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1107: && XVECLEN (PATTERN (i2), 0) >= 2
1108: && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1109: && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1110: == MODE_CC)
1111: && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1112: && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1113: && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1114: && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1115: && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1116: SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1117: {
1118: for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1119: if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1120: break;
1121:
1122: if (i == 1)
1123: {
1124: /* We make I1 with the same INSN_UID as I2. This gives it
1125: the same INSN_CUID for value tracking. Our fake I1 will
1126: never appear in the insn stream so giving it the same INSN_UID
1127: as I2 will not cause a problem. */
1128:
1129: i1 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), 0, i2,
1130: XVECEXP (PATTERN (i2), 0, 1), -1, 0, 0);
1131:
1132: SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1133: SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1134: SET_DEST (PATTERN (i1)));
1135: }
1136: }
1137: #endif
1138:
1139: /* Verify that I2 and I1 are valid for combining. */
1140: if (! can_combine_p (i2, i3, i1, 0, &i2dest, &i2src)
1141: || (i1 && ! can_combine_p (i1, i3, 0, i2, &i1dest, &i1src)))
1142: {
1143: undo_all ();
1144: return 0;
1145: }
1146:
1147: /* Record whether I2DEST is used in I2SRC and similarly for the other
1148: cases. Knowing this will help in register status updating below. */
1149: i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1150: i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1151: i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1152:
1153: /* See if I1 directly feeds into I3. It does if I1dest is not used
1154: in I2SRC. */
1155: i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1156:
1157: /* Ensure that I3's pattern can be the destination of combines. */
1158: if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1159: i1 && i2dest_in_i1src && i1_feeds_i3,
1160: &i3dest_killed))
1161: {
1162: undo_all ();
1163: return 0;
1164: }
1165:
1166: /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1167: We used to do this EXCEPT in one case: I3 has a post-inc in an
1168: output operand. However, that exception can give rise to insns like
1169: mov r3,(r3)+
1170: which is a famous insn on the PDP-11 where the value of r3 used as the
1.1.1.2 ! root 1171: source was model-dependent. Avoid this sort of thing. */
1.1 root 1172:
1173: #if 0
1174: if (!(GET_CODE (PATTERN (i3)) == SET
1175: && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1176: && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1177: && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1178: || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1179: /* It's not the exception. */
1180: #endif
1181: #ifdef AUTO_INC_DEC
1182: for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1183: if (REG_NOTE_KIND (link) == REG_INC
1184: && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1185: || (i1 != 0
1186: && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1187: {
1188: undo_all ();
1189: return 0;
1190: }
1191: #endif
1192:
1193: /* See if the SETs in I1 or I2 need to be kept around in the merged
1194: instruction: whenever the value set there is still needed past I3.
1195: For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1196:
1197: For the SET in I1, we have two cases: If I1 and I2 independently
1198: feed into I3, the set in I1 needs to be kept around if I1DEST dies
1199: or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1200: in I1 needs to be kept around unless I1DEST dies or is set in either
1201: I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1202: I1DEST. If so, we know I1 feeds into I2. */
1203:
1204: added_sets_2 = ! dead_or_set_p (i3, i2dest);
1205:
1206: added_sets_1
1207: = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1208: : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1209:
1210: /* If the set in I2 needs to be kept around, we must make a copy of
1211: PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1.1.1.2 ! root 1212: PATTERN (I2), we are only substituting for the original I1DEST, not into
1.1 root 1213: an already-substituted copy. This also prevents making self-referential
1214: rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1215: I2DEST. */
1216:
1217: i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1218: ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1219: : PATTERN (i2));
1220:
1221: if (added_sets_2)
1222: i2pat = copy_rtx (i2pat);
1223:
1224: combine_merges++;
1225:
1226: /* Substitute in the latest insn for the regs set by the earlier ones. */
1227:
1228: maxreg = max_reg_num ();
1229:
1230: subst_insn = i3;
1231: subst_low_cuid = i1 ? INSN_CUID (i1) : INSN_CUID (i2);
1232:
1233: /* It is possible that the source of I2 or I1 may be performing an
1234: unneeded operation, such as a ZERO_EXTEND of something that is known
1235: to have the high part zero. Handle that case by letting subst look at
1236: the innermost one of them.
1237:
1238: Another way to do this would be to have a function that tries to
1239: simplify a single insn instead of merging two or more insns. We don't
1240: do this because of the potential of infinite loops and because
1241: of the potential extra memory required. However, doing it the way
1242: we are is a bit of a kludge and doesn't catch all cases.
1243:
1244: But only do this if -fexpensive-optimizations since it slows things down
1245: and doesn't usually win. */
1246:
1247: if (flag_expensive_optimizations)
1248: {
1249: /* Pass pc_rtx so no substitutions are done, just simplifications.
1250: The cases that we are interested in here do not involve the few
1251: cases were is_replaced is checked. */
1252: if (i1)
1253: i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1254: else
1255: i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1256:
1257: previous_num_undos = undobuf.num_undo;
1258: }
1259:
1260: #ifndef HAVE_cc0
1261: /* Many machines that don't use CC0 have insns that can both perform an
1262: arithmetic operation and set the condition code. These operations will
1263: be represented as a PARALLEL with the first element of the vector
1264: being a COMPARE of an arithmetic operation with the constant zero.
1265: The second element of the vector will set some pseudo to the result
1266: of the same arithmetic operation. If we simplify the COMPARE, we won't
1267: match such a pattern and so will generate an extra insn. Here we test
1268: for this case, where both the comparison and the operation result are
1269: needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1270: I2SRC. Later we will make the PARALLEL that contains I2. */
1271:
1272: if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1273: && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1274: && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1275: && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1276: {
1277: rtx *cc_use;
1278: enum machine_mode compare_mode;
1279:
1280: newpat = PATTERN (i3);
1281: SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1282:
1283: i2_is_used = 1;
1284:
1285: #ifdef EXTRA_CC_MODES
1286: /* See if a COMPARE with the operand we substituted in should be done
1287: with the mode that is currently being used. If not, do the same
1288: processing we do in `subst' for a SET; namely, if the destination
1289: is used only once, try to replace it with a register of the proper
1290: mode and also replace the COMPARE. */
1291: if (undobuf.other_insn == 0
1292: && (cc_use = find_single_use (SET_DEST (newpat), i3,
1293: &undobuf.other_insn))
1294: && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use), i2src))
1295: != GET_MODE (SET_DEST (newpat))))
1296: {
1297: int regno = REGNO (SET_DEST (newpat));
1298: rtx new_dest = gen_rtx (REG, compare_mode, regno);
1299:
1300: if (regno < FIRST_PSEUDO_REGISTER
1301: || (reg_n_sets[regno] == 1 && ! added_sets_2
1302: && ! REG_USERVAR_P (SET_DEST (newpat))))
1303: {
1304: if (regno >= FIRST_PSEUDO_REGISTER)
1305: SUBST (regno_reg_rtx[regno], new_dest);
1306:
1307: SUBST (SET_DEST (newpat), new_dest);
1308: SUBST (XEXP (*cc_use, 0), new_dest);
1309: SUBST (SET_SRC (newpat),
1310: gen_rtx_combine (COMPARE, compare_mode,
1311: i2src, const0_rtx));
1312: }
1313: else
1314: undobuf.other_insn = 0;
1315: }
1316: #endif
1317: }
1318: else
1319: #endif
1320: {
1321: n_occurrences = 0; /* `subst' counts here */
1322:
1323: /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1324: need to make a unique copy of I2SRC each time we substitute it
1325: to avoid self-referential rtl. */
1326:
1327: newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1328: ! i1_feeds_i3 && i1dest_in_i1src);
1329: previous_num_undos = undobuf.num_undo;
1330:
1331: /* Record whether i2's body now appears within i3's body. */
1332: i2_is_used = n_occurrences;
1333: }
1334:
1335: /* If we already got a failure, don't try to do more. Otherwise,
1336: try to substitute in I1 if we have it. */
1337:
1338: if (i1 && GET_CODE (newpat) != CLOBBER)
1339: {
1340: /* Before we can do this substitution, we must redo the test done
1341: above (see detailed comments there) that ensures that I1DEST
1342: isn't mentioned in any SETs in NEWPAT that are field assignments. */
1343:
1344: if (! combinable_i3pat (0, &newpat, i1dest, 0, 0, 0))
1345: {
1346: undo_all ();
1347: return 0;
1348: }
1349:
1350: n_occurrences = 0;
1351: newpat = subst (newpat, i1dest, i1src, 0, 0);
1352: previous_num_undos = undobuf.num_undo;
1353: }
1354:
1355: /* Fail if an autoincrement side-effect has been duplicated. */
1356: if ((i2_is_used > 1 && FIND_REG_INC_NOTE (i2, 0) != 0)
1357: || (i1 != 0 && n_occurrences > 1 && FIND_REG_INC_NOTE (i1, 0) != 0)
1358: /* Fail if we tried to make a new register (we used to abort, but there's
1359: really no reason to). */
1360: || max_reg_num () != maxreg
1361: /* Fail if we couldn't do something and have a CLOBBER. */
1362: || GET_CODE (newpat) == CLOBBER)
1363: {
1364: undo_all ();
1365: return 0;
1366: }
1367:
1368: /* If the actions of the earlier insns must be kept
1369: in addition to substituting them into the latest one,
1370: we must make a new PARALLEL for the latest insn
1371: to hold additional the SETs. */
1372:
1373: if (added_sets_1 || added_sets_2)
1374: {
1375: combine_extras++;
1376:
1377: if (GET_CODE (newpat) == PARALLEL)
1378: {
1379: rtvec old = XVEC (newpat, 0);
1380: total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1381: newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1382: bcopy (&old->elem[0], &XVECEXP (newpat, 0, 0),
1383: sizeof (old->elem[0]) * old->num_elem);
1384: }
1385: else
1386: {
1387: rtx old = newpat;
1388: total_sets = 1 + added_sets_1 + added_sets_2;
1389: newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1390: XVECEXP (newpat, 0, 0) = old;
1391: }
1392:
1393: if (added_sets_1)
1394: XVECEXP (newpat, 0, --total_sets)
1395: = (GET_CODE (PATTERN (i1)) == PARALLEL
1396: ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1397:
1398: if (added_sets_2)
1399: {
1400: /* If there is no I1, use I2's body as is. We used to also not do
1401: the subst call below if I2 was substituted into I3,
1402: but that could lose a simplification. */
1403: if (i1 == 0)
1404: XVECEXP (newpat, 0, --total_sets) = i2pat;
1405: else
1406: /* See comment where i2pat is assigned. */
1407: XVECEXP (newpat, 0, --total_sets)
1408: = subst (i2pat, i1dest, i1src, 0, 0);
1409: }
1410: }
1411:
1412: /* We come here when we are replacing a destination in I2 with the
1413: destination of I3. */
1414: validate_replacement:
1415:
1416: /* Is the result of combination a valid instruction? */
1417: insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1418:
1419: /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1420: the second SET's destination is a register that is unused. In that case,
1421: we just need the first SET. This can occur when simplifying a divmod
1422: insn. We *must* test for this case here because the code below that
1423: splits two independent SETs doesn't handle this case correctly when it
1424: updates the register status. Also check the case where the first
1425: SET's destination is unused. That would not cause incorrect code, but
1426: does cause an unneeded insn to remain. */
1427:
1428: if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1429: && XVECLEN (newpat, 0) == 2
1430: && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1431: && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1432: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1433: && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1434: && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1435: && asm_noperands (newpat) < 0)
1436: {
1437: newpat = XVECEXP (newpat, 0, 0);
1438: insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1439: }
1440:
1441: else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1442: && XVECLEN (newpat, 0) == 2
1443: && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1444: && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1445: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1446: && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1447: && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1448: && asm_noperands (newpat) < 0)
1449: {
1450: newpat = XVECEXP (newpat, 0, 1);
1451: insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1452: }
1453:
1454: /* If we were combining three insns and the result is a simple SET
1455: with no ASM_OPERANDS that wasn't recognized, try to split it into two
1456: insns. */
1457: if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1458: && asm_noperands (newpat) < 0)
1459: {
1460: rtx *split = find_split_point (&newpat);
1461:
1462: /* If we can split it and use I2DEST, go ahead and see if that
1463: helps things be recognized. Verify that none of the registers
1464: are set between I2 and I3. */
1465: if (split
1466: #ifdef HAVE_cc0
1467: && GET_CODE (i2dest) == REG
1468: #endif
1469: /* We need I2DEST in the proper mode. If it is a hard register
1470: or the only use of a pseudo, we can change its mode. */
1471: && (GET_MODE (*split) == GET_MODE (i2dest)
1472: || GET_MODE (*split) == VOIDmode
1473: || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1474: || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1475: && ! REG_USERVAR_P (i2dest)))
1476: && (next_real_insn (i2) == i3
1477: || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1478: /* We can't overwrite I2DEST if its value is still used by
1479: NEWPAT. */
1480: && ! reg_referenced_p (i2dest, newpat))
1481: {
1482: rtx newdest = i2dest;
1483:
1484: /* Get NEWDEST as a register in the proper mode. We have already
1485: validated that we can do this. */
1486: if (GET_MODE (i2dest) != GET_MODE (*split)
1487: && GET_MODE (*split) != VOIDmode)
1488: {
1489: newdest = gen_rtx (REG, GET_MODE (*split), REGNO (i2dest));
1490:
1491: if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1492: SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1493: }
1494:
1495: /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1496: an ASHIFT. This can occur if it was inside a PLUS and hence
1497: appeared to be a memory address. This is a kludge. */
1498: if (GET_CODE (*split) == MULT
1499: && GET_CODE (XEXP (*split, 1)) == CONST_INT
1500: && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1501: SUBST (*split, gen_rtx_combine (ASHIFT, GET_MODE (*split),
1502: XEXP (*split, 0),
1503: gen_rtx (CONST_INT, VOIDmode, i)));
1504:
1505: #ifdef INSN_SCHEDULING
1506: /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1507: be written as a ZERO_EXTEND. */
1508: if (GET_CODE (*split) == SUBREG
1509: && GET_CODE (SUBREG_REG (*split)) == MEM)
1510: SUBST (*split, gen_rtx_combine (ZERO_EXTEND, GET_MODE (*split),
1511: XEXP (*split, 0)));
1512: #endif
1513:
1514: newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1515: SUBST (*split, newdest);
1516: i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1517: if (i2_code_number >= 0)
1518: insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1519: }
1520: }
1521:
1522: /* Check for a case where we loaded from memory in a narrow mode and
1523: then sign extended it, but we need both registers. In that case,
1524: we have a PARALLEL with both loads from the same memory location.
1525: We can split this into a load from memory followed by a register-register
1526: copy. This saves at least one insn, more if register allocation can
1527: eliminate the copy. */
1528:
1529: else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1530: && GET_CODE (newpat) == PARALLEL
1531: && XVECLEN (newpat, 0) == 2
1532: && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1533: && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1534: && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1535: && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1536: XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1537: && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1538: INSN_CUID (i2))
1539: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1540: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1541: && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1542: SET_SRC (XVECEXP (newpat, 0, 1)))
1543: && ! find_reg_note (i3, REG_UNUSED,
1544: SET_DEST (XVECEXP (newpat, 0, 0))))
1545: {
1546: newi2pat = XVECEXP (newpat, 0, 0);
1547: newpat = XVECEXP (newpat, 0, 1);
1548: SUBST (SET_SRC (newpat),
1549: gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)),
1550: SET_DEST (newi2pat)));
1551: i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1552: if (i2_code_number >= 0)
1553: insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1.1.1.2 ! root 1554:
! 1555: if (insn_code_number >= 0)
! 1556: {
! 1557: rtx insn;
! 1558: rtx link;
! 1559:
! 1560: /* If we will be able to accept this, we have made a change to the
! 1561: destination of I3. This can invalidate a LOG_LINKS pointing
! 1562: to I3. No other part of combine.c makes such a transformation.
! 1563:
! 1564: The new I3 will have a destination that was previously the
! 1565: destination of I1 or I2 and which was used in i2 or I3. Call
! 1566: distribute_links to make a LOG_LINK from the next use of
! 1567: that destination. */
! 1568:
! 1569: PATTERN (i3) = newpat;
! 1570: distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, 0));
! 1571:
! 1572: /* I3 now uses what used to be its destination and which is
! 1573: now I2's destination. That means we need a LOG_LINK from
! 1574: I3 to I2. But we used to have one, so we still will.
! 1575:
! 1576: However, some later insn might be using I2's dest and have
! 1577: a LOG_LINK pointing at I3. We must remove this link.
! 1578: The simplest way to remove the link is to point it at I1,
! 1579: which we know will be a NOTE. */
! 1580:
! 1581: for (insn = NEXT_INSN (i3);
! 1582: insn && GET_CODE (insn) != CODE_LABEL
! 1583: && GET_CODE (PREV_INSN (insn)) != JUMP_INSN;
! 1584: insn = NEXT_INSN (insn))
! 1585: {
! 1586: if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
! 1587: && reg_referenced_p (SET_DEST (newi2pat), PATTERN (insn)))
! 1588: {
! 1589: for (link = LOG_LINKS (insn); link;
! 1590: link = XEXP (link, 1))
! 1591: if (XEXP (link, 0) == i3)
! 1592: XEXP (link, 0) = i1;
! 1593:
! 1594: break;
! 1595: }
! 1596: }
! 1597: }
1.1 root 1598: }
1599:
1600: /* Similarly, check for a case where we have a PARALLEL of two independent
1601: SETs but we started with three insns. In this case, we can do the sets
1602: as two separate insns. This case occurs when some SET allows two
1603: other insns to combine, but the destination of that SET is still live. */
1604:
1605: else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1606: && GET_CODE (newpat) == PARALLEL
1607: && XVECLEN (newpat, 0) == 2
1608: && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1609: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
1610: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
1611: && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1612: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1613: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1614: && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1615: INSN_CUID (i2))
1616: /* Don't pass sets with (USE (MEM ...)) dests to the following. */
1617: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
1618: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
1619: && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1620: XVECEXP (newpat, 0, 0))
1621: && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
1622: XVECEXP (newpat, 0, 1)))
1623: {
1624: newi2pat = XVECEXP (newpat, 0, 1);
1625: newpat = XVECEXP (newpat, 0, 0);
1626:
1627: i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1628: if (i2_code_number >= 0)
1629: insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1630: }
1631:
1632: /* If it still isn't recognized, fail and change things back the way they
1633: were. */
1634: if ((insn_code_number < 0
1635: /* Is the result a reasonable ASM_OPERANDS? */
1636: && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
1637: {
1638: undo_all ();
1639: return 0;
1640: }
1641:
1642: /* If we had to change another insn, make sure it is valid also. */
1643: if (undobuf.other_insn)
1644: {
1645: rtx other_notes = REG_NOTES (undobuf.other_insn);
1646: rtx other_pat = PATTERN (undobuf.other_insn);
1647: rtx new_other_notes;
1648: rtx note, next;
1649:
1650: other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
1651: &new_other_notes);
1652:
1653: if (other_code_number < 0 && ! check_asm_operands (other_pat))
1654: {
1655: undo_all ();
1656: return 0;
1657: }
1658:
1659: PATTERN (undobuf.other_insn) = other_pat;
1660:
1661: /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
1662: are still valid. Then add any non-duplicate notes added by
1663: recog_for_combine. */
1664: for (note = REG_NOTES (undobuf.other_insn); note; note = next)
1665: {
1666: next = XEXP (note, 1);
1667:
1668: if (REG_NOTE_KIND (note) == REG_UNUSED
1669: && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
1670: remove_note (undobuf.other_insn, note);
1671: }
1672:
1673: distribute_notes (new_other_notes, undobuf.other_insn,
1674: undobuf.other_insn, 0, 0, 0);
1675: }
1676:
1677: /* We now know that we can do this combination. Merge the insns and
1678: update the status of registers and LOG_LINKS. */
1679:
1680: {
1681: rtx i3notes, i2notes, i1notes = 0;
1682: rtx i3links, i2links, i1links = 0;
1683: rtx midnotes = 0;
1684: int all_adjacent = (next_real_insn (i2) == i3
1685: && (i1 == 0 || next_real_insn (i1) == i2));
1686: register int regno;
1687: /* Compute which registers we expect to eliminate. */
1688: rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
1689: ? 0 : i2dest);
1690: rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
1691:
1692: /* Get the old REG_NOTES and LOG_LINKS from all our insns and
1693: clear them. */
1694: i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
1695: i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
1696: if (i1)
1697: i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
1698:
1699: /* Ensure that we do not have something that should not be shared but
1700: occurs multiple times in the new insns. Check this by first
1.1.1.2 ! root 1701: resetting all the `used' flags and then copying anything is shared. */
1.1 root 1702:
1703: reset_used_flags (i3notes);
1704: reset_used_flags (i2notes);
1705: reset_used_flags (i1notes);
1706: reset_used_flags (newpat);
1707: reset_used_flags (newi2pat);
1708: if (undobuf.other_insn)
1709: reset_used_flags (PATTERN (undobuf.other_insn));
1710:
1711: i3notes = copy_rtx_if_shared (i3notes);
1712: i2notes = copy_rtx_if_shared (i2notes);
1713: i1notes = copy_rtx_if_shared (i1notes);
1714: newpat = copy_rtx_if_shared (newpat);
1715: newi2pat = copy_rtx_if_shared (newi2pat);
1716: if (undobuf.other_insn)
1717: reset_used_flags (PATTERN (undobuf.other_insn));
1718:
1719: INSN_CODE (i3) = insn_code_number;
1720: PATTERN (i3) = newpat;
1721: if (undobuf.other_insn)
1722: INSN_CODE (undobuf.other_insn) = other_code_number;
1723:
1724: /* We had one special case above where I2 had more than one set and
1725: we replaced a destination of one of those sets with the destination
1726: of I3. In that case, we have to update LOG_LINKS of insns later
1727: in this basic block. Note that this (expensive) case is rare. */
1728:
1729: if (GET_CODE (PATTERN (i2)) == PARALLEL)
1730: for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
1731: if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
1732: && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
1733: && ! find_reg_note (i2, REG_UNUSED,
1734: SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
1735: {
1736: register rtx insn;
1737:
1738: for (insn = NEXT_INSN (i2); insn; insn = NEXT_INSN (insn))
1739: {
1740: if (insn != i3 && GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1741: for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1742: if (XEXP (link, 0) == i2)
1743: XEXP (link, 0) = i3;
1744:
1745: if (GET_CODE (insn) == CODE_LABEL
1746: || GET_CODE (insn) == JUMP_INSN)
1747: break;
1748: }
1749: }
1750:
1751: LOG_LINKS (i3) = 0;
1752: REG_NOTES (i3) = 0;
1753: LOG_LINKS (i2) = 0;
1754: REG_NOTES (i2) = 0;
1755:
1756: if (newi2pat)
1757: {
1758: INSN_CODE (i2) = i2_code_number;
1759: PATTERN (i2) = newi2pat;
1760: }
1761: else
1762: {
1763: PUT_CODE (i2, NOTE);
1764: NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
1765: NOTE_SOURCE_FILE (i2) = 0;
1766: }
1767:
1768: if (i1)
1769: {
1770: LOG_LINKS (i1) = 0;
1771: REG_NOTES (i1) = 0;
1772: PUT_CODE (i1, NOTE);
1773: NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
1774: NOTE_SOURCE_FILE (i1) = 0;
1775: }
1776:
1777: /* Get death notes for everything that is now used in either I3 or
1778: I2 and used to die in a previous insn. */
1779:
1780: move_deaths (newpat, i1 ? INSN_CUID (i1) : INSN_CUID (i2), i3, &midnotes);
1781: if (newi2pat)
1782: move_deaths (newi2pat, INSN_CUID (i1), i2, &midnotes);
1783:
1784: /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
1785: if (i3notes)
1786: distribute_notes (i3notes, i3, i3, newi2pat ? i2 : 0, elim_i2, elim_i1);
1787: if (i2notes)
1788: distribute_notes (i2notes, i2, i3, newi2pat ? i2 : 0, elim_i2, elim_i1);
1789: if (i1notes)
1790: distribute_notes (i1notes, i1, i3, newi2pat ? i2 : 0, elim_i2, elim_i1);
1791: if (midnotes)
1792: distribute_notes (midnotes, 0, i3, newi2pat ? i2 : 0, elim_i2, elim_i1);
1793:
1794: /* Distribute any notes added to I2 or I3 by recog_for_combine. We
1795: know these are REG_UNUSED and want them to go to the desired insn,
1796: so we always pass it as i3. */
1797: if (newi2pat && new_i2_notes)
1798: distribute_notes (new_i2_notes, i2, i2, 0, 0, 0);
1799: if (new_i3_notes)
1800: distribute_notes (new_i3_notes, i3, i3, 0, 0, 0);
1801:
1802: /* If I3DEST was used in I3SRC, it really died in I3. We may need to
1803: put a REG_DEAD note for it somewhere. Similarly for I2 and I1. */
1804: if (i3dest_killed)
1805: distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed, 0),
1806: 0, i3, newi2pat ? i2 : 0, 0, 0);
1807: if (i2dest_in_i2src)
1808: distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, 0),
1809: 0, i3, newi2pat ? i2 : 0, 0, 0);
1810: if (i1dest_in_i1src)
1811: distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, 0),
1812: 0, i3, newi2pat ? i2 : 0, 0, 0);
1813:
1814: distribute_links (i3links);
1815: distribute_links (i2links);
1816: distribute_links (i1links);
1817:
1818: if (GET_CODE (i2dest) == REG)
1819: {
1820: /* The insn that previously set this register doesn't exist, and
1821: this life of the register may not exist either. Show that
1822: we don't know its value any more. If we don't do this and
1823: I2 set the register to a value that depended on its old
1824: contents, we will get confused. If this insn is used, thing
1825: will be set correctly in combine_instructions. */
1826: record_value_for_reg (i2dest, 0, 0);
1827:
1828: /* If the reg formerly set in I2 died only once and that was in I3,
1829: zero its use count so it won't make `reload' do any work. */
1830: if (! added_sets_2 && newi2pat == 0)
1831: {
1832: regno = REGNO (i2dest);
1833: reg_n_sets[regno]--;
1834: if (reg_n_sets[regno] == 0
1835: && ! (basic_block_live_at_start[0][regno / HOST_BITS_PER_INT]
1836: & (1 << (regno % HOST_BITS_PER_INT))))
1837: reg_n_refs[regno] = 0;
1838: }
1839: }
1840:
1841: if (i1 && GET_CODE (i1dest) == REG)
1842: {
1843: record_value_for_reg (i1dest, 0, 0);
1844: regno = REGNO (i1dest);
1845: if (! added_sets_1)
1846: {
1847: reg_n_sets[regno]--;
1848: if (reg_n_sets[regno] == 0
1849: && ! (basic_block_live_at_start[0][regno / HOST_BITS_PER_INT]
1850: & (1 << (regno % HOST_BITS_PER_INT))))
1851: reg_n_refs[regno] = 0;
1852: }
1853: }
1854:
1855: /* If I3 is now an unconditional jump, ensure that it has a
1856: BARRIER following it since it may have initially been a
1857: conditional jump. */
1858:
1859: if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
1860: && GET_CODE (next_nonnote_insn (i3)) != BARRIER)
1861: emit_barrier_after (i3);
1862: }
1863:
1864: combine_successes++;
1865:
1866: return newi2pat ? i2 : i3;
1867: }
1868:
1869: /* Undo all the modifications recorded in undobuf. */
1870:
1871: static void
1872: undo_all ()
1873: {
1874: register int i;
1875: if (undobuf.num_undo > MAX_UNDO)
1876: undobuf.num_undo = MAX_UNDO;
1877: for (i = undobuf.num_undo - 1; i >= 0; i--)
1878: *undobuf.undo[i].where = undobuf.undo[i].old_contents;
1879:
1880: obfree (undobuf.storage);
1881: undobuf.num_undo = 0;
1882: }
1883:
1884: /* Find the innermost point within the rtx at LOC, possibly LOC itself,
1885: where we have an arithmetic expression and return that point.
1886:
1887: try_combine will call this function to see if an insn can be split into
1888: two insns. */
1889:
1890: static rtx *
1891: find_split_point (loc)
1892: rtx *loc;
1893: {
1894: rtx x = *loc;
1895: enum rtx_code code = GET_CODE (x);
1896: rtx *split;
1897: int len = 0, pos, unsignedp;
1898: rtx inner;
1899:
1900: /* First special-case some codes. */
1901: switch (code)
1902: {
1903: case SUBREG:
1904: #ifdef INSN_SCHEDULING
1905: /* If we are making a paradoxical SUBREG invalid, it becomes a split
1906: point. */
1907: if (GET_CODE (SUBREG_REG (x)) == MEM)
1908: return loc;
1909: #endif
1910: return find_split_point (&SUBREG_REG (x));
1911:
1912: #ifdef HAVE_lo_sum
1913: case MEM:
1914: /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
1915: using LO_SUM and HIGH. */
1916: if (GET_CODE (XEXP (x, 0)) == CONST
1917: || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
1918: {
1919: SUBST (XEXP (x, 0),
1920: gen_rtx_combine (LO_SUM, Pmode,
1921: gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
1922: XEXP (x, 0)));
1923: return &XEXP (XEXP (x, 0), 0);
1924: }
1925: break;
1926: #endif
1927:
1928: case SET:
1929: #ifdef HAVE_cc0
1930: /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
1931: ZERO_EXTRACT, the most likely reason why this doesn't match is that
1932: we need to put the operand into a register. So split at that
1933: point. */
1934:
1935: if (SET_DEST (x) == cc0_rtx
1936: && GET_CODE (SET_SRC (x)) != COMPARE
1937: && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
1938: && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
1939: && ! (GET_CODE (SET_SRC (x)) == SUBREG
1940: && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
1941: return &SET_SRC (x);
1942: #endif
1943:
1944: /* See if we can split SET_SRC as it stands. */
1945: split = find_split_point (&SET_SRC (x));
1946: if (split && split != &SET_SRC (x))
1947: return split;
1948:
1949: /* See if this is a bitfield assignment with everything constant. If
1950: so, this is an IOR of an AND, so split it into that. */
1951: if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
1952: && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
1953: <= HOST_BITS_PER_INT)
1954: && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
1955: && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
1956: && GET_CODE (SET_SRC (x)) == CONST_INT
1957: && ((INTVAL (XEXP (SET_DEST (x), 1))
1958: + INTVAL (XEXP (SET_DEST (x), 2)))
1959: <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
1960: && ! side_effects_p (XEXP (SET_DEST (x), 0)))
1961: {
1962: int pos = INTVAL (XEXP (SET_DEST (x), 2));
1963: int len = INTVAL (XEXP (SET_DEST (x), 1));
1964: int src = INTVAL (SET_SRC (x));
1965: rtx dest = XEXP (SET_DEST (x), 0);
1966: enum machine_mode mode = GET_MODE (dest);
1967: unsigned int mask = (1 << len) - 1;
1968:
1969: #if BITS_BIG_ENDIAN
1970: pos = GET_MODE_BITSIZE (mode) - len - pos;
1971: #endif
1972:
1973: if (src == mask)
1974: SUBST (SET_SRC (x),
1975: gen_binary (IOR, mode, dest,
1976: gen_rtx (CONST_INT, VOIDmode, src << pos)));
1977: else
1978: SUBST (SET_SRC (x),
1979: gen_binary (IOR, mode,
1980: gen_binary (AND, mode, dest,
1981: gen_rtx (CONST_INT, VOIDmode,
1982: (~ (mask << pos)
1983: & GET_MODE_MASK (mode)))),
1984: gen_rtx (CONST_INT, VOIDmode, src << pos)));
1985:
1986: SUBST (SET_DEST (x), dest);
1987:
1988: split = find_split_point (&SET_SRC (x));
1989: if (split && split != &SET_SRC (x))
1990: return split;
1991: }
1992:
1993: /* Otherwise, see if this is an operation that we can split into two.
1994: If so, try to split that. */
1995: code = GET_CODE (SET_SRC (x));
1996:
1997: switch (code)
1998: {
1999: case SIGN_EXTEND:
2000: inner = XEXP (SET_SRC (x), 0);
2001: pos = 0;
2002: len = GET_MODE_BITSIZE (GET_MODE (inner));
2003: unsignedp = 0;
2004: break;
2005:
2006: case SIGN_EXTRACT:
2007: case ZERO_EXTRACT:
2008: if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2009: && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2010: {
2011: inner = XEXP (SET_SRC (x), 0);
2012: len = INTVAL (XEXP (SET_SRC (x), 1));
2013: pos = INTVAL (XEXP (SET_SRC (x), 2));
2014:
2015: #if BITS_BIG_ENDIAN
2016: pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2017: #endif
2018: unsignedp = (code == ZERO_EXTRACT);
2019: }
2020: break;
2021: }
2022:
2023: if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2024: {
2025: enum machine_mode mode = GET_MODE (SET_SRC (x));
2026:
2027: if (unsignedp && len < HOST_BITS_PER_INT)
2028: {
2029: SUBST (SET_SRC (x),
2030: gen_rtx_combine
2031: (AND, mode,
2032: gen_rtx_combine (LSHIFTRT, mode,
2033: gen_lowpart_for_combine (mode, inner),
2034: gen_rtx (CONST_INT, VOIDmode, pos)),
2035: gen_rtx (CONST_INT, VOIDmode, (1 << len) - 1)));
2036:
2037: split = find_split_point (&SET_SRC (x));
2038: if (split && split != &SET_SRC (x))
2039: return split;
2040: }
2041: else
2042: {
2043: SUBST (SET_SRC (x),
2044: gen_rtx_combine
2045: (ASHIFTRT, mode,
2046: gen_rtx_combine (ASHIFT, mode,
2047: gen_lowpart_for_combine (mode, inner),
2048: gen_rtx (CONST_INT, VOIDmode,
2049: (GET_MODE_BITSIZE (mode)
2050: - len - pos))),
2051: gen_rtx (CONST_INT, VOIDmode,
2052: GET_MODE_BITSIZE (mode) - len)));
2053:
2054: split = find_split_point (&SET_SRC (x));
2055: if (split && split != &SET_SRC (x))
2056: return split;
2057: }
2058: }
2059:
2060: /* See if this is a simple operation with a constant as the second
2061: operand. It might be that this constant is out of range and hence
2062: could be used as a split point. */
2063: if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2064: || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2065: || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2066: && CONSTANT_P (XEXP (SET_SRC (x), 1))
2067: && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2068: || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2069: && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2070: == 'o'))))
2071: return &XEXP (SET_SRC (x), 1);
2072:
2073: /* Finally, see if this is a simple operation with its first operand
2074: not in a register. The operation might require this operand in a
2075: register, so return it as a split point. We can always do this
2076: because if the first operand were another operation, we would have
2077: already found it as a split point. */
2078: if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2079: || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2080: || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2081: || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2082: && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2083: return &XEXP (SET_SRC (x), 0);
2084:
2085: return 0;
2086:
2087: case AND:
2088: case IOR:
2089: /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2090: it is better to write this as (not (ior A B)) so we can split it.
2091: Similarly for IOR. */
2092: if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2093: {
2094: SUBST (*loc,
2095: gen_rtx_combine (NOT, GET_MODE (x),
2096: gen_rtx_combine (code == IOR ? AND : IOR,
2097: GET_MODE (x),
2098: XEXP (XEXP (x, 0), 0),
2099: XEXP (XEXP (x, 1), 0))));
2100: return find_split_point (loc);
2101: }
2102:
2103: /* Many RISC machines have a large set of logical insns. If the
2104: second operand is a NOT, put it first so we will try to split the
2105: other operand first. */
2106: if (GET_CODE (XEXP (x, 1)) == NOT)
2107: {
2108: rtx tem = XEXP (x, 0);
2109: SUBST (XEXP (x, 0), XEXP (x, 1));
2110: SUBST (XEXP (x, 1), tem);
2111: }
2112: break;
2113: }
2114:
2115: /* Otherwise, select our actions depending on our rtx class. */
2116: switch (GET_RTX_CLASS (code))
2117: {
2118: case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2119: case '3':
2120: split = find_split_point (&XEXP (x, 2));
2121: if (split)
2122: return split;
2123: /* ... fall through ... */
2124: case '2':
2125: case 'c':
2126: case '<':
2127: split = find_split_point (&XEXP (x, 1));
2128: if (split)
2129: return split;
2130: /* ... fall through ... */
2131: case '1':
2132: /* Some machines have (and (shift ...) ...) insns. If X is not
2133: an AND, but XEXP (X, 0) is, use it as our split point. */
2134: if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2135: return &XEXP (x, 0);
2136:
2137: split = find_split_point (&XEXP (x, 0));
2138: if (split)
2139: return split;
2140: return loc;
2141: }
2142:
2143: /* Otherwise, we don't have a split point. */
2144: return 0;
2145: }
2146:
2147: /* Throughout X, replace FROM with TO, and return the result.
2148: The result is TO if X is FROM;
2149: otherwise the result is X, but its contents may have been modified.
2150: If they were modified, a record was made in undobuf so that
2151: undo_all will (among other things) return X to its original state.
2152:
2153: If the number of changes necessary is too much to record to undo,
2154: the excess changes are not made, so the result is invalid.
2155: The changes already made can still be undone.
2156: undobuf.num_undo is incremented for such changes, so by testing that
2157: the caller can tell whether the result is valid.
2158:
2159: `n_occurrences' is incremented each time FROM is replaced.
2160:
2161: IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2162:
1.1.1.2 ! root 2163: UNIQUE_COPY is non-zero if each substitution must be unique. We do this
1.1 root 2164: by copying if `n_occurrences' is non-zero. */
2165:
2166: static rtx
2167: subst (x, from, to, in_dest, unique_copy)
2168: register rtx x, from, to;
2169: int in_dest;
2170: int unique_copy;
2171: {
2172: register char *fmt;
2173: register int len, i;
2174: register enum rtx_code code = GET_CODE (x), orig_code = code;
2175: rtx temp;
2176: enum machine_mode mode = GET_MODE (x);
2177: enum machine_mode op0_mode = VOIDmode;
2178: rtx other_insn;
2179: rtx *cc_use;
2180: int n_restarts = 0;
2181:
2182: /* FAKE_EXTEND_SAFE_P (MODE, FROM) is 1 if (subreg:MODE FROM 0) is a safe
2183: replacement for (zero_extend:MODE FROM) or (sign_extend:MODE FROM).
2184: If it is 0, that cannot be done. We can now do this for any MEM
2185: because (SUBREG (MEM...)) is guaranteed to cause the MEM to be reloaded.
2186: If not for that, MEM's would very rarely be safe. */
2187:
2188: /* Reject MODEs bigger than a word, because we might not be able
2189: to reference a two-register group starting with an arbitrary register
2190: (and currently gen_lowpart might crash for a SUBREG). */
2191:
2192: #define FAKE_EXTEND_SAFE_P(MODE, FROM) \
2193: (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)
2194:
2195: /* Two expressions are equal if they are identical copies of a shared
2196: RTX or if they are both registers with the same register number
2197: and mode. */
2198:
2199: #define COMBINE_RTX_EQUAL_P(X,Y) \
2200: ((X) == (Y) \
2201: || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2202: && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2203:
2204: if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2205: {
2206: n_occurrences++;
2207: return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2208: }
2209:
2210: /* If X and FROM are the same register but different modes, they will
2211: not have been seen as equal above. However, flow.c will make a
2212: LOG_LINKS entry for that case. If we do nothing, we will try to
2213: rerecognize our original insn and, when it succeeds, we will
2214: delete the feeding insn, which is incorrect.
2215:
2216: So force this insn not to match in this (rare) case. */
2217: if (! in_dest && code == REG && GET_CODE (from) == REG
2218: && REGNO (x) == REGNO (from))
2219: return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2220:
2221: /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2222: of which may contain things that can be combined. */
2223: if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2224: return x;
2225:
2226: /* It is possible to have a subexpression appear twice in the insn.
2227: Suppose that FROM is a register that appears within TO.
2228: Then, after that subexpression has been scanned once by `subst',
2229: the second time it is scanned, TO may be found. If we were
2230: to scan TO here, we would find FROM within it and create a
2231: self-referent rtl structure which is completely wrong. */
2232: if (COMBINE_RTX_EQUAL_P (x, to))
2233: return to;
2234:
2235: len = GET_RTX_LENGTH (code);
2236: fmt = GET_RTX_FORMAT (code);
2237:
2238: /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2239: set up to skip this common case. All other cases where we want to
2240: suppress replacing something inside a SET_SRC are handled via the
2241: IN_DEST operand. */
2242: if (code == SET
2243: && (GET_CODE (SET_DEST (x)) == REG
2244: || GET_CODE (SET_DEST (x)) == CC0
2245: || GET_CODE (SET_DEST (x)) == PC))
2246: fmt = "ie";
2247:
2248: /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a constant. */
2249: if (fmt[0] == 'e')
2250: op0_mode = GET_MODE (XEXP (x, 0));
2251:
2252: for (i = 0; i < len; i++)
2253: {
2254: if (fmt[i] == 'E')
2255: {
2256: register int j;
2257: for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2258: {
2259: register rtx new;
2260: if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
2261: {
2262: new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2263: n_occurrences++;
2264: }
2265: else
2266: {
2267: new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
2268:
2269: /* If this substitution failed, this whole thing fails. */
2270: if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2271: return new;
2272: }
2273:
2274: SUBST (XVECEXP (x, i, j), new);
2275: }
2276: }
2277: else if (fmt[i] == 'e')
2278: {
2279: register rtx new;
2280:
2281: if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
2282: {
2283: new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2284: n_occurrences++;
2285: }
2286: else
2287: /* If we are in a SET_DEST, suppress most cases unless we
2288: have gone inside a MEM, in which case we want to
2289: simplify the address. We assume here that things that
2290: are actually part of the destination have their inner
2291: parts in the first expression. This is true for SUBREG,
2292: STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
2293: things aside from REG and MEM that should appear in a
2294: SET_DEST. */
2295: new = subst (XEXP (x, i), from, to,
2296: (((in_dest
2297: && (code == SUBREG || code == STRICT_LOW_PART
2298: || code == ZERO_EXTRACT))
2299: || code == SET)
2300: && i == 0), unique_copy);
2301:
2302: /* If we found that we will have to reject this combination,
2303: indicate that by returning the CLOBBER ourselves, rather than
2304: an expression containing it. This will speed things up as
2305: well as prevent accidents where two CLOBBERs are considered
2306: to be equal, thus producing an incorrect simplification. */
2307:
2308: if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2309: return new;
2310:
2311: SUBST (XEXP (x, i), new);
2312: }
2313: }
2314:
2315: /* If this is a commutative operation, put a constant last and a complex
2316: expression first. We don't need to do this for comparisons here. */
2317: if (GET_RTX_CLASS (code) == 'c'
2318: && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
2319: || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
2320: && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
2321: || (GET_CODE (XEXP (x, 0)) == SUBREG
2322: && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
2323: && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
2324: {
2325: temp = XEXP (x, 0);
2326: SUBST (XEXP (x, 0), XEXP (x, 1));
2327: SUBST (XEXP (x, 1), temp);
2328: }
2329:
2330: /* Try to fold this expression in case we have constants that weren't
2331: present before. */
2332: temp = 0;
2333: switch (GET_RTX_CLASS (code))
2334: {
2335: case '1':
2336: temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
2337: break;
2338: case '<':
2339: temp = simplify_relational_operation (code, op0_mode,
2340: XEXP (x, 0), XEXP (x, 1));
2341: break;
2342: case 'c':
2343: case '2':
2344: temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
2345: break;
2346: case 'b':
2347: case '3':
2348: temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
2349: XEXP (x, 1), XEXP (x, 2));
2350: break;
2351: }
2352:
2353: if (temp)
2354: x = temp;
2355:
2356: /* We come back to here if we have replaced the expression with one of
2357: a different code and it is likely that further simplification will be
2358: possible. */
2359:
2360: restart:
2361:
2362: /* If we have restarted more than 4 times, we are probably looping, so
2363: give up. */
2364: if (++n_restarts > 4)
2365: return x;
2366:
2367: code = GET_CODE (x);
2368:
2369: /* First see if we can apply the inverse distributive law. */
2370: if (code == PLUS || code == MINUS || code == IOR || code == XOR)
2371: {
2372: x = apply_distributive_law (x);
2373: code = GET_CODE (x);
2374: }
2375:
2376: /* If CODE is an associative operation not otherwise handled, see if we
2377: can associate some operands. This can win if they are constants or
2378: if they are logically related (i.e. (a & b) & a. */
2379: if ((code == PLUS || code == MINUS
2380: || code == MULT || code == AND || code == IOR || code == XOR
2381: || code == DIV || code == UDIV
2382: || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
2383: && GET_MODE_CLASS (mode) == MODE_INT)
2384: {
2385: if (GET_CODE (XEXP (x, 0)) == code)
2386: {
2387: rtx other = XEXP (XEXP (x, 0), 0);
2388: rtx inner_op0 = XEXP (XEXP (x, 0), 1);
2389: rtx inner_op1 = XEXP (x, 1);
2390: rtx inner;
2391:
2392: /* Make sure we pass the constant operand if any as the second
2393: one if this is a commutative operation. */
2394: if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
2395: {
2396: rtx tem = inner_op0;
2397: inner_op0 = inner_op1;
2398: inner_op1 = tem;
2399: }
2400: inner = simplify_binary_operation (code == MINUS ? PLUS
2401: : code == DIV ? MULT
2402: : code == UDIV ? MULT
2403: : code,
2404: mode, inner_op0, inner_op1);
2405:
2406: /* For commutative operations, try the other pair if that one
2407: didn't simplify. */
2408: if (inner == 0 && GET_RTX_CLASS (code) == 'c')
2409: {
2410: other = XEXP (XEXP (x, 0), 1);
2411: inner = simplify_binary_operation (code, mode,
2412: XEXP (XEXP (x, 0), 0),
2413: XEXP (x, 1));
2414: }
2415:
2416: if (inner)
2417: {
2418: x = gen_binary (code, mode, other, inner);
2419: goto restart;
2420:
2421: }
2422: }
2423: }
2424:
2425: /* A little bit of algebraic simplification here. */
2426: switch (code)
2427: {
2428: case MEM:
2429: /* Ensure that our address has any ASHIFTs converted to MULT in case
2430: address-recognizing predicates are called later. */
2431: temp = make_compound_operation (XEXP (x, 0), MEM);
2432: SUBST (XEXP (x, 0), temp);
2433: break;
2434:
2435: case SUBREG:
2436: /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
2437: is paradoxical. If we can't do that safely, then it becomes
2438: something nonsensical so that this combination won't take place. */
2439:
2440: if (GET_CODE (SUBREG_REG (x)) == MEM
2441: && (GET_MODE_SIZE (mode)
2442: <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
2443: {
2444: rtx inner = SUBREG_REG (x);
2445: int endian_offset = 0;
2446: /* Don't change the mode of the MEM
2447: if that would change the meaning of the address. */
2448: if (MEM_VOLATILE_P (SUBREG_REG (x))
2449: || mode_dependent_address_p (XEXP (inner, 0)))
2450: return gen_rtx (CLOBBER, mode, const0_rtx);
2451:
2452: #if BYTES_BIG_ENDIAN
2453: if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
2454: endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
2455: if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
2456: endian_offset -= UNITS_PER_WORD - GET_MODE_SIZE (GET_MODE (inner));
2457: #endif
2458: /* Note if the plus_constant doesn't make a valid address
2459: then this combination won't be accepted. */
2460: x = gen_rtx (MEM, mode,
2461: plus_constant (XEXP (inner, 0),
2462: (SUBREG_WORD (x) * UNITS_PER_WORD
2463: + endian_offset)));
2464: MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
2465: RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
2466: MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
2467: return x;
2468: }
2469:
2470: /* If we are in a SET_DEST, these other cases can't apply. */
2471: if (in_dest)
2472: return x;
2473:
2474: /* Changing mode twice with SUBREG => just change it once,
2475: or not at all if changing back to starting mode. */
2476: if (GET_CODE (SUBREG_REG (x)) == SUBREG)
2477: {
2478: if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
2479: && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
2480: return SUBREG_REG (SUBREG_REG (x));
2481:
2482: SUBST_INT (SUBREG_WORD (x),
2483: SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
2484: SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
2485: }
2486:
2487: /* SUBREG of a hard register => just change the register number
2488: and/or mode. If the hard register is not valid in that mode,
2489: suppress this combination. */
2490:
2491: if (GET_CODE (SUBREG_REG (x)) == REG
2492: && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER)
2493: {
2494: if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
2495: mode))
2496: return gen_rtx (REG, mode,
2497: REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
2498: else
2499: return gen_rtx (CLOBBER, mode, const0_rtx);
2500: }
2501:
2502: /* For a constant, try to pick up the part we want. Handle a full
2503: word and low-order part. */
2504:
2505: if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
2506: && GET_MODE_SIZE (mode) == UNITS_PER_WORD
2507: && GET_MODE_CLASS (mode) == MODE_INT)
2508: {
2509: temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
2510: 0, op0_mode);
2511: if (temp)
2512: return temp;
2513: }
2514:
2515: if (CONSTANT_P (SUBREG_REG (x)) && subreg_lowpart_p (x))
2516: return gen_lowpart_for_combine (mode, SUBREG_REG (x));
2517:
2518: /* If we are narrowing the object, we need to see if we can simplify
2519: the expression for the object knowing that we only need the
2520: low-order bits. We do this by computing an AND of the object
2521: with only the bits we care about. That will produce any needed
2522: simplifications. If the resulting computation is just the
2523: AND with the significant bits, our operand is the first operand
2524: of the AND. Otherwise, it is the resulting expression. */
2525: if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
2526: && subreg_lowpart_p (x)
2527: && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= HOST_BITS_PER_INT)
2528: {
2529: temp = simplify_and_const_int (0, GET_MODE (SUBREG_REG (x)),
2530: SUBREG_REG (x), GET_MODE_MASK (mode));
2531: if (GET_CODE (temp) == AND && GET_CODE (XEXP (temp, 1)) == CONST_INT
2532: && INTVAL (XEXP (temp, 1)) == GET_MODE_MASK (mode))
2533: temp = XEXP (temp, 0);
2534: return gen_lowpart_for_combine (mode, temp);
2535: }
2536:
2537: break;
2538:
2539: case NOT:
2540: /* (not (plus X -1)) can become (neg X). */
2541: if (GET_CODE (XEXP (x, 0)) == PLUS
2542: && XEXP (XEXP (x, 0), 1) == constm1_rtx)
2543: {
2544: x = gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
2545: goto restart;
2546: }
2547:
2548: /* Similarly, (not (neg X)) is (plus X -1). */
2549: if (GET_CODE (XEXP (x, 0)) == NEG)
2550: {
2551: x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
2552: goto restart;
2553: }
2554:
2555: /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
2556: other than 1, but that is not valid. We could do a similar
2557: simplification for (not (lshiftrt C X)) where C is just the sign bit,
2558: but this doesn't seem common enough to bother with. */
2559: if (GET_CODE (XEXP (x, 0)) == ASHIFT
2560: && XEXP (XEXP (x, 0), 0) == const1_rtx)
2561: {
2562: x = gen_rtx (ROTATE, mode, gen_unary (NOT, mode, const1_rtx),
2563: XEXP (XEXP (x, 0), 1));
2564: goto restart;
2565: }
2566:
2567: if (GET_CODE (XEXP (x, 0)) == SUBREG
2568: && subreg_lowpart_p (XEXP (x, 0))
2569: && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
2570: < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
2571: && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
2572: && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
2573: {
2574: enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
2575:
2576: x = gen_rtx (ROTATE, inner_mode,
2577: gen_unary (NOT, inner_mode, const1_rtx),
2578: XEXP (SUBREG_REG (XEXP (x, 0)), 1));
2579: x = gen_lowpart_for_combine (mode, x);
2580: goto restart;
2581: }
2582:
2583: #if STORE_FLAG_VALUE == -1
2584: /* (not (comparison foo bar)) can be done by reversing the comparison
2585: code if valid. */
2586: if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
2587: && reversible_comparison_p (XEXP (x, 0)))
2588: return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
2589: mode, XEXP (XEXP (x, 0), 0),
2590: XEXP (XEXP (x, 0), 1));
2591: #endif
2592:
2593: /* Apply De Morgan's laws to reduce number of patterns for machines
2594: with negating logical insns (and-not, nand, etc.). If result has
2595: only one NOT, put it first, since that is how the patterns are
2596: coded. */
2597:
2598: if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
2599: {
2600: rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
2601:
2602: if (GET_CODE (in1) == NOT)
2603: in1 = XEXP (in1, 0);
2604: else
2605: in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
2606:
2607: if (GET_CODE (in2) == NOT)
2608: in2 = XEXP (in2, 0);
2609: else if (GET_CODE (in2) == CONST_INT
2610: && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT)
2611: in2 = gen_rtx (CONST_INT, VOIDmode,
2612: GET_MODE_MASK (mode) & ~ INTVAL (in2));
2613: else
2614: in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
2615:
2616: if (GET_CODE (in2) == NOT)
2617: {
2618: rtx tem = in2;
2619: in2 = in1; in1 = tem;
2620: }
2621:
2622: x = gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
2623: mode, in1, in2);
2624: goto restart;
2625: }
2626: break;
2627:
2628: case NEG:
2629: /* (neg (plus X 1)) can become (not X). */
2630: if (GET_CODE (XEXP (x, 0)) == PLUS
2631: && XEXP (XEXP (x, 0), 1) == const1_rtx)
2632: {
2633: x = gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
2634: goto restart;
2635: }
2636:
2637: /* Similarly, (neg (not X)) is (plus X 1). */
2638: if (GET_CODE (XEXP (x, 0)) == NOT)
2639: {
2640: x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), const1_rtx);
2641: goto restart;
2642: }
2643:
2644: /* (neg (abs X)) is X if X is a value known to be either -1 or 0. */
2645: if (GET_CODE (XEXP (x, 0)) == ABS
2646: && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTRACT
2647: && XEXP (XEXP (XEXP (x, 0), 0), 1) == const1_rtx)
2648: || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFTRT
2649: && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
2650: && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
2651: == GET_MODE_BITSIZE (mode) - 1))
2652: || ((temp = get_last_value (XEXP (XEXP (x, 0), 0))) != 0
2653: && ((GET_CODE (temp) == SIGN_EXTRACT
2654: && XEXP (temp, 1) == const1_rtx)
2655: || (GET_CODE (temp) == ASHIFTRT
2656: && GET_CODE (XEXP (temp, 1)) == CONST_INT
2657: && (INTVAL (XEXP (temp, 1))
2658: == GET_MODE_BITSIZE (mode) - 1))))))
2659: return XEXP (XEXP (x, 0), 0);
2660:
2661: /* (neg (minus X Y)) can become (minus Y X). */
2662: if (GET_CODE (XEXP (x, 0)) == MINUS
2663: && (GET_MODE_CLASS (mode) != MODE_FLOAT
2664: /* x-y != -(y-x) with IEEE floating point. */
2665: || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT))
2666: {
2667: x = gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
2668: XEXP (XEXP (x, 0), 0));
2669: goto restart;
2670: }
2671:
2672: /* NEG commutes with ASHIFT since it is multiplication. Only do this
2673: if we can then eliminate the NEG (e.g.,
2674: if the operand is a constant). */
2675:
2676: if (GET_CODE (XEXP (x, 0)) == ASHIFT)
2677: {
2678: temp = simplify_unary_operation (NEG, mode,
2679: XEXP (XEXP (x, 0), 0), mode);
2680: if (temp)
2681: {
2682: SUBST (XEXP (XEXP (x, 0), 0), temp);
2683: return XEXP (x, 0);
2684: }
2685: }
2686:
2687: temp = expand_compound_operation (XEXP (x, 0));
2688:
2689: /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
2690: replaced by (lshiftrt X C). This will convert
2691: (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
2692:
2693: if (GET_CODE (temp) == ASHIFTRT
2694: && GET_CODE (XEXP (temp, 1)) == CONST_INT
2695: && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
2696: {
2697: x = simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
2698: INTVAL (XEXP (temp, 1)));
2699: goto restart;
2700: }
2701:
2702: /* If X has only a single bit significant, say, bit I, convert
2703: (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
2704: MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
2705: (sign_extract X 1 Y). But only do this if TEMP isn't a register
2706: or a SUBREG of one since we'd be making the expression more
2707: complex if it was just a register. */
2708:
2709: if (GET_CODE (temp) != REG
2710: && ! (GET_CODE (temp) == SUBREG
2711: && GET_CODE (SUBREG_REG (temp)) == REG)
2712: && (i = exact_log2 (significant_bits (temp, mode))) >= 0)
2713: {
2714: rtx temp1 = simplify_shift_const
2715: (0, ASHIFTRT, mode,
2716: simplify_shift_const (0, ASHIFT, mode, temp,
2717: GET_MODE_BITSIZE (mode) - 1 - i),
2718: GET_MODE_BITSIZE (mode) - 1 - i);
2719:
2720: /* If all we did was surround TEMP with the two shifts, we
2721: haven't improved anything, so don't use it. Otherwise,
2722: we are better off with TEMP1. */
2723: if (GET_CODE (temp1) != ASHIFTRT
2724: || GET_CODE (XEXP (temp1, 0)) != ASHIFT
2725: || XEXP (XEXP (temp1, 0), 0) != temp)
2726: {
2727: x = temp1;
2728: goto restart;
2729: }
2730: }
2731: break;
2732:
2733: case FLOAT_TRUNCATE:
2734: /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
2735: if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
2736: && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
2737: return XEXP (XEXP (x, 0), 0);
2738: break;
2739:
2740: #ifdef HAVE_cc0
2741: case COMPARE:
2742: /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
2743: using cc0, in which case we want to leave it as a COMPARE
2744: so we can distinguish it from a register-register-copy. */
2745: if (XEXP (x, 1) == const0_rtx)
2746: return XEXP (x, 0);
2747:
2748: /* In IEEE floating point, x-0 is not the same as x. */
2749: if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
2750: || GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) == MODE_INT)
2751: && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
2752: return XEXP (x, 0);
2753: break;
2754: #endif
2755:
2756: case CONST:
2757: /* (const (const X)) can become (const X). Do it this way rather than
2758: returning the inner CONST since CONST can be shared with a
2759: REG_EQUAL note. */
2760: if (GET_CODE (XEXP (x, 0)) == CONST)
2761: SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
2762: break;
2763:
2764: #ifdef HAVE_lo_sum
2765: case LO_SUM:
2766: /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
2767: can add in an offset. find_split_point will split this address up
2768: again if it doesn't match. */
2769: if (GET_CODE (XEXP (x, 0)) == HIGH
2770: && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
2771: return XEXP (x, 1);
2772: break;
2773: #endif
2774:
2775: case PLUS:
2776: /* If we have (plus (plus (A const) B)), associate it so that CONST is
2777: outermost. That's because that's the way indexed addresses are
2778: supposed to appear. This code used to check many more cases, but
2779: they are now checked elsewhere. */
2780: if (GET_CODE (XEXP (x, 0)) == PLUS
2781: && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
2782: return gen_binary (PLUS, mode,
2783: gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
2784: XEXP (x, 1)),
2785: XEXP (XEXP (x, 0), 1));
2786:
2787: /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
2788: when c is (const_int (pow2 + 1) / 2) is a sign extension of a
2789: bit-field and can be replaced by either a sign_extend or a
2790: sign_extract. The `and' may be a zero_extend. */
2791: if (GET_CODE (XEXP (x, 0)) == XOR
2792: && GET_CODE (XEXP (x, 1)) == CONST_INT
2793: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2794: && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
2795: && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
2796: && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT
2797: && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
2798: && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
2799: && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
2800: == (1 << (i + 1)) - 1))
2801: || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
2802: && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
2803: == i + 1))))
2804: {
2805: x = simplify_shift_const
2806: (0, ASHIFTRT, mode,
2807: simplify_shift_const (0, ASHIFT, mode,
2808: XEXP (XEXP (XEXP (x, 0), 0), 0),
2809: GET_MODE_BITSIZE (mode) - (i + 1)),
2810: GET_MODE_BITSIZE (mode) - (i + 1));
2811: goto restart;
2812: }
2813:
2814: /* If only the low-order bit of X is significant, (plus x -1)
2815: can become (ashiftrt (ashift (xor x 1) C) C) where C is
2816: the bitsize of the mode - 1. This allows simplification of
2817: "a = (b & 8) == 0;" */
2818: if (XEXP (x, 1) == constm1_rtx
2819: && GET_CODE (XEXP (x, 0)) != REG
2820: && ! (GET_CODE (XEXP (x,0)) == SUBREG
2821: && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
2822: && significant_bits (XEXP (x, 0), mode) == 1)
2823: {
2824: x = simplify_shift_const
2825: (0, ASHIFTRT, mode,
2826: simplify_shift_const (0, ASHIFT, mode,
2827: gen_rtx_combine (XOR, mode,
2828: XEXP (x, 0), const1_rtx),
2829: GET_MODE_BITSIZE (mode) - 1),
2830: GET_MODE_BITSIZE (mode) - 1);
2831: goto restart;
2832: }
2833: break;
2834:
2835: case MINUS:
2836: /* (minus <foo> (and <foo> (const_int -pow2))) becomes
2837: (and <foo> (const_int pow2-1)) */
2838: if (GET_CODE (XEXP (x, 1)) == AND
2839: && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
2840: && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
2841: && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
2842: {
2843: x = simplify_and_const_int (0, mode, XEXP (x, 0),
2844: - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
2845: goto restart;
2846: }
2847: break;
2848:
2849: case MULT:
2850: /* If we have (mult (plus A B) C), apply the distributive law and then
2851: the inverse distributive law to see if things simplify. This
2852: occurs mostly in addresses, often when unrolling loops. */
2853:
2854: if (GET_CODE (XEXP (x, 0)) == PLUS)
2855: {
2856: x = apply_distributive_law
2857: (gen_binary (PLUS, mode,
2858: gen_binary (MULT, mode,
2859: XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
2860: gen_binary (MULT, mode,
2861: XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
2862:
2863: if (GET_CODE (x) != MULT)
2864: goto restart;
2865: }
2866:
2867: /* If this is multiplication by a power of two and its first operand is
2868: a shift, treat the multiply as a shift to allow the shifts to
2869: possibly combine. */
2870: if (GET_CODE (XEXP (x, 1)) == CONST_INT
2871: && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
2872: && (GET_CODE (XEXP (x, 0)) == ASHIFT
2873: || GET_CODE (XEXP (x, 0)) == LSHIFTRT
2874: || GET_CODE (XEXP (x, 0)) == ASHIFTRT
2875: || GET_CODE (XEXP (x, 0)) == ROTATE
2876: || GET_CODE (XEXP (x, 0)) == ROTATERT))
2877: {
2878: x = simplify_shift_const (0, ASHIFT, mode, XEXP (x, 0), i);
2879: goto restart;
2880: }
2881:
2882: /* Convert (mult (ashift (const_int 1) A) B) to (ashift B A). */
2883: if (GET_CODE (XEXP (x, 0)) == ASHIFT
2884: && XEXP (XEXP (x, 0), 0) == const1_rtx)
2885: return gen_rtx_combine (ASHIFT, mode, XEXP (x, 1),
2886: XEXP (XEXP (x, 0), 1));
2887: break;
2888:
2889: case UDIV:
2890: /* If this is a divide by a power of two, treat it as a shift if
2891: its first operand is a shift. */
2892: if (GET_CODE (XEXP (x, 1)) == CONST_INT
2893: && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
2894: && (GET_CODE (XEXP (x, 0)) == ASHIFT
2895: || GET_CODE (XEXP (x, 0)) == LSHIFTRT
2896: || GET_CODE (XEXP (x, 0)) == ASHIFTRT
2897: || GET_CODE (XEXP (x, 0)) == ROTATE
2898: || GET_CODE (XEXP (x, 0)) == ROTATERT))
2899: {
2900: x = simplify_shift_const (0, LSHIFTRT, mode, XEXP (x, 0), i);
2901: goto restart;
2902: }
2903: break;
2904:
2905: case EQ: case NE:
2906: case GT: case GTU: case GE: case GEU:
2907: case LT: case LTU: case LE: case LEU:
2908: /* If the first operand is a condition code, we can't do anything
2909: with it. */
2910: if (GET_CODE (XEXP (x, 0)) == COMPARE
2911: || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
2912: #ifdef HAVE_cc0
2913: && XEXP (x, 0) != cc0_rtx
2914: #endif
2915: ))
2916: {
2917: rtx op0 = XEXP (x, 0);
2918: rtx op1 = XEXP (x, 1);
2919: enum rtx_code new_code;
2920:
2921: if (GET_CODE (op0) == COMPARE)
2922: op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
2923:
2924: /* Simplify our comparison, if possible. */
2925: new_code = simplify_comparison (code, &op0, &op1);
2926:
2927: #if STORE_FLAG_VALUE == 1
2928: /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
2929: if only the low-order bit is significant in X (such as when
2930: X is a ZERO_EXTRACT of one bit. Similarly, we can convert
2931: EQ to (xor X 1). */
2932: if (new_code == NE && mode != VOIDmode
2933: && op1 == const0_rtx
2934: && significant_bits (op0, GET_MODE (op0)) == 1)
2935: return gen_lowpart_for_combine (mode, op0);
2936: else if (new_code == EQ && mode != VOIDmode
2937: && op1 == const0_rtx
2938: && significant_bits (op0, GET_MODE (op0)) == 1)
2939: return gen_rtx_combine (XOR, mode,
2940: gen_lowpart_for_combine (mode, op0),
2941: const1_rtx);
2942: #endif
2943:
2944: #if STORE_FLAG_VALUE == -1
2945: /* If STORE_FLAG_VALUE is -1, we can convert (ne x 0)
2946: to (neg x) if only the low-order bit of X is significant.
2947: This converts (ne (zero_extract X 1 Y) 0) to
2948: (sign_extract X 1 Y). */
2949: if (new_code == NE && mode != VOIDmode
2950: && op1 == const0_rtx
2951: && significant_bits (op0, GET_MODE (op0)) == 1)
2952: {
2953: x = gen_rtx_combine (NEG, mode,
2954: gen_lowpart_for_combine (mode, op0));
2955: goto restart;
2956: }
2957: #endif
2958:
2959: /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
2960: one significant bit, we can convert (ne x 0) to (ashift x c)
2961: where C puts the bit in the sign bit. Remove any AND with
2962: STORE_FLAG_VALUE when we are done, since we are only going to
2963: test the sign bit. */
2964: if (new_code == NE && mode != VOIDmode
2965: && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT
2966: && STORE_FLAG_VALUE == 1 << (GET_MODE_BITSIZE (mode) - 1)
2967: && op1 == const0_rtx
2968: && mode == GET_MODE (op0)
2969: && (i = exact_log2 (significant_bits (op0, GET_MODE (op0)))) >= 0)
2970: {
2971: x = simplify_shift_const (0, ASHIFT, mode, op0,
2972: GET_MODE_BITSIZE (mode) - 1 - i);
2973: if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
2974: return XEXP (x, 0);
2975: else
2976: return x;
2977: }
2978:
2979: /* If the code changed, return a whole new comparison. */
2980: if (new_code != code)
2981: return gen_rtx_combine (new_code, mode, op0, op1);
2982:
2983: /* Otherwise, keep this operation, but maybe change its operands.
2984: This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
2985: SUBST (XEXP (x, 0), op0);
2986: SUBST (XEXP (x, 1), op1);
2987: }
2988: break;
2989:
2990: case IF_THEN_ELSE:
2991: /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
2992: reversed, do so to avoid needing two sets of patterns for
2993: subtract-and-branch insns. */
2994: if (XEXP (x, 1) == pc_rtx && reversible_comparison_p (XEXP (x, 0)))
2995: {
2996: SUBST (XEXP (x, 0),
2997: gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
2998: GET_MODE (XEXP (x, 0)),
2999: XEXP (XEXP (x, 0), 0),
3000: XEXP (XEXP (x, 0), 1)));
3001: SUBST (XEXP (x, 1), XEXP (x, 2));
3002: SUBST (XEXP (x, 2), pc_rtx);
3003: }
3004: break;
3005:
3006: case ZERO_EXTRACT:
3007: case SIGN_EXTRACT:
3008: case ZERO_EXTEND:
3009: case SIGN_EXTEND:
3010: /* If we are processing SET_DEST, we are done. */
3011: if (in_dest)
3012: return x;
3013:
3014: x = expand_compound_operation (x);
3015: if (GET_CODE (x) != code)
3016: goto restart;
3017: break;
3018:
3019: case SET:
3020: /* (set (pc) (return)) gets written as (return). */
3021: if (GET_CODE (SET_DEST (x)) == PC && GET_CODE (SET_SRC (x)) == RETURN)
3022: return SET_SRC (x);
3023:
3024: /* Convert this into a field assignment operation, if possible. */
3025: x = make_field_assignment (x);
3026:
3027: /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some
3028: operation, and X being a REG or (subreg (reg)), we may be able to
3029: convert this to (set (subreg:m2 x) (op)).
3030:
3031: We can always do this if M1 is narrower than M2 because that
3032: means that we only care about the low bits of the result.
3033:
3034: However, on most machines (those with BYTE_LOADS_ZERO_EXTEND
3035: not defined), we cannot perform a narrower operation that
3036: requested since the high-order bits will be undefined. On
3037: machine where BYTE_LOADS_ZERO_EXTEND are defined, however, this
3038: transformation is safe as long as M1 and M2 have the same number
3039: of words. */
3040:
3041: if (GET_CODE (SET_SRC (x)) == SUBREG
3042: && subreg_lowpart_p (SET_SRC (x))
3043: && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) != 'o'
3044: && (((GET_MODE_SIZE (GET_MODE (SET_SRC (x))) + (UNITS_PER_WORD - 1))
3045: / UNITS_PER_WORD)
3046: == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x))))
3047: + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
3048: #ifndef BYTE_LOADS_ZERO_EXTEND
3049: && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
3050: < GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
3051: #endif
3052: && (GET_CODE (SET_DEST (x)) == REG
3053: || (GET_CODE (SET_DEST (x)) == SUBREG
3054: && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG)))
3055: {
3056: /* Get the object that will be the SUBREG_REG of the
3057: SUBREG we are making. Note that SUBREG_WORD will always
3058: be zero because this will either be a paradoxical SUBREG
3059: or a SUBREG with the same number of words on the outside and
3060: inside. */
3061: rtx object = (GET_CODE (SET_DEST (x)) == REG ? SET_DEST (x)
3062: : SUBREG_REG (SET_DEST (x)));
3063:
3064: SUBST (SET_DEST (x),
3065: gen_rtx (SUBREG, GET_MODE (SUBREG_REG (SET_SRC (x))),
3066: object, 0));
3067: SUBST (SET_SRC (x), SUBREG_REG (SET_SRC (x)));
3068: }
3069:
3070: /* If we are setting CC0 or if the source is a COMPARE, look for the
3071: use of the comparison result and try to simplify it unless we already
3072: have used undobuf.other_insn. */
3073: if ((GET_CODE (SET_SRC (x)) == COMPARE
3074: #ifdef HAVE_cc0
3075: || SET_DEST (x) == cc0_rtx
3076: #endif
3077: )
3078: && (cc_use = find_single_use (SET_DEST (x), subst_insn,
3079: &other_insn)) != 0
3080: && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
3081: && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
3082: && XEXP (*cc_use, 0) == SET_DEST (x))
3083: {
3084: enum rtx_code old_code = GET_CODE (*cc_use);
3085: enum rtx_code new_code;
3086: rtx op0, op1;
3087: int other_changed = 0;
3088: enum machine_mode compare_mode = GET_MODE (SET_DEST (x));
3089:
3090: if (GET_CODE (SET_SRC (x)) == COMPARE)
3091: op0 = XEXP (SET_SRC (x), 0), op1 = XEXP (SET_SRC (x), 1);
3092: else
3093: op0 = SET_SRC (x), op1 = const0_rtx;
3094:
3095: /* Simplify our comparison, if possible. */
3096: new_code = simplify_comparison (old_code, &op0, &op1);
3097:
3098: #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
3099: /* If this machine has CC modes other than CCmode, check to see
3100: if we need to use a different CC mode here. */
3101: compare_mode = SELECT_CC_MODE (new_code, op0);
3102:
3103: /* If the mode changed, we have to change SET_DEST, the mode
3104: in the compare, and the mode in the place SET_DEST is used.
3105: If SET_DEST is a hard register, just build new versions with
3106: the proper mode. If it is a pseudo, we lose unless it is only
3107: time we set the pseudo, in which case we can safely change
3108: its mode. */
3109: if (compare_mode != GET_MODE (SET_DEST (x)))
3110: {
3111: int regno = REGNO (SET_DEST (x));
3112: rtx new_dest = gen_rtx (REG, compare_mode, regno);
3113:
3114: if (regno < FIRST_PSEUDO_REGISTER
3115: || (reg_n_sets[regno] == 1
3116: && ! REG_USERVAR_P (SET_DEST (x))))
3117: {
3118: if (regno >= FIRST_PSEUDO_REGISTER)
3119: SUBST (regno_reg_rtx[regno], new_dest);
3120:
3121: SUBST (SET_DEST (x), new_dest);
3122: SUBST (XEXP (*cc_use, 0), new_dest);
3123: other_changed = 1;
3124: }
3125: }
3126: #endif
3127:
3128: /* If the code changed, we have to build a new comparison
3129: in undobuf.other_insn. */
3130: if (new_code != old_code)
3131: {
3132: unsigned mask;
3133:
3134: SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
3135: SET_DEST (x), const0_rtx));
3136:
3137: /* If the only change we made was to change an EQ into an
3138: NE or vice versa, OP0 has only one significant bit,
3139: and OP1 is zero, check if changing the user of the condition
3140: code will produce a valid insn. If it won't, we can keep
3141: the original code in that insn by surrounding our operation
3142: with an XOR. */
3143:
3144: if (((old_code == NE && new_code == EQ)
3145: || (old_code == EQ && new_code == NE))
3146: && ! other_changed && op1 == const0_rtx
3147: && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_INT
3148: && (exact_log2 (mask = significant_bits (op0,
3149: GET_MODE (op0)))
3150: >= 0))
3151: {
3152: rtx pat = PATTERN (other_insn), note = 0;
3153:
3154: if ((recog_for_combine (&pat, undobuf.other_insn, ¬e) < 0
3155: && ! check_asm_operands (pat)))
3156: {
3157: PUT_CODE (*cc_use, old_code);
3158: other_insn = 0;
3159:
3160: op0 = gen_binary (XOR, GET_MODE (op0), op0,
3161: gen_rtx (CONST_INT, VOIDmode, mask));
3162: }
3163: }
3164:
3165: other_changed = 1;
3166: }
3167:
3168: if (other_changed)
3169: undobuf.other_insn = other_insn;
3170:
3171: #ifdef HAVE_cc0
3172: /* If we are now comparing against zero, change our source if
3173: needed. If we do not use cc0, we always have a COMPARE. */
3174: if (op1 == const0_rtx && SET_DEST (x) == cc0_rtx)
3175: SUBST (SET_SRC (x), op0);
3176: else
3177: #endif
3178:
3179: /* Otherwise, if we didn't previously have a COMPARE in the
3180: correct mode, we need one. */
3181: if (GET_CODE (SET_SRC (x)) != COMPARE
3182: || GET_MODE (SET_SRC (x)) != compare_mode)
3183: SUBST (SET_SRC (x), gen_rtx_combine (COMPARE, compare_mode,
3184: op0, op1));
3185: else
3186: {
3187: /* Otherwise, update the COMPARE if needed. */
3188: SUBST (XEXP (SET_SRC (x), 0), op0);
3189: SUBST (XEXP (SET_SRC (x), 1), op1);
3190: }
3191: }
3192: else
3193: {
3194: /* Get SET_SRC in a form where we have placed back any
3195: compound expressions. Then do the checks below. */
3196: temp = make_compound_operation (SET_SRC (x), SET);
3197: SUBST (SET_SRC (x), temp);
3198: }
3199:
3200: #ifdef BYTE_LOADS_ZERO_EXTEND
3201: /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with
3202: M wider than N, this would require a paradoxical subreg.
3203: Replace the subreg with a zero_extend to avoid the reload that
3204: would otherwise be required. */
3205: if (GET_CODE (SET_SRC (x)) == SUBREG
3206: && subreg_lowpart_p (SET_SRC (x))
3207: && SUBREG_WORD (SET_SRC (x)) == 0
3208: && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
3209: > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
3210: && GET_CODE (SUBREG_REG (SET_SRC (x))) == MEM)
3211: SUBST (SET_SRC (x), gen_rtx_combine (ZERO_EXTEND,
3212: GET_MODE (SET_SRC (x)),
3213: XEXP (SET_SRC (x), 0)));
3214: #endif
3215:
3216: break;
3217:
3218: case AND:
3219: if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3220: {
3221: x = simplify_and_const_int (x, mode, XEXP (x, 0),
3222: INTVAL (XEXP (x, 1)));
3223:
3224: /* If we have (ior (and (X C1) C2)) and the next restart would be
3225: the last, simplify this by making C1 as small as possible
3226: and then exit. */
3227: if (n_restarts >= 3 && GET_CODE (x) == IOR
3228: && GET_CODE (XEXP (x, 0)) == AND
3229: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3230: && GET_CODE (XEXP (x, 1)) == CONST_INT)
3231: {
3232: temp = gen_binary (AND, mode, XEXP (XEXP (x, 0), 0),
3233: gen_rtx (CONST_INT, VOIDmode,
3234: (INTVAL (XEXP (XEXP (x, 0), 1))
3235: & ~ INTVAL (XEXP (x, 1)))));
3236: return gen_binary (IOR, mode, temp, XEXP (x, 1));
3237: }
3238:
3239: if (GET_CODE (x) != AND)
3240: goto restart;
3241: }
3242:
3243: /* Convert (A | B) & A to A. */
3244: if (GET_CODE (XEXP (x, 0)) == IOR
3245: && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3246: || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
3247: && ! side_effects_p (XEXP (XEXP (x, 0), 0))
3248: && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
3249: return XEXP (x, 1);
3250:
3251: /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
3252: insn (and may simplify more). */
3253: else if (GET_CODE (XEXP (x, 0)) == XOR
3254: && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3255: && ! side_effects_p (XEXP (x, 1)))
3256: {
3257: x = gen_binary (AND, mode,
3258: gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
3259: XEXP (x, 1));
3260: goto restart;
3261: }
3262: else if (GET_CODE (XEXP (x, 0)) == XOR
3263: && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
3264: && ! side_effects_p (XEXP (x, 1)))
3265: {
3266: x = gen_binary (AND, mode,
3267: gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
3268: XEXP (x, 1));
3269: goto restart;
3270: }
3271:
3272: /* Similarly for (~ (A ^ B)) & A. */
3273: else if (GET_CODE (XEXP (x, 0)) == NOT
3274: && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
3275: && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 0), XEXP (x, 1))
3276: && ! side_effects_p (XEXP (x, 1)))
3277: {
3278: x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 1),
3279: XEXP (x, 1));
3280: goto restart;
3281: }
3282: else if (GET_CODE (XEXP (x, 0)) == NOT
3283: && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
3284: && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 1), XEXP (x, 1))
3285: && ! side_effects_p (XEXP (x, 1)))
3286: {
3287: x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 0),
3288: XEXP (x, 1));
3289: goto restart;
3290: }
3291:
3292: /* In the follow group of tests (and those in case IOR below),
3293: we start with some combination of logical operations and apply
3294: the distributive law followed by the inverse distributive law.
3295: Most of the time, this results in no change. However, if some of
3296: the operands are the same or inverses of each other, simplifications
3297: will result.
3298:
3299: For example, (and (ior A B) (not B)) can occur as the result of
3300: expanding a bit field assignment. When we apply the distributive
3301: law to this, we get (ior (and (A (not B))) (and (B (not B)))),
3302: which then simplifies to (and (A (not B))). */
3303:
3304: /* If we have (and (ior A B) C), apply the distributive law and then
3305: the inverse distributive law to see if things simplify. */
3306:
3307: if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == XOR)
3308: {
3309: x = apply_distributive_law
3310: (gen_binary (GET_CODE (XEXP (x, 0)), mode,
3311: gen_binary (AND, mode,
3312: XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3313: gen_binary (AND, mode,
3314: XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3315: if (GET_CODE (x) != AND)
3316: goto restart;
3317: }
3318:
3319: if (GET_CODE (XEXP (x, 1)) == IOR || GET_CODE (XEXP (x, 1)) == XOR)
3320: {
3321: x = apply_distributive_law
3322: (gen_binary (GET_CODE (XEXP (x, 1)), mode,
3323: gen_binary (AND, mode,
3324: XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
3325: gen_binary (AND, mode,
3326: XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
3327: if (GET_CODE (x) != AND)
3328: goto restart;
3329: }
3330:
3331: /* Similarly, taking advantage of the fact that
3332: (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
3333:
3334: if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == XOR)
3335: {
3336: x = apply_distributive_law
3337: (gen_binary (XOR, mode,
3338: gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
3339: XEXP (XEXP (x, 1), 0)),
3340: gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
3341: XEXP (XEXP (x, 1), 1))));
3342: if (GET_CODE (x) != AND)
3343: goto restart;
3344: }
3345:
3346: else if (GET_CODE (XEXP (x, 1)) == NOT && GET_CODE (XEXP (x, 0)) == XOR)
3347: {
3348: x = apply_distributive_law
3349: (gen_binary (XOR, mode,
3350: gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
3351: XEXP (XEXP (x, 0), 0)),
3352: gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
3353: XEXP (XEXP (x, 0), 1))));
3354: if (GET_CODE (x) != AND)
3355: goto restart;
3356: }
3357: break;
3358:
3359: case IOR:
3360: /* Convert (A & B) | A to A. */
3361: if (GET_CODE (XEXP (x, 0)) == AND
3362: && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3363: || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
3364: && ! side_effects_p (XEXP (XEXP (x, 0), 0))
3365: && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
3366: return XEXP (x, 1);
3367:
3368: /* If we have (ior (and A B) C), apply the distributive law and then
3369: the inverse distributive law to see if things simplify. */
3370:
3371: if (GET_CODE (XEXP (x, 0)) == AND)
3372: {
3373: x = apply_distributive_law
3374: (gen_binary (AND, mode,
3375: gen_binary (IOR, mode,
3376: XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3377: gen_binary (IOR, mode,
3378: XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3379:
3380: if (GET_CODE (x) != IOR)
3381: goto restart;
3382: }
3383:
3384: if (GET_CODE (XEXP (x, 1)) == AND)
3385: {
3386: x = apply_distributive_law
3387: (gen_binary (AND, mode,
3388: gen_binary (IOR, mode,
3389: XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
3390: gen_binary (IOR, mode,
3391: XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
3392:
3393: if (GET_CODE (x) != IOR)
3394: goto restart;
3395: }
3396:
3397: /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
3398: mode size to (rotate A CX). */
3399:
3400: if (((GET_CODE (XEXP (x, 0)) == ASHIFT
3401: && GET_CODE (XEXP (x, 1)) == LSHIFTRT)
3402: || (GET_CODE (XEXP (x, 1)) == ASHIFT
3403: && GET_CODE (XEXP (x, 0)) == LSHIFTRT))
3404: && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 1), 0))
3405: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3406: && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3407: && (INTVAL (XEXP (XEXP (x, 0), 1)) + INTVAL (XEXP (XEXP (x, 1), 1))
3408: == GET_MODE_BITSIZE (mode)))
3409: {
3410: rtx shift_count;
3411:
3412: if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3413: shift_count = XEXP (XEXP (x, 0), 1);
3414: else
3415: shift_count = XEXP (XEXP (x, 1), 1);
3416: x = gen_rtx (ROTATE, mode, XEXP (XEXP (x, 0), 0), shift_count);
3417: goto restart;
3418: }
3419: break;
3420:
3421: case XOR:
3422: /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
3423: Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
3424: (NOT y). */
3425: {
3426: int num_negated = 0;
3427: rtx in1 = XEXP (x, 0), in2 = XEXP (x, 1);
3428:
3429: if (GET_CODE (in1) == NOT)
3430: num_negated++, in1 = XEXP (in1, 0);
3431: if (GET_CODE (in2) == NOT)
3432: num_negated++, in2 = XEXP (in2, 0);
3433:
3434: if (num_negated == 2)
3435: {
3436: SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3437: SUBST (XEXP (x, 1), XEXP (XEXP (x, 1), 0));
3438: }
3439: else if (num_negated == 1)
3440: return gen_rtx_combine (NOT, mode,
3441: gen_rtx_combine (XOR, mode, in1, in2));
3442: }
3443:
3444: /* Convert (xor (and A B) B) to (and (not A) B). The latter may
3445: correspond to a machine insn or result in further simplifications
3446: if B is a constant. */
3447:
3448: if (GET_CODE (XEXP (x, 0)) == AND
3449: && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
3450: && ! side_effects_p (XEXP (x, 1)))
3451: {
3452: x = gen_binary (AND, mode,
3453: gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
3454: XEXP (x, 1));
3455: goto restart;
3456: }
3457: else if (GET_CODE (XEXP (x, 0)) == AND
3458: && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3459: && ! side_effects_p (XEXP (x, 1)))
3460: {
3461: x = gen_binary (AND, mode,
3462: gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
3463: XEXP (x, 1));
3464: goto restart;
3465: }
3466:
3467:
3468: #if STORE_FLAG_VALUE == 1
3469: /* (xor (comparison foo bar) (const_int 1)) can become the reversed
3470: comparison. */
3471: if (XEXP (x, 1) == const1_rtx
3472: && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3473: && reversible_comparison_p (XEXP (x, 0)))
3474: return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3475: mode, XEXP (XEXP (x, 0), 0),
3476: XEXP (XEXP (x, 0), 1));
3477: #endif
3478:
3479: /* (xor (comparison foo bar) (const_int sign-bit))
3480: when STORE_FLAG_VALUE is the sign bit. */
3481: if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT
3482: && STORE_FLAG_VALUE == 1 << (GET_MODE_BITSIZE (mode) - 1)
3483: && XEXP (x, 1) == const_true_rtx
3484: && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3485: && reversible_comparison_p (XEXP (x, 0)))
3486: return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3487: mode, XEXP (XEXP (x, 0), 0),
3488: XEXP (XEXP (x, 0), 1));
3489: break;
3490:
3491: case ABS:
3492: /* (abs (neg <foo>)) -> (abs <foo>) */
3493: if (GET_CODE (XEXP (x, 0)) == NEG)
3494: SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3495:
3496: /* If operand is something known to be positive, ignore the ABS. */
3497: if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
3498: || (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) <= HOST_BITS_PER_INT
3499: && ((significant_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3500: & (1 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
3501: == 0)))
3502: return XEXP (x, 0);
3503:
3504:
3505: /* If operand is known to be only -1 or 0, convert ABS to NEG. */
3506: if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTRACT
3507: && XEXP (XEXP (x, 0), 1) == const1_rtx)
3508: || (GET_CODE (XEXP (x, 0)) == ASHIFTRT
3509: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3510: && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3511: || ((temp = get_last_value (XEXP (x, 0))) != 0
3512: && ((GET_CODE (temp) == SIGN_EXTRACT
3513: && XEXP (temp, 1) == const1_rtx)
3514: || (GET_CODE (temp) == ASHIFTRT
3515: && GET_CODE (XEXP (temp, 1)) == CONST_INT
3516: && (INTVAL (XEXP (temp, 1))
3517: == GET_MODE_BITSIZE (mode) - 1)))))
3518: {
3519: x = gen_rtx_combine (NEG, mode, XEXP (x, 0));
3520: goto restart;
3521: }
3522: break;
3523:
3524: case FLOAT:
3525: /* (float (sign_extend <X>)) = (float <X>). */
3526: if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
3527: SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3528: break;
3529:
3530: case LSHIFT:
3531: case ASHIFT:
3532: case LSHIFTRT:
3533: case ASHIFTRT:
3534: case ROTATE:
3535: case ROTATERT:
3536: #ifdef SHIFT_COUNT_TRUNCATED
3537: /* (*shift <X> (sign_extend <Y>)) = (*shift <X> <Y>) (most machines).
3538: True for all kinds of shifts and also for zero_extend. */
3539: if ((GET_CODE (XEXP (x, 1)) == SIGN_EXTEND
3540: || GET_CODE (XEXP (x, 1)) == ZERO_EXTEND)
3541: && FAKE_EXTEND_SAFE_P (mode, XEXP (XEXP (x, 1), 0)))
3542: SUBST (XEXP (x, 1),
3543: /* This is a perverse SUBREG, wider than its base. */
3544: gen_lowpart_for_combine (mode, XEXP (XEXP (x, 1), 0)));
3545:
3546: /* tege: Change (bitshifts ... (and ... mask), c)
3547: to (bitshifts ... c) if mask just masks the bits the bitshift
3548: insns do automatically on this machine. */
3549: if (GET_CODE (XEXP (x, 1)) == AND
3550: && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3551: && (~ INTVAL (XEXP (XEXP (x, 1), 1)) & GET_MODE_MASK (mode)) == 0)
3552: SUBST (XEXP (x, 1), XEXP (XEXP (x, 1), 0));
3553: #endif
3554:
3555: /* If this is a shift by a constant amount, simplify it. */
3556: if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3557: {
3558: x = simplify_shift_const (x, code, mode, XEXP (x, 0),
3559: INTVAL (XEXP (x, 1)));
3560: if (GET_CODE (x) != code)
3561: goto restart;
3562: }
3563: break;
3564: }
3565:
3566: return x;
3567: }
3568:
3569: /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
3570: operations" because they can be replaced with two more basic operations.
3571: ZERO_EXTEND is also considered "compound" because it can be replaced with
3572: an AND operation, which is simpler, though only one operation.
3573:
3574: The function expand_compound_operation is called with an rtx expression
3575: and will convert it to the appropriate shifts and AND operations,
3576: simplifying at each stage.
3577:
3578: The function make_compound_operation is called to convert an expression
3579: consisting of shifts and ANDs into the equivalent compound expression.
3580: It is the inverse of this function, loosely speaking. */
3581:
3582: static rtx
3583: expand_compound_operation (x)
3584: rtx x;
3585: {
3586: int pos = 0, len;
3587: int unsignedp = 0;
3588: int modewidth;
3589: rtx tem;
3590:
3591: switch (GET_CODE (x))
3592: {
3593: case ZERO_EXTEND:
3594: unsignedp = 1;
3595: case SIGN_EXTEND:
3596: /* If we somehow managed to end up with (sign/zero_extend (const_int x)),
3597: just return the CONST_INT. We can't know how much masking to do
3598: in that case. */
3599: if (GET_CODE (XEXP (x, 0)) == CONST_INT)
3600: return XEXP (x, 0);
3601:
3602: if (! FAKE_EXTEND_SAFE_P (GET_MODE (XEXP (x, 0)), XEXP (x, 0)))
3603: return x;
3604:
3605: len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
3606: /* If the inner object has VOIDmode (the only way this can happen
3607: is if it is a ASM_OPERANDS), we can't do anything since we don't
3608: know how much masking to do. */
3609: if (len == 0)
3610: return x;
3611:
3612: break;
3613:
3614: case ZERO_EXTRACT:
3615: unsignedp = 1;
3616: case SIGN_EXTRACT:
3617: /* If the operand is a CLOBBER, just return it. */
3618: if (GET_CODE (XEXP (x, 0)) == CLOBBER)
3619: return XEXP (x, 0);
3620:
3621: if (GET_CODE (XEXP (x, 1)) != CONST_INT
3622: || GET_CODE (XEXP (x, 2)) != CONST_INT
3623: || GET_MODE (XEXP (x, 0)) == VOIDmode)
3624: return x;
3625:
3626: len = INTVAL (XEXP (x, 1));
3627: pos = INTVAL (XEXP (x, 2));
3628:
3629: /* If this goes outside the object being extracted, replace the object
3630: with a (use (mem ...)) construct that only combine understands
3631: and is used only for this purpose. */
3632: if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
3633: SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
3634:
3635: #if BITS_BIG_ENDIAN
3636: pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
3637: #endif
3638: break;
3639:
3640: default:
3641: return x;
3642: }
3643:
3644: /* If we reach here, we want to return a pair of shifts. The inner
3645: shift is a left shift of BITSIZE - POS - LEN bits. The outer
3646: shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
3647: logical depending on the value of UNSIGNEDP.
3648:
3649: If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
3650: converted into an AND of a shift.
3651:
3652: We must check for the case where the left shift would have a negative
3653: count. This can happen in a case like (x >> 31) & 255 on machines
3654: that can't shift by a constant. On those machines, we would first
3655: combine the shift with the AND to produce a variable-position
3656: extraction. Then the constant of 31 would be substituted in to produce
3657: a such a position. */
3658:
3659: modewidth = GET_MODE_BITSIZE (GET_MODE (x));
3660: if (modewidth >= pos - len)
3661: tem = simplify_shift_const (0, unsignedp ? LSHIFTRT : ASHIFTRT,
3662: GET_MODE (x),
3663: simplify_shift_const (0, ASHIFT, GET_MODE (x),
3664: XEXP (x, 0),
3665: modewidth - pos - len),
3666: modewidth - len);
3667:
3668: else if (unsignedp && len < HOST_BITS_PER_INT)
3669: tem = simplify_and_const_int (0, GET_MODE (x),
3670: simplify_shift_const (0, LSHIFTRT,
3671: GET_MODE (x),
3672: XEXP (x, 0), pos),
3673: (1 << len) - 1);
3674: else
3675: /* Any other cases we can't handle. */
3676: return x;
3677:
3678:
3679: /* If we couldn't do this for some reason, return the original
3680: expression. */
3681: if (GET_CODE (tem) == CLOBBER)
3682: return x;
3683:
3684: return tem;
3685: }
3686:
3687: /* X is a SET which contains an assignment of one object into
3688: a part of another (such as a bit-field assignment, STRICT_LOW_PART,
3689: or certain SUBREGS). If possible, convert it into a series of
3690: logical operations.
3691:
3692: We half-heartedly support variable positions, but do not at all
3693: support variable lengths. */
3694:
3695: static rtx
3696: expand_field_assignment (x)
3697: rtx x;
3698: {
3699: rtx inner;
3700: rtx pos; /* Always counts from low bit. */
3701: int len;
3702: rtx mask;
3703: enum machine_mode compute_mode;
3704:
3705: /* Loop until we find something we can't simplify. */
3706: while (1)
3707: {
3708: if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
3709: && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
3710: {
3711: inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
3712: len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
3713: pos = const0_rtx;
3714: }
3715: else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3716: && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
3717: {
3718: inner = XEXP (SET_DEST (x), 0);
3719: len = INTVAL (XEXP (SET_DEST (x), 1));
3720: pos = XEXP (SET_DEST (x), 2);
3721:
3722: /* If the position is constant and spans the width of INNER,
3723: surround INNER with a USE to indicate this. */
3724: if (GET_CODE (pos) == CONST_INT
3725: && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
3726: inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
3727:
3728: #if BITS_BIG_ENDIAN
3729: if (GET_CODE (pos) == CONST_INT)
3730: pos = gen_rtx (CONST_INT, VOIDmode,
3731: (GET_MODE_BITSIZE (GET_MODE (inner)) - len
3732: - INTVAL (pos)));
3733: else if (GET_CODE (pos) == MINUS
3734: && GET_CODE (XEXP (pos, 1)) == CONST_INT
3735: && (INTVAL (XEXP (pos, 1))
3736: == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
3737: /* If position is ADJUST - X, new position is X. */
3738: pos = XEXP (pos, 0);
3739: else
3740: pos = gen_binary (MINUS, GET_MODE (pos),
3741: gen_rtx (CONST_INT, VOIDmode,
3742: (GET_MODE_BITSIZE (GET_MODE (inner))
3743: - len)), pos);
3744: #endif
3745: }
3746:
3747: /* A SUBREG between two modes that occupy the same numbers of words
3748: can be done by moving the SUBREG to the source. */
3749: else if (GET_CODE (SET_DEST (x)) == SUBREG
3750: && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
3751: + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
3752: == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
3753: + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
3754: {
3755: x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
3756: gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
3757: SET_SRC (x)));
3758: continue;
3759: }
3760: else
3761: break;
3762:
3763: while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
3764: inner = SUBREG_REG (inner);
3765:
3766: compute_mode = GET_MODE (inner);
3767:
3768: /* Compute a mask of LEN bits, if we can do this on the host machine. */
3769: if (len < HOST_BITS_PER_INT)
3770: mask = gen_rtx (CONST_INT, VOIDmode, (1 << len) - 1);
3771: else
3772: break;
3773:
3774: /* Now compute the equivalent expression. Make a copy of INNER
3775: for the SET_DEST in case it is a MEM into which we will substitute;
3776: we don't want shared RTL in that case. */
3777: x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
3778: gen_binary (IOR, compute_mode,
3779: gen_binary (AND, compute_mode,
3780: gen_unary (NOT, compute_mode,
3781: gen_binary (ASHIFT,
3782: compute_mode,
3783: mask, pos)),
3784: inner),
3785: gen_binary (ASHIFT, compute_mode,
3786: gen_binary (AND, compute_mode,
3787: gen_lowpart_for_combine
3788: (compute_mode,
3789: SET_SRC (x)),
3790: mask),
3791: pos)));
3792: }
3793:
3794: return x;
3795: }
3796:
3797: /* Return an RTX for a reference to LEN bits of INNER. POS is the starting
3798: bit position (counted from the LSB) if >= 0; otherwise POS_RTX represents
3799: the starting bit position.
3800:
3801: INNER may be a USE. This will occur when we started with a bitfield
3802: that went outside the boundary of the object in memory, which is
3803: allowed on most machines. To isolate this case, we produce a USE
3804: whose mode is wide enough and surround the MEM with it. The only
3805: code that understands the USE is this routine. If it is not removed,
3806: it will cause the resulting insn not to match.
3807:
3808: UNSIGNEDP is non-zero for an unsigned reference and zero for a
3809: signed reference.
3810:
3811: IN_DEST is non-zero if this is a reference in the destination of a
3812: SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
3813: a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
3814: be used.
3815:
3816: IN_COMPARE is non-zero if we are in a COMPARE. This means that a
3817: ZERO_EXTRACT should be built even for bits starting at bit 0.
3818:
3819: MODE is the desired mode of the result (if IN_DEST == 0). */
3820:
3821: static rtx
3822: make_extraction (mode, inner, pos, pos_rtx, len,
3823: unsignedp, in_dest, in_compare)
3824: enum machine_mode mode;
3825: rtx inner;
3826: int pos;
3827: rtx pos_rtx;
3828: int len;
3829: int unsignedp;
3830: int in_dest, in_compare;
3831: {
3832: enum machine_mode is_mode = GET_MODE (inner);
3833: enum machine_mode inner_mode;
3834: enum machine_mode wanted_mem_mode = byte_mode;
3835: enum machine_mode pos_mode = word_mode;
3836: enum machine_mode extraction_mode = word_mode;
3837: enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
3838: int spans_byte = 0;
3839: rtx new = 0;
3840:
3841: /* Get some information about INNER and get the innermost object. */
3842: if (GET_CODE (inner) == USE)
3843: /* We don't need to adjust the position because we set up the USE
3844: to pretend that it was a full-word object. */
3845: spans_byte = 1, inner = XEXP (inner, 0);
3846: else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
3847: inner = SUBREG_REG (inner);
3848:
3849: inner_mode = GET_MODE (inner);
3850:
3851: if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
3852: pos = INTVAL (pos_rtx);
3853:
3854: /* See if this can be done without an extraction. We never can if the
3855: width of the field is not the same as that of some integer mode. For
3856: registers, we can only avoid the extraction if the position is at the
3857: low-order bit and this is either not in the destination or we have the
3858: appropriate STRICT_LOW_PART operation available.
3859:
3860: For MEM, we can avoid an extract if the field starts on an appropriate
3861: boundary and we can change the mode of the memory reference. However,
3862: we cannot directly access the MEM if we have a USE and the underlying
3863: MEM is not TMODE. This combination means that MEM was being used in a
3864: context where bits outside its mode were being referenced; that is only
3865: valid in bit-field insns. */
3866:
3867: if (tmode != BLKmode
3868: && ! (spans_byte && inner_mode != tmode)
3869: && ((pos == 0 && GET_CODE (inner) == REG
3870: && (! in_dest
3871: || (movstrict_optab->handlers[(int) tmode].insn_code
3872: != CODE_FOR_nothing)))
3873: || (GET_CODE (inner) == MEM && pos >= 0
1.1.1.2 ! root 3874: && (pos
! 3875: % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
! 3876: : BITS_PER_UNIT)) == 0
1.1 root 3877: /* We can't do this if we are widening INNER_MODE (it
3878: may not be aligned, for one thing). */
3879: && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
3880: && (inner_mode == tmode
3881: || (! mode_dependent_address_p (XEXP (inner, 0))
3882: && ! MEM_VOLATILE_P (inner))))))
3883: {
3884: int offset = pos / BITS_PER_UNIT;
3885:
3886: /* If INNER is a MEM, make a new MEM that encompasses just the desired
3887: field. If the original and current mode are the same, we need not
3888: adjust the offset. Otherwise, we do if bytes big endian.
3889:
3890: If INNER is not a MEM, get a piece consisting of the just the field
3891: of interest (in this case INNER must be a REG and POS must be 0). */
3892:
3893: if (GET_CODE (inner) == MEM)
3894: {
3895: #if BYTES_BIG_ENDIAN
3896: if (inner_mode != tmode)
3897: offset = (GET_MODE_SIZE (inner_mode)
3898: - GET_MODE_SIZE (tmode) - offset);
3899: #endif
3900:
3901: new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
3902: RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
3903: MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
3904: MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
3905: }
3906: else
3907: new = gen_lowpart_for_combine (tmode, inner);
3908:
3909: /* If this extraction is going into the destination of a SET,
3910: make a STRICT_LOW_PART unless we made a MEM. */
3911:
3912: if (in_dest)
3913: return (GET_CODE (new) == MEM ? new
3914: : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new));
3915:
3916: /* Otherwise, sign- or zero-extend unless we already are in the
3917: proper mode. */
3918:
3919: return (mode == tmode ? new
3920: : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
3921: mode, new));
3922: }
3923:
3924: /* Unless this is in a COMPARE or we have a funny memory reference,
3925: don't do anything with field extracts starting at the low-order
3926: bit since they are simple AND operations. */
3927: if (pos == 0 && ! in_dest && ! in_compare && ! spans_byte)
3928: return 0;
3929:
3930: /* Get the mode to use should INNER be a MEM, the mode for the position,
3931: and the mode for the result. */
3932: #ifdef HAVE_insv
3933: if (in_dest)
3934: {
3935: wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
3936: pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
3937: extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
3938: }
3939: #endif
3940:
3941: #ifdef HAVE_extzv
3942: if (! in_dest && unsignedp)
3943: {
3944: wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
3945: pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
3946: extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
3947: }
3948: #endif
3949:
3950: #ifdef HAVE_extv
3951: if (! in_dest && ! unsignedp)
3952: {
3953: wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
3954: pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
3955: extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
3956: }
3957: #endif
3958:
3959: /* Never narrow an object, since that might not be safe. */
3960:
3961: if (mode != VOIDmode
3962: && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
3963: extraction_mode = mode;
3964:
3965: if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
3966: && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
3967: pos_mode = GET_MODE (pos_rtx);
3968:
3969: /* If this is not from memory or we have to change the mode of memory and
3970: cannot, the desired mode is EXTRACTION_MODE. */
3971: if (GET_CODE (inner) != MEM
3972: || (inner_mode != wanted_mem_mode
3973: && (mode_dependent_address_p (XEXP (inner, 0))
3974: || MEM_VOLATILE_P (inner))))
3975: wanted_mem_mode = extraction_mode;
3976:
3977: #if BITS_BIG_ENDIAN
3978: /* If position is constant, compute new position. Otherwise, build
3979: subtraction. */
3980: if (pos >= 0)
3981: pos = (MAX (GET_MODE_BITSIZE (is_mode), GET_MODE_BITSIZE (wanted_mem_mode))
3982: - len - pos);
3983: else
3984: pos_rtx
3985: = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
3986: gen_rtx (CONST_INT, VOIDmode,
3987: (MAX (GET_MODE_BITSIZE (is_mode),
3988: GET_MODE_BITSIZE (wanted_mem_mode))
3989: - len)), pos_rtx);
3990: #endif
3991:
3992: /* If INNER has a wider mode, make it smaller. If this is a constant
3993: extract, try to adjust the byte to point to the byte containing
3994: the value. */
3995: if (wanted_mem_mode != VOIDmode
3996: && GET_MODE_SIZE (wanted_mem_mode) < GET_MODE_SIZE (is_mode)
3997: && ((GET_CODE (inner) == MEM
3998: && (inner_mode == wanted_mem_mode
3999: || (! mode_dependent_address_p (XEXP (inner, 0))
4000: && ! MEM_VOLATILE_P (inner))))))
4001: {
4002: int offset = 0;
4003:
4004: /* The computations below will be correct if the machine is big
4005: endian in both bits and bytes or little endian in bits and bytes.
4006: If it is mixed, we must adjust. */
4007:
4008: #if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
4009: if (! spans_byte && is_mode != wanted_mem_mode)
4010: offset = (GET_MODE_SIZE (is_mode)
4011: - GET_MODE_SIZE (wanted_mem_mode) - offset);
4012: #endif
4013:
4014: /* If bytes are big endian and we had a paradoxical SUBREG, we must
4015: adjust OFFSET to compensate. */
4016: #if BYTES_BIG_ENDIAN
4017: if (! spans_byte
4018: && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
4019: offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
4020: #endif
4021:
4022: /* If this is a constant position, we can move to the desired byte. */
4023: if (pos >= 0)
4024: {
4025: offset += pos / BITS_PER_UNIT;
4026: pos %= GET_MODE_BITSIZE (wanted_mem_mode);
4027: }
4028:
4029: if (offset != 0 || inner_mode != wanted_mem_mode)
4030: {
4031: rtx newmem = gen_rtx (MEM, wanted_mem_mode,
4032: plus_constant (XEXP (inner, 0), offset));
4033: RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
4034: MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
4035: MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
4036: inner = newmem;
4037: }
4038: }
4039:
4040: /* If INNER is not memory, we can always get it into the proper mode. */
4041: else if (GET_CODE (inner) != MEM)
4042: inner = gen_lowpart_for_combine (extraction_mode, inner);
4043:
4044: /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
4045: have to zero extend. Otherwise, we can just use a SUBREG. */
4046: if (pos < 0
4047: && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
4048: pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
4049: else if (pos < 0
4050: && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
4051: pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
4052:
4053: /* Make POS_RTX unless we already have it and it is correct. */
4054: if (pos_rtx == 0 || (pos >= 0 && INTVAL (pos_rtx) != pos))
4055: pos_rtx = gen_rtx (CONST_INT, VOIDmode, pos);
4056:
4057: /* Make the required operation. See if we can use existing rtx. */
4058: new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
4059: extraction_mode, inner,
4060: gen_rtx (CONST_INT, VOIDmode, len), pos_rtx);
4061: if (! in_dest)
4062: new = gen_lowpart_for_combine (mode, new);
4063:
4064: return new;
4065: }
4066:
4067: /* Look at the expression rooted at X. Look for expressions
4068: equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
4069: Form these expressions.
4070:
4071: Return the new rtx, usually just X.
4072:
4073: Also, for machines like the Vax that don't have logical shift insns,
4074: try to convert logical to arithmetic shift operations in cases where
4075: they are equivalent. This undoes the canonicalizations to logical
4076: shifts done elsewhere.
4077:
4078: We try, as much as possible, to re-use rtl expressions to save memory.
4079:
4080: IN_CODE says what kind of expression we are processing. Normally, it is
4081: SET. In a memory address (inside a MEM or PLUS, the latter being a
4082: kludge), it is MEM. When processing the arguments of a comparison
4083: or a COMPARE against zero, it is COMPARE. */
4084:
4085: static rtx
4086: make_compound_operation (x, in_code)
4087: rtx x;
4088: enum rtx_code in_code;
4089: {
4090: enum rtx_code code = GET_CODE (x);
4091: enum machine_mode mode = GET_MODE (x);
4092: int mode_width = GET_MODE_BITSIZE (mode);
4093: enum rtx_code next_code;
4094: int i;
4095: rtx new = 0;
4096: char *fmt;
4097:
4098: /* Select the code to be used in recursive calls. Once we are inside an
4099: address, we stay there. If we have a comparison, set to COMPARE,
4100: but once inside, go back to our default of SET. */
4101:
4102: next_code = (code == MEM || code == PLUS ? MEM
4103: : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
4104: && XEXP (x, 1) == const0_rtx) ? COMPARE
4105: : in_code == COMPARE ? SET : in_code);
4106:
4107: /* Process depending on the code of this operation. If NEW is set
4108: non-zero, it will be returned. */
4109:
4110: switch (code)
4111: {
4112: case ASHIFT:
4113: case LSHIFT:
4114: /* Convert shifts by constants into multiplications if inside
4115: an address. */
4116: if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
4117: && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_INT
4118: && INTVAL (XEXP (x, 1)) >= 0)
4119: new = gen_rtx_combine (MULT, mode, XEXP (x, 0),
4120: gen_rtx (CONST_INT, VOIDmode,
4121: 1 << INTVAL (XEXP (x, 1))));
4122: break;
4123:
4124: case AND:
4125: /* If the second operand is not a constant, we can't do anything
4126: with it. */
4127: if (GET_CODE (XEXP (x, 1)) != CONST_INT)
4128: break;
4129:
4130: /* If the constant is a power of two minus one and the first operand
4131: is a logical right shift, make an extraction. */
4132: if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4133: && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4134: new = make_extraction (mode, XEXP (XEXP (x, 0), 0), -1,
4135: XEXP (XEXP (x, 0), 1), i, 1,
4136: 0, in_code == COMPARE);
1.1.1.2 ! root 4137:
1.1 root 4138: /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
4139: else if (GET_CODE (XEXP (x, 0)) == SUBREG
4140: && subreg_lowpart_p (XEXP (x, 0))
4141: && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
4142: && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4143: new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))),
4144: XEXP (SUBREG_REG (XEXP (x, 0)), 0), -1,
4145: XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
4146: 0, in_code == COMPARE);
4147:
4148: /* One machines without logical shifts, if the operand of the AND is
4149: a logical shift and our mask turns off all the propagated sign
4150: bits, we can replace the logical shift with an arithmetic shift. */
4151: else if (
4152: #ifdef HAVE_ashrsi3
4153: HAVE_ashrsi3
4154: #else
4155: 0
4156: #endif
4157: #ifdef HAVE_lshrsi3
4158: && ! HAVE_lshrsi3
4159: #else
4160: && 1
4161: #endif
4162: && GET_CODE (XEXP (x, 0)) == LSHIFTRT
4163: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4164: && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
4165: && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_INT
4166: && mode_width <= HOST_BITS_PER_INT)
4167: {
4168: unsigned mask = GET_MODE_MASK (mode);
4169:
4170: mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
4171: if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
4172: SUBST (XEXP (x, 0),
4173: gen_rtx_combine (ASHIFTRT, mode, XEXP (XEXP (x, 0), 0),
4174: XEXP (XEXP (x, 0), 1)));
4175: }
4176:
4177: /* If the constant is one less than a power of two, this might be
4178: representable by an extraction even if no shift is present.
4179: If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
4180: we are in a COMPARE. */
4181: else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4182: new = make_extraction (mode, XEXP (x, 0), 0, 0, i, 1,
4183: 0, in_code == COMPARE);
4184:
4185: /* If we are in a comparison and this is an AND with a power of two,
4186: convert this into the appropriate bit extract. */
4187: else if (in_code == COMPARE
4188: && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4189: new = make_extraction (mode, XEXP (x, 0), i, 0, 1, 1, 0, 1);
4190:
4191: break;
4192:
4193: case LSHIFTRT:
4194: /* If the sign bit is known to be zero, replace this with an
4195: arithmetic shift. */
4196: if (
4197: #ifdef HAVE_ashrsi3
4198: HAVE_ashrsi3
4199: #else
4200: 0
4201: #endif
4202: #ifdef HAVE_lshrsi3
4203: && ! HAVE_lshrsi3
4204: #else
4205: && 1
4206: #endif
4207: && mode_width <= HOST_BITS_PER_INT
4208: && (significant_bits (XEXP (x, 0), mode)
4209: & (1 << (mode_width - 1))) == 0)
4210: {
4211: new = gen_rtx_combine (ASHIFTRT, mode, XEXP (x, 0), XEXP (x, 1));
4212: break;
4213: }
4214:
4215: /* ... fall through ... */
4216:
4217: case ASHIFTRT:
4218: /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
4219: this is a SIGN_EXTRACT. */
4220: if (GET_CODE (XEXP (x, 1)) == CONST_INT
4221: && GET_CODE (XEXP (x, 0)) == ASHIFT
4222: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4223: && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (x, 0), 1)))
4224: new = make_extraction (mode, XEXP (XEXP (x, 0), 0),
4225: (INTVAL (XEXP (x, 1))
4226: - INTVAL (XEXP (XEXP (x, 0), 1))),
4227: 0, mode_width - INTVAL (XEXP (x, 1)),
4228: code == LSHIFTRT, 0, in_code == COMPARE);
4229: break;
4230: }
4231:
4232: if (new)
4233: {
4234: x = new;
4235: code = GET_CODE (x);
4236: }
4237:
4238: /* Now recursively process each operand of this operation. */
4239: fmt = GET_RTX_FORMAT (code);
4240: for (i = 0; i < GET_RTX_LENGTH (code); i++)
4241: if (fmt[i] == 'e')
4242: {
4243: new = make_compound_operation (XEXP (x, i), next_code);
4244: SUBST (XEXP (x, i), new);
4245: }
4246:
4247: return x;
4248: }
4249:
4250: /* Given M see if it is a value that would select a field of bits
4251: within an item, but not the entire word. Return -1 if not.
4252: Otherwise, return the starting position of the field, where 0 is the
4253: low-order bit.
4254:
4255: *PLEN is set to the length of the field. */
4256:
4257: static int
4258: get_pos_from_mask (m, plen)
4259: unsigned int m;
4260: int *plen;
4261: {
4262: /* Get the bit number of the first 1 bit from the right, -1 if none. */
4263: int pos = exact_log2 (m & - m);
4264:
4265: if (pos < 0)
4266: return -1;
4267:
4268: /* Now shift off the low-order zero bits and see if we have a power of
4269: two minus 1. */
4270: *plen = exact_log2 ((m >> pos) + 1);
4271:
4272: if (*plen <= 0)
4273: return -1;
4274:
4275: return pos;
4276: }
4277:
1.1.1.2 ! root 4278: /* Rewrite X so that it is an expression in MODE. We only care about the
! 4279: low-order BITS bits so we can ignore AND operations that just clear
! 4280: higher-order bits.
! 4281:
! 4282: Also, if REG is non-zero and X is a register equal in value to REG,
! 4283: replace X with REG. */
! 4284:
! 4285: static rtx
! 4286: force_to_mode (x, mode, bits, reg)
! 4287: rtx x;
! 4288: enum machine_mode mode;
! 4289: int bits;
! 4290: rtx reg;
! 4291: {
! 4292: enum rtx_code code = GET_CODE (x);
! 4293:
! 4294: /* If X is narrower than MODE or if BITS is larger than the size of MODE,
! 4295: just get X in the proper mode. */
! 4296:
! 4297: if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
! 4298: || bits > GET_MODE_BITSIZE (mode))
! 4299: return gen_lowpart_for_combine (mode, x);
! 4300:
! 4301: switch (code)
! 4302: {
! 4303: case SIGN_EXTEND:
! 4304: case ZERO_EXTEND:
! 4305: case ZERO_EXTRACT:
! 4306: case SIGN_EXTRACT:
! 4307: x = expand_compound_operation (x);
! 4308: if (GET_CODE (x) != code)
! 4309: return force_to_mode (x, mode, bits, reg);
! 4310: break;
! 4311:
! 4312: case REG:
! 4313: if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
! 4314: || rtx_equal_p (reg, get_last_value (x))))
! 4315: x = reg;
! 4316: break;
! 4317:
! 4318: case CONST_INT:
! 4319: if (bits < HOST_BITS_PER_INT)
! 4320: x = gen_rtx (CONST_INT, VOIDmode,
! 4321: INTVAL (x) & ((1 << (bits + 1)) - 1));
! 4322: return x;
! 4323:
! 4324: case SUBREG:
! 4325: /* Ignore low-order SUBREGs. */
! 4326: if (subreg_lowpart_p (x))
! 4327: return force_to_mode (SUBREG_REG (x), mode, bits, reg);
! 4328: break;
! 4329:
! 4330: case AND:
! 4331: /* If this is an AND with a constant. Otherwise, we fall through to
! 4332: do the general binary case. */
! 4333:
! 4334: if (GET_CODE (XEXP (x, 1)) == CONST_INT)
! 4335: {
! 4336: int mask = INTVAL (XEXP (x, 1));
! 4337: int len = exact_log2 (mask + 1);
! 4338: rtx op = XEXP (x, 0);
! 4339:
! 4340: /* If this is masking some low-order bits, we may be able to
! 4341: impose a stricter constraint on what bits of the operand are
! 4342: required. */
! 4343:
! 4344: op = force_to_mode (op, mode, len > 0 ? MIN (len, bits) : bits,
! 4345: reg);
! 4346:
! 4347: if (bits < HOST_BITS_PER_INT)
! 4348: mask &= (1 << (bits + 1)) - 1;
! 4349:
! 4350: x = simplify_and_const_int (x, mode, op, mask);
! 4351:
! 4352: /* If X is still an AND, see if it is an AND with a mask that
! 4353: is just some low-order bits. If so, and it is BITS wide (it
! 4354: can't be wider), we don't need it. */
! 4355:
! 4356: if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
! 4357: && bits < HOST_BITS_PER_INT
! 4358: && INTVAL (XEXP (x, 1)) == (1 << (bits + 1)) - 1)
! 4359: x = XEXP (x, 0);
! 4360: return x;
! 4361: }
! 4362:
! 4363: /* ... fall through ... */
! 4364:
! 4365: case PLUS:
! 4366: case MINUS:
! 4367: case MULT:
! 4368: case IOR:
! 4369: case XOR:
! 4370: /* For most binary operations, just propagate into the operation and
! 4371: change the mode. */
! 4372:
! 4373: return gen_binary (code, mode,
! 4374: force_to_mode (XEXP (x, 0), mode, bits, reg),
! 4375: force_to_mode (XEXP (x, 1), mode, bits, reg));
! 4376:
! 4377: case ASHIFT:
! 4378: case LSHIFT:
! 4379: /* For left shifts, do the same, but just for the first operand.
! 4380: If the shift count is a constant, we need even fewer bits of the
! 4381: first operand. */
! 4382:
! 4383: if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) < bits)
! 4384: bits -= INTVAL (XEXP (x, 1));
! 4385:
! 4386: return gen_binary (code, mode,
! 4387: force_to_mode (XEXP (x, 0), mode, bits, reg),
! 4388: XEXP (x, 1));
! 4389:
! 4390: case LSHIFTRT:
! 4391: /* Here we can only do something if the shift count is a constant and
! 4392: the count plus BITS is no larger than the width of MODE, we can do
! 4393: the shift in MODE. */
! 4394:
! 4395: if (GET_CODE (XEXP (x, 1)) == CONST_INT
! 4396: && INTVAL (XEXP (x, 1)) + bits <= GET_MODE_BITSIZE (mode))
! 4397: return gen_binary (LSHIFTRT, mode,
! 4398: force_to_mode (XEXP (x, 0), mode,
! 4399: bits + INTVAL (XEXP (x, 1)), reg),
! 4400: XEXP (x, 1));
! 4401: break;
! 4402:
! 4403: case NEG:
! 4404: case NOT:
! 4405: /* Handle these similarly to the way we handle most binary operations. */
! 4406: return gen_unary (code, mode,
! 4407: force_to_mode (XEXP (x, 0), mode, bits, reg));
! 4408: }
! 4409:
! 4410: /* Otherwise, just do the operation canonically. */
! 4411: return gen_lowpart_for_combine (mode, x);
! 4412: }
! 4413:
1.1 root 4414: /* See if X, a SET operation, can be rewritten as a bit-field assignment.
4415: Return that assignment if so.
4416:
4417: We only handle the most common cases. */
4418:
4419: static rtx
4420: make_field_assignment (x)
4421: rtx x;
4422: {
4423: rtx dest = SET_DEST (x);
4424: rtx src = SET_SRC (x);
1.1.1.2 ! root 4425: rtx ourdest;
! 4426: rtx assign;
! 4427: int c1, pos, len;
! 4428: rtx other;
! 4429: enum machine_mode mode;
1.1 root 4430:
4431: /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
4432: a clear of a one-bit field. We will have changed it to
4433: (and (rotate (const_int -2) POS) DEST), so check for that. Also check
4434: for a SUBREG. */
4435:
4436: if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
4437: && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
4438: && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
1.1.1.2 ! root 4439: && (rtx_equal_p (dest, XEXP (src, 1))
! 4440: || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
! 4441: || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
1.1 root 4442: {
4443: assign = make_extraction (VOIDmode, dest, -1, XEXP (XEXP (src, 0), 1),
4444: 1, 1, 1, 0);
1.1.1.2 ! root 4445: return gen_rtx (SET, VOIDmode, assign, const0_rtx);
1.1 root 4446: }
4447:
4448: else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
4449: && subreg_lowpart_p (XEXP (src, 0))
4450: && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
4451: < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
4452: && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
4453: && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
1.1.1.2 ! root 4454: && (rtx_equal_p (dest, XEXP (src, 1))
! 4455: || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
! 4456: || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
1.1 root 4457: {
4458: assign = make_extraction (VOIDmode, dest, -1,
4459: XEXP (SUBREG_REG (XEXP (src, 0)), 1),
4460: 1, 1, 1, 0);
1.1.1.2 ! root 4461: return gen_rtx (SET, VOIDmode, assign, const0_rtx);
1.1 root 4462: }
4463:
4464: /* If SRC is (ior (ashift (const_int 1) POS DEST)), this is a set of a
4465: one-bit field. */
4466: else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
4467: && XEXP (XEXP (src, 0), 0) == const1_rtx
1.1.1.2 ! root 4468: && (rtx_equal_p (dest, XEXP (src, 1))
! 4469: || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
! 4470: || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
1.1 root 4471: {
4472: assign = make_extraction (VOIDmode, dest, -1, XEXP (XEXP (src, 0), 1),
4473: 1, 1, 1, 0);
1.1.1.2 ! root 4474: return gen_rtx (SET, VOIDmode, assign, const1_rtx);
1.1 root 4475: }
4476:
1.1.1.2 ! root 4477: /* The other case we handle is assignments into a constant-position
! 4478: field. They look like (ior (and DEST C1) OTHER). If C1 represents
! 4479: a mask that has all one bits except for a group of zero bits and
! 4480: OTHER is known to have zeros where C1 has ones, this is such an
! 4481: assignment. Compute the position and length from C1. Shift OTHER
! 4482: to the appropriate position, force it to the required mode, and
! 4483: make the extraction. Check for the AND in both operands. */
! 4484:
! 4485: if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == AND
! 4486: && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT
! 4487: && (rtx_equal_p (XEXP (XEXP (src, 0), 0), dest)
! 4488: || rtx_equal_p (XEXP (XEXP (src, 0), 0), get_last_value (dest))
! 4489: || rtx_equal_p (get_last_value (XEXP (XEXP (src, 0), 1)), dest)))
! 4490: c1 = INTVAL (XEXP (XEXP (src, 0), 1)), other = XEXP (src, 1);
! 4491: else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 1)) == AND
! 4492: && GET_CODE (XEXP (XEXP (src, 1), 1)) == CONST_INT
! 4493: && (rtx_equal_p (XEXP (XEXP (src, 1), 0), dest)
! 4494: || rtx_equal_p (XEXP (XEXP (src, 1), 0), get_last_value (dest))
! 4495: || rtx_equal_p (get_last_value (XEXP (XEXP (src, 1), 0)),
! 4496: dest)))
! 4497: c1 = INTVAL (XEXP (XEXP (src, 1), 1)), other = XEXP (src, 0);
! 4498: else
! 4499: return x;
1.1 root 4500:
1.1.1.2 ! root 4501: pos = get_pos_from_mask (~c1, &len);
! 4502: if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
! 4503: || (c1 & significant_bits (other, GET_MODE (other))) != 0)
! 4504: return x;
1.1 root 4505:
1.1.1.2 ! root 4506: assign = make_extraction (VOIDmode, dest, pos, 0, len, 1, 1, 0);
1.1 root 4507:
1.1.1.2 ! root 4508: /* The mode to use for the source is the mode of the assignment, or of
! 4509: what is inside a possible STRICT_LOW_PART. */
! 4510: mode = (GET_CODE (assign) == STRICT_LOW_PART
! 4511: ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
1.1 root 4512:
1.1.1.2 ! root 4513: /* Shift OTHER right POS places and make it the source, restricting it
! 4514: to the proper length and mode. */
1.1 root 4515:
1.1.1.2 ! root 4516: src = force_to_mode (simplify_shift_const (0, LSHIFTRT, GET_MODE (src),
! 4517: other, pos),
! 4518: mode, len, dest);
1.1 root 4519:
1.1.1.2 ! root 4520: return gen_rtx_combine (SET, VOIDmode, assign, src);
1.1 root 4521: }
4522:
4523: /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
4524: if so. */
4525:
4526: static rtx
4527: apply_distributive_law (x)
4528: rtx x;
4529: {
4530: enum rtx_code code = GET_CODE (x);
4531: rtx lhs, rhs, other;
4532: rtx tem;
4533: enum rtx_code inner_code;
4534:
4535: /* The outer operation can only be one of the following: */
4536: if (code != IOR && code != AND && code != XOR
4537: && code != PLUS && code != MINUS)
4538: return x;
4539:
4540: lhs = XEXP (x, 0), rhs = XEXP (x, 1);
4541:
1.1.1.2 ! root 4542: /* If either operand is a primitive we can't do anything, so get out fast. */
1.1 root 4543: if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
1.1.1.2 ! root 4544: || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
1.1 root 4545: return x;
4546:
4547: lhs = expand_compound_operation (lhs);
4548: rhs = expand_compound_operation (rhs);
4549: inner_code = GET_CODE (lhs);
4550: if (inner_code != GET_CODE (rhs))
4551: return x;
4552:
4553: /* See if the inner and outer operations distribute. */
4554: switch (inner_code)
4555: {
4556: case LSHIFTRT:
4557: case ASHIFTRT:
4558: case AND:
4559: case IOR:
4560: /* These all distribute except over PLUS. */
4561: if (code == PLUS || code == MINUS)
4562: return x;
4563: break;
4564:
4565: case MULT:
4566: if (code != PLUS && code != MINUS)
4567: return x;
4568: break;
4569:
4570: case ASHIFT:
4571: case LSHIFT:
4572: /* These are also multiplies, so they distribute over everything. */
4573: break;
4574:
4575: case SUBREG:
1.1.1.2 ! root 4576: /* Non-paradoxical SUBREGs distributes over all operations, provided
! 4577: the inner modes and word numbers are the same, this is an extraction
! 4578: of a low-order part, and we would not be converting a single-word
! 4579: operation into a multi-word operation. The latter test is not
! 4580: required, but we prevents generating unneeded multi-word operations.
! 4581: Some of the previous tests are redundant given the latter test, but
! 4582: are retained because they are required for correctness.
! 4583:
! 4584: We produce the result slightly differently in this case. */
! 4585:
! 4586: if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
! 4587: || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
! 4588: || ! subreg_lowpart_p (lhs)
! 4589: || (GET_MODE_SIZE (GET_MODE (lhs))
! 4590: < GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
! 4591: || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
1.1 root 4592: return x;
4593:
4594: tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
4595: SUBREG_REG (lhs), SUBREG_REG (rhs));
4596: return gen_lowpart_for_combine (GET_MODE (x), tem);
4597:
4598: default:
4599: return x;
4600: }
4601:
4602: /* Set LHS and RHS to the inner operands (A and B in the example
4603: above) and set OTHER to the common operand (C in the example).
4604: These is only one way to do this unless the inner operation is
4605: commutative. */
4606: if (GET_RTX_CLASS (inner_code) == 'c'
4607: && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
4608: other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
4609: else if (GET_RTX_CLASS (inner_code) == 'c'
4610: && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
4611: other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
4612: else if (GET_RTX_CLASS (inner_code) == 'c'
4613: && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
4614: other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
4615: else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
4616: other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
4617: else
4618: return x;
4619:
4620: /* Form the new inner operation, seeing if it simplifies first. */
4621: tem = gen_binary (code, GET_MODE (x), lhs, rhs);
4622:
4623: /* There is one exception to the general way of distributing:
4624: (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
4625: if (code == XOR && inner_code == IOR)
4626: {
4627: inner_code = AND;
4628: other = gen_unary (NOT, GET_MODE (x), other);
4629: }
4630:
4631: /* We may be able to continuing distributing the result, so call
4632: ourselves recursively on the inner operation before forming the
4633: outer operation, which we return. */
4634: return gen_binary (inner_code, GET_MODE (x),
4635: apply_distributive_law (tem), other);
4636: }
4637:
4638: /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
4639: in MODE.
4640:
4641: Return an equivalent form, if different from X. Otherwise, return X. If
4642: X is zero, we are to always construct the equivalent form. */
4643:
4644: static rtx
4645: simplify_and_const_int (x, mode, varop, constop)
4646: rtx x;
4647: enum machine_mode mode;
4648: rtx varop;
4649: unsigned constop;
4650: {
4651: register enum machine_mode tmode;
4652: register rtx temp;
4653: unsigned significant;
4654:
4655: /* There is a large class of optimizations based on the principle that
4656: some operations produce results where certain bits are known to be zero,
4657: and hence are not significant to the AND. For example, if we have just
4658: done a left shift of one bit, the low-order bit is known to be zero and
4659: hence an AND with a mask of ~1 would not do anything.
4660:
4661: At the end of the following loop, we set:
4662:
4663: VAROP to be the item to be AND'ed with;
4664: CONSTOP to the constant value to AND it with. */
4665:
4666: while (1)
4667: {
4668: /* If we ever encounter a mode wider than the host machine's word
4669: size, we can't compute the masks accurately, so give up. */
4670: if (GET_MODE_BITSIZE (GET_MODE (varop)) > HOST_BITS_PER_INT)
4671: break;
4672:
4673: /* Unless one of the cases below does a `continue',
4674: a `break' will be executed to exit the loop. */
4675:
4676: switch (GET_CODE (varop))
4677: {
4678: case CLOBBER:
4679: /* If VAROP is a (clobber (const_int)), return it since we know
4680: we are generating something that won't match. */
4681: return varop;
4682:
4683: #if ! BITS_BIG_ENDIAN
4684: case USE:
4685: /* VAROP is a (use (mem ..)) that was made from a bit-field
4686: extraction that spanned the boundary of the MEM. If we are
4687: now masking so it is within that boundary, we don't need the
4688: USE any more. */
4689: if ((constop & ~ GET_MODE_MASK (GET_MODE (XEXP (varop, 0)))) == 0)
4690: {
4691: varop = XEXP (varop, 0);
4692: continue;
4693: }
4694: break;
4695: #endif
4696:
4697: case SUBREG:
4698: if (subreg_lowpart_p (varop)
4699: /* We can ignore the effect this SUBREG if it narrows the mode
4700: or, on machines where byte operations zero extend, if the
4701: constant masks to zero all the bits the mode doesn't have. */
4702: && ((GET_MODE_SIZE (GET_MODE (varop))
4703: < GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))))
4704: #ifdef BYTE_LOADS_ZERO_EXTEND
4705: || (0 == (constop
4706: & GET_MODE_MASK (GET_MODE (varop))
4707: & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (varop)))))
4708: #endif
4709: ))
4710: {
4711: varop = SUBREG_REG (varop);
4712: continue;
4713: }
4714: break;
4715:
4716: case ZERO_EXTRACT:
4717: case SIGN_EXTRACT:
4718: case ZERO_EXTEND:
4719: case SIGN_EXTEND:
4720: /* Try to expand these into a series of shifts and then work
4721: with that result. If we can't, for example, if the extract
4722: isn't at a fixed position, give up. */
4723: temp = expand_compound_operation (varop);
4724: if (temp != varop)
4725: {
4726: varop = temp;
4727: continue;
4728: }
4729: break;
4730:
4731: case AND:
4732: if (GET_CODE (XEXP (varop, 1)) == CONST_INT)
4733: {
4734: constop &= INTVAL (XEXP (varop, 1));
4735: varop = XEXP (varop, 0);
4736: continue;
4737: }
4738: break;
4739:
4740: case IOR:
4741: case XOR:
4742: /* If VAROP is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
4743: LSHIFT so we end up with an (and (lshiftrt (ior ...) ...) ...)
4744: operation which may be a bitfield extraction. */
4745:
4746: if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT
4747: && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
4748: && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0
4749: && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_INT
4750: && GET_CODE (XEXP (varop, 1)) == CONST_INT
4751: && (INTVAL (XEXP (varop, 1))
4752: & ~ significant_bits (XEXP (varop, 0),
4753: GET_MODE (varop)) == 0))
4754: {
4755: temp = gen_rtx (CONST_INT, VOIDmode,
4756: ((INTVAL (XEXP (varop, 1)) & constop)
4757: << INTVAL (XEXP (XEXP (varop, 0), 1))));
4758: temp = gen_binary (GET_CODE (varop), GET_MODE (varop),
4759: XEXP (XEXP (varop, 0), 0), temp);
4760: varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
4761: temp, XEXP (varop, 1));
4762: continue;
4763: }
4764:
4765: /* Apply the AND to both branches of the IOR or XOR, then try to
4766: apply the distributive law. This may eliminate operations
4767: if either branch can be simplified because of the AND.
4768: It may also make some cases more complex, but those cases
4769: probably won't match a pattern either with or without this. */
4770: return
4771: gen_lowpart_for_combine
4772: (mode, apply_distributive_law
4773: (gen_rtx_combine
4774: (GET_CODE (varop), GET_MODE (varop),
4775: simplify_and_const_int (0, GET_MODE (varop),
4776: XEXP (varop, 0), constop),
4777: simplify_and_const_int (0, GET_MODE (varop),
4778: XEXP (varop, 1), constop))));
4779:
4780: case NOT:
4781: /* (and (not FOO)) is (and (xor FOO CONST_OP)) so if FOO is an
4782: LSHIFTRT we can do the same as above. */
4783:
4784: if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT
4785: && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
4786: && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0
4787: && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_INT)
4788: {
4789: temp = gen_rtx (CONST_INT, VOIDmode,
4790: constop << INTVAL (XEXP (XEXP (varop, 0), 1)));
4791: temp = gen_binary (XOR, GET_MODE (varop),
4792: XEXP (XEXP (varop, 0), 0), temp);
4793: varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
4794: temp, XEXP (XEXP (varop, 0), 1));
4795: continue;
4796: }
4797: break;
4798:
4799: case ASHIFTRT:
4800: /* If we are just looking for the sign bit, we don't need this
4801: shift at all, even if it has a variable count. */
4802: if (constop == 1 << (GET_MODE_BITSIZE (GET_MODE (varop)) - 1))
4803: {
4804: varop = XEXP (varop, 0);
4805: continue;
4806: }
4807:
4808: /* If this is a shift by a constant, get a mask that contains
4809: those bits that are not copies of the sign bit. We then have
4810: two cases: If CONSTOP only includes those bits, this can be
4811: a logical shift, which may allow simplifications. If CONSTOP
4812: is a single-bit field not within those bits, we are requesting
4813: a copy of the sign bit and hence can shift the sign bit to
4814: the appropriate location. */
4815: if (GET_CODE (XEXP (varop, 1)) == CONST_INT
4816: && INTVAL (XEXP (varop, 1)) >= 0
4817: && INTVAL (XEXP (varop, 1)) < HOST_BITS_PER_INT)
4818: {
4819: int i = -1;
4820:
4821: significant = GET_MODE_MASK (GET_MODE (varop));
4822: significant >>= INTVAL (XEXP (varop, 1));
4823:
4824: if ((constop & ~significant) == 0
4825: || (i = exact_log2 (constop)) >= 0)
4826: {
4827: varop = simplify_shift_const
4828: (varop, LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
4829: i < 0 ? INTVAL (XEXP (varop, 1))
4830: : GET_MODE_BITSIZE (GET_MODE (varop)) - 1 - i);
4831: if (GET_CODE (varop) != ASHIFTRT)
4832: continue;
4833: }
4834: }
4835:
4836: /* If our mask is 1, convert this to a LSHIFTRT. This can be done
4837: even if the shift count isn't a constant. */
4838: if (constop == 1)
4839: varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
4840: XEXP (varop, 0), XEXP (varop, 1));
4841: break;
4842:
4843: case NE:
4844: /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is
4845: included in STORE_FLAG_VALUE and FOO has no significant bits
4846: not in CONST. */
4847: if ((constop & ~ STORE_FLAG_VALUE) == 0
4848: && XEXP (varop, 0) == const0_rtx
4849: && (significant_bits (XEXP (varop, 0), mode) & ~ constop) == 0)
4850: {
4851: varop = XEXP (varop, 0);
4852: continue;
4853: }
4854: break;
4855:
4856: case PLUS:
4857: /* In (and (plus FOO C1) M), if M is a mask that just turns off
4858: low-order bits (as in an alignment operation) and FOO is already
4859: aligned to that boundary, we can convert remove this AND
4860: and possibly the PLUS if it is now adding zero. */
4861: if (GET_CODE (XEXP (varop, 1)) == CONST_INT
4862: && exact_log2 (-constop) >= 0
4863: && (significant_bits (XEXP (varop, 0), mode) & ~ constop) == 0)
4864: {
4865: varop = plus_constant (XEXP (varop, 0),
4866: INTVAL (XEXP (varop, 1)) & constop);
4867: constop = ~0;
4868: break;
4869: }
4870:
4871: /* ... fall through ... */
4872:
4873: case MINUS:
4874: /* In (and (plus (and FOO M1) BAR) M2), if M1 and M2 are one
4875: less than powers of two and M2 is narrower than M1, we can
4876: eliminate the inner AND. This occurs when incrementing
4877: bit fields. */
4878:
4879: if (GET_CODE (XEXP (varop, 0)) == ZERO_EXTRACT
4880: || GET_CODE (XEXP (varop, 0)) == ZERO_EXTEND)
4881: SUBST (XEXP (varop, 0),
4882: expand_compound_operation (XEXP (varop, 0)));
4883:
4884: if (GET_CODE (XEXP (varop, 0)) == AND
4885: && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
4886: && exact_log2 (constop + 1) >= 0
4887: && exact_log2 (INTVAL (XEXP (XEXP (varop, 0), 1)) + 1) >= 0
4888: && (~ INTVAL (XEXP (XEXP (varop, 0), 1)) & constop) == 0)
4889: SUBST (XEXP (varop, 0), XEXP (XEXP (varop, 0), 0));
4890: break;
4891: }
4892:
4893: break;
4894: }
4895:
4896: /* If we have reached a constant, this whole thing is constant. */
4897: if (GET_CODE (varop) == CONST_INT)
4898: return gen_rtx (CONST_INT, VOIDmode, constop & INTVAL (varop));
4899:
4900: /* See what bits are significant in VAROP. */
4901: significant = significant_bits (varop, mode);
4902:
4903: /* Turn off all bits in the constant that are known to already be zero.
4904: Thus, if the AND isn't needed at all, we will have CONSTOP == SIGNIFICANT
4905: which is tested below. */
4906:
4907: constop &= significant;
4908:
4909: /* If we don't have any bits left, return zero. */
4910: if (constop == 0)
4911: return const0_rtx;
4912:
4913: /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
4914: if we already had one (just check for the simplest cases). */
4915: if (x && GET_CODE (XEXP (x, 0)) == SUBREG
4916: && GET_MODE (XEXP (x, 0)) == mode
4917: && SUBREG_REG (XEXP (x, 0)) == varop)
4918: varop = XEXP (x, 0);
4919: else
4920: varop = gen_lowpart_for_combine (mode, varop);
4921:
4922: /* If we can't make the SUBREG, try to return what we were given. */
4923: if (GET_CODE (varop) == CLOBBER)
4924: return x ? x : varop;
4925:
4926: /* If we are only masking insignificant bits, return VAROP. */
4927: if (constop == significant)
4928: x = varop;
4929:
4930: /* Otherwise, return an AND. See how much, if any, of X we can use. */
4931: else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
4932: x = gen_rtx_combine (AND, mode, varop,
4933: gen_rtx (CONST_INT, VOIDmode, constop));
4934:
4935: else
4936: {
4937: if (GET_CODE (XEXP (x, 1)) != CONST_INT
4938: || INTVAL (XEXP (x, 1)) != constop)
4939: SUBST (XEXP (x, 1), gen_rtx (CONST_INT, VOIDmode, constop));
4940:
4941: SUBST (XEXP (x, 0), varop);
4942: }
4943:
4944: return x;
4945: }
4946:
4947: /* Given an expression, X, compute which bits in X can be non-zero.
4948: We don't care about bits outside of those defined in MODE.
4949:
4950: For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
4951: a shift, AND, or zero_extract, we can do better. */
4952:
4953: static unsigned
4954: significant_bits (x, mode)
4955: rtx x;
4956: enum machine_mode mode;
4957: {
4958: unsigned significant = GET_MODE_MASK (mode);
4959: unsigned inner_sig;
4960: enum rtx_code code;
4961: int mode_width = GET_MODE_BITSIZE (mode);
4962: rtx tem;
4963:
4964: /* If X is wider than MODE, use its mode instead. */
4965: if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
4966: {
4967: mode = GET_MODE (x);
4968: significant = GET_MODE_MASK (mode);
4969: mode_width = GET_MODE_BITSIZE (mode);
4970: }
4971:
4972: if (mode_width > HOST_BITS_PER_INT)
4973: /* Our only callers in this case look for single bit values. So
4974: just return the mode mask. Those tests will then be false. */
4975: return significant;
4976:
4977: code = GET_CODE (x);
4978: switch (code)
4979: {
4980: case REG:
4981: #ifdef STACK_BOUNDARY
4982: /* If this is the stack pointer, we may know something about its
4983: alignment. If PUSH_ROUNDING is defined, it is possible for the
4984: stack to be momentarily aligned only to that amount, so we pick
4985: the least alignment. */
4986:
4987: if (x == stack_pointer_rtx)
4988: {
4989: int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
4990:
4991: #ifdef PUSH_ROUNDING
4992: sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
4993: #endif
4994:
4995: return significant & ~ (sp_alignment - 1);
4996: }
4997: #endif
4998:
4999: /* If X is a register whose value we can find, use that value.
5000: Otherwise, use the previously-computed significant bits for this
5001: register. */
5002:
5003: tem = get_last_value (x);
5004: if (tem)
5005: return significant_bits (tem, mode);
5006: else if (significant_valid && reg_significant[REGNO (x)])
5007: return reg_significant[REGNO (x)] & significant;
5008: else
5009: return significant;
5010:
5011: case CONST_INT:
5012: return INTVAL (x);
5013:
5014: #ifdef BYTE_LOADS_ZERO_EXTEND
5015: case MEM:
5016: /* In many, if not most, RISC machines, reading a byte from memory
5017: zeros the rest of the register. Noticing that fact saves a lot
5018: of extra zero-extends. */
5019: significant &= GET_MODE_MASK (GET_MODE (x));
5020: break;
5021: #endif
5022:
5023: #if STORE_FLAG_VALUE == 1
5024: case EQ: case NE:
5025: case GT: case GTU:
5026: case LT: case LTU:
5027: case GE: case GEU:
5028: case LE: case LEU:
5029: significant = 1;
5030:
5031: /* A comparison operation only sets the bits given by its mode. The
5032: rest are set undefined. */
5033: if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
5034: significant |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
5035: break;
5036: #endif
5037:
5038: #if STORE_FLAG_VALUE == -1
5039: case NEG:
5040: if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5041: || ((tem = get_last_value (XEXP (x, 0))) != 0
5042: && GET_RTX_CLASS (GET_CODE (tem)) == '<'))
5043: significant = 1;
5044:
5045: if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
5046: significant |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
5047: break;
5048: #endif
5049:
5050: case TRUNCATE:
5051: significant &= (significant_bits (XEXP (x, 0), mode)
5052: & GET_MODE_MASK (mode));
5053: break;
5054:
5055: case ZERO_EXTEND:
5056: significant &= significant_bits (XEXP (x, 0), mode);
5057: if (GET_MODE (XEXP (x, 0)) != VOIDmode)
5058: significant &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
5059: break;
5060:
5061: case SIGN_EXTEND:
5062: /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
5063: Otherwise, show all the bits in the outer mode but not the inner
5064: may be non-zero. */
5065: inner_sig = significant_bits (XEXP (x, 0), mode);
5066: if (GET_MODE (XEXP (x, 0)) != VOIDmode)
5067: {
5068: inner_sig &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
5069: if (inner_sig &
5070: (1 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
5071: inner_sig |= (GET_MODE_MASK (mode)
5072: & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
5073: }
5074:
5075: significant &= inner_sig;
5076: break;
5077:
5078: case AND:
5079: significant &= (significant_bits (XEXP (x, 0), mode)
5080: & significant_bits (XEXP (x, 1), mode));
5081: break;
5082:
5083: case XOR:
5084: case IOR:
5085: significant &= (significant_bits (XEXP (x, 0), mode)
5086: | significant_bits (XEXP (x, 1), mode));
5087: break;
5088:
5089: case PLUS: case MINUS:
5090: case MULT:
5091: case DIV: case UDIV:
5092: case MOD: case UMOD:
5093: /* We can apply the rules of arithmetic to compute the number of
5094: high- and low-order zero bits of these operations. We start by
5095: computing the width (position of the highest-order non-zero bit)
5096: and the number of low-order zero bits for each value. */
5097: {
5098: unsigned sig0 = significant_bits (XEXP (x, 0), mode);
5099: unsigned sig1 = significant_bits (XEXP (x, 1), mode);
5100: int width0 = floor_log2 (sig0) + 1;
5101: int width1 = floor_log2 (sig1) + 1;
5102: int low0 = floor_log2 (sig0 & -sig0);
5103: int low1 = floor_log2 (sig1 & -sig1);
5104: int op0_maybe_minusp = (sig0 & (1 << (mode_width - 1)));
5105: int op1_maybe_minusp = (sig1 & (1 << (mode_width - 1)));
5106: int result_width = mode_width;
5107: int result_low = 0;
5108:
5109: switch (code)
5110: {
5111: case PLUS:
5112: result_width = MAX (width0, width1) + 1;
5113: result_low = MIN (low0, low1);
5114: break;
5115: case MINUS:
5116: result_low = MIN (low0, low1);
5117: break;
5118: case MULT:
5119: result_width = width0 + width1;
5120: result_low = low0 + low1;
5121: break;
5122: case DIV:
5123: if (! op0_maybe_minusp && ! op1_maybe_minusp)
5124: result_width = width0;
5125: break;
5126: case UDIV:
5127: result_width = width0;
5128: break;
5129: case MOD:
5130: if (! op0_maybe_minusp && ! op1_maybe_minusp)
5131: result_width = MIN (width0, width1);
5132: result_low = MIN (low0, low1);
5133: break;
5134: case UMOD:
5135: result_width = MIN (width0, width1);
5136: result_low = MIN (low0, low1);
5137: break;
5138: }
5139:
5140: if (result_width < mode_width)
5141: significant &= (1 << result_width) - 1;
5142:
5143: if (result_low > 0)
5144: significant &= ~ ((1 << result_low) - 1);
5145: }
5146: break;
5147:
5148: case ZERO_EXTRACT:
5149: if (GET_CODE (XEXP (x, 1)) == CONST_INT
5150: && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_INT)
5151: significant &= (1 << INTVAL (XEXP (x, 1))) - 1;
5152: break;
5153:
5154: case SUBREG:
5155: /* If the inner mode is a single word for both the host and target
5156: machines, we can compute this from which bits of the inner
5157: object are known significant. */
5158: if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
5159: && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= HOST_BITS_PER_INT)
5160: {
5161: significant &= significant_bits (SUBREG_REG (x), mode);
5162: #ifndef BYTE_LOADS_ZERO_EXTEND
5163: /* On many CISC machines, accessing an object in a wider mode
5164: causes the high-order bits to become undefined. So they are
5165: not known to be zero. */
5166: if (GET_MODE_SIZE (GET_MODE (x))
5167: > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
5168: significant |= (GET_MODE_MASK (GET_MODE (x))
5169: & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
5170: #endif
5171: }
5172: break;
5173:
5174: case ASHIFTRT:
5175: case LSHIFTRT:
5176: case ASHIFT:
5177: case LSHIFT:
5178: case ROTATE:
5179: /* The significant bits are in two classes: any bits within MODE
5180: that aren't in GET_MODE (x) are always significant. The rest of the
5181: significant bits are those that are significant in the operand of
5182: the shift when shifted the appropriate number of bits. This
5183: shows that high-order bits are cleared by the right shift and
5184: low-order bits by left shifts. */
5185: if (GET_CODE (XEXP (x, 1)) == CONST_INT
5186: && INTVAL (XEXP (x, 1)) >= 0
5187: && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_INT)
5188: {
5189: enum machine_mode inner_mode = GET_MODE (x);
5190: int width = GET_MODE_BITSIZE (inner_mode);
5191: int count = INTVAL (XEXP (x, 1));
5192: unsigned mode_mask = GET_MODE_MASK (inner_mode);
5193: unsigned op_significant = significant_bits (XEXP (x, 0), mode);
5194: unsigned inner = op_significant & mode_mask;
5195: unsigned outer = 0;
5196:
5197: if (mode_width > width)
5198: outer = (op_significant & significant & ~ mode_mask);
5199:
5200: if (code == LSHIFTRT)
5201: inner >>= count;
5202: else if (code == ASHIFTRT)
5203: {
5204: inner >>= count;
5205:
5206: /* If the sign bit was significant at before the shift, we
5207: need to mark all the places it could have been copied to
5208: by the shift significant. */
5209: if (inner & (1 << (width - 1 - count)))
5210: inner |= ((1 << count) - 1) << (width - count);
5211: }
5212: else if (code == LSHIFT || code == ASHIFT)
5213: inner <<= count;
5214: else
5215: inner = ((inner << (count % width)
5216: | (inner >> (width - (count % width)))) & mode_mask);
5217:
5218: significant &= (outer | inner);
5219: }
5220: break;
5221:
5222: case FFS:
5223: /* This is at most the number of bits in the mode. */
5224: significant = (1 << (floor_log2 (mode_width) + 1)) - 1;
5225: break;
5226: }
5227:
5228: return significant;
5229: }
5230:
5231: /* This function is called from `simplify_shift_const' to merge two
5232: outer operations. Specifically, we have already found that we need
5233: to perform operation *POP0 with constant *PCONST0 at the outermost
5234: position. We would now like to also perform OP1 with constant CONST1
5235: (with *POP0 being done last).
5236:
5237: Return 1 if we can do the operation and update *POP0 and *PCONST0 with
5238: the resulting operation. *PCOMP_P is set to 1 if we would need to
5239: complement the innermost operand, otherwise it is unchanged.
5240:
5241: MODE is the mode in which the operation will be done. No bits outside
5242: the width of this mode matter. It is assumed that the width of this mode
5243: is smaller than or equal to HOST_BITS_PER_INT.
5244:
5245: If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
5246: IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
5247: result is simply *PCONST0.
5248:
5249: If the resulting operation cannot be expressed as one operation, we
5250: return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
5251:
5252: static int
5253: merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
5254: enum rtx_code *pop0;
5255: int *pconst0;
5256: enum rtx_code op1;
5257: int const1;
5258: enum machine_mode mode;
5259: int *pcomp_p;
5260: {
5261: enum rtx_code op0 = *pop0;
5262: int const0 = *pconst0;
5263:
5264: const0 &= GET_MODE_MASK (mode);
5265: const1 &= GET_MODE_MASK (mode);
5266:
5267: /* If OP0 is an AND, clear unimportant bits in CONST1. */
5268: if (op0 == AND)
5269: const1 &= const0;
5270:
5271: /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
5272: if OP0 is SET. */
5273:
5274: if (op1 == NIL || op0 == SET)
5275: return 1;
5276:
5277: else if (op0 == NIL)
5278: op0 = op1, const0 = const1;
5279:
5280: else if (op0 == op1)
5281: {
5282: switch (op0)
5283: {
5284: case AND:
5285: const0 &= const1;
5286: break;
5287: case IOR:
5288: const0 |= const1;
5289: break;
5290: case XOR:
5291: const0 ^= const1;
5292: break;
5293: case PLUS:
5294: const0 += const1;
5295: break;
5296: case NEG:
5297: op0 = NIL;
5298: break;
5299: }
5300: }
5301:
5302: /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
5303: else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
5304: return 0;
5305:
5306: /* If the two constants aren't the same, we can't do anything. The
5307: remaining six cases can all be done. */
5308: else if (const0 != const1)
5309: return 0;
5310:
5311: else
5312: switch (op0)
5313: {
5314: case IOR:
5315: if (op1 == AND)
5316: /* (a & b) | b == b */
5317: op0 = SET;
5318: else /* op1 == XOR */
5319: /* (a ^ b) | b == a | b */
5320: ;
5321: break;
5322:
5323: case XOR:
5324: if (op1 == AND)
5325: /* (a & b) ^ b == (~a) & b */
5326: op0 = AND, *pcomp_p = 1;
5327: else /* op1 == IOR */
5328: /* (a | b) ^ b == a & ~b */
5329: op0 = AND, *pconst0 = ~ const0;
5330: break;
5331:
5332: case AND:
5333: if (op1 == IOR)
5334: /* (a | b) & b == b */
5335: op0 = SET;
5336: else /* op1 == XOR */
5337: /* (a ^ b) & b) == (~a) & b */
5338: *pcomp_p = 1;
5339: break;
5340: }
5341:
5342: /* Check for NO-OP cases. */
5343: const0 &= GET_MODE_MASK (mode);
5344: if (const0 == 0
5345: && (op0 == IOR || op0 == XOR || op0 == PLUS))
5346: op0 = NIL;
5347: else if (const0 == 0 && op0 == AND)
5348: op0 = SET;
5349: else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
5350: op0 = NIL;
5351:
5352: *pop0 = op0;
5353: *pconst0 = const0;
5354:
5355: return 1;
5356: }
5357:
5358: /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
5359: The result of the shift is RESULT_MODE. X, if non-zero, is an expression
5360: that we started with.
5361:
5362: The shift is normally computed in the widest mode we find in VAROP, as
5363: long as it isn't a different number of words than RESULT_MODE. Exceptions
5364: are ASHIFTRT and ROTATE, which are always done in their original mode, */
5365:
5366: static rtx
5367: simplify_shift_const (x, code, result_mode, varop, count)
5368: rtx x;
5369: enum rtx_code code;
5370: enum machine_mode result_mode;
5371: rtx varop;
5372: int count;
5373: {
5374: enum rtx_code orig_code = code;
5375: int orig_count = count;
5376: enum machine_mode mode = result_mode;
5377: enum machine_mode shift_mode, tmode;
5378: int mode_words
5379: = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
5380: /* We form (outer_op (code varop count) (outer_const)). */
5381: enum rtx_code outer_op = NIL;
5382: int outer_const;
5383: rtx const_rtx;
5384: int complement_p = 0;
5385: rtx new;
5386:
5387: /* If we were given an invalid count, don't do anything except exactly
5388: what was requested. */
5389:
5390: if (count < 0 || count > GET_MODE_BITSIZE (mode))
5391: {
5392: if (x)
5393: return x;
5394:
5395: return gen_rtx (code, mode, varop, gen_rtx (CONST_INT, VOIDmode, count));
5396: }
5397:
5398: /* Unless one of the branches of the `if' in this loop does a `continue',
5399: we will `break' the loop after the `if'. */
5400:
5401: while (count != 0)
5402: {
5403: /* If we have an operand of (clobber (const_int 0)), just return that
5404: value. */
5405: if (GET_CODE (varop) == CLOBBER)
5406: return varop;
5407:
5408: /* If we discovered we had to complement VAROP, leave. Making a NOT
5409: here would cause an infinite loop. */
5410: if (complement_p)
5411: break;
5412:
5413: /* Convert ROTATETRT to ROTATE. */
5414: if (code == ROTATERT)
5415: code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
5416:
5417: /* Canonicalize LSHIFT to ASHIFT. */
5418: if (code == LSHIFT)
5419: code = ASHIFT;
5420:
5421: /* We need to determine what mode we will do the shift in. If the
5422: shift is a ASHIFTRT or ROTATE, we must always do it in the mode it
5423: was originally done in. Otherwise, we can do it in MODE, the widest
5424: mode encountered. */
5425: shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
5426:
5427: /* Handle cases where the count is greater than the size of the mode
5428: minus 1. For ASHIFT, use the size minus one as the count (this can
5429: occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
5430: take the count modulo the size. For other shifts, the result is
5431: zero.
5432:
5433: Since these shifts are being produced by the compiler by combining
5434: multiple operations, each of which are defined, we know what the
5435: result is supposed to be. */
5436:
5437: if (count > GET_MODE_BITSIZE (shift_mode) - 1)
5438: {
5439: if (code == ASHIFTRT)
5440: count = GET_MODE_BITSIZE (shift_mode) - 1;
5441: else if (code == ROTATE || code == ROTATERT)
5442: count %= GET_MODE_BITSIZE (shift_mode);
5443: else
5444: {
5445: /* We can't simply return zero because there may be an
5446: outer op. */
5447: varop = const0_rtx;
5448: count = 0;
5449: break;
5450: }
5451: }
5452:
5453: /* Negative counts are invalid and should not have been made (a
5454: programmer-specified negative count should have been handled
5455: above). */
5456: else if (count < 0)
5457: abort ();
5458:
5459: /* We simplify the tests below and elsewhere by converting
5460: ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
5461: `make_compound_operation' will convert it to a ASHIFTRT for
5462: those machines (such as Vax) that don't have a LSHIFTRT. */
5463: if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_INT
5464: && code == ASHIFTRT
5465: && (significant_bits (varop, shift_mode)
5466: & (1 << (GET_MODE_BITSIZE (shift_mode) - 1))) == 0)
5467: code = LSHIFTRT;
5468:
5469: switch (GET_CODE (varop))
5470: {
5471: case SIGN_EXTEND:
5472: case ZERO_EXTEND:
5473: case SIGN_EXTRACT:
5474: case ZERO_EXTRACT:
5475: new = expand_compound_operation (varop);
5476: if (new != varop)
5477: {
5478: varop = new;
5479: continue;
5480: }
5481: break;
5482:
5483: case MEM:
5484: /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
5485: minus the width of a smaller mode, we can do this with a
5486: SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
5487: if ((code == ASHIFTRT || code == LSHIFTRT)
5488: && ! mode_dependent_address_p (XEXP (varop, 0))
5489: && ! MEM_VOLATILE_P (varop)
5490: && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
5491: MODE_INT, 1)) != BLKmode)
5492: {
5493: #if BYTES_BIG_ENDIAN
5494: new = gen_rtx (MEM, tmode, XEXP (varop, 0));
5495: #else
5496: new = gen_rtx (MEM, tmode,
5497: plus_constant (XEXP (varop, 0),
5498: count / BITS_PER_UNIT));
5499: RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
5500: MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
5501: MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
5502: #endif
5503: varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
5504: : ZERO_EXTEND, mode, new);
5505: count = 0;
5506: continue;
5507: }
5508: break;
5509:
5510: case USE:
5511: /* Similar to the case above, except that we can only do this if
5512: the resulting mode is the same as that of the underlying
5513: MEM and adjust the address depending on the *bits* endianness
5514: because of the way that bit-field extract insns are defined. */
5515: if ((code == ASHIFTRT || code == LSHIFTRT)
5516: && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
5517: MODE_INT, 1)) != BLKmode
5518: && tmode == GET_MODE (XEXP (varop, 0)))
5519: {
5520: #if BITS_BIG_ENDIAN
5521: new = XEXP (varop, 0);
5522: #else
5523: new = copy_rtx (XEXP (varop, 0));
5524: SUBST (XEXP (new, 0),
5525: plus_constant (XEXP (new, 0),
5526: count / BITS_PER_UNIT));
5527: #endif
5528:
5529: varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
5530: : ZERO_EXTEND, mode, new);
5531: count = 0;
5532: continue;
5533: }
5534: break;
5535:
5536: case SUBREG:
5537: /* If VAROP is a SUBREG, strip it as long as the inner operand has
5538: the same number of words as what we've seen so far. Then store
5539: the widest mode in MODE. */
5540: if (SUBREG_WORD (varop) == 0
5541: && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
5542: + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5543: == mode_words))
5544: {
5545: varop = SUBREG_REG (varop);
5546: if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
5547: mode = GET_MODE (varop);
5548: continue;
5549: }
5550: break;
5551:
5552: case MULT:
5553: /* Some machines use MULT instead of ASHIFT because MULT
5554: is cheaper. But it is still better on those machines to
5555: merge two shifts into one. */
5556: if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5557: && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
5558: {
5559: varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
5560: gen_rtx (CONST_INT, VOIDmode,
5561: exact_log2 (INTVAL (XEXP (varop, 1)))));
5562: continue;
5563: }
5564: break;
5565:
5566: case UDIV:
5567: /* Similar, for when divides are cheaper. */
5568: if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5569: && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
5570: {
5571: varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
5572: gen_rtx (CONST_INT, VOIDmode,
5573: exact_log2 (INTVAL (XEXP (varop, 1)))));
5574: continue;
5575: }
5576: break;
5577:
5578: case ASHIFTRT:
5579: /* If we are extracting just the sign bit of an arithmetic right
5580: shift, that shift is not needed. */
5581: if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
5582: {
5583: varop = XEXP (varop, 0);
5584: continue;
5585: }
5586:
5587: /* ... fall through ... */
5588:
5589: case LSHIFTRT:
5590: case ASHIFT:
5591: case LSHIFT:
5592: case ROTATE:
5593: /* Here we have two nested shifts. The result is usually the
5594: AND of a new shift with a mask. We compute the result below. */
5595: if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5596: && INTVAL (XEXP (varop, 1)) >= 0
5597: && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
5598: && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_INT
5599: && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT)
5600: {
5601: enum rtx_code first_code = GET_CODE (varop);
5602: int first_count = INTVAL (XEXP (varop, 1));
5603: unsigned int mask;
5604: rtx mask_rtx;
5605: rtx inner;
5606:
5607: if (first_code == LSHIFT)
5608: first_code = ASHIFT;
5609:
5610: /* We have one common special case. We can't do any merging if
5611: the inner code is an ASHIFTRT of a smaller mode. However, if
5612: we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
5613: with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
5614: we can convert it to
5615: (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
5616: This simplifies certain SIGN_EXTEND operations. */
5617: if (code == ASHIFT && first_code == ASHIFTRT
5618: && (GET_MODE_BITSIZE (result_mode)
5619: - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
5620: {
5621: /* C3 has the low-order C1 bits zero. */
5622:
5623: mask = GET_MODE_MASK (mode) & ~ ((1 << first_count) - 1);
5624:
5625: varop = simplify_and_const_int (0, result_mode,
5626: XEXP (varop, 0), mask);
5627: varop = simplify_shift_const (0, ASHIFT, result_mode,
5628: varop, count);
5629: count = first_count;
5630: code = ASHIFTRT;
5631: continue;
5632: }
5633:
5634: /* If this was (ashiftrt (ashift foo C1) C2) and we know
5635: something about FOO's previous value, we may be able to
5636: optimize this even though the code below can't handle this
5637: case.
5638:
5639: If FOO has J high-order bits equal to the sign bit with
5640: J > C1, then we can convert this to either an ASHIFT or
5641: a ASHIFTRT depending on the two counts.
5642:
5643: We cannot do this if VAROP's mode is not SHIFT_MODE. */
5644:
5645: if (code == ASHIFTRT && first_code == ASHIFT
5646: && GET_MODE (varop) == shift_mode
5647: && (inner = get_last_value (XEXP (varop, 0))) != 0)
5648: {
5649: if ((GET_CODE (inner) == CONST_INT
5650: && (INTVAL (inner) >> (HOST_BITS_PER_INT - (first_count + 1)) == 0
5651: || (INTVAL (inner) >> (HOST_BITS_PER_INT - (first_count + 1)) == -1)))
5652: || (GET_CODE (inner) == SIGN_EXTEND
5653: && ((GET_MODE_BITSIZE (GET_MODE (inner))
5654: - GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner))))
5655: >= first_count))
5656: || (GET_CODE (inner) == ASHIFTRT
5657: && GET_CODE (XEXP (inner, 1)) == CONST_INT
5658: && INTVAL (XEXP (inner, 1)) >= first_count))
5659: {
5660: count -= first_count;
5661: if (count < 0)
5662: count = - count, code = ASHIFT;
5663: varop = XEXP (varop, 0);
5664: continue;
5665: }
5666: }
5667:
5668: /* There are some cases we can't do. If CODE is ASHIFTRT,
5669: we can only do this if FIRST_CODE is also ASHIFTRT.
5670:
5671: We can't do the case when CODE is ROTATE and FIRST_CODE is
5672: ASHIFTRT.
5673:
5674: If the mode of this shift is not the mode of the outer shift,
5675: we can't do this if either shift is ASHIFTRT or ROTATE.
5676:
5677: Finally, we can't do any of these if the mode is too wide
5678: unless the codes are the same.
5679:
5680: Handle the case where the shift codes are the same
5681: first. */
5682:
5683: if (code == first_code)
5684: {
5685: if (GET_MODE (varop) != result_mode
5686: && (code == ASHIFTRT || code == ROTATE))
5687: break;
5688:
5689: count += first_count;
5690: varop = XEXP (varop, 0);
5691: continue;
5692: }
5693:
5694: if (code == ASHIFTRT
5695: || (code == ROTATE && first_code == ASHIFTRT)
5696: || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_INT
5697: || (GET_MODE (varop) != result_mode
5698: && (first_code == ASHIFTRT || first_code == ROTATE
5699: || code == ROTATE)))
5700: break;
5701:
5702: /* To compute the mask to apply after the shift, shift the
5703: significant bits of the inner shift the same way the
5704: outer shift will. */
5705:
5706: mask_rtx = gen_rtx (CONST_INT, VOIDmode,
5707: significant_bits (varop, GET_MODE (varop)));
5708:
5709: mask_rtx
5710: = simplify_binary_operation (code, result_mode, mask_rtx,
5711: gen_rtx (CONST_INT, VOIDmode,
5712: count));
5713:
5714: /* Give up if we can't compute an outer operation to use. */
5715: if (mask_rtx == 0
5716: || GET_CODE (mask_rtx) != CONST_INT
5717: || ! merge_outer_ops (&outer_op, &outer_const, AND,
5718: INTVAL (mask_rtx),
5719: result_mode, &complement_p))
5720: break;
5721:
5722: /* If the shifts are in the same direction, we add the
5723: counts. Otherwise, we subtract them. */
5724: if ((code == ASHIFTRT || code == LSHIFTRT)
5725: == (first_code == ASHIFTRT || first_code == LSHIFTRT))
5726: count += first_count;
5727: else
5728: count -= first_count;
5729:
5730: /* If COUNT is positive, the new shift is usually CODE,
5731: except for the two exceptions below, in which case it is
5732: FIRST_CODE. If the count is negative, FIRST_CODE should
5733: always be used */
5734: if (count > 0
5735: && ((first_code == ROTATE && code == ASHIFT)
5736: || (first_code == ASHIFTRT && code == LSHIFTRT)))
5737: code = first_code;
5738: else if (count < 0)
5739: code = first_code, count = - count;
5740:
5741: varop = XEXP (varop, 0);
5742: continue;
5743: }
5744:
5745: /* If we have (A << B << C) for any shift, we can convert this to
5746: (A << C << B). This wins if A is a constant. Only try this if
5747: B is not a constant. */
5748:
5749: else if (GET_CODE (varop) == code
5750: && GET_CODE (XEXP (varop, 1)) != CONST_INT
5751: && 0 != (new
5752: = simplify_binary_operation (code, mode,
5753: XEXP (varop, 0),
5754: gen_rtx (CONST_INT,
5755: VOIDmode,
5756: count))))
5757: {
5758: varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
5759: count = 0;
5760: continue;
5761: }
5762: break;
5763:
5764: case NOT:
5765: /* Make this fit the case below. */
5766: varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
5767: gen_rtx (CONST_INT, VOIDmode,
5768: GET_MODE_MASK (mode)));
5769: continue;
5770:
5771: case IOR:
5772: case AND:
5773: case XOR:
5774: /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
5775: with C the size of VAROP - 1 and the shift is logical if
5776: STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
5777: we have an (le X 0) operation. If we have an arithmetic shift
5778: and STORE_FLAG_VALUE is 1 or we have a logical shift with
5779: STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
5780:
5781: if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
5782: && XEXP (XEXP (varop, 0), 1) == constm1_rtx
5783: && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5784: && (code == LSHIFTRT || code == ASHIFTRT)
5785: && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
5786: && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
5787: {
5788: count = 0;
5789: varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
5790: const0_rtx);
5791:
5792: if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
5793: varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
5794:
5795: continue;
5796: }
5797:
5798: /* If we have (shift (logical)), move the logical to the outside
5799: to allow it to possibly combine with another logical and the
5800: shift to combine with another shift. This also canonicalizes to
5801: what a ZERO_EXTRACT looks like. Also, some machines have
5802: (and (shift)) insns. */
5803:
5804: if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5805: && (new = simplify_binary_operation (code, result_mode,
5806: XEXP (varop, 1),
5807: gen_rtx (CONST_INT,
5808: VOIDmode,
5809: count))) != 0
5810: && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
5811: INTVAL (new), result_mode, &complement_p))
5812: {
5813: varop = XEXP (varop, 0);
5814: continue;
5815: }
5816:
5817: /* If we can't do that, try to simplify the shift in each arm of the
5818: logical expression, make a new logical expression, and apply
5819: the inverse distributive law. */
5820: {
5821: rtx lhs = simplify_shift_const (0, code, result_mode,
5822: XEXP (varop, 0), count);
5823: rtx rhs = simplify_shift_const (0, code, result_mode,
5824: XEXP (varop, 1), count);
5825:
5826: varop = gen_binary (GET_CODE (varop), result_mode, lhs, rhs);
5827: varop = apply_distributive_law (varop);
5828:
5829: count = 0;
5830: }
5831: break;
5832:
5833: case EQ:
5834: /* convert (lshift (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
5835: says that the sign bit can be tested, FOO has mode MODE, C is
5836: GET_MODE_BITSIZE (MODE) - 1, and FOO has only the low-order bit
5837: significant. */
5838: if (code == LSHIFT
5839: && XEXP (varop, 1) == const0_rtx
5840: && GET_MODE (XEXP (varop, 0)) == result_mode
5841: && count == GET_MODE_BITSIZE (result_mode) - 1
5842: && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_INT
5843: && ((STORE_FLAG_VALUE
5844: & (1 << (GET_MODE_BITSIZE (result_mode) - 1))))
5845: && significant_bits (XEXP (varop, 0), result_mode) == 1
5846: && merge_outer_ops (&outer_op, &outer_const, XOR, 1,
5847: result_mode, &complement_p))
5848: {
5849: varop = XEXP (varop, 0);
5850: count = 0;
5851: continue;
5852: }
5853: break;
5854:
5855: case NEG:
5856: /* If we are doing an arithmetic right shift of something known
5857: to be -1 or 0, we don't need the shift. */
5858: if (code == ASHIFTRT
5859: && significant_bits (XEXP (varop, 0), result_mode) == 1)
5860: {
5861: count = 0;
5862: continue;
5863: }
5864:
5865: /* NEG commutes with ASHIFT since it is multiplication. Move the
5866: NEG outside to allow shifts to combine. */
5867: if (code == ASHIFT
5868: && merge_outer_ops (&outer_op, &outer_const, NEG, 0,
5869: result_mode, &complement_p))
5870: {
5871: varop = XEXP (varop, 0);
5872: continue;
5873: }
5874: break;
5875:
5876: case PLUS:
5877: /* Similar to case above. If X is 0 or 1 then X - 1 is -1 or 0. */
5878: if (XEXP (varop, 1) == constm1_rtx && code == ASHIFTRT
5879: && significant_bits (XEXP (varop, 0), result_mode) == 1)
5880: {
5881: count = 0;
5882: continue;
5883: }
5884:
5885: /* If we have the same operands as above but we are shifting the
5886: sign bit into the low-order bit, we are exclusive-or'ing
5887: the operand of the PLUS with a one. */
5888: if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
5889: && XEXP (varop, 1) == constm1_rtx
5890: && significant_bits (XEXP (varop, 0), result_mode) == 1
5891: && merge_outer_ops (&outer_op, &outer_const, XOR, 1,
5892: result_mode, &complement_p))
5893: {
5894: count = 0;
5895: varop = XEXP (varop, 0);
5896: continue;
5897: }
5898:
5899: /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
5900: if (code == ASHIFT
5901: && GET_CODE (XEXP (varop, 1)) == CONST_INT
5902: && (new = simplify_binary_operation (ASHIFT, result_mode,
5903: XEXP (varop, 1),
5904: gen_rtx (CONST_INT,
5905: VOIDmode,
5906: count))) != 0
5907: && merge_outer_ops (&outer_op, &outer_const, PLUS,
5908: INTVAL (new), result_mode, &complement_p))
5909: {
5910: varop = XEXP (varop, 0);
5911: continue;
5912: }
5913: break;
5914:
5915: case MINUS:
5916: /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
5917: with C the size of VAROP - 1 and the shift is logical if
5918: STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
5919: we have a (gt X 0) operation. If the shift is arithmetic with
5920: STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
5921: we have a (neg (gt X 0)) operation. */
5922:
5923: if (GET_CODE (XEXP (varop, 0)) == ASHIFTRT
5924: && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
5925: && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5926: && (code == LSHIFTRT || code == ASHIFTRT)
5927: && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
5928: && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
5929: && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
5930: {
5931: count = 0;
5932: varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
5933: const0_rtx);
5934:
5935: if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
5936: varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
5937:
5938: continue;
5939: }
5940: break;
5941: }
5942:
5943: break;
5944: }
5945:
5946: /* We need to determine what mode to do the shift in. If the shift is
5947: a ASHIFTRT or ROTATE, we must always do it in the mode it was originally
5948: done in. Otherwise, we can do it in MODE, the widest mode encountered.
5949: The code we care about is that of the shift that will actually be done,
5950: not the shift that was originally requested. */
5951: shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
5952:
5953: /* We have now finished analyzing the shift. The result should be
5954: a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
5955: OUTER_OP is non-NIL, it is an operation that needs to be applied
5956: to the result of the shift. OUTER_CONST is the relevant constant,
5957: but we must turn off all bits turned off in the shift.
5958:
5959: If we were passed a value for X, see if we can use any pieces of
5960: it. If not, make new rtx. */
5961:
5962: if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
5963: && GET_CODE (XEXP (x, 1)) == CONST_INT
5964: && INTVAL (XEXP (x, 1)) == count)
5965: const_rtx = XEXP (x, 1);
5966: else
5967: const_rtx = gen_rtx (CONST_INT, VOIDmode, count);
5968:
5969: if (x && GET_CODE (XEXP (x, 0)) == SUBREG
5970: && GET_MODE (XEXP (x, 0)) == shift_mode
5971: && SUBREG_REG (XEXP (x, 0)) == varop)
5972: varop = XEXP (x, 0);
5973: else if (GET_MODE (varop) != shift_mode)
5974: varop = gen_lowpart_for_combine (shift_mode, varop);
5975:
5976: /* If we can't make the SUBREG, try to return what we were given. */
5977: if (GET_CODE (varop) == CLOBBER)
5978: return x ? x : varop;
5979:
5980: new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
5981: if (new != 0)
5982: x = new;
5983: else
5984: {
5985: if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
5986: x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
5987:
5988: SUBST (XEXP (x, 0), varop);
5989: SUBST (XEXP (x, 1), const_rtx);
5990: }
5991:
5992: /* If we were doing a LSHIFTRT in a wider mode than it was originally,
5993: turn off all the bits that the shift would have turned off. */
5994: if (orig_code == LSHIFTRT && result_mode != shift_mode)
5995: x = simplify_and_const_int (0, shift_mode, x,
5996: GET_MODE_MASK (result_mode) >> orig_count);
5997:
5998: /* Do the remainder of the processing in RESULT_MODE. */
5999: x = gen_lowpart_for_combine (result_mode, x);
6000:
6001: /* If COMPLEMENT_P is set, we have to complement X before doing the outer
6002: operation. */
6003: if (complement_p)
6004: x = gen_unary (NOT, result_mode, x);
6005:
6006: if (outer_op != NIL)
6007: {
6008: if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_INT)
6009: outer_const &= GET_MODE_MASK (result_mode);
6010:
6011: if (outer_op == AND)
6012: x = simplify_and_const_int (0, result_mode, x, outer_const);
6013: else if (outer_op == SET)
6014: /* This means that we have determined that the result is
6015: equivalent to a constant. This should be rare. */
6016: x = gen_rtx (CONST_INT, VOIDmode, outer_const);
6017: else if (GET_RTX_CLASS (outer_op) == '1')
6018: x = gen_unary (outer_op, result_mode, x);
6019: else
6020: x = gen_binary (outer_op, result_mode, x,
6021: gen_rtx (CONST_INT, VOIDmode, outer_const));
6022: }
6023:
6024: return x;
6025: }
6026:
6027: /* Like recog, but we receive the address of a pointer to a new pattern.
6028: We try to match the rtx that the pointer points to.
6029: If that fails, we may try to modify or replace the pattern,
6030: storing the replacement into the same pointer object.
6031:
6032: Modifications include deletion or addition of CLOBBERs.
6033:
6034: PNOTES is a pointer to a location where any REG_UNUSED notes added for
6035: the CLOBBERs are placed.
6036:
6037: The value is the final insn code from the pattern ultimately matched,
6038: or -1. */
6039:
6040: static int
6041: recog_for_combine (pnewpat, insn, pnotes)
6042: rtx *pnewpat;
6043: rtx insn;
6044: rtx *pnotes;
6045: {
6046: register rtx pat = *pnewpat;
6047: int insn_code_number;
6048: int num_clobbers_to_add = 0;
6049: int i;
6050: rtx notes = 0;
6051:
6052: /* Is the result of combination a valid instruction? */
6053: insn_code_number = recog (pat, insn, &num_clobbers_to_add);
6054:
6055: /* If it isn't, there is the possibility that we previously had an insn
6056: that clobbered some register as a side effect, but the combined
6057: insn doesn't need to do that. So try once more without the clobbers
6058: unless this represents an ASM insn. */
6059:
6060: if (insn_code_number < 0 && ! check_asm_operands (pat)
6061: && GET_CODE (pat) == PARALLEL)
6062: {
6063: int pos;
6064:
6065: for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
6066: if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
6067: {
6068: if (i != pos)
6069: SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
6070: pos++;
6071: }
6072:
6073: SUBST_INT (XVECLEN (pat, 0), pos);
6074:
6075: if (pos == 1)
6076: pat = XVECEXP (pat, 0, 0);
6077:
6078: insn_code_number = recog (pat, insn, &num_clobbers_to_add);
6079: }
6080:
6081: /* If we had any clobbers to add, make a new pattern than contains
6082: them. Then check to make sure that all of them are dead. */
6083: if (num_clobbers_to_add)
6084: {
6085: rtx newpat = gen_rtx (PARALLEL, VOIDmode,
6086: gen_rtvec (GET_CODE (pat) == PARALLEL
6087: ? XVECLEN (pat, 0) + num_clobbers_to_add
6088: : num_clobbers_to_add + 1));
6089:
6090: if (GET_CODE (pat) == PARALLEL)
6091: for (i = 0; i < XVECLEN (pat, 0); i++)
6092: XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
6093: else
6094: XVECEXP (newpat, 0, 0) = pat;
6095:
6096: add_clobbers (newpat, insn_code_number);
6097:
6098: for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
6099: i < XVECLEN (newpat, 0); i++)
6100: {
6101: if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
6102: && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
6103: return -1;
6104: notes = gen_rtx (EXPR_LIST, REG_UNUSED,
6105: XEXP (XVECEXP (newpat, 0, i), 0), notes);
6106: }
6107: pat = newpat;
6108: }
6109:
6110: *pnewpat = pat;
6111: *pnotes = notes;
6112:
6113: return insn_code_number;
6114: }
6115:
6116: /* Like gen_lowpart but for use by combine. In combine it is not possible
6117: to create any new pseudoregs. However, it is safe to create
6118: invalid memory addresses, because combine will try to recognize
6119: them and all they will do is make the combine attempt fail.
6120:
6121: If for some reason this cannot do its job, an rtx
6122: (clobber (const_int 0)) is returned.
6123: An insn containing that will not be recognized. */
6124:
6125: #undef gen_lowpart
6126:
6127: static rtx
6128: gen_lowpart_for_combine (mode, x)
6129: enum machine_mode mode;
6130: register rtx x;
6131: {
6132: rtx result;
6133:
6134: if (GET_MODE (x) == mode)
6135: return x;
6136:
6137: if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
6138: return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
6139:
6140: /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
6141: won't know what to do. So we will strip off the SUBREG here and
6142: process normally. */
6143: if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
6144: {
6145: x = SUBREG_REG (x);
6146: if (GET_MODE (x) == mode)
6147: return x;
6148: }
6149:
6150: result = gen_lowpart_common (mode, x);
6151: if (result)
6152: return result;
6153:
6154: if (GET_CODE (x) == MEM)
6155: {
6156: register int offset = 0;
6157: rtx new;
6158:
6159: /* Refuse to work on a volatile memory ref or one with a mode-dependent
6160: address. */
6161: if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
6162: return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
6163:
6164: /* If we want to refer to something bigger than the original memref,
6165: generate a perverse subreg instead. That will force a reload
6166: of the original memref X. */
6167: if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
6168: return gen_rtx (SUBREG, mode, x, 0);
6169:
6170: #if WORDS_BIG_ENDIAN
6171: offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
6172: - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
6173: #endif
6174: #if BYTES_BIG_ENDIAN
6175: /* Adjust the address so that the address-after-the-data
6176: is unchanged. */
6177: offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
6178: - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
6179: #endif
6180: new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
6181: RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
6182: MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
6183: MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
6184: return new;
6185: }
6186:
6187: /* If X is a comparison operator, rewrite it in a new mode. This
6188: probably won't match, but may allow further simplifications. */
6189: else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
6190: return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
6191:
6192: /* If we couldn't simplify X any other way, just enclose it in a
6193: SUBREG. Normally, this SUBREG won't match, but some patterns may
6194: include and explicit SUBREG or we may simplify it further in combine. */
6195: else
1.1.1.2 ! root 6196: {
! 6197: int word = 0;
! 6198:
! 6199: if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
! 6200: word = ((GET_MODE_SIZE (GET_MODE (x))
! 6201: - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
! 6202: / UNITS_PER_WORD);
! 6203: return gen_rtx (SUBREG, mode, x, word);
! 6204: }
1.1 root 6205: }
6206:
6207: /* Make an rtx expression. This is a subset of gen_rtx and only supports
6208: expressions of 1, 2, or 3 operands, each of which are rtx expressions.
6209:
6210: If the identical expression was previously in the insn (in the undobuf),
6211: it will be returned. Only if it is not found will a new expression
6212: be made. */
6213:
6214: /*VARARGS2*/
6215: static rtx
6216: gen_rtx_combine (va_alist)
6217: va_dcl
6218: {
6219: va_list p;
6220: enum rtx_code code;
6221: enum machine_mode mode;
6222: int n_args;
6223: rtx args[3];
6224: int i, j;
6225: char *fmt;
6226: rtx rt;
6227:
6228: va_start (p);
6229: code = va_arg (p, enum rtx_code);
6230: mode = va_arg (p, enum machine_mode);
6231: n_args = GET_RTX_LENGTH (code);
6232: fmt = GET_RTX_FORMAT (code);
6233:
6234: if (n_args == 0 || n_args > 3)
6235: abort ();
6236:
6237: /* Get each arg and verify that it is supposed to be an expression. */
6238: for (j = 0; j < n_args; j++)
6239: {
6240: if (*fmt++ != 'e')
6241: abort ();
6242:
6243: args[j] = va_arg (p, rtx);
6244: }
6245:
6246: /* See if this is in undobuf. Be sure we don't use objects that came
6247: from another insn; this could produce circular rtl structures. */
6248:
6249: for (i = previous_num_undos; i < undobuf.num_undo; i++)
6250: if (!undobuf.undo[i].is_int
6251: && GET_CODE (undobuf.undo[i].old_contents) == code
6252: && GET_MODE (undobuf.undo[i].old_contents) == mode)
6253: {
6254: for (j = 0; j < n_args; j++)
6255: if (XEXP (undobuf.undo[i].old_contents, j) != args[j])
6256: break;
6257:
6258: if (j == n_args)
6259: return undobuf.undo[i].old_contents;
6260: }
6261:
6262: /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
6263: Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
6264: rt = rtx_alloc (code);
6265: PUT_MODE (rt, mode);
6266: XEXP (rt, 0) = args[0];
6267: if (n_args > 1)
6268: {
6269: XEXP (rt, 1) = args[1];
6270: if (n_args > 2)
6271: XEXP (rt, 2) = args[2];
6272: }
6273: return rt;
6274: }
6275:
6276: /* These routines make binary and unary operations by first seeing if they
6277: fold; if not, a new expression is allocated. */
6278:
6279: static rtx
6280: gen_binary (code, mode, op0, op1)
6281: enum rtx_code code;
6282: enum machine_mode mode;
6283: rtx op0, op1;
6284: {
6285: rtx result;
6286:
6287: if (GET_RTX_CLASS (code) == '<')
6288: {
6289: enum machine_mode op_mode = GET_MODE (op0);
6290: if (op_mode == VOIDmode)
6291: op_mode = GET_MODE (op1);
6292: result = simplify_relational_operation (code, op_mode, op0, op1);
6293: }
6294: else
6295: result = simplify_binary_operation (code, mode, op0, op1);
6296:
6297: if (result)
6298: return result;
6299:
6300: /* Put complex operands first and constants second. */
6301: if (GET_RTX_CLASS (code) == 'c'
6302: && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
6303: || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
6304: && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
6305: || (GET_CODE (op0) == SUBREG
6306: && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
6307: && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
6308: return gen_rtx_combine (code, mode, op1, op0);
6309:
6310: return gen_rtx_combine (code, mode, op0, op1);
6311: }
6312:
6313: static rtx
6314: gen_unary (code, mode, op0)
6315: enum rtx_code code;
6316: enum machine_mode mode;
6317: rtx op0;
6318: {
6319: rtx result = simplify_unary_operation (code, mode, op0, mode);
6320:
6321: if (result)
6322: return result;
6323:
6324: return gen_rtx_combine (code, mode, op0);
6325: }
6326:
6327: /* Simplify a comparison between *POP0 and *POP1 where CODE is the
6328: comparison code that will be tested.
6329:
6330: The result is a possibly different comparison code to use. *POP0 and
6331: *POP1 may be updated.
6332:
6333: It is possible that we might detect that a comparison is either always
6334: true or always false. However, we do not perform general constant
1.1.1.2 ! root 6335: folding in combine, so this knowledge isn't useful. Such tautologies
1.1 root 6336: should have been detected earlier. Hence we ignore all such cases. */
6337:
6338: static enum rtx_code
6339: simplify_comparison (code, pop0, pop1)
6340: enum rtx_code code;
6341: rtx *pop0;
6342: rtx *pop1;
6343: {
6344: rtx op0 = *pop0;
6345: rtx op1 = *pop1;
6346: rtx tem, tem1;
6347: int i;
6348: enum machine_mode mode, tmode;
6349:
6350: /* Try a few ways of applying the same transformation to both operands. */
6351: while (1)
6352: {
6353: /* If both operands are the same constant shift, see if we can ignore the
6354: shift. We can if the shift is a rotate or if the bits shifted out of
6355: this shift are not significant for either input and if the type of
6356: comparison is compatible with the shift. */
6357: if (GET_CODE (op0) == GET_CODE (op1)
6358: && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_INT
6359: && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
6360: || ((GET_CODE (op0) == LSHIFTRT
6361: || GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
6362: && (code != GT && code != LT && code != GE && code != LE))
6363: || (GET_CODE (op0) == ASHIFTRT
6364: && (code != GTU && code != LTU
6365: && code != GEU && code != GEU)))
6366: && GET_CODE (XEXP (op0, 1)) == CONST_INT
6367: && INTVAL (XEXP (op0, 1)) >= 0
6368: && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_INT
6369: && XEXP (op0, 1) == XEXP (op1, 1))
6370: {
6371: enum machine_mode mode = GET_MODE (op0);
6372: unsigned mask = GET_MODE_MASK (mode);
6373: int shift_count = INTVAL (XEXP (op0, 1));
6374:
6375: if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
6376: mask &= (mask >> shift_count) << shift_count;
6377: else if (GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
6378: mask = (mask & (mask << shift_count)) >> shift_count;
6379:
6380: if ((significant_bits (XEXP (op0, 0), mode) & ~ mask) == 0
6381: && (significant_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
6382: op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
6383: else
6384: break;
6385: }
6386:
6387: /* If both operands are AND's of a paradoxical SUBREG by constant, the
6388: SUBREGs are of the same mode, and, in both cases, the AND would
6389: be redundant if the comparison was done in the narrower mode,
6390: do the comparison in the narrower mode (e.g., we are AND'ing with 1
6391: and the operand's significant bits are 0xffffff01; in that case if
6392: we only care about QImode, we don't need the AND). This case occurs
6393: if the output mode of an scc insn is not SImode and
6394: STORE_FLAG_VALUE == 1 (e.g., the 386). */
6395:
6396: else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
6397: && GET_CODE (XEXP (op0, 1)) == CONST_INT
6398: && GET_CODE (XEXP (op1, 1)) == CONST_INT
6399: && GET_CODE (XEXP (op0, 0)) == SUBREG
6400: && GET_CODE (XEXP (op1, 0)) == SUBREG
6401: && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
6402: > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
6403: && (GET_MODE (SUBREG_REG (XEXP (op0, 0)))
6404: == GET_MODE (SUBREG_REG (XEXP (op1, 0))))
6405: && (significant_bits (SUBREG_REG (XEXP (op0, 0)),
6406: GET_MODE (SUBREG_REG (XEXP (op0, 0))))
6407: & ~ INTVAL (XEXP (op0, 1))) == 0
6408: && (significant_bits (SUBREG_REG (XEXP (op1, 0)),
6409: GET_MODE (SUBREG_REG (XEXP (op1, 0))))
6410: & ~ INTVAL (XEXP (op1, 1))) == 0)
6411: {
6412: op0 = SUBREG_REG (XEXP (op0, 0));
6413: op1 = SUBREG_REG (XEXP (op1, 0));
6414:
6415: /* the resulting comparison is always unsigned since we masked off
6416: the original sign bit. */
6417: code = unsigned_condition (code);
6418: }
6419: else
6420: break;
6421: }
6422:
6423: /* If the first operand is a constant, swap the operands and adjust the
6424: comparison code appropriately. */
6425: if (CONSTANT_P (op0))
6426: {
6427: tem = op0, op0 = op1, op1 = tem;
6428: code = swap_condition (code);
6429: }
6430:
6431: /* We now enter a loop during which we will try to simplify the comparison.
6432: For the most part, we only are concerned with comparisons with zero,
6433: but some things may really be comparisons with zero but not start
6434: out looking that way. */
6435:
6436: while (GET_CODE (op1) == CONST_INT)
6437: {
6438: enum machine_mode mode = GET_MODE (op0);
6439: int mode_width = GET_MODE_BITSIZE (mode);
6440: unsigned mask = GET_MODE_MASK (mode);
6441: int equality_comparison_p;
6442: int sign_bit_comparison_p;
6443: int unsigned_comparison_p;
6444: int const_op;
6445:
6446: /* We only want to handle integral modes. This catches VOIDmode,
6447: CCmode, and the floating-point modes. An exception is that we
6448: can handle VOIDmode if OP0 is a COMPARE or a comparison
6449: operation. */
6450:
6451: if (GET_MODE_CLASS (mode) != MODE_INT
6452: && ! (mode == VOIDmode
6453: && (GET_CODE (op0) == COMPARE
6454: || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
6455: break;
6456:
6457: /* Get the constant we are comparing against and turn off all bits
6458: not on in our mode. */
6459: const_op = INTVAL (op1);
6460: if (mode_width <= HOST_BITS_PER_INT)
6461: const_op &= GET_MODE_MASK (mode);
6462:
6463: /* If we are comparing against a constant power of two and the value
6464: being compared has only that single significant bit (e.g., it was
6465: `and'ed with that bit), we can replace this with a comparison
6466: with zero. */
6467: if (const_op
6468: && (code == EQ || code == NE || code == GE || code == GEU
6469: || code == LT || code == LTU)
6470: && mode_width <= HOST_BITS_PER_INT
6471: && exact_log2 (const_op) >= 0
6472: && significant_bits (op0, mode) == const_op)
6473: {
6474: code = (code == EQ || code == GE || code == GEU ? NE : EQ);
6475: op1 = const0_rtx, const_op = 0;
6476: }
6477:
6478: /* Do some canonicalizations based on the comparison code. We prefer
6479: comparisons against zero and then prefer equality comparisons. */
6480:
6481: switch (code)
6482: {
6483: case LT:
6484: /* < 1 is equivalent to <= 0 */
6485: if (const_op == 1)
6486: {
6487: op1 = const0_rtx;
6488: const_op = 0;
6489: code = LE;
6490: /* ... fall through to LE case below. */
6491: }
6492: else
6493: break;
6494:
6495: case LE:
6496: /* <= -1 is equivalent to < 0 */
6497: if (op1 == constm1_rtx)
6498: op1 = const0_rtx, const_op = 0, code = LT;
6499:
6500: /* If we are doing a <= 0 comparison on a value known to have
6501: a zero sign bit, we can replace this with == 0. */
6502: else if (const_op == 0
6503: && mode_width <= HOST_BITS_PER_INT
6504: && (significant_bits (op0, mode)
6505: & (1 << (mode_width - 1))) == 0)
6506: code = EQ;
6507: break;
6508:
6509: case GE:
6510: /* >= 1 is equivalent to > 0. */
6511: if (const_op == 1)
6512: {
6513: op1 = const0_rtx;
6514: const_op = 0;
6515: code = GT;
6516: /* ... fall through to GT below. */
6517: }
6518: else
6519: break;
6520:
6521: case GT:
6522: /* > -1 is equivalent to >= 0. */
6523: if (op1 == constm1_rtx)
6524: op1 = const0_rtx, const_op = 0, code = GE;
6525:
6526: /* If we are doing a > 0 comparison on a value known to have
6527: a zero sign bit, we can replace this with != 0. */
6528: else if (const_op == 0
6529: && mode_width <= HOST_BITS_PER_INT
6530: && (significant_bits (op0, mode)
6531: & (1 << (mode_width - 1))) == 0)
6532: code = NE;
6533: break;
6534:
6535: case GEU:
6536: /* unsigned >= 1 is equivalent to != 0 */
6537: if (const_op == 1)
6538: op1 = const0_rtx, const_op = 0, code = NE;
6539: break;
6540:
6541: case LTU:
6542: /* unsigned < 1 is equivalent to == 0 */
6543: if (const_op == 1)
6544: op1 = const0_rtx, const_op = 0, code = EQ;
6545: break;
6546:
6547: case LEU:
6548: /* unsigned <= 0 is equivalent to == 0 */
6549: if (const_op == 0)
6550: code = EQ;
6551: break;
6552:
6553: case GTU:
6554: /* unsigned > 0 is equivalent to != 0 */
6555: if (const_op == 0)
6556: code = NE;
6557: break;
6558: }
6559:
6560: /* Compute some predicates to simplify code below. */
6561:
6562: equality_comparison_p = (code == EQ || code == NE);
6563: sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
6564: unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
6565: || code == LEU);
6566:
6567: /* Now try cases based on the opcode of OP0. If none of the cases
6568: does a "continue", we exit this loop immediately after the
6569: switch. */
6570:
6571: switch (GET_CODE (op0))
6572: {
6573: case ZERO_EXTRACT:
6574: /* If we are extracting a single bit from a variable position in
6575: a constant that has only a single bit set and are comparing it
6576: with zero, we can convert this into an equality comparison
6577: between the position and the location of the single bit. We can't
6578: do this if bit endian and we don't have an extzv since we then
6579: can't know what mode to use for the endianness adjustment. */
6580:
6581: #if ! BITS_BIG_ENDIAN || defined (HAVE_extzv)
6582: if (GET_CODE (XEXP (op0, 0)) == CONST_INT
6583: && XEXP (op0, 1) == const1_rtx
6584: && equality_comparison_p && const_op == 0
6585: && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
6586: {
6587: #if BITS_BIG_ENDIAN
6588: i = (GET_MODE_BITSIZE
6589: (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
6590: #endif
6591:
6592: op0 = XEXP (op0, 2);
6593: op1 = gen_rtx (CONST_INT, VOIDmode, i);
6594: const_op = i;
6595:
6596: /* Result is nonzero iff shift count is equal to I. */
6597: code = reverse_condition (code);
6598: continue;
6599: }
6600: #endif
6601:
6602: /* ... fall through ... */
6603:
6604: case SIGN_EXTRACT:
6605: tem = expand_compound_operation (op0);
6606: if (tem != op0)
6607: {
6608: op0 = tem;
6609: continue;
6610: }
6611: break;
6612:
6613: case NOT:
6614: /* If testing for equality, we can take the NOT of the constant. */
6615: if (equality_comparison_p
6616: && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
6617: {
6618: op0 = XEXP (op0, 0);
6619: op1 = tem;
6620: continue;
6621: }
6622:
6623: /* If just looking at the sign bit, reverse the sense of the
6624: comparison. */
6625: if (sign_bit_comparison_p)
6626: {
6627: op0 = XEXP (op0, 0);
6628: code = (code == GE ? LT : GE);
6629: continue;
6630: }
6631: break;
6632:
6633: case NEG:
6634: /* If testing for equality, we can take the NEG of the constant. */
6635: if (equality_comparison_p
6636: && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
6637: {
6638: op0 = XEXP (op0, 0);
6639: op1 = tem;
6640: continue;
6641: }
6642:
6643: /* The remaining cases only apply to comparisons with zero. */
6644: if (const_op != 0)
6645: break;
6646:
6647: /* When X is ABS or is known positive,
6648: (neg X) is < 0 if and only if X != 0. */
6649:
6650: if (sign_bit_comparison_p
6651: && (GET_CODE (XEXP (op0, 0)) == ABS
6652: || (mode_width <= HOST_BITS_PER_INT
6653: && (significant_bits (XEXP (op0, 0), mode)
6654: & (1 << (mode_width - 1))) == 0)))
6655: {
6656: op0 = XEXP (op0, 0);
6657: code = (code == LT ? NE : EQ);
6658: continue;
6659: }
6660:
6661: /* If we have NEG of something that is the result of a
6662: SIGN_EXTEND, SIGN_EXTRACT, or ASHIFTRT, we know that the
6663: two high-order bits must be the same and hence that
6664: "(-a) < 0" is equivalent to "a > 0". Otherwise, we can't
6665: do this. */
6666: if (GET_CODE (XEXP (op0, 0)) == SIGN_EXTEND
6667: || (GET_CODE (XEXP (op0, 0)) == SIGN_EXTRACT
6668: && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
6669: && (INTVAL (XEXP (XEXP (op0, 0), 1))
6670: < GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (op0, 0), 0)))))
6671: || (GET_CODE (XEXP (op0, 0)) == ASHIFTRT
6672: && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
6673: && XEXP (XEXP (op0, 0), 1) != const0_rtx)
6674: || ((tem = get_last_value (XEXP (op0, 0))) != 0
6675: && (GET_CODE (tem) == SIGN_EXTEND
6676: || (GET_CODE (tem) == SIGN_EXTRACT
6677: && GET_CODE (XEXP (tem, 1)) == CONST_INT
6678: && (INTVAL (XEXP (tem, 1))
6679: < GET_MODE_BITSIZE (GET_MODE (XEXP (tem, 0)))))
6680: || (GET_CODE (tem) == ASHIFTRT
6681: && GET_CODE (XEXP (tem, 1)) == CONST_INT
6682: && XEXP (tem, 1) != const0_rtx))))
6683: {
6684: op0 = XEXP (op0, 0);
6685: code = swap_condition (code);
6686: continue;
6687: }
6688: break;
6689:
6690: case ROTATE:
6691: /* If we are testing equality and our count is a constant, we
6692: can perform the inverse operation on our RHS. */
6693: if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
6694: && (tem = simplify_binary_operation (ROTATERT, mode,
6695: op1, XEXP (op0, 1))) != 0)
6696: {
6697: op0 = XEXP (op0, 0);
6698: op1 = tem;
6699: continue;
6700: }
6701:
6702: /* If we are doing a < 0 or >= 0 comparison, it means we are testing
6703: a particular bit. Convert it to an AND of a constant of that
6704: bit. This will be converted into a ZERO_EXTRACT. */
6705: if (const_op == 0 && sign_bit_comparison_p
6706: && GET_CODE (XEXP (op0, 1)) == CONST_INT
6707: && mode_width <= HOST_BITS_PER_INT)
6708: {
6709: op0 = simplify_and_const_int (0, mode, XEXP (op0, 0),
6710: 1 << (mode_width - 1
6711: - INTVAL (XEXP (op0, 1))));
6712: code = (code == LT ? NE : EQ);
6713: continue;
6714: }
6715:
6716: /* ... fall through ... */
6717:
6718: case ABS:
6719: /* ABS is ignorable inside an equality comparison with zero. */
6720: if (const_op == 0 && equality_comparison_p)
6721: {
6722: op0 = XEXP (op0, 0);
6723: continue;
6724: }
6725: break;
6726:
6727:
6728: case SIGN_EXTEND:
6729: /* Can simplify (compare (zero/sign_extend FOO) CONST)
6730: to (compare FOO CONST) if CONST fits in FOO's mode and we
6731: are either testing inequality or have an unsigned comparison
6732: with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
6733: if (! unsigned_comparison_p
6734: && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
6735: <= HOST_BITS_PER_INT)
6736: && ((unsigned) const_op
6737: < (1 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1))))
6738: {
6739: op0 = XEXP (op0, 0);
6740: continue;
6741: }
6742: break;
6743:
6744: case SUBREG:
6745: /* If the inner mode is smaller and we are extracting the low
6746: part, we can treat the SUBREG as if it were a ZERO_EXTEND. */
6747: if (! subreg_lowpart_p (op0)
6748: || GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) >= mode_width)
6749: break;
6750:
6751: /* ... fall through ... */
6752:
6753: case ZERO_EXTEND:
6754: if ((unsigned_comparison_p || equality_comparison_p)
6755: && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
6756: <= HOST_BITS_PER_INT)
6757: && ((unsigned) const_op
6758: < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
6759: {
6760: op0 = XEXP (op0, 0);
6761: continue;
6762: }
6763: break;
6764:
6765: case PLUS:
6766: /* (eq (plus X C1) C2) -> (eq X (minus C2 C1)). We can only do
1.1.1.2 ! root 6767: this for equality comparisons due to pathological cases involving
1.1 root 6768: overflows. */
6769: if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
6770: && (tem = simplify_binary_operation (MINUS, mode, op1,
6771: XEXP (op0, 1))) != 0)
6772: {
6773: op0 = XEXP (op0, 0);
6774: op1 = tem;
6775: continue;
6776: }
6777:
6778: /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
6779: if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
6780: && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
6781: {
6782: op0 = XEXP (XEXP (op0, 0), 0);
6783: code = (code == LT ? EQ : NE);
6784: continue;
6785: }
6786: break;
6787:
6788: case MINUS:
6789: /* The sign bit of (minus (ashiftrt X C) X), where C is the number
6790: of bits in X minus 1, is one iff X > 0. */
6791: if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
6792: && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
6793: && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
6794: && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
6795: {
6796: op0 = XEXP (op0, 1);
6797: code = (code == GE ? LE : GT);
6798: continue;
6799: }
6800: break;
6801:
6802: case XOR:
6803: /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
6804: if C is zero or B is a constant. */
6805: if (equality_comparison_p
6806: && 0 != (tem = simplify_binary_operation (XOR, mode,
6807: XEXP (op0, 1), op1)))
6808: {
6809: op0 = XEXP (op0, 0);
6810: op1 = tem;
6811: continue;
6812: }
6813: break;
6814:
6815: case EQ: case NE:
6816: case LT: case LTU: case LE: case LEU:
6817: case GT: case GTU: case GE: case GEU:
6818: /* We can't do anything if OP0 is a condition code value, rather
6819: than an actual data value. */
6820: if (const_op != 0
6821: #ifdef HAVE_cc0
6822: || XEXP (op0, 0) == cc0_rtx
6823: #endif
6824: || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
6825: break;
6826:
6827: /* Get the two operands being compared. */
6828: if (GET_CODE (XEXP (op0, 0)) == COMPARE)
6829: tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
6830: else
6831: tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
6832:
6833: /* Check for the cases where we simply want the result of the
6834: earlier test or the opposite of that result. */
6835: if (code == NE
6836: || (code == EQ && reversible_comparison_p (op0))
6837: || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_INT
6838: && (STORE_FLAG_VALUE
6839: & (1 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1)))
6840: && (code == LT
6841: || (code == GE && reversible_comparison_p (op0)))))
6842: {
6843: code = (code == LT || code == NE
6844: ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
6845: op0 = tem, op1 = tem1;
6846: continue;
6847: }
6848: break;
6849:
6850: case IOR:
6851: /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
6852: iff X <= 0. */
6853: if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
6854: && XEXP (XEXP (op0, 0), 1) == constm1_rtx
6855: && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
6856: {
6857: op0 = XEXP (op0, 1);
6858: code = (code == GE ? GT : LE);
6859: continue;
6860: }
6861: break;
6862:
6863: case AND:
6864: /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
6865: will be converted to a ZERO_EXTRACT later. */
6866: if (const_op == 0 && equality_comparison_p
6867: && (GET_CODE (XEXP (op0, 0)) == ASHIFT
6868: || GET_CODE (XEXP (op0, 0)) == LSHIFT)
6869: && XEXP (XEXP (op0, 0), 0) == const1_rtx)
6870: {
6871: op0 = simplify_and_const_int
6872: (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
6873: XEXP (op0, 1),
6874: XEXP (XEXP (op0, 0), 1)),
6875: 1);
6876: continue;
6877: }
6878:
6879: /* If we are comparing (and (lshiftrt X C1) C2) for equality with
6880: zero and X is a comparison and C1 and C2 describe only bits set
6881: in STORE_FLAG_VALUE, we can compare with X. */
6882: if (const_op == 0 && equality_comparison_p
6883: && mode_width <= HOST_BITS_PER_INT
6884: && GET_CODE (XEXP (op0, 1)) == CONST_INT
6885: && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
6886: && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
6887: && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
6888: && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_INT)
6889: {
6890: mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
6891: << INTVAL (XEXP (XEXP (op0, 0), 1)));
6892: if ((~ STORE_FLAG_VALUE & mask) == 0
6893: && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
6894: || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
6895: && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
6896: {
6897: op0 = XEXP (XEXP (op0, 0), 0);
6898: continue;
6899: }
6900: }
6901:
6902: /* If we are doing an equality comparison of an AND of a bit equal
6903: to the sign bit, replace this with a LT or GE comparison of
6904: the underlying value. */
6905: if (equality_comparison_p
6906: && const_op == 0
6907: && GET_CODE (XEXP (op0, 1)) == CONST_INT
6908: && mode_width <= HOST_BITS_PER_INT
6909: && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
6910: == 1 << (mode_width - 1)))
6911: {
6912: op0 = XEXP (op0, 0);
6913: code = (code == EQ ? GE : LT);
6914: continue;
6915: }
6916:
6917: /* If this AND operation is really a ZERO_EXTEND from a narrower
6918: mode, the constant fits within that mode, and this is either an
6919: equality or unsigned comparison, try to do this comparison in
6920: the narrower mode. */
6921: if ((equality_comparison_p || unsigned_comparison_p)
6922: && GET_CODE (XEXP (op0, 1)) == CONST_INT
6923: && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
6924: & GET_MODE_MASK (mode))
6925: + 1)) >= 0
6926: && const_op >> i == 0
6927: && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
6928: {
6929: op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
6930: continue;
6931: }
6932: break;
6933:
6934: case ASHIFT:
6935: case LSHIFT:
6936: /* If we have (compare (xshift FOO N) (const_int C)) and
6937: the high order N bits of FOO (N+1 if an inequality comparison)
6938: are not significant, we can do this by comparing FOO with C
6939: shifted right N bits so long as the low-order N bits of C are
6940: zero. */
6941: if (GET_CODE (XEXP (op0, 1)) == CONST_INT
6942: && INTVAL (XEXP (op0, 1)) >= 0
6943: && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
6944: < HOST_BITS_PER_INT)
6945: && (const_op & ~ ((1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
6946: && mode_width <= HOST_BITS_PER_INT
6947: && (significant_bits (XEXP (op0, 0), mode)
6948: & ~ (mask >> (INTVAL (XEXP (op0, 1))
6949: + ! equality_comparison_p))) == 0)
6950: {
6951: const_op >>= INTVAL (XEXP (op0, 1));
6952: op1 = gen_rtx (CONST_INT, VOIDmode, const_op);
6953: op0 = XEXP (op0, 0);
6954: continue;
6955: }
6956:
1.1.1.2 ! root 6957: /* If we are doing a sign bit comparison, it means we are testing
1.1 root 6958: a particular bit. Convert it to the appropriate AND. */
1.1.1.2 ! root 6959: if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
1.1 root 6960: && mode_width <= HOST_BITS_PER_INT)
6961: {
6962: op0 = simplify_and_const_int (0, mode, XEXP (op0, 0),
6963: 1 << ( mode_width - 1
6964: - INTVAL (XEXP (op0, 1))));
6965: code = (code == LT ? NE : EQ);
6966: continue;
6967: }
1.1.1.2 ! root 6968:
! 6969: /* If this an equality comparison with zero and we are shifting
! 6970: the low bit to the sign bit, we can convert this to an AND of the
! 6971: low-order bit. */
! 6972: if (const_op == 0 && equality_comparison_p
! 6973: && GET_CODE (XEXP (op0, 1)) == CONST_INT
! 6974: && INTVAL (XEXP (op0, 1)) == mode_width - 1)
! 6975: {
! 6976: op0 = simplify_and_const_int (0, mode, XEXP (op0, 0), 1);
! 6977: continue;
! 6978: }
1.1 root 6979: break;
6980:
6981: case ASHIFTRT:
6982: /* If OP0 is a sign extension and CODE is not an unsigned comparison,
6983: do the comparison in a narrower mode. */
6984: if (! unsigned_comparison_p
6985: && GET_CODE (XEXP (op0, 1)) == CONST_INT
6986: && GET_CODE (XEXP (op0, 0)) == ASHIFT
6987: && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
6988: && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
6989: MODE_INT, 1)) != VOIDmode
6990: && ((unsigned) const_op <= GET_MODE_MASK (tmode)
6991: || (unsigned) - const_op <= GET_MODE_MASK (tmode)))
6992: {
6993: op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
6994: continue;
6995: }
6996:
6997: /* ... fall through ... */
6998: case LSHIFTRT:
6999: /* If we have (compare (xshiftrt FOO N) (const_int C)) and
7000: the low order N bits of FOO are not significant, we can do this
7001: by comparing FOO with C shifted left N bits so long as no
7002: overflow occurs. */
7003: if (GET_CODE (XEXP (op0, 1)) == CONST_INT
7004: && INTVAL (XEXP (op0, 1)) >= 0
7005: && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_INT
7006: && mode_width <= HOST_BITS_PER_INT
7007: && (significant_bits (XEXP (op0, 0), mode)
7008: & ((1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
7009: && (const_op == 0
7010: || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
7011: < mode_width)))
7012: {
7013: const_op <<= INTVAL (XEXP (op0, 1));
7014: op1 = gen_rtx (CONST_INT, VOIDmode, const_op);
7015: op0 = XEXP (op0, 0);
7016: continue;
7017: }
7018:
7019: /* If we are using this shift to extract just the sign bit, we
7020: can replace this with an LT or GE comparison. */
7021: if (const_op == 0
7022: && (equality_comparison_p || sign_bit_comparison_p)
7023: && GET_CODE (XEXP (op0, 1)) == CONST_INT
7024: && INTVAL (XEXP (op0, 1)) == mode_width - 1)
7025: {
7026: op0 = XEXP (op0, 0);
7027: code = (code == NE || code == GT ? LT : GE);
7028: continue;
7029: }
7030: break;
7031: }
7032:
7033: break;
7034: }
7035:
7036: /* Now make any compound operations involved in this comparison. Then,
7037: check for an outmost SUBREG on OP0 that isn't doing anything or is
7038: paradoxical. The latter case can only occur when it is known that the
7039: "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
7040: We can never remove a SUBREG for a non-equality comparison because the
7041: sign bit is in a different place in the underlying object. */
7042:
7043: op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
7044: op1 = make_compound_operation (op1, SET);
7045:
7046: if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
7047: && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
7048: && (code == NE || code == EQ)
7049: && ((GET_MODE_SIZE (GET_MODE (op0))
7050: > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
7051: {
7052: op0 = SUBREG_REG (op0);
7053: op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
7054: }
7055:
7056: else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
7057: && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
7058: && (code == NE || code == EQ)
7059: && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_INT
7060: && (significant_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
7061: & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
7062: && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
7063: op1),
7064: (significant_bits (tem, GET_MODE (SUBREG_REG (op0)))
7065: & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
7066: op0 = SUBREG_REG (op0), op1 = tem;
7067:
7068: /* We now do the opposite procedure: Some machines don't have compare
7069: insns in all modes. If OP0's mode is an integer mode smaller than a
7070: word and we can't do a compare in that mode, see if there is a larger
7071: mode for which we can do the compare and where the only significant
7072: bits in OP0 and OP1 are those in the narrower mode. We can do
7073: this if this is an equality comparison, in which case we can
7074: merely widen the operation, or if we are testing the sign bit, in
7075: which case we can explicitly put in the test. */
7076:
7077: mode = GET_MODE (op0);
7078: if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
7079: && GET_MODE_SIZE (mode) < UNITS_PER_WORD
7080: && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
7081: for (tmode = GET_MODE_WIDER_MODE (mode);
7082: tmode != VOIDmode && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_INT;
7083: tmode = GET_MODE_WIDER_MODE (tmode))
7084: if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing
7085: && (significant_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
7086: && (significant_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0
7087: && (code == EQ || code == NE
7088: || (op1 == const0_rtx && (code == LT || code == GE)
7089: && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT)))
7090: {
7091: op0 = gen_lowpart_for_combine (tmode, op0);
7092: op1 = gen_lowpart_for_combine (tmode, op1);
7093:
7094: if (code == LT || code == GE)
7095: {
7096: op0 = gen_binary (AND, tmode, op0,
7097: gen_rtx (CONST_INT, VOIDmode,
7098: 1 << (GET_MODE_BITSIZE (mode) - 1)));
7099: code = (code == LT) ? NE : EQ;
7100: }
7101:
7102: break;
7103: }
7104:
7105: *pop0 = op0;
7106: *pop1 = op1;
7107:
7108: return code;
7109: }
7110:
7111: /* Return 1 if we know that X, a comparison operation, is not operating
7112: on a floating-point value or is EQ or NE, meaning that we can safely
7113: reverse it. */
7114:
7115: static int
7116: reversible_comparison_p (x)
7117: rtx x;
7118: {
7119: if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
7120: || GET_CODE (x) == NE || GET_CODE (x) == EQ)
7121: return 1;
7122:
7123: switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
7124: {
7125: case MODE_INT:
7126: return 1;
7127:
7128: case MODE_CC:
7129: x = get_last_value (XEXP (x, 0));
7130: return (x && GET_CODE (x) == COMPARE
7131: && GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) == MODE_INT);
7132: }
7133:
7134: return 0;
7135: }
7136:
7137: /* Utility function for following routine. Called when X is part of a value
7138: being stored into reg_last_set_value. Sets reg_last_set_table_tick
7139: for each register mentioned. Similar to mention_regs in cse.c */
7140:
7141: static void
7142: update_table_tick (x)
7143: rtx x;
7144: {
7145: register enum rtx_code code = GET_CODE (x);
7146: register char *fmt = GET_RTX_FORMAT (code);
7147: register int i;
7148:
7149: if (code == REG)
7150: {
7151: int regno = REGNO (x);
7152: int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
7153: ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
7154:
7155: for (i = regno; i < endregno; i++)
7156: reg_last_set_table_tick[i] = label_tick;
7157:
7158: return;
7159: }
7160:
7161: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7162: /* Note that we can't have an "E" in values stored; see
7163: get_last_value_validate. */
7164: if (fmt[i] == 'e')
7165: update_table_tick (XEXP (x, i));
7166: }
7167:
7168: /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
7169: are saying that the register is clobbered and we no longer know its
7170: value. If INSN is zero, don't update reg_last_set; this call is normally
7171: done with VALUE also zero to invalidate the register. */
7172:
7173: static void
7174: record_value_for_reg (reg, insn, value)
7175: rtx reg;
7176: rtx insn;
7177: rtx value;
7178: {
7179: int regno = REGNO (reg);
7180: int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
7181: ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
7182: int i;
7183:
7184: /* If VALUE contains REG and we have a previous value for REG, substitute
7185: the previous value. */
7186: if (value && insn && reg_overlap_mentioned_p (reg, value))
7187: {
7188: rtx tem;
7189:
7190: /* Set things up so get_last_value is allowed to see anything set up to
7191: our insn. */
7192: subst_low_cuid = INSN_CUID (insn);
7193: tem = get_last_value (reg);
7194:
7195: if (tem)
7196: value = replace_rtx (copy_rtx (value), reg, tem);
7197: }
7198:
7199: /* For each register modified, show we don't know its value, that
7200: its value has been updated, and that we don't know the location of
7201: the death of the register. */
7202: for (i = regno; i < endregno; i ++)
7203: {
7204: if (insn)
7205: reg_last_set[i] = insn;
7206: reg_last_set_value[i] = 0;
7207: reg_last_death[i] = 0;
7208: }
7209:
7210: /* Mark registers that are being referenced in this value. */
7211: if (value)
7212: update_table_tick (value);
7213:
7214: /* Now update the status of each register being set.
7215: If someone is using this register in this block, set this register
7216: to invalid since we will get confused between the two lives in this
7217: basic block. This makes using this register always invalid. In cse, we
7218: scan the table to invalidate all entries using this register, but this
7219: is too much work for us. */
7220:
7221: for (i = regno; i < endregno; i++)
7222: {
7223: reg_last_set_label[i] = label_tick;
7224: if (value && reg_last_set_table_tick[i] == label_tick)
7225: reg_last_set_invalid[i] = 1;
7226: else
7227: reg_last_set_invalid[i] = 0;
7228: }
7229:
7230: /* The value being assigned might refer to X (like in "x++;"). In that
7231: case, we must replace it with (clobber (const_int 0)) to prevent
7232: infinite loops. */
7233: if (value && ! get_last_value_validate (&value,
7234: reg_last_set_label[regno], 0))
7235: {
7236: value = copy_rtx (value);
7237: if (! get_last_value_validate (&value, reg_last_set_label[regno], 1))
7238: value = 0;
7239: }
7240:
7241: /* For the main register being modified, update the value. */
7242: reg_last_set_value[regno] = value;
7243:
7244: }
7245:
7246: /* Used for communication between the following two routines. */
7247: static rtx record_dead_insn;
7248:
7249: /* Called via note_stores from record_dead_and_set_regs to handle one
7250: SET or CLOBBER in an insn. */
7251:
7252: static void
7253: record_dead_and_set_regs_1 (dest, setter)
7254: rtx dest, setter;
7255: {
7256: if (GET_CODE (dest) == REG)
7257: {
7258: /* If we are setting the whole register, we know its value. Otherwise
7259: show that we don't know the value. We can handle SUBREG in
7260: some cases. */
7261: if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
7262: record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
7263: else if (GET_CODE (setter) == SET
7264: && GET_CODE (SET_DEST (setter)) == SUBREG
7265: && SUBREG_REG (SET_DEST (setter)) == dest
7266: && subreg_lowpart_p (SET_DEST (setter)))
7267: record_value_for_reg
7268: (dest, record_dead_insn,
7269: gen_lowpart_for_combine (GET_MODE (SET_DEST (setter)),
7270: SET_SRC (setter)));
7271: else
7272: record_value_for_reg (dest, record_dead_insn, 0);
7273: }
7274: else if (GET_CODE (dest) == MEM
7275: /* Ignore pushes, they clobber nothing. */
7276: && ! push_operand (dest, GET_MODE (dest)))
7277: mem_last_set = INSN_CUID (record_dead_insn);
7278: }
7279:
7280: /* Update the records of when each REG was most recently set or killed
7281: for the things done by INSN. This is the last thing done in processing
7282: INSN in the combiner loop.
7283:
7284: We update reg_last_set, reg_last_set_value, reg_last_death, and also the
7285: similar information mem_last_set (which insn most recently modified memory)
7286: and last_call_cuid (which insn was the most recent subroutine call). */
7287:
7288: static void
7289: record_dead_and_set_regs (insn)
7290: rtx insn;
7291: {
7292: register rtx link;
7293: for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
7294: {
7295: if (REG_NOTE_KIND (link) == REG_DEAD)
7296: reg_last_death[REGNO (XEXP (link, 0))] = insn;
7297: else if (REG_NOTE_KIND (link) == REG_INC)
7298: record_value_for_reg (XEXP (link, 0), insn, 0);
7299: }
7300:
7301: if (GET_CODE (insn) == CALL_INSN)
7302: last_call_cuid = mem_last_set = INSN_CUID (insn);
7303:
7304: record_dead_insn = insn;
7305: note_stores (PATTERN (insn), record_dead_and_set_regs_1);
7306: }
7307:
7308: /* Utility routine for the following function. Verify that all the registers
7309: mentioned in *LOC are valid when *LOC was part of a value set when
7310: label_tick == TICK. Return 0 if some are not.
7311:
7312: If REPLACE is non-zero, replace the invalid reference with
7313: (clobber (const_int 0)) and return 1. This replacement is useful because
7314: we often can get useful information about the form of a value (e.g., if
7315: it was produced by a shift that always produces -1 or 0) even though
7316: we don't know exactly what registers it was produced from. */
7317:
7318: static int
7319: get_last_value_validate (loc, tick, replace)
7320: rtx *loc;
7321: int tick;
7322: int replace;
7323: {
7324: rtx x = *loc;
7325: char *fmt = GET_RTX_FORMAT (GET_CODE (x));
7326: int len = GET_RTX_LENGTH (GET_CODE (x));
7327: int i;
7328:
7329: if (GET_CODE (x) == REG)
7330: {
7331: int regno = REGNO (x);
7332: int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
7333: ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
7334: int j;
7335:
7336: for (j = regno; j < endregno; j++)
7337: if (reg_last_set_invalid[j]
7338: /* If this is a pseudo-register that was only set once, it is
7339: always valid. */
7340: || (! (regno >= FIRST_PSEUDO_REGISTER && reg_n_sets[regno] == 1)
7341: && reg_last_set_label[j] > tick))
7342: {
7343: if (replace)
7344: *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
7345: return replace;
7346: }
7347:
7348: return 1;
7349: }
7350:
7351: for (i = 0; i < len; i++)
7352: if ((fmt[i] == 'e'
7353: && get_last_value_validate (&XEXP (x, i), tick, replace) == 0)
7354: /* Don't bother with these. They shouldn't occur anyway. */
7355: || fmt[i] == 'E')
7356: return 0;
7357:
7358: /* If we haven't found a reason for it to be invalid, it is valid. */
7359: return 1;
7360: }
7361:
7362: /* Get the last value assigned to X, if known. Some registers
7363: in the value may be replaced with (clobber (const_int 0)) if their value
7364: is known longer known reliably. */
7365:
7366: static rtx
7367: get_last_value (x)
7368: rtx x;
7369: {
7370: int regno;
7371: rtx value;
7372:
7373: /* If this is a non-paradoxical SUBREG, get the value of its operand and
7374: then convert it to the desired mode. If this is a paradoxical SUBREG,
7375: we cannot predict what values the "extra" bits might have. */
7376: if (GET_CODE (x) == SUBREG
7377: && subreg_lowpart_p (x)
7378: && (GET_MODE_SIZE (GET_MODE (x))
7379: <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7380: && (value = get_last_value (SUBREG_REG (x))) != 0)
7381: return gen_lowpart_for_combine (GET_MODE (x), value);
7382:
7383: if (GET_CODE (x) != REG)
7384: return 0;
7385:
7386: regno = REGNO (x);
7387: value = reg_last_set_value[regno];
7388:
7389: /* If we don't have a value, it isn't for this basic block, or if it was
7390: set in a later insn that the ones we are processing, return 0. */
7391:
7392: if (value == 0
7393: || (reg_n_sets[regno] != 1
7394: && (reg_last_set_label[regno] != label_tick
7395: || INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)))
7396: return 0;
7397:
7398: /* If the value has all its register valid, return it. */
7399: if (get_last_value_validate (&value, reg_last_set_label[regno], 0))
7400: return value;
7401:
7402: /* Otherwise, make a copy and replace any invalid register with
7403: (clobber (const_int 0)). If that fails for some reason, return 0. */
7404:
7405: value = copy_rtx (value);
7406: if (get_last_value_validate (&value, reg_last_set_label[regno], 1))
7407: return value;
7408:
7409: return 0;
7410: }
7411:
7412: /* Return nonzero if expression X refers to a REG or to memory
7413: that is set in an instruction more recent than FROM_CUID. */
7414:
7415: static int
7416: use_crosses_set_p (x, from_cuid)
7417: register rtx x;
7418: int from_cuid;
7419: {
7420: register char *fmt;
7421: register int i;
7422: register enum rtx_code code = GET_CODE (x);
7423:
7424: if (code == REG)
7425: {
7426: register int regno = REGNO (x);
7427: #ifdef PUSH_ROUNDING
7428: /* Don't allow uses of the stack pointer to be moved,
7429: because we don't know whether the move crosses a push insn. */
7430: if (regno == STACK_POINTER_REGNUM)
7431: return 1;
7432: #endif
7433: return (reg_last_set[regno]
7434: && INSN_CUID (reg_last_set[regno]) > from_cuid);
7435: }
7436:
7437: if (code == MEM && mem_last_set > from_cuid)
7438: return 1;
7439:
7440: fmt = GET_RTX_FORMAT (code);
7441:
7442: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7443: {
7444: if (fmt[i] == 'E')
7445: {
7446: register int j;
7447: for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7448: if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
7449: return 1;
7450: }
7451: else if (fmt[i] == 'e'
7452: && use_crosses_set_p (XEXP (x, i), from_cuid))
7453: return 1;
7454: }
7455: return 0;
7456: }
7457:
7458: /* Define three variables used for communication between the following
7459: routines. */
7460:
7461: static int reg_dead_regno, reg_dead_endregno;
7462: static int reg_dead_flag;
7463:
7464: /* Function called via note_stores from reg_dead_at_p.
7465:
7466: If DEST is within [reg_dead_rengno, reg_dead_endregno), set
7467: reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
7468:
7469: static void
7470: reg_dead_at_p_1 (dest, x)
7471: rtx dest;
7472: rtx x;
7473: {
7474: int regno, endregno;
7475:
7476: if (GET_CODE (dest) != REG)
7477: return;
7478:
7479: regno = REGNO (dest);
7480: endregno = regno + (regno < FIRST_PSEUDO_REGISTER
7481: ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
7482:
7483: if (reg_dead_endregno > regno && reg_dead_regno < endregno)
7484: reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
7485: }
7486:
7487: /* Return non-zero if REG is known to be dead at INSN.
7488:
7489: We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
7490: referencing REG, it is dead. If we hit a SET referencing REG, it is
7491: live. Otherwise, see if it is live or dead at the start of the basic
7492: block we are in. */
7493:
7494: static int
7495: reg_dead_at_p (reg, insn)
7496: rtx reg;
7497: rtx insn;
7498: {
7499: int block, i;
7500:
7501: /* Set variables for reg_dead_at_p_1. */
7502: reg_dead_regno = REGNO (reg);
7503: reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
7504: ? HARD_REGNO_NREGS (reg_dead_regno,
7505: GET_MODE (reg))
7506: : 1);
7507:
7508: reg_dead_flag = 0;
7509:
7510: /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
7511: beginning of function. */
7512: for (; insn && GET_CODE (insn) != CODE_LABEL;
7513: insn = prev_nonnote_insn (insn))
7514: {
7515: note_stores (PATTERN (insn), reg_dead_at_p_1);
7516: if (reg_dead_flag)
7517: return reg_dead_flag == 1 ? 1 : 0;
7518:
7519: if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
7520: return 1;
7521: }
7522:
7523: /* Get the basic block number that we were in. */
7524: if (insn == 0)
7525: block = 0;
7526: else
7527: {
7528: for (block = 0; block < n_basic_blocks; block++)
7529: if (insn == basic_block_head[block])
7530: break;
7531:
7532: if (block == n_basic_blocks)
7533: return 0;
7534: }
7535:
7536: for (i = reg_dead_regno; i < reg_dead_endregno; i++)
7537: if (basic_block_live_at_start[block][i / HOST_BITS_PER_INT]
7538: & (1 << (i % HOST_BITS_PER_INT)))
7539: return 0;
7540:
7541: return 1;
7542: }
7543:
7544: /* Remove register number REGNO from the dead registers list of INSN.
7545:
7546: Return the note used to record the death, if there was one. */
7547:
7548: rtx
7549: remove_death (regno, insn)
7550: int regno;
7551: rtx insn;
7552: {
7553: register rtx note = find_regno_note (insn, REG_DEAD, regno);
7554:
7555: if (note)
7556: remove_note (insn, note);
7557:
7558: return note;
7559: }
7560:
7561: /* For each register (hardware or pseudo) used within expression X, if its
7562: death is in an instruction with cuid between FROM_CUID (inclusive) and
7563: TO_INSN (exclusive), put a REG_DEAD note for that register in the
7564: list headed by PNOTES.
7565:
7566: This is done when X is being merged by combination into TO_INSN. These
7567: notes will then be distributed as needed. */
7568:
7569: static void
7570: move_deaths (x, from_cuid, to_insn, pnotes)
7571: rtx x;
7572: int from_cuid;
7573: rtx to_insn;
7574: rtx *pnotes;
7575: {
7576: register char *fmt;
7577: register int len, i;
7578: register enum rtx_code code = GET_CODE (x);
7579:
7580: if (code == REG)
7581: {
7582: register int regno = REGNO (x);
7583: register rtx where_dead = reg_last_death[regno];
7584:
7585: if (where_dead && INSN_CUID (where_dead) >= from_cuid
7586: && INSN_CUID (where_dead) < INSN_CUID (to_insn))
7587: {
7588: rtx note = remove_death (regno, reg_last_death[regno]);
7589:
7590: /* It is possible for the call above to return 0. This can occur
7591: when reg_last_death points to I2 or I1 that we combined with.
7592: In that case make a new note. */
7593:
7594: if (note)
7595: {
7596: XEXP (note, 1) = *pnotes;
7597: *pnotes = note;
7598: }
7599: else
7600: *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
7601: }
7602:
7603: return;
7604: }
7605:
7606: else if (GET_CODE (x) == SET)
7607: {
7608: rtx dest = SET_DEST (x);
7609:
7610: move_deaths (SET_SRC (x), from_cuid, to_insn, pnotes);
7611:
7612: if (GET_CODE (dest) == ZERO_EXTRACT)
7613: {
7614: move_deaths (XEXP (dest, 1), from_cuid, to_insn, pnotes);
7615: move_deaths (XEXP (dest, 2), from_cuid, to_insn, pnotes);
7616: }
7617:
7618: while (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SUBREG
7619: || GET_CODE (dest) == STRICT_LOW_PART)
7620: dest = XEXP (dest, 0);
7621:
7622: if (GET_CODE (dest) == MEM)
7623: move_deaths (XEXP (dest, 0), from_cuid, to_insn, pnotes);
7624: return;
7625: }
7626:
7627: else if (GET_CODE (x) == CLOBBER)
7628: return;
7629:
7630: len = GET_RTX_LENGTH (code);
7631: fmt = GET_RTX_FORMAT (code);
7632:
7633: for (i = 0; i < len; i++)
7634: {
7635: if (fmt[i] == 'E')
7636: {
7637: register int j;
7638: for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7639: move_deaths (XVECEXP (x, i, j), from_cuid, to_insn, pnotes);
7640: }
7641: else if (fmt[i] == 'e')
7642: move_deaths (XEXP (x, i), from_cuid, to_insn, pnotes);
7643: }
7644: }
7645:
7646: /* Return 1 if REG is the target of a bit-field assignment in BODY, the
7647: pattern of an insn. */
7648:
7649: static int
7650: reg_bitfield_target_p (reg, body)
7651: rtx reg;
7652: rtx body;
7653: {
7654: int i;
7655:
7656: if (GET_CODE (body) == SET)
7657: return ((GET_CODE (SET_DEST (body)) == ZERO_EXTRACT
1.1.1.2 ! root 7658: && rtx_equal_p (reg, XEXP (SET_DEST (body), 0)))
1.1 root 7659: || (GET_CODE (SET_DEST (body)) == STRICT_LOW_PART
1.1.1.2 ! root 7660: && rtx_equal_p (reg, SUBREG_REG (XEXP (SET_DEST (body), 0)))));
1.1 root 7661:
7662: else if (GET_CODE (body) == PARALLEL)
7663: for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
7664: if (reg_bitfield_target_p (reg, XVECEXP (body, 0, i)))
7665: return 1;
7666:
7667: return 0;
7668: }
7669:
7670: /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
7671: as appropriate. I3 and I2 are the insns resulting from the combination
7672: insns including FROM (I2 may be zero).
7673:
7674: ELIM_I2 and ELIM_I1 are either zero or registers that we know will
7675: not need REG_DEAD notes because they are being substituted for. This
7676: saves searching in the most common cases.
7677:
7678: Each note in the list is either ignored or placed on some insns, depending
7679: on the type of note. */
7680:
7681: static void
7682: distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
7683: rtx notes;
7684: rtx from_insn;
7685: rtx i3, i2;
7686: rtx elim_i2, elim_i1;
7687: {
7688: rtx note, next_note;
7689: rtx tem;
7690:
7691: for (note = notes; note; note = next_note)
7692: {
7693: rtx place = 0, place2 = 0;
7694:
7695: /* If this NOTE references a pseudo register, ensure it references
7696: the latest copy of that register. */
7697: if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
7698: && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
7699: XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
7700:
7701: next_note = XEXP (note, 1);
7702: switch (REG_NOTE_KIND (note))
7703: {
7704: case REG_UNUSED:
7705: /* If this register is set or clobbered in I3, put the note there
7706: unless there is one already. */
7707: if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
7708: {
7709: if (! (GET_CODE (XEXP (note, 0)) == REG
7710: ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
7711: : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
7712: place = i3;
7713: }
7714: /* Otherwise, if this register is used by I3, then this register
7715: now dies here, so we must put a REG_DEAD note here unless there
7716: is one already. */
7717: else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
7718: && ! (GET_CODE (XEXP (note, 0)) == REG
7719: ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
7720: : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
7721: {
7722: PUT_REG_NOTE_KIND (note, REG_DEAD);
7723: place = i3;
7724: }
7725: break;
7726:
7727: case REG_EQUAL:
7728: case REG_EQUIV:
7729: case REG_NONNEG:
7730: /* These notes say something about results of an insn. We can
7731: only support them if they used to be on I3 in which case they
7732: remain on I3. Otherwise they are ignored. */
7733: if (from_insn == i3)
7734: place = i3;
7735: break;
7736:
7737: case REG_INC:
7738: case REG_NO_CONFLICT:
7739: case REG_LABEL:
7740: /* These notes say something about how a register is used. They must
7741: be present on any use of the register in I2 or I3. */
7742: if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
7743: place = i3;
7744:
7745: if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
7746: {
7747: if (place)
7748: place2 = i2;
7749: else
7750: place = i2;
7751: }
7752: break;
7753:
7754: case REG_WAS_0:
7755: /* It is too much trouble to try to see if this note is still
7756: correct in all situations. It is better to simply delete it. */
7757: break;
7758:
7759: case REG_RETVAL:
7760: /* If the insn previously containing this note still exists,
7761: put it back where it was. Otherwise move it to the previous
7762: insn. Adjust the corresponding REG_LIBCALL note. */
7763: if (GET_CODE (from_insn) != NOTE)
7764: place = from_insn;
7765: else
7766: {
7767: tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, 0);
7768: place = prev_real_insn (from_insn);
7769: if (tem && place)
7770: XEXP (tem, 0) = place;
7771: }
7772: break;
7773:
7774: case REG_LIBCALL:
7775: /* This is handled similarly to REG_RETVAL. */
7776: if (GET_CODE (from_insn) != NOTE)
7777: place = from_insn;
7778: else
7779: {
7780: tem = find_reg_note (XEXP (note, 0), REG_RETVAL, 0);
7781: place = next_real_insn (from_insn);
7782: if (tem && place)
7783: XEXP (tem, 0) = place;
7784: }
7785: break;
7786:
7787: case REG_DEAD:
7788: /* If the register is used as an input in I3, it dies there.
7789: Similarly for I2, if it is non-zero and adjacent to I3.
7790:
7791: If the register is not used as an input in either I3 or I2
7792: and it is not one of the registers we were supposed to eliminate,
7793: there are two possibilities. We might have a non-adjacent I2
7794: or we might have somehow eliminated an additional register
7795: from a computation. For example, we might have had A & B where
7796: we discover that B will always be zero. In this case we will
7797: eliminate the reference to A.
7798:
7799: In both cases, we must search to see if we can find a previous
7800: use of A and put the death note there. */
7801:
7802: if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
7803: place = i3;
7804: else if (i2 != 0 && next_nonnote_insn (i2) == i3
7805: && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
7806: place = i2;
7807:
7808: if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
7809: break;
7810:
7811: if (place == 0)
7812: for (tem = prev_nonnote_insn (i3);
7813: tem && (GET_CODE (tem) == INSN
7814: || GET_CODE (tem) == CALL_INSN);
7815: tem = prev_nonnote_insn (tem))
7816: {
7817: /* If the register is being set at TEM, see if that is all
7818: TEM is doing. If so, delete TEM. Otherwise, make this
7819: into a REG_UNUSED note instead. */
7820: if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
7821: {
7822: rtx set = single_set (tem);
7823:
1.1.1.2 ! root 7824: /* Verify that it was the set, and not a clobber that
! 7825: modified the register. */
! 7826:
! 7827: if (set != 0 && ! side_effects_p (SET_SRC (set))
! 7828: && rtx_equal_p (XEXP (note, 0), SET_DEST (set)))
1.1 root 7829: {
7830: /* Move the notes and links of TEM elsewhere.
7831: This might delete other dead insns recursively.
7832: First set the pattern to something that won't use
7833: any register. */
7834:
7835: PATTERN (tem) = pc_rtx;
7836:
7837: distribute_notes (REG_NOTES (tem), tem, tem, 0, 0, 0);
7838: distribute_links (LOG_LINKS (tem));
7839:
7840: PUT_CODE (tem, NOTE);
7841: NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
7842: NOTE_SOURCE_FILE (tem) = 0;
7843: }
7844: else
7845: {
7846: PUT_REG_NOTE_KIND (note, REG_UNUSED);
7847:
7848: /* If there isn't already a REG_UNUSED note, put one
7849: here. */
7850: if (! find_regno_note (tem, REG_UNUSED,
7851: REGNO (XEXP (note, 0))))
7852: place = tem;
7853: break;
7854: }
7855: }
7856: else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem)))
7857: {
7858: place = tem;
7859: break;
7860: }
7861: }
7862:
7863: /* If the register is set or already dead at PLACE, we needn't do
7864: anything with this note if it is still a REG_DEAD note.
7865:
7866: Note that we cannot use just `dead_or_set_p' here since we can
7867: convert an assignment to a register into a bit-field assignment.
7868: Therefore, we must also omit the note if the register is the
7869: target of a bitfield assignment. */
7870:
7871: if (place && REG_NOTE_KIND (note) == REG_DEAD)
7872: {
7873: int regno = REGNO (XEXP (note, 0));
7874:
7875: if (dead_or_set_p (place, XEXP (note, 0))
7876: || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
7877: {
7878: /* Unless the register previously died in PLACE, clear
7879: reg_last_death. [I no longer understand why this is
7880: being done.] */
7881: if (reg_last_death[regno] != place)
7882: reg_last_death[regno] = 0;
7883: place = 0;
7884: }
7885: else
7886: reg_last_death[regno] = place;
7887:
7888: /* If this is a death note for a hard reg that is occupying
7889: multiple registers, ensure that we are still using all
7890: parts of the object. If we find a piece of the object
7891: that is unused, we must add a USE for that piece before
7892: PLACE and put the appropriate REG_DEAD note on it.
7893:
7894: An alternative would be to put a REG_UNUSED for the pieces
7895: on the insn that set the register, but that can't be done if
7896: it is not in the same block. It is simpler, though less
7897: efficient, to add the USE insns. */
7898:
7899: if (place && regno < FIRST_PSEUDO_REGISTER
7900: && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
7901: {
7902: int endregno
7903: = regno + HARD_REGNO_NREGS (regno,
7904: GET_MODE (XEXP (note, 0)));
7905: int all_used = 1;
7906: int i;
7907:
7908: for (i = regno; i < endregno; i++)
7909: if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0))
7910: {
7911: rtx piece = gen_rtx (REG, word_mode, i);
7912: rtx use_insn
7913: = emit_insn_before (gen_rtx (USE, VOIDmode, piece),
7914: place);
7915:
1.1.1.2 ! root 7916: all_used = 0;
1.1 root 7917: REG_NOTES (use_insn)
7918: = gen_rtx (EXPR_LIST, REG_DEAD, piece,
7919: REG_NOTES (use_insn));
7920: }
7921:
7922: if (! all_used)
7923: {
7924: /* Put only REG_DEAD notes for pieces that are
7925: still used and that are not already dead or set. */
7926:
7927: for (i = regno; i < endregno; i++)
7928: {
7929: rtx piece = gen_rtx (REG, word_mode, i);
7930:
7931: if (reg_referenced_p (piece, PATTERN (place))
7932: && ! dead_or_set_p (place, piece)
7933: && ! reg_bitfield_target_p (piece,
7934: PATTERN (place)))
7935: REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
7936: piece,
7937: REG_NOTES (place));
7938: }
7939:
7940: place = 0;
7941: }
7942: }
7943: }
7944: break;
7945:
7946: default:
7947: /* Any other notes should not be present at this point in the
7948: compilation. */
7949: abort ();
7950: }
7951:
7952: if (place)
7953: {
7954: XEXP (note, 1) = REG_NOTES (place);
7955: REG_NOTES (place) = note;
7956: }
7957:
7958: if (place2)
7959: REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
7960: XEXP (note, 0), REG_NOTES (place2));
7961: }
7962: }
7963:
7964: /* Similarly to above, distribute the LOG_LINKS that used to be present on
1.1.1.2 ! root 7965: I3, I2, and I1 to new locations. This is also called in one case to
! 7966: add a link pointing at I3 when I3's destination is changed. */
1.1 root 7967:
7968: static void
7969: distribute_links (links)
7970: rtx links;
7971: {
7972: rtx link, next_link;
7973:
7974: for (link = links; link; link = next_link)
7975: {
7976: rtx place = 0;
7977: rtx insn;
7978: rtx set, reg;
7979:
7980: next_link = XEXP (link, 1);
7981:
7982: /* If the insn that this link points to is a NOTE or isn't a single
7983: set, ignore it. In the latter case, it isn't clear what we
7984: can do other than ignore the link, since we can't tell which
7985: register it was for. Such links wouldn't be used by combine
7986: anyway.
7987:
7988: It is not possible for the destination of the target of the link to
7989: have been changed by combine. The only potential of this is if we
7990: replace I3, I2, and I1 by I3 and I2. But in that case the
7991: destination of I2 also remains unchanged. */
7992:
7993: if (GET_CODE (XEXP (link, 0)) == NOTE
7994: || (set = single_set (XEXP (link, 0))) == 0)
7995: continue;
7996:
7997: reg = SET_DEST (set);
7998: while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
7999: || GET_CODE (reg) == SIGN_EXTRACT
8000: || GET_CODE (reg) == STRICT_LOW_PART)
8001: reg = XEXP (reg, 0);
8002:
8003: /* A LOG_LINK is defined as being placed on the first insn that uses
8004: a register and points to the insn that sets the register. Start
8005: searching at the next insn after the target of the link and stop
8006: when we reach a set of the register or the end of the basic block.
8007:
8008: Note that this correctly handles the link that used to point from
1.1.1.2 ! root 8009: I3 to I2. Also note that not much searching is typically done here
1.1 root 8010: since most links don't point very far away. */
8011:
8012: for (insn = NEXT_INSN (XEXP (link, 0));
8013: (insn && GET_CODE (insn) != CODE_LABEL
8014: && GET_CODE (PREV_INSN (insn)) != JUMP_INSN);
8015: insn = NEXT_INSN (insn))
8016: if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
8017: && reg_overlap_mentioned_p (reg, PATTERN (insn)))
8018: {
8019: if (reg_referenced_p (reg, PATTERN (insn)))
8020: place = insn;
8021: break;
8022: }
8023:
8024: /* If we found a place to put the link, place it there unless there
8025: is already a link to the same insn as LINK at that point. */
8026:
8027: if (place)
8028: {
8029: rtx link2;
8030:
8031: for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
8032: if (XEXP (link2, 0) == XEXP (link, 0))
8033: break;
8034:
8035: if (link2 == 0)
8036: {
8037: XEXP (link, 1) = LOG_LINKS (place);
8038: LOG_LINKS (place) = link;
8039: }
8040: }
8041: }
8042: }
8043:
8044: void
8045: dump_combine_stats (file)
8046: FILE *file;
8047: {
8048: fprintf
8049: (file,
8050: ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
8051: combine_attempts, combine_merges, combine_extras, combine_successes);
8052: }
8053:
8054: void
8055: dump_combine_total_stats (file)
8056: FILE *file;
8057: {
8058: fprintf
8059: (file,
8060: "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
8061: total_attempts, total_merges, total_extras, total_successes);
8062: }
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