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1.1 root 1: /* Optimize by combining instructions for GNU compiler.
1.1.1.2 root 2: Copyright (C) 1987, 1988 Free Software Foundation, Inc.
1.1 root 3:
4: This file is part of GNU CC.
5:
6: GNU CC is distributed in the hope that it will be useful,
7: but WITHOUT ANY WARRANTY. No author or distributor
8: accepts responsibility to anyone for the consequences of using it
9: or for whether it serves any particular purpose or works at all,
10: unless he says so in writing. Refer to the GNU CC General Public
11: License for full details.
12:
13: Everyone is granted permission to copy, modify and redistribute
14: GNU CC, but only under the conditions described in the
15: GNU CC General Public License. A copy of this license is
16: supposed to have been given to you along with GNU CC so you
17: can know your rights and responsibilities. It should be in a
18: file named COPYING. Among other things, the copyright notice
19: and this notice must be preserved on all copies. */
20:
21:
22: /* This module is essentially the "combiner" phase of the U. of Arizona
23: Portable Optimizer, but redone to work on our list-structured
24: representation for RTL instead of their string representation.
25:
26: The LOG_LINKS of each insn identify the most recent assignment
27: to each REG used in the insn. It is a list of previous insns,
28: each of which contains a SET for a REG that is used in this insn
29: and not used or set in between. LOG_LINKs never cross basic blocks.
30: They were set up by the preceding pass (lifetime analysis).
31:
32: We try to combine each pair of insns joined by a logical link.
33: We also try to combine triples of insns A, B and C when
34: C has a link back to B and B has a link back to A.
35:
36: LOG_LINKS does not have links for use of the CC0. They don't
37: need to, because the insn that sets the CC0 is always immediately
38: before the insn that tests it. So we always regard a branch
39: insn as having a logical link to the preceding insn.
40:
41: We check (with use_crosses_set_p) to avoid combining in such a way
42: as to move a computation to a place where its value would be different.
43:
44: Combination is done by mathematically substituting the previous
45: insn(s) values for the regs they set into the expressions in
46: the later insns that refer to these regs. If the result is a valid insn
47: for our target machine, according to the machine description,
48: we install it, delete the earlier insns, and update the data flow
49: information (LOG_LINKS and REG_NOTES) for what we did.
50:
51: To simplify substitution, we combine only when the earlier insn(s)
52: consist of only a single assignment. To simplify updating afterward,
53: we never combine when a subroutine call appears in the middle.
54:
55: Since we do not represent assignments to CC0 explicitly except when that
56: is all an insn does, there is no LOG_LINKS entry in an insn that uses
57: the condition code for the insn that set the condition code.
58: Fortunately, these two insns must be consecutive.
59: Therefore, every JUMP_INSN is taken to have an implicit logical link
60: to the preceding insn. This is not quite right, since non-jumps can
61: also use the condition code; but in practice such insns would not
62: combine anyway. */
63:
64: #include "config.h"
65: #include "rtl.h"
1.1.1.2 root 66: #include "flags.h"
1.1 root 67: #include "regs.h"
68: #include "basic-block.h"
69: #include "insn-config.h"
70: #include "recog.h"
71:
72: #define max(A,B) ((A) > (B) ? (A) : (B))
73: #define min(A,B) ((A) < (B) ? (A) : (B))
74:
1.1.1.2 root 75: /* It is not safe to use ordinary gen_lowpart in combine.
76: Use gen_lowpart_for_combine instead. See comments there. */
77: #define gen_lowpart dont_use_gen_lowpart_you_dummy
78:
1.1 root 79: /* Number of attempts to combine instructions in this function. */
80:
81: static int combine_attempts;
82:
83: /* Number of attempts that got as far as substitution in this function. */
84:
85: static int combine_merges;
86:
87: /* Number of instructions combined with added SETs in this function. */
88:
89: static int combine_extras;
90:
91: /* Number of instructions combined in this function. */
92:
93: static int combine_successes;
94:
95: /* Totals over entire compilation. */
96:
97: static int total_attempts, total_merges, total_extras, total_successes;
98:
99:
100: /* Vector mapping INSN_UIDs to cuids.
101: The cuids are like uids but increase monononically always.
102: Combine always uses cuids so that it can compare them.
103: But actually renumbering the uids, which we used to do,
104: proves to be a bad idea because it makes it hard to compare
105: the dumps produced by earlier passes with those from later passes. */
106:
107: static short *uid_cuid;
108:
109: /* Get the cuid of an insn. */
110:
111: #define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)])
112:
113:
114: /* Record last point of death of (hard or pseudo) register n. */
115:
116: static rtx *reg_last_death;
117:
118: /* Record last point of modification of (hard or pseudo) register n. */
119:
120: static rtx *reg_last_set;
121:
122: /* Record the cuid of the last insn that invalidated memory
123: (anything that writes memory, and subroutine calls). */
124:
125: static int mem_last_set;
126:
127: /* Record the cuid of the last CALL_INSN
128: so we can tell whether a potential combination crosses any calls. */
129:
130: static int last_call_cuid;
131:
132: /* When `subst' is called, this is the insn that is being modified
133: (by combining in a previous insn). The PATTERN of this insn
134: is still the old pattern partially modified and it should not be
135: looked at, but this may be used to examine the successors of the insn
136: to judge whether a simplification is valid. */
137:
138: static rtx subst_insn;
139:
140: /* Record one modification to rtl structure
141: to be undone by storing old_contents into *where. */
142:
143: struct undo
144: {
145: rtx *where;
146: rtx old_contents;
147: };
148:
149: /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
150: num_undo says how many are currently recorded.
151: storage is nonzero if we must undo the allocation of new storage.
152: The value of storage is what to pass to obfree. */
153:
154: #define MAX_UNDO 10
155:
156: struct undobuf
157: {
158: int num_undo;
159: char *storage;
160: struct undo undo[MAX_UNDO];
161: };
162:
163: static struct undobuf undobuf;
164:
1.1.1.2 root 165: /* Number of times the pseudo being substituted for
166: was found and replaced. */
167:
168: static int n_occurrences;
169:
1.1 root 170: static void move_deaths ();
1.1.1.4 ! root 171: void remove_death ();
1.1 root 172: static void record_dead_and_set_regs ();
173: int regno_dead_p ();
174: static int use_crosses_set_p ();
1.1.1.4 ! root 175: static int try_combine ();
1.1 root 176: static rtx subst ();
177: static void undo_all ();
1.1.1.2 root 178: static void copy_substitutions ();
1.1 root 179: static void add_links ();
180: static void add_incs ();
1.1.1.2 root 181: static int insn_has_inc_p ();
1.1 root 182: static int adjacent_insns_p ();
183: static rtx simplify_and_const_int ();
184: static rtx gen_lowpart_for_combine ();
185: static void simplify_set_cc0_and ();
186:
187: /* Main entry point for combiner. F is the first insn of the function.
188: NREGS is the first unused pseudo-reg number. */
189:
190: void
191: combine_instructions (f, nregs)
192: rtx f;
193: int nregs;
194: {
195: register rtx insn;
196: register int i;
197: register rtx links, nextlinks;
198: rtx prev;
199:
200: combine_attempts = 0;
201: combine_merges = 0;
202: combine_extras = 0;
203: combine_successes = 0;
204:
205: reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
206: reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
207: bzero (reg_last_death, nregs * sizeof (rtx));
208: bzero (reg_last_set, nregs * sizeof (rtx));
209:
210: init_recog ();
211:
212: /* Compute maximum uid value so uid_cuid can be allocated. */
213:
214: for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
215: if (INSN_UID (insn) > i)
216: i = INSN_UID (insn);
217:
218: uid_cuid = (short *) alloca ((i + 1) * sizeof (short));
219:
220: /* Compute the mapping from uids to cuids.
221: Cuids are numbers assigned to insns, like uids,
222: except that cuids increase monotonically through the code. */
223:
224: for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
225: INSN_CUID (insn) = ++i;
226:
227: /* Now scan all the insns in forward order. */
228:
229: last_call_cuid = 0;
230: mem_last_set = 0;
231: prev = 0;
232:
233: for (insn = f; insn; insn = NEXT_INSN (insn))
234: {
235: if (GET_CODE (insn) == INSN
236: || GET_CODE (insn) == CALL_INSN
237: || GET_CODE (insn) == JUMP_INSN)
238: {
239: retry:
240: /* Try this insn with each insn it links back to. */
241:
242: for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
243: if (try_combine (insn, XEXP (links, 0), 0))
244: goto retry;
245:
246: /* Try each sequence of three linked insns ending with this one. */
247:
248: for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
249: if (GET_CODE (XEXP (links, 0)) != NOTE)
250: for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
251: nextlinks = XEXP (nextlinks, 1))
252: if (try_combine (insn, XEXP (links, 0), XEXP (nextlinks, 0)))
253: goto retry;
254:
255: /* Try to combine a jump insn that uses CC0
256: with a preceding insn that sets CC0, and maybe with its
257: logical predecessor as well.
258: This is how we make decrement-and-branch insns.
259: We need this special code because data flow connections
260: via CC0 do not get entered in LOG_LINKS. */
261:
262: if (GET_CODE (insn) == JUMP_INSN
263: && prev != 0
264: && GET_CODE (prev) == INSN
265: && GET_CODE (PATTERN (prev)) == SET
266: && GET_CODE (SET_DEST (PATTERN (prev))) == CC0)
267: {
268: if (try_combine (insn, prev, 0))
269: goto retry;
270:
271: if (GET_CODE (prev) != NOTE)
272: for (nextlinks = LOG_LINKS (prev); nextlinks;
273: nextlinks = XEXP (nextlinks, 1))
274: if (try_combine (insn, prev, XEXP (nextlinks, 0)))
275: goto retry;
276: }
277: #if 0
278: /* Turned off because on 68020 it takes four insns to make
279: something like (a[b / 32] & (1 << (31 - (b % 32)))) != 0
280: that could actually be optimized, and that's an unlikely piece of code. */
281: /* If an insn gets or sets a bit field, try combining it
282: with two different insns whose results it uses. */
283: if (GET_CODE (insn) == INSN
284: && GET_CODE (PATTERN (insn)) == SET
285: && (GET_CODE (SET_DEST (PATTERN (insn))) == ZERO_EXTRACT
286: || GET_CODE (SET_DEST (PATTERN (insn))) == SIGN_EXTRACT
287: || GET_CODE (SET_SRC (PATTERN (insn))) == ZERO_EXTRACT
288: || GET_CODE (SET_SRC (PATTERN (insn))) == SIGN_EXTRACT))
289: {
290: for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
291: if (GET_CODE (XEXP (links, 0)) != NOTE)
292: for (nextlinks = XEXP (links, 1); nextlinks;
293: nextlinks = XEXP (nextlinks, 1))
294: if (try_combine (insn, XEXP (links, 0), XEXP (nextlinks, 0)))
295: goto retry;
296: }
297: #endif
298: record_dead_and_set_regs (insn);
299: prev = insn;
300: }
301: else if (GET_CODE (insn) != NOTE)
302: prev = 0;
303: }
304: total_attempts += combine_attempts;
305: total_merges += combine_merges;
306: total_extras += combine_extras;
307: total_successes += combine_successes;
308: }
309:
310: /* Try to combine the insns I1 and I2 into I3.
311: Here I1 appears earlier than I2, which is earlier than I3.
312: I1 can be zero; then we combine just I2 into I3.
313:
314: Return 1 if successful; if that happens, I1 and I2 are pseudo-deleted
315: by turning them into NOTEs, and I3 is modified.
316: Return 0 if the combination does not work. Then nothing is changed. */
317:
318: static int
319: try_combine (i3, i2, i1)
320: register rtx i3, i2, i1;
321: {
322: register rtx newpat;
323: int added_sets_1 = 0;
324: int added_sets_2 = 0;
325: int total_sets;
326: int i2_is_used;
327: register rtx link;
328: int insn_code_number;
329: int recog_flags = 0;
330: rtx i2dest, i2src;
331: rtx i1dest, i1src;
1.1.1.2 root 332: int maxreg;
1.1 root 333:
334: combine_attempts++;
335:
336: /* Don't combine with something already used up by combination. */
337:
338: if (GET_CODE (i2) == NOTE
339: || (i1 && GET_CODE (i1) == NOTE))
340: return 0;
341:
342: /* Don't combine across a CALL_INSN, because that would possibly
343: change whether the life span of some REGs crosses calls or not,
344: and it is a pain to update that information. */
345:
346: if (INSN_CUID (i2) < last_call_cuid
347: || (i1 && INSN_CUID (i1) < last_call_cuid))
348: return 0;
349:
350: /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
351: That REG must be either set or dead by the final instruction
352: (so that we can safely forget about setting it).
353: Also test use_crosses_set_p to make sure that the value
354: that is to be substituted for the register
355: does not use any registers whose values alter in between.
356: Do not try combining with moves from one register to another
357: since it is better to let them be tied by register allocation.
1.1.1.2 root 358: (There is a switch to permit such combination; except the insns
359: that copy a function value into another register are never combined
360: because moving that too far away from the function call could cause
361: something else to be stored in that register in the interim.)
1.1 root 362:
363: A set of a SUBREG is considered as if it were a set from
364: SUBREG. Thus, (SET (SUBREG:X (REG:Y...)) (something:X...))
365: is handled by substituting (SUBREG:Y (something:X...)) for (REG:Y...). */
366:
367: if (GET_CODE (PATTERN (i2)) != SET)
368: return 0;
369: i2dest = SET_DEST (PATTERN (i2));
370: i2src = SET_SRC (PATTERN (i2));
371: if (GET_CODE (i2dest) == SUBREG)
372: {
373: i2dest = SUBREG_REG (i2dest);
374: i2src = gen_rtx (SUBREG, GET_MODE (i2dest), i2src, 0);
375: }
1.1.1.4 ! root 376: /* Don't eliminate a store in the stack pointer. */
! 377: if (i2dest == stack_pointer_rtx)
! 378: return 0;
1.1 root 379: if (GET_CODE (i2dest) != CC0
380: && (GET_CODE (i2dest) != REG
1.1.1.2 root 381: || (GET_CODE (i2src) == REG
382: && (!flag_combine_regs
383: || FUNCTION_VALUE_REGNO_P (REGNO (i2src))))
384: || GET_CODE (i2src) == CALL
1.1 root 385: || use_crosses_set_p (i2src, INSN_CUID (i2))))
386: return 0;
387:
388: if (i1 != 0)
389: {
390: if (GET_CODE (PATTERN (i1)) != SET)
391: return 0;
392: i1dest = SET_DEST (PATTERN (i1));
393: i1src = SET_SRC (PATTERN (i1));
394: if (GET_CODE (i1dest) == SUBREG)
395: {
396: i1dest = SUBREG_REG (i1dest);
397: i1src = gen_rtx (SUBREG, GET_MODE (i1dest), i1src, 0);
398: }
1.1.1.4 ! root 399: if (i1dest == stack_pointer_rtx)
! 400: return 0;
1.1 root 401: if (GET_CODE (i1dest) != CC0
402: && (GET_CODE (i1dest) != REG
1.1.1.2 root 403: || (GET_CODE (i1src) == REG
404: && (!flag_combine_regs
405: || FUNCTION_VALUE_REGNO_P (REGNO (i1src))))
406: || GET_CODE (i1src) == CALL
1.1 root 407: || use_crosses_set_p (i1src, INSN_CUID (i1))))
408: return 0;
409: }
410:
411: /* If I1 or I2 contains an autoincrement or autodecrement,
412: make sure that register is not used between there and I3.
413: Also insist that I3 not be a jump; if it were one
414: and the incremented register were spilled, we would lose. */
1.1.1.2 root 415: if ((link = find_reg_note (i2, REG_INC, 0)) != 0
416: && (GET_CODE (i3) == JUMP_INSN
1.1.1.3 root 417: || reg_used_between_p (XEXP (link, 0), i2, i3)
418: || reg_mentioned_p (XEXP (link, 0), i3)))
1.1.1.2 root 419: return 0;
1.1 root 420:
1.1.1.2 root 421: if (i1 && (link = find_reg_note (i1, REG_INC, 0)) != 0
422: && (GET_CODE (i3) == JUMP_INSN
1.1.1.3 root 423: || reg_used_between_p (XEXP (link, 0), i1, i3)
424: || reg_mentioned_p (XEXP (link, 0), i3)))
1.1.1.2 root 425: return 0;
1.1 root 426:
427: /* See if the SETs in i1 or i2 need to be kept around in the merged
428: instruction: whenever the value set there is still needed past i3. */
429: added_sets_2 = (GET_CODE (i2dest) != CC0
430: && ! dead_or_set_p (i3, i2dest));
431: if (i1)
432: added_sets_1 = ! (dead_or_set_p (i3, i1dest)
433: || dead_or_set_p (i2, i1dest));
434:
435: combine_merges++;
436:
437: undobuf.num_undo = 0;
438: undobuf.storage = 0;
439:
440: /* Substitute in the latest insn for the regs set by the earlier ones. */
441:
1.1.1.2 root 442: maxreg = max_reg_num ();
443:
1.1 root 444: subst_insn = i3;
1.1.1.2 root 445: n_occurrences = 0; /* `subst' counts here */
446:
1.1 root 447: newpat = subst (PATTERN (i3), i2dest, i2src);
448: /* Record whether i2's body now appears within i3's body. */
1.1.1.2 root 449: i2_is_used = n_occurrences;
1.1 root 450:
451: if (i1)
1.1.1.2 root 452: {
453: n_occurrences = 0;
454: newpat = subst (newpat, i1dest, i1src);
455: }
1.1 root 456:
457: if (GET_CODE (PATTERN (i3)) == SET
458: && SET_DEST (PATTERN (i3)) == cc0_rtx
1.1.1.2 root 459: && (GET_CODE (SET_SRC (PATTERN (i3))) == AND
460: || GET_CODE (SET_SRC (PATTERN (i3))) == LSHIFTRT)
1.1 root 461: && next_insn_tests_no_inequality (i3))
462: simplify_set_cc0_and (i3);
463:
1.1.1.2 root 464: if (max_reg_num () != maxreg)
465: abort ();
466:
1.1 root 467: /* If the actions of the earler insns must be kept
468: in addition to substituting them into the latest one,
469: we must make a new PARALLEL for the latest insn
470: to hold additional the SETs. */
471:
472: if (added_sets_1 || added_sets_2)
473: {
474: combine_extras++;
475:
476: /* Arrange to free later what we allocate now
477: if we don't accept this combination. */
478: if (!undobuf.storage)
479: undobuf.storage = (char *) oballoc (0);
480:
481: if (GET_CODE (newpat) == PARALLEL)
482: {
1.1.1.2 root 483: rtvec old = XVEC (newpat, 0);
1.1 root 484: total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1.1.1.2 root 485: newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
486: bcopy (&old->elem[0], &XVECEXP (newpat, 0, 0),
487: sizeof (old->elem[0]) * old->num_elem);
1.1 root 488: }
489: else
490: {
1.1.1.2 root 491: rtx old = newpat;
1.1 root 492: total_sets = 1 + added_sets_1 + added_sets_2;
1.1.1.2 root 493: newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
494: XVECEXP (newpat, 0, 0) = old;
1.1 root 495: }
496: if (added_sets_1)
497: {
498: XVECEXP (newpat, 0, --total_sets) = PATTERN (i1);
499: }
500: if (added_sets_2)
501: {
502: /* If there is no I1, use I2's body as is. */
503: if (i1 == 0
504: /* If I2 was stuck into I3, then anything within it has
505: already had I1 substituted into it when that was done to I3. */
506: || i2_is_used)
507: {
508: XVECEXP (newpat, 0, --total_sets) = PATTERN (i2);
509: }
510: else
511: XVECEXP (newpat, 0, --total_sets)
512: = subst (PATTERN (i2), i1dest, i1src);
513: }
514: }
515:
1.1.1.2 root 516: /* Fail if an autoincrement side-effect has been duplicated. */
517: if ((i2_is_used > 1 && find_reg_note (i2, REG_INC, 0) != 0)
518: || (i1 != 0 && n_occurrences > 1 && find_reg_note (i1, REG_INC, 0) != 0))
519: {
520: undo_all ();
521: return 0;
522: }
523:
1.1 root 524: /* Is the result of combination a valid instruction? */
525: insn_code_number = recog (newpat, i3);
526:
527: if (insn_code_number >= 0)
528: {
529: /* Yes. Install it. */
530: register int regno;
531: INSN_CODE (i3) = insn_code_number;
532: PATTERN (i3) = newpat;
1.1.1.2 root 533: /* If anything was substituted more than once,
534: copy it to avoid invalid shared rtl structure. */
535: copy_substitutions ();
536: /* The data flowing into I2 now flows into I3.
537: But we cannot always move all of I2's LOG_LINKS into I3,
538: since they must go to a setting of a REG from the
539: first use following. If I2 was the first use following a set,
540: I3 is now a use, but it is not the first use
541: if some instruction between I2 and I3 is also a use.
542: Here, for simplicity, we move all the links only if
543: there are no real insns between I2 and I3.
544: Otherwise, we move only links that correspond to regs
545: that used to die in I2. They are always safe to move. */
546: add_links (i3, i2, adjacent_insns_p (i2, i3));
1.1 root 547: /* Most REGs that previously died in I2 now die in I3. */
548: move_deaths (i2src, INSN_CUID (i2), i3);
549: if (GET_CODE (i2dest) == REG)
550: {
551: /* If the reg formerly set in I2 died only once and that was in I3,
552: zero its use count so it won't make `reload' do any work. */
553: regno = REGNO (i2dest);
554: if (! added_sets_2)
1.1.1.2 root 555: {
556: reg_n_sets[regno]--;
557: /* Used to check && regno_dead_p (regno, i3) also here. */
558: if (reg_n_sets[regno] == 0
559: && ! (basic_block_live_at_start[0][regno / HOST_BITS_PER_INT]
560: & (1 << (regno % HOST_BITS_PER_INT))))
561: reg_n_refs[regno] = 0;
562: }
1.1 root 563: /* If a ref to REGNO was substituted into I3 from I2,
564: then it still dies there if it previously did.
565: Otherwise either REGNO never did die in I3 so remove_death is safe
566: or this entire life of REGNO is gone so remove its death. */
567: if (!added_sets_2
568: && ! reg_mentioned_p (i2dest, PATTERN (i3)))
569: remove_death (regno, i3);
570: }
571: /* Any registers previously autoincremented in I2
572: are now incremented in I3. */
573: add_incs (i3, REG_NOTES (i2));
574: if (i1)
575: {
576: /* Likewise, merge the info from I1 and get rid of it. */
1.1.1.2 root 577: add_links (i3, i1,
578: adjacent_insns_p (i1, i2) && adjacent_insns_p (i2, i3));
1.1 root 579: move_deaths (i1src, INSN_CUID (i1), i3);
580: if (GET_CODE (i1dest) == REG)
581: {
582: regno = REGNO (i1dest);
583: if (! added_sets_1)
1.1.1.2 root 584: {
585: reg_n_sets[regno]--;
586: /* Used to also check && regno_dead_p (regno, i3) here. */
587:
588: if (reg_n_sets[regno] == 0
589: && ! (basic_block_live_at_start[0][regno / HOST_BITS_PER_INT]
590: & (1 << (regno % HOST_BITS_PER_INT))))
591:
592: reg_n_refs[regno] = 0;
593: }
1.1 root 594: /* If a ref to REGNO was substituted into I3 from I1,
595: then it still dies there if it previously did.
596: Else either REGNO never did die in I3 so remove_death is safe
597: or this entire life of REGNO is gone so remove its death. */
598: if (! added_sets_1
599: && ! reg_mentioned_p (i1dest, PATTERN (i3)))
600: remove_death (regno, i3);
601: }
602: add_incs (i3, REG_NOTES (i1));
603: LOG_LINKS (i1) = 0;
604: PUT_CODE (i1, NOTE);
605: NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
606: NOTE_SOURCE_FILE (i1) = 0;
607: }
1.1.1.2 root 608: /* Get rid of I2. */
609: LOG_LINKS (i2) = 0;
610: PUT_CODE (i2, NOTE);
611: NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
612: NOTE_SOURCE_FILE (i2) = 0;
1.1 root 613:
614: combine_successes++;
615: return 1;
616: }
617:
618: /* Failure: change I3 back the way it was. */
619: undo_all ();
620:
621: return 0;
622: }
623:
624: /* Undo all the modifications recorded in undobuf. */
625:
626: static void
627: undo_all ()
628: {
629: register int i;
630: if (undobuf.num_undo > MAX_UNDO)
631: undobuf.num_undo = MAX_UNDO;
632: for (i = undobuf.num_undo - 1; i >= 0; i--)
633: *undobuf.undo[i].where = undobuf.undo[i].old_contents;
634: if (undobuf.storage)
635: obfree (undobuf.storage);
636: undobuf.num_undo = 0;
637: undobuf.storage = 0;
638: }
639:
1.1.1.2 root 640: /* If this insn had more than one substitution,
641: copy all but one, so that no invalid shared substructure is introduced. */
642:
643: static void
644: copy_substitutions ()
645: {
646: register int i;
647: if (undobuf.num_undo > 1)
648: {
649: for (i = undobuf.num_undo - 1; i >= 1; i--)
650: *undobuf.undo[i].where = copy_rtx (*undobuf.undo[i].where);
651: }
652: }
653:
1.1 root 654: /* Throughout X, replace FROM with TO, and return the result.
655: The result is TO if X is FROM;
656: otherwise the result is X, but its contents may have been modified.
657: If they were modified, a record was made in undobuf so that
658: undo_all will (among other things) return X to its original state.
659:
660: If the number of changes necessary is too much to record to undo,
661: the excess changes are not made, so the result is invalid.
662: The changes already made can still be undone.
663: undobuf.num_undo is incremented for such changes, so by testing that
1.1.1.2 root 664: the caller can tell whether the result is valid.
665:
666: `n_occurrences' is incremented each time FROM is replaced. */
1.1 root 667:
668: static rtx
669: subst (x, from, to)
670: register rtx x, from, to;
671: {
672: register char *fmt;
673: register int len, i;
674: register enum rtx_code code;
1.1.1.2 root 675: char was_replaced[2];
1.1 root 676:
1.1.1.2 root 677: #define SUBST(INTO, NEWVAL) \
678: do { if (undobuf.num_undo < MAX_UNDO) \
679: { \
680: undobuf.undo[undobuf.num_undo].where = &INTO; \
681: undobuf.undo[undobuf.num_undo].old_contents = INTO; \
682: INTO = NEWVAL; \
683: } \
684: undobuf.num_undo++; } while (0)
685:
686: /* FAKE_EXTEND_SAFE_P (MODE, FROM) is 1 if (subreg:MODE FROM 0) is a safe
687: replacement for (zero_extend:MODE FROM) or (sign_extend:MODE FROM).
688: If it is 0, that cannot be done because it might cause a badly aligned
689: memory reference. */
690:
1.1.1.3 root 691: /* Now we never do this for memory refs, because of the danger of
692: turning a reference to the last byte on a page into a page-crossing
693: reference that could get a spurious fault. It could be done safely
694: for certain cases but it's hard to check for them. */
695: #if 0
1.1.1.2 root 696: #define FAKE_EXTEND_SAFE_P(MODE, FROM) \
697: (GET_CODE (FROM) == REG || \
698: (GET_CODE (FROM) == MEM \
699: && offsetable_address_p ((MODE), XEXP ((FROM), 0)) \
700: && ! mode_dependent_address_p ((XEXP ((FROM), 0)))))
701: #else
702: #define FAKE_EXTEND_SAFE_P(MODE, FROM) (GET_CODE (FROM) == REG)
703: #endif
1.1 root 704:
705: if (x == from)
706: return to;
707:
1.1.1.2 root 708: /* It is possible to have a subexpression appear twice in the insn.
709: Suppose that FROM is a register that appears within TO.
710: Then, after that subexpression has been scanned once by `subst',
711: the second time it is scanned, TO may be found. If we were
712: to scan TO here, we would find FROM within it and create a
713: self-referent rtl structure which is completely wrong. */
714: if (x == to)
715: return to;
716:
1.1 root 717: code = GET_CODE (x);
718:
719: /* A little bit of algebraic simplification here. */
720: switch (code)
721: {
722: /* This case has no effect except to speed things up. */
723: case REG:
724: case CONST_INT:
725: case CONST:
726: case SYMBOL_REF:
727: case LABEL_REF:
728: case PC:
729: case CC0:
730: return x;
1.1.1.2 root 731: }
732:
733: was_replaced[0] = 0;
734: was_replaced[1] = 0;
735:
736: len = GET_RTX_LENGTH (code);
737: fmt = GET_RTX_FORMAT (code);
738:
739: /* Don't replace FROM where it is being stored in rather than used. */
740: if (code == SET && SET_DEST (x) == from)
741: fmt = "ie";
742: if (code == SET && GET_CODE (SET_DEST (x)) == SUBREG
743: && SUBREG_REG (SET_DEST (x)) == from)
744: fmt = "ie";
745:
746: for (i = 0; i < len; i++)
747: {
748: if (fmt[i] == 'E')
749: {
750: register int j;
751: for (j = XVECLEN (x, i) - 1; j >= 0; j--)
752: {
753: register rtx new;
754: if (XVECEXP (x, i, j) == from)
755: new = to, n_occurrences++;
756: else
757: new = subst (XVECEXP (x, i, j), from, to);
758: if (new != XVECEXP (x, i, j))
759: SUBST (XVECEXP (x, i, j), new);
760: }
761: }
762: else if (fmt[i] == 'e')
763: {
764: register rtx new;
765:
766: if (XEXP (x, i) == from)
767: {
768: new = to;
769: n_occurrences++;
770: if (i < 2)
771: was_replaced[i] = 1;
772: }
773: else
774: new = subst (XEXP (x, i), from, to);
775:
776: if (new != XEXP (x, i))
777: SUBST (XEXP (x, i), new);
778: }
779: }
780:
781: /* A little bit of algebraic simplification here. */
782: switch (code)
783: {
784: case SUBREG:
785: /* Changing mode twice with SUBREG => just change it once,
786: or not at all if changing back to starting mode. */
787: if (SUBREG_REG (x) == to
788: && GET_CODE (to) == SUBREG
789: && SUBREG_WORD (x) == 0
790: && SUBREG_WORD (to) == 0)
791: {
792: if (GET_MODE (x) == GET_MODE (SUBREG_REG (to)))
793: return SUBREG_REG (to);
794: SUBST (SUBREG_REG (x), SUBREG_REG (to));
795: }
1.1.1.4 ! root 796: /* (subreg (sign_extend X)) is X, if it has same mode as X. */
! 797: if (SUBREG_REG (x) == to
! 798: && (GET_CODE (to) == SIGN_EXTEND || GET_CODE (to) == ZERO_EXTEND)
! 799: && SUBREG_WORD (x) == 0
! 800: && GET_MODE (x) == GET_MODE (XEXP (to, 0)))
! 801: return XEXP (to, 0);
1.1.1.2 root 802: break;
1.1 root 803:
804: case NOT:
1.1.1.4 ! root 805: /* (not (minus X 1)) can become (neg X). */
! 806: if (was_replaced[0]
! 807: && ((GET_CODE (to) == PLUS && INTVAL (XEXP (to, 1)) == -1)
! 808: || (GET_CODE (to) == MINUS && XEXP (to, 1) == const1_rtx)))
! 809: return gen_rtx (NEG, GET_MODE (to), XEXP (to, 0));
! 810: /* Don't let substitution introduce double-negatives. */
! 811: if (was_replaced[0]
! 812: && GET_CODE (to) == code)
! 813: return XEXP (to, 0);
! 814: break;
! 815:
1.1 root 816: case NEG:
1.1.1.4 ! root 817: /* (neg (minus X Y)) can become (minus Y X). */
! 818: if (was_replaced[0] && GET_CODE (to) == MINUS)
! 819: return gen_rtx (MINUS, GET_MODE (to),
! 820: XEXP (to, 1), XEXP (to, 0));
1.1 root 821: /* Don't let substitution introduce double-negatives. */
1.1.1.2 root 822: if (was_replaced[0]
1.1 root 823: && GET_CODE (to) == code)
824: return XEXP (to, 0);
825: break;
826:
1.1.1.2 root 827: case FLOAT_TRUNCATE:
828: /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
829: if (was_replaced[0]
830: && GET_CODE (to) == FLOAT_EXTEND
831: && GET_MODE (XEXP (to, 0)) == GET_MODE (x))
832: return XEXP (to, 0);
833: break;
834:
1.1 root 835: case PLUS:
836: /* In (plus <foo> (ashift <bar> <n>))
837: change the shift to a multiply so we can recognize
838: scaled indexed addresses. */
1.1.1.2 root 839: if ((was_replaced[0]
840: || was_replaced[1])
1.1 root 841: && GET_CODE (to) == ASHIFT
1.1.1.2 root 842: && GET_CODE (XEXP (to, 1)) == CONST_INT
843: && INTVAL (XEXP (to, 1)) < HOST_BITS_PER_INT)
844: {
845: rtx temp;
846: if (!undobuf.storage)
847: undobuf.storage = (char *) oballoc (0);
848: temp = gen_rtx (MULT, GET_MODE (to),
849: XEXP (to, 0),
850: gen_rtx (CONST_INT, VOIDmode,
851: 1 << INTVAL (XEXP (to, 1))));
852: if (was_replaced[0])
853: SUBST (XEXP (x, 0), temp);
854: else
855: SUBST (XEXP (x, 1), temp);
856: }
857: /* (plus X (neg Y)) becomes (minus X Y). */
858: if (GET_CODE (XEXP (x, 1)) == NEG)
859: {
860: if (!undobuf.storage)
861: undobuf.storage = (char *) oballoc (0);
862: return gen_rtx (MINUS, GET_MODE (x),
863: XEXP (x, 0), XEXP (XEXP (x, 1), 0));
864: }
865: /* (plus (neg X) Y) becomes (minus Y X). */
866: if (GET_CODE (XEXP (x, 0)) == NEG)
1.1 root 867: {
868: if (!undobuf.storage)
869: undobuf.storage = (char *) oballoc (0);
1.1.1.2 root 870: return gen_rtx (MINUS, GET_MODE (x),
871: XEXP (x, 1), XEXP (XEXP (x, 0), 0));
872: }
873: /* (plus (plus x c1) c2) => (plus x c1+c2) */
874: if (GET_CODE (XEXP (x, 1)) == CONST_INT
875: && GET_CODE (XEXP (x, 0)) == PLUS
876: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
877: {
878: int sum = (INTVAL (XEXP (x, 1))
879: + INTVAL (XEXP (XEXP (x, 0), 1)));
880: if (sum == 0)
881: return XEXP (XEXP (x, 0), 0);
882: if (!undobuf.storage)
883: undobuf.storage = (char *) oballoc (0);
884: SUBST (XEXP (x, 1), gen_rtx (CONST_INT, VOIDmode, sum));
885: SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
886: break;
1.1 root 887: }
888: /* If we have something (putative index) being added to a sum,
889: associate it so that any constant term is outermost.
890: That's because that's the way indexed addresses are
891: now supposed to appear. */
1.1.1.2 root 892: if (((was_replaced[0] && GET_CODE (XEXP (x, 1)) == PLUS)
893: || (was_replaced[1] && GET_CODE (XEXP (x, 0)) == PLUS))
1.1 root 894: ||
1.1.1.2 root 895: ((was_replaced[0] || was_replaced[1])
896: && GET_CODE (to) == PLUS))
1.1 root 897: {
898: rtx offset = 0, base, index;
1.1.1.2 root 899: if (GET_CODE (to) != PLUS)
1.1 root 900: {
1.1.1.2 root 901: index = to;
902: base = was_replaced[0] ? XEXP (x, 1) : XEXP (x, 0);
1.1 root 903: }
904: else
905: {
1.1.1.2 root 906: index = was_replaced[0] ? XEXP (x, 1) : XEXP (x, 0);
907: base = to;
1.1 root 908: }
909: if (CONSTANT_ADDRESS_P (XEXP (base, 0)))
910: {
911: offset = XEXP (base, 0);
912: base = XEXP (base, 1);
913: }
914: else if (CONSTANT_ADDRESS_P (XEXP (base, 1)))
915: {
916: offset = XEXP (base, 1);
917: base = XEXP (base, 0);
918: }
919: if (offset != 0)
920: {
921: if (!undobuf.storage)
922: undobuf.storage = (char *) oballoc (0);
1.1.1.2 root 923: if (GET_CODE (offset) == CONST_INT)
924: return plus_constant (gen_rtx (PLUS, GET_MODE (index),
925: base, index),
926: INTVAL (offset));
927: if (GET_CODE (index) == CONST_INT)
928: return plus_constant (gen_rtx (PLUS, GET_MODE (offset),
929: base, offset),
930: INTVAL (index));
931: return gen_rtx (PLUS, GET_MODE (index),
1.1 root 932: gen_rtx (PLUS, GET_MODE (index),
1.1.1.2 root 933: base, index),
934: offset);
1.1 root 935: }
936: }
937: break;
938:
939: case MINUS:
940: /* Can simplify (minus:VOIDmode (zero/sign_extend FOO) CONST)
941: (which is a compare instruction, not a subtract instruction)
942: to (minus FOO CONST) if CONST fits in FOO's mode
943: and we are only testing equality.
944: In fact, this is valid for zero_extend if what follows is an
945: unsigned comparison, and for sign_extend with a signed comparison. */
946: if (GET_MODE (x) == VOIDmode
1.1.1.2 root 947: && was_replaced[0]
1.1 root 948: && (GET_CODE (to) == ZERO_EXTEND || GET_CODE (to) == SIGN_EXTEND)
949: && next_insn_tests_no_inequality (subst_insn)
950: && GET_CODE (XEXP (x, 1)) == CONST_INT
1.1.1.2 root 951: /* This is overly cautious by one bit, but saves worrying about
952: whether it is zero-extension or sign extension. */
1.1 root 953: && ((unsigned) INTVAL (XEXP (x, 1))
1.1.1.2 root 954: < (1 << (GET_MODE_BITSIZE (GET_MODE (XEXP (to, 0))) - 1))))
955: SUBST (XEXP (x, 0), XEXP (to, 0));
1.1 root 956: break;
957:
958: case EQ:
959: case NE:
960: /* If comparing a subreg against zero, discard the subreg. */
1.1.1.2 root 961: if (was_replaced[0]
1.1 root 962: && GET_CODE (to) == SUBREG
963: && SUBREG_WORD (to) == 0
964: && XEXP (x, 1) == const0_rtx)
1.1.1.2 root 965: SUBST (XEXP (x, 0), SUBREG_REG (to));
1.1 root 966:
967: /* If comparing a ZERO_EXTRACT against zero,
968: canonicalize to a SIGN_EXTRACT,
969: since the two are equivalent here. */
1.1.1.2 root 970: if (was_replaced[0]
971: && GET_CODE (to) == ZERO_EXTRACT
1.1 root 972: && XEXP (x, 1) == const0_rtx)
973: {
974: if (!undobuf.storage)
975: undobuf.storage = (char *) oballoc (0);
1.1.1.2 root 976: SUBST (XEXP (x, 0),
977: gen_rtx (SIGN_EXTRACT, GET_MODE (to),
978: XEXP (to, 0), XEXP (to, 1),
979: XEXP (to, 2)));
1.1 root 980: }
981: /* If we are putting (ASHIFT 1 x) into (EQ (AND ... y) 0),
982: arrange to return (EQ (SIGN_EXTRACT y 1 x) 0),
983: which is what jump-on-bit instructions are written with. */
984: else if (XEXP (x, 1) == const0_rtx
985: && GET_CODE (XEXP (x, 0)) == AND
1.1.1.2 root 986: && (XEXP (XEXP (x, 0), 0) == to
987: || XEXP (XEXP (x, 0), 1) == to)
988: && GET_CODE (to) == ASHIFT
989: && XEXP (to, 0) == const1_rtx)
1.1 root 990: {
991: register rtx y = XEXP (XEXP (x, 0),
1.1.1.2 root 992: XEXP (XEXP (x, 0), 0) == to);
1.1 root 993: if (!undobuf.storage)
994: undobuf.storage = (char *) oballoc (0);
1.1.1.2 root 995: SUBST (XEXP (x, 0),
996: gen_rtx (SIGN_EXTRACT, GET_MODE (to),
997: y,
998: const1_rtx, XEXP (to, 1)));
1.1 root 999: }
1000:
1001: break;
1002:
1003: case ZERO_EXTEND:
1.1.1.2 root 1004: if (was_replaced[0]
1.1 root 1005: && GET_CODE (to) == ZERO_EXTEND)
1.1.1.2 root 1006: SUBST (XEXP (x, 0), XEXP (to, 0));
1.1 root 1007: /* Zero-extending the result of an and with a constant can be done
1008: with a wider and. */
1.1.1.2 root 1009: if (was_replaced[0]
1.1 root 1010: && GET_CODE (to) == AND
1011: && GET_CODE (XEXP (to, 1)) == CONST_INT
1.1.1.2 root 1012: && FAKE_EXTEND_SAFE_P (GET_MODE (x), XEXP (to, 0))
1.1 root 1013: /* Avoid getting wrong result if the constant has high bits set
1014: that are irrelevant in the narrow mode where it is being used. */
1.1.1.2 root 1015: && 0 == (INTVAL (XEXP (to, 1))
1016: & ~ GET_MODE_MASK (GET_MODE (to))))
1.1 root 1017: {
1018: if (!undobuf.storage)
1019: undobuf.storage = (char *) oballoc (0);
1020: return gen_rtx (AND, GET_MODE (x),
1.1.1.2 root 1021: gen_lowpart_for_combine (GET_MODE (x), XEXP (to, 0)),
1.1 root 1022: XEXP (to, 1));
1.1.1.2 root 1023: }
1024: /* Change (zero_extend:M (subreg:N (zero_extract:M ...) 0))
1025: to (zero_extract:M ...) if the field extracted fits in mode N. */
1026: if (GET_CODE (XEXP (x, 0)) == SUBREG
1027: && GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTRACT
1028: && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1029: && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
1030: <= GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
1031: {
1032: return XEXP (XEXP (x, 0), 0);
1033: }
1.1 root 1034: break;
1035:
1036: case SIGN_EXTEND:
1.1.1.2 root 1037: if (was_replaced[0]
1.1 root 1038: && GET_CODE (to) == SIGN_EXTEND)
1.1.1.2 root 1039: SUBST (XEXP (x, 0), XEXP (to, 0));
1.1 root 1040: /* Sign-extending the result of an and with a constant can be done
1041: with a wider and, provided the high bit of the constant is 0. */
1.1.1.2 root 1042: if (was_replaced[0]
1.1 root 1043: && GET_CODE (to) == AND
1044: && GET_CODE (XEXP (to, 1)) == CONST_INT
1.1.1.2 root 1045: && FAKE_EXTEND_SAFE_P (GET_MODE (x), XEXP (to, 0))
1.1 root 1046: && ((INTVAL (XEXP (to, 1))
1.1.1.2 root 1047: & (-1 << (GET_MODE_BITSIZE (GET_MODE (to)) - 1)))
1.1 root 1048: == 0))
1049: {
1050: if (!undobuf.storage)
1051: undobuf.storage = (char *) oballoc (0);
1052: return gen_rtx (AND, GET_MODE (x),
1.1.1.2 root 1053: gen_lowpart_for_combine (GET_MODE (x), XEXP (to, 0)),
1.1 root 1054: XEXP (to, 1));
1055: }
1056: break;
1057:
1058: case SET:
1.1.1.2 root 1059: /* In (set (zero-extract <x> <n> <y>) (and <foo> <(2**n-1) | anything>))
1.1 root 1060: the `and' can be deleted. This can happen when storing a bit
1.1.1.2 root 1061: that came from a set-flag insn followed by masking to one bit. */
1.1 root 1062: if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
1.1.1.2 root 1063: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1064: && was_replaced[1]
1.1 root 1065: && GET_CODE (to) == AND
1.1.1.2 root 1066: && GET_CODE (XEXP (to, 1)) == CONST_INT
1067: && 0 == (((1 << INTVAL (XEXP (XEXP (x, 0), 1))) - 1)
1068: & ~ INTVAL (XEXP (to, 1))))
1.1 root 1069: {
1.1.1.2 root 1070: SUBST (XEXP (x, 1), XEXP (to, 0));
1071: }
1072: /* In (set (zero-extract <x> <n> <y>)
1073: (subreg (and <foo> <(2**n-1) | anything>)))
1074: the `and' can be deleted. */
1075: if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
1076: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1077: && GET_CODE (XEXP (x, 1)) == SUBREG
1078: && SUBREG_WORD (XEXP (x, 1)) == 0
1079: && GET_CODE (SUBREG_REG (XEXP (x, 1))) == AND
1080: && GET_CODE (XEXP (SUBREG_REG (XEXP (x, 1)), 1)) == CONST_INT
1081: && 0 == (((1 << INTVAL (XEXP (XEXP (x, 0), 1))) - 1)
1082: & ~ INTVAL (XEXP (SUBREG_REG (XEXP (x, 1)), 1))))
1083: {
1084: SUBST (SUBREG_REG (XEXP (x, 1)), XEXP (SUBREG_REG (XEXP (x, 1)), 0));
1085: }
1086: /* (set (zero_extract ...) (and/or/xor (zero_extract ...) const)),
1087: if both zero_extracts have the byte size and position,
1088: can be changed to avoid the byte extracts. */
1089: if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
1090: || GET_CODE (XEXP (x, 0)) == SIGN_EXTRACT)
1091: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1092: && (GET_CODE (XEXP (x, 1)) == AND
1093: || GET_CODE (XEXP (x, 1)) == IOR
1094: || GET_CODE (XEXP (x, 1)) == XOR)
1095: && (GET_CODE (XEXP (XEXP (x, 1), 0)) == ZERO_EXTRACT
1096: || GET_CODE (XEXP (XEXP (x, 1), 0)) == SIGN_EXTRACT)
1097: && rtx_equal_p (XEXP (XEXP (XEXP (x, 1), 0), 1),
1098: XEXP (XEXP (x, 0), 1))
1099: && rtx_equal_p (XEXP (XEXP (XEXP (x, 1), 0), 2),
1100: XEXP (XEXP (x, 0), 2))
1101: && GET_CODE (XEXP (XEXP (x, 1), 0)) == GET_CODE (XEXP (x, 0))
1102: && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
1103: {
1104: #ifdef BITS_BIG_ENDIAN
1105: int shiftcount
1106: = GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
1107: - INTVAL (XEXP (XEXP (x, 0), 1)) - INTVAL (XEXP (XEXP (x, 0), 2));
1108: #else
1109: int shiftcount
1110: = INTVAL (XEXP (XEXP (x, 0), 2));
1111: #endif
1112: if (!undobuf.storage)
1113: undobuf.storage = (char *) oballoc (0);
1114: return
1115: gen_rtx (SET, VOIDmode,
1116: XEXP (XEXP (x, 0), 0),
1117: gen_rtx (GET_CODE (XEXP (x, 1)),
1118: GET_MODE (XEXP (XEXP (x, 0), 0)),
1119: XEXP (XEXP (XEXP (x, 1), 0), 0),
1120: gen_rtx (CONST_INT, VOIDmode,
1121: (INTVAL (XEXP (XEXP (x, 1), 1))
1122: << shiftcount)
1123: + (GET_CODE (XEXP (x, 1)) == AND
1124: ? (1 << shiftcount) - 1
1125: : 0))));
1126: }
1.1 root 1127: break;
1128:
1129: case AND:
1130: if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1131: {
1.1.1.2 root 1132: rtx tem = simplify_and_const_int (x, to);
1.1 root 1133: if (tem)
1134: return tem;
1135: }
1136: break;
1137:
1138: case FLOAT:
1139: /* (float (sign_extend <X>)) = (float <X>). */
1.1.1.2 root 1140: if (was_replaced[0]
1.1 root 1141: && GET_CODE (to) == SIGN_EXTEND)
1.1.1.2 root 1142: SUBST (XEXP (x, 0), XEXP (to, 0));
1.1 root 1143: break;
1144:
1145: case ZERO_EXTRACT:
1.1.1.2 root 1146: /* (ZERO_EXTRACT (TRUNCATE x)...)
1147: can become (ZERO_EXTRACT x ...). */
1148: if (was_replaced[0]
1149: && GET_CODE (to) == TRUNCATE)
1150: {
1151: #ifdef BITS_BIG_ENDIAN
1152: if (GET_CODE (XEXP (x, 2)) == CONST_INT)
1153: {
1154: if (!undobuf.storage)
1155: undobuf.storage = (char *) oballoc (0);
1156: /* On a big-endian machine, must increment the bit-number
1157: since sign bit is farther away in the pre-truncated value. */
1158: return gen_rtx (ZERO_EXTRACT, GET_MODE (x),
1159: XEXP (to, 0),
1160: XEXP (x, 1),
1161: gen_rtx (CONST_INT, VOIDmode,
1162: (INTVAL (XEXP (x, 2))
1163: + GET_MODE_BITSIZE (GET_MODE (XEXP (to, 0)))
1164: - GET_MODE_BITSIZE (GET_MODE (to)))));
1165: }
1166: #else
1167: SUBST (XEXP (x, 0), XEXP (to, 0));
1168: #endif
1169: }
1.1 root 1170: /* Extracting a single bit from the result of a shift:
1171: see which bit it was before the shift and extract that directly. */
1.1.1.2 root 1172: if (was_replaced[0]
1.1 root 1173: && (GET_CODE (to) == ASHIFTRT || GET_CODE (to) == LSHIFTRT
1174: || GET_CODE (to) == ASHIFT || GET_CODE (to) == LSHIFT)
1175: && GET_CODE (XEXP (to, 1)) == CONST_INT
1176: && XEXP (x, 1) == const1_rtx
1177: && GET_CODE (XEXP (x, 2)) == CONST_INT)
1178: {
1179: int shift = INTVAL (XEXP (to, 1));
1180: int newpos;
1181: if (GET_CODE (to) == ASHIFT || GET_CODE (to) == LSHIFT)
1182: shift = - shift;
1183: #ifdef BITS_BIG_ENDIAN
1184: shift = - shift;
1185: #endif
1186: newpos = INTVAL (XEXP (x, 2)) + shift;
1187: if (newpos >= 0 &&
1.1.1.2 root 1188: newpos < GET_MODE_BITSIZE (GET_MODE (to)))
1.1 root 1189: {
1190: if (!undobuf.storage)
1191: undobuf.storage = (char *) oballoc (0);
1192: return gen_rtx (ZERO_EXTRACT, GET_MODE (x),
1193: XEXP (to, 0), const1_rtx,
1194: gen_rtx (CONST_INT, VOIDmode, newpos));
1195: }
1196: }
1197: break;
1198:
1199: case LSHIFTRT:
1200: case ASHIFTRT:
1201: case ROTATE:
1202: case ROTATERT:
1203: #ifdef SHIFT_COUNT_TRUNCATED
1204: /* (lshift <X> (sign_extend <Y>)) = (lshift <X> <Y>) (most machines).
1205: True for all kinds of shifts and also for zero_extend. */
1.1.1.2 root 1206: if (was_replaced[1]
1.1 root 1207: && (GET_CODE (to) == SIGN_EXTEND
1.1.1.2 root 1208: || GET_CODE (to) == ZERO_EXTEND)
1209: && FAKE_EXTEND_SAFE_P (GET_MODE (to), XEXP (to, 0)))
1.1 root 1210: {
1211: if (!undobuf.storage)
1212: undobuf.storage = (char *) oballoc (0);
1.1.1.2 root 1213: SUBST (XEXP (x, 1),
1214: /* This is a perverse SUBREG, wider than its base. */
1215: gen_lowpart_for_combine (GET_MODE (to), XEXP (to, 0)));
1.1 root 1216: }
1217: #endif
1218: /* Two shifts in a row of same kind
1219: in same direction with constant counts
1220: may be combined. */
1.1.1.2 root 1221: if (was_replaced[0]
1.1 root 1222: && GET_CODE (to) == GET_CODE (x)
1223: && GET_CODE (XEXP (x, 1)) == CONST_INT
1224: && GET_CODE (XEXP (to, 1)) == CONST_INT
1225: && INTVAL (XEXP (to, 1)) > 0
1226: && INTVAL (XEXP (x, 1)) > 0
1227: && (INTVAL (XEXP (x, 1)) + INTVAL (XEXP (to, 1))
1.1.1.2 root 1228: < GET_MODE_BITSIZE (GET_MODE (x))))
1.1 root 1229: {
1230: if (!undobuf.storage)
1231: undobuf.storage = (char *) oballoc (0);
1232: return gen_rtx (GET_CODE (x), GET_MODE (x),
1233: XEXP (to, 0),
1234: gen_rtx (CONST_INT, VOIDmode,
1235: INTVAL (XEXP (x, 1))
1236: + INTVAL (XEXP (to, 1))));
1237: }
1238: break;
1239:
1240: case LSHIFT:
1241: case ASHIFT:
1242: #ifdef SHIFT_COUNT_TRUNCATED
1243: /* (lshift <X> (sign_extend <Y>)) = (lshift <X> <Y>) (most machines).
1244: True for all kinds of shifts and also for zero_extend. */
1.1.1.2 root 1245: if (was_replaced[1]
1.1 root 1246: && (GET_CODE (to) == SIGN_EXTEND
1.1.1.4 ! root 1247: || GET_CODE (to) == ZERO_EXTEND)
! 1248: && GET_CODE (to) == REG)
1.1 root 1249: {
1250: if (!undobuf.storage)
1251: undobuf.storage = (char *) oballoc (0);
1.1.1.2 root 1252: SUBST (XEXP (x, 1), gen_rtx (SUBREG, GET_MODE (to), XEXP (to, 0), 0));
1.1 root 1253: }
1254: #endif
1255: /* (lshift (and (lshiftrt <foo> <X>) <Y>) <X>)
1256: happens copying between bit fields in similar structures.
1257: It can be replaced by one and instruction.
1258: It does not matter whether the shifts are logical or arithmetic. */
1259: if (GET_CODE (XEXP (x, 0)) == AND
1260: && GET_CODE (XEXP (x, 1)) == CONST_INT
1261: && INTVAL (XEXP (x, 1)) > 0
1262: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1.1.1.2 root 1263: && XEXP (XEXP (x, 0), 0) == to
1.1 root 1264: && (GET_CODE (to) == LSHIFTRT
1265: || GET_CODE (to) == ASHIFTRT)
1266: #if 0
1267: /* I now believe this restriction is unnecessary.
1268: The outer shift will discard those bits in any case, right? */
1269:
1270: /* If inner shift is arithmetic, either it shifts left or
1271: the bits it shifts the sign into are zeroed by the and. */
1272: && (INTVAL (XEXP (x, 1)) < 0
1273: || ((unsigned) INTVAL (XEXP (XEXP (x, 0), 1))
1274: < 1 << (GET_MODE_BITSIZE (GET_MODE (x))
1275: - INTVAL (XEXP (x, 0)))))
1276: #endif
1277: && GET_CODE (XEXP (to, 1)) == CONST_INT
1278: && INTVAL (XEXP (x, 1)) == INTVAL (XEXP (to, 1)))
1279: {
1280: if (!undobuf.storage)
1281: undobuf.storage = (char *) oballoc (0);
1282: /* The constant in the new `and' is <Y> << <X>
1283: but clear out all bits that don't belong in our mode. */
1284: return gen_rtx (AND, GET_MODE (x), XEXP (to, 0),
1285: gen_rtx (CONST_INT, VOIDmode,
1286: (GET_MODE_MASK (GET_MODE (x))
1287: & ((GET_MODE_MASK (GET_MODE (x))
1288: & INTVAL (XEXP (XEXP (x, 0), 1)))
1289: << INTVAL (XEXP (x, 1))))));
1290: }
1291: /* Two shifts in a row in same direction with constant counts
1292: may be combined. */
1.1.1.2 root 1293: if (was_replaced[0]
1.1 root 1294: && (GET_CODE (to) == ASHIFT || GET_CODE (to) == LSHIFT)
1295: && GET_CODE (XEXP (x, 1)) == CONST_INT
1296: && GET_CODE (XEXP (to, 1)) == CONST_INT
1297: && INTVAL (XEXP (to, 1)) > 0
1298: && INTVAL (XEXP (x, 1)) > 0
1299: && (INTVAL (XEXP (x, 1)) + INTVAL (XEXP (to, 1))
1.1.1.2 root 1300: < GET_MODE_BITSIZE (GET_MODE (x))))
1.1 root 1301: {
1302: if (!undobuf.storage)
1303: undobuf.storage = (char *) oballoc (0);
1304: return gen_rtx (GET_CODE (x), GET_MODE (x),
1305: XEXP (to, 0),
1306: gen_rtx (CONST_INT, VOIDmode,
1307: INTVAL (XEXP (x, 1))
1308: + INTVAL (XEXP (to, 1))));
1309: }
1310: /* (ashift (ashiftrt <foo> <X>) <X>)
1311: (or, on some machines, (ashift (ashift <foo> <-X>) <X>) instead)
1312: happens if you divide by 2**N and then multiply by 2**N.
1313: It can be replaced by one `and' instruction.
1314: It does not matter whether the shifts are logical or arithmetic. */
1315: if (GET_CODE (XEXP (x, 1)) == CONST_INT
1316: && INTVAL (XEXP (x, 1)) > 0
1.1.1.2 root 1317: && was_replaced[0]
1.1 root 1318: && (((GET_CODE (to) == LSHIFTRT || GET_CODE (to) == ASHIFTRT)
1319: && GET_CODE (XEXP (to, 1)) == CONST_INT
1320: && INTVAL (XEXP (x, 1)) == INTVAL (XEXP (to, 1)))
1321: ||
1322: ((GET_CODE (to) == LSHIFT || GET_CODE (to) == ASHIFT)
1323: && GET_CODE (XEXP (to, 1)) == CONST_INT
1324: && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (to, 1)))))
1325: {
1326: if (!undobuf.storage)
1327: undobuf.storage = (char *) oballoc (0);
1.1.1.2 root 1328: /* The constant in the new `and' is -1 << <X>
1.1 root 1329: but clear out all bits that don't belong in our mode. */
1330: return gen_rtx (AND, GET_MODE (x), XEXP (to, 0),
1331: gen_rtx (CONST_INT, VOIDmode,
1332: (GET_MODE_MASK (GET_MODE (x))
1333: & (GET_MODE_MASK (GET_MODE (x))
1334: << INTVAL (XEXP (x, 1))))));
1335: }
1336:
1337: }
1338:
1339: return x;
1340: }
1341:
1342: /* This is the AND case of the function subst. */
1343:
1344: static rtx
1.1.1.2 root 1345: simplify_and_const_int (x, to)
1346: rtx x, to;
1.1 root 1347: {
1348: register rtx varop = XEXP (x, 0);
1349: register int constop = INTVAL (XEXP (x, 1));
1350:
1351: /* (and (subreg (and <foo> <constant>) 0) <constant>)
1352: results from an andsi followed by an andqi,
1353: which happens frequently when storing bit-fields
1354: on something whose result comes from an andsi. */
1355: if (GET_CODE (varop) == SUBREG
1.1.1.2 root 1356: && XEXP (varop, 0) == to
1.1 root 1357: && subreg_lowpart_p (varop)
1358: && GET_CODE (to) == AND
1359: && GET_CODE (XEXP (to, 1)) == CONST_INT
1360: /* Verify that the result of the outer `and'
1361: is not affected by any bits not defined in the inner `and'.
1362: True if the outer mode is narrower, or if the outer constant
1363: masks to zero all the bits that the inner mode doesn't have. */
1.1.1.2 root 1364: && (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (GET_MODE (to))
1365: || (constop & ~ GET_MODE_MASK (GET_MODE (to))) == 0))
1.1 root 1366: {
1367: if (!undobuf.storage)
1368: undobuf.storage = (char *) oballoc (0);
1369: return gen_rtx (AND, GET_MODE (x),
1.1.1.2 root 1370: gen_lowpart_for_combine (GET_MODE (x), XEXP (to, 0)),
1.1 root 1371: gen_rtx (CONST_INT, VOIDmode,
1372: constop
1373: /* Remember that the bits outside that mode
1374: are not being changed, so the effect
1375: is as if they were all 1. */
1376: & INTVAL (XEXP (to, 1))));
1377: }
1.1.1.2 root 1378: /* (and:SI (zero_extract:SI ...) <constant>)
1379: results from an andsi following a byte-fetch on risc machines.
1380: When the constant includes all bits extracted, eliminate the `and'. */
1381: if (GET_CODE (varop) == ZERO_EXTRACT
1382: && GET_CODE (XEXP (varop, 1)) == CONST_INT
1383: /* The `and' must not clear any bits that the extract can give. */
1384: && (~ constop & ((1 << INTVAL (XEXP (varop, 1))) - 1)) == 0)
1385: return varop;
1.1 root 1386: /* (and (zero_extend <foo>) <constant>)
1387: often results from storing in a bit-field something
1388: that was calculated as a short. Replace with a single `and'
1389: in whose constant all bits not in <foo>'s mode are zero. */
1.1.1.2 root 1390: if (varop == to
1391: && GET_CODE (to) == ZERO_EXTEND
1392: && FAKE_EXTEND_SAFE_P (GET_MODE (x), XEXP (to, 0)))
1.1 root 1393: {
1394: if (!undobuf.storage)
1395: undobuf.storage = (char *) oballoc (0);
1396: return gen_rtx (AND, GET_MODE (x),
1.1.1.2 root 1397: /* This is a perverse SUBREG, wider than its base. */
1398: gen_lowpart_for_combine (GET_MODE (x), XEXP (to, 0)),
1.1 root 1399: gen_rtx (CONST_INT, VOIDmode,
1.1.1.2 root 1400: constop & GET_MODE_MASK (GET_MODE (XEXP (to, 0)))));
1.1 root 1401: }
1402: /* (and (sign_extend <foo>) <constant>)
1403: can be replaced with (and (subreg <foo>) <constant>)
1404: if <constant> is narrower than <foo>'s mode,
1405: or with (zero_extend <foo>) if <constant> is a mask for that mode. */
1.1.1.2 root 1406: if (varop == to
1.1 root 1407: && GET_CODE (to) == SIGN_EXTEND
1.1.1.2 root 1408: && ((unsigned) constop <= GET_MODE_MASK (GET_MODE (XEXP (to, 0))))
1409: && FAKE_EXTEND_SAFE_P (GET_MODE (x), XEXP (to, 0)))
1.1 root 1410: {
1411: if (!undobuf.storage)
1412: undobuf.storage = (char *) oballoc (0);
1.1.1.2 root 1413: if (constop == GET_MODE_MASK (GET_MODE (XEXP (to, 0))))
1.1 root 1414: return gen_rtx (ZERO_EXTEND, GET_MODE (x), XEXP (to, 0));
1415: return gen_rtx (AND, GET_MODE (x),
1.1.1.2 root 1416: /* This is a perverse SUBREG, wider than its base. */
1417: gen_lowpart_for_combine (GET_MODE (x), XEXP (to, 0)),
1.1 root 1418: XEXP (x, 1));
1419: }
1420: /* (and (and <foo> <constant>) <constant>)
1421: comes from two and instructions in a row. */
1.1.1.2 root 1422: if (varop == to
1.1 root 1423: && GET_CODE (to) == AND
1424: && GET_CODE (XEXP (to, 1)) == CONST_INT)
1425: {
1426: if (!undobuf.storage)
1427: undobuf.storage = (char *) oballoc (0);
1428: return gen_rtx (AND, GET_MODE (x),
1429: XEXP (to, 0),
1430: gen_rtx (CONST_INT, VOIDmode,
1431: constop
1432: & INTVAL (XEXP (to, 1))));
1433: }
1434: /* (and (ashiftrt (ashift FOO N) N) CONST)
1435: may be simplified to (and FOO CONST) if CONST masks off the bits
1436: changed by the two shifts. */
1437: if (GET_CODE (varop) == ASHIFTRT
1438: && GET_CODE (XEXP (varop, 1)) == CONST_INT
1.1.1.2 root 1439: && XEXP (varop, 0) == to
1.1 root 1440: && GET_CODE (to) == ASHIFT
1441: && GET_CODE (XEXP (to, 1)) == CONST_INT
1442: && INTVAL (XEXP (varop, 1)) == INTVAL (XEXP (to, 1))
1443: && ((unsigned) constop >> INTVAL (XEXP (varop, 1))) == 0)
1444: {
1445: if (!undobuf.storage)
1446: undobuf.storage = (char *) oballoc (0);
1447: /* If CONST is a mask for the low byte,
1448: change this into a zero-extend instruction
1449: from just the low byte of FOO. */
1.1.1.2 root 1450: if (constop == GET_MODE_MASK (QImode))
1.1 root 1451: {
1452: rtx temp = gen_lowpart_for_combine (QImode, XEXP (to, 0));
1.1.1.2 root 1453: if (GET_CODE (temp) != CLOBBER)
1.1 root 1454: return gen_rtx (ZERO_EXTEND, GET_MODE (x), temp);
1455: }
1456: return gen_rtx (AND, GET_MODE (x),
1457: XEXP (to, 0), XEXP (x, 1));
1458: }
1.1.1.2 root 1459: /* (and x const) may be converted to (zero_extend (subreg x 0)). */
1.1.1.4 ! root 1460: if (constop == GET_MODE_MASK (QImode)
! 1461: && GET_CODE (varop) == REG)
1.1.1.2 root 1462: {
1463: if (!undobuf.storage)
1464: undobuf.storage = (char *) oballoc (0);
1465: return gen_rtx (ZERO_EXTEND, GET_MODE (x),
1466: gen_rtx (SUBREG, QImode, varop, 0));
1467: }
1.1.1.4 ! root 1468: if (constop == GET_MODE_MASK (HImode)
! 1469: && GET_CODE (varop) == REG)
1.1.1.2 root 1470: {
1471: if (!undobuf.storage)
1472: undobuf.storage = (char *) oballoc (0);
1473: return gen_rtx (ZERO_EXTEND, GET_MODE (x),
1474: gen_rtx (SUBREG, HImode, varop, 0));
1475: }
1.1 root 1476: /* No simplification applies. */
1477: return 0;
1478: }
1479:
1480: /* Like gen_lowpart but for use by combine. In combine it is not possible
1481: to create any new pseudoregs. However, it is safe to create
1482: invalid memory addresses, because combine will try to recognize
1483: them and all they will do is make the combine attempt fail.
1484:
1.1.1.2 root 1485: If for some reason this cannot do its job, an rtx
1486: (clobber (const_int 0)) is returned.
1487: An insn containing that will not be recognized. */
1488:
1489: #undef gen_lowpart
1.1 root 1490:
1491: static rtx
1492: gen_lowpart_for_combine (mode, x)
1493: enum machine_mode mode;
1494: register rtx x;
1495: {
1496: if (GET_CODE (x) == SUBREG || GET_CODE (x) == REG)
1497: return gen_lowpart (mode, x);
1.1.1.2 root 1498: if (GET_MODE (x) == mode || x->volatil)
1499: return gen_rtx (CLOBBER, VOIDmode, const0_rtx);
1.1 root 1500: if (GET_CODE (x) == MEM)
1501: {
1502: register int offset = 0;
1503: #ifdef WORDS_BIG_ENDIAN
1504: offset = (max (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
1505: - max (GET_MODE_SIZE (mode), UNITS_PER_WORD));
1506: #endif
1507: #ifdef BYTES_BIG_ENDIAN
1.1.1.2 root 1508: /* Adjust the address so that the address-after-the-data
1509: is unchanged. */
1510: offset -= (min (UNITS_PER_WORD, GET_MODE_SIZE (mode))
1511: - min (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
1.1 root 1512: #endif
1513: return gen_rtx (MEM, mode, plus_constant (XEXP (x, 0),
1514: offset));
1515: }
1516: else
1.1.1.2 root 1517: return gen_rtx (CLOBBER, VOIDmode, const0_rtx);
1.1 root 1518: }
1519:
1520: /* After substitution, if the resulting pattern looks like
1.1.1.2 root 1521: (set (cc0) (and ...)) or (set (cc0) (lshiftrt ...)),
1522: this function is called to simplify the
1.1 root 1523: pattern into a bit-field operation if possible. */
1524:
1525: static void
1526: simplify_set_cc0_and (insn)
1527: rtx insn;
1528: {
1529: register rtx value = XEXP (PATTERN (insn), 1);
1530: register rtx op0 = XEXP (value, 0);
1531: register rtx op1 = XEXP (value, 1);
1532: int offset = 0;
1533: rtx var = 0;
1534: rtx bitnum = 0;
1535: int temp;
1536: int unit;
1.1.1.2 root 1537: rtx newpat;
1538:
1539: if (GET_CODE (value) == AND)
1540: {
1541: op0 = XEXP (value, 0);
1542: op1 = XEXP (value, 1);
1543: }
1544: else if (GET_CODE (value) == LSHIFTRT)
1545: {
1546: /* If there is no AND, but there is a shift that discards
1547: all but the sign bit, we can pretend that the shift result
1548: is ANDed with 1. Otherwise we cannot handle just a shift. */
1549: if (GET_CODE (XEXP (value, 1)) == CONST_INT
1550: && (INTVAL (XEXP (value, 1))
1551: == GET_MODE_BITSIZE (GET_MODE (value)) - 1))
1552: {
1553: op0 = value;
1554: op1 = const1_rtx;
1555: }
1556: else
1557: return;
1558: }
1559: else
1560: abort ();
1.1 root 1561:
1562: /* Look for a constant power of 2 or a shifted 1
1563: on either side of the AND. Set VAR to the other side.
1564: Set BITNUM to the shift count of the 1 (as an rtx).
1565: Or, if bit number is constant, set OFFSET to the bit number. */
1566:
1567: switch (GET_CODE (op0))
1568: {
1569: case CONST_INT:
1570: temp = exact_log2 (INTVAL (op0));
1571: if (temp < 0)
1572: return;
1573: offset = temp;
1574: var = op1;
1575: break;
1576:
1577: case ASHIFT:
1578: case LSHIFT:
1579: if (XEXP (op0, 0) == const1_rtx)
1580: {
1581: bitnum = XEXP (op0, 1);
1582: var = op1;
1583: }
1584: }
1585: if (var == 0)
1586: switch (GET_CODE (op1))
1587: {
1588: case CONST_INT:
1589: temp = exact_log2 (INTVAL (op1));
1590: if (temp < 0)
1591: return;
1592: offset = temp;
1593: var = op0;
1594: break;
1595:
1596: case ASHIFT:
1597: case LSHIFT:
1598: if (XEXP (op1, 0) == const1_rtx)
1599: {
1600: bitnum = XEXP (op1, 1);
1601: var = op0;
1602: }
1603: }
1604:
1605: /* If VAR is 0, we didn't find something recognizable. */
1606: if (var == 0)
1607: return;
1608:
1609: if (!undobuf.storage)
1610: undobuf.storage = (char *) oballoc (0);
1611:
1612: /* If the bit position is currently exactly 0,
1613: extract a right-shift from the variable portion. */
1614: if (offset == 0
1615: && (GET_CODE (var) == ASHIFTRT || GET_CODE (var) == LSHIFTRT))
1616: {
1617: bitnum = XEXP (var, 1);
1618: var = XEXP (var, 0);
1619: }
1620:
1.1.1.2 root 1621: if (GET_CODE (var) == SUBREG && SUBREG_WORD (var) == 0)
1622: var = SUBREG_REG (var);
1623:
1624: /* Note that BITNUM and OFFSET are always little-endian thru here
1625: even on a big-endian machine. */
1626:
1.1 root 1627: #ifdef BITS_BIG_ENDIAN
1.1.1.2 root 1628: unit = GET_MODE_BITSIZE (GET_MODE (var)) - 1;
1.1 root 1629:
1630: if (bitnum != 0)
1631: bitnum = gen_rtx (MINUS, SImode,
1632: gen_rtx (CONST_INT, VOIDmode, unit), bitnum);
1633: else
1634: offset = unit - offset;
1635: #endif
1636:
1637: if (bitnum == 0)
1638: bitnum = gen_rtx (CONST_INT, VOIDmode, offset);
1639:
1.1.1.2 root 1640: newpat = gen_rtx (SET, VOIDmode, cc0_rtx,
1641: gen_rtx (ZERO_EXTRACT, VOIDmode, var, const1_rtx, bitnum));
1642: if (recog (newpat, insn) >= 0)
1.1 root 1643: {
1.1.1.2 root 1644: if (undobuf.num_undo < MAX_UNDO)
1645: {
1646: undobuf.undo[undobuf.num_undo].where = &XEXP (PATTERN (insn), 1);
1647: undobuf.undo[undobuf.num_undo].old_contents = value;
1648: XEXP (PATTERN (insn), 1) = XEXP (newpat, 1);
1649: }
1650: undobuf.num_undo++;
1.1 root 1651: }
1652: }
1653:
1654: /* Update the records of when each REG was most recently set or killed
1655: for the things done by INSN. This is the last thing done in processing
1656: INSN in the combiner loop.
1657:
1658: We update reg_last_set, reg_last_death, and also the similar information
1659: mem_last_set (which insn most recently modified memory)
1660: and last_call_cuid (which insn was the most recent subroutine call). */
1661:
1662: static void
1663: record_dead_and_set_regs (insn)
1664: rtx insn;
1665: {
1666: register rtx link;
1667: for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1668: {
1.1.1.2 root 1669: if (REG_NOTE_KIND (link) == REG_DEAD)
1.1 root 1670: reg_last_death[REGNO (XEXP (link, 0))] = insn;
1.1.1.2 root 1671: else if (REG_NOTE_KIND (link) == REG_INC)
1.1 root 1672: reg_last_set[REGNO (XEXP (link, 0))] = insn;
1673: }
1674:
1675: if (GET_CODE (insn) == CALL_INSN)
1676: last_call_cuid = mem_last_set = INSN_CUID (insn);
1677:
1678: if (GET_CODE (PATTERN (insn)) == PARALLEL)
1679: {
1680: register int i;
1681: for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
1682: {
1683: register rtx elt = XVECEXP (PATTERN (insn), 0, i);
1684: register enum rtx_code code = GET_CODE (elt);
1685: if (code == SET || code == CLOBBER)
1686: {
1687: if (GET_CODE (XEXP (elt, 0)) == REG)
1688: reg_last_set[REGNO (XEXP (elt, 0))] = insn;
1.1.1.2 root 1689: if (GET_CODE (XEXP (elt, 0)) == SUBREG
1690: && GET_CODE (SUBREG_REG (XEXP (elt, 0))) == REG)
1691: reg_last_set[REGNO (SUBREG_REG (XEXP (elt, 0)))] = insn;
1.1 root 1692: else if (GET_CODE (XEXP (elt, 0)) == MEM)
1693: mem_last_set = INSN_CUID (insn);
1694: }
1695: }
1696: }
1697: else if (GET_CODE (PATTERN (insn)) == SET
1698: || GET_CODE (PATTERN (insn)) == CLOBBER)
1699: {
1700: register rtx x = XEXP (PATTERN (insn), 0);
1701: if (GET_CODE (x) == REG)
1702: reg_last_set[REGNO (x)] = insn;
1.1.1.2 root 1703: if (GET_CODE (x) == SUBREG
1704: && GET_CODE (SUBREG_REG (x)) == REG)
1705: reg_last_set[REGNO (SUBREG_REG (x))] = insn;
1.1 root 1706: else if (GET_CODE (x) == MEM)
1707: mem_last_set = INSN_CUID (insn);
1708: }
1709: }
1710:
1711: /* Return nonzero if expression X refers to a REG or to memory
1712: that is set in an instruction more recent than FROM_CUID. */
1713:
1714: static int
1715: use_crosses_set_p (x, from_cuid)
1716: register rtx x;
1717: int from_cuid;
1718: {
1719: register char *fmt;
1720: register int i;
1721: register enum rtx_code code = GET_CODE (x);
1722:
1723: if (code == REG)
1724: {
1725: register int regno = REGNO (x);
1726: return (reg_last_set[regno]
1727: && INSN_CUID (reg_last_set[regno]) > from_cuid);
1728: }
1729:
1730: if (code == MEM && mem_last_set > from_cuid)
1731: return 1;
1732:
1733: fmt = GET_RTX_FORMAT (code);
1734:
1735: for (i = GET_RTX_LENGTH (code); i >= 0; i--)
1736: {
1737: if (fmt[i] == 'E')
1738: {
1739: register int j;
1740: for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1741: if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
1742: return 1;
1743: }
1744: else if (fmt[i] == 'e'
1745: && use_crosses_set_p (XEXP (x, i), from_cuid))
1746: return 1;
1747: }
1748: return 0;
1749: }
1750:
1751: /* Return nonzero if reg REGNO is marked as dying in INSN. */
1752:
1753: int
1754: regno_dead_p (regno, insn)
1755: int regno;
1756: rtx insn;
1757: {
1758: register rtx link;
1759:
1760: for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1.1.1.2 root 1761: if ((REG_NOTE_KIND (link) == REG_DEAD
1762: || REG_NOTE_KIND (link) == REG_INC)
1763: && REGNO (XEXP (link, 0)) == regno)
1.1 root 1764: return 1;
1765:
1766: return 0;
1767: }
1768:
1769: /* Remove register number REGNO from the dead registers list of INSN. */
1770:
1.1.1.4 ! root 1771: void
1.1 root 1772: remove_death (regno, insn)
1773: int regno;
1774: rtx insn;
1775: {
1776: register rtx link, next;
1777: while ((link = REG_NOTES (insn))
1.1.1.2 root 1778: && REG_NOTE_KIND (link) == REG_DEAD
1779: && REGNO (XEXP (link, 0)) == regno)
1.1 root 1780: REG_NOTES (insn) = XEXP (link, 1);
1781:
1782: if (link)
1783: while (next = XEXP (link, 1))
1784: {
1.1.1.2 root 1785: if (REG_NOTE_KIND (next) == REG_DEAD
1786: && REGNO (XEXP (next, 0)) == regno)
1.1 root 1787: XEXP (link, 1) = XEXP (next, 1);
1788: else
1789: link = next;
1790: }
1791: }
1792:
1793: /* Return nonzero if J is the first insn following I,
1794: not counting labels, line numbers, etc.
1795: We assume that J follows I. */
1796:
1797: static int
1798: adjacent_insns_p (i, j)
1799: rtx i, j;
1800: {
1801: register rtx insn;
1802: for (insn = NEXT_INSN (i); insn != j; insn = NEXT_INSN (insn))
1803: if (GET_CODE (insn) == INSN
1804: || GET_CODE (insn) == CALL_INSN
1805: || GET_CODE (insn) == JUMP_INSN)
1806: return 0;
1807: return 1;
1808: }
1809:
1.1.1.2 root 1810: /* Concatenate the list of logical links of OINSN
1.1 root 1811: into INSN's list of logical links.
1.1.1.2 root 1812: Modifies OINSN destructively.
1813:
1814: If ALL_LINKS is nonzero, move all the links that OINSN has.
1815: Otherwise, move only those that point to insns that set regs
1816: that die in the insn OINSN.
1817: Other links are clobbered so that they are no longer effective. */
1.1 root 1818:
1819: static void
1.1.1.2 root 1820: add_links (insn, oinsn, all_links)
1821: rtx insn, oinsn;
1822: int all_links;
1.1 root 1823: {
1.1.1.2 root 1824: register rtx links = LOG_LINKS (oinsn);
1825: if (! all_links)
1826: {
1827: rtx tail;
1828: for (tail = links; tail; tail = XEXP (tail, 1))
1829: {
1830: rtx target = XEXP (tail, 0);
1831: if (GET_CODE (target) != INSN
1832: || GET_CODE (PATTERN (target)) != SET
1833: || GET_CODE (SET_DEST (PATTERN (target))) != REG
1834: || ! dead_or_set_p (oinsn, SET_DEST (PATTERN (target))))
1835: /* OINSN is going to become a NOTE
1836: so a link pointing there will have no effect. */
1837: XEXP (tail, 0) = oinsn;
1838: }
1839: }
1.1 root 1840: if (LOG_LINKS (insn) == 0)
1841: LOG_LINKS (insn) = links;
1842: else
1843: {
1844: register rtx next, prev = LOG_LINKS (insn);
1845: while (next = XEXP (prev, 1))
1846: prev = next;
1847: XEXP (prev, 1) = links;
1848: }
1849: }
1850:
1851: /* Concatenate the any elements of the list of reg-notes INCS
1852: which are of type REG_INC
1853: into INSN's list of reg-notes. */
1854:
1855: static void
1856: add_incs (insn, incs)
1857: rtx insn, incs;
1858: {
1859: register rtx tail;
1860:
1861: for (tail = incs; tail; tail = XEXP (tail, 1))
1.1.1.2 root 1862: if (REG_NOTE_KIND (tail) == REG_INC)
1.1 root 1863: REG_NOTES (insn)
1864: = gen_rtx (EXPR_LIST, REG_INC, XEXP (tail, 0), REG_NOTES (insn));
1865: }
1866:
1867: /* For each register (hardware or pseudo) used within expression X,
1868: if its death is in an instruction with cuid
1869: between FROM_CUID (inclusive) and TO_INSN (exclusive),
1870: mark it as dead in TO_INSN instead.
1871:
1872: This is done when X is being merged by combination into TO_INSN. */
1873:
1874: static void
1875: move_deaths (x, from_cuid, to_insn)
1876: rtx x;
1877: int from_cuid;
1878: rtx to_insn;
1879: {
1880: register char *fmt;
1881: register int len, i;
1882: register enum rtx_code code = GET_CODE (x);
1883:
1884: if (code == REG)
1885: {
1886: register rtx where_dead = reg_last_death[REGNO (x)];
1887:
1888: if (where_dead && INSN_CUID (where_dead) >= from_cuid
1889: && INSN_CUID (where_dead) < INSN_CUID (to_insn))
1890: {
1891: remove_death (REGNO (x), reg_last_death[REGNO (x)]);
1892: if (! dead_or_set_p (to_insn, x))
1893: REG_NOTES (to_insn)
1894: = gen_rtx (EXPR_LIST, REG_DEAD, x, REG_NOTES (to_insn));
1895: }
1896: return;
1897: }
1898:
1899: len = GET_RTX_LENGTH (code);
1900: fmt = GET_RTX_FORMAT (code);
1901:
1902: for (i = 0; i < len; i++)
1903: {
1904: if (fmt[i] == 'E')
1905: {
1906: register int j;
1907: for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1908: move_deaths (XVECEXP (x, i, j), from_cuid, to_insn);
1909: }
1910: else if (fmt[i] == 'e')
1911: move_deaths (XEXP (x, i), from_cuid, to_insn);
1912: }
1913: }
1914:
1.1.1.2 root 1915: void
1.1 root 1916: dump_combine_stats (file)
1917: char *file;
1918: {
1919: fprintf
1920: (file,
1921: ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n"
1922: , combine_attempts, combine_merges, combine_extras, combine_successes);
1923: }
1924:
1.1.1.2 root 1925: void
1.1 root 1926: dump_combine_total_stats (file)
1927: char *file;
1928: {
1929: fprintf
1930: (file,
1931: "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
1932: total_attempts, total_merges, total_extras, total_successes);
1933: }
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