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1.1 root 1: /* Optimize by combining instructions for GNU compiler.
2: Copyright (C) 1987, 1988, 1992 Free Software Foundation, Inc.
3:
4: This file is part of GNU CC.
5:
6: GNU CC is free software; you can redistribute it and/or modify
7: it under the terms of the GNU General Public License as published by
8: the Free Software Foundation; either version 2, or (at your option)
9: any later version.
10:
11: GNU CC is distributed in the hope that it will be useful,
12: but WITHOUT ANY WARRANTY; without even the implied warranty of
13: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14: GNU General Public License for more details.
15:
16: You should have received a copy of the GNU General Public License
17: along with GNU CC; see the file COPYING. If not, write to
18: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
19:
20:
21: /* This module is essentially the "combiner" phase of the U. of Arizona
22: Portable Optimizer, but redone to work on our list-structured
23: representation for RTL instead of their string representation.
24:
25: The LOG_LINKS of each insn identify the most recent assignment
26: to each REG used in the insn. It is a list of previous insns,
27: each of which contains a SET for a REG that is used in this insn
28: and not used or set in between. LOG_LINKs never cross basic blocks.
29: They were set up by the preceding pass (lifetime analysis).
30:
31: We try to combine each pair of insns joined by a logical link.
32: We also try to combine triples of insns A, B and C when
33: C has a link back to B and B has a link back to A.
34:
35: LOG_LINKS does not have links for use of the CC0. They don't
36: need to, because the insn that sets the CC0 is always immediately
37: before the insn that tests it. So we always regard a branch
38: insn as having a logical link to the preceding insn. The same is true
39: for an insn explicitly using CC0.
40:
41: We check (with use_crosses_set_p) to avoid combining in such a way
42: as to move a computation to a place where its value would be different.
43:
44: Combination is done by mathematically substituting the previous
45: insn(s) values for the regs they set into the expressions in
46: the later insns that refer to these regs. If the result is a valid insn
47: for our target machine, according to the machine description,
48: we install it, delete the earlier insns, and update the data flow
49: information (LOG_LINKS and REG_NOTES) for what we did.
50:
51: There are a few exceptions where the dataflow information created by
52: flow.c aren't completely updated:
53:
54: - reg_live_length is not updated
55: - reg_n_refs is not adjusted in the rare case when a register is
56: no longer required in a computation
57: - there are extremely rare cases (see distribute_regnotes) when a
58: REG_DEAD note is lost
59: - a LOG_LINKS entry that refers to an insn with multiple SETs may be
60: removed because there is no way to know which register it was
61: linking
62:
63: To simplify substitution, we combine only when the earlier insn(s)
64: consist of only a single assignment. To simplify updating afterward,
65: we never combine when a subroutine call appears in the middle.
66:
67: Since we do not represent assignments to CC0 explicitly except when that
68: is all an insn does, there is no LOG_LINKS entry in an insn that uses
69: the condition code for the insn that set the condition code.
70: Fortunately, these two insns must be consecutive.
71: Therefore, every JUMP_INSN is taken to have an implicit logical link
72: to the preceding insn. This is not quite right, since non-jumps can
73: also use the condition code; but in practice such insns would not
74: combine anyway. */
75:
76: #include "config.h"
77: #include "gvarargs.h"
78: #include "rtl.h"
79: #include "flags.h"
80: #include "regs.h"
81: #include "expr.h"
82: #include "basic-block.h"
83: #include "insn-config.h"
84: #include "insn-flags.h"
85: #include "insn-codes.h"
86: #include "insn-attr.h"
87: #include "recog.h"
88: #include "real.h"
1.1.1.4 ! root 89: #include <stdio.h>
1.1 root 90:
91: /* It is not safe to use ordinary gen_lowpart in combine.
92: Use gen_lowpart_for_combine instead. See comments there. */
93: #define gen_lowpart dont_use_gen_lowpart_you_dummy
94:
95: /* Number of attempts to combine instructions in this function. */
96:
97: static int combine_attempts;
98:
99: /* Number of attempts that got as far as substitution in this function. */
100:
101: static int combine_merges;
102:
103: /* Number of instructions combined with added SETs in this function. */
104:
105: static int combine_extras;
106:
107: /* Number of instructions combined in this function. */
108:
109: static int combine_successes;
110:
111: /* Totals over entire compilation. */
112:
113: static int total_attempts, total_merges, total_extras, total_successes;
114:
115: /* Vector mapping INSN_UIDs to cuids.
1.1.1.2 root 116: The cuids are like uids but increase monotonically always.
1.1 root 117: Combine always uses cuids so that it can compare them.
118: But actually renumbering the uids, which we used to do,
119: proves to be a bad idea because it makes it hard to compare
120: the dumps produced by earlier passes with those from later passes. */
121:
122: static int *uid_cuid;
123:
124: /* Get the cuid of an insn. */
125:
126: #define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)])
127:
128: /* Maximum register number, which is the size of the tables below. */
129:
130: static int combine_max_regno;
131:
132: /* Record last point of death of (hard or pseudo) register n. */
133:
134: static rtx *reg_last_death;
135:
136: /* Record last point of modification of (hard or pseudo) register n. */
137:
138: static rtx *reg_last_set;
139:
140: /* Record the cuid of the last insn that invalidated memory
141: (anything that writes memory, and subroutine calls, but not pushes). */
142:
143: static int mem_last_set;
144:
145: /* Record the cuid of the last CALL_INSN
146: so we can tell whether a potential combination crosses any calls. */
147:
148: static int last_call_cuid;
149:
150: /* When `subst' is called, this is the insn that is being modified
151: (by combining in a previous insn). The PATTERN of this insn
152: is still the old pattern partially modified and it should not be
153: looked at, but this may be used to examine the successors of the insn
154: to judge whether a simplification is valid. */
155:
156: static rtx subst_insn;
157:
158: /* This is the lowest CUID that `subst' is currently dealing with.
159: get_last_value will not return a value if the register was set at or
160: after this CUID. If not for this mechanism, we could get confused if
161: I2 or I1 in try_combine were an insn that used the old value of a register
162: to obtain a new value. In that case, we might erroneously get the
163: new value of the register when we wanted the old one. */
164:
165: static int subst_low_cuid;
166:
167: /* This is the value of undobuf.num_undo when we started processing this
168: substitution. This will prevent gen_rtx_combine from re-used a piece
169: from the previous expression. Doing so can produce circular rtl
170: structures. */
171:
172: static int previous_num_undos;
173:
174: /* The next group of arrays allows the recording of the last value assigned
175: to (hard or pseudo) register n. We use this information to see if a
1.1.1.2 root 176: operation being processed is redundant given a prior operation performed
1.1 root 177: on the register. For example, an `and' with a constant is redundant if
178: all the zero bits are already known to be turned off.
179:
180: We use an approach similar to that used by cse, but change it in the
181: following ways:
182:
183: (1) We do not want to reinitialize at each label.
184: (2) It is useful, but not critical, to know the actual value assigned
185: to a register. Often just its form is helpful.
186:
187: Therefore, we maintain the following arrays:
188:
189: reg_last_set_value the last value assigned
190: reg_last_set_label records the value of label_tick when the
191: register was assigned
192: reg_last_set_table_tick records the value of label_tick when a
193: value using the register is assigned
194: reg_last_set_invalid set to non-zero when it is not valid
195: to use the value of this register in some
196: register's value
197:
198: To understand the usage of these tables, it is important to understand
199: the distinction between the value in reg_last_set_value being valid
200: and the register being validly contained in some other expression in the
201: table.
202:
203: Entry I in reg_last_set_value is valid if it is non-zero, and either
204: reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
205:
206: Register I may validly appear in any expression returned for the value
207: of another register if reg_n_sets[i] is 1. It may also appear in the
208: value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
209: reg_last_set_invalid[j] is zero.
210:
211: If an expression is found in the table containing a register which may
212: not validly appear in an expression, the register is replaced by
213: something that won't match, (clobber (const_int 0)).
214:
215: reg_last_set_invalid[i] is set non-zero when register I is being assigned
216: to and reg_last_set_table_tick[i] == label_tick. */
217:
218: /* Record last value assigned to (hard or pseudo) register n. */
219:
220: static rtx *reg_last_set_value;
221:
222: /* Record the value of label_tick when the value for register n is placed in
223: reg_last_set_value[n]. */
224:
225: static short *reg_last_set_label;
226:
227: /* Record the value of label_tick when an expression involving register n
228: is placed in reg_last_set_value. */
229:
230: static short *reg_last_set_table_tick;
231:
232: /* Set non-zero if references to register n in expressions should not be
233: used. */
234:
235: static char *reg_last_set_invalid;
236:
237: /* Incremented for each label. */
238:
239: static short label_tick;
240:
241: /* Some registers that are set more than once and used in more than one
242: basic block are nevertheless always set in similar ways. For example,
243: a QImode register may be loaded from memory in two places on a machine
244: where byte loads zero extend.
245:
246: We record in the following array what we know about the significant
247: bits of a register, specifically which bits are known to be zero.
248:
249: If an entry is zero, it means that we don't know anything special. */
250:
1.1.1.4 ! root 251: static HOST_WIDE_INT *reg_significant;
1.1 root 252:
253: /* Mode used to compute significance in reg_significant. It is the largest
1.1.1.4 ! root 254: integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
1.1 root 255:
256: static enum machine_mode significant_mode;
257:
1.1.1.4 ! root 258: /* Nonzero if we know that a register has some leading bits that are always
! 259: equal to the sign bit. */
! 260:
! 261: static char *reg_sign_bit_copies;
! 262:
! 263: /* Nonzero when reg_significant and reg_sign_bit_copies can be safely used.
! 264: It is zero while computing them and after combine has completed. This
! 265: former test prevents propagating values based on previously set values,
! 266: which can be incorrect if a variable is modified in a loop. */
1.1 root 267:
268: static int significant_valid;
269:
270: /* Record one modification to rtl structure
271: to be undone by storing old_contents into *where.
272: is_int is 1 if the contents are an int. */
273:
274: struct undo
275: {
276: int is_int;
1.1.1.4 ! root 277: union {rtx rtx; int i;} old_contents;
! 278: union {rtx *rtx; int *i;} where;
1.1 root 279: };
280:
281: /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
282: num_undo says how many are currently recorded.
283:
284: storage is nonzero if we must undo the allocation of new storage.
285: The value of storage is what to pass to obfree.
286:
287: other_insn is nonzero if we have modified some other insn in the process
288: of working on subst_insn. It must be verified too. */
289:
290: #define MAX_UNDO 50
291:
292: struct undobuf
293: {
294: int num_undo;
295: char *storage;
296: struct undo undo[MAX_UNDO];
297: rtx other_insn;
298: };
299:
300: static struct undobuf undobuf;
301:
1.1.1.4 ! root 302: /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
1.1 root 303: insn. The substitution can be undone by undo_all. If INTO is already
1.1.1.4 ! root 304: set to NEWVAL, do not record this change. Because computing NEWVAL might
! 305: also call SUBST, we have to compute it before we put anything into
! 306: the undo table. */
1.1 root 307:
308: #define SUBST(INTO, NEWVAL) \
1.1.1.4 ! root 309: do { rtx _new = (NEWVAL); \
! 310: if (undobuf.num_undo < MAX_UNDO) \
1.1 root 311: { \
312: undobuf.undo[undobuf.num_undo].is_int = 0; \
1.1.1.4 ! root 313: undobuf.undo[undobuf.num_undo].where.rtx = &INTO; \
! 314: undobuf.undo[undobuf.num_undo].old_contents.rtx = INTO; \
! 315: INTO = _new; \
! 316: if (undobuf.undo[undobuf.num_undo].old_contents.rtx != INTO) \
1.1 root 317: undobuf.num_undo++; \
318: } \
319: } while (0)
320:
321: /* Similar to SUBST, but NEWVAL is an int. INTO will normally be an XINT
322: expression.
323: Note that substitution for the value of a CONST_INT is not safe. */
324:
325: #define SUBST_INT(INTO, NEWVAL) \
326: do { if (undobuf.num_undo < MAX_UNDO) \
327: { \
1.1.1.4 ! root 328: undobuf.undo[undobuf.num_undo].is_int = 1; \
! 329: undobuf.undo[undobuf.num_undo].where.i = (int *) &INTO; \
! 330: undobuf.undo[undobuf.num_undo].old_contents.i = INTO; \
1.1 root 331: INTO = NEWVAL; \
1.1.1.4 ! root 332: if (undobuf.undo[undobuf.num_undo].old_contents.i != INTO) \
1.1 root 333: undobuf.num_undo++; \
334: } \
335: } while (0)
336:
337: /* Number of times the pseudo being substituted for
338: was found and replaced. */
339:
340: static int n_occurrences;
341:
342: static void set_significant ();
343: static void move_deaths ();
344: rtx remove_death ();
345: static void record_value_for_reg ();
346: static void record_dead_and_set_regs ();
347: static int use_crosses_set_p ();
348: static rtx try_combine ();
349: static rtx *find_split_point ();
350: static rtx subst ();
351: static void undo_all ();
352: static int reg_dead_at_p ();
353: static rtx expand_compound_operation ();
354: static rtx expand_field_assignment ();
355: static rtx make_extraction ();
356: static int get_pos_from_mask ();
1.1.1.4 ! root 357: static rtx force_to_mode ();
! 358: static rtx known_cond ();
1.1 root 359: static rtx make_field_assignment ();
360: static rtx make_compound_operation ();
361: static rtx apply_distributive_law ();
362: static rtx simplify_and_const_int ();
1.1.1.4 ! root 363: static unsigned HOST_WIDE_INT significant_bits ();
! 364: static int num_sign_bit_copies ();
1.1 root 365: static int merge_outer_ops ();
366: static rtx simplify_shift_const ();
367: static int recog_for_combine ();
368: static rtx gen_lowpart_for_combine ();
369: static rtx gen_rtx_combine ();
370: static rtx gen_binary ();
371: static rtx gen_unary ();
372: static enum rtx_code simplify_comparison ();
373: static int reversible_comparison_p ();
374: static int get_last_value_validate ();
375: static rtx get_last_value ();
376: static void distribute_notes ();
377: static void distribute_links ();
378:
379: /* Main entry point for combiner. F is the first insn of the function.
380: NREGS is the first unused pseudo-reg number. */
381:
382: void
383: combine_instructions (f, nregs)
384: rtx f;
385: int nregs;
386: {
387: register rtx insn, next, prev;
388: register int i;
389: register rtx links, nextlinks;
390:
391: combine_attempts = 0;
392: combine_merges = 0;
393: combine_extras = 0;
394: combine_successes = 0;
395:
396: combine_max_regno = nregs;
397:
398: reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
399: reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
400: reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
401: reg_last_set_table_tick = (short *) alloca (nregs * sizeof (short));
402: reg_last_set_label = (short *) alloca (nregs * sizeof (short));
1.1.1.4 ! root 403: reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
! 404: reg_significant = (HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
! 405: reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
1.1 root 406:
407: bzero (reg_last_death, nregs * sizeof (rtx));
408: bzero (reg_last_set, nregs * sizeof (rtx));
409: bzero (reg_last_set_value, nregs * sizeof (rtx));
410: bzero (reg_last_set_table_tick, nregs * sizeof (short));
411: bzero (reg_last_set_invalid, nregs * sizeof (char));
1.1.1.4 ! root 412: bzero (reg_significant, nregs * sizeof (HOST_WIDE_INT));
! 413: bzero (reg_sign_bit_copies, nregs * sizeof (char));
1.1 root 414:
415: init_recog_no_volatile ();
416:
417: /* Compute maximum uid value so uid_cuid can be allocated. */
418:
419: for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
420: if (INSN_UID (insn) > i)
421: i = INSN_UID (insn);
422:
423: uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
424:
1.1.1.4 ! root 425: significant_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1.1 root 426:
427: /* Don't use reg_significant when computing it. This can cause problems
428: when, for example, we have j <<= 1 in a loop. */
429:
430: significant_valid = 0;
431:
432: /* Compute the mapping from uids to cuids.
433: Cuids are numbers assigned to insns, like uids,
434: except that cuids increase monotonically through the code.
435:
436: Scan all SETs and see if we can deduce anything about what
437: bits are significant for some registers. */
438:
439: for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
440: {
441: INSN_CUID (insn) = ++i;
442: if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
443: note_stores (PATTERN (insn), set_significant);
444: }
445:
446: significant_valid = 1;
447:
448: /* Now scan all the insns in forward order. */
449:
450: label_tick = 1;
451: last_call_cuid = 0;
452: mem_last_set = 0;
453:
454: for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
455: {
456: next = 0;
457:
458: if (GET_CODE (insn) == CODE_LABEL)
459: label_tick++;
460:
461: else if (GET_CODE (insn) == INSN
462: || GET_CODE (insn) == CALL_INSN
463: || GET_CODE (insn) == JUMP_INSN)
464: {
465: /* Try this insn with each insn it links back to. */
466:
467: for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1.1.1.4 ! root 468: if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
1.1 root 469: goto retry;
470:
471: /* Try each sequence of three linked insns ending with this one. */
472:
473: for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
474: for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
475: nextlinks = XEXP (nextlinks, 1))
476: if ((next = try_combine (insn, XEXP (links, 0),
477: XEXP (nextlinks, 0))) != 0)
478: goto retry;
479:
480: #ifdef HAVE_cc0
481: /* Try to combine a jump insn that uses CC0
482: with a preceding insn that sets CC0, and maybe with its
483: logical predecessor as well.
484: This is how we make decrement-and-branch insns.
485: We need this special code because data flow connections
486: via CC0 do not get entered in LOG_LINKS. */
487:
488: if (GET_CODE (insn) == JUMP_INSN
489: && (prev = prev_nonnote_insn (insn)) != 0
490: && GET_CODE (prev) == INSN
491: && sets_cc0_p (PATTERN (prev)))
492: {
1.1.1.4 ! root 493: if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
1.1 root 494: goto retry;
495:
496: for (nextlinks = LOG_LINKS (prev); nextlinks;
497: nextlinks = XEXP (nextlinks, 1))
498: if ((next = try_combine (insn, prev,
499: XEXP (nextlinks, 0))) != 0)
500: goto retry;
501: }
502:
503: /* Do the same for an insn that explicitly references CC0. */
504: if (GET_CODE (insn) == INSN
505: && (prev = prev_nonnote_insn (insn)) != 0
506: && GET_CODE (prev) == INSN
507: && sets_cc0_p (PATTERN (prev))
508: && GET_CODE (PATTERN (insn)) == SET
509: && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
510: {
1.1.1.4 ! root 511: if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
1.1 root 512: goto retry;
513:
514: for (nextlinks = LOG_LINKS (prev); nextlinks;
515: nextlinks = XEXP (nextlinks, 1))
516: if ((next = try_combine (insn, prev,
517: XEXP (nextlinks, 0))) != 0)
518: goto retry;
519: }
520:
521: /* Finally, see if any of the insns that this insn links to
522: explicitly references CC0. If so, try this insn, that insn,
1.1.1.2 root 523: and its predecessor if it sets CC0. */
1.1 root 524: for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
525: if (GET_CODE (XEXP (links, 0)) == INSN
526: && GET_CODE (PATTERN (XEXP (links, 0))) == SET
527: && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
528: && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
529: && GET_CODE (prev) == INSN
530: && sets_cc0_p (PATTERN (prev))
531: && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
532: goto retry;
533: #endif
534:
535: /* Try combining an insn with two different insns whose results it
536: uses. */
537: for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
538: for (nextlinks = XEXP (links, 1); nextlinks;
539: nextlinks = XEXP (nextlinks, 1))
540: if ((next = try_combine (insn, XEXP (links, 0),
541: XEXP (nextlinks, 0))) != 0)
542: goto retry;
543:
544: if (GET_CODE (insn) != NOTE)
545: record_dead_and_set_regs (insn);
546:
547: retry:
548: ;
549: }
550: }
551:
552: total_attempts += combine_attempts;
553: total_merges += combine_merges;
554: total_extras += combine_extras;
555: total_successes += combine_successes;
1.1.1.4 ! root 556:
! 557: significant_valid = 0;
1.1 root 558: }
559:
560: /* Called via note_stores. If X is a pseudo that is used in more than
1.1.1.4 ! root 561: one basic block, is narrower that HOST_BITS_PER_WIDE_INT, and is being
1.1 root 562: set, record what bits are significant. If we are clobbering X,
563: ignore this "set" because the clobbered value won't be used.
564:
565: If we are setting only a portion of X and we can't figure out what
566: portion, assume all bits will be used since we don't know what will
1.1.1.4 ! root 567: be happening.
! 568:
! 569: Similarly, set how many bits of X are known to be copies of the sign bit
! 570: at all locations in the function. This is the smallest number implied
! 571: by any set of X. */
1.1 root 572:
573: static void
574: set_significant (x, set)
575: rtx x;
576: rtx set;
577: {
1.1.1.4 ! root 578: int num;
! 579:
1.1 root 580: if (GET_CODE (x) == REG
581: && REGNO (x) >= FIRST_PSEUDO_REGISTER
582: && reg_n_sets[REGNO (x)] > 1
583: && reg_basic_block[REGNO (x)] < 0
1.1.1.4 ! root 584: && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1.1 root 585: {
586: if (GET_CODE (set) == CLOBBER)
587: return;
588:
589: /* If this is a complex assignment, see if we can convert it into a
1.1.1.2 root 590: simple assignment. */
1.1 root 591: set = expand_field_assignment (set);
592: if (SET_DEST (set) == x)
1.1.1.4 ! root 593: {
! 594: reg_significant[REGNO (x)]
! 595: |= significant_bits (SET_SRC (set), significant_mode);
! 596: num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
! 597: if (reg_sign_bit_copies[REGNO (x)] == 0
! 598: || reg_sign_bit_copies[REGNO (x)] > num)
! 599: reg_sign_bit_copies[REGNO (x)] = num;
! 600: }
1.1 root 601: else
1.1.1.4 ! root 602: {
! 603: reg_significant[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
! 604: reg_sign_bit_copies[REGNO (x)] = 0;
! 605: }
1.1 root 606: }
607: }
608:
609: /* See if INSN can be combined into I3. PRED and SUCC are optionally
610: insns that were previously combined into I3 or that will be combined
611: into the merger of INSN and I3.
612:
613: Return 0 if the combination is not allowed for any reason.
614:
615: If the combination is allowed, *PDEST will be set to the single
616: destination of INSN and *PSRC to the single source, and this function
617: will return 1. */
618:
619: static int
620: can_combine_p (insn, i3, pred, succ, pdest, psrc)
621: rtx insn;
622: rtx i3;
623: rtx pred, succ;
624: rtx *pdest, *psrc;
625: {
626: int i;
627: rtx set = 0, src, dest;
628: rtx p, link;
629: int all_adjacent = (succ ? (next_active_insn (insn) == succ
630: && next_active_insn (succ) == i3)
631: : next_active_insn (insn) == i3);
632:
633: /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
634: or a PARALLEL consisting of such a SET and CLOBBERs.
635:
636: If INSN has CLOBBER parallel parts, ignore them for our processing.
637: By definition, these happen during the execution of the insn. When it
638: is merged with another insn, all bets are off. If they are, in fact,
639: needed and aren't also supplied in I3, they may be added by
640: recog_for_combine. Otherwise, it won't match.
641:
642: We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
643: note.
644:
645: Get the source and destination of INSN. If more than one, can't
646: combine. */
647:
648: if (GET_CODE (PATTERN (insn)) == SET)
649: set = PATTERN (insn);
650: else if (GET_CODE (PATTERN (insn)) == PARALLEL
651: && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
652: {
653: for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
654: {
655: rtx elt = XVECEXP (PATTERN (insn), 0, i);
656:
657: switch (GET_CODE (elt))
658: {
659: /* We can ignore CLOBBERs. */
660: case CLOBBER:
661: break;
662:
663: case SET:
664: /* Ignore SETs whose result isn't used but not those that
665: have side-effects. */
666: if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
667: && ! side_effects_p (elt))
668: break;
669:
670: /* If we have already found a SET, this is a second one and
671: so we cannot combine with this insn. */
672: if (set)
673: return 0;
674:
675: set = elt;
676: break;
677:
678: default:
679: /* Anything else means we can't combine. */
680: return 0;
681: }
682: }
683:
684: if (set == 0
685: /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
686: so don't do anything with it. */
687: || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
688: return 0;
689: }
690: else
691: return 0;
692:
693: if (set == 0)
694: return 0;
695:
696: set = expand_field_assignment (set);
697: src = SET_SRC (set), dest = SET_DEST (set);
698:
699: /* Don't eliminate a store in the stack pointer. */
700: if (dest == stack_pointer_rtx
701: /* Don't install a subreg involving two modes not tieable.
702: It can worsen register allocation, and can even make invalid reload
703: insns, since the reg inside may need to be copied from in the
704: outside mode, and that may be invalid if it is an fp reg copied in
1.1.1.2 root 705: integer mode. As a special exception, we can allow this if
706: I3 is simply copying DEST, a REG, to CC0. */
1.1 root 707: || (GET_CODE (src) == SUBREG
1.1.1.2 root 708: && ! MODES_TIEABLE_P (GET_MODE (src), GET_MODE (SUBREG_REG (src)))
709: #ifdef HAVE_cc0
710: && ! (GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
711: && SET_DEST (PATTERN (i3)) == cc0_rtx
712: && GET_CODE (dest) == REG && dest == SET_SRC (PATTERN (i3)))
713: #endif
714: )
1.1 root 715: /* If we couldn't eliminate a field assignment, we can't combine. */
716: || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
717: /* Don't combine with an insn that sets a register to itself if it has
718: a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1.1.1.4 ! root 719: || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1.1 root 720: /* Can't merge a function call. */
721: || GET_CODE (src) == CALL
722: /* Don't substitute into an incremented register. */
723: || FIND_REG_INC_NOTE (i3, dest)
724: || (succ && FIND_REG_INC_NOTE (succ, dest))
725: /* Don't combine the end of a libcall into anything. */
1.1.1.4 ! root 726: || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1.1 root 727: /* Make sure that DEST is not used after SUCC but before I3. */
728: || (succ && ! all_adjacent
729: && reg_used_between_p (dest, succ, i3))
730: /* Make sure that the value that is to be substituted for the register
731: does not use any registers whose values alter in between. However,
732: If the insns are adjacent, a use can't cross a set even though we
733: think it might (this can happen for a sequence of insns each setting
734: the same destination; reg_last_set of that register might point to
735: a NOTE). Also, don't move a volatile asm across any other insns. */
736: || (! all_adjacent
737: && (use_crosses_set_p (src, INSN_CUID (insn))
738: || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))))
739: /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
740: better register allocation by not doing the combine. */
741: || find_reg_note (i3, REG_NO_CONFLICT, dest)
742: || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
743: /* Don't combine across a CALL_INSN, because that would possibly
744: change whether the life span of some REGs crosses calls or not,
745: and it is a pain to update that information.
746: Exception: if source is a constant, moving it later can't hurt.
747: Accept that special case, because it helps -fforce-addr a lot. */
748: || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
749: return 0;
750:
751: /* DEST must either be a REG or CC0. */
752: if (GET_CODE (dest) == REG)
753: {
754: /* If register alignment is being enforced for multi-word items in all
755: cases except for parameters, it is possible to have a register copy
756: insn referencing a hard register that is not allowed to contain the
757: mode being copied and which would not be valid as an operand of most
758: insns. Eliminate this problem by not combining with such an insn.
759:
760: Also, on some machines we don't want to extend the life of a hard
761: register. */
762:
763: if (GET_CODE (src) == REG
764: && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
765: && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
766: #ifdef SMALL_REGISTER_CLASSES
767: /* Don't extend the life of a hard register. */
768: || REGNO (src) < FIRST_PSEUDO_REGISTER
769: #else
770: || (REGNO (src) < FIRST_PSEUDO_REGISTER
771: && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))
772: #endif
773: ))
774: return 0;
775: }
776: else if (GET_CODE (dest) != CC0)
777: return 0;
778:
1.1.1.4 ! root 779: /* Don't substitute for a register intended as a clobberable operand.
! 780: Similarly, don't substitute an expression containing a register that
! 781: will be clobbered in I3. */
1.1 root 782: if (GET_CODE (PATTERN (i3)) == PARALLEL)
783: for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
784: if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1.1.1.4 ! root 785: && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
! 786: src)
! 787: || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1.1 root 788: return 0;
789:
790: /* If INSN contains anything volatile, or is an `asm' (whether volatile
791: or not), reject, unless nothing volatile comes between it and I3,
792: with the exception of SUCC. */
793:
794: if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
795: for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
796: if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
797: && p != succ && volatile_refs_p (PATTERN (p)))
798: return 0;
799:
800: /* If INSN or I2 contains an autoincrement or autodecrement,
801: make sure that register is not used between there and I3,
802: and not already used in I3 either.
803: Also insist that I3 not be a jump; if it were one
804: and the incremented register were spilled, we would lose. */
805:
806: #ifdef AUTO_INC_DEC
807: for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
808: if (REG_NOTE_KIND (link) == REG_INC
809: && (GET_CODE (i3) == JUMP_INSN
810: || reg_used_between_p (XEXP (link, 0), insn, i3)
811: || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
812: return 0;
813: #endif
814:
815: #ifdef HAVE_cc0
816: /* Don't combine an insn that follows a CC0-setting insn.
817: An insn that uses CC0 must not be separated from the one that sets it.
818: We do, however, allow I2 to follow a CC0-setting insn if that insn
819: is passed as I1; in that case it will be deleted also.
820: We also allow combining in this case if all the insns are adjacent
821: because that would leave the two CC0 insns adjacent as well.
822: It would be more logical to test whether CC0 occurs inside I1 or I2,
823: but that would be much slower, and this ought to be equivalent. */
824:
825: p = prev_nonnote_insn (insn);
826: if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
827: && ! all_adjacent)
828: return 0;
829: #endif
830:
831: /* If we get here, we have passed all the tests and the combination is
832: to be allowed. */
833:
834: *pdest = dest;
835: *psrc = src;
836:
837: return 1;
838: }
839:
840: /* LOC is the location within I3 that contains its pattern or the component
841: of a PARALLEL of the pattern. We validate that it is valid for combining.
842:
843: One problem is if I3 modifies its output, as opposed to replacing it
844: entirely, we can't allow the output to contain I2DEST or I1DEST as doing
845: so would produce an insn that is not equivalent to the original insns.
846:
847: Consider:
848:
849: (set (reg:DI 101) (reg:DI 100))
850: (set (subreg:SI (reg:DI 101) 0) <foo>)
851:
852: This is NOT equivalent to:
853:
854: (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
855: (set (reg:DI 101) (reg:DI 100))])
856:
857: Not only does this modify 100 (in which case it might still be valid
858: if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
859:
860: We can also run into a problem if I2 sets a register that I1
861: uses and I1 gets directly substituted into I3 (not via I2). In that
862: case, we would be getting the wrong value of I2DEST into I3, so we
863: must reject the combination. This case occurs when I2 and I1 both
864: feed into I3, rather than when I1 feeds into I2, which feeds into I3.
865: If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
866: of a SET must prevent combination from occurring.
867:
868: On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
869: if the destination of a SET is a hard register.
870:
871: Before doing the above check, we first try to expand a field assignment
872: into a set of logical operations.
873:
874: If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
875: we place a register that is both set and used within I3. If more than one
876: such register is detected, we fail.
877:
878: Return 1 if the combination is valid, zero otherwise. */
879:
880: static int
881: combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
882: rtx i3;
883: rtx *loc;
884: rtx i2dest;
885: rtx i1dest;
886: int i1_not_in_src;
887: rtx *pi3dest_killed;
888: {
889: rtx x = *loc;
890:
891: if (GET_CODE (x) == SET)
892: {
893: rtx set = expand_field_assignment (x);
894: rtx dest = SET_DEST (set);
895: rtx src = SET_SRC (set);
896: rtx inner_dest = dest, inner_src = src;
897:
898: SUBST (*loc, set);
899:
900: while (GET_CODE (inner_dest) == STRICT_LOW_PART
901: || GET_CODE (inner_dest) == SUBREG
902: || GET_CODE (inner_dest) == ZERO_EXTRACT)
903: inner_dest = XEXP (inner_dest, 0);
904:
905: /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
906: was added. */
907: #if 0
908: while (GET_CODE (inner_src) == STRICT_LOW_PART
909: || GET_CODE (inner_src) == SUBREG
910: || GET_CODE (inner_src) == ZERO_EXTRACT)
911: inner_src = XEXP (inner_src, 0);
912:
913: /* If it is better that two different modes keep two different pseudos,
914: avoid combining them. This avoids producing the following pattern
915: on a 386:
916: (set (subreg:SI (reg/v:QI 21) 0)
917: (lshiftrt:SI (reg/v:SI 20)
918: (const_int 24)))
919: If that were made, reload could not handle the pair of
920: reg 20/21, since it would try to get any GENERAL_REGS
921: but some of them don't handle QImode. */
922:
923: if (rtx_equal_p (inner_src, i2dest)
924: && GET_CODE (inner_dest) == REG
925: && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
926: return 0;
927: #endif
928:
929: /* Check for the case where I3 modifies its output, as
930: discussed above. */
931: if ((inner_dest != dest
932: && (reg_overlap_mentioned_p (i2dest, inner_dest)
933: || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1.1.1.3 root 934: /* This is the same test done in can_combine_p except that we
935: allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
936: CALL operation. */
1.1 root 937: || (GET_CODE (inner_dest) == REG
1.1.1.2 root 938: && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1.1.1.3 root 939: #ifdef SMALL_REGISTER_CLASSES
940: && GET_CODE (src) != CALL
941: #else
1.1.1.2 root 942: && ! HARD_REGNO_MODE_OK (REGNO (inner_dest),
943: GET_MODE (inner_dest))
1.1 root 944: #endif
1.1.1.2 root 945: )
946:
1.1 root 947: || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
948: return 0;
949:
950: /* If DEST is used in I3, it is being killed in this insn,
951: so record that for later. */
952: if (pi3dest_killed && GET_CODE (dest) == REG
953: && reg_referenced_p (dest, PATTERN (i3)))
954: {
955: if (*pi3dest_killed)
956: return 0;
957:
958: *pi3dest_killed = dest;
959: }
960: }
961:
962: else if (GET_CODE (x) == PARALLEL)
963: {
964: int i;
965:
966: for (i = 0; i < XVECLEN (x, 0); i++)
967: if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
968: i1_not_in_src, pi3dest_killed))
969: return 0;
970: }
971:
972: return 1;
973: }
974:
975: /* Try to combine the insns I1 and I2 into I3.
976: Here I1 and I2 appear earlier than I3.
977: I1 can be zero; then we combine just I2 into I3.
978:
979: It we are combining three insns and the resulting insn is not recognized,
980: try splitting it into two insns. If that happens, I2 and I3 are retained
981: and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
982: are pseudo-deleted.
983:
984: If we created two insns, return I2; otherwise return I3.
985: Return 0 if the combination does not work. Then nothing is changed. */
986:
987: static rtx
988: try_combine (i3, i2, i1)
989: register rtx i3, i2, i1;
990: {
991: /* New patterns for I3 and I3, respectively. */
992: rtx newpat, newi2pat = 0;
993: /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
994: int added_sets_1, added_sets_2;
995: /* Total number of SETs to put into I3. */
996: int total_sets;
997: /* Nonzero is I2's body now appears in I3. */
998: int i2_is_used;
999: /* INSN_CODEs for new I3, new I2, and user of condition code. */
1000: int insn_code_number, i2_code_number, other_code_number;
1001: /* Contains I3 if the destination of I3 is used in its source, which means
1002: that the old life of I3 is being killed. If that usage is placed into
1003: I2 and not in I3, a REG_DEAD note must be made. */
1004: rtx i3dest_killed = 0;
1005: /* SET_DEST and SET_SRC of I2 and I1. */
1006: rtx i2dest, i2src, i1dest = 0, i1src = 0;
1007: /* PATTERN (I2), or a copy of it in certain cases. */
1008: rtx i2pat;
1009: /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1010: int i2dest_in_i2src, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1011: int i1_feeds_i3 = 0;
1012: /* Notes that must be added to REG_NOTES in I3 and I2. */
1013: rtx new_i3_notes, new_i2_notes;
1014:
1015: int maxreg;
1016: rtx temp;
1017: register rtx link;
1018: int i;
1019:
1020: /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1021: This can occur when flow deletes an insn that it has merged into an
1022: auto-increment address. We also can't do anything if I3 has a
1023: REG_LIBCALL note since we don't want to disrupt the contiguity of a
1024: libcall. */
1025:
1026: if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1027: || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1028: || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1.1.1.4 ! root 1029: || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
1.1 root 1030: return 0;
1031:
1032: combine_attempts++;
1033:
1034: undobuf.num_undo = previous_num_undos = 0;
1035: undobuf.other_insn = 0;
1036:
1037: /* Save the current high-water-mark so we can free storage if we didn't
1038: accept this combination. */
1039: undobuf.storage = (char *) oballoc (0);
1040:
1041: /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1042: code below, set I1 to be the earlier of the two insns. */
1043: if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1044: temp = i1, i1 = i2, i2 = temp;
1045:
1046: /* First check for one important special-case that the code below will
1047: not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1048: and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1049: we may be able to replace that destination with the destination of I3.
1050: This occurs in the common code where we compute both a quotient and
1051: remainder into a structure, in which case we want to do the computation
1052: directly into the structure to avoid register-register copies.
1053:
1054: We make very conservative checks below and only try to handle the
1055: most common cases of this. For example, we only handle the case
1056: where I2 and I3 are adjacent to avoid making difficult register
1057: usage tests. */
1058:
1059: if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1060: && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1061: && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1062: #ifdef SMALL_REGISTER_CLASSES
1063: && (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1064: || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER)
1065: #endif
1066: && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1067: && GET_CODE (PATTERN (i2)) == PARALLEL
1068: && ! side_effects_p (SET_DEST (PATTERN (i3)))
1.1.1.2 root 1069: /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1070: below would need to check what is inside (and reg_overlap_mentioned_p
1071: doesn't support those codes anyway). Don't allow those destinations;
1072: the resulting insn isn't likely to be recognized anyway. */
1073: && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1074: && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1.1 root 1075: && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1076: SET_DEST (PATTERN (i3)))
1077: && next_real_insn (i2) == i3)
1.1.1.2 root 1078: {
1079: rtx p2 = PATTERN (i2);
1.1 root 1080:
1.1.1.2 root 1081: /* Make sure that the destination of I3,
1082: which we are going to substitute into one output of I2,
1083: is not used within another output of I2. We must avoid making this:
1084: (parallel [(set (mem (reg 69)) ...)
1085: (set (reg 69) ...)])
1086: which is not well-defined as to order of actions.
1087: (Besides, reload can't handle output reloads for this.)
1088:
1089: The problem can also happen if the dest of I3 is a memory ref,
1090: if another dest in I2 is an indirect memory ref. */
1091: for (i = 0; i < XVECLEN (p2, 0); i++)
1092: if (GET_CODE (XVECEXP (p2, 0, i)) == SET
1093: && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1094: SET_DEST (XVECEXP (p2, 0, i))))
1095: break;
1096:
1097: if (i == XVECLEN (p2, 0))
1098: for (i = 0; i < XVECLEN (p2, 0); i++)
1099: if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1100: {
1101: combine_merges++;
1102:
1103: subst_insn = i3;
1104: subst_low_cuid = INSN_CUID (i2);
1105:
1106: added_sets_2 = 0;
1107: i2dest = SET_SRC (PATTERN (i3));
1108:
1109: /* Replace the dest in I2 with our dest and make the resulting
1110: insn the new pattern for I3. Then skip to where we
1111: validate the pattern. Everything was set up above. */
1112: SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1113: SET_DEST (PATTERN (i3)));
1.1 root 1114:
1.1.1.2 root 1115: newpat = p2;
1116: goto validate_replacement;
1117: }
1118: }
1.1 root 1119:
1120: #ifndef HAVE_cc0
1121: /* If we have no I1 and I2 looks like:
1122: (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1123: (set Y OP)])
1124: make up a dummy I1 that is
1125: (set Y OP)
1126: and change I2 to be
1127: (set (reg:CC X) (compare:CC Y (const_int 0)))
1128:
1129: (We can ignore any trailing CLOBBERs.)
1130:
1131: This undoes a previous combination and allows us to match a branch-and-
1132: decrement insn. */
1133:
1134: if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1135: && XVECLEN (PATTERN (i2), 0) >= 2
1136: && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1137: && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1138: == MODE_CC)
1139: && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1140: && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1141: && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1142: && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1143: && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1144: SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1145: {
1146: for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1147: if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1148: break;
1149:
1150: if (i == 1)
1151: {
1152: /* We make I1 with the same INSN_UID as I2. This gives it
1153: the same INSN_CUID for value tracking. Our fake I1 will
1154: never appear in the insn stream so giving it the same INSN_UID
1155: as I2 will not cause a problem. */
1156:
1157: i1 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), 0, i2,
1158: XVECEXP (PATTERN (i2), 0, 1), -1, 0, 0);
1159:
1160: SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1161: SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1162: SET_DEST (PATTERN (i1)));
1163: }
1164: }
1165: #endif
1166:
1167: /* Verify that I2 and I1 are valid for combining. */
1.1.1.4 ! root 1168: if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
! 1169: || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1.1 root 1170: {
1171: undo_all ();
1172: return 0;
1173: }
1174:
1175: /* Record whether I2DEST is used in I2SRC and similarly for the other
1176: cases. Knowing this will help in register status updating below. */
1177: i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1178: i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1179: i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1180:
1.1.1.3 root 1181: /* See if I1 directly feeds into I3. It does if I1DEST is not used
1.1 root 1182: in I2SRC. */
1183: i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1184:
1185: /* Ensure that I3's pattern can be the destination of combines. */
1186: if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1187: i1 && i2dest_in_i1src && i1_feeds_i3,
1188: &i3dest_killed))
1189: {
1190: undo_all ();
1191: return 0;
1192: }
1193:
1194: /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1195: We used to do this EXCEPT in one case: I3 has a post-inc in an
1196: output operand. However, that exception can give rise to insns like
1197: mov r3,(r3)+
1198: which is a famous insn on the PDP-11 where the value of r3 used as the
1.1.1.2 root 1199: source was model-dependent. Avoid this sort of thing. */
1.1 root 1200:
1201: #if 0
1202: if (!(GET_CODE (PATTERN (i3)) == SET
1203: && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1204: && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1205: && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1206: || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1207: /* It's not the exception. */
1208: #endif
1209: #ifdef AUTO_INC_DEC
1210: for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1211: if (REG_NOTE_KIND (link) == REG_INC
1212: && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1213: || (i1 != 0
1214: && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1215: {
1216: undo_all ();
1217: return 0;
1218: }
1219: #endif
1220:
1221: /* See if the SETs in I1 or I2 need to be kept around in the merged
1222: instruction: whenever the value set there is still needed past I3.
1223: For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1224:
1225: For the SET in I1, we have two cases: If I1 and I2 independently
1226: feed into I3, the set in I1 needs to be kept around if I1DEST dies
1227: or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1228: in I1 needs to be kept around unless I1DEST dies or is set in either
1229: I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1230: I1DEST. If so, we know I1 feeds into I2. */
1231:
1232: added_sets_2 = ! dead_or_set_p (i3, i2dest);
1233:
1234: added_sets_1
1235: = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1236: : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1237:
1238: /* If the set in I2 needs to be kept around, we must make a copy of
1239: PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1.1.1.2 root 1240: PATTERN (I2), we are only substituting for the original I1DEST, not into
1.1 root 1241: an already-substituted copy. This also prevents making self-referential
1242: rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1243: I2DEST. */
1244:
1245: i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1246: ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1247: : PATTERN (i2));
1248:
1249: if (added_sets_2)
1250: i2pat = copy_rtx (i2pat);
1251:
1252: combine_merges++;
1253:
1254: /* Substitute in the latest insn for the regs set by the earlier ones. */
1255:
1256: maxreg = max_reg_num ();
1257:
1258: subst_insn = i3;
1259:
1260: /* It is possible that the source of I2 or I1 may be performing an
1261: unneeded operation, such as a ZERO_EXTEND of something that is known
1262: to have the high part zero. Handle that case by letting subst look at
1263: the innermost one of them.
1264:
1265: Another way to do this would be to have a function that tries to
1266: simplify a single insn instead of merging two or more insns. We don't
1267: do this because of the potential of infinite loops and because
1268: of the potential extra memory required. However, doing it the way
1269: we are is a bit of a kludge and doesn't catch all cases.
1270:
1271: But only do this if -fexpensive-optimizations since it slows things down
1272: and doesn't usually win. */
1273:
1274: if (flag_expensive_optimizations)
1275: {
1276: /* Pass pc_rtx so no substitutions are done, just simplifications.
1277: The cases that we are interested in here do not involve the few
1278: cases were is_replaced is checked. */
1279: if (i1)
1.1.1.4 ! root 1280: {
! 1281: subst_low_cuid = INSN_CUID (i1);
! 1282: i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
! 1283: }
1.1 root 1284: else
1.1.1.4 ! root 1285: {
! 1286: subst_low_cuid = INSN_CUID (i2);
! 1287: i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
! 1288: }
1.1 root 1289:
1290: previous_num_undos = undobuf.num_undo;
1291: }
1292:
1293: #ifndef HAVE_cc0
1294: /* Many machines that don't use CC0 have insns that can both perform an
1295: arithmetic operation and set the condition code. These operations will
1296: be represented as a PARALLEL with the first element of the vector
1297: being a COMPARE of an arithmetic operation with the constant zero.
1298: The second element of the vector will set some pseudo to the result
1299: of the same arithmetic operation. If we simplify the COMPARE, we won't
1300: match such a pattern and so will generate an extra insn. Here we test
1301: for this case, where both the comparison and the operation result are
1302: needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1303: I2SRC. Later we will make the PARALLEL that contains I2. */
1304:
1305: if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1306: && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1307: && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1308: && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1309: {
1310: rtx *cc_use;
1311: enum machine_mode compare_mode;
1312:
1313: newpat = PATTERN (i3);
1314: SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1315:
1316: i2_is_used = 1;
1317:
1318: #ifdef EXTRA_CC_MODES
1319: /* See if a COMPARE with the operand we substituted in should be done
1320: with the mode that is currently being used. If not, do the same
1321: processing we do in `subst' for a SET; namely, if the destination
1322: is used only once, try to replace it with a register of the proper
1323: mode and also replace the COMPARE. */
1324: if (undobuf.other_insn == 0
1325: && (cc_use = find_single_use (SET_DEST (newpat), i3,
1326: &undobuf.other_insn))
1.1.1.4 ! root 1327: && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
! 1328: i2src, const0_rtx))
1.1 root 1329: != GET_MODE (SET_DEST (newpat))))
1330: {
1331: int regno = REGNO (SET_DEST (newpat));
1332: rtx new_dest = gen_rtx (REG, compare_mode, regno);
1333:
1334: if (regno < FIRST_PSEUDO_REGISTER
1335: || (reg_n_sets[regno] == 1 && ! added_sets_2
1336: && ! REG_USERVAR_P (SET_DEST (newpat))))
1337: {
1338: if (regno >= FIRST_PSEUDO_REGISTER)
1339: SUBST (regno_reg_rtx[regno], new_dest);
1340:
1341: SUBST (SET_DEST (newpat), new_dest);
1342: SUBST (XEXP (*cc_use, 0), new_dest);
1343: SUBST (SET_SRC (newpat),
1344: gen_rtx_combine (COMPARE, compare_mode,
1345: i2src, const0_rtx));
1346: }
1347: else
1348: undobuf.other_insn = 0;
1349: }
1350: #endif
1351: }
1352: else
1353: #endif
1354: {
1355: n_occurrences = 0; /* `subst' counts here */
1356:
1357: /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1358: need to make a unique copy of I2SRC each time we substitute it
1359: to avoid self-referential rtl. */
1360:
1.1.1.4 ! root 1361: subst_low_cuid = INSN_CUID (i2);
1.1 root 1362: newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1363: ! i1_feeds_i3 && i1dest_in_i1src);
1364: previous_num_undos = undobuf.num_undo;
1365:
1366: /* Record whether i2's body now appears within i3's body. */
1367: i2_is_used = n_occurrences;
1368: }
1369:
1370: /* If we already got a failure, don't try to do more. Otherwise,
1371: try to substitute in I1 if we have it. */
1372:
1373: if (i1 && GET_CODE (newpat) != CLOBBER)
1374: {
1375: /* Before we can do this substitution, we must redo the test done
1376: above (see detailed comments there) that ensures that I1DEST
1377: isn't mentioned in any SETs in NEWPAT that are field assignments. */
1378:
1.1.1.4 ! root 1379: if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
! 1380: 0, NULL_PTR))
1.1 root 1381: {
1382: undo_all ();
1383: return 0;
1384: }
1385:
1386: n_occurrences = 0;
1.1.1.4 ! root 1387: subst_low_cuid = INSN_CUID (i1);
1.1 root 1388: newpat = subst (newpat, i1dest, i1src, 0, 0);
1389: previous_num_undos = undobuf.num_undo;
1390: }
1391:
1.1.1.3 root 1392: /* Fail if an autoincrement side-effect has been duplicated. Be careful
1393: to count all the ways that I2SRC and I1SRC can be used. */
1.1.1.4 ! root 1394: if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1.1.1.3 root 1395: && i2_is_used + added_sets_2 > 1)
1.1.1.4 ! root 1396: || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1.1.1.3 root 1397: && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1398: > 1))
1.1 root 1399: /* Fail if we tried to make a new register (we used to abort, but there's
1400: really no reason to). */
1401: || max_reg_num () != maxreg
1402: /* Fail if we couldn't do something and have a CLOBBER. */
1403: || GET_CODE (newpat) == CLOBBER)
1404: {
1405: undo_all ();
1406: return 0;
1407: }
1408:
1409: /* If the actions of the earlier insns must be kept
1410: in addition to substituting them into the latest one,
1411: we must make a new PARALLEL for the latest insn
1412: to hold additional the SETs. */
1413:
1414: if (added_sets_1 || added_sets_2)
1415: {
1416: combine_extras++;
1417:
1418: if (GET_CODE (newpat) == PARALLEL)
1419: {
1420: rtvec old = XVEC (newpat, 0);
1421: total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1422: newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1423: bcopy (&old->elem[0], &XVECEXP (newpat, 0, 0),
1424: sizeof (old->elem[0]) * old->num_elem);
1425: }
1426: else
1427: {
1428: rtx old = newpat;
1429: total_sets = 1 + added_sets_1 + added_sets_2;
1430: newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1431: XVECEXP (newpat, 0, 0) = old;
1432: }
1433:
1434: if (added_sets_1)
1435: XVECEXP (newpat, 0, --total_sets)
1436: = (GET_CODE (PATTERN (i1)) == PARALLEL
1437: ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1438:
1439: if (added_sets_2)
1440: {
1441: /* If there is no I1, use I2's body as is. We used to also not do
1442: the subst call below if I2 was substituted into I3,
1443: but that could lose a simplification. */
1444: if (i1 == 0)
1445: XVECEXP (newpat, 0, --total_sets) = i2pat;
1446: else
1447: /* See comment where i2pat is assigned. */
1448: XVECEXP (newpat, 0, --total_sets)
1449: = subst (i2pat, i1dest, i1src, 0, 0);
1450: }
1451: }
1452:
1453: /* We come here when we are replacing a destination in I2 with the
1454: destination of I3. */
1455: validate_replacement:
1456:
1457: /* Is the result of combination a valid instruction? */
1458: insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1459:
1460: /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1461: the second SET's destination is a register that is unused. In that case,
1462: we just need the first SET. This can occur when simplifying a divmod
1463: insn. We *must* test for this case here because the code below that
1464: splits two independent SETs doesn't handle this case correctly when it
1465: updates the register status. Also check the case where the first
1466: SET's destination is unused. That would not cause incorrect code, but
1467: does cause an unneeded insn to remain. */
1468:
1469: if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1470: && XVECLEN (newpat, 0) == 2
1471: && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1472: && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1473: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1474: && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1475: && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1476: && asm_noperands (newpat) < 0)
1477: {
1478: newpat = XVECEXP (newpat, 0, 0);
1479: insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1480: }
1481:
1482: else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1483: && XVECLEN (newpat, 0) == 2
1484: && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1485: && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1486: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1487: && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1488: && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1489: && asm_noperands (newpat) < 0)
1490: {
1491: newpat = XVECEXP (newpat, 0, 1);
1492: insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1493: }
1494:
1.1.1.4 ! root 1495: /* See if this is an XOR. If so, perhaps the problem is that the
! 1496: constant is out of range. Replace it with a complemented XOR with
! 1497: a complemented constant; it might be in range. */
! 1498:
! 1499: else if (insn_code_number < 0 && GET_CODE (newpat) == SET
! 1500: && GET_CODE (SET_SRC (newpat)) == XOR
! 1501: && GET_CODE (XEXP (SET_SRC (newpat), 1)) == CONST_INT
! 1502: && ((temp = simplify_unary_operation (NOT,
! 1503: GET_MODE (SET_SRC (newpat)),
! 1504: XEXP (SET_SRC (newpat), 1),
! 1505: GET_MODE (SET_SRC (newpat))))
! 1506: != 0))
! 1507: {
! 1508: enum machine_mode i_mode = GET_MODE (SET_SRC (newpat));
! 1509: rtx pat
! 1510: = gen_rtx_combine (SET, VOIDmode, SET_DEST (newpat),
! 1511: gen_unary (NOT, i_mode,
! 1512: gen_binary (XOR, i_mode,
! 1513: XEXP (SET_SRC (newpat), 0),
! 1514: temp)));
! 1515:
! 1516: insn_code_number = recog_for_combine (&pat, i3, &new_i3_notes);
! 1517: if (insn_code_number >= 0)
! 1518: newpat = pat;
! 1519: }
! 1520:
1.1 root 1521: /* If we were combining three insns and the result is a simple SET
1522: with no ASM_OPERANDS that wasn't recognized, try to split it into two
1.1.1.3 root 1523: insns. There are two ways to do this. It can be split using a
1524: machine-specific method (like when you have an addition of a large
1525: constant) or by combine in the function find_split_point. */
1526:
1.1 root 1527: if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1528: && asm_noperands (newpat) < 0)
1529: {
1.1.1.3 root 1530: rtx m_split, *split;
1.1.1.4 ! root 1531: rtx ni2dest = i2dest;
1.1.1.3 root 1532:
1533: /* See if the MD file can split NEWPAT. If it can't, see if letting it
1.1.1.4 ! root 1534: use I2DEST as a scratch register will help. In the latter case,
! 1535: convert I2DEST to the mode of the source of NEWPAT if we can. */
1.1.1.3 root 1536:
1537: m_split = split_insns (newpat, i3);
1.1.1.4 ! root 1538:
! 1539: /* We can only use I2DEST as a scratch reg if it doesn't overlap any
! 1540: inputs of NEWPAT. */
! 1541:
! 1542: /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
! 1543: possible to try that as a scratch reg. This would require adding
! 1544: more code to make it work though. */
! 1545:
! 1546: if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
! 1547: {
! 1548: /* If I2DEST is a hard register or the only use of a pseudo,
! 1549: we can change its mode. */
! 1550: if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
! 1551: && GET_MODE (SET_DEST (newpat)) != VOIDmode
! 1552: && GET_CODE (i2dest) == REG
! 1553: && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
! 1554: || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
! 1555: && ! REG_USERVAR_P (i2dest))))
! 1556: ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)),
! 1557: REGNO (i2dest));
! 1558:
! 1559: m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
! 1560: gen_rtvec (2, newpat,
! 1561: gen_rtx (CLOBBER,
! 1562: VOIDmode,
! 1563: ni2dest))),
! 1564: i3);
! 1565: }
1.1.1.3 root 1566:
1567: if (m_split && GET_CODE (m_split) == SEQUENCE
1568: && XVECLEN (m_split, 0) == 2
1569: && (next_real_insn (i2) == i3
1570: || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1571: INSN_CUID (i2))))
1572: {
1.1.1.4 ! root 1573: rtx i2set, i3set;
! 1574: rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1.1.1.3 root 1575: newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1.1.1.4 ! root 1576:
! 1577: i3set = single_set (XVECEXP (m_split, 0, 1));
! 1578: i2set = single_set (XVECEXP (m_split, 0, 0));
! 1579:
! 1580: /* In case we changed the mode of I2DEST, replace it in the
! 1581: pseudo-register table here. We can't do it above in case this
! 1582: code doesn't get executed and we do a split the other way. */
! 1583:
! 1584: if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
! 1585: SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1.1.1.3 root 1586:
1587: i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1.1.1.4 ! root 1588:
! 1589: /* If I2 or I3 has multiple SETs, we won't know how to track
! 1590: register status, so don't use these insns. */
! 1591:
! 1592: if (i2_code_number >= 0 && i2set && i3set)
! 1593: insn_code_number = recog_for_combine (&newi3pat, i3,
! 1594: &new_i3_notes);
! 1595:
! 1596: if (insn_code_number >= 0)
! 1597: newpat = newi3pat;
! 1598:
! 1599: /* It is possible that both insns now set the destination of I3.
! 1600: If so, we must show an extra use of it. */
! 1601:
! 1602: if (insn_code_number >= 0 && GET_CODE (SET_DEST (i3set)) == REG
! 1603: && GET_CODE (SET_DEST (i2set)) == REG
! 1604: && REGNO (SET_DEST (i3set)) == REGNO (SET_DEST (i2set)))
! 1605: reg_n_sets[REGNO (SET_DEST (i2set))]++;
1.1.1.3 root 1606: }
1.1 root 1607:
1608: /* If we can split it and use I2DEST, go ahead and see if that
1609: helps things be recognized. Verify that none of the registers
1610: are set between I2 and I3. */
1.1.1.4 ! root 1611: if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1.1 root 1612: #ifdef HAVE_cc0
1613: && GET_CODE (i2dest) == REG
1614: #endif
1615: /* We need I2DEST in the proper mode. If it is a hard register
1616: or the only use of a pseudo, we can change its mode. */
1617: && (GET_MODE (*split) == GET_MODE (i2dest)
1618: || GET_MODE (*split) == VOIDmode
1619: || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1620: || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1621: && ! REG_USERVAR_P (i2dest)))
1622: && (next_real_insn (i2) == i3
1623: || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1624: /* We can't overwrite I2DEST if its value is still used by
1625: NEWPAT. */
1626: && ! reg_referenced_p (i2dest, newpat))
1627: {
1628: rtx newdest = i2dest;
1629:
1630: /* Get NEWDEST as a register in the proper mode. We have already
1631: validated that we can do this. */
1632: if (GET_MODE (i2dest) != GET_MODE (*split)
1633: && GET_MODE (*split) != VOIDmode)
1634: {
1635: newdest = gen_rtx (REG, GET_MODE (*split), REGNO (i2dest));
1636:
1637: if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1638: SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1639: }
1640:
1641: /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1642: an ASHIFT. This can occur if it was inside a PLUS and hence
1643: appeared to be a memory address. This is a kludge. */
1644: if (GET_CODE (*split) == MULT
1645: && GET_CODE (XEXP (*split, 1)) == CONST_INT
1646: && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1647: SUBST (*split, gen_rtx_combine (ASHIFT, GET_MODE (*split),
1.1.1.4 ! root 1648: XEXP (*split, 0), GEN_INT (i)));
1.1 root 1649:
1650: #ifdef INSN_SCHEDULING
1651: /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1652: be written as a ZERO_EXTEND. */
1653: if (GET_CODE (*split) == SUBREG
1654: && GET_CODE (SUBREG_REG (*split)) == MEM)
1655: SUBST (*split, gen_rtx_combine (ZERO_EXTEND, GET_MODE (*split),
1656: XEXP (*split, 0)));
1657: #endif
1658:
1659: newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1660: SUBST (*split, newdest);
1661: i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1662: if (i2_code_number >= 0)
1663: insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1664: }
1665: }
1666:
1667: /* Check for a case where we loaded from memory in a narrow mode and
1668: then sign extended it, but we need both registers. In that case,
1669: we have a PARALLEL with both loads from the same memory location.
1670: We can split this into a load from memory followed by a register-register
1671: copy. This saves at least one insn, more if register allocation can
1672: eliminate the copy. */
1673:
1674: else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1675: && GET_CODE (newpat) == PARALLEL
1676: && XVECLEN (newpat, 0) == 2
1677: && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1678: && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1679: && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1680: && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1681: XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1682: && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1683: INSN_CUID (i2))
1684: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1685: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1686: && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1687: SET_SRC (XVECEXP (newpat, 0, 1)))
1688: && ! find_reg_note (i3, REG_UNUSED,
1689: SET_DEST (XVECEXP (newpat, 0, 0))))
1690: {
1.1.1.4 ! root 1691: rtx ni2dest;
! 1692:
1.1 root 1693: newi2pat = XVECEXP (newpat, 0, 0);
1.1.1.4 ! root 1694: ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
1.1 root 1695: newpat = XVECEXP (newpat, 0, 1);
1696: SUBST (SET_SRC (newpat),
1.1.1.4 ! root 1697: gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
1.1 root 1698: i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1699: if (i2_code_number >= 0)
1700: insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1.1.1.2 root 1701:
1702: if (insn_code_number >= 0)
1703: {
1704: rtx insn;
1705: rtx link;
1706:
1707: /* If we will be able to accept this, we have made a change to the
1708: destination of I3. This can invalidate a LOG_LINKS pointing
1709: to I3. No other part of combine.c makes such a transformation.
1710:
1711: The new I3 will have a destination that was previously the
1712: destination of I1 or I2 and which was used in i2 or I3. Call
1713: distribute_links to make a LOG_LINK from the next use of
1714: that destination. */
1715:
1716: PATTERN (i3) = newpat;
1.1.1.4 ! root 1717: distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, NULL_RTX));
1.1.1.2 root 1718:
1719: /* I3 now uses what used to be its destination and which is
1720: now I2's destination. That means we need a LOG_LINK from
1721: I3 to I2. But we used to have one, so we still will.
1722:
1723: However, some later insn might be using I2's dest and have
1724: a LOG_LINK pointing at I3. We must remove this link.
1725: The simplest way to remove the link is to point it at I1,
1726: which we know will be a NOTE. */
1727:
1728: for (insn = NEXT_INSN (i3);
1729: insn && GET_CODE (insn) != CODE_LABEL
1730: && GET_CODE (PREV_INSN (insn)) != JUMP_INSN;
1731: insn = NEXT_INSN (insn))
1732: {
1733: if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1.1.1.4 ! root 1734: && reg_referenced_p (ni2dest, PATTERN (insn)))
1.1.1.2 root 1735: {
1736: for (link = LOG_LINKS (insn); link;
1737: link = XEXP (link, 1))
1738: if (XEXP (link, 0) == i3)
1739: XEXP (link, 0) = i1;
1740:
1741: break;
1742: }
1743: }
1744: }
1.1 root 1745: }
1746:
1747: /* Similarly, check for a case where we have a PARALLEL of two independent
1748: SETs but we started with three insns. In this case, we can do the sets
1749: as two separate insns. This case occurs when some SET allows two
1750: other insns to combine, but the destination of that SET is still live. */
1751:
1752: else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1753: && GET_CODE (newpat) == PARALLEL
1754: && XVECLEN (newpat, 0) == 2
1755: && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1756: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
1757: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
1758: && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1759: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1760: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1761: && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1762: INSN_CUID (i2))
1763: /* Don't pass sets with (USE (MEM ...)) dests to the following. */
1764: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
1765: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
1766: && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1767: XVECEXP (newpat, 0, 0))
1768: && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
1769: XVECEXP (newpat, 0, 1)))
1770: {
1771: newi2pat = XVECEXP (newpat, 0, 1);
1772: newpat = XVECEXP (newpat, 0, 0);
1773:
1774: i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1775: if (i2_code_number >= 0)
1776: insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1777: }
1778:
1779: /* If it still isn't recognized, fail and change things back the way they
1780: were. */
1781: if ((insn_code_number < 0
1782: /* Is the result a reasonable ASM_OPERANDS? */
1783: && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
1784: {
1785: undo_all ();
1786: return 0;
1787: }
1788:
1789: /* If we had to change another insn, make sure it is valid also. */
1790: if (undobuf.other_insn)
1791: {
1792: rtx other_notes = REG_NOTES (undobuf.other_insn);
1793: rtx other_pat = PATTERN (undobuf.other_insn);
1794: rtx new_other_notes;
1795: rtx note, next;
1796:
1797: other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
1798: &new_other_notes);
1799:
1800: if (other_code_number < 0 && ! check_asm_operands (other_pat))
1801: {
1802: undo_all ();
1803: return 0;
1804: }
1805:
1806: PATTERN (undobuf.other_insn) = other_pat;
1807:
1808: /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
1809: are still valid. Then add any non-duplicate notes added by
1810: recog_for_combine. */
1811: for (note = REG_NOTES (undobuf.other_insn); note; note = next)
1812: {
1813: next = XEXP (note, 1);
1814:
1815: if (REG_NOTE_KIND (note) == REG_UNUSED
1816: && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
1.1.1.4 ! root 1817: {
! 1818: if (GET_CODE (XEXP (note, 0)) == REG)
! 1819: reg_n_deaths[REGNO (XEXP (note, 0))]--;
! 1820:
! 1821: remove_note (undobuf.other_insn, note);
! 1822: }
1.1 root 1823: }
1824:
1.1.1.4 ! root 1825: for (note = new_other_notes; note; note = XEXP (note, 1))
! 1826: if (GET_CODE (XEXP (note, 0)) == REG)
! 1827: reg_n_deaths[REGNO (XEXP (note, 0))]++;
! 1828:
1.1 root 1829: distribute_notes (new_other_notes, undobuf.other_insn,
1.1.1.4 ! root 1830: undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
1.1 root 1831: }
1832:
1833: /* We now know that we can do this combination. Merge the insns and
1834: update the status of registers and LOG_LINKS. */
1835:
1836: {
1837: rtx i3notes, i2notes, i1notes = 0;
1838: rtx i3links, i2links, i1links = 0;
1839: rtx midnotes = 0;
1840: int all_adjacent = (next_real_insn (i2) == i3
1841: && (i1 == 0 || next_real_insn (i1) == i2));
1842: register int regno;
1843: /* Compute which registers we expect to eliminate. */
1844: rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
1845: ? 0 : i2dest);
1846: rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
1847:
1848: /* Get the old REG_NOTES and LOG_LINKS from all our insns and
1849: clear them. */
1850: i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
1851: i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
1852: if (i1)
1853: i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
1854:
1855: /* Ensure that we do not have something that should not be shared but
1856: occurs multiple times in the new insns. Check this by first
1.1.1.2 root 1857: resetting all the `used' flags and then copying anything is shared. */
1.1 root 1858:
1859: reset_used_flags (i3notes);
1860: reset_used_flags (i2notes);
1861: reset_used_flags (i1notes);
1862: reset_used_flags (newpat);
1863: reset_used_flags (newi2pat);
1864: if (undobuf.other_insn)
1865: reset_used_flags (PATTERN (undobuf.other_insn));
1866:
1867: i3notes = copy_rtx_if_shared (i3notes);
1868: i2notes = copy_rtx_if_shared (i2notes);
1869: i1notes = copy_rtx_if_shared (i1notes);
1870: newpat = copy_rtx_if_shared (newpat);
1871: newi2pat = copy_rtx_if_shared (newi2pat);
1872: if (undobuf.other_insn)
1873: reset_used_flags (PATTERN (undobuf.other_insn));
1874:
1875: INSN_CODE (i3) = insn_code_number;
1876: PATTERN (i3) = newpat;
1877: if (undobuf.other_insn)
1878: INSN_CODE (undobuf.other_insn) = other_code_number;
1879:
1880: /* We had one special case above where I2 had more than one set and
1881: we replaced a destination of one of those sets with the destination
1882: of I3. In that case, we have to update LOG_LINKS of insns later
1883: in this basic block. Note that this (expensive) case is rare. */
1884:
1885: if (GET_CODE (PATTERN (i2)) == PARALLEL)
1886: for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
1887: if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
1888: && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
1889: && ! find_reg_note (i2, REG_UNUSED,
1890: SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
1891: {
1892: register rtx insn;
1893:
1894: for (insn = NEXT_INSN (i2); insn; insn = NEXT_INSN (insn))
1895: {
1896: if (insn != i3 && GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1897: for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1898: if (XEXP (link, 0) == i2)
1899: XEXP (link, 0) = i3;
1900:
1901: if (GET_CODE (insn) == CODE_LABEL
1902: || GET_CODE (insn) == JUMP_INSN)
1903: break;
1904: }
1905: }
1906:
1907: LOG_LINKS (i3) = 0;
1908: REG_NOTES (i3) = 0;
1909: LOG_LINKS (i2) = 0;
1910: REG_NOTES (i2) = 0;
1911:
1912: if (newi2pat)
1913: {
1914: INSN_CODE (i2) = i2_code_number;
1915: PATTERN (i2) = newi2pat;
1916: }
1917: else
1918: {
1919: PUT_CODE (i2, NOTE);
1920: NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
1921: NOTE_SOURCE_FILE (i2) = 0;
1922: }
1923:
1924: if (i1)
1925: {
1926: LOG_LINKS (i1) = 0;
1927: REG_NOTES (i1) = 0;
1928: PUT_CODE (i1, NOTE);
1929: NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
1930: NOTE_SOURCE_FILE (i1) = 0;
1931: }
1932:
1933: /* Get death notes for everything that is now used in either I3 or
1934: I2 and used to die in a previous insn. */
1935:
1936: move_deaths (newpat, i1 ? INSN_CUID (i1) : INSN_CUID (i2), i3, &midnotes);
1937: if (newi2pat)
1938: move_deaths (newi2pat, INSN_CUID (i1), i2, &midnotes);
1939:
1940: /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
1941: if (i3notes)
1.1.1.4 ! root 1942: distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
! 1943: elim_i2, elim_i1);
1.1 root 1944: if (i2notes)
1.1.1.4 ! root 1945: distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
! 1946: elim_i2, elim_i1);
1.1 root 1947: if (i1notes)
1.1.1.4 ! root 1948: distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
! 1949: elim_i2, elim_i1);
1.1 root 1950: if (midnotes)
1.1.1.4 ! root 1951: distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
! 1952: elim_i2, elim_i1);
1.1 root 1953:
1954: /* Distribute any notes added to I2 or I3 by recog_for_combine. We
1955: know these are REG_UNUSED and want them to go to the desired insn,
1.1.1.4 ! root 1956: so we always pass it as i3. We have not counted the notes in
! 1957: reg_n_deaths yet, so we need to do so now. */
! 1958:
1.1 root 1959: if (newi2pat && new_i2_notes)
1.1.1.4 ! root 1960: {
! 1961: for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
! 1962: if (GET_CODE (XEXP (temp, 0)) == REG)
! 1963: reg_n_deaths[REGNO (XEXP (temp, 0))]++;
! 1964:
! 1965: distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
! 1966: }
! 1967:
1.1 root 1968: if (new_i3_notes)
1.1.1.4 ! root 1969: {
! 1970: for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
! 1971: if (GET_CODE (XEXP (temp, 0)) == REG)
! 1972: reg_n_deaths[REGNO (XEXP (temp, 0))]++;
! 1973:
! 1974: distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
! 1975: }
1.1 root 1976:
1977: /* If I3DEST was used in I3SRC, it really died in I3. We may need to
1.1.1.4 ! root 1978: put a REG_DEAD note for it somewhere. Similarly for I2 and I1.
! 1979: Show an additional death due to the REG_DEAD note we make here. If
! 1980: we discard it in distribute_notes, we will decrement it again. */
! 1981:
1.1 root 1982: if (i3dest_killed)
1.1.1.4 ! root 1983: {
! 1984: if (GET_CODE (i3dest_killed) == REG)
! 1985: reg_n_deaths[REGNO (i3dest_killed)]++;
! 1986:
! 1987: distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
! 1988: NULL_RTX),
! 1989: NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
! 1990: NULL_RTX, NULL_RTX);
! 1991: }
! 1992:
! 1993: /* For I2 and I1, we have to be careful. If NEWI2PAT exists and sets
! 1994: I2DEST or I1DEST, the death must be somewhere before I2, not I3. If
! 1995: we passed I3 in that case, it might delete I2. */
! 1996:
1.1 root 1997: if (i2dest_in_i2src)
1.1.1.4 ! root 1998: {
! 1999: if (GET_CODE (i2dest) == REG)
! 2000: reg_n_deaths[REGNO (i2dest)]++;
! 2001:
! 2002: if (newi2pat && reg_set_p (i2dest, newi2pat))
! 2003: distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
! 2004: NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
! 2005: else
! 2006: distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
! 2007: NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
! 2008: NULL_RTX, NULL_RTX);
! 2009: }
! 2010:
1.1 root 2011: if (i1dest_in_i1src)
1.1.1.4 ! root 2012: {
! 2013: if (GET_CODE (i1dest) == REG)
! 2014: reg_n_deaths[REGNO (i1dest)]++;
! 2015:
! 2016: if (newi2pat && reg_set_p (i1dest, newi2pat))
! 2017: distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
! 2018: NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
! 2019: else
! 2020: distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
! 2021: NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
! 2022: NULL_RTX, NULL_RTX);
! 2023: }
1.1 root 2024:
2025: distribute_links (i3links);
2026: distribute_links (i2links);
2027: distribute_links (i1links);
2028:
2029: if (GET_CODE (i2dest) == REG)
2030: {
1.1.1.4 ! root 2031: rtx link;
! 2032: rtx i2_insn = 0, i2_val = 0, set;
! 2033:
! 2034: /* The insn that used to set this register doesn't exist, and
! 2035: this life of the register may not exist either. See if one of
! 2036: I3's links points to an insn that sets I2DEST. If it does,
! 2037: that is now the last known value for I2DEST. If we don't update
! 2038: this and I2 set the register to a value that depended on its old
1.1 root 2039: contents, we will get confused. If this insn is used, thing
2040: will be set correctly in combine_instructions. */
1.1.1.4 ! root 2041:
! 2042: for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
! 2043: if ((set = single_set (XEXP (link, 0))) != 0
! 2044: && rtx_equal_p (i2dest, SET_DEST (set)))
! 2045: i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
! 2046:
! 2047: record_value_for_reg (i2dest, i2_insn, i2_val);
1.1 root 2048:
2049: /* If the reg formerly set in I2 died only once and that was in I3,
2050: zero its use count so it won't make `reload' do any work. */
2051: if (! added_sets_2 && newi2pat == 0)
2052: {
2053: regno = REGNO (i2dest);
2054: reg_n_sets[regno]--;
2055: if (reg_n_sets[regno] == 0
1.1.1.4 ! root 2056: && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
! 2057: & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
1.1 root 2058: reg_n_refs[regno] = 0;
2059: }
2060: }
2061:
2062: if (i1 && GET_CODE (i1dest) == REG)
2063: {
1.1.1.4 ! root 2064: rtx link;
! 2065: rtx i1_insn = 0, i1_val = 0, set;
! 2066:
! 2067: for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
! 2068: if ((set = single_set (XEXP (link, 0))) != 0
! 2069: && rtx_equal_p (i1dest, SET_DEST (set)))
! 2070: i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
! 2071:
! 2072: record_value_for_reg (i1dest, i1_insn, i1_val);
! 2073:
1.1 root 2074: regno = REGNO (i1dest);
2075: if (! added_sets_1)
2076: {
2077: reg_n_sets[regno]--;
2078: if (reg_n_sets[regno] == 0
1.1.1.4 ! root 2079: && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
! 2080: & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
1.1 root 2081: reg_n_refs[regno] = 0;
2082: }
2083: }
2084:
1.1.1.4 ! root 2085: /* Update reg_significant et al for any changes that may have been made
! 2086: to this insn. */
! 2087:
! 2088: note_stores (newpat, set_significant);
! 2089: if (newi2pat)
! 2090: note_stores (newi2pat, set_significant);
! 2091:
1.1 root 2092: /* If I3 is now an unconditional jump, ensure that it has a
2093: BARRIER following it since it may have initially been a
1.1.1.4 ! root 2094: conditional jump. It may also be the last nonnote insn. */
1.1 root 2095:
2096: if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
1.1.1.4 ! root 2097: && ((temp = next_nonnote_insn (i3)) == NULL_RTX
! 2098: || GET_CODE (temp) != BARRIER))
1.1 root 2099: emit_barrier_after (i3);
2100: }
2101:
2102: combine_successes++;
2103:
2104: return newi2pat ? i2 : i3;
2105: }
2106:
2107: /* Undo all the modifications recorded in undobuf. */
2108:
2109: static void
2110: undo_all ()
2111: {
2112: register int i;
2113: if (undobuf.num_undo > MAX_UNDO)
2114: undobuf.num_undo = MAX_UNDO;
2115: for (i = undobuf.num_undo - 1; i >= 0; i--)
1.1.1.4 ! root 2116: {
! 2117: if (undobuf.undo[i].is_int)
! 2118: *undobuf.undo[i].where.i = undobuf.undo[i].old_contents.i;
! 2119: else
! 2120: *undobuf.undo[i].where.rtx = undobuf.undo[i].old_contents.rtx;
! 2121:
! 2122: }
1.1 root 2123:
2124: obfree (undobuf.storage);
2125: undobuf.num_undo = 0;
2126: }
2127:
2128: /* Find the innermost point within the rtx at LOC, possibly LOC itself,
1.1.1.4 ! root 2129: where we have an arithmetic expression and return that point. LOC will
! 2130: be inside INSN.
1.1 root 2131:
2132: try_combine will call this function to see if an insn can be split into
2133: two insns. */
2134:
2135: static rtx *
1.1.1.4 ! root 2136: find_split_point (loc, insn)
1.1 root 2137: rtx *loc;
1.1.1.4 ! root 2138: rtx insn;
1.1 root 2139: {
2140: rtx x = *loc;
2141: enum rtx_code code = GET_CODE (x);
2142: rtx *split;
2143: int len = 0, pos, unsignedp;
2144: rtx inner;
2145:
2146: /* First special-case some codes. */
2147: switch (code)
2148: {
2149: case SUBREG:
2150: #ifdef INSN_SCHEDULING
2151: /* If we are making a paradoxical SUBREG invalid, it becomes a split
2152: point. */
2153: if (GET_CODE (SUBREG_REG (x)) == MEM)
2154: return loc;
2155: #endif
1.1.1.4 ! root 2156: return find_split_point (&SUBREG_REG (x), insn);
1.1 root 2157:
2158: case MEM:
1.1.1.3 root 2159: #ifdef HAVE_lo_sum
1.1 root 2160: /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2161: using LO_SUM and HIGH. */
2162: if (GET_CODE (XEXP (x, 0)) == CONST
2163: || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2164: {
2165: SUBST (XEXP (x, 0),
2166: gen_rtx_combine (LO_SUM, Pmode,
2167: gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2168: XEXP (x, 0)));
2169: return &XEXP (XEXP (x, 0), 0);
2170: }
2171: #endif
2172:
1.1.1.3 root 2173: /* If we have a PLUS whose second operand is a constant and the
2174: address is not valid, perhaps will can split it up using
2175: the machine-specific way to split large constants. We use
2176: the first psuedo-reg (one of the virtual regs) as a placeholder;
2177: it will not remain in the result. */
2178: if (GET_CODE (XEXP (x, 0)) == PLUS
2179: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2180: && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2181: {
2182: rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2183: rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
2184: subst_insn);
2185:
2186: /* This should have produced two insns, each of which sets our
2187: placeholder. If the source of the second is a valid address,
2188: we can make put both sources together and make a split point
2189: in the middle. */
2190:
2191: if (seq && XVECLEN (seq, 0) == 2
2192: && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2193: && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2194: && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2195: && ! reg_mentioned_p (reg,
2196: SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2197: && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2198: && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2199: && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2200: && memory_address_p (GET_MODE (x),
2201: SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2202: {
2203: rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2204: rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2205:
2206: /* Replace the placeholder in SRC2 with SRC1. If we can
2207: find where in SRC2 it was placed, that can become our
2208: split point and we can replace this address with SRC2.
2209: Just try two obvious places. */
2210:
2211: src2 = replace_rtx (src2, reg, src1);
2212: split = 0;
2213: if (XEXP (src2, 0) == src1)
2214: split = &XEXP (src2, 0);
2215: else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2216: && XEXP (XEXP (src2, 0), 0) == src1)
2217: split = &XEXP (XEXP (src2, 0), 0);
2218:
2219: if (split)
2220: {
2221: SUBST (XEXP (x, 0), src2);
2222: return split;
2223: }
2224: }
1.1.1.4 ! root 2225:
! 2226: /* If that didn't work, perhaps the first operand is complex and
! 2227: needs to be computed separately, so make a split point there.
! 2228: This will occur on machines that just support REG + CONST
! 2229: and have a constant moved through some previous computation. */
! 2230:
! 2231: else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
! 2232: && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
! 2233: && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
! 2234: == 'o')))
! 2235: return &XEXP (XEXP (x, 0), 0);
1.1.1.3 root 2236: }
2237: break;
2238:
1.1 root 2239: case SET:
2240: #ifdef HAVE_cc0
2241: /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2242: ZERO_EXTRACT, the most likely reason why this doesn't match is that
2243: we need to put the operand into a register. So split at that
2244: point. */
2245:
2246: if (SET_DEST (x) == cc0_rtx
2247: && GET_CODE (SET_SRC (x)) != COMPARE
2248: && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2249: && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2250: && ! (GET_CODE (SET_SRC (x)) == SUBREG
2251: && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2252: return &SET_SRC (x);
2253: #endif
2254:
2255: /* See if we can split SET_SRC as it stands. */
1.1.1.4 ! root 2256: split = find_split_point (&SET_SRC (x), insn);
1.1 root 2257: if (split && split != &SET_SRC (x))
2258: return split;
2259:
2260: /* See if this is a bitfield assignment with everything constant. If
2261: so, this is an IOR of an AND, so split it into that. */
2262: if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2263: && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
1.1.1.4 ! root 2264: <= HOST_BITS_PER_WIDE_INT)
1.1 root 2265: && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2266: && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2267: && GET_CODE (SET_SRC (x)) == CONST_INT
2268: && ((INTVAL (XEXP (SET_DEST (x), 1))
2269: + INTVAL (XEXP (SET_DEST (x), 2)))
2270: <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2271: && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2272: {
2273: int pos = INTVAL (XEXP (SET_DEST (x), 2));
2274: int len = INTVAL (XEXP (SET_DEST (x), 1));
2275: int src = INTVAL (SET_SRC (x));
2276: rtx dest = XEXP (SET_DEST (x), 0);
2277: enum machine_mode mode = GET_MODE (dest);
1.1.1.4 ! root 2278: unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
1.1 root 2279:
2280: #if BITS_BIG_ENDIAN
2281: pos = GET_MODE_BITSIZE (mode) - len - pos;
2282: #endif
2283:
2284: if (src == mask)
2285: SUBST (SET_SRC (x),
1.1.1.4 ! root 2286: gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
1.1 root 2287: else
2288: SUBST (SET_SRC (x),
2289: gen_binary (IOR, mode,
2290: gen_binary (AND, mode, dest,
1.1.1.4 ! root 2291: GEN_INT (~ (mask << pos)
! 2292: & GET_MODE_MASK (mode))),
! 2293: GEN_INT (src << pos)));
1.1 root 2294:
2295: SUBST (SET_DEST (x), dest);
2296:
1.1.1.4 ! root 2297: split = find_split_point (&SET_SRC (x), insn);
1.1 root 2298: if (split && split != &SET_SRC (x))
2299: return split;
2300: }
2301:
2302: /* Otherwise, see if this is an operation that we can split into two.
2303: If so, try to split that. */
2304: code = GET_CODE (SET_SRC (x));
2305:
2306: switch (code)
2307: {
1.1.1.4 ! root 2308: case AND:
! 2309: /* If we are AND'ing with a large constant that is only a single
! 2310: bit and the result is only being used in a context where we
! 2311: need to know if it is zero or non-zero, replace it with a bit
! 2312: extraction. This will avoid the large constant, which might
! 2313: have taken more than one insn to make. If the constant were
! 2314: not a valid argument to the AND but took only one insn to make,
! 2315: this is no worse, but if it took more than one insn, it will
! 2316: be better. */
! 2317:
! 2318: if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
! 2319: && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
! 2320: && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
! 2321: && GET_CODE (SET_DEST (x)) == REG
! 2322: && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
! 2323: && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
! 2324: && XEXP (*split, 0) == SET_DEST (x)
! 2325: && XEXP (*split, 1) == const0_rtx)
! 2326: {
! 2327: SUBST (SET_SRC (x),
! 2328: make_extraction (GET_MODE (SET_DEST (x)),
! 2329: XEXP (SET_SRC (x), 0),
! 2330: pos, NULL_RTX, 1, 1, 0, 0));
! 2331: return find_split_point (loc, insn);
! 2332: }
! 2333: break;
! 2334:
1.1 root 2335: case SIGN_EXTEND:
2336: inner = XEXP (SET_SRC (x), 0);
2337: pos = 0;
2338: len = GET_MODE_BITSIZE (GET_MODE (inner));
2339: unsignedp = 0;
2340: break;
2341:
2342: case SIGN_EXTRACT:
2343: case ZERO_EXTRACT:
2344: if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2345: && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2346: {
2347: inner = XEXP (SET_SRC (x), 0);
2348: len = INTVAL (XEXP (SET_SRC (x), 1));
2349: pos = INTVAL (XEXP (SET_SRC (x), 2));
2350:
2351: #if BITS_BIG_ENDIAN
2352: pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2353: #endif
2354: unsignedp = (code == ZERO_EXTRACT);
2355: }
2356: break;
2357: }
2358:
2359: if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2360: {
2361: enum machine_mode mode = GET_MODE (SET_SRC (x));
2362:
1.1.1.4 ! root 2363: /* For unsigned, we have a choice of a shift followed by an
! 2364: AND or two shifts. Use two shifts for field sizes where the
! 2365: constant might be too large. We assume here that we can
! 2366: always at least get 8-bit constants in an AND insn, which is
! 2367: true for every current RISC. */
! 2368:
! 2369: if (unsignedp && len <= 8)
1.1 root 2370: {
2371: SUBST (SET_SRC (x),
2372: gen_rtx_combine
2373: (AND, mode,
2374: gen_rtx_combine (LSHIFTRT, mode,
2375: gen_lowpart_for_combine (mode, inner),
1.1.1.4 ! root 2376: GEN_INT (pos)),
! 2377: GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
1.1 root 2378:
1.1.1.4 ! root 2379: split = find_split_point (&SET_SRC (x), insn);
1.1 root 2380: if (split && split != &SET_SRC (x))
2381: return split;
2382: }
2383: else
2384: {
2385: SUBST (SET_SRC (x),
2386: gen_rtx_combine
1.1.1.4 ! root 2387: (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
1.1 root 2388: gen_rtx_combine (ASHIFT, mode,
2389: gen_lowpart_for_combine (mode, inner),
1.1.1.4 ! root 2390: GEN_INT (GET_MODE_BITSIZE (mode)
! 2391: - len - pos)),
! 2392: GEN_INT (GET_MODE_BITSIZE (mode) - len)));
1.1 root 2393:
1.1.1.4 ! root 2394: split = find_split_point (&SET_SRC (x), insn);
1.1 root 2395: if (split && split != &SET_SRC (x))
2396: return split;
2397: }
2398: }
2399:
2400: /* See if this is a simple operation with a constant as the second
2401: operand. It might be that this constant is out of range and hence
2402: could be used as a split point. */
2403: if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2404: || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2405: || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2406: && CONSTANT_P (XEXP (SET_SRC (x), 1))
2407: && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2408: || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2409: && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2410: == 'o'))))
2411: return &XEXP (SET_SRC (x), 1);
2412:
2413: /* Finally, see if this is a simple operation with its first operand
2414: not in a register. The operation might require this operand in a
2415: register, so return it as a split point. We can always do this
2416: because if the first operand were another operation, we would have
2417: already found it as a split point. */
2418: if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2419: || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2420: || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2421: || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2422: && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2423: return &XEXP (SET_SRC (x), 0);
2424:
2425: return 0;
2426:
2427: case AND:
2428: case IOR:
2429: /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2430: it is better to write this as (not (ior A B)) so we can split it.
2431: Similarly for IOR. */
2432: if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2433: {
2434: SUBST (*loc,
2435: gen_rtx_combine (NOT, GET_MODE (x),
2436: gen_rtx_combine (code == IOR ? AND : IOR,
2437: GET_MODE (x),
2438: XEXP (XEXP (x, 0), 0),
2439: XEXP (XEXP (x, 1), 0))));
1.1.1.4 ! root 2440: return find_split_point (loc, insn);
1.1 root 2441: }
2442:
2443: /* Many RISC machines have a large set of logical insns. If the
2444: second operand is a NOT, put it first so we will try to split the
2445: other operand first. */
2446: if (GET_CODE (XEXP (x, 1)) == NOT)
2447: {
2448: rtx tem = XEXP (x, 0);
2449: SUBST (XEXP (x, 0), XEXP (x, 1));
2450: SUBST (XEXP (x, 1), tem);
2451: }
2452: break;
2453: }
2454:
2455: /* Otherwise, select our actions depending on our rtx class. */
2456: switch (GET_RTX_CLASS (code))
2457: {
2458: case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2459: case '3':
1.1.1.4 ! root 2460: split = find_split_point (&XEXP (x, 2), insn);
1.1 root 2461: if (split)
2462: return split;
2463: /* ... fall through ... */
2464: case '2':
2465: case 'c':
2466: case '<':
1.1.1.4 ! root 2467: split = find_split_point (&XEXP (x, 1), insn);
1.1 root 2468: if (split)
2469: return split;
2470: /* ... fall through ... */
2471: case '1':
2472: /* Some machines have (and (shift ...) ...) insns. If X is not
2473: an AND, but XEXP (X, 0) is, use it as our split point. */
2474: if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2475: return &XEXP (x, 0);
2476:
1.1.1.4 ! root 2477: split = find_split_point (&XEXP (x, 0), insn);
1.1 root 2478: if (split)
2479: return split;
2480: return loc;
2481: }
2482:
2483: /* Otherwise, we don't have a split point. */
2484: return 0;
2485: }
2486:
2487: /* Throughout X, replace FROM with TO, and return the result.
2488: The result is TO if X is FROM;
2489: otherwise the result is X, but its contents may have been modified.
2490: If they were modified, a record was made in undobuf so that
2491: undo_all will (among other things) return X to its original state.
2492:
2493: If the number of changes necessary is too much to record to undo,
2494: the excess changes are not made, so the result is invalid.
2495: The changes already made can still be undone.
2496: undobuf.num_undo is incremented for such changes, so by testing that
2497: the caller can tell whether the result is valid.
2498:
2499: `n_occurrences' is incremented each time FROM is replaced.
2500:
2501: IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2502:
1.1.1.2 root 2503: UNIQUE_COPY is non-zero if each substitution must be unique. We do this
1.1 root 2504: by copying if `n_occurrences' is non-zero. */
2505:
2506: static rtx
2507: subst (x, from, to, in_dest, unique_copy)
2508: register rtx x, from, to;
2509: int in_dest;
2510: int unique_copy;
2511: {
2512: register char *fmt;
2513: register int len, i;
2514: register enum rtx_code code = GET_CODE (x), orig_code = code;
2515: rtx temp;
2516: enum machine_mode mode = GET_MODE (x);
2517: enum machine_mode op0_mode = VOIDmode;
2518: rtx other_insn;
2519: rtx *cc_use;
2520: int n_restarts = 0;
2521:
2522: /* FAKE_EXTEND_SAFE_P (MODE, FROM) is 1 if (subreg:MODE FROM 0) is a safe
2523: replacement for (zero_extend:MODE FROM) or (sign_extend:MODE FROM).
2524: If it is 0, that cannot be done. We can now do this for any MEM
2525: because (SUBREG (MEM...)) is guaranteed to cause the MEM to be reloaded.
2526: If not for that, MEM's would very rarely be safe. */
2527:
2528: /* Reject MODEs bigger than a word, because we might not be able
2529: to reference a two-register group starting with an arbitrary register
2530: (and currently gen_lowpart might crash for a SUBREG). */
2531:
2532: #define FAKE_EXTEND_SAFE_P(MODE, FROM) \
2533: (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)
2534:
2535: /* Two expressions are equal if they are identical copies of a shared
2536: RTX or if they are both registers with the same register number
2537: and mode. */
2538:
2539: #define COMBINE_RTX_EQUAL_P(X,Y) \
2540: ((X) == (Y) \
2541: || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2542: && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2543:
2544: if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2545: {
2546: n_occurrences++;
2547: return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2548: }
2549:
2550: /* If X and FROM are the same register but different modes, they will
2551: not have been seen as equal above. However, flow.c will make a
2552: LOG_LINKS entry for that case. If we do nothing, we will try to
2553: rerecognize our original insn and, when it succeeds, we will
2554: delete the feeding insn, which is incorrect.
2555:
2556: So force this insn not to match in this (rare) case. */
2557: if (! in_dest && code == REG && GET_CODE (from) == REG
2558: && REGNO (x) == REGNO (from))
2559: return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2560:
2561: /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2562: of which may contain things that can be combined. */
2563: if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2564: return x;
2565:
2566: /* It is possible to have a subexpression appear twice in the insn.
2567: Suppose that FROM is a register that appears within TO.
2568: Then, after that subexpression has been scanned once by `subst',
2569: the second time it is scanned, TO may be found. If we were
2570: to scan TO here, we would find FROM within it and create a
2571: self-referent rtl structure which is completely wrong. */
2572: if (COMBINE_RTX_EQUAL_P (x, to))
2573: return to;
2574:
2575: len = GET_RTX_LENGTH (code);
2576: fmt = GET_RTX_FORMAT (code);
2577:
2578: /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2579: set up to skip this common case. All other cases where we want to
2580: suppress replacing something inside a SET_SRC are handled via the
2581: IN_DEST operand. */
2582: if (code == SET
2583: && (GET_CODE (SET_DEST (x)) == REG
2584: || GET_CODE (SET_DEST (x)) == CC0
2585: || GET_CODE (SET_DEST (x)) == PC))
2586: fmt = "ie";
2587:
2588: /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a constant. */
2589: if (fmt[0] == 'e')
2590: op0_mode = GET_MODE (XEXP (x, 0));
2591:
2592: for (i = 0; i < len; i++)
2593: {
2594: if (fmt[i] == 'E')
2595: {
2596: register int j;
2597: for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2598: {
2599: register rtx new;
2600: if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
2601: {
2602: new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2603: n_occurrences++;
2604: }
2605: else
2606: {
2607: new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
2608:
2609: /* If this substitution failed, this whole thing fails. */
2610: if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2611: return new;
2612: }
2613:
2614: SUBST (XVECEXP (x, i, j), new);
2615: }
2616: }
2617: else if (fmt[i] == 'e')
2618: {
2619: register rtx new;
2620:
2621: if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
2622: {
2623: new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2624: n_occurrences++;
2625: }
2626: else
2627: /* If we are in a SET_DEST, suppress most cases unless we
2628: have gone inside a MEM, in which case we want to
2629: simplify the address. We assume here that things that
2630: are actually part of the destination have their inner
2631: parts in the first expression. This is true for SUBREG,
2632: STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
2633: things aside from REG and MEM that should appear in a
2634: SET_DEST. */
2635: new = subst (XEXP (x, i), from, to,
2636: (((in_dest
2637: && (code == SUBREG || code == STRICT_LOW_PART
2638: || code == ZERO_EXTRACT))
2639: || code == SET)
2640: && i == 0), unique_copy);
2641:
2642: /* If we found that we will have to reject this combination,
2643: indicate that by returning the CLOBBER ourselves, rather than
2644: an expression containing it. This will speed things up as
2645: well as prevent accidents where two CLOBBERs are considered
2646: to be equal, thus producing an incorrect simplification. */
2647:
2648: if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2649: return new;
2650:
2651: SUBST (XEXP (x, i), new);
2652: }
2653: }
2654:
1.1.1.4 ! root 2655: /* We come back to here if we have replaced the expression with one of
! 2656: a different code and it is likely that further simplification will be
! 2657: possible. */
! 2658:
! 2659: restart:
! 2660:
! 2661: /* If we have restarted more than 4 times, we are probably looping, so
! 2662: give up. */
! 2663: if (++n_restarts > 4)
! 2664: return x;
! 2665:
! 2666: /* If we are restarting at all, it means that we no longer know the
! 2667: original mode of operand 0 (since we have probably changed the
! 2668: form of X). */
! 2669:
! 2670: if (n_restarts > 1)
! 2671: op0_mode = VOIDmode;
! 2672:
! 2673: code = GET_CODE (x);
! 2674:
1.1 root 2675: /* If this is a commutative operation, put a constant last and a complex
2676: expression first. We don't need to do this for comparisons here. */
2677: if (GET_RTX_CLASS (code) == 'c'
2678: && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
2679: || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
2680: && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
2681: || (GET_CODE (XEXP (x, 0)) == SUBREG
2682: && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
2683: && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
2684: {
2685: temp = XEXP (x, 0);
2686: SUBST (XEXP (x, 0), XEXP (x, 1));
2687: SUBST (XEXP (x, 1), temp);
2688: }
2689:
1.1.1.4 ! root 2690: /* If this is a PLUS, MINUS, or MULT, and the first operand is the
! 2691: sign extension of a PLUS with a constant, reverse the order of the sign
! 2692: extension and the addition. Note that this not the same as the original
! 2693: code, but overflow is undefined for signed values. Also note that the
! 2694: PLUS will have been partially moved "inside" the sign-extension, so that
! 2695: the first operand of X will really look like:
! 2696: (ashiftrt (plus (ashift A C4) C5) C4).
! 2697: We convert this to
! 2698: (plus (ashiftrt (ashift A C4) C2) C4)
! 2699: and replace the first operand of X with that expression. Later parts
! 2700: of this function may simplify the expression further.
! 2701:
! 2702: For example, if we start with (mult (sign_extend (plus A C1)) C2),
! 2703: we swap the SIGN_EXTEND and PLUS. Later code will apply the
! 2704: distributive law to produce (plus (mult (sign_extend X) C1) C3).
! 2705:
! 2706: We do this to simplify address expressions. */
! 2707:
! 2708: if ((code == PLUS || code == MINUS || code == MULT)
! 2709: && GET_CODE (XEXP (x, 0)) == ASHIFTRT
! 2710: && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
! 2711: && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
! 2712: && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
! 2713: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
! 2714: && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
! 2715: && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
! 2716: && (temp = simplify_binary_operation (ASHIFTRT, mode,
! 2717: XEXP (XEXP (XEXP (x, 0), 0), 1),
! 2718: XEXP (XEXP (x, 0), 1))) != 0)
! 2719: {
! 2720: rtx new
! 2721: = simplify_shift_const (NULL_RTX, ASHIFT, mode,
! 2722: XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
! 2723: INTVAL (XEXP (XEXP (x, 0), 1)));
! 2724:
! 2725: new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
! 2726: INTVAL (XEXP (XEXP (x, 0), 1)));
! 2727:
! 2728: SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
! 2729: }
! 2730:
! 2731: /* If this is a simple operation applied to an IF_THEN_ELSE, try
! 2732: applying it to the arms of the IF_THEN_ELSE. This often simplifies
! 2733: things. Don't deal with operations that change modes here. */
! 2734:
! 2735: if ((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c')
! 2736: && GET_CODE (XEXP (x, 0)) == IF_THEN_ELSE)
! 2737: {
! 2738: /* Don't do this by using SUBST inside X since we might be messing
! 2739: up a shared expression. */
! 2740: rtx cond = XEXP (XEXP (x, 0), 0);
! 2741: rtx t_arm = subst (gen_binary (code, mode, XEXP (XEXP (x, 0), 1),
! 2742: XEXP (x, 1)),
! 2743: pc_rtx, pc_rtx, 0, 0);
! 2744: rtx f_arm = subst (gen_binary (code, mode, XEXP (XEXP (x, 0), 2),
! 2745: XEXP (x, 1)),
! 2746: pc_rtx, pc_rtx, 0, 0);
! 2747:
! 2748:
! 2749: x = gen_rtx (IF_THEN_ELSE, mode, cond, t_arm, f_arm);
! 2750: goto restart;
! 2751: }
! 2752:
! 2753: else if (GET_RTX_CLASS (code) == '1'
! 2754: && GET_CODE (XEXP (x, 0)) == IF_THEN_ELSE
! 2755: && GET_MODE (XEXP (x, 0)) == mode)
! 2756: {
! 2757: rtx cond = XEXP (XEXP (x, 0), 0);
! 2758: rtx t_arm = subst (gen_unary (code, mode, XEXP (XEXP (x, 0), 1)),
! 2759: pc_rtx, pc_rtx, 0, 0);
! 2760: rtx f_arm = subst (gen_unary (code, mode, XEXP (XEXP (x, 0), 2)),
! 2761: pc_rtx, pc_rtx, 0, 0);
! 2762:
! 2763: x = gen_rtx_combine (IF_THEN_ELSE, mode, cond, t_arm, f_arm);
! 2764: goto restart;
! 2765: }
! 2766:
1.1 root 2767: /* Try to fold this expression in case we have constants that weren't
2768: present before. */
2769: temp = 0;
2770: switch (GET_RTX_CLASS (code))
2771: {
2772: case '1':
2773: temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
2774: break;
2775: case '<':
2776: temp = simplify_relational_operation (code, op0_mode,
2777: XEXP (x, 0), XEXP (x, 1));
1.1.1.4 ! root 2778: #ifdef FLOAT_STORE_FLAG_VALUE
! 2779: if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
! 2780: temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
! 2781: : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
! 2782: #endif
1.1 root 2783: break;
2784: case 'c':
2785: case '2':
2786: temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
2787: break;
2788: case 'b':
2789: case '3':
2790: temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
2791: XEXP (x, 1), XEXP (x, 2));
2792: break;
2793: }
2794:
2795: if (temp)
1.1.1.4 ! root 2796: x = temp, code = GET_CODE (temp);
1.1 root 2797:
2798: /* First see if we can apply the inverse distributive law. */
2799: if (code == PLUS || code == MINUS || code == IOR || code == XOR)
2800: {
2801: x = apply_distributive_law (x);
2802: code = GET_CODE (x);
2803: }
2804:
2805: /* If CODE is an associative operation not otherwise handled, see if we
2806: can associate some operands. This can win if they are constants or
2807: if they are logically related (i.e. (a & b) & a. */
2808: if ((code == PLUS || code == MINUS
2809: || code == MULT || code == AND || code == IOR || code == XOR
2810: || code == DIV || code == UDIV
2811: || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
2812: && GET_MODE_CLASS (mode) == MODE_INT)
2813: {
2814: if (GET_CODE (XEXP (x, 0)) == code)
2815: {
2816: rtx other = XEXP (XEXP (x, 0), 0);
2817: rtx inner_op0 = XEXP (XEXP (x, 0), 1);
2818: rtx inner_op1 = XEXP (x, 1);
2819: rtx inner;
2820:
2821: /* Make sure we pass the constant operand if any as the second
2822: one if this is a commutative operation. */
2823: if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
2824: {
2825: rtx tem = inner_op0;
2826: inner_op0 = inner_op1;
2827: inner_op1 = tem;
2828: }
2829: inner = simplify_binary_operation (code == MINUS ? PLUS
2830: : code == DIV ? MULT
2831: : code == UDIV ? MULT
2832: : code,
2833: mode, inner_op0, inner_op1);
2834:
2835: /* For commutative operations, try the other pair if that one
2836: didn't simplify. */
2837: if (inner == 0 && GET_RTX_CLASS (code) == 'c')
2838: {
2839: other = XEXP (XEXP (x, 0), 1);
2840: inner = simplify_binary_operation (code, mode,
2841: XEXP (XEXP (x, 0), 0),
2842: XEXP (x, 1));
2843: }
2844:
2845: if (inner)
2846: {
2847: x = gen_binary (code, mode, other, inner);
2848: goto restart;
2849:
2850: }
2851: }
2852: }
2853:
2854: /* A little bit of algebraic simplification here. */
2855: switch (code)
2856: {
2857: case MEM:
2858: /* Ensure that our address has any ASHIFTs converted to MULT in case
2859: address-recognizing predicates are called later. */
2860: temp = make_compound_operation (XEXP (x, 0), MEM);
2861: SUBST (XEXP (x, 0), temp);
2862: break;
2863:
2864: case SUBREG:
2865: /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
2866: is paradoxical. If we can't do that safely, then it becomes
2867: something nonsensical so that this combination won't take place. */
2868:
2869: if (GET_CODE (SUBREG_REG (x)) == MEM
2870: && (GET_MODE_SIZE (mode)
2871: <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
2872: {
2873: rtx inner = SUBREG_REG (x);
2874: int endian_offset = 0;
2875: /* Don't change the mode of the MEM
2876: if that would change the meaning of the address. */
2877: if (MEM_VOLATILE_P (SUBREG_REG (x))
2878: || mode_dependent_address_p (XEXP (inner, 0)))
2879: return gen_rtx (CLOBBER, mode, const0_rtx);
2880:
2881: #if BYTES_BIG_ENDIAN
2882: if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
2883: endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
2884: if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
2885: endian_offset -= UNITS_PER_WORD - GET_MODE_SIZE (GET_MODE (inner));
2886: #endif
2887: /* Note if the plus_constant doesn't make a valid address
2888: then this combination won't be accepted. */
2889: x = gen_rtx (MEM, mode,
2890: plus_constant (XEXP (inner, 0),
2891: (SUBREG_WORD (x) * UNITS_PER_WORD
2892: + endian_offset)));
2893: MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
2894: RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
2895: MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
2896: return x;
2897: }
2898:
2899: /* If we are in a SET_DEST, these other cases can't apply. */
2900: if (in_dest)
2901: return x;
2902:
2903: /* Changing mode twice with SUBREG => just change it once,
2904: or not at all if changing back to starting mode. */
2905: if (GET_CODE (SUBREG_REG (x)) == SUBREG)
2906: {
2907: if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
2908: && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
2909: return SUBREG_REG (SUBREG_REG (x));
2910:
2911: SUBST_INT (SUBREG_WORD (x),
2912: SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
2913: SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
2914: }
2915:
2916: /* SUBREG of a hard register => just change the register number
2917: and/or mode. If the hard register is not valid in that mode,
1.1.1.4 ! root 2918: suppress this combination. If the hard register is the stack,
! 2919: frame, or argument pointer, leave this as a SUBREG. */
1.1 root 2920:
2921: if (GET_CODE (SUBREG_REG (x)) == REG
1.1.1.4 ! root 2922: && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
! 2923: && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
! 2924: #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
! 2925: && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
! 2926: #endif
! 2927: && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
1.1 root 2928: {
2929: if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
2930: mode))
2931: return gen_rtx (REG, mode,
2932: REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
2933: else
2934: return gen_rtx (CLOBBER, mode, const0_rtx);
2935: }
2936:
2937: /* For a constant, try to pick up the part we want. Handle a full
1.1.1.3 root 2938: word and low-order part. Only do this if we are narrowing
2939: the constant; if it is being widened, we have no idea what
2940: the extra bits will have been set to. */
1.1 root 2941:
2942: if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
2943: && GET_MODE_SIZE (mode) == UNITS_PER_WORD
1.1.1.3 root 2944: && GET_MODE_SIZE (op0_mode) < UNITS_PER_WORD
1.1 root 2945: && GET_MODE_CLASS (mode) == MODE_INT)
2946: {
2947: temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
1.1.1.4 ! root 2948: 0, op0_mode);
1.1 root 2949: if (temp)
2950: return temp;
2951: }
2952:
1.1.1.3 root 2953: if (CONSTANT_P (SUBREG_REG (x)) && subreg_lowpart_p (x)
2954: && GET_MODE_SIZE (mode) < GET_MODE_SIZE (op0_mode))
1.1 root 2955: return gen_lowpart_for_combine (mode, SUBREG_REG (x));
2956:
2957: /* If we are narrowing the object, we need to see if we can simplify
2958: the expression for the object knowing that we only need the
1.1.1.4 ! root 2959: low-order bits. */
! 2960:
1.1 root 2961: if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
1.1.1.4 ! root 2962: && subreg_lowpart_p (x))
! 2963: return force_to_mode (SUBREG_REG (x), mode, GET_MODE_BITSIZE (mode),
! 2964: NULL_RTX);
1.1 root 2965: break;
2966:
2967: case NOT:
2968: /* (not (plus X -1)) can become (neg X). */
2969: if (GET_CODE (XEXP (x, 0)) == PLUS
2970: && XEXP (XEXP (x, 0), 1) == constm1_rtx)
2971: {
2972: x = gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
2973: goto restart;
2974: }
2975:
2976: /* Similarly, (not (neg X)) is (plus X -1). */
2977: if (GET_CODE (XEXP (x, 0)) == NEG)
2978: {
2979: x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
2980: goto restart;
2981: }
2982:
1.1.1.4 ! root 2983: /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
! 2984: if (GET_CODE (XEXP (x, 0)) == XOR
! 2985: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
! 2986: && (temp = simplify_unary_operation (NOT, mode,
! 2987: XEXP (XEXP (x, 0), 1),
! 2988: mode)) != 0)
! 2989: {
! 2990: SUBST (XEXP (XEXP (x, 0), 1), temp);
! 2991: return XEXP (x, 0);
! 2992: }
! 2993:
1.1 root 2994: /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
2995: other than 1, but that is not valid. We could do a similar
2996: simplification for (not (lshiftrt C X)) where C is just the sign bit,
2997: but this doesn't seem common enough to bother with. */
2998: if (GET_CODE (XEXP (x, 0)) == ASHIFT
2999: && XEXP (XEXP (x, 0), 0) == const1_rtx)
3000: {
3001: x = gen_rtx (ROTATE, mode, gen_unary (NOT, mode, const1_rtx),
3002: XEXP (XEXP (x, 0), 1));
3003: goto restart;
3004: }
3005:
3006: if (GET_CODE (XEXP (x, 0)) == SUBREG
3007: && subreg_lowpart_p (XEXP (x, 0))
3008: && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3009: < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3010: && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3011: && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3012: {
3013: enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3014:
3015: x = gen_rtx (ROTATE, inner_mode,
3016: gen_unary (NOT, inner_mode, const1_rtx),
3017: XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3018: x = gen_lowpart_for_combine (mode, x);
3019: goto restart;
3020: }
3021:
3022: #if STORE_FLAG_VALUE == -1
3023: /* (not (comparison foo bar)) can be done by reversing the comparison
3024: code if valid. */
3025: if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3026: && reversible_comparison_p (XEXP (x, 0)))
3027: return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3028: mode, XEXP (XEXP (x, 0), 0),
3029: XEXP (XEXP (x, 0), 1));
3030: #endif
3031:
3032: /* Apply De Morgan's laws to reduce number of patterns for machines
3033: with negating logical insns (and-not, nand, etc.). If result has
3034: only one NOT, put it first, since that is how the patterns are
3035: coded. */
3036:
3037: if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3038: {
3039: rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3040:
3041: if (GET_CODE (in1) == NOT)
3042: in1 = XEXP (in1, 0);
3043: else
3044: in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3045:
3046: if (GET_CODE (in2) == NOT)
3047: in2 = XEXP (in2, 0);
3048: else if (GET_CODE (in2) == CONST_INT
1.1.1.4 ! root 3049: && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
! 3050: in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
1.1 root 3051: else
3052: in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3053:
3054: if (GET_CODE (in2) == NOT)
3055: {
3056: rtx tem = in2;
3057: in2 = in1; in1 = tem;
3058: }
3059:
3060: x = gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3061: mode, in1, in2);
3062: goto restart;
3063: }
3064: break;
3065:
3066: case NEG:
3067: /* (neg (plus X 1)) can become (not X). */
3068: if (GET_CODE (XEXP (x, 0)) == PLUS
3069: && XEXP (XEXP (x, 0), 1) == const1_rtx)
3070: {
3071: x = gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3072: goto restart;
3073: }
3074:
3075: /* Similarly, (neg (not X)) is (plus X 1). */
3076: if (GET_CODE (XEXP (x, 0)) == NOT)
3077: {
3078: x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), const1_rtx);
3079: goto restart;
3080: }
3081:
3082: /* (neg (minus X Y)) can become (minus Y X). */
3083: if (GET_CODE (XEXP (x, 0)) == MINUS
3084: && (GET_MODE_CLASS (mode) != MODE_FLOAT
3085: /* x-y != -(y-x) with IEEE floating point. */
3086: || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT))
3087: {
3088: x = gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3089: XEXP (XEXP (x, 0), 0));
3090: goto restart;
3091: }
3092:
1.1.1.4 ! root 3093: /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
! 3094: if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
! 3095: && significant_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
! 3096: {
! 3097: x = gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
! 3098: goto restart;
! 3099: }
! 3100:
1.1 root 3101: /* NEG commutes with ASHIFT since it is multiplication. Only do this
3102: if we can then eliminate the NEG (e.g.,
3103: if the operand is a constant). */
3104:
3105: if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3106: {
3107: temp = simplify_unary_operation (NEG, mode,
3108: XEXP (XEXP (x, 0), 0), mode);
3109: if (temp)
3110: {
3111: SUBST (XEXP (XEXP (x, 0), 0), temp);
3112: return XEXP (x, 0);
3113: }
3114: }
3115:
3116: temp = expand_compound_operation (XEXP (x, 0));
3117:
3118: /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3119: replaced by (lshiftrt X C). This will convert
3120: (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3121:
3122: if (GET_CODE (temp) == ASHIFTRT
3123: && GET_CODE (XEXP (temp, 1)) == CONST_INT
3124: && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3125: {
3126: x = simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3127: INTVAL (XEXP (temp, 1)));
3128: goto restart;
3129: }
3130:
3131: /* If X has only a single bit significant, say, bit I, convert
3132: (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3133: MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3134: (sign_extract X 1 Y). But only do this if TEMP isn't a register
3135: or a SUBREG of one since we'd be making the expression more
3136: complex if it was just a register. */
3137:
3138: if (GET_CODE (temp) != REG
3139: && ! (GET_CODE (temp) == SUBREG
3140: && GET_CODE (SUBREG_REG (temp)) == REG)
3141: && (i = exact_log2 (significant_bits (temp, mode))) >= 0)
3142: {
3143: rtx temp1 = simplify_shift_const
1.1.1.4 ! root 3144: (NULL_RTX, ASHIFTRT, mode,
! 3145: simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
1.1 root 3146: GET_MODE_BITSIZE (mode) - 1 - i),
3147: GET_MODE_BITSIZE (mode) - 1 - i);
3148:
3149: /* If all we did was surround TEMP with the two shifts, we
3150: haven't improved anything, so don't use it. Otherwise,
3151: we are better off with TEMP1. */
3152: if (GET_CODE (temp1) != ASHIFTRT
3153: || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3154: || XEXP (XEXP (temp1, 0), 0) != temp)
3155: {
3156: x = temp1;
3157: goto restart;
3158: }
3159: }
3160: break;
3161:
3162: case FLOAT_TRUNCATE:
3163: /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3164: if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3165: && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3166: return XEXP (XEXP (x, 0), 0);
3167: break;
3168:
3169: #ifdef HAVE_cc0
3170: case COMPARE:
3171: /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3172: using cc0, in which case we want to leave it as a COMPARE
3173: so we can distinguish it from a register-register-copy. */
3174: if (XEXP (x, 1) == const0_rtx)
3175: return XEXP (x, 0);
3176:
3177: /* In IEEE floating point, x-0 is not the same as x. */
3178: if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3179: || GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) == MODE_INT)
3180: && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3181: return XEXP (x, 0);
3182: break;
3183: #endif
3184:
3185: case CONST:
3186: /* (const (const X)) can become (const X). Do it this way rather than
3187: returning the inner CONST since CONST can be shared with a
3188: REG_EQUAL note. */
3189: if (GET_CODE (XEXP (x, 0)) == CONST)
3190: SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3191: break;
3192:
3193: #ifdef HAVE_lo_sum
3194: case LO_SUM:
3195: /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3196: can add in an offset. find_split_point will split this address up
3197: again if it doesn't match. */
3198: if (GET_CODE (XEXP (x, 0)) == HIGH
3199: && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3200: return XEXP (x, 1);
3201: break;
3202: #endif
3203:
3204: case PLUS:
3205: /* If we have (plus (plus (A const) B)), associate it so that CONST is
3206: outermost. That's because that's the way indexed addresses are
3207: supposed to appear. This code used to check many more cases, but
3208: they are now checked elsewhere. */
3209: if (GET_CODE (XEXP (x, 0)) == PLUS
3210: && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3211: return gen_binary (PLUS, mode,
3212: gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3213: XEXP (x, 1)),
3214: XEXP (XEXP (x, 0), 1));
3215:
3216: /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3217: when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3218: bit-field and can be replaced by either a sign_extend or a
3219: sign_extract. The `and' may be a zero_extend. */
3220: if (GET_CODE (XEXP (x, 0)) == XOR
3221: && GET_CODE (XEXP (x, 1)) == CONST_INT
3222: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3223: && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3224: && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
1.1.1.4 ! root 3225: && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
1.1 root 3226: && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3227: && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3228: && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
1.1.1.4 ! root 3229: == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
1.1 root 3230: || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3231: && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3232: == i + 1))))
3233: {
3234: x = simplify_shift_const
1.1.1.4 ! root 3235: (NULL_RTX, ASHIFTRT, mode,
! 3236: simplify_shift_const (NULL_RTX, ASHIFT, mode,
1.1 root 3237: XEXP (XEXP (XEXP (x, 0), 0), 0),
3238: GET_MODE_BITSIZE (mode) - (i + 1)),
3239: GET_MODE_BITSIZE (mode) - (i + 1));
3240: goto restart;
3241: }
3242:
3243: /* If only the low-order bit of X is significant, (plus x -1)
3244: can become (ashiftrt (ashift (xor x 1) C) C) where C is
3245: the bitsize of the mode - 1. This allows simplification of
3246: "a = (b & 8) == 0;" */
3247: if (XEXP (x, 1) == constm1_rtx
3248: && GET_CODE (XEXP (x, 0)) != REG
3249: && ! (GET_CODE (XEXP (x,0)) == SUBREG
3250: && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3251: && significant_bits (XEXP (x, 0), mode) == 1)
3252: {
3253: x = simplify_shift_const
1.1.1.4 ! root 3254: (NULL_RTX, ASHIFTRT, mode,
! 3255: simplify_shift_const (NULL_RTX, ASHIFT, mode,
1.1 root 3256: gen_rtx_combine (XOR, mode,
3257: XEXP (x, 0), const1_rtx),
3258: GET_MODE_BITSIZE (mode) - 1),
3259: GET_MODE_BITSIZE (mode) - 1);
3260: goto restart;
3261: }
1.1.1.4 ! root 3262:
! 3263: /* If we are adding two things that have no bits in common, convert
! 3264: the addition into an IOR. This will often be further simplified,
! 3265: for example in cases like ((a & 1) + (a & 2)), which can
! 3266: become a & 3. */
! 3267:
! 3268: if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
! 3269: && (significant_bits (XEXP (x, 0), mode)
! 3270: & significant_bits (XEXP (x, 1), mode)) == 0)
! 3271: {
! 3272: x = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
! 3273: goto restart;
! 3274: }
1.1 root 3275: break;
3276:
3277: case MINUS:
3278: /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3279: (and <foo> (const_int pow2-1)) */
3280: if (GET_CODE (XEXP (x, 1)) == AND
3281: && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3282: && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3283: && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3284: {
1.1.1.4 ! root 3285: x = simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
1.1 root 3286: - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
3287: goto restart;
3288: }
3289: break;
3290:
3291: case MULT:
3292: /* If we have (mult (plus A B) C), apply the distributive law and then
3293: the inverse distributive law to see if things simplify. This
3294: occurs mostly in addresses, often when unrolling loops. */
3295:
3296: if (GET_CODE (XEXP (x, 0)) == PLUS)
3297: {
3298: x = apply_distributive_law
3299: (gen_binary (PLUS, mode,
3300: gen_binary (MULT, mode,
3301: XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3302: gen_binary (MULT, mode,
3303: XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3304:
3305: if (GET_CODE (x) != MULT)
3306: goto restart;
3307: }
3308:
3309: /* If this is multiplication by a power of two and its first operand is
3310: a shift, treat the multiply as a shift to allow the shifts to
3311: possibly combine. */
3312: if (GET_CODE (XEXP (x, 1)) == CONST_INT
3313: && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3314: && (GET_CODE (XEXP (x, 0)) == ASHIFT
3315: || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3316: || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3317: || GET_CODE (XEXP (x, 0)) == ROTATE
3318: || GET_CODE (XEXP (x, 0)) == ROTATERT))
3319: {
1.1.1.4 ! root 3320: x = simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), i);
1.1 root 3321: goto restart;
3322: }
3323:
3324: /* Convert (mult (ashift (const_int 1) A) B) to (ashift B A). */
3325: if (GET_CODE (XEXP (x, 0)) == ASHIFT
3326: && XEXP (XEXP (x, 0), 0) == const1_rtx)
3327: return gen_rtx_combine (ASHIFT, mode, XEXP (x, 1),
3328: XEXP (XEXP (x, 0), 1));
3329: break;
3330:
3331: case UDIV:
3332: /* If this is a divide by a power of two, treat it as a shift if
3333: its first operand is a shift. */
3334: if (GET_CODE (XEXP (x, 1)) == CONST_INT
3335: && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3336: && (GET_CODE (XEXP (x, 0)) == ASHIFT
3337: || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3338: || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3339: || GET_CODE (XEXP (x, 0)) == ROTATE
3340: || GET_CODE (XEXP (x, 0)) == ROTATERT))
3341: {
1.1.1.4 ! root 3342: x = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
1.1 root 3343: goto restart;
3344: }
3345: break;
3346:
3347: case EQ: case NE:
3348: case GT: case GTU: case GE: case GEU:
3349: case LT: case LTU: case LE: case LEU:
3350: /* If the first operand is a condition code, we can't do anything
3351: with it. */
3352: if (GET_CODE (XEXP (x, 0)) == COMPARE
3353: || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3354: #ifdef HAVE_cc0
3355: && XEXP (x, 0) != cc0_rtx
3356: #endif
3357: ))
3358: {
3359: rtx op0 = XEXP (x, 0);
3360: rtx op1 = XEXP (x, 1);
3361: enum rtx_code new_code;
3362:
3363: if (GET_CODE (op0) == COMPARE)
3364: op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3365:
3366: /* Simplify our comparison, if possible. */
3367: new_code = simplify_comparison (code, &op0, &op1);
3368:
3369: #if STORE_FLAG_VALUE == 1
3370: /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3371: if only the low-order bit is significant in X (such as when
3372: X is a ZERO_EXTRACT of one bit. Similarly, we can convert
3373: EQ to (xor X 1). */
1.1.1.3 root 3374: if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
1.1 root 3375: && op1 == const0_rtx
3376: && significant_bits (op0, GET_MODE (op0)) == 1)
3377: return gen_lowpart_for_combine (mode, op0);
1.1.1.3 root 3378: else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
1.1 root 3379: && op1 == const0_rtx
3380: && significant_bits (op0, GET_MODE (op0)) == 1)
3381: return gen_rtx_combine (XOR, mode,
3382: gen_lowpart_for_combine (mode, op0),
3383: const1_rtx);
3384: #endif
3385:
3386: #if STORE_FLAG_VALUE == -1
3387: /* If STORE_FLAG_VALUE is -1, we can convert (ne x 0)
3388: to (neg x) if only the low-order bit of X is significant.
3389: This converts (ne (zero_extract X 1 Y) 0) to
3390: (sign_extract X 1 Y). */
1.1.1.3 root 3391: if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
1.1 root 3392: && op1 == const0_rtx
3393: && significant_bits (op0, GET_MODE (op0)) == 1)
3394: {
3395: x = gen_rtx_combine (NEG, mode,
3396: gen_lowpart_for_combine (mode, op0));
3397: goto restart;
3398: }
3399: #endif
3400:
3401: /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3402: one significant bit, we can convert (ne x 0) to (ashift x c)
3403: where C puts the bit in the sign bit. Remove any AND with
3404: STORE_FLAG_VALUE when we are done, since we are only going to
3405: test the sign bit. */
1.1.1.3 root 3406: if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
1.1.1.4 ! root 3407: && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
! 3408: && (STORE_FLAG_VALUE
! 3409: == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
1.1 root 3410: && op1 == const0_rtx
3411: && mode == GET_MODE (op0)
3412: && (i = exact_log2 (significant_bits (op0, GET_MODE (op0)))) >= 0)
3413: {
1.1.1.4 ! root 3414: x = simplify_shift_const (NULL_RTX, ASHIFT, mode, op0,
1.1 root 3415: GET_MODE_BITSIZE (mode) - 1 - i);
3416: if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
3417: return XEXP (x, 0);
3418: else
3419: return x;
3420: }
3421:
3422: /* If the code changed, return a whole new comparison. */
3423: if (new_code != code)
3424: return gen_rtx_combine (new_code, mode, op0, op1);
3425:
3426: /* Otherwise, keep this operation, but maybe change its operands.
3427: This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
3428: SUBST (XEXP (x, 0), op0);
3429: SUBST (XEXP (x, 1), op1);
3430: }
3431: break;
3432:
3433: case IF_THEN_ELSE:
1.1.1.4 ! root 3434: /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register
! 3435: used in it is being compared against certain values. Get the
! 3436: true and false comparisons and see if that says anything about the
! 3437: value of each arm. */
! 3438:
! 3439: if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
! 3440: && reversible_comparison_p (XEXP (x, 0))
! 3441: && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG)
! 3442: {
! 3443: HOST_WIDE_INT sig;
! 3444: rtx from = XEXP (XEXP (x, 0), 0);
! 3445: enum rtx_code true_code = GET_CODE (XEXP (x, 0));
! 3446: enum rtx_code false_code = reverse_condition (true_code);
! 3447: rtx true_val = XEXP (XEXP (x, 0), 1);
! 3448: rtx false_val = true_val;
! 3449: rtx true_arm = XEXP (x, 1);
! 3450: rtx false_arm = XEXP (x, 2);
! 3451: int swapped = 0;
! 3452:
! 3453: /* If FALSE_CODE is EQ, swap the codes and arms. */
! 3454:
! 3455: if (false_code == EQ)
! 3456: {
! 3457: swapped = 1, true_code = EQ, false_code = NE;
! 3458: true_arm = XEXP (x, 2), false_arm = XEXP (x, 1);
! 3459: }
! 3460:
! 3461: /* If we are comparing against zero and the expression being tested
! 3462: has only a single significant bit, that is its value when it is
! 3463: not equal to zero. Similarly if it is known to be -1 or 0. */
! 3464:
! 3465: if (true_code == EQ && true_val == const0_rtx
! 3466: && exact_log2 (sig = significant_bits (from,
! 3467: GET_MODE (from))) >= 0)
! 3468: false_code = EQ, false_val = GEN_INT (sig);
! 3469: else if (true_code == EQ && true_val == const0_rtx
! 3470: && (num_sign_bit_copies (from, GET_MODE (from))
! 3471: == GET_MODE_BITSIZE (GET_MODE (from))))
! 3472: false_code = EQ, false_val = constm1_rtx;
! 3473:
! 3474: /* Now simplify an arm if we know the value of the register
! 3475: in the branch and it is used in the arm. Be carefull due to
! 3476: the potential of locally-shared RTL. */
! 3477:
! 3478: if (reg_mentioned_p (from, true_arm))
! 3479: true_arm = subst (known_cond (copy_rtx (true_arm), true_code,
! 3480: from, true_val),
! 3481: pc_rtx, pc_rtx, 0, 0);
! 3482: if (reg_mentioned_p (from, false_arm))
! 3483: false_arm = subst (known_cond (copy_rtx (false_arm), false_code,
! 3484: from, false_val),
! 3485: pc_rtx, pc_rtx, 0, 0);
! 3486:
! 3487: SUBST (XEXP (x, 1), swapped ? false_arm : true_arm);
! 3488: SUBST (XEXP (x, 2), swapped ? true_arm : false_arm);
! 3489: }
! 3490:
1.1 root 3491: /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
3492: reversed, do so to avoid needing two sets of patterns for
1.1.1.4 ! root 3493: subtract-and-branch insns. Similarly if we have a constant in that
! 3494: position or if the third operand is the same as the first operand
! 3495: of the comparison. */
! 3496:
! 3497: if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
! 3498: && reversible_comparison_p (XEXP (x, 0))
! 3499: && (XEXP (x, 1) == pc_rtx || GET_CODE (XEXP (x, 1)) == CONST_INT
! 3500: || rtx_equal_p (XEXP (x, 2), XEXP (XEXP (x, 0), 0))))
1.1 root 3501: {
3502: SUBST (XEXP (x, 0),
1.1.1.4 ! root 3503: gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
! 3504: GET_MODE (XEXP (x, 0)),
! 3505: XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 0), 1)));
! 3506:
! 3507: temp = XEXP (x, 1);
1.1 root 3508: SUBST (XEXP (x, 1), XEXP (x, 2));
1.1.1.4 ! root 3509: SUBST (XEXP (x, 2), temp);
! 3510: }
! 3511:
! 3512: /* If the two arms are identical, we don't need the comparison. */
! 3513:
! 3514: if (rtx_equal_p (XEXP (x, 1), XEXP (x, 2))
! 3515: && ! side_effects_p (XEXP (x, 0)))
! 3516: return XEXP (x, 1);
! 3517:
! 3518: /* Look for cases where we have (abs x) or (neg (abs X)). */
! 3519:
! 3520: if (GET_MODE_CLASS (mode) == MODE_INT
! 3521: && GET_CODE (XEXP (x, 2)) == NEG
! 3522: && rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 2), 0))
! 3523: && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
! 3524: && rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 0), 0))
! 3525: && ! side_effects_p (XEXP (x, 1)))
! 3526: switch (GET_CODE (XEXP (x, 0)))
! 3527: {
! 3528: case GT:
! 3529: case GE:
! 3530: x = gen_unary (ABS, mode, XEXP (x, 1));
! 3531: goto restart;
! 3532: case LT:
! 3533: case LE:
! 3534: x = gen_unary (NEG, mode, gen_unary (ABS, mode, XEXP (x, 1)));
! 3535: goto restart;
! 3536: }
! 3537:
! 3538: /* Look for MIN or MAX. */
! 3539:
! 3540: if (GET_MODE_CLASS (mode) == MODE_INT
! 3541: && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
! 3542: && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
! 3543: && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 2))
! 3544: && ! side_effects_p (XEXP (x, 0)))
! 3545: switch (GET_CODE (XEXP (x, 0)))
! 3546: {
! 3547: case GE:
! 3548: case GT:
! 3549: x = gen_binary (SMAX, mode, XEXP (x, 1), XEXP (x, 2));
! 3550: goto restart;
! 3551: case LE:
! 3552: case LT:
! 3553: x = gen_binary (SMIN, mode, XEXP (x, 1), XEXP (x, 2));
! 3554: goto restart;
! 3555: case GEU:
! 3556: case GTU:
! 3557: x = gen_binary (UMAX, mode, XEXP (x, 1), XEXP (x, 2));
! 3558: goto restart;
! 3559: case LEU:
! 3560: case LTU:
! 3561: x = gen_binary (UMIN, mode, XEXP (x, 1), XEXP (x, 2));
! 3562: goto restart;
! 3563: }
! 3564:
! 3565: /* If we have something like (if_then_else (ne A 0) (OP X C) X),
! 3566: A is known to be either 0 or 1, and OP is an identity when its
! 3567: second operand is zero, this can be done as (OP X (mult A C)).
! 3568: Similarly if A is known to be 0 or -1 and also similarly if we have
! 3569: a ZERO_EXTEND or SIGN_EXTEND as long as X is already extended (so
! 3570: we don't destroy it). */
! 3571:
! 3572: if (mode != VOIDmode
! 3573: && (GET_CODE (XEXP (x, 0)) == EQ || GET_CODE (XEXP (x, 0)) == NE)
! 3574: && XEXP (XEXP (x, 0), 1) == const0_rtx
! 3575: && (significant_bits (XEXP (XEXP (x, 0), 0), mode) == 1
! 3576: || (num_sign_bit_copies (XEXP (XEXP (x, 0), 0), mode)
! 3577: == GET_MODE_BITSIZE (mode))))
! 3578: {
! 3579: rtx nz = make_compound_operation (GET_CODE (XEXP (x, 0)) == NE
! 3580: ? XEXP (x, 1) : XEXP (x, 2));
! 3581: rtx z = GET_CODE (XEXP (x, 0)) == NE ? XEXP (x, 2) : XEXP (x, 1);
! 3582: rtx dir = (significant_bits (XEXP (XEXP (x, 0), 0), mode) == 1
! 3583: ? const1_rtx : constm1_rtx);
! 3584: rtx c = 0;
! 3585: enum machine_mode m = mode;
! 3586: enum rtx_code op, extend_op = 0;
! 3587:
! 3588: if ((GET_CODE (nz) == PLUS || GET_CODE (nz) == MINUS
! 3589: || GET_CODE (nz) == IOR || GET_CODE (nz) == XOR
! 3590: || GET_CODE (nz) == ASHIFT
! 3591: || GET_CODE (nz) == LSHIFTRT || GET_CODE (nz) == ASHIFTRT)
! 3592: && rtx_equal_p (XEXP (nz, 0), z))
! 3593: c = XEXP (nz, 1), op = GET_CODE (nz);
! 3594: else if (GET_CODE (nz) == SIGN_EXTEND
! 3595: && (GET_CODE (XEXP (nz, 0)) == PLUS
! 3596: || GET_CODE (XEXP (nz, 0)) == MINUS
! 3597: || GET_CODE (XEXP (nz, 0)) == IOR
! 3598: || GET_CODE (XEXP (nz, 0)) == XOR
! 3599: || GET_CODE (XEXP (nz, 0)) == ASHIFT
! 3600: || GET_CODE (XEXP (nz, 0)) == LSHIFTRT
! 3601: || GET_CODE (XEXP (nz, 0)) == ASHIFTRT)
! 3602: && GET_CODE (XEXP (XEXP (nz, 0), 0)) == SUBREG
! 3603: && subreg_lowpart_p (XEXP (XEXP (nz, 0), 0))
! 3604: && rtx_equal_p (SUBREG_REG (XEXP (XEXP (nz, 0), 0)), z)
! 3605: && (num_sign_bit_copies (z, GET_MODE (z))
! 3606: >= (GET_MODE_BITSIZE (mode)
! 3607: - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (nz, 0), 0))))))
! 3608: {
! 3609: c = XEXP (XEXP (nz, 0), 1);
! 3610: op = GET_CODE (XEXP (nz, 0));
! 3611: extend_op = SIGN_EXTEND;
! 3612: m = GET_MODE (XEXP (nz, 0));
! 3613: }
! 3614: else if (GET_CODE (nz) == ZERO_EXTEND
! 3615: && (GET_CODE (XEXP (nz, 0)) == PLUS
! 3616: || GET_CODE (XEXP (nz, 0)) == MINUS
! 3617: || GET_CODE (XEXP (nz, 0)) == IOR
! 3618: || GET_CODE (XEXP (nz, 0)) == XOR
! 3619: || GET_CODE (XEXP (nz, 0)) == ASHIFT
! 3620: || GET_CODE (XEXP (nz, 0)) == LSHIFTRT
! 3621: || GET_CODE (XEXP (nz, 0)) == ASHIFTRT)
! 3622: && GET_CODE (XEXP (XEXP (nz, 0), 0)) == SUBREG
! 3623: && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
! 3624: && subreg_lowpart_p (XEXP (XEXP (nz, 0), 0))
! 3625: && rtx_equal_p (SUBREG_REG (XEXP (XEXP (nz, 0), 0)), z)
! 3626: && ((significant_bits (z, GET_MODE (z))
! 3627: & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (nz, 0), 0))))
! 3628: == 0))
! 3629: {
! 3630: c = XEXP (XEXP (nz, 0), 1);
! 3631: op = GET_CODE (XEXP (nz, 0));
! 3632: extend_op = ZERO_EXTEND;
! 3633: m = GET_MODE (XEXP (nz, 0));
! 3634: }
! 3635:
! 3636: if (c && ! side_effects_p (c) && ! side_effects_p (z))
! 3637: {
! 3638: temp
! 3639: = gen_binary (MULT, m,
! 3640: gen_lowpart_for_combine (m,
! 3641: XEXP (XEXP (x, 0), 0)),
! 3642: gen_binary (MULT, m, c, dir));
! 3643:
! 3644: temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
! 3645:
! 3646: if (extend_op != 0)
! 3647: temp = gen_unary (extend_op, mode, temp);
! 3648:
! 3649: return temp;
! 3650: }
1.1 root 3651: }
3652: break;
3653:
3654: case ZERO_EXTRACT:
3655: case SIGN_EXTRACT:
3656: case ZERO_EXTEND:
3657: case SIGN_EXTEND:
3658: /* If we are processing SET_DEST, we are done. */
3659: if (in_dest)
3660: return x;
3661:
3662: x = expand_compound_operation (x);
3663: if (GET_CODE (x) != code)
3664: goto restart;
3665: break;
3666:
3667: case SET:
3668: /* (set (pc) (return)) gets written as (return). */
3669: if (GET_CODE (SET_DEST (x)) == PC && GET_CODE (SET_SRC (x)) == RETURN)
3670: return SET_SRC (x);
3671:
3672: /* Convert this into a field assignment operation, if possible. */
3673: x = make_field_assignment (x);
3674:
3675: /* If we are setting CC0 or if the source is a COMPARE, look for the
3676: use of the comparison result and try to simplify it unless we already
3677: have used undobuf.other_insn. */
3678: if ((GET_CODE (SET_SRC (x)) == COMPARE
3679: #ifdef HAVE_cc0
3680: || SET_DEST (x) == cc0_rtx
3681: #endif
3682: )
3683: && (cc_use = find_single_use (SET_DEST (x), subst_insn,
3684: &other_insn)) != 0
3685: && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
3686: && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
3687: && XEXP (*cc_use, 0) == SET_DEST (x))
3688: {
3689: enum rtx_code old_code = GET_CODE (*cc_use);
3690: enum rtx_code new_code;
3691: rtx op0, op1;
3692: int other_changed = 0;
3693: enum machine_mode compare_mode = GET_MODE (SET_DEST (x));
3694:
3695: if (GET_CODE (SET_SRC (x)) == COMPARE)
3696: op0 = XEXP (SET_SRC (x), 0), op1 = XEXP (SET_SRC (x), 1);
3697: else
3698: op0 = SET_SRC (x), op1 = const0_rtx;
3699:
3700: /* Simplify our comparison, if possible. */
3701: new_code = simplify_comparison (old_code, &op0, &op1);
3702:
3703: #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
3704: /* If this machine has CC modes other than CCmode, check to see
3705: if we need to use a different CC mode here. */
1.1.1.4 ! root 3706: compare_mode = SELECT_CC_MODE (new_code, op0, op1);
1.1 root 3707:
3708: /* If the mode changed, we have to change SET_DEST, the mode
3709: in the compare, and the mode in the place SET_DEST is used.
3710: If SET_DEST is a hard register, just build new versions with
3711: the proper mode. If it is a pseudo, we lose unless it is only
3712: time we set the pseudo, in which case we can safely change
3713: its mode. */
3714: if (compare_mode != GET_MODE (SET_DEST (x)))
3715: {
3716: int regno = REGNO (SET_DEST (x));
3717: rtx new_dest = gen_rtx (REG, compare_mode, regno);
3718:
3719: if (regno < FIRST_PSEUDO_REGISTER
3720: || (reg_n_sets[regno] == 1
3721: && ! REG_USERVAR_P (SET_DEST (x))))
3722: {
3723: if (regno >= FIRST_PSEUDO_REGISTER)
3724: SUBST (regno_reg_rtx[regno], new_dest);
3725:
3726: SUBST (SET_DEST (x), new_dest);
3727: SUBST (XEXP (*cc_use, 0), new_dest);
3728: other_changed = 1;
3729: }
3730: }
3731: #endif
3732:
3733: /* If the code changed, we have to build a new comparison
3734: in undobuf.other_insn. */
3735: if (new_code != old_code)
3736: {
3737: unsigned mask;
3738:
3739: SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
3740: SET_DEST (x), const0_rtx));
3741:
3742: /* If the only change we made was to change an EQ into an
3743: NE or vice versa, OP0 has only one significant bit,
3744: and OP1 is zero, check if changing the user of the condition
3745: code will produce a valid insn. If it won't, we can keep
3746: the original code in that insn by surrounding our operation
3747: with an XOR. */
3748:
3749: if (((old_code == NE && new_code == EQ)
3750: || (old_code == EQ && new_code == NE))
3751: && ! other_changed && op1 == const0_rtx
1.1.1.4 ! root 3752: && (GET_MODE_BITSIZE (GET_MODE (op0))
! 3753: <= HOST_BITS_PER_WIDE_INT)
1.1 root 3754: && (exact_log2 (mask = significant_bits (op0,
3755: GET_MODE (op0)))
3756: >= 0))
3757: {
3758: rtx pat = PATTERN (other_insn), note = 0;
3759:
3760: if ((recog_for_combine (&pat, undobuf.other_insn, ¬e) < 0
3761: && ! check_asm_operands (pat)))
3762: {
3763: PUT_CODE (*cc_use, old_code);
3764: other_insn = 0;
3765:
3766: op0 = gen_binary (XOR, GET_MODE (op0), op0,
1.1.1.4 ! root 3767: GEN_INT (mask));
1.1 root 3768: }
3769: }
3770:
3771: other_changed = 1;
3772: }
3773:
3774: if (other_changed)
3775: undobuf.other_insn = other_insn;
3776:
3777: #ifdef HAVE_cc0
3778: /* If we are now comparing against zero, change our source if
3779: needed. If we do not use cc0, we always have a COMPARE. */
3780: if (op1 == const0_rtx && SET_DEST (x) == cc0_rtx)
3781: SUBST (SET_SRC (x), op0);
3782: else
3783: #endif
3784:
3785: /* Otherwise, if we didn't previously have a COMPARE in the
3786: correct mode, we need one. */
3787: if (GET_CODE (SET_SRC (x)) != COMPARE
3788: || GET_MODE (SET_SRC (x)) != compare_mode)
3789: SUBST (SET_SRC (x), gen_rtx_combine (COMPARE, compare_mode,
3790: op0, op1));
3791: else
3792: {
3793: /* Otherwise, update the COMPARE if needed. */
3794: SUBST (XEXP (SET_SRC (x), 0), op0);
3795: SUBST (XEXP (SET_SRC (x), 1), op1);
3796: }
3797: }
3798: else
3799: {
3800: /* Get SET_SRC in a form where we have placed back any
3801: compound expressions. Then do the checks below. */
3802: temp = make_compound_operation (SET_SRC (x), SET);
3803: SUBST (SET_SRC (x), temp);
3804: }
3805:
1.1.1.4 ! root 3806: /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some
! 3807: operation, and X being a REG or (subreg (reg)), we may be able to
! 3808: convert this to (set (subreg:m2 x) (op)).
! 3809:
! 3810: We can always do this if M1 is narrower than M2 because that
! 3811: means that we only care about the low bits of the result.
! 3812:
! 3813: However, on most machines (those with BYTE_LOADS_ZERO_EXTEND
! 3814: and BYTES_LOADS_SIGN_EXTEND not defined), we cannot perform a
! 3815: narrower operation that requested since the high-order bits will
! 3816: be undefined. On machine where BYTE_LOADS_*_EXTEND is defined,
! 3817: however, this transformation is safe as long as M1 and M2 have
! 3818: the same number of words. */
! 3819:
! 3820: if (GET_CODE (SET_SRC (x)) == SUBREG
! 3821: && subreg_lowpart_p (SET_SRC (x))
! 3822: && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) != 'o'
! 3823: && (((GET_MODE_SIZE (GET_MODE (SET_SRC (x))) + (UNITS_PER_WORD - 1))
! 3824: / UNITS_PER_WORD)
! 3825: == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x))))
! 3826: + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
! 3827: #if ! defined(BYTE_LOADS_ZERO_EXTEND) && ! defined (BYTE_LOADS_SIGN_EXTEND)
! 3828: && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
! 3829: < GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
! 3830: #endif
! 3831: && (GET_CODE (SET_DEST (x)) == REG
! 3832: || (GET_CODE (SET_DEST (x)) == SUBREG
! 3833: && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG)))
! 3834: {
! 3835: SUBST (SET_DEST (x),
! 3836: gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_SRC (x))),
! 3837: SET_DEST (x)));
! 3838: SUBST (SET_SRC (x), SUBREG_REG (SET_SRC (x)));
! 3839: }
! 3840:
1.1 root 3841: #ifdef BYTE_LOADS_ZERO_EXTEND
3842: /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with
3843: M wider than N, this would require a paradoxical subreg.
3844: Replace the subreg with a zero_extend to avoid the reload that
3845: would otherwise be required. */
3846: if (GET_CODE (SET_SRC (x)) == SUBREG
3847: && subreg_lowpart_p (SET_SRC (x))
3848: && SUBREG_WORD (SET_SRC (x)) == 0
3849: && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
3850: > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
3851: && GET_CODE (SUBREG_REG (SET_SRC (x))) == MEM)
3852: SUBST (SET_SRC (x), gen_rtx_combine (ZERO_EXTEND,
3853: GET_MODE (SET_SRC (x)),
3854: XEXP (SET_SRC (x), 0)));
3855: #endif
3856:
1.1.1.4 ! root 3857: #ifndef HAVE_conditional_move
! 3858:
! 3859: /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE,
! 3860: and we are comparing an item known to be 0 or -1 against 0, use a
! 3861: logical operation instead. Check for one of the arms being an IOR
! 3862: of the other arm with some value. We compute three terms to be
! 3863: IOR'ed together. In practice, at most two will be nonzero. Then
! 3864: we do the IOR's. */
! 3865:
! 3866: if (GET_CODE (SET_DEST (x)) != PC
! 3867: && GET_CODE (SET_SRC (x)) == IF_THEN_ELSE
! 3868: && (GET_CODE (XEXP (SET_SRC (x), 0)) == EQ
! 3869: || GET_CODE (XEXP (SET_SRC (x), 0)) == NE)
! 3870: && XEXP (XEXP (SET_SRC (x), 0), 1) == const0_rtx
! 3871: && (num_sign_bit_copies (XEXP (XEXP (SET_SRC (x), 0), 0),
! 3872: GET_MODE (XEXP (XEXP (SET_SRC (x), 0), 0)))
! 3873: == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (SET_SRC (x), 0), 0))))
! 3874: && ! side_effects_p (SET_SRC (x)))
! 3875: {
! 3876: rtx true = (GET_CODE (XEXP (SET_SRC (x), 0)) == NE
! 3877: ? XEXP (SET_SRC (x), 1) : XEXP (SET_SRC (x), 2));
! 3878: rtx false = (GET_CODE (XEXP (SET_SRC (x), 0)) == NE
! 3879: ? XEXP (SET_SRC (x), 2) : XEXP (SET_SRC (x), 1));
! 3880: rtx term1 = const0_rtx, term2, term3;
! 3881:
! 3882: if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
! 3883: term1 = false, true = XEXP (true, 1), false = const0_rtx;
! 3884: else if (GET_CODE (true) == IOR
! 3885: && rtx_equal_p (XEXP (true, 1), false))
! 3886: term1 = false, true = XEXP (true, 0), false = const0_rtx;
! 3887: else if (GET_CODE (false) == IOR
! 3888: && rtx_equal_p (XEXP (false, 0), true))
! 3889: term1 = true, false = XEXP (false, 1), true = const0_rtx;
! 3890: else if (GET_CODE (false) == IOR
! 3891: && rtx_equal_p (XEXP (false, 1), true))
! 3892: term1 = true, false = XEXP (false, 0), true = const0_rtx;
! 3893:
! 3894: term2 = gen_binary (AND, GET_MODE (SET_SRC (x)),
! 3895: XEXP (XEXP (SET_SRC (x), 0), 0), true);
! 3896: term3 = gen_binary (AND, GET_MODE (SET_SRC (x)),
! 3897: gen_unary (NOT, GET_MODE (SET_SRC (x)),
! 3898: XEXP (XEXP (SET_SRC (x), 0), 0)),
! 3899: false);
! 3900:
! 3901: SUBST (SET_SRC (x),
! 3902: gen_binary (IOR, GET_MODE (SET_SRC (x)),
! 3903: gen_binary (IOR, GET_MODE (SET_SRC (x)),
! 3904: term1, term2),
! 3905: term3));
! 3906: }
! 3907: #endif
1.1 root 3908: break;
3909:
3910: case AND:
3911: if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3912: {
3913: x = simplify_and_const_int (x, mode, XEXP (x, 0),
3914: INTVAL (XEXP (x, 1)));
3915:
3916: /* If we have (ior (and (X C1) C2)) and the next restart would be
3917: the last, simplify this by making C1 as small as possible
3918: and then exit. */
3919: if (n_restarts >= 3 && GET_CODE (x) == IOR
3920: && GET_CODE (XEXP (x, 0)) == AND
3921: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3922: && GET_CODE (XEXP (x, 1)) == CONST_INT)
3923: {
3924: temp = gen_binary (AND, mode, XEXP (XEXP (x, 0), 0),
1.1.1.4 ! root 3925: GEN_INT (INTVAL (XEXP (XEXP (x, 0), 1))
! 3926: & ~ INTVAL (XEXP (x, 1))));
1.1 root 3927: return gen_binary (IOR, mode, temp, XEXP (x, 1));
3928: }
3929:
3930: if (GET_CODE (x) != AND)
3931: goto restart;
3932: }
3933:
3934: /* Convert (A | B) & A to A. */
3935: if (GET_CODE (XEXP (x, 0)) == IOR
3936: && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3937: || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
3938: && ! side_effects_p (XEXP (XEXP (x, 0), 0))
3939: && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
3940: return XEXP (x, 1);
3941:
3942: /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
3943: insn (and may simplify more). */
3944: else if (GET_CODE (XEXP (x, 0)) == XOR
3945: && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3946: && ! side_effects_p (XEXP (x, 1)))
3947: {
3948: x = gen_binary (AND, mode,
3949: gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
3950: XEXP (x, 1));
3951: goto restart;
3952: }
3953: else if (GET_CODE (XEXP (x, 0)) == XOR
3954: && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
3955: && ! side_effects_p (XEXP (x, 1)))
3956: {
3957: x = gen_binary (AND, mode,
3958: gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
3959: XEXP (x, 1));
3960: goto restart;
3961: }
3962:
3963: /* Similarly for (~ (A ^ B)) & A. */
3964: else if (GET_CODE (XEXP (x, 0)) == NOT
3965: && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
3966: && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 0), XEXP (x, 1))
3967: && ! side_effects_p (XEXP (x, 1)))
3968: {
3969: x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 1),
3970: XEXP (x, 1));
3971: goto restart;
3972: }
3973: else if (GET_CODE (XEXP (x, 0)) == NOT
3974: && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
3975: && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 1), XEXP (x, 1))
3976: && ! side_effects_p (XEXP (x, 1)))
3977: {
3978: x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 0),
3979: XEXP (x, 1));
3980: goto restart;
3981: }
3982:
1.1.1.4 ! root 3983: /* If we have (and A B) with A not an object but that is known to
! 3984: be -1 or 0, this is equivalent to the expression
! 3985: (if_then_else (ne A (const_int 0)) B (const_int 0))
! 3986: We make this conversion because it may allow further
! 3987: simplifications and then allow use of conditional move insns.
! 3988: If the machine doesn't have condition moves, code in case SET
! 3989: will convert the IF_THEN_ELSE back to the logical operation.
! 3990: We build the IF_THEN_ELSE here in case further simplification
! 3991: is possible (e.g., we can convert it to ABS). */
! 3992:
! 3993: if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
! 3994: && ! (GET_CODE (XEXP (x, 0)) == SUBREG
! 3995: && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o')
! 3996: && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
! 3997: == GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
! 3998: {
! 3999: rtx op0 = XEXP (x, 0);
! 4000: rtx op1 = const0_rtx;
! 4001: enum rtx_code comp_code
! 4002: = simplify_comparison (NE, &op0, &op1);
! 4003:
! 4004: x = gen_rtx_combine (IF_THEN_ELSE, mode,
! 4005: gen_binary (comp_code, VOIDmode, op0, op1),
! 4006: XEXP (x, 1), const0_rtx);
! 4007: goto restart;
! 4008: }
! 4009:
! 4010: /* In the following group of tests (and those in case IOR below),
1.1 root 4011: we start with some combination of logical operations and apply
4012: the distributive law followed by the inverse distributive law.
4013: Most of the time, this results in no change. However, if some of
4014: the operands are the same or inverses of each other, simplifications
4015: will result.
4016:
4017: For example, (and (ior A B) (not B)) can occur as the result of
4018: expanding a bit field assignment. When we apply the distributive
4019: law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4020: which then simplifies to (and (A (not B))). */
4021:
4022: /* If we have (and (ior A B) C), apply the distributive law and then
4023: the inverse distributive law to see if things simplify. */
4024:
4025: if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == XOR)
4026: {
4027: x = apply_distributive_law
4028: (gen_binary (GET_CODE (XEXP (x, 0)), mode,
4029: gen_binary (AND, mode,
4030: XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4031: gen_binary (AND, mode,
4032: XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
4033: if (GET_CODE (x) != AND)
4034: goto restart;
4035: }
4036:
4037: if (GET_CODE (XEXP (x, 1)) == IOR || GET_CODE (XEXP (x, 1)) == XOR)
4038: {
4039: x = apply_distributive_law
4040: (gen_binary (GET_CODE (XEXP (x, 1)), mode,
4041: gen_binary (AND, mode,
4042: XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
4043: gen_binary (AND, mode,
4044: XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
4045: if (GET_CODE (x) != AND)
4046: goto restart;
4047: }
4048:
4049: /* Similarly, taking advantage of the fact that
4050: (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4051:
4052: if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == XOR)
4053: {
4054: x = apply_distributive_law
4055: (gen_binary (XOR, mode,
4056: gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
4057: XEXP (XEXP (x, 1), 0)),
4058: gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
4059: XEXP (XEXP (x, 1), 1))));
4060: if (GET_CODE (x) != AND)
4061: goto restart;
4062: }
4063:
4064: else if (GET_CODE (XEXP (x, 1)) == NOT && GET_CODE (XEXP (x, 0)) == XOR)
4065: {
4066: x = apply_distributive_law
4067: (gen_binary (XOR, mode,
4068: gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
4069: XEXP (XEXP (x, 0), 0)),
4070: gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
4071: XEXP (XEXP (x, 0), 1))));
4072: if (GET_CODE (x) != AND)
4073: goto restart;
4074: }
4075: break;
4076:
4077: case IOR:
1.1.1.4 ! root 4078: /* (ior A C) is C if all significant bits of A are on in C. */
! 4079: if (GET_CODE (XEXP (x, 1)) == CONST_INT
! 4080: && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
! 4081: && (significant_bits (XEXP (x, 0), mode)
! 4082: & ~ INTVAL (XEXP (x, 1))) == 0)
! 4083: return XEXP (x, 1);
! 4084:
1.1 root 4085: /* Convert (A & B) | A to A. */
4086: if (GET_CODE (XEXP (x, 0)) == AND
4087: && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4088: || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
4089: && ! side_effects_p (XEXP (XEXP (x, 0), 0))
4090: && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
4091: return XEXP (x, 1);
4092:
4093: /* If we have (ior (and A B) C), apply the distributive law and then
4094: the inverse distributive law to see if things simplify. */
4095:
4096: if (GET_CODE (XEXP (x, 0)) == AND)
4097: {
4098: x = apply_distributive_law
4099: (gen_binary (AND, mode,
4100: gen_binary (IOR, mode,
4101: XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4102: gen_binary (IOR, mode,
4103: XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
4104:
4105: if (GET_CODE (x) != IOR)
4106: goto restart;
4107: }
4108:
4109: if (GET_CODE (XEXP (x, 1)) == AND)
4110: {
4111: x = apply_distributive_law
4112: (gen_binary (AND, mode,
4113: gen_binary (IOR, mode,
4114: XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
4115: gen_binary (IOR, mode,
4116: XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
4117:
4118: if (GET_CODE (x) != IOR)
4119: goto restart;
4120: }
4121:
4122: /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4123: mode size to (rotate A CX). */
4124:
4125: if (((GET_CODE (XEXP (x, 0)) == ASHIFT
4126: && GET_CODE (XEXP (x, 1)) == LSHIFTRT)
4127: || (GET_CODE (XEXP (x, 1)) == ASHIFT
4128: && GET_CODE (XEXP (x, 0)) == LSHIFTRT))
4129: && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 1), 0))
4130: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4131: && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4132: && (INTVAL (XEXP (XEXP (x, 0), 1)) + INTVAL (XEXP (XEXP (x, 1), 1))
4133: == GET_MODE_BITSIZE (mode)))
4134: {
4135: rtx shift_count;
4136:
4137: if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4138: shift_count = XEXP (XEXP (x, 0), 1);
4139: else
4140: shift_count = XEXP (XEXP (x, 1), 1);
4141: x = gen_rtx (ROTATE, mode, XEXP (XEXP (x, 0), 0), shift_count);
4142: goto restart;
4143: }
4144: break;
4145:
4146: case XOR:
4147: /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
4148: Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
4149: (NOT y). */
4150: {
4151: int num_negated = 0;
4152: rtx in1 = XEXP (x, 0), in2 = XEXP (x, 1);
4153:
4154: if (GET_CODE (in1) == NOT)
4155: num_negated++, in1 = XEXP (in1, 0);
4156: if (GET_CODE (in2) == NOT)
4157: num_negated++, in2 = XEXP (in2, 0);
4158:
4159: if (num_negated == 2)
4160: {
4161: SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4162: SUBST (XEXP (x, 1), XEXP (XEXP (x, 1), 0));
4163: }
4164: else if (num_negated == 1)
1.1.1.4 ! root 4165: {
! 4166: x = gen_unary (NOT, mode,
! 4167: gen_binary (XOR, mode, in1, in2));
! 4168: goto restart;
! 4169: }
1.1 root 4170: }
4171:
4172: /* Convert (xor (and A B) B) to (and (not A) B). The latter may
4173: correspond to a machine insn or result in further simplifications
4174: if B is a constant. */
4175:
4176: if (GET_CODE (XEXP (x, 0)) == AND
4177: && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
4178: && ! side_effects_p (XEXP (x, 1)))
4179: {
4180: x = gen_binary (AND, mode,
4181: gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
4182: XEXP (x, 1));
4183: goto restart;
4184: }
4185: else if (GET_CODE (XEXP (x, 0)) == AND
4186: && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4187: && ! side_effects_p (XEXP (x, 1)))
4188: {
4189: x = gen_binary (AND, mode,
4190: gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
4191: XEXP (x, 1));
4192: goto restart;
4193: }
4194:
4195:
4196: #if STORE_FLAG_VALUE == 1
4197: /* (xor (comparison foo bar) (const_int 1)) can become the reversed
4198: comparison. */
4199: if (XEXP (x, 1) == const1_rtx
4200: && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4201: && reversible_comparison_p (XEXP (x, 0)))
4202: return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
4203: mode, XEXP (XEXP (x, 0), 0),
4204: XEXP (XEXP (x, 0), 1));
4205: #endif
4206:
4207: /* (xor (comparison foo bar) (const_int sign-bit))
4208: when STORE_FLAG_VALUE is the sign bit. */
1.1.1.4 ! root 4209: if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
! 4210: && (STORE_FLAG_VALUE
! 4211: == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
1.1 root 4212: && XEXP (x, 1) == const_true_rtx
4213: && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4214: && reversible_comparison_p (XEXP (x, 0)))
4215: return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
4216: mode, XEXP (XEXP (x, 0), 0),
4217: XEXP (XEXP (x, 0), 1));
4218: break;
4219:
4220: case ABS:
4221: /* (abs (neg <foo>)) -> (abs <foo>) */
4222: if (GET_CODE (XEXP (x, 0)) == NEG)
4223: SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4224:
4225: /* If operand is something known to be positive, ignore the ABS. */
4226: if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
1.1.1.4 ! root 4227: || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
! 4228: <= HOST_BITS_PER_WIDE_INT)
1.1 root 4229: && ((significant_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
1.1.1.4 ! root 4230: & ((HOST_WIDE_INT) 1
! 4231: << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
1.1 root 4232: == 0)))
4233: return XEXP (x, 0);
4234:
4235:
4236: /* If operand is known to be only -1 or 0, convert ABS to NEG. */
1.1.1.4 ! root 4237: if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
1.1 root 4238: {
4239: x = gen_rtx_combine (NEG, mode, XEXP (x, 0));
4240: goto restart;
4241: }
4242: break;
4243:
1.1.1.3 root 4244: case FFS:
4245: /* (ffs (*_extend <X>)) = (ffs <X>) */
4246: if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4247: || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4248: SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4249: break;
4250:
1.1 root 4251: case FLOAT:
4252: /* (float (sign_extend <X>)) = (float <X>). */
4253: if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4254: SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4255: break;
4256:
4257: case LSHIFT:
4258: case ASHIFT:
4259: case LSHIFTRT:
4260: case ASHIFTRT:
4261: case ROTATE:
4262: case ROTATERT:
4263: /* If this is a shift by a constant amount, simplify it. */
4264: if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4265: {
4266: x = simplify_shift_const (x, code, mode, XEXP (x, 0),
4267: INTVAL (XEXP (x, 1)));
4268: if (GET_CODE (x) != code)
4269: goto restart;
4270: }
1.1.1.4 ! root 4271:
! 4272: #ifdef SHIFT_COUNT_TRUNCATED
! 4273: else if (GET_CODE (XEXP (x, 1)) != REG)
! 4274: SUBST (XEXP (x, 1),
! 4275: force_to_mode (XEXP (x, 1), GET_MODE (x),
! 4276: exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))),
! 4277: NULL_RTX));
! 4278: #endif
! 4279:
1.1 root 4280: break;
4281: }
4282:
4283: return x;
4284: }
4285:
4286: /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
4287: operations" because they can be replaced with two more basic operations.
4288: ZERO_EXTEND is also considered "compound" because it can be replaced with
4289: an AND operation, which is simpler, though only one operation.
4290:
4291: The function expand_compound_operation is called with an rtx expression
4292: and will convert it to the appropriate shifts and AND operations,
4293: simplifying at each stage.
4294:
4295: The function make_compound_operation is called to convert an expression
4296: consisting of shifts and ANDs into the equivalent compound expression.
4297: It is the inverse of this function, loosely speaking. */
4298:
4299: static rtx
4300: expand_compound_operation (x)
4301: rtx x;
4302: {
4303: int pos = 0, len;
4304: int unsignedp = 0;
4305: int modewidth;
4306: rtx tem;
4307:
4308: switch (GET_CODE (x))
4309: {
4310: case ZERO_EXTEND:
4311: unsignedp = 1;
4312: case SIGN_EXTEND:
1.1.1.3 root 4313: /* We can't necessarily use a const_int for a multiword mode;
4314: it depends on implicitly extending the value.
4315: Since we don't know the right way to extend it,
4316: we can't tell whether the implicit way is right.
4317:
4318: Even for a mode that is no wider than a const_int,
4319: we can't win, because we need to sign extend one of its bits through
4320: the rest of it, and we don't know which bit. */
1.1 root 4321: if (GET_CODE (XEXP (x, 0)) == CONST_INT)
1.1.1.3 root 4322: return x;
1.1 root 4323:
4324: if (! FAKE_EXTEND_SAFE_P (GET_MODE (XEXP (x, 0)), XEXP (x, 0)))
4325: return x;
4326:
4327: len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
4328: /* If the inner object has VOIDmode (the only way this can happen
4329: is if it is a ASM_OPERANDS), we can't do anything since we don't
4330: know how much masking to do. */
4331: if (len == 0)
4332: return x;
4333:
4334: break;
4335:
4336: case ZERO_EXTRACT:
4337: unsignedp = 1;
4338: case SIGN_EXTRACT:
4339: /* If the operand is a CLOBBER, just return it. */
4340: if (GET_CODE (XEXP (x, 0)) == CLOBBER)
4341: return XEXP (x, 0);
4342:
4343: if (GET_CODE (XEXP (x, 1)) != CONST_INT
4344: || GET_CODE (XEXP (x, 2)) != CONST_INT
4345: || GET_MODE (XEXP (x, 0)) == VOIDmode)
4346: return x;
4347:
4348: len = INTVAL (XEXP (x, 1));
4349: pos = INTVAL (XEXP (x, 2));
4350:
4351: /* If this goes outside the object being extracted, replace the object
4352: with a (use (mem ...)) construct that only combine understands
4353: and is used only for this purpose. */
4354: if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4355: SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
4356:
4357: #if BITS_BIG_ENDIAN
4358: pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
4359: #endif
4360: break;
4361:
4362: default:
4363: return x;
4364: }
4365:
4366: /* If we reach here, we want to return a pair of shifts. The inner
4367: shift is a left shift of BITSIZE - POS - LEN bits. The outer
4368: shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
4369: logical depending on the value of UNSIGNEDP.
4370:
4371: If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
4372: converted into an AND of a shift.
4373:
4374: We must check for the case where the left shift would have a negative
4375: count. This can happen in a case like (x >> 31) & 255 on machines
4376: that can't shift by a constant. On those machines, we would first
4377: combine the shift with the AND to produce a variable-position
4378: extraction. Then the constant of 31 would be substituted in to produce
4379: a such a position. */
4380:
4381: modewidth = GET_MODE_BITSIZE (GET_MODE (x));
4382: if (modewidth >= pos - len)
1.1.1.4 ! root 4383: tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
1.1 root 4384: GET_MODE (x),
1.1.1.4 ! root 4385: simplify_shift_const (NULL_RTX, ASHIFT,
! 4386: GET_MODE (x),
1.1 root 4387: XEXP (x, 0),
4388: modewidth - pos - len),
4389: modewidth - len);
4390:
1.1.1.4 ! root 4391: else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
! 4392: tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
! 4393: simplify_shift_const (NULL_RTX, LSHIFTRT,
1.1 root 4394: GET_MODE (x),
4395: XEXP (x, 0), pos),
1.1.1.4 ! root 4396: ((HOST_WIDE_INT) 1 << len) - 1);
1.1 root 4397: else
4398: /* Any other cases we can't handle. */
4399: return x;
4400:
4401:
4402: /* If we couldn't do this for some reason, return the original
4403: expression. */
4404: if (GET_CODE (tem) == CLOBBER)
4405: return x;
4406:
4407: return tem;
4408: }
4409:
4410: /* X is a SET which contains an assignment of one object into
4411: a part of another (such as a bit-field assignment, STRICT_LOW_PART,
4412: or certain SUBREGS). If possible, convert it into a series of
4413: logical operations.
4414:
4415: We half-heartedly support variable positions, but do not at all
4416: support variable lengths. */
4417:
4418: static rtx
4419: expand_field_assignment (x)
4420: rtx x;
4421: {
4422: rtx inner;
4423: rtx pos; /* Always counts from low bit. */
4424: int len;
4425: rtx mask;
4426: enum machine_mode compute_mode;
4427:
4428: /* Loop until we find something we can't simplify. */
4429: while (1)
4430: {
4431: if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
4432: && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
4433: {
4434: inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
4435: len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
4436: pos = const0_rtx;
4437: }
4438: else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4439: && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
4440: {
4441: inner = XEXP (SET_DEST (x), 0);
4442: len = INTVAL (XEXP (SET_DEST (x), 1));
4443: pos = XEXP (SET_DEST (x), 2);
4444:
4445: /* If the position is constant and spans the width of INNER,
4446: surround INNER with a USE to indicate this. */
4447: if (GET_CODE (pos) == CONST_INT
4448: && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
4449: inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
4450:
4451: #if BITS_BIG_ENDIAN
4452: if (GET_CODE (pos) == CONST_INT)
1.1.1.4 ! root 4453: pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
! 4454: - INTVAL (pos));
1.1 root 4455: else if (GET_CODE (pos) == MINUS
4456: && GET_CODE (XEXP (pos, 1)) == CONST_INT
4457: && (INTVAL (XEXP (pos, 1))
4458: == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
4459: /* If position is ADJUST - X, new position is X. */
4460: pos = XEXP (pos, 0);
4461: else
4462: pos = gen_binary (MINUS, GET_MODE (pos),
1.1.1.4 ! root 4463: GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
! 4464: - len),
! 4465: pos);
1.1 root 4466: #endif
4467: }
4468:
4469: /* A SUBREG between two modes that occupy the same numbers of words
4470: can be done by moving the SUBREG to the source. */
4471: else if (GET_CODE (SET_DEST (x)) == SUBREG
4472: && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
4473: + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
4474: == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
4475: + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
4476: {
4477: x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
4478: gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
4479: SET_SRC (x)));
4480: continue;
4481: }
4482: else
4483: break;
4484:
4485: while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
4486: inner = SUBREG_REG (inner);
4487:
4488: compute_mode = GET_MODE (inner);
4489:
4490: /* Compute a mask of LEN bits, if we can do this on the host machine. */
1.1.1.4 ! root 4491: if (len < HOST_BITS_PER_WIDE_INT)
! 4492: mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
1.1 root 4493: else
4494: break;
4495:
4496: /* Now compute the equivalent expression. Make a copy of INNER
4497: for the SET_DEST in case it is a MEM into which we will substitute;
4498: we don't want shared RTL in that case. */
4499: x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
4500: gen_binary (IOR, compute_mode,
4501: gen_binary (AND, compute_mode,
4502: gen_unary (NOT, compute_mode,
4503: gen_binary (ASHIFT,
4504: compute_mode,
4505: mask, pos)),
4506: inner),
4507: gen_binary (ASHIFT, compute_mode,
4508: gen_binary (AND, compute_mode,
4509: gen_lowpart_for_combine
4510: (compute_mode,
4511: SET_SRC (x)),
4512: mask),
4513: pos)));
4514: }
4515:
4516: return x;
4517: }
4518:
4519: /* Return an RTX for a reference to LEN bits of INNER. POS is the starting
4520: bit position (counted from the LSB) if >= 0; otherwise POS_RTX represents
4521: the starting bit position.
4522:
4523: INNER may be a USE. This will occur when we started with a bitfield
4524: that went outside the boundary of the object in memory, which is
4525: allowed on most machines. To isolate this case, we produce a USE
4526: whose mode is wide enough and surround the MEM with it. The only
4527: code that understands the USE is this routine. If it is not removed,
4528: it will cause the resulting insn not to match.
4529:
4530: UNSIGNEDP is non-zero for an unsigned reference and zero for a
4531: signed reference.
4532:
4533: IN_DEST is non-zero if this is a reference in the destination of a
4534: SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
4535: a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
4536: be used.
4537:
4538: IN_COMPARE is non-zero if we are in a COMPARE. This means that a
4539: ZERO_EXTRACT should be built even for bits starting at bit 0.
4540:
4541: MODE is the desired mode of the result (if IN_DEST == 0). */
4542:
4543: static rtx
4544: make_extraction (mode, inner, pos, pos_rtx, len,
4545: unsignedp, in_dest, in_compare)
4546: enum machine_mode mode;
4547: rtx inner;
4548: int pos;
4549: rtx pos_rtx;
4550: int len;
4551: int unsignedp;
4552: int in_dest, in_compare;
4553: {
1.1.1.4 ! root 4554: /* This mode describes the size of the storage area
! 4555: to fetch the overall value from. Within that, we
! 4556: ignore the POS lowest bits, etc. */
1.1 root 4557: enum machine_mode is_mode = GET_MODE (inner);
4558: enum machine_mode inner_mode;
4559: enum machine_mode wanted_mem_mode = byte_mode;
4560: enum machine_mode pos_mode = word_mode;
4561: enum machine_mode extraction_mode = word_mode;
4562: enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
4563: int spans_byte = 0;
4564: rtx new = 0;
4565:
4566: /* Get some information about INNER and get the innermost object. */
4567: if (GET_CODE (inner) == USE)
1.1.1.4 ! root 4568: /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
1.1 root 4569: /* We don't need to adjust the position because we set up the USE
4570: to pretend that it was a full-word object. */
4571: spans_byte = 1, inner = XEXP (inner, 0);
4572: else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
1.1.1.4 ! root 4573: {
! 4574: /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
! 4575: consider just the QI as the memory to extract from.
! 4576: The subreg adds or removes high bits; its mode is
! 4577: irrelevant to the meaning of this extraction,
! 4578: since POS and LEN count from the lsb. */
! 4579: if (GET_CODE (SUBREG_REG (inner)) == MEM)
! 4580: is_mode = GET_MODE (SUBREG_REG (inner));
! 4581: inner = SUBREG_REG (inner);
! 4582: }
1.1 root 4583:
4584: inner_mode = GET_MODE (inner);
4585:
4586: if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
4587: pos = INTVAL (pos_rtx);
4588:
4589: /* See if this can be done without an extraction. We never can if the
4590: width of the field is not the same as that of some integer mode. For
4591: registers, we can only avoid the extraction if the position is at the
4592: low-order bit and this is either not in the destination or we have the
4593: appropriate STRICT_LOW_PART operation available.
4594:
4595: For MEM, we can avoid an extract if the field starts on an appropriate
4596: boundary and we can change the mode of the memory reference. However,
4597: we cannot directly access the MEM if we have a USE and the underlying
4598: MEM is not TMODE. This combination means that MEM was being used in a
4599: context where bits outside its mode were being referenced; that is only
4600: valid in bit-field insns. */
4601:
4602: if (tmode != BLKmode
4603: && ! (spans_byte && inner_mode != tmode)
1.1.1.4 ! root 4604: && ((pos == 0 && GET_CODE (inner) != MEM
1.1 root 4605: && (! in_dest
1.1.1.4 ! root 4606: || (GET_CODE (inner) == REG
! 4607: && (movstrict_optab->handlers[(int) tmode].insn_code
! 4608: != CODE_FOR_nothing))))
1.1 root 4609: || (GET_CODE (inner) == MEM && pos >= 0
1.1.1.2 root 4610: && (pos
4611: % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
4612: : BITS_PER_UNIT)) == 0
1.1 root 4613: /* We can't do this if we are widening INNER_MODE (it
4614: may not be aligned, for one thing). */
4615: && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
4616: && (inner_mode == tmode
4617: || (! mode_dependent_address_p (XEXP (inner, 0))
4618: && ! MEM_VOLATILE_P (inner))))))
4619: {
4620: /* If INNER is a MEM, make a new MEM that encompasses just the desired
4621: field. If the original and current mode are the same, we need not
4622: adjust the offset. Otherwise, we do if bytes big endian.
4623:
4624: If INNER is not a MEM, get a piece consisting of the just the field
1.1.1.4 ! root 4625: of interest (in this case POS must be 0). */
1.1 root 4626:
4627: if (GET_CODE (inner) == MEM)
4628: {
1.1.1.4 ! root 4629: int offset;
! 4630: /* POS counts from lsb, but make OFFSET count in memory order. */
! 4631: if (BYTES_BIG_ENDIAN)
! 4632: offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
! 4633: else
! 4634: offset = pos / BITS_PER_UNIT;
1.1 root 4635:
4636: new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
4637: RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
4638: MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
4639: MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
4640: }
1.1.1.4 ! root 4641: else if (GET_CODE (inner) == REG)
! 4642: /* We can't call gen_lowpart_for_combine here since we always want
! 4643: a SUBREG and it would sometimes return a new hard register. */
! 4644: new = gen_rtx (SUBREG, tmode, inner,
! 4645: (WORDS_BIG_ENDIAN
! 4646: && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
! 4647: ? ((GET_MODE_SIZE (inner_mode) - GET_MODE_SIZE (tmode))
! 4648: / UNITS_PER_WORD)
! 4649: : 0));
1.1 root 4650: else
1.1.1.4 ! root 4651: new = force_to_mode (inner, tmode, len, NULL_RTX);
1.1 root 4652:
4653: /* If this extraction is going into the destination of a SET,
4654: make a STRICT_LOW_PART unless we made a MEM. */
4655:
4656: if (in_dest)
4657: return (GET_CODE (new) == MEM ? new
1.1.1.4 ! root 4658: : (GET_CODE (new) != SUBREG
! 4659: ? gen_rtx (CLOBBER, tmode, const0_rtx)
! 4660: : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
1.1 root 4661:
4662: /* Otherwise, sign- or zero-extend unless we already are in the
4663: proper mode. */
4664:
4665: return (mode == tmode ? new
4666: : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
4667: mode, new));
4668: }
4669:
1.1.1.4 ! root 4670: /* Unless this is a COMPARE or we have a funny memory reference,
! 4671: don't do anything with zero-extending field extracts starting at
! 4672: the low-order bit since they are simple AND operations. */
! 4673: if (pos == 0 && ! in_dest && ! in_compare && ! spans_byte && unsignedp)
1.1 root 4674: return 0;
4675:
4676: /* Get the mode to use should INNER be a MEM, the mode for the position,
4677: and the mode for the result. */
4678: #ifdef HAVE_insv
4679: if (in_dest)
4680: {
4681: wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
4682: pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
4683: extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
4684: }
4685: #endif
4686:
4687: #ifdef HAVE_extzv
4688: if (! in_dest && unsignedp)
4689: {
4690: wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
4691: pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
4692: extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
4693: }
4694: #endif
4695:
4696: #ifdef HAVE_extv
4697: if (! in_dest && ! unsignedp)
4698: {
4699: wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
4700: pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
4701: extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
4702: }
4703: #endif
4704:
4705: /* Never narrow an object, since that might not be safe. */
4706:
4707: if (mode != VOIDmode
4708: && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
4709: extraction_mode = mode;
4710:
4711: if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
4712: && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
4713: pos_mode = GET_MODE (pos_rtx);
4714:
4715: /* If this is not from memory or we have to change the mode of memory and
4716: cannot, the desired mode is EXTRACTION_MODE. */
4717: if (GET_CODE (inner) != MEM
4718: || (inner_mode != wanted_mem_mode
4719: && (mode_dependent_address_p (XEXP (inner, 0))
4720: || MEM_VOLATILE_P (inner))))
4721: wanted_mem_mode = extraction_mode;
4722:
4723: #if BITS_BIG_ENDIAN
4724: /* If position is constant, compute new position. Otherwise, build
4725: subtraction. */
4726: if (pos >= 0)
4727: pos = (MAX (GET_MODE_BITSIZE (is_mode), GET_MODE_BITSIZE (wanted_mem_mode))
4728: - len - pos);
4729: else
4730: pos_rtx
4731: = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
1.1.1.4 ! root 4732: GEN_INT (MAX (GET_MODE_BITSIZE (is_mode),
! 4733: GET_MODE_BITSIZE (wanted_mem_mode))
! 4734: - len),
! 4735: pos_rtx);
1.1 root 4736: #endif
4737:
4738: /* If INNER has a wider mode, make it smaller. If this is a constant
4739: extract, try to adjust the byte to point to the byte containing
4740: the value. */
4741: if (wanted_mem_mode != VOIDmode
4742: && GET_MODE_SIZE (wanted_mem_mode) < GET_MODE_SIZE (is_mode)
4743: && ((GET_CODE (inner) == MEM
4744: && (inner_mode == wanted_mem_mode
4745: || (! mode_dependent_address_p (XEXP (inner, 0))
4746: && ! MEM_VOLATILE_P (inner))))))
4747: {
4748: int offset = 0;
4749:
4750: /* The computations below will be correct if the machine is big
4751: endian in both bits and bytes or little endian in bits and bytes.
4752: If it is mixed, we must adjust. */
4753:
4754: #if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
4755: if (! spans_byte && is_mode != wanted_mem_mode)
4756: offset = (GET_MODE_SIZE (is_mode)
4757: - GET_MODE_SIZE (wanted_mem_mode) - offset);
4758: #endif
4759:
4760: /* If bytes are big endian and we had a paradoxical SUBREG, we must
4761: adjust OFFSET to compensate. */
4762: #if BYTES_BIG_ENDIAN
4763: if (! spans_byte
4764: && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
4765: offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
4766: #endif
4767:
4768: /* If this is a constant position, we can move to the desired byte. */
4769: if (pos >= 0)
4770: {
4771: offset += pos / BITS_PER_UNIT;
4772: pos %= GET_MODE_BITSIZE (wanted_mem_mode);
4773: }
4774:
4775: if (offset != 0 || inner_mode != wanted_mem_mode)
4776: {
4777: rtx newmem = gen_rtx (MEM, wanted_mem_mode,
4778: plus_constant (XEXP (inner, 0), offset));
4779: RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
4780: MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
4781: MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
4782: inner = newmem;
4783: }
4784: }
4785:
4786: /* If INNER is not memory, we can always get it into the proper mode. */
4787: else if (GET_CODE (inner) != MEM)
1.1.1.4 ! root 4788: inner = force_to_mode (inner, extraction_mode,
! 4789: (pos < 0 ? GET_MODE_BITSIZE (extraction_mode)
! 4790: : len + pos),
! 4791: NULL_RTX);
1.1 root 4792:
4793: /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
4794: have to zero extend. Otherwise, we can just use a SUBREG. */
4795: if (pos < 0
4796: && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
4797: pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
4798: else if (pos < 0
4799: && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
4800: pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
4801:
4802: /* Make POS_RTX unless we already have it and it is correct. */
4803: if (pos_rtx == 0 || (pos >= 0 && INTVAL (pos_rtx) != pos))
1.1.1.4 ! root 4804: pos_rtx = GEN_INT (pos);
1.1 root 4805:
4806: /* Make the required operation. See if we can use existing rtx. */
4807: new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
1.1.1.4 ! root 4808: extraction_mode, inner, GEN_INT (len), pos_rtx);
1.1 root 4809: if (! in_dest)
4810: new = gen_lowpart_for_combine (mode, new);
4811:
4812: return new;
4813: }
4814:
4815: /* Look at the expression rooted at X. Look for expressions
4816: equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
4817: Form these expressions.
4818:
4819: Return the new rtx, usually just X.
4820:
4821: Also, for machines like the Vax that don't have logical shift insns,
4822: try to convert logical to arithmetic shift operations in cases where
4823: they are equivalent. This undoes the canonicalizations to logical
4824: shifts done elsewhere.
4825:
4826: We try, as much as possible, to re-use rtl expressions to save memory.
4827:
4828: IN_CODE says what kind of expression we are processing. Normally, it is
1.1.1.4 ! root 4829: SET. In a memory address (inside a MEM, PLUS or minus, the latter two
! 4830: being kludges), it is MEM. When processing the arguments of a comparison
1.1 root 4831: or a COMPARE against zero, it is COMPARE. */
4832:
4833: static rtx
4834: make_compound_operation (x, in_code)
4835: rtx x;
4836: enum rtx_code in_code;
4837: {
4838: enum rtx_code code = GET_CODE (x);
4839: enum machine_mode mode = GET_MODE (x);
4840: int mode_width = GET_MODE_BITSIZE (mode);
4841: enum rtx_code next_code;
1.1.1.4 ! root 4842: int i, count;
1.1 root 4843: rtx new = 0;
4844: char *fmt;
4845:
4846: /* Select the code to be used in recursive calls. Once we are inside an
4847: address, we stay there. If we have a comparison, set to COMPARE,
4848: but once inside, go back to our default of SET. */
4849:
1.1.1.4 ! root 4850: next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
1.1 root 4851: : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
4852: && XEXP (x, 1) == const0_rtx) ? COMPARE
4853: : in_code == COMPARE ? SET : in_code);
4854:
4855: /* Process depending on the code of this operation. If NEW is set
4856: non-zero, it will be returned. */
4857:
4858: switch (code)
4859: {
4860: case ASHIFT:
4861: case LSHIFT:
4862: /* Convert shifts by constants into multiplications if inside
4863: an address. */
4864: if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
1.1.1.4 ! root 4865: && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
1.1 root 4866: && INTVAL (XEXP (x, 1)) >= 0)
4867: new = gen_rtx_combine (MULT, mode, XEXP (x, 0),
1.1.1.4 ! root 4868: GEN_INT ((HOST_WIDE_INT) 1
! 4869: << INTVAL (XEXP (x, 1))));
1.1 root 4870: break;
4871:
4872: case AND:
4873: /* If the second operand is not a constant, we can't do anything
4874: with it. */
4875: if (GET_CODE (XEXP (x, 1)) != CONST_INT)
4876: break;
4877:
4878: /* If the constant is a power of two minus one and the first operand
4879: is a logical right shift, make an extraction. */
4880: if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4881: && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4882: new = make_extraction (mode, XEXP (XEXP (x, 0), 0), -1,
4883: XEXP (XEXP (x, 0), 1), i, 1,
4884: 0, in_code == COMPARE);
1.1.1.2 root 4885:
1.1 root 4886: /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
4887: else if (GET_CODE (XEXP (x, 0)) == SUBREG
4888: && subreg_lowpart_p (XEXP (x, 0))
4889: && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
4890: && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4891: new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))),
4892: XEXP (SUBREG_REG (XEXP (x, 0)), 0), -1,
4893: XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
4894: 0, in_code == COMPARE);
4895:
1.1.1.3 root 4896:
4897: /* If we are have (and (rotate X C) M) and C is larger than the number
4898: of bits in M, this is an extraction. */
4899:
4900: else if (GET_CODE (XEXP (x, 0)) == ROTATE
4901: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4902: && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
4903: && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
4904: new = make_extraction (mode, XEXP (XEXP (x, 0), 0),
4905: (GET_MODE_BITSIZE (mode)
4906: - INTVAL (XEXP (XEXP (x, 0), 1))),
1.1.1.4 ! root 4907: NULL_RTX, i, 1, 0, in_code == COMPARE);
1.1.1.3 root 4908:
4909: /* On machines without logical shifts, if the operand of the AND is
1.1 root 4910: a logical shift and our mask turns off all the propagated sign
4911: bits, we can replace the logical shift with an arithmetic shift. */
1.1.1.4 ! root 4912: else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
! 4913: && (lshr_optab->handlers[(int) mode].insn_code
! 4914: == CODE_FOR_nothing)
1.1 root 4915: && GET_CODE (XEXP (x, 0)) == LSHIFTRT
4916: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4917: && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
1.1.1.4 ! root 4918: && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
! 4919: && mode_width <= HOST_BITS_PER_WIDE_INT)
1.1 root 4920: {
1.1.1.4 ! root 4921: unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
1.1 root 4922:
4923: mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
4924: if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
4925: SUBST (XEXP (x, 0),
4926: gen_rtx_combine (ASHIFTRT, mode, XEXP (XEXP (x, 0), 0),
4927: XEXP (XEXP (x, 0), 1)));
4928: }
4929:
4930: /* If the constant is one less than a power of two, this might be
4931: representable by an extraction even if no shift is present.
4932: If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
4933: we are in a COMPARE. */
4934: else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
1.1.1.4 ! root 4935: new = make_extraction (mode, XEXP (x, 0), 0, NULL_RTX, i, 1,
1.1 root 4936: 0, in_code == COMPARE);
4937:
4938: /* If we are in a comparison and this is an AND with a power of two,
4939: convert this into the appropriate bit extract. */
4940: else if (in_code == COMPARE
4941: && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
1.1.1.4 ! root 4942: new = make_extraction (mode, XEXP (x, 0), i, NULL_RTX, 1, 1, 0, 1);
1.1 root 4943:
4944: break;
4945:
4946: case LSHIFTRT:
4947: /* If the sign bit is known to be zero, replace this with an
4948: arithmetic shift. */
1.1.1.4 ! root 4949: if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
! 4950: && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
! 4951: && mode_width <= HOST_BITS_PER_WIDE_INT
1.1 root 4952: && (significant_bits (XEXP (x, 0), mode)
4953: & (1 << (mode_width - 1))) == 0)
4954: {
4955: new = gen_rtx_combine (ASHIFTRT, mode, XEXP (x, 0), XEXP (x, 1));
4956: break;
4957: }
4958:
4959: /* ... fall through ... */
4960:
4961: case ASHIFTRT:
4962: /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
4963: this is a SIGN_EXTRACT. */
4964: if (GET_CODE (XEXP (x, 1)) == CONST_INT
1.1.1.4 ! root 4965: && GET_CODE (XEXP (x, 0)) == ASHIFT
! 4966: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
! 4967: && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (x, 0), 1)))
! 4968: new = make_extraction (mode, XEXP (XEXP (x, 0), 0),
! 4969: (INTVAL (XEXP (x, 1))
! 4970: - INTVAL (XEXP (XEXP (x, 0), 1))),
! 4971: NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
! 4972: code == LSHIFTRT, 0, in_code == COMPARE);
! 4973:
! 4974: /* Similarly if we have (ashifrt (OP (ashift foo C1) C3) C2). In these
! 4975: cases, we are better off returning a SIGN_EXTEND of the operation. */
! 4976:
! 4977: if (GET_CODE (XEXP (x, 1)) == CONST_INT
! 4978: && (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND
! 4979: || GET_CODE (XEXP (x, 0)) == XOR
! 4980: || GET_CODE (XEXP (x, 0)) == PLUS)
! 4981: && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT
! 4982: && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
! 4983: && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
! 4984: && INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) < HOST_BITS_PER_WIDE_INT
1.1 root 4985: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1.1.1.4 ! root 4986: && (INTVAL (XEXP (XEXP (x, 0), 1))
! 4987: & (((HOST_WIDE_INT) 1
! 4988: << INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))) - 1)) == 0)
! 4989: {
! 4990: HOST_WIDE_INT newop1
! 4991: = (INTVAL (XEXP (XEXP (x, 0), 1))
! 4992: >> INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)));
! 4993:
! 4994: new = make_extraction (mode,
! 4995: gen_binary (GET_CODE (XEXP (x, 0)), mode,
! 4996: XEXP (XEXP (XEXP (x, 0), 0), 0),
! 4997: GEN_INT (newop1)),
! 4998: (INTVAL (XEXP (x, 1))
! 4999: - INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))),
! 5000: NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
! 5001: code == LSHIFTRT, 0, in_code == COMPARE);
! 5002: }
! 5003:
! 5004: /* Similarly for (ashiftrt (neg (ashift FOO C1)) C2). */
! 5005: if (GET_CODE (XEXP (x, 1)) == CONST_INT
! 5006: && GET_CODE (XEXP (x, 0)) == NEG
! 5007: && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT
! 5008: && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
! 5009: && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
! 5010: new = make_extraction (mode,
! 5011: gen_unary (GET_CODE (XEXP (x, 0)), mode,
! 5012: XEXP (XEXP (XEXP (x, 0), 0), 0)),
1.1 root 5013: (INTVAL (XEXP (x, 1))
1.1.1.4 ! root 5014: - INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))),
! 5015: NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
1.1 root 5016: code == LSHIFTRT, 0, in_code == COMPARE);
5017: break;
5018: }
5019:
5020: if (new)
5021: {
1.1.1.4 ! root 5022: x = gen_lowpart_for_combine (mode, new);
1.1 root 5023: code = GET_CODE (x);
5024: }
5025:
5026: /* Now recursively process each operand of this operation. */
5027: fmt = GET_RTX_FORMAT (code);
5028: for (i = 0; i < GET_RTX_LENGTH (code); i++)
5029: if (fmt[i] == 'e')
5030: {
5031: new = make_compound_operation (XEXP (x, i), next_code);
5032: SUBST (XEXP (x, i), new);
5033: }
5034:
5035: return x;
5036: }
5037:
5038: /* Given M see if it is a value that would select a field of bits
5039: within an item, but not the entire word. Return -1 if not.
5040: Otherwise, return the starting position of the field, where 0 is the
5041: low-order bit.
5042:
5043: *PLEN is set to the length of the field. */
5044:
5045: static int
5046: get_pos_from_mask (m, plen)
1.1.1.4 ! root 5047: unsigned HOST_WIDE_INT m;
1.1 root 5048: int *plen;
5049: {
5050: /* Get the bit number of the first 1 bit from the right, -1 if none. */
5051: int pos = exact_log2 (m & - m);
5052:
5053: if (pos < 0)
5054: return -1;
5055:
5056: /* Now shift off the low-order zero bits and see if we have a power of
5057: two minus 1. */
5058: *plen = exact_log2 ((m >> pos) + 1);
5059:
5060: if (*plen <= 0)
5061: return -1;
5062:
5063: return pos;
5064: }
5065:
1.1.1.2 root 5066: /* Rewrite X so that it is an expression in MODE. We only care about the
5067: low-order BITS bits so we can ignore AND operations that just clear
5068: higher-order bits.
5069:
5070: Also, if REG is non-zero and X is a register equal in value to REG,
5071: replace X with REG. */
5072:
5073: static rtx
5074: force_to_mode (x, mode, bits, reg)
5075: rtx x;
5076: enum machine_mode mode;
5077: int bits;
5078: rtx reg;
5079: {
5080: enum rtx_code code = GET_CODE (x);
1.1.1.4 ! root 5081: enum machine_mode op_mode = mode;
1.1.1.2 root 5082:
5083: /* If X is narrower than MODE or if BITS is larger than the size of MODE,
5084: just get X in the proper mode. */
5085:
5086: if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
5087: || bits > GET_MODE_BITSIZE (mode))
5088: return gen_lowpart_for_combine (mode, x);
5089:
5090: switch (code)
5091: {
5092: case SIGN_EXTEND:
5093: case ZERO_EXTEND:
5094: case ZERO_EXTRACT:
5095: case SIGN_EXTRACT:
5096: x = expand_compound_operation (x);
5097: if (GET_CODE (x) != code)
5098: return force_to_mode (x, mode, bits, reg);
5099: break;
5100:
5101: case REG:
5102: if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
5103: || rtx_equal_p (reg, get_last_value (x))))
5104: x = reg;
5105: break;
5106:
5107: case CONST_INT:
1.1.1.4 ! root 5108: if (bits < HOST_BITS_PER_WIDE_INT)
! 5109: x = GEN_INT (INTVAL (x) & (((HOST_WIDE_INT) 1 << bits) - 1));
1.1.1.2 root 5110: return x;
5111:
5112: case SUBREG:
5113: /* Ignore low-order SUBREGs. */
5114: if (subreg_lowpart_p (x))
5115: return force_to_mode (SUBREG_REG (x), mode, bits, reg);
5116: break;
5117:
5118: case AND:
5119: /* If this is an AND with a constant. Otherwise, we fall through to
5120: do the general binary case. */
5121:
5122: if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5123: {
1.1.1.4 ! root 5124: HOST_WIDE_INT mask = INTVAL (XEXP (x, 1));
1.1.1.2 root 5125: int len = exact_log2 (mask + 1);
5126: rtx op = XEXP (x, 0);
5127:
5128: /* If this is masking some low-order bits, we may be able to
5129: impose a stricter constraint on what bits of the operand are
5130: required. */
5131:
5132: op = force_to_mode (op, mode, len > 0 ? MIN (len, bits) : bits,
5133: reg);
5134:
1.1.1.4 ! root 5135: if (bits < HOST_BITS_PER_WIDE_INT)
! 5136: mask &= ((HOST_WIDE_INT) 1 << bits) - 1;
1.1.1.2 root 5137:
1.1.1.4 ! root 5138: /* If we have no AND in MODE, use the original mode for the
! 5139: operation. */
! 5140:
! 5141: if (and_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
! 5142: op_mode = GET_MODE (x);
! 5143:
! 5144: x = simplify_and_const_int (x, op_mode, op, mask);
1.1.1.2 root 5145:
5146: /* If X is still an AND, see if it is an AND with a mask that
5147: is just some low-order bits. If so, and it is BITS wide (it
5148: can't be wider), we don't need it. */
5149:
5150: if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
1.1.1.4 ! root 5151: && bits < HOST_BITS_PER_WIDE_INT
! 5152: && INTVAL (XEXP (x, 1)) == ((HOST_WIDE_INT) 1 << bits) - 1)
1.1.1.2 root 5153: x = XEXP (x, 0);
1.1.1.4 ! root 5154:
! 5155: break;
1.1.1.2 root 5156: }
5157:
5158: /* ... fall through ... */
5159:
5160: case PLUS:
5161: case MINUS:
5162: case MULT:
5163: case IOR:
5164: case XOR:
5165: /* For most binary operations, just propagate into the operation and
1.1.1.4 ! root 5166: change the mode if we have an operation of that mode. */
1.1.1.2 root 5167:
1.1.1.4 ! root 5168: if ((code == PLUS
! 5169: && add_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
! 5170: || (code == MINUS
! 5171: && sub_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
! 5172: || (code == MULT && (smul_optab->handlers[(int) mode].insn_code
! 5173: == CODE_FOR_nothing))
! 5174: || (code == AND
! 5175: && and_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
! 5176: || (code == IOR
! 5177: && ior_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
! 5178: || (code == XOR && (xor_optab->handlers[(int) mode].insn_code
! 5179: == CODE_FOR_nothing)))
! 5180: op_mode = GET_MODE (x);
! 5181:
! 5182: x = gen_binary (code, op_mode,
! 5183: gen_lowpart_for_combine (op_mode,
! 5184: force_to_mode (XEXP (x, 0),
! 5185: mode, bits,
! 5186: reg)),
! 5187: gen_lowpart_for_combine (op_mode,
! 5188: force_to_mode (XEXP (x, 1),
! 5189: mode, bits,
! 5190: reg)));
! 5191: break;
1.1.1.2 root 5192:
5193: case ASHIFT:
5194: case LSHIFT:
5195: /* For left shifts, do the same, but just for the first operand.
5196: If the shift count is a constant, we need even fewer bits of the
5197: first operand. */
5198:
5199: if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) < bits)
5200: bits -= INTVAL (XEXP (x, 1));
5201:
1.1.1.4 ! root 5202: if ((code == ASHIFT
! 5203: && ashl_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
! 5204: || (code == LSHIFT && (lshl_optab->handlers[(int) mode].insn_code
! 5205: == CODE_FOR_nothing)))
! 5206: op_mode = GET_MODE (x);
! 5207:
! 5208: x = gen_binary (code, op_mode,
! 5209: gen_lowpart_for_combine (op_mode,
! 5210: force_to_mode (XEXP (x, 0),
! 5211: mode, bits,
! 5212: reg)),
! 5213: XEXP (x, 1));
! 5214: break;
1.1.1.2 root 5215:
5216: case LSHIFTRT:
5217: /* Here we can only do something if the shift count is a constant and
5218: the count plus BITS is no larger than the width of MODE, we can do
5219: the shift in MODE. */
5220:
5221: if (GET_CODE (XEXP (x, 1)) == CONST_INT
5222: && INTVAL (XEXP (x, 1)) + bits <= GET_MODE_BITSIZE (mode))
1.1.1.4 ! root 5223: {
! 5224: rtx inner = force_to_mode (XEXP (x, 0), mode,
! 5225: bits + INTVAL (XEXP (x, 1)), reg);
! 5226:
! 5227: if (lshr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
! 5228: op_mode = GET_MODE (x);
! 5229:
! 5230: x = gen_binary (LSHIFTRT, op_mode,
! 5231: gen_lowpart_for_combine (op_mode, inner),
! 5232: XEXP (x, 1));
! 5233: }
! 5234: break;
! 5235:
! 5236: case ASHIFTRT:
! 5237: /* If this is a sign-extension operation that just affects bits
! 5238: we don't care about, remove it. */
! 5239:
! 5240: if (GET_CODE (XEXP (x, 1)) == CONST_INT
! 5241: && INTVAL (XEXP (x, 1)) >= 0
! 5242: && INTVAL (XEXP (x, 1)) <= GET_MODE_BITSIZE (GET_MODE (x)) - bits
! 5243: && GET_CODE (XEXP (x, 0)) == ASHIFT
! 5244: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
! 5245: && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
! 5246: return force_to_mode (XEXP (XEXP (x, 0), 0), mode, bits, reg);
1.1.1.2 root 5247: break;
5248:
5249: case NEG:
5250: case NOT:
1.1.1.4 ! root 5251: if ((code == NEG
! 5252: && neg_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
! 5253: || (code == NOT && (one_cmpl_optab->handlers[(int) mode].insn_code
! 5254: == CODE_FOR_nothing)))
! 5255: op_mode = GET_MODE (x);
! 5256:
1.1.1.2 root 5257: /* Handle these similarly to the way we handle most binary operations. */
1.1.1.4 ! root 5258: x = gen_unary (code, op_mode,
! 5259: gen_lowpart_for_combine (op_mode,
! 5260: force_to_mode (XEXP (x, 0), mode,
! 5261: bits, reg)));
! 5262: break;
! 5263:
! 5264: case IF_THEN_ELSE:
! 5265: /* We have no way of knowing if the IF_THEN_ELSE can itself be
! 5266: written in a narrower mode. We play it safe and do not do so. */
! 5267:
! 5268: SUBST (XEXP (x, 1),
! 5269: gen_lowpart_for_combine (GET_MODE (x),
! 5270: force_to_mode (XEXP (x, 1), mode,
! 5271: bits, reg)));
! 5272: SUBST (XEXP (x, 2),
! 5273: gen_lowpart_for_combine (GET_MODE (x),
! 5274: force_to_mode (XEXP (x, 2), mode,
! 5275: bits, reg)));
! 5276: break;
1.1.1.2 root 5277: }
5278:
1.1.1.4 ! root 5279: /* Ensure we return a value of the proper mode. */
1.1.1.2 root 5280: return gen_lowpart_for_combine (mode, x);
5281: }
5282:
1.1.1.4 ! root 5283: /* Return the value of expression X given the fact that condition COND
! 5284: is known to be true when applied to REG as its first operand and VAL
! 5285: as its second. X is known to not be shared and so can be modified in
! 5286: place.
! 5287:
! 5288: We only handle the simplest cases, and specifically those cases that
! 5289: arise with IF_THEN_ELSE expressions. */
! 5290:
! 5291: static rtx
! 5292: known_cond (x, cond, reg, val)
! 5293: rtx x;
! 5294: enum rtx_code cond;
! 5295: rtx reg, val;
! 5296: {
! 5297: enum rtx_code code = GET_CODE (x);
! 5298: rtx new, temp;
! 5299: char *fmt;
! 5300: int i, j;
! 5301:
! 5302: if (side_effects_p (x))
! 5303: return x;
! 5304:
! 5305: if (cond == EQ && rtx_equal_p (x, reg))
! 5306: return val;
! 5307:
! 5308: /* If X is (abs REG) and we know something about REG's relationship
! 5309: with zero, we may be able to simplify this. */
! 5310:
! 5311: if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
! 5312: switch (cond)
! 5313: {
! 5314: case GE: case GT: case EQ:
! 5315: return XEXP (x, 0);
! 5316: case LT: case LE:
! 5317: return gen_unary (NEG, GET_MODE (XEXP (x, 0)), XEXP (x, 0));
! 5318: }
! 5319:
! 5320: /* The only other cases we handle are MIN, MAX, and comparisons if the
! 5321: operands are the same as REG and VAL. */
! 5322:
! 5323: else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
! 5324: {
! 5325: if (rtx_equal_p (XEXP (x, 0), val))
! 5326: cond = swap_condition (cond), temp = val, val = reg, reg = temp;
! 5327:
! 5328: if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
! 5329: {
! 5330: if (GET_RTX_CLASS (code) == '<')
! 5331: return (comparison_dominates_p (cond, code) ? const_true_rtx
! 5332: : (comparison_dominates_p (cond,
! 5333: reverse_condition (code))
! 5334: ? const0_rtx : x));
! 5335:
! 5336: else if (code == SMAX || code == SMIN
! 5337: || code == UMIN || code == UMAX)
! 5338: {
! 5339: int unsignedp = (code == UMIN || code == UMAX);
! 5340:
! 5341: if (code == SMAX || code == UMAX)
! 5342: cond = reverse_condition (cond);
! 5343:
! 5344: switch (cond)
! 5345: {
! 5346: case GE: case GT:
! 5347: return unsignedp ? x : XEXP (x, 1);
! 5348: case LE: case LT:
! 5349: return unsignedp ? x : XEXP (x, 0);
! 5350: case GEU: case GTU:
! 5351: return unsignedp ? XEXP (x, 1) : x;
! 5352: case LEU: case LTU:
! 5353: return unsignedp ? XEXP (x, 0) : x;
! 5354: }
! 5355: }
! 5356: }
! 5357: }
! 5358:
! 5359: fmt = GET_RTX_FORMAT (code);
! 5360: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
! 5361: {
! 5362: if (fmt[i] == 'e')
! 5363: SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
! 5364: else if (fmt[i] == 'E')
! 5365: for (j = XVECLEN (x, i) - 1; j >= 0; j--)
! 5366: SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
! 5367: cond, reg, val));
! 5368: }
! 5369:
! 5370: return x;
! 5371: }
! 5372:
1.1 root 5373: /* See if X, a SET operation, can be rewritten as a bit-field assignment.
5374: Return that assignment if so.
5375:
5376: We only handle the most common cases. */
5377:
5378: static rtx
5379: make_field_assignment (x)
5380: rtx x;
5381: {
5382: rtx dest = SET_DEST (x);
5383: rtx src = SET_SRC (x);
1.1.1.2 root 5384: rtx ourdest;
5385: rtx assign;
1.1.1.4 ! root 5386: HOST_WIDE_INT c1;
! 5387: int pos, len;
1.1.1.2 root 5388: rtx other;
5389: enum machine_mode mode;
1.1 root 5390:
5391: /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
5392: a clear of a one-bit field. We will have changed it to
5393: (and (rotate (const_int -2) POS) DEST), so check for that. Also check
5394: for a SUBREG. */
5395:
5396: if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
5397: && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
5398: && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
1.1.1.2 root 5399: && (rtx_equal_p (dest, XEXP (src, 1))
5400: || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
5401: || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
1.1 root 5402: {
5403: assign = make_extraction (VOIDmode, dest, -1, XEXP (XEXP (src, 0), 1),
5404: 1, 1, 1, 0);
1.1.1.2 root 5405: return gen_rtx (SET, VOIDmode, assign, const0_rtx);
1.1 root 5406: }
5407:
5408: else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
5409: && subreg_lowpart_p (XEXP (src, 0))
5410: && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
5411: < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
5412: && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
5413: && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
1.1.1.2 root 5414: && (rtx_equal_p (dest, XEXP (src, 1))
5415: || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
5416: || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
1.1 root 5417: {
5418: assign = make_extraction (VOIDmode, dest, -1,
5419: XEXP (SUBREG_REG (XEXP (src, 0)), 1),
5420: 1, 1, 1, 0);
1.1.1.2 root 5421: return gen_rtx (SET, VOIDmode, assign, const0_rtx);
1.1 root 5422: }
5423:
5424: /* If SRC is (ior (ashift (const_int 1) POS DEST)), this is a set of a
5425: one-bit field. */
5426: else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
5427: && XEXP (XEXP (src, 0), 0) == const1_rtx
1.1.1.2 root 5428: && (rtx_equal_p (dest, XEXP (src, 1))
5429: || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
5430: || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
1.1 root 5431: {
5432: assign = make_extraction (VOIDmode, dest, -1, XEXP (XEXP (src, 0), 1),
5433: 1, 1, 1, 0);
1.1.1.2 root 5434: return gen_rtx (SET, VOIDmode, assign, const1_rtx);
1.1 root 5435: }
5436:
1.1.1.2 root 5437: /* The other case we handle is assignments into a constant-position
5438: field. They look like (ior (and DEST C1) OTHER). If C1 represents
5439: a mask that has all one bits except for a group of zero bits and
5440: OTHER is known to have zeros where C1 has ones, this is such an
5441: assignment. Compute the position and length from C1. Shift OTHER
5442: to the appropriate position, force it to the required mode, and
5443: make the extraction. Check for the AND in both operands. */
5444:
5445: if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == AND
5446: && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT
5447: && (rtx_equal_p (XEXP (XEXP (src, 0), 0), dest)
5448: || rtx_equal_p (XEXP (XEXP (src, 0), 0), get_last_value (dest))
5449: || rtx_equal_p (get_last_value (XEXP (XEXP (src, 0), 1)), dest)))
5450: c1 = INTVAL (XEXP (XEXP (src, 0), 1)), other = XEXP (src, 1);
5451: else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 1)) == AND
5452: && GET_CODE (XEXP (XEXP (src, 1), 1)) == CONST_INT
5453: && (rtx_equal_p (XEXP (XEXP (src, 1), 0), dest)
5454: || rtx_equal_p (XEXP (XEXP (src, 1), 0), get_last_value (dest))
5455: || rtx_equal_p (get_last_value (XEXP (XEXP (src, 1), 0)),
5456: dest)))
5457: c1 = INTVAL (XEXP (XEXP (src, 1), 1)), other = XEXP (src, 0);
5458: else
5459: return x;
1.1 root 5460:
1.1.1.2 root 5461: pos = get_pos_from_mask (~c1, &len);
5462: if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
1.1.1.4 ! root 5463: || (GET_MODE_BITSIZE (GET_MODE (other)) <= HOST_BITS_PER_WIDE_INT
! 5464: && (c1 & significant_bits (other, GET_MODE (other))) != 0))
1.1.1.2 root 5465: return x;
1.1 root 5466:
1.1.1.4 ! root 5467: assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
1.1 root 5468:
1.1.1.2 root 5469: /* The mode to use for the source is the mode of the assignment, or of
5470: what is inside a possible STRICT_LOW_PART. */
5471: mode = (GET_CODE (assign) == STRICT_LOW_PART
5472: ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
1.1 root 5473:
1.1.1.2 root 5474: /* Shift OTHER right POS places and make it the source, restricting it
5475: to the proper length and mode. */
1.1 root 5476:
1.1.1.4 ! root 5477: src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
! 5478: GET_MODE (src), other, pos),
1.1.1.2 root 5479: mode, len, dest);
1.1 root 5480:
1.1.1.2 root 5481: return gen_rtx_combine (SET, VOIDmode, assign, src);
1.1 root 5482: }
5483:
5484: /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
5485: if so. */
5486:
5487: static rtx
5488: apply_distributive_law (x)
5489: rtx x;
5490: {
5491: enum rtx_code code = GET_CODE (x);
5492: rtx lhs, rhs, other;
5493: rtx tem;
5494: enum rtx_code inner_code;
5495:
5496: /* The outer operation can only be one of the following: */
5497: if (code != IOR && code != AND && code != XOR
5498: && code != PLUS && code != MINUS)
5499: return x;
5500:
5501: lhs = XEXP (x, 0), rhs = XEXP (x, 1);
5502:
1.1.1.2 root 5503: /* If either operand is a primitive we can't do anything, so get out fast. */
1.1 root 5504: if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
1.1.1.2 root 5505: || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
1.1 root 5506: return x;
5507:
5508: lhs = expand_compound_operation (lhs);
5509: rhs = expand_compound_operation (rhs);
5510: inner_code = GET_CODE (lhs);
5511: if (inner_code != GET_CODE (rhs))
5512: return x;
5513:
5514: /* See if the inner and outer operations distribute. */
5515: switch (inner_code)
5516: {
5517: case LSHIFTRT:
5518: case ASHIFTRT:
5519: case AND:
5520: case IOR:
5521: /* These all distribute except over PLUS. */
5522: if (code == PLUS || code == MINUS)
5523: return x;
5524: break;
5525:
5526: case MULT:
5527: if (code != PLUS && code != MINUS)
5528: return x;
5529: break;
5530:
5531: case ASHIFT:
5532: case LSHIFT:
5533: /* These are also multiplies, so they distribute over everything. */
5534: break;
5535:
5536: case SUBREG:
1.1.1.2 root 5537: /* Non-paradoxical SUBREGs distributes over all operations, provided
5538: the inner modes and word numbers are the same, this is an extraction
1.1.1.3 root 5539: of a low-order part, we don't convert an fp operation to int or
5540: vice versa, and we would not be converting a single-word
1.1.1.2 root 5541: operation into a multi-word operation. The latter test is not
1.1.1.3 root 5542: required, but it prevents generating unneeded multi-word operations.
1.1.1.2 root 5543: Some of the previous tests are redundant given the latter test, but
5544: are retained because they are required for correctness.
5545:
5546: We produce the result slightly differently in this case. */
5547:
5548: if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
5549: || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
5550: || ! subreg_lowpart_p (lhs)
1.1.1.3 root 5551: || (GET_MODE_CLASS (GET_MODE (lhs))
5552: != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
1.1.1.2 root 5553: || (GET_MODE_SIZE (GET_MODE (lhs))
5554: < GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
5555: || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
1.1 root 5556: return x;
5557:
5558: tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
5559: SUBREG_REG (lhs), SUBREG_REG (rhs));
5560: return gen_lowpart_for_combine (GET_MODE (x), tem);
5561:
5562: default:
5563: return x;
5564: }
5565:
5566: /* Set LHS and RHS to the inner operands (A and B in the example
5567: above) and set OTHER to the common operand (C in the example).
5568: These is only one way to do this unless the inner operation is
5569: commutative. */
5570: if (GET_RTX_CLASS (inner_code) == 'c'
5571: && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
5572: other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
5573: else if (GET_RTX_CLASS (inner_code) == 'c'
5574: && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
5575: other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
5576: else if (GET_RTX_CLASS (inner_code) == 'c'
5577: && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
5578: other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
5579: else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
5580: other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
5581: else
5582: return x;
5583:
5584: /* Form the new inner operation, seeing if it simplifies first. */
5585: tem = gen_binary (code, GET_MODE (x), lhs, rhs);
5586:
5587: /* There is one exception to the general way of distributing:
5588: (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
5589: if (code == XOR && inner_code == IOR)
5590: {
5591: inner_code = AND;
5592: other = gen_unary (NOT, GET_MODE (x), other);
5593: }
5594:
5595: /* We may be able to continuing distributing the result, so call
5596: ourselves recursively on the inner operation before forming the
5597: outer operation, which we return. */
5598: return gen_binary (inner_code, GET_MODE (x),
5599: apply_distributive_law (tem), other);
5600: }
5601:
5602: /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
5603: in MODE.
5604:
5605: Return an equivalent form, if different from X. Otherwise, return X. If
5606: X is zero, we are to always construct the equivalent form. */
5607:
5608: static rtx
5609: simplify_and_const_int (x, mode, varop, constop)
5610: rtx x;
5611: enum machine_mode mode;
5612: rtx varop;
1.1.1.4 ! root 5613: unsigned HOST_WIDE_INT constop;
1.1 root 5614: {
5615: register enum machine_mode tmode;
5616: register rtx temp;
1.1.1.4 ! root 5617: unsigned HOST_WIDE_INT significant;
1.1 root 5618:
5619: /* There is a large class of optimizations based on the principle that
5620: some operations produce results where certain bits are known to be zero,
5621: and hence are not significant to the AND. For example, if we have just
5622: done a left shift of one bit, the low-order bit is known to be zero and
5623: hence an AND with a mask of ~1 would not do anything.
5624:
5625: At the end of the following loop, we set:
5626:
5627: VAROP to be the item to be AND'ed with;
5628: CONSTOP to the constant value to AND it with. */
5629:
5630: while (1)
5631: {
1.1.1.4 ! root 5632: /* If we ever encounter a mode wider than the host machine's widest
! 5633: integer size, we can't compute the masks accurately, so give up. */
! 5634: if (GET_MODE_BITSIZE (GET_MODE (varop)) > HOST_BITS_PER_WIDE_INT)
1.1 root 5635: break;
5636:
5637: /* Unless one of the cases below does a `continue',
5638: a `break' will be executed to exit the loop. */
5639:
5640: switch (GET_CODE (varop))
5641: {
5642: case CLOBBER:
5643: /* If VAROP is a (clobber (const_int)), return it since we know
5644: we are generating something that won't match. */
5645: return varop;
5646:
5647: #if ! BITS_BIG_ENDIAN
5648: case USE:
5649: /* VAROP is a (use (mem ..)) that was made from a bit-field
5650: extraction that spanned the boundary of the MEM. If we are
5651: now masking so it is within that boundary, we don't need the
5652: USE any more. */
5653: if ((constop & ~ GET_MODE_MASK (GET_MODE (XEXP (varop, 0)))) == 0)
5654: {
5655: varop = XEXP (varop, 0);
5656: continue;
5657: }
5658: break;
5659: #endif
5660:
5661: case SUBREG:
5662: if (subreg_lowpart_p (varop)
5663: /* We can ignore the effect this SUBREG if it narrows the mode
1.1.1.4 ! root 5664: or, on machines where byte operations extend, if the
1.1 root 5665: constant masks to zero all the bits the mode doesn't have. */
5666: && ((GET_MODE_SIZE (GET_MODE (varop))
5667: < GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))))
1.1.1.4 ! root 5668: #if defined(BYTE_LOADS_ZERO_EXTEND) || defined(BYTE_LOADS_SIGN_EXTEND)
1.1 root 5669: || (0 == (constop
5670: & GET_MODE_MASK (GET_MODE (varop))
5671: & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (varop)))))
5672: #endif
5673: ))
5674: {
5675: varop = SUBREG_REG (varop);
5676: continue;
5677: }
5678: break;
5679:
5680: case ZERO_EXTRACT:
5681: case SIGN_EXTRACT:
5682: case ZERO_EXTEND:
5683: case SIGN_EXTEND:
5684: /* Try to expand these into a series of shifts and then work
5685: with that result. If we can't, for example, if the extract
5686: isn't at a fixed position, give up. */
5687: temp = expand_compound_operation (varop);
5688: if (temp != varop)
5689: {
5690: varop = temp;
5691: continue;
5692: }
5693: break;
5694:
5695: case AND:
5696: if (GET_CODE (XEXP (varop, 1)) == CONST_INT)
5697: {
5698: constop &= INTVAL (XEXP (varop, 1));
5699: varop = XEXP (varop, 0);
5700: continue;
5701: }
5702: break;
5703:
5704: case IOR:
5705: case XOR:
5706: /* If VAROP is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
5707: LSHIFT so we end up with an (and (lshiftrt (ior ...) ...) ...)
5708: operation which may be a bitfield extraction. */
5709:
5710: if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT
5711: && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
5712: && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0
1.1.1.4 ! root 5713: && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_WIDE_INT
1.1 root 5714: && GET_CODE (XEXP (varop, 1)) == CONST_INT
5715: && (INTVAL (XEXP (varop, 1))
5716: & ~ significant_bits (XEXP (varop, 0),
5717: GET_MODE (varop)) == 0))
5718: {
1.1.1.4 ! root 5719: temp = GEN_INT ((INTVAL (XEXP (varop, 1)) & constop)
! 5720: << INTVAL (XEXP (XEXP (varop, 0), 1)));
1.1 root 5721: temp = gen_binary (GET_CODE (varop), GET_MODE (varop),
5722: XEXP (XEXP (varop, 0), 0), temp);
5723: varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
5724: temp, XEXP (varop, 1));
5725: continue;
5726: }
5727:
5728: /* Apply the AND to both branches of the IOR or XOR, then try to
5729: apply the distributive law. This may eliminate operations
5730: if either branch can be simplified because of the AND.
5731: It may also make some cases more complex, but those cases
5732: probably won't match a pattern either with or without this. */
5733: return
5734: gen_lowpart_for_combine
5735: (mode, apply_distributive_law
5736: (gen_rtx_combine
5737: (GET_CODE (varop), GET_MODE (varop),
1.1.1.4 ! root 5738: simplify_and_const_int (NULL_RTX, GET_MODE (varop),
1.1 root 5739: XEXP (varop, 0), constop),
1.1.1.4 ! root 5740: simplify_and_const_int (NULL_RTX, GET_MODE (varop),
1.1 root 5741: XEXP (varop, 1), constop))));
5742:
5743: case NOT:
5744: /* (and (not FOO)) is (and (xor FOO CONST_OP)) so if FOO is an
5745: LSHIFTRT we can do the same as above. */
5746:
5747: if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT
5748: && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
5749: && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0
1.1.1.4 ! root 5750: && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_WIDE_INT)
1.1 root 5751: {
1.1.1.4 ! root 5752: temp = GEN_INT (constop << INTVAL (XEXP (XEXP (varop, 0), 1)));
1.1 root 5753: temp = gen_binary (XOR, GET_MODE (varop),
5754: XEXP (XEXP (varop, 0), 0), temp);
5755: varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
5756: temp, XEXP (XEXP (varop, 0), 1));
5757: continue;
5758: }
5759: break;
5760:
5761: case ASHIFTRT:
5762: /* If we are just looking for the sign bit, we don't need this
5763: shift at all, even if it has a variable count. */
1.1.1.4 ! root 5764: if (constop == ((HOST_WIDE_INT) 1
! 5765: << (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)))
1.1 root 5766: {
5767: varop = XEXP (varop, 0);
5768: continue;
5769: }
5770:
5771: /* If this is a shift by a constant, get a mask that contains
5772: those bits that are not copies of the sign bit. We then have
5773: two cases: If CONSTOP only includes those bits, this can be
5774: a logical shift, which may allow simplifications. If CONSTOP
5775: is a single-bit field not within those bits, we are requesting
5776: a copy of the sign bit and hence can shift the sign bit to
5777: the appropriate location. */
5778: if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5779: && INTVAL (XEXP (varop, 1)) >= 0
1.1.1.4 ! root 5780: && INTVAL (XEXP (varop, 1)) < HOST_BITS_PER_WIDE_INT)
1.1 root 5781: {
5782: int i = -1;
5783:
5784: significant = GET_MODE_MASK (GET_MODE (varop));
5785: significant >>= INTVAL (XEXP (varop, 1));
5786:
5787: if ((constop & ~significant) == 0
5788: || (i = exact_log2 (constop)) >= 0)
5789: {
5790: varop = simplify_shift_const
5791: (varop, LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
5792: i < 0 ? INTVAL (XEXP (varop, 1))
5793: : GET_MODE_BITSIZE (GET_MODE (varop)) - 1 - i);
5794: if (GET_CODE (varop) != ASHIFTRT)
5795: continue;
5796: }
5797: }
5798:
5799: /* If our mask is 1, convert this to a LSHIFTRT. This can be done
5800: even if the shift count isn't a constant. */
5801: if (constop == 1)
5802: varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
5803: XEXP (varop, 0), XEXP (varop, 1));
5804: break;
5805:
5806: case NE:
5807: /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is
5808: included in STORE_FLAG_VALUE and FOO has no significant bits
5809: not in CONST. */
5810: if ((constop & ~ STORE_FLAG_VALUE) == 0
5811: && XEXP (varop, 0) == const0_rtx
5812: && (significant_bits (XEXP (varop, 0), mode) & ~ constop) == 0)
5813: {
5814: varop = XEXP (varop, 0);
5815: continue;
5816: }
5817: break;
5818:
5819: case PLUS:
5820: /* In (and (plus FOO C1) M), if M is a mask that just turns off
5821: low-order bits (as in an alignment operation) and FOO is already
5822: aligned to that boundary, we can convert remove this AND
5823: and possibly the PLUS if it is now adding zero. */
5824: if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5825: && exact_log2 (-constop) >= 0
5826: && (significant_bits (XEXP (varop, 0), mode) & ~ constop) == 0)
5827: {
5828: varop = plus_constant (XEXP (varop, 0),
5829: INTVAL (XEXP (varop, 1)) & constop);
5830: constop = ~0;
5831: break;
5832: }
5833:
5834: /* ... fall through ... */
5835:
5836: case MINUS:
5837: /* In (and (plus (and FOO M1) BAR) M2), if M1 and M2 are one
5838: less than powers of two and M2 is narrower than M1, we can
5839: eliminate the inner AND. This occurs when incrementing
5840: bit fields. */
5841:
5842: if (GET_CODE (XEXP (varop, 0)) == ZERO_EXTRACT
5843: || GET_CODE (XEXP (varop, 0)) == ZERO_EXTEND)
5844: SUBST (XEXP (varop, 0),
5845: expand_compound_operation (XEXP (varop, 0)));
5846:
5847: if (GET_CODE (XEXP (varop, 0)) == AND
5848: && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
5849: && exact_log2 (constop + 1) >= 0
5850: && exact_log2 (INTVAL (XEXP (XEXP (varop, 0), 1)) + 1) >= 0
5851: && (~ INTVAL (XEXP (XEXP (varop, 0), 1)) & constop) == 0)
5852: SUBST (XEXP (varop, 0), XEXP (XEXP (varop, 0), 0));
5853: break;
5854: }
5855:
5856: break;
5857: }
5858:
5859: /* If we have reached a constant, this whole thing is constant. */
5860: if (GET_CODE (varop) == CONST_INT)
1.1.1.4 ! root 5861: return GEN_INT (constop & INTVAL (varop));
1.1 root 5862:
5863: /* See what bits are significant in VAROP. */
5864: significant = significant_bits (varop, mode);
5865:
5866: /* Turn off all bits in the constant that are known to already be zero.
5867: Thus, if the AND isn't needed at all, we will have CONSTOP == SIGNIFICANT
5868: which is tested below. */
5869:
5870: constop &= significant;
5871:
5872: /* If we don't have any bits left, return zero. */
5873: if (constop == 0)
5874: return const0_rtx;
5875:
5876: /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
5877: if we already had one (just check for the simplest cases). */
5878: if (x && GET_CODE (XEXP (x, 0)) == SUBREG
5879: && GET_MODE (XEXP (x, 0)) == mode
5880: && SUBREG_REG (XEXP (x, 0)) == varop)
5881: varop = XEXP (x, 0);
5882: else
5883: varop = gen_lowpart_for_combine (mode, varop);
5884:
5885: /* If we can't make the SUBREG, try to return what we were given. */
5886: if (GET_CODE (varop) == CLOBBER)
5887: return x ? x : varop;
5888:
5889: /* If we are only masking insignificant bits, return VAROP. */
5890: if (constop == significant)
5891: x = varop;
5892:
5893: /* Otherwise, return an AND. See how much, if any, of X we can use. */
5894: else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
1.1.1.4 ! root 5895: x = gen_rtx_combine (AND, mode, varop, GEN_INT (constop));
1.1 root 5896:
5897: else
5898: {
5899: if (GET_CODE (XEXP (x, 1)) != CONST_INT
5900: || INTVAL (XEXP (x, 1)) != constop)
1.1.1.4 ! root 5901: SUBST (XEXP (x, 1), GEN_INT (constop));
1.1 root 5902:
5903: SUBST (XEXP (x, 0), varop);
5904: }
5905:
5906: return x;
5907: }
5908:
5909: /* Given an expression, X, compute which bits in X can be non-zero.
5910: We don't care about bits outside of those defined in MODE.
5911:
5912: For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
5913: a shift, AND, or zero_extract, we can do better. */
5914:
1.1.1.4 ! root 5915: static unsigned HOST_WIDE_INT
1.1 root 5916: significant_bits (x, mode)
5917: rtx x;
5918: enum machine_mode mode;
5919: {
1.1.1.4 ! root 5920: unsigned HOST_WIDE_INT significant = GET_MODE_MASK (mode);
! 5921: unsigned HOST_WIDE_INT inner_sig;
1.1 root 5922: enum rtx_code code;
5923: int mode_width = GET_MODE_BITSIZE (mode);
5924: rtx tem;
5925:
5926: /* If X is wider than MODE, use its mode instead. */
5927: if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
5928: {
5929: mode = GET_MODE (x);
5930: significant = GET_MODE_MASK (mode);
5931: mode_width = GET_MODE_BITSIZE (mode);
5932: }
5933:
1.1.1.4 ! root 5934: if (mode_width > HOST_BITS_PER_WIDE_INT)
1.1 root 5935: /* Our only callers in this case look for single bit values. So
5936: just return the mode mask. Those tests will then be false. */
5937: return significant;
5938:
5939: code = GET_CODE (x);
5940: switch (code)
5941: {
5942: case REG:
5943: #ifdef STACK_BOUNDARY
5944: /* If this is the stack pointer, we may know something about its
5945: alignment. If PUSH_ROUNDING is defined, it is possible for the
5946: stack to be momentarily aligned only to that amount, so we pick
5947: the least alignment. */
5948:
5949: if (x == stack_pointer_rtx)
5950: {
5951: int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
5952:
5953: #ifdef PUSH_ROUNDING
5954: sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
5955: #endif
5956:
5957: return significant & ~ (sp_alignment - 1);
5958: }
5959: #endif
5960:
5961: /* If X is a register whose value we can find, use that value.
5962: Otherwise, use the previously-computed significant bits for this
5963: register. */
5964:
5965: tem = get_last_value (x);
5966: if (tem)
5967: return significant_bits (tem, mode);
5968: else if (significant_valid && reg_significant[REGNO (x)])
5969: return reg_significant[REGNO (x)] & significant;
5970: else
5971: return significant;
5972:
5973: case CONST_INT:
5974: return INTVAL (x);
5975:
5976: #ifdef BYTE_LOADS_ZERO_EXTEND
5977: case MEM:
5978: /* In many, if not most, RISC machines, reading a byte from memory
5979: zeros the rest of the register. Noticing that fact saves a lot
5980: of extra zero-extends. */
5981: significant &= GET_MODE_MASK (GET_MODE (x));
5982: break;
5983: #endif
5984:
5985: #if STORE_FLAG_VALUE == 1
5986: case EQ: case NE:
5987: case GT: case GTU:
5988: case LT: case LTU:
5989: case GE: case GEU:
5990: case LE: case LEU:
1.1.1.3 root 5991:
5992: if (GET_MODE_CLASS (mode) == MODE_INT)
5993: significant = 1;
1.1 root 5994:
5995: /* A comparison operation only sets the bits given by its mode. The
5996: rest are set undefined. */
5997: if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
5998: significant |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
5999: break;
6000: #endif
6001:
6002: case NEG:
1.1.1.4 ! root 6003: if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
! 6004: == GET_MODE_BITSIZE (GET_MODE (x)))
1.1 root 6005: significant = 1;
6006:
6007: if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
6008: significant |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
6009: break;
1.1.1.4 ! root 6010:
! 6011: case ABS:
! 6012: if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
! 6013: == GET_MODE_BITSIZE (GET_MODE (x)))
! 6014: significant = 1;
! 6015: break;
1.1 root 6016:
6017: case TRUNCATE:
6018: significant &= (significant_bits (XEXP (x, 0), mode)
6019: & GET_MODE_MASK (mode));
6020: break;
6021:
6022: case ZERO_EXTEND:
6023: significant &= significant_bits (XEXP (x, 0), mode);
6024: if (GET_MODE (XEXP (x, 0)) != VOIDmode)
6025: significant &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
6026: break;
6027:
6028: case SIGN_EXTEND:
6029: /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
6030: Otherwise, show all the bits in the outer mode but not the inner
6031: may be non-zero. */
6032: inner_sig = significant_bits (XEXP (x, 0), mode);
6033: if (GET_MODE (XEXP (x, 0)) != VOIDmode)
6034: {
6035: inner_sig &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
6036: if (inner_sig &
1.1.1.4 ! root 6037: (((HOST_WIDE_INT) 1
! 6038: << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
1.1 root 6039: inner_sig |= (GET_MODE_MASK (mode)
6040: & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
6041: }
6042:
6043: significant &= inner_sig;
6044: break;
6045:
6046: case AND:
6047: significant &= (significant_bits (XEXP (x, 0), mode)
6048: & significant_bits (XEXP (x, 1), mode));
6049: break;
6050:
1.1.1.4 ! root 6051: case XOR: case IOR:
! 6052: case UMIN: case UMAX: case SMIN: case SMAX:
1.1 root 6053: significant &= (significant_bits (XEXP (x, 0), mode)
6054: | significant_bits (XEXP (x, 1), mode));
6055: break;
6056:
6057: case PLUS: case MINUS:
6058: case MULT:
6059: case DIV: case UDIV:
6060: case MOD: case UMOD:
6061: /* We can apply the rules of arithmetic to compute the number of
6062: high- and low-order zero bits of these operations. We start by
6063: computing the width (position of the highest-order non-zero bit)
6064: and the number of low-order zero bits for each value. */
6065: {
1.1.1.4 ! root 6066: unsigned HOST_WIDE_INT sig0 = significant_bits (XEXP (x, 0), mode);
! 6067: unsigned HOST_WIDE_INT sig1 = significant_bits (XEXP (x, 1), mode);
1.1 root 6068: int width0 = floor_log2 (sig0) + 1;
6069: int width1 = floor_log2 (sig1) + 1;
6070: int low0 = floor_log2 (sig0 & -sig0);
6071: int low1 = floor_log2 (sig1 & -sig1);
6072: int op0_maybe_minusp = (sig0 & (1 << (mode_width - 1)));
6073: int op1_maybe_minusp = (sig1 & (1 << (mode_width - 1)));
6074: int result_width = mode_width;
6075: int result_low = 0;
6076:
6077: switch (code)
6078: {
6079: case PLUS:
6080: result_width = MAX (width0, width1) + 1;
6081: result_low = MIN (low0, low1);
6082: break;
6083: case MINUS:
6084: result_low = MIN (low0, low1);
6085: break;
6086: case MULT:
6087: result_width = width0 + width1;
6088: result_low = low0 + low1;
6089: break;
6090: case DIV:
6091: if (! op0_maybe_minusp && ! op1_maybe_minusp)
6092: result_width = width0;
6093: break;
6094: case UDIV:
6095: result_width = width0;
6096: break;
6097: case MOD:
6098: if (! op0_maybe_minusp && ! op1_maybe_minusp)
6099: result_width = MIN (width0, width1);
6100: result_low = MIN (low0, low1);
6101: break;
6102: case UMOD:
6103: result_width = MIN (width0, width1);
6104: result_low = MIN (low0, low1);
6105: break;
6106: }
6107:
6108: if (result_width < mode_width)
1.1.1.4 ! root 6109: significant &= ((HOST_WIDE_INT) 1 << result_width) - 1;
1.1 root 6110:
6111: if (result_low > 0)
1.1.1.4 ! root 6112: significant &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
1.1 root 6113: }
6114: break;
6115:
6116: case ZERO_EXTRACT:
6117: if (GET_CODE (XEXP (x, 1)) == CONST_INT
1.1.1.4 ! root 6118: && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
! 6119: significant &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
1.1 root 6120: break;
6121:
6122: case SUBREG:
1.1.1.4 ! root 6123: /* If this is a SUBREG formed for a promoted variable that has
! 6124: been zero-extended, we know that at least the high-order bits
! 6125: are zero, though others might be too. */
! 6126:
! 6127: if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
! 6128: significant = (GET_MODE_MASK (GET_MODE (x))
! 6129: & significant_bits (SUBREG_REG (x), GET_MODE (x)));
! 6130:
1.1 root 6131: /* If the inner mode is a single word for both the host and target
6132: machines, we can compute this from which bits of the inner
6133: object are known significant. */
6134: if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
1.1.1.4 ! root 6135: && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
! 6136: <= HOST_BITS_PER_WIDE_INT))
1.1 root 6137: {
6138: significant &= significant_bits (SUBREG_REG (x), mode);
1.1.1.4 ! root 6139: #if ! defined(BYTE_LOADS_ZERO_EXTEND) && ! defined(BYTE_LOADS_SIGN_EXTEND)
1.1 root 6140: /* On many CISC machines, accessing an object in a wider mode
6141: causes the high-order bits to become undefined. So they are
6142: not known to be zero. */
6143: if (GET_MODE_SIZE (GET_MODE (x))
6144: > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6145: significant |= (GET_MODE_MASK (GET_MODE (x))
6146: & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
6147: #endif
6148: }
6149: break;
6150:
6151: case ASHIFTRT:
6152: case LSHIFTRT:
6153: case ASHIFT:
6154: case LSHIFT:
6155: case ROTATE:
6156: /* The significant bits are in two classes: any bits within MODE
6157: that aren't in GET_MODE (x) are always significant. The rest of the
6158: significant bits are those that are significant in the operand of
6159: the shift when shifted the appropriate number of bits. This
6160: shows that high-order bits are cleared by the right shift and
6161: low-order bits by left shifts. */
6162: if (GET_CODE (XEXP (x, 1)) == CONST_INT
6163: && INTVAL (XEXP (x, 1)) >= 0
1.1.1.4 ! root 6164: && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
1.1 root 6165: {
6166: enum machine_mode inner_mode = GET_MODE (x);
6167: int width = GET_MODE_BITSIZE (inner_mode);
6168: int count = INTVAL (XEXP (x, 1));
1.1.1.4 ! root 6169: unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
! 6170: unsigned HOST_WIDE_INT op_significant
! 6171: = significant_bits (XEXP (x, 0), mode);
! 6172: unsigned HOST_WIDE_INT inner = op_significant & mode_mask;
! 6173: unsigned HOST_WIDE_INT outer = 0;
1.1 root 6174:
6175: if (mode_width > width)
6176: outer = (op_significant & significant & ~ mode_mask);
6177:
6178: if (code == LSHIFTRT)
6179: inner >>= count;
6180: else if (code == ASHIFTRT)
6181: {
6182: inner >>= count;
6183:
6184: /* If the sign bit was significant at before the shift, we
6185: need to mark all the places it could have been copied to
6186: by the shift significant. */
1.1.1.4 ! root 6187: if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
! 6188: inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
1.1 root 6189: }
6190: else if (code == LSHIFT || code == ASHIFT)
6191: inner <<= count;
6192: else
6193: inner = ((inner << (count % width)
6194: | (inner >> (width - (count % width)))) & mode_mask);
6195:
6196: significant &= (outer | inner);
6197: }
6198: break;
6199:
6200: case FFS:
6201: /* This is at most the number of bits in the mode. */
1.1.1.4 ! root 6202: significant = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
! 6203: break;
! 6204:
! 6205: case IF_THEN_ELSE:
! 6206: significant &= (significant_bits (XEXP (x, 1), mode)
! 6207: | significant_bits (XEXP (x, 2), mode));
1.1 root 6208: break;
6209: }
6210:
6211: return significant;
6212: }
6213:
1.1.1.4 ! root 6214: /* Return the number of bits at the high-order end of X that are known to
! 6215: be equal to the sign bit. This number will always be between 1 and
! 6216: the number of bits in the mode of X. MODE is the mode to be used
! 6217: if X is VOIDmode. */
! 6218:
! 6219: static int
! 6220: num_sign_bit_copies (x, mode)
! 6221: rtx x;
! 6222: enum machine_mode mode;
! 6223: {
! 6224: enum rtx_code code = GET_CODE (x);
! 6225: int bitwidth;
! 6226: int num0, num1, result;
! 6227: unsigned HOST_WIDE_INT sig;
! 6228: rtx tem;
! 6229:
! 6230: /* If we weren't given a mode, use the mode of X. If the mode is still
! 6231: VOIDmode, we don't know anything. */
! 6232:
! 6233: if (mode == VOIDmode)
! 6234: mode = GET_MODE (x);
! 6235:
! 6236: if (mode == VOIDmode)
! 6237: return 1;
! 6238:
! 6239: bitwidth = GET_MODE_BITSIZE (mode);
! 6240:
! 6241: switch (code)
! 6242: {
! 6243: case REG:
! 6244: if (significant_valid && reg_sign_bit_copies[REGNO (x)] != 0)
! 6245: return reg_sign_bit_copies[REGNO (x)];
! 6246:
! 6247: tem = get_last_value (x);
! 6248: if (tem != 0)
! 6249: return num_sign_bit_copies (tem, mode);
! 6250: break;
! 6251:
! 6252: #ifdef BYTE_LOADS_SIGN_EXTEND
! 6253: case MEM:
! 6254: /* Some RISC machines sign-extend all loads of smaller than a word. */
! 6255: return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
! 6256: #endif
! 6257:
! 6258: case CONST_INT:
! 6259: /* If the constant is negative, take its 1's complement and remask.
! 6260: Then see how many zero bits we have. */
! 6261: sig = INTVAL (x) & GET_MODE_MASK (mode);
! 6262: if (bitwidth <= HOST_BITS_PER_WIDE_INT
! 6263: && (sig & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
! 6264: sig = (~ sig) & GET_MODE_MASK (mode);
! 6265:
! 6266: return (sig == 0 ? bitwidth : bitwidth - floor_log2 (sig) - 1);
! 6267:
! 6268: case SUBREG:
! 6269: /* If this is a SUBREG for a promoted object that is sign-extended
! 6270: and we are looking at it in a wider mode, we know that at least the
! 6271: high-order bits are known to be sign bit copies. */
! 6272:
! 6273: if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
! 6274: return (GET_MODE_BITSIZE (mode) - GET_MODE_BITSIZE (GET_MODE (x))
! 6275: + num_sign_bit_copies (SUBREG_REG (x), GET_MODE (x)));
! 6276:
! 6277: /* For a smaller object, just ignore the high bits. */
! 6278: if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
! 6279: {
! 6280: num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
! 6281: return MAX (1, (num0
! 6282: - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
! 6283: - bitwidth)));
! 6284: }
! 6285:
! 6286: #if defined(BYTE_LOADS_ZERO_EXTEND) || defined(BYTE_LOADS_SIGN_EXTEND)
! 6287: /* For paradoxical SUBREGs, just look inside since, on machines with
! 6288: one of these defined, we assume that operations are actually
! 6289: performed on the full register. Note that we are passing MODE
! 6290: to the recursive call, so the number of sign bit copies will
! 6291: remain relative to that mode, not the inner mode. */
! 6292:
! 6293: if (GET_MODE_SIZE (GET_MODE (x))
! 6294: > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
! 6295: return num_sign_bit_copies (SUBREG_REG (x), mode);
! 6296: #endif
! 6297:
! 6298: break;
! 6299:
! 6300: case SIGN_EXTRACT:
! 6301: if (GET_CODE (XEXP (x, 1)) == CONST_INT)
! 6302: return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
! 6303: break;
! 6304:
! 6305: case SIGN_EXTEND:
! 6306: return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
! 6307: + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
! 6308:
! 6309: case TRUNCATE:
! 6310: /* For a smaller object, just ignore the high bits. */
! 6311: num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
! 6312: return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
! 6313: - bitwidth)));
! 6314:
! 6315: case NOT:
! 6316: return num_sign_bit_copies (XEXP (x, 0), mode);
! 6317:
! 6318: case ROTATE: case ROTATERT:
! 6319: /* If we are rotating left by a number of bits less than the number
! 6320: of sign bit copies, we can just subtract that amount from the
! 6321: number. */
! 6322: if (GET_CODE (XEXP (x, 1)) == CONST_INT
! 6323: && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
! 6324: {
! 6325: num0 = num_sign_bit_copies (XEXP (x, 0), mode);
! 6326: return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
! 6327: : bitwidth - INTVAL (XEXP (x, 1))));
! 6328: }
! 6329: break;
! 6330:
! 6331: case NEG:
! 6332: /* In general, this subtracts one sign bit copy. But if the value
! 6333: is known to be positive, the number of sign bit copies is the
! 6334: same as that of the input. Finally, if the input has just one
! 6335: significant bit, all the bits are copies of the sign bit. */
! 6336: sig = significant_bits (XEXP (x, 0), mode);
! 6337: if (sig == 1)
! 6338: return bitwidth;
! 6339:
! 6340: num0 = num_sign_bit_copies (XEXP (x, 0), mode);
! 6341: if (num0 > 1
! 6342: && bitwidth <= HOST_BITS_PER_WIDE_INT
! 6343: && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & sig))
! 6344: num0--;
! 6345:
! 6346: return num0;
! 6347:
! 6348: case IOR: case AND: case XOR:
! 6349: case SMIN: case SMAX: case UMIN: case UMAX:
! 6350: /* Logical operations will preserve the number of sign-bit copies.
! 6351: MIN and MAX operations always return one of the operands. */
! 6352: num0 = num_sign_bit_copies (XEXP (x, 0), mode);
! 6353: num1 = num_sign_bit_copies (XEXP (x, 1), mode);
! 6354: return MIN (num0, num1);
! 6355:
! 6356: case PLUS: case MINUS:
! 6357: /* For addition and subtraction, we can have a 1-bit carry. However,
! 6358: if we are subtracting 1 from a positive number, there will not
! 6359: be such a carry. Furthermore, if the positive number is known to
! 6360: be 0 or 1, we know the result is either -1 or 0. */
! 6361:
! 6362: if (code == PLUS && XEXP (x, 1) == constm1_rtx
! 6363: /* Don't do this if XEXP (x, 0) is a paradoxical subreg
! 6364: because in principle we don't know what the high bits are. */
! 6365: && !(GET_CODE (XEXP (x, 0)) == SUBREG
! 6366: && (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
! 6367: < GET_MODE_SIZE (GET_MODE (XEXP (x, 0))))))
! 6368: {
! 6369: sig = significant_bits (XEXP (x, 0), mode);
! 6370: if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & sig) == 0)
! 6371: return (sig == 1 || sig == 0 ? bitwidth
! 6372: : bitwidth - floor_log2 (sig) - 1);
! 6373: }
! 6374:
! 6375: num0 = num_sign_bit_copies (XEXP (x, 0), mode);
! 6376: num1 = num_sign_bit_copies (XEXP (x, 1), mode);
! 6377: return MAX (1, MIN (num0, num1) - 1);
! 6378:
! 6379: case MULT:
! 6380: /* The number of bits of the product is the sum of the number of
! 6381: bits of both terms. However, unless one of the terms if known
! 6382: to be positive, we must allow for an additional bit since negating
! 6383: a negative number can remove one sign bit copy. */
! 6384:
! 6385: num0 = num_sign_bit_copies (XEXP (x, 0), mode);
! 6386: num1 = num_sign_bit_copies (XEXP (x, 1), mode);
! 6387:
! 6388: result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
! 6389: if (result > 0
! 6390: && bitwidth <= HOST_BITS_PER_INT
! 6391: && ((significant_bits (XEXP (x, 0), mode)
! 6392: & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
! 6393: && (significant_bits (XEXP (x, 1), mode)
! 6394: & ((HOST_WIDE_INT) 1 << (bitwidth - 1)) != 0))
! 6395: result--;
! 6396:
! 6397: return MAX (1, result);
! 6398:
! 6399: case UDIV:
! 6400: /* The result must be <= the first operand. */
! 6401: return num_sign_bit_copies (XEXP (x, 0), mode);
! 6402:
! 6403: case UMOD:
! 6404: /* The result must be <= the scond operand. */
! 6405: return num_sign_bit_copies (XEXP (x, 1), mode);
! 6406:
! 6407: case DIV:
! 6408: /* Similar to unsigned division, except that we have to worry about
! 6409: the case where the divisor is negative, in which case we have
! 6410: to add 1. */
! 6411: result = num_sign_bit_copies (XEXP (x, 0), mode);
! 6412: if (result > 1
! 6413: && bitwidth <= HOST_BITS_PER_WIDE_INT
! 6414: && (significant_bits (XEXP (x, 1), mode)
! 6415: & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
! 6416: result --;
! 6417:
! 6418: return result;
! 6419:
! 6420: case MOD:
! 6421: result = num_sign_bit_copies (XEXP (x, 1), mode);
! 6422: if (result > 1
! 6423: && bitwidth <= HOST_BITS_PER_WIDE_INT
! 6424: && (significant_bits (XEXP (x, 1), mode)
! 6425: & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
! 6426: result --;
! 6427:
! 6428: return result;
! 6429:
! 6430: case ASHIFTRT:
! 6431: /* Shifts by a constant add to the number of bits equal to the
! 6432: sign bit. */
! 6433: num0 = num_sign_bit_copies (XEXP (x, 0), mode);
! 6434: if (GET_CODE (XEXP (x, 1)) == CONST_INT
! 6435: && INTVAL (XEXP (x, 1)) > 0)
! 6436: num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
! 6437:
! 6438: return num0;
! 6439:
! 6440: case ASHIFT:
! 6441: case LSHIFT:
! 6442: /* Left shifts destroy copies. */
! 6443: if (GET_CODE (XEXP (x, 1)) != CONST_INT
! 6444: || INTVAL (XEXP (x, 1)) < 0
! 6445: || INTVAL (XEXP (x, 1)) >= bitwidth)
! 6446: return 1;
! 6447:
! 6448: num0 = num_sign_bit_copies (XEXP (x, 0), mode);
! 6449: return MAX (1, num0 - INTVAL (XEXP (x, 1)));
! 6450:
! 6451: case IF_THEN_ELSE:
! 6452: num0 = num_sign_bit_copies (XEXP (x, 1), mode);
! 6453: num1 = num_sign_bit_copies (XEXP (x, 2), mode);
! 6454: return MIN (num0, num1);
! 6455:
! 6456: #if STORE_FLAG_VALUE == -1
! 6457: case EQ: case NE: case GE: case GT: case LE: case LT:
! 6458: case GEU: case GTU: case LEU: case LTU:
! 6459: return bitwidth;
! 6460: #endif
! 6461: }
! 6462:
! 6463: /* If we haven't been able to figure it out by one of the above rules,
! 6464: see if some of the high-order bits are known to be zero. If so,
! 6465: count those bits and return one less than that amount. If we can't
! 6466: safely compute the mask for this mode, always return BITWIDTH. */
! 6467:
! 6468: if (bitwidth > HOST_BITS_PER_WIDE_INT)
! 6469: return 1;
! 6470:
! 6471: sig = significant_bits (x, mode);
! 6472: return sig == GET_MODE_MASK (mode) ? 1 : bitwidth - floor_log2 (sig) - 1;
! 6473: }
! 6474:
! 6475: /* Return the number of "extended" bits there are in X, when interpreted
! 6476: as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
! 6477: unsigned quantities, this is the number of high-order zero bits.
! 6478: For signed quantities, this is the number of copies of the sign bit
! 6479: minus 1. In both case, this function returns the number of "spare"
! 6480: bits. For example, if two quantities for which this function returns
! 6481: at least 1 are added, the addition is known not to overflow.
! 6482:
! 6483: This function will always return 0 unless called during combine, which
! 6484: implies that it must be called from a define_split. */
! 6485:
! 6486: int
! 6487: extended_count (x, mode, unsignedp)
! 6488: rtx x;
! 6489: enum machine_mode mode;
! 6490: int unsignedp;
! 6491: {
! 6492: if (significant_valid == 0)
! 6493: return 0;
! 6494:
! 6495: return (unsignedp
! 6496: ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
! 6497: && (GET_MODE_BITSIZE (mode) - 1
! 6498: - floor_log2 (significant_bits (x, mode))))
! 6499: : num_sign_bit_copies (x, mode) - 1);
! 6500: }
! 6501:
1.1 root 6502: /* This function is called from `simplify_shift_const' to merge two
6503: outer operations. Specifically, we have already found that we need
6504: to perform operation *POP0 with constant *PCONST0 at the outermost
6505: position. We would now like to also perform OP1 with constant CONST1
6506: (with *POP0 being done last).
6507:
6508: Return 1 if we can do the operation and update *POP0 and *PCONST0 with
6509: the resulting operation. *PCOMP_P is set to 1 if we would need to
6510: complement the innermost operand, otherwise it is unchanged.
6511:
6512: MODE is the mode in which the operation will be done. No bits outside
6513: the width of this mode matter. It is assumed that the width of this mode
1.1.1.4 ! root 6514: is smaller than or equal to HOST_BITS_PER_WIDE_INT.
1.1 root 6515:
6516: If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
6517: IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
6518: result is simply *PCONST0.
6519:
6520: If the resulting operation cannot be expressed as one operation, we
6521: return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
6522:
6523: static int
6524: merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
6525: enum rtx_code *pop0;
1.1.1.4 ! root 6526: HOST_WIDE_INT *pconst0;
1.1 root 6527: enum rtx_code op1;
1.1.1.4 ! root 6528: HOST_WIDE_INT const1;
1.1 root 6529: enum machine_mode mode;
6530: int *pcomp_p;
6531: {
6532: enum rtx_code op0 = *pop0;
1.1.1.4 ! root 6533: HOST_WIDE_INT const0 = *pconst0;
1.1 root 6534:
6535: const0 &= GET_MODE_MASK (mode);
6536: const1 &= GET_MODE_MASK (mode);
6537:
6538: /* If OP0 is an AND, clear unimportant bits in CONST1. */
6539: if (op0 == AND)
6540: const1 &= const0;
6541:
6542: /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
6543: if OP0 is SET. */
6544:
6545: if (op1 == NIL || op0 == SET)
6546: return 1;
6547:
6548: else if (op0 == NIL)
6549: op0 = op1, const0 = const1;
6550:
6551: else if (op0 == op1)
6552: {
6553: switch (op0)
6554: {
6555: case AND:
6556: const0 &= const1;
6557: break;
6558: case IOR:
6559: const0 |= const1;
6560: break;
6561: case XOR:
6562: const0 ^= const1;
6563: break;
6564: case PLUS:
6565: const0 += const1;
6566: break;
6567: case NEG:
6568: op0 = NIL;
6569: break;
6570: }
6571: }
6572:
6573: /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
6574: else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
6575: return 0;
6576:
6577: /* If the two constants aren't the same, we can't do anything. The
6578: remaining six cases can all be done. */
6579: else if (const0 != const1)
6580: return 0;
6581:
6582: else
6583: switch (op0)
6584: {
6585: case IOR:
6586: if (op1 == AND)
6587: /* (a & b) | b == b */
6588: op0 = SET;
6589: else /* op1 == XOR */
6590: /* (a ^ b) | b == a | b */
6591: ;
6592: break;
6593:
6594: case XOR:
6595: if (op1 == AND)
6596: /* (a & b) ^ b == (~a) & b */
6597: op0 = AND, *pcomp_p = 1;
6598: else /* op1 == IOR */
6599: /* (a | b) ^ b == a & ~b */
6600: op0 = AND, *pconst0 = ~ const0;
6601: break;
6602:
6603: case AND:
6604: if (op1 == IOR)
6605: /* (a | b) & b == b */
6606: op0 = SET;
6607: else /* op1 == XOR */
6608: /* (a ^ b) & b) == (~a) & b */
6609: *pcomp_p = 1;
6610: break;
6611: }
6612:
6613: /* Check for NO-OP cases. */
6614: const0 &= GET_MODE_MASK (mode);
6615: if (const0 == 0
6616: && (op0 == IOR || op0 == XOR || op0 == PLUS))
6617: op0 = NIL;
6618: else if (const0 == 0 && op0 == AND)
6619: op0 = SET;
6620: else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
6621: op0 = NIL;
6622:
6623: *pop0 = op0;
6624: *pconst0 = const0;
6625:
6626: return 1;
6627: }
6628:
6629: /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
6630: The result of the shift is RESULT_MODE. X, if non-zero, is an expression
6631: that we started with.
6632:
6633: The shift is normally computed in the widest mode we find in VAROP, as
6634: long as it isn't a different number of words than RESULT_MODE. Exceptions
6635: are ASHIFTRT and ROTATE, which are always done in their original mode, */
6636:
6637: static rtx
6638: simplify_shift_const (x, code, result_mode, varop, count)
6639: rtx x;
6640: enum rtx_code code;
6641: enum machine_mode result_mode;
6642: rtx varop;
6643: int count;
6644: {
6645: enum rtx_code orig_code = code;
6646: int orig_count = count;
6647: enum machine_mode mode = result_mode;
6648: enum machine_mode shift_mode, tmode;
6649: int mode_words
6650: = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
6651: /* We form (outer_op (code varop count) (outer_const)). */
6652: enum rtx_code outer_op = NIL;
1.1.1.4 ! root 6653: HOST_WIDE_INT outer_const;
1.1 root 6654: rtx const_rtx;
6655: int complement_p = 0;
6656: rtx new;
6657:
6658: /* If we were given an invalid count, don't do anything except exactly
6659: what was requested. */
6660:
6661: if (count < 0 || count > GET_MODE_BITSIZE (mode))
6662: {
6663: if (x)
6664: return x;
6665:
1.1.1.4 ! root 6666: return gen_rtx (code, mode, varop, GEN_INT (count));
1.1 root 6667: }
6668:
6669: /* Unless one of the branches of the `if' in this loop does a `continue',
6670: we will `break' the loop after the `if'. */
6671:
6672: while (count != 0)
6673: {
6674: /* If we have an operand of (clobber (const_int 0)), just return that
6675: value. */
6676: if (GET_CODE (varop) == CLOBBER)
6677: return varop;
6678:
6679: /* If we discovered we had to complement VAROP, leave. Making a NOT
6680: here would cause an infinite loop. */
6681: if (complement_p)
6682: break;
6683:
6684: /* Convert ROTATETRT to ROTATE. */
6685: if (code == ROTATERT)
6686: code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
6687:
6688: /* Canonicalize LSHIFT to ASHIFT. */
6689: if (code == LSHIFT)
6690: code = ASHIFT;
6691:
6692: /* We need to determine what mode we will do the shift in. If the
6693: shift is a ASHIFTRT or ROTATE, we must always do it in the mode it
6694: was originally done in. Otherwise, we can do it in MODE, the widest
6695: mode encountered. */
6696: shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
6697:
6698: /* Handle cases where the count is greater than the size of the mode
6699: minus 1. For ASHIFT, use the size minus one as the count (this can
6700: occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
6701: take the count modulo the size. For other shifts, the result is
6702: zero.
6703:
6704: Since these shifts are being produced by the compiler by combining
6705: multiple operations, each of which are defined, we know what the
6706: result is supposed to be. */
6707:
6708: if (count > GET_MODE_BITSIZE (shift_mode) - 1)
6709: {
6710: if (code == ASHIFTRT)
6711: count = GET_MODE_BITSIZE (shift_mode) - 1;
6712: else if (code == ROTATE || code == ROTATERT)
6713: count %= GET_MODE_BITSIZE (shift_mode);
6714: else
6715: {
6716: /* We can't simply return zero because there may be an
6717: outer op. */
6718: varop = const0_rtx;
6719: count = 0;
6720: break;
6721: }
6722: }
6723:
6724: /* Negative counts are invalid and should not have been made (a
6725: programmer-specified negative count should have been handled
6726: above). */
6727: else if (count < 0)
6728: abort ();
6729:
1.1.1.4 ! root 6730: /* An arithmetic right shift of a quantity known to be -1 or 0
! 6731: is a no-op. */
! 6732: if (code == ASHIFTRT
! 6733: && (num_sign_bit_copies (varop, shift_mode)
! 6734: == GET_MODE_BITSIZE (shift_mode)))
! 6735: {
! 6736: count = 0;
! 6737: break;
! 6738: }
! 6739:
1.1 root 6740: /* We simplify the tests below and elsewhere by converting
6741: ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
6742: `make_compound_operation' will convert it to a ASHIFTRT for
6743: those machines (such as Vax) that don't have a LSHIFTRT. */
1.1.1.4 ! root 6744: if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
1.1 root 6745: && code == ASHIFTRT
1.1.1.4 ! root 6746: && ((significant_bits (varop, shift_mode)
! 6747: & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
! 6748: == 0))
1.1 root 6749: code = LSHIFTRT;
6750:
6751: switch (GET_CODE (varop))
6752: {
6753: case SIGN_EXTEND:
6754: case ZERO_EXTEND:
6755: case SIGN_EXTRACT:
6756: case ZERO_EXTRACT:
6757: new = expand_compound_operation (varop);
6758: if (new != varop)
6759: {
6760: varop = new;
6761: continue;
6762: }
6763: break;
6764:
6765: case MEM:
6766: /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
6767: minus the width of a smaller mode, we can do this with a
6768: SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
6769: if ((code == ASHIFTRT || code == LSHIFTRT)
6770: && ! mode_dependent_address_p (XEXP (varop, 0))
6771: && ! MEM_VOLATILE_P (varop)
6772: && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
6773: MODE_INT, 1)) != BLKmode)
6774: {
6775: #if BYTES_BIG_ENDIAN
6776: new = gen_rtx (MEM, tmode, XEXP (varop, 0));
6777: #else
6778: new = gen_rtx (MEM, tmode,
6779: plus_constant (XEXP (varop, 0),
6780: count / BITS_PER_UNIT));
6781: RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
6782: MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
6783: MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
6784: #endif
6785: varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
6786: : ZERO_EXTEND, mode, new);
6787: count = 0;
6788: continue;
6789: }
6790: break;
6791:
6792: case USE:
6793: /* Similar to the case above, except that we can only do this if
6794: the resulting mode is the same as that of the underlying
6795: MEM and adjust the address depending on the *bits* endianness
6796: because of the way that bit-field extract insns are defined. */
6797: if ((code == ASHIFTRT || code == LSHIFTRT)
6798: && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
6799: MODE_INT, 1)) != BLKmode
6800: && tmode == GET_MODE (XEXP (varop, 0)))
6801: {
6802: #if BITS_BIG_ENDIAN
6803: new = XEXP (varop, 0);
6804: #else
6805: new = copy_rtx (XEXP (varop, 0));
6806: SUBST (XEXP (new, 0),
6807: plus_constant (XEXP (new, 0),
6808: count / BITS_PER_UNIT));
6809: #endif
6810:
6811: varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
6812: : ZERO_EXTEND, mode, new);
6813: count = 0;
6814: continue;
6815: }
6816: break;
6817:
6818: case SUBREG:
6819: /* If VAROP is a SUBREG, strip it as long as the inner operand has
6820: the same number of words as what we've seen so far. Then store
6821: the widest mode in MODE. */
1.1.1.4 ! root 6822: if (subreg_lowpart_p (varop)
! 6823: && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
! 6824: > GET_MODE_SIZE (GET_MODE (varop)))
1.1 root 6825: && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
6826: + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6827: == mode_words))
6828: {
6829: varop = SUBREG_REG (varop);
6830: if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
6831: mode = GET_MODE (varop);
6832: continue;
6833: }
6834: break;
6835:
6836: case MULT:
6837: /* Some machines use MULT instead of ASHIFT because MULT
6838: is cheaper. But it is still better on those machines to
6839: merge two shifts into one. */
6840: if (GET_CODE (XEXP (varop, 1)) == CONST_INT
6841: && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
6842: {
6843: varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
1.1.1.4 ! root 6844: GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
1.1 root 6845: continue;
6846: }
6847: break;
6848:
6849: case UDIV:
6850: /* Similar, for when divides are cheaper. */
6851: if (GET_CODE (XEXP (varop, 1)) == CONST_INT
6852: && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
6853: {
6854: varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
1.1.1.4 ! root 6855: GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
1.1 root 6856: continue;
6857: }
6858: break;
6859:
6860: case ASHIFTRT:
6861: /* If we are extracting just the sign bit of an arithmetic right
6862: shift, that shift is not needed. */
6863: if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
6864: {
6865: varop = XEXP (varop, 0);
6866: continue;
6867: }
6868:
6869: /* ... fall through ... */
6870:
6871: case LSHIFTRT:
6872: case ASHIFT:
6873: case LSHIFT:
6874: case ROTATE:
6875: /* Here we have two nested shifts. The result is usually the
6876: AND of a new shift with a mask. We compute the result below. */
6877: if (GET_CODE (XEXP (varop, 1)) == CONST_INT
6878: && INTVAL (XEXP (varop, 1)) >= 0
6879: && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
1.1.1.4 ! root 6880: && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
! 6881: && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
1.1 root 6882: {
6883: enum rtx_code first_code = GET_CODE (varop);
6884: int first_count = INTVAL (XEXP (varop, 1));
1.1.1.4 ! root 6885: unsigned HOST_WIDE_INT mask;
1.1 root 6886: rtx mask_rtx;
6887: rtx inner;
6888:
6889: if (first_code == LSHIFT)
6890: first_code = ASHIFT;
6891:
6892: /* We have one common special case. We can't do any merging if
6893: the inner code is an ASHIFTRT of a smaller mode. However, if
6894: we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
6895: with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
6896: we can convert it to
6897: (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
6898: This simplifies certain SIGN_EXTEND operations. */
6899: if (code == ASHIFT && first_code == ASHIFTRT
6900: && (GET_MODE_BITSIZE (result_mode)
6901: - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
6902: {
6903: /* C3 has the low-order C1 bits zero. */
6904:
1.1.1.4 ! root 6905: mask = (GET_MODE_MASK (mode)
! 6906: & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
1.1 root 6907:
1.1.1.4 ! root 6908: varop = simplify_and_const_int (NULL_RTX, result_mode,
1.1 root 6909: XEXP (varop, 0), mask);
1.1.1.4 ! root 6910: varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
1.1 root 6911: varop, count);
6912: count = first_count;
6913: code = ASHIFTRT;
6914: continue;
6915: }
6916:
1.1.1.4 ! root 6917: /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
! 6918: than C1 high-order bits equal to the sign bit, we can convert
! 6919: this to either an ASHIFT or a ASHIFTRT depending on the
! 6920: two counts.
1.1 root 6921:
6922: We cannot do this if VAROP's mode is not SHIFT_MODE. */
6923:
6924: if (code == ASHIFTRT && first_code == ASHIFT
6925: && GET_MODE (varop) == shift_mode
1.1.1.4 ! root 6926: && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
! 6927: > first_count))
1.1 root 6928: {
1.1.1.4 ! root 6929: count -= first_count;
! 6930: if (count < 0)
! 6931: count = - count, code = ASHIFT;
! 6932: varop = XEXP (varop, 0);
! 6933: continue;
1.1 root 6934: }
6935:
6936: /* There are some cases we can't do. If CODE is ASHIFTRT,
6937: we can only do this if FIRST_CODE is also ASHIFTRT.
6938:
6939: We can't do the case when CODE is ROTATE and FIRST_CODE is
6940: ASHIFTRT.
6941:
6942: If the mode of this shift is not the mode of the outer shift,
6943: we can't do this if either shift is ASHIFTRT or ROTATE.
6944:
6945: Finally, we can't do any of these if the mode is too wide
6946: unless the codes are the same.
6947:
6948: Handle the case where the shift codes are the same
6949: first. */
6950:
6951: if (code == first_code)
6952: {
6953: if (GET_MODE (varop) != result_mode
6954: && (code == ASHIFTRT || code == ROTATE))
6955: break;
6956:
6957: count += first_count;
6958: varop = XEXP (varop, 0);
6959: continue;
6960: }
6961:
6962: if (code == ASHIFTRT
6963: || (code == ROTATE && first_code == ASHIFTRT)
1.1.1.4 ! root 6964: || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
1.1 root 6965: || (GET_MODE (varop) != result_mode
6966: && (first_code == ASHIFTRT || first_code == ROTATE
6967: || code == ROTATE)))
6968: break;
6969:
6970: /* To compute the mask to apply after the shift, shift the
6971: significant bits of the inner shift the same way the
6972: outer shift will. */
6973:
1.1.1.4 ! root 6974: mask_rtx = GEN_INT (significant_bits (varop, GET_MODE (varop)));
1.1 root 6975:
6976: mask_rtx
6977: = simplify_binary_operation (code, result_mode, mask_rtx,
1.1.1.4 ! root 6978: GEN_INT (count));
1.1 root 6979:
6980: /* Give up if we can't compute an outer operation to use. */
6981: if (mask_rtx == 0
6982: || GET_CODE (mask_rtx) != CONST_INT
6983: || ! merge_outer_ops (&outer_op, &outer_const, AND,
6984: INTVAL (mask_rtx),
6985: result_mode, &complement_p))
6986: break;
6987:
6988: /* If the shifts are in the same direction, we add the
6989: counts. Otherwise, we subtract them. */
6990: if ((code == ASHIFTRT || code == LSHIFTRT)
6991: == (first_code == ASHIFTRT || first_code == LSHIFTRT))
6992: count += first_count;
6993: else
6994: count -= first_count;
6995:
6996: /* If COUNT is positive, the new shift is usually CODE,
6997: except for the two exceptions below, in which case it is
6998: FIRST_CODE. If the count is negative, FIRST_CODE should
6999: always be used */
7000: if (count > 0
7001: && ((first_code == ROTATE && code == ASHIFT)
7002: || (first_code == ASHIFTRT && code == LSHIFTRT)))
7003: code = first_code;
7004: else if (count < 0)
7005: code = first_code, count = - count;
7006:
7007: varop = XEXP (varop, 0);
7008: continue;
7009: }
7010:
7011: /* If we have (A << B << C) for any shift, we can convert this to
7012: (A << C << B). This wins if A is a constant. Only try this if
7013: B is not a constant. */
7014:
7015: else if (GET_CODE (varop) == code
7016: && GET_CODE (XEXP (varop, 1)) != CONST_INT
7017: && 0 != (new
7018: = simplify_binary_operation (code, mode,
7019: XEXP (varop, 0),
1.1.1.4 ! root 7020: GEN_INT (count))))
1.1 root 7021: {
7022: varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
7023: count = 0;
7024: continue;
7025: }
7026: break;
7027:
7028: case NOT:
7029: /* Make this fit the case below. */
7030: varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
1.1.1.4 ! root 7031: GEN_INT (GET_MODE_MASK (mode)));
1.1 root 7032: continue;
7033:
7034: case IOR:
7035: case AND:
7036: case XOR:
7037: /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
7038: with C the size of VAROP - 1 and the shift is logical if
7039: STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
7040: we have an (le X 0) operation. If we have an arithmetic shift
7041: and STORE_FLAG_VALUE is 1 or we have a logical shift with
7042: STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
7043:
7044: if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
7045: && XEXP (XEXP (varop, 0), 1) == constm1_rtx
7046: && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7047: && (code == LSHIFTRT || code == ASHIFTRT)
7048: && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
7049: && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
7050: {
7051: count = 0;
7052: varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
7053: const0_rtx);
7054:
7055: if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
7056: varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
7057:
7058: continue;
7059: }
7060:
7061: /* If we have (shift (logical)), move the logical to the outside
7062: to allow it to possibly combine with another logical and the
7063: shift to combine with another shift. This also canonicalizes to
7064: what a ZERO_EXTRACT looks like. Also, some machines have
7065: (and (shift)) insns. */
7066:
7067: if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7068: && (new = simplify_binary_operation (code, result_mode,
7069: XEXP (varop, 1),
1.1.1.4 ! root 7070: GEN_INT (count))) != 0
1.1 root 7071: && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
7072: INTVAL (new), result_mode, &complement_p))
7073: {
7074: varop = XEXP (varop, 0);
7075: continue;
7076: }
7077:
7078: /* If we can't do that, try to simplify the shift in each arm of the
7079: logical expression, make a new logical expression, and apply
7080: the inverse distributive law. */
7081: {
1.1.1.4 ! root 7082: rtx lhs = simplify_shift_const (NULL_RTX, code, result_mode,
1.1 root 7083: XEXP (varop, 0), count);
1.1.1.4 ! root 7084: rtx rhs = simplify_shift_const (NULL_RTX, code, result_mode,
1.1 root 7085: XEXP (varop, 1), count);
7086:
7087: varop = gen_binary (GET_CODE (varop), result_mode, lhs, rhs);
7088: varop = apply_distributive_law (varop);
7089:
7090: count = 0;
7091: }
7092: break;
7093:
7094: case EQ:
7095: /* convert (lshift (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
7096: says that the sign bit can be tested, FOO has mode MODE, C is
7097: GET_MODE_BITSIZE (MODE) - 1, and FOO has only the low-order bit
7098: significant. */
7099: if (code == LSHIFT
7100: && XEXP (varop, 1) == const0_rtx
7101: && GET_MODE (XEXP (varop, 0)) == result_mode
7102: && count == GET_MODE_BITSIZE (result_mode) - 1
1.1.1.4 ! root 7103: && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
1.1 root 7104: && ((STORE_FLAG_VALUE
1.1.1.4 ! root 7105: & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
1.1 root 7106: && significant_bits (XEXP (varop, 0), result_mode) == 1
1.1.1.4 ! root 7107: && merge_outer_ops (&outer_op, &outer_const, XOR,
! 7108: (HOST_WIDE_INT) 1, result_mode,
! 7109: &complement_p))
1.1 root 7110: {
7111: varop = XEXP (varop, 0);
7112: count = 0;
7113: continue;
7114: }
7115: break;
7116:
7117: case NEG:
1.1.1.4 ! root 7118: /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
! 7119: than the number of bits in the mode is equivalent to A. */
! 7120: if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
1.1 root 7121: && significant_bits (XEXP (varop, 0), result_mode) == 1)
7122: {
1.1.1.4 ! root 7123: varop = XEXP (varop, 0);
1.1 root 7124: count = 0;
7125: continue;
7126: }
7127:
7128: /* NEG commutes with ASHIFT since it is multiplication. Move the
7129: NEG outside to allow shifts to combine. */
7130: if (code == ASHIFT
1.1.1.4 ! root 7131: && merge_outer_ops (&outer_op, &outer_const, NEG,
! 7132: (HOST_WIDE_INT) 0, result_mode,
! 7133: &complement_p))
1.1 root 7134: {
7135: varop = XEXP (varop, 0);
7136: continue;
7137: }
7138: break;
7139:
7140: case PLUS:
1.1.1.4 ! root 7141: /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
! 7142: is one less than the number of bits in the mode is
! 7143: equivalent to (xor A 1). */
1.1 root 7144: if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
7145: && XEXP (varop, 1) == constm1_rtx
7146: && significant_bits (XEXP (varop, 0), result_mode) == 1
1.1.1.4 ! root 7147: && merge_outer_ops (&outer_op, &outer_const, XOR,
! 7148: (HOST_WIDE_INT) 1, result_mode,
! 7149: &complement_p))
1.1 root 7150: {
7151: count = 0;
7152: varop = XEXP (varop, 0);
7153: continue;
7154: }
7155:
1.1.1.3 root 7156: /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
7157: significant in BAR are those being shifted out and those
7158: bits are known zero in FOO, we can replace the PLUS with FOO.
7159: Similarly in the other operand order. This code occurs when
7160: we are computing the size of a variable-size array. */
7161:
7162: if ((code == ASHIFTRT || code == LSHIFTRT)
1.1.1.4 ! root 7163: && count < HOST_BITS_PER_WIDE_INT
1.1.1.3 root 7164: && significant_bits (XEXP (varop, 1), result_mode) >> count == 0
7165: && (significant_bits (XEXP (varop, 1), result_mode)
7166: & significant_bits (XEXP (varop, 0), result_mode)) == 0)
7167: {
7168: varop = XEXP (varop, 0);
7169: continue;
7170: }
7171: else if ((code == ASHIFTRT || code == LSHIFTRT)
1.1.1.4 ! root 7172: && count < HOST_BITS_PER_WIDE_INT
! 7173: && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
1.1.1.3 root 7174: && 0 == (significant_bits (XEXP (varop, 0), result_mode)
7175: >> count)
7176: && 0 == (significant_bits (XEXP (varop, 0), result_mode)
7177: & significant_bits (XEXP (varop, 1),
7178: result_mode)))
7179: {
7180: varop = XEXP (varop, 1);
7181: continue;
7182: }
7183:
1.1 root 7184: /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
7185: if (code == ASHIFT
7186: && GET_CODE (XEXP (varop, 1)) == CONST_INT
7187: && (new = simplify_binary_operation (ASHIFT, result_mode,
7188: XEXP (varop, 1),
1.1.1.4 ! root 7189: GEN_INT (count))) != 0
1.1 root 7190: && merge_outer_ops (&outer_op, &outer_const, PLUS,
7191: INTVAL (new), result_mode, &complement_p))
7192: {
7193: varop = XEXP (varop, 0);
7194: continue;
7195: }
7196: break;
7197:
7198: case MINUS:
7199: /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
7200: with C the size of VAROP - 1 and the shift is logical if
7201: STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
7202: we have a (gt X 0) operation. If the shift is arithmetic with
7203: STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
7204: we have a (neg (gt X 0)) operation. */
7205:
7206: if (GET_CODE (XEXP (varop, 0)) == ASHIFTRT
7207: && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
7208: && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7209: && (code == LSHIFTRT || code == ASHIFTRT)
7210: && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
7211: && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
7212: && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
7213: {
7214: count = 0;
7215: varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
7216: const0_rtx);
7217:
7218: if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
7219: varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
7220:
7221: continue;
7222: }
7223: break;
7224: }
7225:
7226: break;
7227: }
7228:
7229: /* We need to determine what mode to do the shift in. If the shift is
7230: a ASHIFTRT or ROTATE, we must always do it in the mode it was originally
7231: done in. Otherwise, we can do it in MODE, the widest mode encountered.
7232: The code we care about is that of the shift that will actually be done,
7233: not the shift that was originally requested. */
7234: shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
7235:
7236: /* We have now finished analyzing the shift. The result should be
7237: a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
7238: OUTER_OP is non-NIL, it is an operation that needs to be applied
7239: to the result of the shift. OUTER_CONST is the relevant constant,
7240: but we must turn off all bits turned off in the shift.
7241:
7242: If we were passed a value for X, see if we can use any pieces of
7243: it. If not, make new rtx. */
7244:
7245: if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
7246: && GET_CODE (XEXP (x, 1)) == CONST_INT
7247: && INTVAL (XEXP (x, 1)) == count)
7248: const_rtx = XEXP (x, 1);
7249: else
1.1.1.4 ! root 7250: const_rtx = GEN_INT (count);
1.1 root 7251:
7252: if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7253: && GET_MODE (XEXP (x, 0)) == shift_mode
7254: && SUBREG_REG (XEXP (x, 0)) == varop)
7255: varop = XEXP (x, 0);
7256: else if (GET_MODE (varop) != shift_mode)
7257: varop = gen_lowpart_for_combine (shift_mode, varop);
7258:
7259: /* If we can't make the SUBREG, try to return what we were given. */
7260: if (GET_CODE (varop) == CLOBBER)
7261: return x ? x : varop;
7262:
7263: new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
7264: if (new != 0)
7265: x = new;
7266: else
7267: {
7268: if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
7269: x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
7270:
7271: SUBST (XEXP (x, 0), varop);
7272: SUBST (XEXP (x, 1), const_rtx);
7273: }
7274:
7275: /* If we were doing a LSHIFTRT in a wider mode than it was originally,
7276: turn off all the bits that the shift would have turned off. */
7277: if (orig_code == LSHIFTRT && result_mode != shift_mode)
1.1.1.4 ! root 7278: x = simplify_and_const_int (NULL_RTX, shift_mode, x,
1.1 root 7279: GET_MODE_MASK (result_mode) >> orig_count);
7280:
7281: /* Do the remainder of the processing in RESULT_MODE. */
7282: x = gen_lowpart_for_combine (result_mode, x);
7283:
7284: /* If COMPLEMENT_P is set, we have to complement X before doing the outer
7285: operation. */
7286: if (complement_p)
7287: x = gen_unary (NOT, result_mode, x);
7288:
7289: if (outer_op != NIL)
7290: {
1.1.1.4 ! root 7291: if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
1.1 root 7292: outer_const &= GET_MODE_MASK (result_mode);
7293:
7294: if (outer_op == AND)
1.1.1.4 ! root 7295: x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
1.1 root 7296: else if (outer_op == SET)
7297: /* This means that we have determined that the result is
7298: equivalent to a constant. This should be rare. */
1.1.1.4 ! root 7299: x = GEN_INT (outer_const);
1.1 root 7300: else if (GET_RTX_CLASS (outer_op) == '1')
7301: x = gen_unary (outer_op, result_mode, x);
7302: else
1.1.1.4 ! root 7303: x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
1.1 root 7304: }
7305:
7306: return x;
7307: }
7308:
7309: /* Like recog, but we receive the address of a pointer to a new pattern.
7310: We try to match the rtx that the pointer points to.
7311: If that fails, we may try to modify or replace the pattern,
7312: storing the replacement into the same pointer object.
7313:
7314: Modifications include deletion or addition of CLOBBERs.
7315:
7316: PNOTES is a pointer to a location where any REG_UNUSED notes added for
7317: the CLOBBERs are placed.
7318:
7319: The value is the final insn code from the pattern ultimately matched,
7320: or -1. */
7321:
7322: static int
7323: recog_for_combine (pnewpat, insn, pnotes)
7324: rtx *pnewpat;
7325: rtx insn;
7326: rtx *pnotes;
7327: {
7328: register rtx pat = *pnewpat;
7329: int insn_code_number;
7330: int num_clobbers_to_add = 0;
7331: int i;
7332: rtx notes = 0;
7333:
7334: /* Is the result of combination a valid instruction? */
7335: insn_code_number = recog (pat, insn, &num_clobbers_to_add);
7336:
7337: /* If it isn't, there is the possibility that we previously had an insn
7338: that clobbered some register as a side effect, but the combined
7339: insn doesn't need to do that. So try once more without the clobbers
7340: unless this represents an ASM insn. */
7341:
7342: if (insn_code_number < 0 && ! check_asm_operands (pat)
7343: && GET_CODE (pat) == PARALLEL)
7344: {
7345: int pos;
7346:
7347: for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
7348: if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
7349: {
7350: if (i != pos)
7351: SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
7352: pos++;
7353: }
7354:
7355: SUBST_INT (XVECLEN (pat, 0), pos);
7356:
7357: if (pos == 1)
7358: pat = XVECEXP (pat, 0, 0);
7359:
7360: insn_code_number = recog (pat, insn, &num_clobbers_to_add);
7361: }
7362:
7363: /* If we had any clobbers to add, make a new pattern than contains
7364: them. Then check to make sure that all of them are dead. */
7365: if (num_clobbers_to_add)
7366: {
7367: rtx newpat = gen_rtx (PARALLEL, VOIDmode,
7368: gen_rtvec (GET_CODE (pat) == PARALLEL
7369: ? XVECLEN (pat, 0) + num_clobbers_to_add
7370: : num_clobbers_to_add + 1));
7371:
7372: if (GET_CODE (pat) == PARALLEL)
7373: for (i = 0; i < XVECLEN (pat, 0); i++)
7374: XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
7375: else
7376: XVECEXP (newpat, 0, 0) = pat;
7377:
7378: add_clobbers (newpat, insn_code_number);
7379:
7380: for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
7381: i < XVECLEN (newpat, 0); i++)
7382: {
7383: if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
7384: && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
7385: return -1;
7386: notes = gen_rtx (EXPR_LIST, REG_UNUSED,
7387: XEXP (XVECEXP (newpat, 0, i), 0), notes);
7388: }
7389: pat = newpat;
7390: }
7391:
7392: *pnewpat = pat;
7393: *pnotes = notes;
7394:
7395: return insn_code_number;
7396: }
7397:
7398: /* Like gen_lowpart but for use by combine. In combine it is not possible
7399: to create any new pseudoregs. However, it is safe to create
7400: invalid memory addresses, because combine will try to recognize
7401: them and all they will do is make the combine attempt fail.
7402:
7403: If for some reason this cannot do its job, an rtx
7404: (clobber (const_int 0)) is returned.
7405: An insn containing that will not be recognized. */
7406:
7407: #undef gen_lowpart
7408:
7409: static rtx
7410: gen_lowpart_for_combine (mode, x)
7411: enum machine_mode mode;
7412: register rtx x;
7413: {
7414: rtx result;
7415:
7416: if (GET_MODE (x) == mode)
7417: return x;
7418:
7419: if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
7420: return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
7421:
7422: /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
7423: won't know what to do. So we will strip off the SUBREG here and
7424: process normally. */
7425: if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
7426: {
7427: x = SUBREG_REG (x);
7428: if (GET_MODE (x) == mode)
7429: return x;
7430: }
7431:
7432: result = gen_lowpart_common (mode, x);
7433: if (result)
7434: return result;
7435:
7436: if (GET_CODE (x) == MEM)
7437: {
7438: register int offset = 0;
7439: rtx new;
7440:
7441: /* Refuse to work on a volatile memory ref or one with a mode-dependent
7442: address. */
7443: if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
7444: return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
7445:
7446: /* If we want to refer to something bigger than the original memref,
7447: generate a perverse subreg instead. That will force a reload
7448: of the original memref X. */
7449: if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
7450: return gen_rtx (SUBREG, mode, x, 0);
7451:
7452: #if WORDS_BIG_ENDIAN
7453: offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
7454: - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
7455: #endif
7456: #if BYTES_BIG_ENDIAN
7457: /* Adjust the address so that the address-after-the-data
7458: is unchanged. */
7459: offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
7460: - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
7461: #endif
7462: new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
7463: RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
7464: MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
7465: MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
7466: return new;
7467: }
7468:
7469: /* If X is a comparison operator, rewrite it in a new mode. This
7470: probably won't match, but may allow further simplifications. */
7471: else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
7472: return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
7473:
7474: /* If we couldn't simplify X any other way, just enclose it in a
7475: SUBREG. Normally, this SUBREG won't match, but some patterns may
1.1.1.3 root 7476: include an explicit SUBREG or we may simplify it further in combine. */
1.1 root 7477: else
1.1.1.2 root 7478: {
7479: int word = 0;
7480:
7481: if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
7482: word = ((GET_MODE_SIZE (GET_MODE (x))
7483: - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
7484: / UNITS_PER_WORD);
7485: return gen_rtx (SUBREG, mode, x, word);
7486: }
1.1 root 7487: }
7488:
7489: /* Make an rtx expression. This is a subset of gen_rtx and only supports
7490: expressions of 1, 2, or 3 operands, each of which are rtx expressions.
7491:
7492: If the identical expression was previously in the insn (in the undobuf),
7493: it will be returned. Only if it is not found will a new expression
7494: be made. */
7495:
7496: /*VARARGS2*/
7497: static rtx
7498: gen_rtx_combine (va_alist)
7499: va_dcl
7500: {
7501: va_list p;
7502: enum rtx_code code;
7503: enum machine_mode mode;
7504: int n_args;
7505: rtx args[3];
7506: int i, j;
7507: char *fmt;
7508: rtx rt;
7509:
7510: va_start (p);
7511: code = va_arg (p, enum rtx_code);
7512: mode = va_arg (p, enum machine_mode);
7513: n_args = GET_RTX_LENGTH (code);
7514: fmt = GET_RTX_FORMAT (code);
7515:
7516: if (n_args == 0 || n_args > 3)
7517: abort ();
7518:
7519: /* Get each arg and verify that it is supposed to be an expression. */
7520: for (j = 0; j < n_args; j++)
7521: {
7522: if (*fmt++ != 'e')
7523: abort ();
7524:
7525: args[j] = va_arg (p, rtx);
7526: }
7527:
7528: /* See if this is in undobuf. Be sure we don't use objects that came
7529: from another insn; this could produce circular rtl structures. */
7530:
7531: for (i = previous_num_undos; i < undobuf.num_undo; i++)
7532: if (!undobuf.undo[i].is_int
1.1.1.4 ! root 7533: && GET_CODE (undobuf.undo[i].old_contents.rtx) == code
! 7534: && GET_MODE (undobuf.undo[i].old_contents.rtx) == mode)
1.1 root 7535: {
7536: for (j = 0; j < n_args; j++)
1.1.1.4 ! root 7537: if (XEXP (undobuf.undo[i].old_contents.rtx, j) != args[j])
1.1 root 7538: break;
7539:
7540: if (j == n_args)
1.1.1.4 ! root 7541: return undobuf.undo[i].old_contents.rtx;
1.1 root 7542: }
7543:
7544: /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
7545: Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
7546: rt = rtx_alloc (code);
7547: PUT_MODE (rt, mode);
7548: XEXP (rt, 0) = args[0];
7549: if (n_args > 1)
7550: {
7551: XEXP (rt, 1) = args[1];
7552: if (n_args > 2)
7553: XEXP (rt, 2) = args[2];
7554: }
7555: return rt;
7556: }
7557:
7558: /* These routines make binary and unary operations by first seeing if they
7559: fold; if not, a new expression is allocated. */
7560:
7561: static rtx
7562: gen_binary (code, mode, op0, op1)
7563: enum rtx_code code;
7564: enum machine_mode mode;
7565: rtx op0, op1;
7566: {
7567: rtx result;
1.1.1.4 ! root 7568: rtx tem;
! 7569:
! 7570: if (GET_RTX_CLASS (code) == 'c'
! 7571: && (GET_CODE (op0) == CONST_INT
! 7572: || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
! 7573: tem = op0, op0 = op1, op1 = tem;
1.1 root 7574:
7575: if (GET_RTX_CLASS (code) == '<')
7576: {
7577: enum machine_mode op_mode = GET_MODE (op0);
7578: if (op_mode == VOIDmode)
7579: op_mode = GET_MODE (op1);
7580: result = simplify_relational_operation (code, op_mode, op0, op1);
7581: }
7582: else
7583: result = simplify_binary_operation (code, mode, op0, op1);
7584:
7585: if (result)
7586: return result;
7587:
7588: /* Put complex operands first and constants second. */
7589: if (GET_RTX_CLASS (code) == 'c'
7590: && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
7591: || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
7592: && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
7593: || (GET_CODE (op0) == SUBREG
7594: && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
7595: && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
7596: return gen_rtx_combine (code, mode, op1, op0);
7597:
7598: return gen_rtx_combine (code, mode, op0, op1);
7599: }
7600:
7601: static rtx
7602: gen_unary (code, mode, op0)
7603: enum rtx_code code;
7604: enum machine_mode mode;
7605: rtx op0;
7606: {
7607: rtx result = simplify_unary_operation (code, mode, op0, mode);
7608:
7609: if (result)
7610: return result;
7611:
7612: return gen_rtx_combine (code, mode, op0);
7613: }
7614:
7615: /* Simplify a comparison between *POP0 and *POP1 where CODE is the
7616: comparison code that will be tested.
7617:
7618: The result is a possibly different comparison code to use. *POP0 and
7619: *POP1 may be updated.
7620:
7621: It is possible that we might detect that a comparison is either always
7622: true or always false. However, we do not perform general constant
1.1.1.2 root 7623: folding in combine, so this knowledge isn't useful. Such tautologies
1.1 root 7624: should have been detected earlier. Hence we ignore all such cases. */
7625:
7626: static enum rtx_code
7627: simplify_comparison (code, pop0, pop1)
7628: enum rtx_code code;
7629: rtx *pop0;
7630: rtx *pop1;
7631: {
7632: rtx op0 = *pop0;
7633: rtx op1 = *pop1;
7634: rtx tem, tem1;
7635: int i;
7636: enum machine_mode mode, tmode;
7637:
7638: /* Try a few ways of applying the same transformation to both operands. */
7639: while (1)
7640: {
7641: /* If both operands are the same constant shift, see if we can ignore the
7642: shift. We can if the shift is a rotate or if the bits shifted out of
7643: this shift are not significant for either input and if the type of
7644: comparison is compatible with the shift. */
7645: if (GET_CODE (op0) == GET_CODE (op1)
1.1.1.4 ! root 7646: && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
1.1 root 7647: && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
7648: || ((GET_CODE (op0) == LSHIFTRT
7649: || GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
7650: && (code != GT && code != LT && code != GE && code != LE))
7651: || (GET_CODE (op0) == ASHIFTRT
7652: && (code != GTU && code != LTU
7653: && code != GEU && code != GEU)))
7654: && GET_CODE (XEXP (op0, 1)) == CONST_INT
7655: && INTVAL (XEXP (op0, 1)) >= 0
1.1.1.4 ! root 7656: && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
1.1 root 7657: && XEXP (op0, 1) == XEXP (op1, 1))
7658: {
7659: enum machine_mode mode = GET_MODE (op0);
1.1.1.4 ! root 7660: unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
1.1 root 7661: int shift_count = INTVAL (XEXP (op0, 1));
7662:
7663: if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
7664: mask &= (mask >> shift_count) << shift_count;
7665: else if (GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
7666: mask = (mask & (mask << shift_count)) >> shift_count;
7667:
7668: if ((significant_bits (XEXP (op0, 0), mode) & ~ mask) == 0
7669: && (significant_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
7670: op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
7671: else
7672: break;
7673: }
7674:
7675: /* If both operands are AND's of a paradoxical SUBREG by constant, the
7676: SUBREGs are of the same mode, and, in both cases, the AND would
7677: be redundant if the comparison was done in the narrower mode,
7678: do the comparison in the narrower mode (e.g., we are AND'ing with 1
7679: and the operand's significant bits are 0xffffff01; in that case if
7680: we only care about QImode, we don't need the AND). This case occurs
7681: if the output mode of an scc insn is not SImode and
7682: STORE_FLAG_VALUE == 1 (e.g., the 386). */
7683:
7684: else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
7685: && GET_CODE (XEXP (op0, 1)) == CONST_INT
7686: && GET_CODE (XEXP (op1, 1)) == CONST_INT
7687: && GET_CODE (XEXP (op0, 0)) == SUBREG
7688: && GET_CODE (XEXP (op1, 0)) == SUBREG
7689: && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
7690: > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
7691: && (GET_MODE (SUBREG_REG (XEXP (op0, 0)))
7692: == GET_MODE (SUBREG_REG (XEXP (op1, 0))))
1.1.1.4 ! root 7693: && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
! 7694: <= HOST_BITS_PER_WIDE_INT)
1.1 root 7695: && (significant_bits (SUBREG_REG (XEXP (op0, 0)),
7696: GET_MODE (SUBREG_REG (XEXP (op0, 0))))
7697: & ~ INTVAL (XEXP (op0, 1))) == 0
7698: && (significant_bits (SUBREG_REG (XEXP (op1, 0)),
7699: GET_MODE (SUBREG_REG (XEXP (op1, 0))))
7700: & ~ INTVAL (XEXP (op1, 1))) == 0)
7701: {
7702: op0 = SUBREG_REG (XEXP (op0, 0));
7703: op1 = SUBREG_REG (XEXP (op1, 0));
7704:
7705: /* the resulting comparison is always unsigned since we masked off
7706: the original sign bit. */
7707: code = unsigned_condition (code);
7708: }
7709: else
7710: break;
7711: }
7712:
7713: /* If the first operand is a constant, swap the operands and adjust the
7714: comparison code appropriately. */
7715: if (CONSTANT_P (op0))
7716: {
7717: tem = op0, op0 = op1, op1 = tem;
7718: code = swap_condition (code);
7719: }
7720:
7721: /* We now enter a loop during which we will try to simplify the comparison.
7722: For the most part, we only are concerned with comparisons with zero,
7723: but some things may really be comparisons with zero but not start
7724: out looking that way. */
7725:
7726: while (GET_CODE (op1) == CONST_INT)
7727: {
7728: enum machine_mode mode = GET_MODE (op0);
7729: int mode_width = GET_MODE_BITSIZE (mode);
1.1.1.4 ! root 7730: unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
1.1 root 7731: int equality_comparison_p;
7732: int sign_bit_comparison_p;
7733: int unsigned_comparison_p;
1.1.1.4 ! root 7734: HOST_WIDE_INT const_op;
1.1 root 7735:
7736: /* We only want to handle integral modes. This catches VOIDmode,
7737: CCmode, and the floating-point modes. An exception is that we
7738: can handle VOIDmode if OP0 is a COMPARE or a comparison
7739: operation. */
7740:
7741: if (GET_MODE_CLASS (mode) != MODE_INT
7742: && ! (mode == VOIDmode
7743: && (GET_CODE (op0) == COMPARE
7744: || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
7745: break;
7746:
7747: /* Get the constant we are comparing against and turn off all bits
7748: not on in our mode. */
7749: const_op = INTVAL (op1);
1.1.1.4 ! root 7750: if (mode_width <= HOST_BITS_PER_WIDE_INT)
1.1.1.3 root 7751: const_op &= mask;
1.1 root 7752:
7753: /* If we are comparing against a constant power of two and the value
7754: being compared has only that single significant bit (e.g., it was
7755: `and'ed with that bit), we can replace this with a comparison
7756: with zero. */
7757: if (const_op
7758: && (code == EQ || code == NE || code == GE || code == GEU
7759: || code == LT || code == LTU)
1.1.1.4 ! root 7760: && mode_width <= HOST_BITS_PER_WIDE_INT
1.1 root 7761: && exact_log2 (const_op) >= 0
7762: && significant_bits (op0, mode) == const_op)
7763: {
7764: code = (code == EQ || code == GE || code == GEU ? NE : EQ);
7765: op1 = const0_rtx, const_op = 0;
7766: }
7767:
1.1.1.4 ! root 7768: /* Similarly, if we are comparing a value known to be either -1 or
! 7769: 0 with -1, change it to the opposite comparison against zero. */
! 7770:
! 7771: if (const_op == -1
! 7772: && (code == EQ || code == NE || code == GT || code == LE
! 7773: || code == GEU || code == LTU)
! 7774: && num_sign_bit_copies (op0, mode) == mode_width)
! 7775: {
! 7776: code = (code == EQ || code == LE || code == GEU ? NE : EQ);
! 7777: op1 = const0_rtx, const_op = 0;
! 7778: }
! 7779:
1.1 root 7780: /* Do some canonicalizations based on the comparison code. We prefer
1.1.1.3 root 7781: comparisons against zero and then prefer equality comparisons.
7782: If we can reduce the size of a constant, we will do that too. */
1.1 root 7783:
7784: switch (code)
7785: {
7786: case LT:
1.1.1.3 root 7787: /* < C is equivalent to <= (C - 1) */
7788: if (const_op > 0)
1.1 root 7789: {
1.1.1.3 root 7790: const_op -= 1;
1.1.1.4 ! root 7791: op1 = GEN_INT (const_op);
1.1 root 7792: code = LE;
7793: /* ... fall through to LE case below. */
7794: }
7795: else
7796: break;
7797:
7798: case LE:
1.1.1.3 root 7799: /* <= C is equivalent to < (C + 1); we do this for C < 0 */
7800: if (const_op < 0)
7801: {
7802: const_op += 1;
1.1.1.4 ! root 7803: op1 = GEN_INT (const_op);
1.1.1.3 root 7804: code = LT;
7805: }
1.1 root 7806:
7807: /* If we are doing a <= 0 comparison on a value known to have
7808: a zero sign bit, we can replace this with == 0. */
7809: else if (const_op == 0
1.1.1.4 ! root 7810: && mode_width <= HOST_BITS_PER_WIDE_INT
1.1 root 7811: && (significant_bits (op0, mode)
1.1.1.4 ! root 7812: & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
1.1 root 7813: code = EQ;
7814: break;
7815:
7816: case GE:
1.1.1.3 root 7817: /* >= C is equivalent to > (C - 1). */
7818: if (const_op > 0)
1.1 root 7819: {
1.1.1.3 root 7820: const_op -= 1;
1.1.1.4 ! root 7821: op1 = GEN_INT (const_op);
1.1 root 7822: code = GT;
7823: /* ... fall through to GT below. */
7824: }
7825: else
7826: break;
7827:
7828: case GT:
1.1.1.3 root 7829: /* > C is equivalent to >= (C + 1); we do this for C < 0*/
7830: if (const_op < 0)
7831: {
7832: const_op += 1;
1.1.1.4 ! root 7833: op1 = GEN_INT (const_op);
1.1.1.3 root 7834: code = GE;
7835: }
1.1 root 7836:
7837: /* If we are doing a > 0 comparison on a value known to have
7838: a zero sign bit, we can replace this with != 0. */
7839: else if (const_op == 0
1.1.1.4 ! root 7840: && mode_width <= HOST_BITS_PER_WIDE_INT
1.1 root 7841: && (significant_bits (op0, mode)
1.1.1.4 ! root 7842: & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
1.1 root 7843: code = NE;
7844: break;
7845:
7846: case LTU:
1.1.1.3 root 7847: /* < C is equivalent to <= (C - 1). */
7848: if (const_op > 0)
7849: {
7850: const_op -= 1;
1.1.1.4 ! root 7851: op1 = GEN_INT (const_op);
1.1.1.3 root 7852: code = LEU;
7853: /* ... fall through ... */
7854: }
1.1.1.4 ! root 7855:
! 7856: /* (unsigned) < 0x80000000 is equivalent to >= 0. */
! 7857: else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
! 7858: {
! 7859: const_op = 0, op1 = const0_rtx;
! 7860: code = GE;
! 7861: break;
! 7862: }
1.1.1.3 root 7863: else
7864: break;
1.1 root 7865:
7866: case LEU:
7867: /* unsigned <= 0 is equivalent to == 0 */
7868: if (const_op == 0)
7869: code = EQ;
1.1.1.4 ! root 7870:
! 7871: /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
! 7872: else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
! 7873: {
! 7874: const_op = 0, op1 = const0_rtx;
! 7875: code = GE;
! 7876: }
1.1 root 7877: break;
7878:
1.1.1.3 root 7879: case GEU:
7880: /* >= C is equivalent to < (C - 1). */
7881: if (const_op > 1)
7882: {
7883: const_op -= 1;
1.1.1.4 ! root 7884: op1 = GEN_INT (const_op);
1.1.1.3 root 7885: code = GTU;
7886: /* ... fall through ... */
7887: }
1.1.1.4 ! root 7888:
! 7889: /* (unsigned) >= 0x80000000 is equivalent to < 0. */
! 7890: else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
! 7891: {
! 7892: const_op = 0, op1 = const0_rtx;
! 7893: code = LT;
! 7894: }
1.1.1.3 root 7895: else
7896: break;
7897:
1.1 root 7898: case GTU:
7899: /* unsigned > 0 is equivalent to != 0 */
7900: if (const_op == 0)
7901: code = NE;
1.1.1.4 ! root 7902:
! 7903: /* (unsigned) > 0x7fffffff is equivalent to < 0. */
! 7904: else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
! 7905: {
! 7906: const_op = 0, op1 = const0_rtx;
! 7907: code = LT;
! 7908: }
1.1 root 7909: break;
7910: }
7911:
7912: /* Compute some predicates to simplify code below. */
7913:
7914: equality_comparison_p = (code == EQ || code == NE);
7915: sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
7916: unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
7917: || code == LEU);
7918:
7919: /* Now try cases based on the opcode of OP0. If none of the cases
7920: does a "continue", we exit this loop immediately after the
7921: switch. */
7922:
7923: switch (GET_CODE (op0))
7924: {
7925: case ZERO_EXTRACT:
7926: /* If we are extracting a single bit from a variable position in
7927: a constant that has only a single bit set and are comparing it
7928: with zero, we can convert this into an equality comparison
7929: between the position and the location of the single bit. We can't
7930: do this if bit endian and we don't have an extzv since we then
7931: can't know what mode to use for the endianness adjustment. */
7932:
7933: #if ! BITS_BIG_ENDIAN || defined (HAVE_extzv)
7934: if (GET_CODE (XEXP (op0, 0)) == CONST_INT
7935: && XEXP (op0, 1) == const1_rtx
7936: && equality_comparison_p && const_op == 0
7937: && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
7938: {
7939: #if BITS_BIG_ENDIAN
7940: i = (GET_MODE_BITSIZE
7941: (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
7942: #endif
7943:
7944: op0 = XEXP (op0, 2);
1.1.1.4 ! root 7945: op1 = GEN_INT (i);
1.1 root 7946: const_op = i;
7947:
7948: /* Result is nonzero iff shift count is equal to I. */
7949: code = reverse_condition (code);
7950: continue;
7951: }
7952: #endif
7953:
7954: /* ... fall through ... */
7955:
7956: case SIGN_EXTRACT:
7957: tem = expand_compound_operation (op0);
7958: if (tem != op0)
7959: {
7960: op0 = tem;
7961: continue;
7962: }
7963: break;
7964:
7965: case NOT:
7966: /* If testing for equality, we can take the NOT of the constant. */
7967: if (equality_comparison_p
7968: && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
7969: {
7970: op0 = XEXP (op0, 0);
7971: op1 = tem;
7972: continue;
7973: }
7974:
7975: /* If just looking at the sign bit, reverse the sense of the
7976: comparison. */
7977: if (sign_bit_comparison_p)
7978: {
7979: op0 = XEXP (op0, 0);
7980: code = (code == GE ? LT : GE);
7981: continue;
7982: }
7983: break;
7984:
7985: case NEG:
7986: /* If testing for equality, we can take the NEG of the constant. */
7987: if (equality_comparison_p
7988: && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
7989: {
7990: op0 = XEXP (op0, 0);
7991: op1 = tem;
7992: continue;
7993: }
7994:
7995: /* The remaining cases only apply to comparisons with zero. */
7996: if (const_op != 0)
7997: break;
7998:
7999: /* When X is ABS or is known positive,
8000: (neg X) is < 0 if and only if X != 0. */
8001:
8002: if (sign_bit_comparison_p
8003: && (GET_CODE (XEXP (op0, 0)) == ABS
1.1.1.4 ! root 8004: || (mode_width <= HOST_BITS_PER_WIDE_INT
1.1 root 8005: && (significant_bits (XEXP (op0, 0), mode)
1.1.1.4 ! root 8006: & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
1.1 root 8007: {
8008: op0 = XEXP (op0, 0);
8009: code = (code == LT ? NE : EQ);
8010: continue;
8011: }
8012:
8013: /* If we have NEG of something that is the result of a
8014: SIGN_EXTEND, SIGN_EXTRACT, or ASHIFTRT, we know that the
8015: two high-order bits must be the same and hence that
8016: "(-a) < 0" is equivalent to "a > 0". Otherwise, we can't
8017: do this. */
8018: if (GET_CODE (XEXP (op0, 0)) == SIGN_EXTEND
8019: || (GET_CODE (XEXP (op0, 0)) == SIGN_EXTRACT
8020: && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8021: && (INTVAL (XEXP (XEXP (op0, 0), 1))
8022: < GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (op0, 0), 0)))))
8023: || (GET_CODE (XEXP (op0, 0)) == ASHIFTRT
8024: && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8025: && XEXP (XEXP (op0, 0), 1) != const0_rtx)
8026: || ((tem = get_last_value (XEXP (op0, 0))) != 0
8027: && (GET_CODE (tem) == SIGN_EXTEND
8028: || (GET_CODE (tem) == SIGN_EXTRACT
8029: && GET_CODE (XEXP (tem, 1)) == CONST_INT
8030: && (INTVAL (XEXP (tem, 1))
8031: < GET_MODE_BITSIZE (GET_MODE (XEXP (tem, 0)))))
8032: || (GET_CODE (tem) == ASHIFTRT
8033: && GET_CODE (XEXP (tem, 1)) == CONST_INT
8034: && XEXP (tem, 1) != const0_rtx))))
8035: {
8036: op0 = XEXP (op0, 0);
8037: code = swap_condition (code);
8038: continue;
8039: }
8040: break;
8041:
8042: case ROTATE:
8043: /* If we are testing equality and our count is a constant, we
8044: can perform the inverse operation on our RHS. */
8045: if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
8046: && (tem = simplify_binary_operation (ROTATERT, mode,
8047: op1, XEXP (op0, 1))) != 0)
8048: {
8049: op0 = XEXP (op0, 0);
8050: op1 = tem;
8051: continue;
8052: }
8053:
8054: /* If we are doing a < 0 or >= 0 comparison, it means we are testing
8055: a particular bit. Convert it to an AND of a constant of that
8056: bit. This will be converted into a ZERO_EXTRACT. */
8057: if (const_op == 0 && sign_bit_comparison_p
8058: && GET_CODE (XEXP (op0, 1)) == CONST_INT
1.1.1.4 ! root 8059: && mode_width <= HOST_BITS_PER_WIDE_INT)
1.1 root 8060: {
1.1.1.4 ! root 8061: op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
! 8062: ((HOST_WIDE_INT) 1
! 8063: << (mode_width - 1
! 8064: - INTVAL (XEXP (op0, 1)))));
1.1 root 8065: code = (code == LT ? NE : EQ);
8066: continue;
8067: }
8068:
8069: /* ... fall through ... */
8070:
8071: case ABS:
8072: /* ABS is ignorable inside an equality comparison with zero. */
8073: if (const_op == 0 && equality_comparison_p)
8074: {
8075: op0 = XEXP (op0, 0);
8076: continue;
8077: }
8078: break;
8079:
8080:
8081: case SIGN_EXTEND:
8082: /* Can simplify (compare (zero/sign_extend FOO) CONST)
8083: to (compare FOO CONST) if CONST fits in FOO's mode and we
8084: are either testing inequality or have an unsigned comparison
8085: with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
8086: if (! unsigned_comparison_p
8087: && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
1.1.1.4 ! root 8088: <= HOST_BITS_PER_WIDE_INT)
! 8089: && ((unsigned HOST_WIDE_INT) const_op
! 8090: < (((HOST_WIDE_INT) 1
! 8091: << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
1.1 root 8092: {
8093: op0 = XEXP (op0, 0);
8094: continue;
8095: }
8096: break;
8097:
8098: case SUBREG:
1.1.1.4 ! root 8099: /* Check for the case where we are comparing A - C1 with C2,
! 8100: both constants are smaller than 1/2 the maxium positive
! 8101: value in MODE, and the comparison is equality or unsigned.
! 8102: In that case, if A is either zero-extended to MODE or has
! 8103: sufficient sign bits so that the high-order bit in MODE
! 8104: is a copy of the sign in the inner mode, we can prove that it is
! 8105: safe to do the operation in the wider mode. This simplifies
! 8106: many range checks. */
! 8107:
! 8108: if (mode_width <= HOST_BITS_PER_WIDE_INT
! 8109: && subreg_lowpart_p (op0)
! 8110: && GET_CODE (SUBREG_REG (op0)) == PLUS
! 8111: && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
! 8112: && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
! 8113: && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
! 8114: < GET_MODE_MASK (mode) / 2)
! 8115: && (unsigned) const_op < GET_MODE_MASK (mode) / 2
! 8116: && (0 == (significant_bits (XEXP (SUBREG_REG (op0), 0),
! 8117: GET_MODE (SUBREG_REG (op0)))
! 8118: & ~ GET_MODE_MASK (mode))
! 8119: || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
! 8120: GET_MODE (SUBREG_REG (op0)))
! 8121: > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
! 8122: - GET_MODE_BITSIZE (mode)))))
! 8123: {
! 8124: op0 = SUBREG_REG (op0);
! 8125: continue;
! 8126: }
! 8127:
! 8128: /* If the inner mode is narrower and we are extracting the low part,
! 8129: we can treat the SUBREG as if it were a ZERO_EXTEND. */
! 8130: if (subreg_lowpart_p (op0)
! 8131: && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
! 8132: /* Fall through */ ;
! 8133: else
1.1 root 8134: break;
8135:
8136: /* ... fall through ... */
8137:
8138: case ZERO_EXTEND:
8139: if ((unsigned_comparison_p || equality_comparison_p)
8140: && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
1.1.1.4 ! root 8141: <= HOST_BITS_PER_WIDE_INT)
! 8142: && ((unsigned HOST_WIDE_INT) const_op
1.1 root 8143: < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
8144: {
8145: op0 = XEXP (op0, 0);
8146: continue;
8147: }
8148: break;
8149:
8150: case PLUS:
8151: /* (eq (plus X C1) C2) -> (eq X (minus C2 C1)). We can only do
1.1.1.2 root 8152: this for equality comparisons due to pathological cases involving
1.1 root 8153: overflows. */
8154: if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
8155: && (tem = simplify_binary_operation (MINUS, mode, op1,
8156: XEXP (op0, 1))) != 0)
8157: {
8158: op0 = XEXP (op0, 0);
8159: op1 = tem;
8160: continue;
8161: }
8162:
8163: /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
8164: if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
8165: && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
8166: {
8167: op0 = XEXP (XEXP (op0, 0), 0);
8168: code = (code == LT ? EQ : NE);
8169: continue;
8170: }
8171: break;
8172:
8173: case MINUS:
8174: /* The sign bit of (minus (ashiftrt X C) X), where C is the number
8175: of bits in X minus 1, is one iff X > 0. */
8176: if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
8177: && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8178: && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
8179: && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
8180: {
8181: op0 = XEXP (op0, 1);
8182: code = (code == GE ? LE : GT);
8183: continue;
8184: }
8185: break;
8186:
8187: case XOR:
8188: /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
8189: if C is zero or B is a constant. */
8190: if (equality_comparison_p
8191: && 0 != (tem = simplify_binary_operation (XOR, mode,
8192: XEXP (op0, 1), op1)))
8193: {
8194: op0 = XEXP (op0, 0);
8195: op1 = tem;
8196: continue;
8197: }
8198: break;
8199:
8200: case EQ: case NE:
8201: case LT: case LTU: case LE: case LEU:
8202: case GT: case GTU: case GE: case GEU:
8203: /* We can't do anything if OP0 is a condition code value, rather
8204: than an actual data value. */
8205: if (const_op != 0
8206: #ifdef HAVE_cc0
8207: || XEXP (op0, 0) == cc0_rtx
8208: #endif
8209: || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
8210: break;
8211:
8212: /* Get the two operands being compared. */
8213: if (GET_CODE (XEXP (op0, 0)) == COMPARE)
8214: tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
8215: else
8216: tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
8217:
8218: /* Check for the cases where we simply want the result of the
8219: earlier test or the opposite of that result. */
8220: if (code == NE
8221: || (code == EQ && reversible_comparison_p (op0))
1.1.1.4 ! root 8222: || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
1.1.1.3 root 8223: && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
1.1 root 8224: && (STORE_FLAG_VALUE
1.1.1.4 ! root 8225: & (((HOST_WIDE_INT) 1
! 8226: << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
1.1 root 8227: && (code == LT
8228: || (code == GE && reversible_comparison_p (op0)))))
8229: {
8230: code = (code == LT || code == NE
8231: ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
8232: op0 = tem, op1 = tem1;
8233: continue;
8234: }
8235: break;
8236:
8237: case IOR:
8238: /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
8239: iff X <= 0. */
8240: if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
8241: && XEXP (XEXP (op0, 0), 1) == constm1_rtx
8242: && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
8243: {
8244: op0 = XEXP (op0, 1);
8245: code = (code == GE ? GT : LE);
8246: continue;
8247: }
8248: break;
8249:
8250: case AND:
8251: /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
8252: will be converted to a ZERO_EXTRACT later. */
8253: if (const_op == 0 && equality_comparison_p
8254: && (GET_CODE (XEXP (op0, 0)) == ASHIFT
8255: || GET_CODE (XEXP (op0, 0)) == LSHIFT)
8256: && XEXP (XEXP (op0, 0), 0) == const1_rtx)
8257: {
8258: op0 = simplify_and_const_int
8259: (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
8260: XEXP (op0, 1),
8261: XEXP (XEXP (op0, 0), 1)),
1.1.1.4 ! root 8262: (HOST_WIDE_INT) 1);
1.1 root 8263: continue;
8264: }
8265:
8266: /* If we are comparing (and (lshiftrt X C1) C2) for equality with
8267: zero and X is a comparison and C1 and C2 describe only bits set
8268: in STORE_FLAG_VALUE, we can compare with X. */
8269: if (const_op == 0 && equality_comparison_p
1.1.1.4 ! root 8270: && mode_width <= HOST_BITS_PER_WIDE_INT
1.1 root 8271: && GET_CODE (XEXP (op0, 1)) == CONST_INT
8272: && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
8273: && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8274: && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
1.1.1.4 ! root 8275: && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
1.1 root 8276: {
8277: mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
8278: << INTVAL (XEXP (XEXP (op0, 0), 1)));
8279: if ((~ STORE_FLAG_VALUE & mask) == 0
8280: && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
8281: || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
8282: && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
8283: {
8284: op0 = XEXP (XEXP (op0, 0), 0);
8285: continue;
8286: }
8287: }
8288:
8289: /* If we are doing an equality comparison of an AND of a bit equal
8290: to the sign bit, replace this with a LT or GE comparison of
8291: the underlying value. */
8292: if (equality_comparison_p
8293: && const_op == 0
8294: && GET_CODE (XEXP (op0, 1)) == CONST_INT
1.1.1.4 ! root 8295: && mode_width <= HOST_BITS_PER_WIDE_INT
1.1 root 8296: && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
1.1.1.4 ! root 8297: == (HOST_WIDE_INT) 1 << (mode_width - 1)))
1.1 root 8298: {
8299: op0 = XEXP (op0, 0);
8300: code = (code == EQ ? GE : LT);
8301: continue;
8302: }
8303:
8304: /* If this AND operation is really a ZERO_EXTEND from a narrower
8305: mode, the constant fits within that mode, and this is either an
8306: equality or unsigned comparison, try to do this comparison in
8307: the narrower mode. */
8308: if ((equality_comparison_p || unsigned_comparison_p)
8309: && GET_CODE (XEXP (op0, 1)) == CONST_INT
8310: && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
8311: & GET_MODE_MASK (mode))
8312: + 1)) >= 0
8313: && const_op >> i == 0
8314: && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
8315: {
8316: op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
8317: continue;
8318: }
8319: break;
8320:
8321: case ASHIFT:
8322: case LSHIFT:
8323: /* If we have (compare (xshift FOO N) (const_int C)) and
8324: the high order N bits of FOO (N+1 if an inequality comparison)
8325: are not significant, we can do this by comparing FOO with C
8326: shifted right N bits so long as the low-order N bits of C are
8327: zero. */
8328: if (GET_CODE (XEXP (op0, 1)) == CONST_INT
8329: && INTVAL (XEXP (op0, 1)) >= 0
8330: && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
1.1.1.4 ! root 8331: < HOST_BITS_PER_WIDE_INT)
! 8332: && ((const_op
! 8333: & ((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1) == 0)
! 8334: && mode_width <= HOST_BITS_PER_WIDE_INT
1.1 root 8335: && (significant_bits (XEXP (op0, 0), mode)
8336: & ~ (mask >> (INTVAL (XEXP (op0, 1))
8337: + ! equality_comparison_p))) == 0)
8338: {
8339: const_op >>= INTVAL (XEXP (op0, 1));
1.1.1.4 ! root 8340: op1 = GEN_INT (const_op);
1.1 root 8341: op0 = XEXP (op0, 0);
8342: continue;
8343: }
8344:
1.1.1.2 root 8345: /* If we are doing a sign bit comparison, it means we are testing
1.1 root 8346: a particular bit. Convert it to the appropriate AND. */
1.1.1.2 root 8347: if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
1.1.1.4 ! root 8348: && mode_width <= HOST_BITS_PER_WIDE_INT)
1.1 root 8349: {
1.1.1.4 ! root 8350: op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
! 8351: ((HOST_WIDE_INT) 1
! 8352: << (mode_width - 1
! 8353: - INTVAL (XEXP (op0, 1)))));
1.1 root 8354: code = (code == LT ? NE : EQ);
8355: continue;
8356: }
1.1.1.2 root 8357:
8358: /* If this an equality comparison with zero and we are shifting
8359: the low bit to the sign bit, we can convert this to an AND of the
8360: low-order bit. */
8361: if (const_op == 0 && equality_comparison_p
8362: && GET_CODE (XEXP (op0, 1)) == CONST_INT
8363: && INTVAL (XEXP (op0, 1)) == mode_width - 1)
8364: {
1.1.1.4 ! root 8365: op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
! 8366: (HOST_WIDE_INT) 1);
1.1.1.2 root 8367: continue;
8368: }
1.1 root 8369: break;
8370:
8371: case ASHIFTRT:
1.1.1.4 ! root 8372: /* If this is an equality comparison with zero, we can do this
! 8373: as a logical shift, which might be much simpler. */
! 8374: if (equality_comparison_p && const_op == 0
! 8375: && GET_CODE (XEXP (op0, 1)) == CONST_INT)
! 8376: {
! 8377: op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
! 8378: XEXP (op0, 0),
! 8379: INTVAL (XEXP (op0, 1)));
! 8380: continue;
! 8381: }
! 8382:
1.1 root 8383: /* If OP0 is a sign extension and CODE is not an unsigned comparison,
8384: do the comparison in a narrower mode. */
8385: if (! unsigned_comparison_p
8386: && GET_CODE (XEXP (op0, 1)) == CONST_INT
8387: && GET_CODE (XEXP (op0, 0)) == ASHIFT
8388: && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
8389: && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
1.1.1.4 ! root 8390: MODE_INT, 1)) != BLKmode
! 8391: && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
! 8392: || ((unsigned HOST_WIDE_INT) - const_op
! 8393: <= GET_MODE_MASK (tmode))))
1.1 root 8394: {
8395: op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
8396: continue;
8397: }
8398:
8399: /* ... fall through ... */
8400: case LSHIFTRT:
8401: /* If we have (compare (xshiftrt FOO N) (const_int C)) and
8402: the low order N bits of FOO are not significant, we can do this
8403: by comparing FOO with C shifted left N bits so long as no
8404: overflow occurs. */
8405: if (GET_CODE (XEXP (op0, 1)) == CONST_INT
8406: && INTVAL (XEXP (op0, 1)) >= 0
1.1.1.4 ! root 8407: && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
! 8408: && mode_width <= HOST_BITS_PER_WIDE_INT
1.1 root 8409: && (significant_bits (XEXP (op0, 0), mode)
1.1.1.4 ! root 8410: & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
1.1 root 8411: && (const_op == 0
8412: || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
8413: < mode_width)))
8414: {
8415: const_op <<= INTVAL (XEXP (op0, 1));
1.1.1.4 ! root 8416: op1 = GEN_INT (const_op);
1.1 root 8417: op0 = XEXP (op0, 0);
8418: continue;
8419: }
8420:
8421: /* If we are using this shift to extract just the sign bit, we
8422: can replace this with an LT or GE comparison. */
8423: if (const_op == 0
8424: && (equality_comparison_p || sign_bit_comparison_p)
8425: && GET_CODE (XEXP (op0, 1)) == CONST_INT
8426: && INTVAL (XEXP (op0, 1)) == mode_width - 1)
8427: {
8428: op0 = XEXP (op0, 0);
8429: code = (code == NE || code == GT ? LT : GE);
8430: continue;
8431: }
8432: break;
8433: }
8434:
8435: break;
8436: }
8437:
8438: /* Now make any compound operations involved in this comparison. Then,
8439: check for an outmost SUBREG on OP0 that isn't doing anything or is
8440: paradoxical. The latter case can only occur when it is known that the
8441: "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
8442: We can never remove a SUBREG for a non-equality comparison because the
8443: sign bit is in a different place in the underlying object. */
8444:
8445: op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
8446: op1 = make_compound_operation (op1, SET);
8447:
8448: if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
8449: && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
8450: && (code == NE || code == EQ)
8451: && ((GET_MODE_SIZE (GET_MODE (op0))
8452: > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
8453: {
8454: op0 = SUBREG_REG (op0);
8455: op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
8456: }
8457:
8458: else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
8459: && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
8460: && (code == NE || code == EQ)
1.1.1.4 ! root 8461: && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
! 8462: <= HOST_BITS_PER_WIDE_INT)
1.1 root 8463: && (significant_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
8464: & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
8465: && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
8466: op1),
8467: (significant_bits (tem, GET_MODE (SUBREG_REG (op0)))
8468: & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
8469: op0 = SUBREG_REG (op0), op1 = tem;
8470:
8471: /* We now do the opposite procedure: Some machines don't have compare
8472: insns in all modes. If OP0's mode is an integer mode smaller than a
8473: word and we can't do a compare in that mode, see if there is a larger
1.1.1.4 ! root 8474: mode for which we can do the compare. There are a number of cases in
! 8475: which we can use the wider mode. */
1.1 root 8476:
8477: mode = GET_MODE (op0);
8478: if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
8479: && GET_MODE_SIZE (mode) < UNITS_PER_WORD
8480: && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
8481: for (tmode = GET_MODE_WIDER_MODE (mode);
1.1.1.4 ! root 8482: (tmode != VOIDmode
! 8483: && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
1.1 root 8484: tmode = GET_MODE_WIDER_MODE (tmode))
1.1.1.4 ! root 8485: if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
! 8486: {
! 8487: /* If the only significant bits in OP0 and OP1 are those in the
! 8488: narrower mode and this is an equality or unsigned comparison,
! 8489: we can use the wider mode. Similarly for sign-extended
! 8490: values and equality or signed comparisons. */
! 8491: if (((code == EQ || code == NE
! 8492: || code == GEU || code == GTU || code == LEU || code == LTU)
! 8493: && ((significant_bits (op0, tmode) & ~ GET_MODE_MASK (mode))
! 8494: == 0)
! 8495: && ((significant_bits (op1, tmode) & ~ GET_MODE_MASK (mode))
! 8496: == 0))
! 8497: || ((code == EQ || code == NE
! 8498: || code == GE || code == GT || code == LE || code == LT)
! 8499: && (num_sign_bit_copies (op0, tmode)
! 8500: > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
! 8501: && (num_sign_bit_copies (op1, tmode)
! 8502: > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
! 8503: {
! 8504: op0 = gen_lowpart_for_combine (tmode, op0);
! 8505: op1 = gen_lowpart_for_combine (tmode, op1);
! 8506: break;
1.1 root 8507: }
8508:
1.1.1.4 ! root 8509: /* If this is a test for negative, we can make an explicit
! 8510: test of the sign bit. */
! 8511:
! 8512: if (op1 == const0_rtx && (code == LT || code == GE)
! 8513: && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
! 8514: {
! 8515: op0 = gen_binary (AND, tmode,
! 8516: gen_lowpart_for_combine (tmode, op0),
! 8517: GEN_INT ((HOST_WIDE_INT) 1
! 8518: << (GET_MODE_BITSIZE (mode) - 1)));
! 8519: code = (code == LT) ? NE : EQ;
! 8520: break;
! 8521: }
1.1 root 8522: }
8523:
8524: *pop0 = op0;
8525: *pop1 = op1;
8526:
8527: return code;
8528: }
8529:
8530: /* Return 1 if we know that X, a comparison operation, is not operating
8531: on a floating-point value or is EQ or NE, meaning that we can safely
8532: reverse it. */
8533:
8534: static int
8535: reversible_comparison_p (x)
8536: rtx x;
8537: {
8538: if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
8539: || GET_CODE (x) == NE || GET_CODE (x) == EQ)
8540: return 1;
8541:
8542: switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
8543: {
8544: case MODE_INT:
8545: return 1;
8546:
8547: case MODE_CC:
8548: x = get_last_value (XEXP (x, 0));
8549: return (x && GET_CODE (x) == COMPARE
8550: && GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) == MODE_INT);
8551: }
8552:
8553: return 0;
8554: }
8555:
8556: /* Utility function for following routine. Called when X is part of a value
8557: being stored into reg_last_set_value. Sets reg_last_set_table_tick
8558: for each register mentioned. Similar to mention_regs in cse.c */
8559:
8560: static void
8561: update_table_tick (x)
8562: rtx x;
8563: {
8564: register enum rtx_code code = GET_CODE (x);
8565: register char *fmt = GET_RTX_FORMAT (code);
8566: register int i;
8567:
8568: if (code == REG)
8569: {
8570: int regno = REGNO (x);
8571: int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
8572: ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
8573:
8574: for (i = regno; i < endregno; i++)
8575: reg_last_set_table_tick[i] = label_tick;
8576:
8577: return;
8578: }
8579:
8580: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8581: /* Note that we can't have an "E" in values stored; see
8582: get_last_value_validate. */
8583: if (fmt[i] == 'e')
8584: update_table_tick (XEXP (x, i));
8585: }
8586:
8587: /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
8588: are saying that the register is clobbered and we no longer know its
8589: value. If INSN is zero, don't update reg_last_set; this call is normally
8590: done with VALUE also zero to invalidate the register. */
8591:
8592: static void
8593: record_value_for_reg (reg, insn, value)
8594: rtx reg;
8595: rtx insn;
8596: rtx value;
8597: {
8598: int regno = REGNO (reg);
8599: int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
8600: ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
8601: int i;
8602:
8603: /* If VALUE contains REG and we have a previous value for REG, substitute
8604: the previous value. */
8605: if (value && insn && reg_overlap_mentioned_p (reg, value))
8606: {
8607: rtx tem;
8608:
8609: /* Set things up so get_last_value is allowed to see anything set up to
8610: our insn. */
8611: subst_low_cuid = INSN_CUID (insn);
8612: tem = get_last_value (reg);
8613:
8614: if (tem)
8615: value = replace_rtx (copy_rtx (value), reg, tem);
8616: }
8617:
8618: /* For each register modified, show we don't know its value, that
8619: its value has been updated, and that we don't know the location of
8620: the death of the register. */
8621: for (i = regno; i < endregno; i ++)
8622: {
8623: if (insn)
8624: reg_last_set[i] = insn;
8625: reg_last_set_value[i] = 0;
8626: reg_last_death[i] = 0;
8627: }
8628:
8629: /* Mark registers that are being referenced in this value. */
8630: if (value)
8631: update_table_tick (value);
8632:
8633: /* Now update the status of each register being set.
8634: If someone is using this register in this block, set this register
8635: to invalid since we will get confused between the two lives in this
8636: basic block. This makes using this register always invalid. In cse, we
8637: scan the table to invalidate all entries using this register, but this
8638: is too much work for us. */
8639:
8640: for (i = regno; i < endregno; i++)
8641: {
8642: reg_last_set_label[i] = label_tick;
8643: if (value && reg_last_set_table_tick[i] == label_tick)
8644: reg_last_set_invalid[i] = 1;
8645: else
8646: reg_last_set_invalid[i] = 0;
8647: }
8648:
8649: /* The value being assigned might refer to X (like in "x++;"). In that
8650: case, we must replace it with (clobber (const_int 0)) to prevent
8651: infinite loops. */
8652: if (value && ! get_last_value_validate (&value,
8653: reg_last_set_label[regno], 0))
8654: {
8655: value = copy_rtx (value);
8656: if (! get_last_value_validate (&value, reg_last_set_label[regno], 1))
8657: value = 0;
8658: }
8659:
8660: /* For the main register being modified, update the value. */
8661: reg_last_set_value[regno] = value;
8662:
8663: }
8664:
8665: /* Used for communication between the following two routines. */
8666: static rtx record_dead_insn;
8667:
8668: /* Called via note_stores from record_dead_and_set_regs to handle one
8669: SET or CLOBBER in an insn. */
8670:
8671: static void
8672: record_dead_and_set_regs_1 (dest, setter)
8673: rtx dest, setter;
8674: {
8675: if (GET_CODE (dest) == REG)
8676: {
8677: /* If we are setting the whole register, we know its value. Otherwise
8678: show that we don't know the value. We can handle SUBREG in
8679: some cases. */
8680: if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
8681: record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
8682: else if (GET_CODE (setter) == SET
8683: && GET_CODE (SET_DEST (setter)) == SUBREG
8684: && SUBREG_REG (SET_DEST (setter)) == dest
8685: && subreg_lowpart_p (SET_DEST (setter)))
1.1.1.4 ! root 8686: record_value_for_reg (dest, record_dead_insn,
! 8687: gen_lowpart_for_combine (GET_MODE (dest),
! 8688: SET_SRC (setter)));
1.1 root 8689: else
1.1.1.4 ! root 8690: record_value_for_reg (dest, record_dead_insn, NULL_RTX);
1.1 root 8691: }
8692: else if (GET_CODE (dest) == MEM
8693: /* Ignore pushes, they clobber nothing. */
8694: && ! push_operand (dest, GET_MODE (dest)))
8695: mem_last_set = INSN_CUID (record_dead_insn);
8696: }
8697:
8698: /* Update the records of when each REG was most recently set or killed
8699: for the things done by INSN. This is the last thing done in processing
8700: INSN in the combiner loop.
8701:
8702: We update reg_last_set, reg_last_set_value, reg_last_death, and also the
8703: similar information mem_last_set (which insn most recently modified memory)
8704: and last_call_cuid (which insn was the most recent subroutine call). */
8705:
8706: static void
8707: record_dead_and_set_regs (insn)
8708: rtx insn;
8709: {
8710: register rtx link;
8711: for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
8712: {
8713: if (REG_NOTE_KIND (link) == REG_DEAD)
8714: reg_last_death[REGNO (XEXP (link, 0))] = insn;
8715: else if (REG_NOTE_KIND (link) == REG_INC)
1.1.1.4 ! root 8716: record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
1.1 root 8717: }
8718:
8719: if (GET_CODE (insn) == CALL_INSN)
8720: last_call_cuid = mem_last_set = INSN_CUID (insn);
8721:
8722: record_dead_insn = insn;
8723: note_stores (PATTERN (insn), record_dead_and_set_regs_1);
8724: }
8725:
8726: /* Utility routine for the following function. Verify that all the registers
8727: mentioned in *LOC are valid when *LOC was part of a value set when
8728: label_tick == TICK. Return 0 if some are not.
8729:
8730: If REPLACE is non-zero, replace the invalid reference with
8731: (clobber (const_int 0)) and return 1. This replacement is useful because
8732: we often can get useful information about the form of a value (e.g., if
8733: it was produced by a shift that always produces -1 or 0) even though
8734: we don't know exactly what registers it was produced from. */
8735:
8736: static int
8737: get_last_value_validate (loc, tick, replace)
8738: rtx *loc;
8739: int tick;
8740: int replace;
8741: {
8742: rtx x = *loc;
8743: char *fmt = GET_RTX_FORMAT (GET_CODE (x));
8744: int len = GET_RTX_LENGTH (GET_CODE (x));
8745: int i;
8746:
8747: if (GET_CODE (x) == REG)
8748: {
8749: int regno = REGNO (x);
8750: int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
8751: ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
8752: int j;
8753:
8754: for (j = regno; j < endregno; j++)
8755: if (reg_last_set_invalid[j]
8756: /* If this is a pseudo-register that was only set once, it is
8757: always valid. */
8758: || (! (regno >= FIRST_PSEUDO_REGISTER && reg_n_sets[regno] == 1)
8759: && reg_last_set_label[j] > tick))
8760: {
8761: if (replace)
8762: *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8763: return replace;
8764: }
8765:
8766: return 1;
8767: }
8768:
8769: for (i = 0; i < len; i++)
8770: if ((fmt[i] == 'e'
8771: && get_last_value_validate (&XEXP (x, i), tick, replace) == 0)
8772: /* Don't bother with these. They shouldn't occur anyway. */
8773: || fmt[i] == 'E')
8774: return 0;
8775:
8776: /* If we haven't found a reason for it to be invalid, it is valid. */
8777: return 1;
8778: }
8779:
8780: /* Get the last value assigned to X, if known. Some registers
8781: in the value may be replaced with (clobber (const_int 0)) if their value
8782: is known longer known reliably. */
8783:
8784: static rtx
8785: get_last_value (x)
8786: rtx x;
8787: {
8788: int regno;
8789: rtx value;
8790:
8791: /* If this is a non-paradoxical SUBREG, get the value of its operand and
8792: then convert it to the desired mode. If this is a paradoxical SUBREG,
8793: we cannot predict what values the "extra" bits might have. */
8794: if (GET_CODE (x) == SUBREG
8795: && subreg_lowpart_p (x)
8796: && (GET_MODE_SIZE (GET_MODE (x))
8797: <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8798: && (value = get_last_value (SUBREG_REG (x))) != 0)
8799: return gen_lowpart_for_combine (GET_MODE (x), value);
8800:
8801: if (GET_CODE (x) != REG)
8802: return 0;
8803:
8804: regno = REGNO (x);
8805: value = reg_last_set_value[regno];
8806:
1.1.1.4 ! root 8807: /* If we don't have a value or if it isn't for this basic block, return 0. */
1.1 root 8808:
8809: if (value == 0
8810: || (reg_n_sets[regno] != 1
1.1.1.4 ! root 8811: && (reg_last_set_label[regno] != label_tick)))
1.1 root 8812: return 0;
8813:
1.1.1.4 ! root 8814: /* If the value was set in a later insn that the ones we are processing,
! 8815: we can't use it even if the register was only set once, but make a quick
! 8816: check to see if the previous insn set it to something. This is commonly
! 8817: the case when the same pseudo is used by repeated insns. */
! 8818:
! 8819: if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
! 8820: {
! 8821: rtx insn, set;
! 8822:
! 8823: for (insn = prev_nonnote_insn (subst_insn);
! 8824: insn && INSN_CUID (insn) >= subst_low_cuid;
! 8825: insn = prev_nonnote_insn (insn))
! 8826: ;
! 8827:
! 8828: if (insn
! 8829: && (set = single_set (insn)) != 0
! 8830: && rtx_equal_p (SET_DEST (set), x))
! 8831: {
! 8832: value = SET_SRC (set);
! 8833:
! 8834: /* Make sure that VALUE doesn't reference X. Replace any
! 8835: expliit references with a CLOBBER. If there are any remaining
! 8836: references (rare), don't use the value. */
! 8837:
! 8838: if (reg_mentioned_p (x, value))
! 8839: value = replace_rtx (copy_rtx (value), x,
! 8840: gen_rtx (CLOBBER, GET_MODE (x), const0_rtx));
! 8841:
! 8842: if (reg_overlap_mentioned_p (x, value))
! 8843: return 0;
! 8844: }
! 8845: else
! 8846: return 0;
! 8847: }
! 8848:
! 8849: /* If the value has all its registers valid, return it. */
1.1 root 8850: if (get_last_value_validate (&value, reg_last_set_label[regno], 0))
8851: return value;
8852:
8853: /* Otherwise, make a copy and replace any invalid register with
8854: (clobber (const_int 0)). If that fails for some reason, return 0. */
8855:
8856: value = copy_rtx (value);
8857: if (get_last_value_validate (&value, reg_last_set_label[regno], 1))
8858: return value;
8859:
8860: return 0;
8861: }
8862:
8863: /* Return nonzero if expression X refers to a REG or to memory
8864: that is set in an instruction more recent than FROM_CUID. */
8865:
8866: static int
8867: use_crosses_set_p (x, from_cuid)
8868: register rtx x;
8869: int from_cuid;
8870: {
8871: register char *fmt;
8872: register int i;
8873: register enum rtx_code code = GET_CODE (x);
8874:
8875: if (code == REG)
8876: {
8877: register int regno = REGNO (x);
8878: #ifdef PUSH_ROUNDING
8879: /* Don't allow uses of the stack pointer to be moved,
8880: because we don't know whether the move crosses a push insn. */
8881: if (regno == STACK_POINTER_REGNUM)
8882: return 1;
8883: #endif
8884: return (reg_last_set[regno]
8885: && INSN_CUID (reg_last_set[regno]) > from_cuid);
8886: }
8887:
8888: if (code == MEM && mem_last_set > from_cuid)
8889: return 1;
8890:
8891: fmt = GET_RTX_FORMAT (code);
8892:
8893: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8894: {
8895: if (fmt[i] == 'E')
8896: {
8897: register int j;
8898: for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8899: if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
8900: return 1;
8901: }
8902: else if (fmt[i] == 'e'
8903: && use_crosses_set_p (XEXP (x, i), from_cuid))
8904: return 1;
8905: }
8906: return 0;
8907: }
8908:
8909: /* Define three variables used for communication between the following
8910: routines. */
8911:
8912: static int reg_dead_regno, reg_dead_endregno;
8913: static int reg_dead_flag;
8914:
8915: /* Function called via note_stores from reg_dead_at_p.
8916:
8917: If DEST is within [reg_dead_rengno, reg_dead_endregno), set
8918: reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
8919:
8920: static void
8921: reg_dead_at_p_1 (dest, x)
8922: rtx dest;
8923: rtx x;
8924: {
8925: int regno, endregno;
8926:
8927: if (GET_CODE (dest) != REG)
8928: return;
8929:
8930: regno = REGNO (dest);
8931: endregno = regno + (regno < FIRST_PSEUDO_REGISTER
8932: ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
8933:
8934: if (reg_dead_endregno > regno && reg_dead_regno < endregno)
8935: reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
8936: }
8937:
8938: /* Return non-zero if REG is known to be dead at INSN.
8939:
8940: We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
8941: referencing REG, it is dead. If we hit a SET referencing REG, it is
8942: live. Otherwise, see if it is live or dead at the start of the basic
8943: block we are in. */
8944:
8945: static int
8946: reg_dead_at_p (reg, insn)
8947: rtx reg;
8948: rtx insn;
8949: {
8950: int block, i;
8951:
8952: /* Set variables for reg_dead_at_p_1. */
8953: reg_dead_regno = REGNO (reg);
8954: reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
8955: ? HARD_REGNO_NREGS (reg_dead_regno,
8956: GET_MODE (reg))
8957: : 1);
8958:
8959: reg_dead_flag = 0;
8960:
8961: /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
8962: beginning of function. */
8963: for (; insn && GET_CODE (insn) != CODE_LABEL;
8964: insn = prev_nonnote_insn (insn))
8965: {
8966: note_stores (PATTERN (insn), reg_dead_at_p_1);
8967: if (reg_dead_flag)
8968: return reg_dead_flag == 1 ? 1 : 0;
8969:
8970: if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
8971: return 1;
8972: }
8973:
8974: /* Get the basic block number that we were in. */
8975: if (insn == 0)
8976: block = 0;
8977: else
8978: {
8979: for (block = 0; block < n_basic_blocks; block++)
8980: if (insn == basic_block_head[block])
8981: break;
8982:
8983: if (block == n_basic_blocks)
8984: return 0;
8985: }
8986:
8987: for (i = reg_dead_regno; i < reg_dead_endregno; i++)
1.1.1.4 ! root 8988: if (basic_block_live_at_start[block][i / REGSET_ELT_BITS]
! 8989: & ((REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS)))
1.1 root 8990: return 0;
8991:
8992: return 1;
8993: }
8994:
8995: /* Remove register number REGNO from the dead registers list of INSN.
8996:
8997: Return the note used to record the death, if there was one. */
8998:
8999: rtx
9000: remove_death (regno, insn)
9001: int regno;
9002: rtx insn;
9003: {
9004: register rtx note = find_regno_note (insn, REG_DEAD, regno);
9005:
9006: if (note)
1.1.1.4 ! root 9007: {
! 9008: reg_n_deaths[regno]--;
! 9009: remove_note (insn, note);
! 9010: }
1.1 root 9011:
9012: return note;
9013: }
9014:
9015: /* For each register (hardware or pseudo) used within expression X, if its
9016: death is in an instruction with cuid between FROM_CUID (inclusive) and
9017: TO_INSN (exclusive), put a REG_DEAD note for that register in the
9018: list headed by PNOTES.
9019:
9020: This is done when X is being merged by combination into TO_INSN. These
9021: notes will then be distributed as needed. */
9022:
9023: static void
9024: move_deaths (x, from_cuid, to_insn, pnotes)
9025: rtx x;
9026: int from_cuid;
9027: rtx to_insn;
9028: rtx *pnotes;
9029: {
9030: register char *fmt;
9031: register int len, i;
9032: register enum rtx_code code = GET_CODE (x);
9033:
9034: if (code == REG)
9035: {
9036: register int regno = REGNO (x);
9037: register rtx where_dead = reg_last_death[regno];
9038:
9039: if (where_dead && INSN_CUID (where_dead) >= from_cuid
9040: && INSN_CUID (where_dead) < INSN_CUID (to_insn))
9041: {
9042: rtx note = remove_death (regno, reg_last_death[regno]);
9043:
9044: /* It is possible for the call above to return 0. This can occur
9045: when reg_last_death points to I2 or I1 that we combined with.
9046: In that case make a new note. */
9047:
9048: if (note)
9049: {
9050: XEXP (note, 1) = *pnotes;
9051: *pnotes = note;
9052: }
9053: else
9054: *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
1.1.1.4 ! root 9055:
! 9056: reg_n_deaths[regno]++;
1.1 root 9057: }
9058:
9059: return;
9060: }
9061:
9062: else if (GET_CODE (x) == SET)
9063: {
9064: rtx dest = SET_DEST (x);
9065:
9066: move_deaths (SET_SRC (x), from_cuid, to_insn, pnotes);
9067:
1.1.1.3 root 9068: /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
9069: that accesses one word of a multi-word item, some
9070: piece of everything register in the expression is used by
9071: this insn, so remove any old death. */
9072:
9073: if (GET_CODE (dest) == ZERO_EXTRACT
9074: || GET_CODE (dest) == STRICT_LOW_PART
9075: || (GET_CODE (dest) == SUBREG
9076: && (((GET_MODE_SIZE (GET_MODE (dest))
9077: + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
9078: == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
9079: + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
9080: {
9081: move_deaths (dest, from_cuid, to_insn, pnotes);
9082: return;
9083: }
9084:
9085: /* If this is some other SUBREG, we know it replaces the entire
9086: value, so use that as the destination. */
9087: if (GET_CODE (dest) == SUBREG)
9088: dest = SUBREG_REG (dest);
9089:
9090: /* If this is a MEM, adjust deaths of anything used in the address.
9091: For a REG (the only other possibility), the entire value is
9092: being replaced so the old value is not used in this insn. */
1.1 root 9093:
9094: if (GET_CODE (dest) == MEM)
9095: move_deaths (XEXP (dest, 0), from_cuid, to_insn, pnotes);
9096: return;
9097: }
9098:
9099: else if (GET_CODE (x) == CLOBBER)
9100: return;
9101:
9102: len = GET_RTX_LENGTH (code);
9103: fmt = GET_RTX_FORMAT (code);
9104:
9105: for (i = 0; i < len; i++)
9106: {
9107: if (fmt[i] == 'E')
9108: {
9109: register int j;
9110: for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9111: move_deaths (XVECEXP (x, i, j), from_cuid, to_insn, pnotes);
9112: }
9113: else if (fmt[i] == 'e')
9114: move_deaths (XEXP (x, i), from_cuid, to_insn, pnotes);
9115: }
9116: }
9117:
1.1.1.3 root 9118: /* Return 1 if X is the target of a bit-field assignment in BODY, the
9119: pattern of an insn. X must be a REG. */
1.1 root 9120:
9121: static int
1.1.1.3 root 9122: reg_bitfield_target_p (x, body)
9123: rtx x;
1.1 root 9124: rtx body;
9125: {
9126: int i;
9127:
9128: if (GET_CODE (body) == SET)
1.1.1.3 root 9129: {
9130: rtx dest = SET_DEST (body);
9131: rtx target;
9132: int regno, tregno, endregno, endtregno;
9133:
9134: if (GET_CODE (dest) == ZERO_EXTRACT)
9135: target = XEXP (dest, 0);
9136: else if (GET_CODE (dest) == STRICT_LOW_PART)
9137: target = SUBREG_REG (XEXP (dest, 0));
9138: else
9139: return 0;
9140:
9141: if (GET_CODE (target) == SUBREG)
9142: target = SUBREG_REG (target);
9143:
9144: if (GET_CODE (target) != REG)
9145: return 0;
9146:
9147: tregno = REGNO (target), regno = REGNO (x);
9148: if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
9149: return target == x;
9150:
9151: endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
9152: endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
9153:
9154: return endregno > tregno && regno < endtregno;
9155: }
1.1 root 9156:
9157: else if (GET_CODE (body) == PARALLEL)
9158: for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
1.1.1.3 root 9159: if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
1.1 root 9160: return 1;
9161:
9162: return 0;
9163: }
9164:
9165: /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
9166: as appropriate. I3 and I2 are the insns resulting from the combination
9167: insns including FROM (I2 may be zero).
9168:
9169: ELIM_I2 and ELIM_I1 are either zero or registers that we know will
9170: not need REG_DEAD notes because they are being substituted for. This
9171: saves searching in the most common cases.
9172:
9173: Each note in the list is either ignored or placed on some insns, depending
9174: on the type of note. */
9175:
9176: static void
9177: distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
9178: rtx notes;
9179: rtx from_insn;
9180: rtx i3, i2;
9181: rtx elim_i2, elim_i1;
9182: {
9183: rtx note, next_note;
9184: rtx tem;
9185:
9186: for (note = notes; note; note = next_note)
9187: {
9188: rtx place = 0, place2 = 0;
9189:
9190: /* If this NOTE references a pseudo register, ensure it references
9191: the latest copy of that register. */
9192: if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
9193: && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
9194: XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
9195:
9196: next_note = XEXP (note, 1);
9197: switch (REG_NOTE_KIND (note))
9198: {
9199: case REG_UNUSED:
9200: /* If this register is set or clobbered in I3, put the note there
9201: unless there is one already. */
9202: if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
9203: {
9204: if (! (GET_CODE (XEXP (note, 0)) == REG
9205: ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
9206: : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
9207: place = i3;
9208: }
9209: /* Otherwise, if this register is used by I3, then this register
9210: now dies here, so we must put a REG_DEAD note here unless there
9211: is one already. */
9212: else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
9213: && ! (GET_CODE (XEXP (note, 0)) == REG
9214: ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
9215: : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
9216: {
9217: PUT_REG_NOTE_KIND (note, REG_DEAD);
9218: place = i3;
9219: }
9220: break;
9221:
9222: case REG_EQUAL:
9223: case REG_EQUIV:
9224: case REG_NONNEG:
9225: /* These notes say something about results of an insn. We can
9226: only support them if they used to be on I3 in which case they
1.1.1.4 ! root 9227: remain on I3. Otherwise they are ignored.
! 9228:
! 9229: If the note refers to an expression that is not a constant, we
! 9230: must also ignore the note since we cannot tell whether the
! 9231: equivalence is still true. It might be possible to do
! 9232: slightly better than this (we only have a problem if I2DEST
! 9233: or I1DEST is present in the expression), but it doesn't
! 9234: seem worth the trouble. */
! 9235:
! 9236: if (from_insn == i3
! 9237: && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
1.1 root 9238: place = i3;
9239: break;
9240:
9241: case REG_INC:
9242: case REG_NO_CONFLICT:
9243: case REG_LABEL:
9244: /* These notes say something about how a register is used. They must
9245: be present on any use of the register in I2 or I3. */
9246: if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
9247: place = i3;
9248:
9249: if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
9250: {
9251: if (place)
9252: place2 = i2;
9253: else
9254: place = i2;
9255: }
9256: break;
9257:
9258: case REG_WAS_0:
9259: /* It is too much trouble to try to see if this note is still
9260: correct in all situations. It is better to simply delete it. */
9261: break;
9262:
9263: case REG_RETVAL:
9264: /* If the insn previously containing this note still exists,
9265: put it back where it was. Otherwise move it to the previous
9266: insn. Adjust the corresponding REG_LIBCALL note. */
9267: if (GET_CODE (from_insn) != NOTE)
9268: place = from_insn;
9269: else
9270: {
1.1.1.4 ! root 9271: tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
1.1 root 9272: place = prev_real_insn (from_insn);
9273: if (tem && place)
9274: XEXP (tem, 0) = place;
9275: }
9276: break;
9277:
9278: case REG_LIBCALL:
9279: /* This is handled similarly to REG_RETVAL. */
9280: if (GET_CODE (from_insn) != NOTE)
9281: place = from_insn;
9282: else
9283: {
1.1.1.4 ! root 9284: tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
1.1 root 9285: place = next_real_insn (from_insn);
9286: if (tem && place)
9287: XEXP (tem, 0) = place;
9288: }
9289: break;
9290:
9291: case REG_DEAD:
9292: /* If the register is used as an input in I3, it dies there.
9293: Similarly for I2, if it is non-zero and adjacent to I3.
9294:
9295: If the register is not used as an input in either I3 or I2
9296: and it is not one of the registers we were supposed to eliminate,
9297: there are two possibilities. We might have a non-adjacent I2
9298: or we might have somehow eliminated an additional register
9299: from a computation. For example, we might have had A & B where
9300: we discover that B will always be zero. In this case we will
9301: eliminate the reference to A.
9302:
9303: In both cases, we must search to see if we can find a previous
9304: use of A and put the death note there. */
9305:
9306: if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
9307: place = i3;
9308: else if (i2 != 0 && next_nonnote_insn (i2) == i3
9309: && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
9310: place = i2;
9311:
9312: if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
9313: break;
9314:
1.1.1.4 ! root 9315: /* If the register is used in both I2 and I3 and it dies in I3,
! 9316: we might have added another reference to it. If reg_n_refs
! 9317: was 2, bump it to 3. This has to be correct since the
! 9318: register must have been set somewhere. The reason this is
! 9319: done is because local-alloc.c treats 2 references as a
! 9320: special case. */
! 9321:
! 9322: if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
! 9323: && reg_n_refs[REGNO (XEXP (note, 0))]== 2
! 9324: && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
! 9325: reg_n_refs[REGNO (XEXP (note, 0))] = 3;
! 9326:
1.1 root 9327: if (place == 0)
9328: for (tem = prev_nonnote_insn (i3);
9329: tem && (GET_CODE (tem) == INSN
9330: || GET_CODE (tem) == CALL_INSN);
9331: tem = prev_nonnote_insn (tem))
9332: {
9333: /* If the register is being set at TEM, see if that is all
9334: TEM is doing. If so, delete TEM. Otherwise, make this
9335: into a REG_UNUSED note instead. */
9336: if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
9337: {
9338: rtx set = single_set (tem);
9339:
1.1.1.2 root 9340: /* Verify that it was the set, and not a clobber that
9341: modified the register. */
9342:
9343: if (set != 0 && ! side_effects_p (SET_SRC (set))
9344: && rtx_equal_p (XEXP (note, 0), SET_DEST (set)))
1.1 root 9345: {
9346: /* Move the notes and links of TEM elsewhere.
9347: This might delete other dead insns recursively.
9348: First set the pattern to something that won't use
9349: any register. */
9350:
9351: PATTERN (tem) = pc_rtx;
9352:
1.1.1.4 ! root 9353: distribute_notes (REG_NOTES (tem), tem, tem,
! 9354: NULL_RTX, NULL_RTX, NULL_RTX);
1.1 root 9355: distribute_links (LOG_LINKS (tem));
9356:
9357: PUT_CODE (tem, NOTE);
9358: NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
9359: NOTE_SOURCE_FILE (tem) = 0;
9360: }
9361: else
9362: {
9363: PUT_REG_NOTE_KIND (note, REG_UNUSED);
9364:
9365: /* If there isn't already a REG_UNUSED note, put one
9366: here. */
9367: if (! find_regno_note (tem, REG_UNUSED,
9368: REGNO (XEXP (note, 0))))
9369: place = tem;
9370: break;
9371: }
9372: }
9373: else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem)))
9374: {
9375: place = tem;
9376: break;
9377: }
9378: }
9379:
9380: /* If the register is set or already dead at PLACE, we needn't do
9381: anything with this note if it is still a REG_DEAD note.
9382:
9383: Note that we cannot use just `dead_or_set_p' here since we can
9384: convert an assignment to a register into a bit-field assignment.
9385: Therefore, we must also omit the note if the register is the
9386: target of a bitfield assignment. */
9387:
9388: if (place && REG_NOTE_KIND (note) == REG_DEAD)
9389: {
9390: int regno = REGNO (XEXP (note, 0));
9391:
9392: if (dead_or_set_p (place, XEXP (note, 0))
9393: || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
9394: {
9395: /* Unless the register previously died in PLACE, clear
9396: reg_last_death. [I no longer understand why this is
9397: being done.] */
9398: if (reg_last_death[regno] != place)
9399: reg_last_death[regno] = 0;
9400: place = 0;
9401: }
9402: else
9403: reg_last_death[regno] = place;
9404:
9405: /* If this is a death note for a hard reg that is occupying
9406: multiple registers, ensure that we are still using all
9407: parts of the object. If we find a piece of the object
9408: that is unused, we must add a USE for that piece before
9409: PLACE and put the appropriate REG_DEAD note on it.
9410:
9411: An alternative would be to put a REG_UNUSED for the pieces
9412: on the insn that set the register, but that can't be done if
9413: it is not in the same block. It is simpler, though less
9414: efficient, to add the USE insns. */
9415:
9416: if (place && regno < FIRST_PSEUDO_REGISTER
9417: && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
9418: {
9419: int endregno
9420: = regno + HARD_REGNO_NREGS (regno,
9421: GET_MODE (XEXP (note, 0)));
9422: int all_used = 1;
9423: int i;
9424:
9425: for (i = regno; i < endregno; i++)
9426: if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0))
9427: {
9428: rtx piece = gen_rtx (REG, word_mode, i);
1.1.1.3 root 9429: rtx p;
9430:
9431: /* See if we already placed a USE note for this
9432: register in front of PLACE. */
9433: for (p = place;
9434: GET_CODE (PREV_INSN (p)) == INSN
9435: && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
9436: p = PREV_INSN (p))
9437: if (rtx_equal_p (piece,
9438: XEXP (PATTERN (PREV_INSN (p)), 0)))
9439: {
9440: p = 0;
9441: break;
9442: }
9443:
9444: if (p)
9445: {
9446: rtx use_insn
9447: = emit_insn_before (gen_rtx (USE, VOIDmode,
9448: piece),
9449: p);
9450: REG_NOTES (use_insn)
9451: = gen_rtx (EXPR_LIST, REG_DEAD, piece,
9452: REG_NOTES (use_insn));
9453: }
1.1 root 9454:
1.1.1.2 root 9455: all_used = 0;
1.1 root 9456: }
9457:
9458: if (! all_used)
9459: {
9460: /* Put only REG_DEAD notes for pieces that are
9461: still used and that are not already dead or set. */
9462:
9463: for (i = regno; i < endregno; i++)
9464: {
9465: rtx piece = gen_rtx (REG, word_mode, i);
9466:
9467: if (reg_referenced_p (piece, PATTERN (place))
9468: && ! dead_or_set_p (place, piece)
9469: && ! reg_bitfield_target_p (piece,
9470: PATTERN (place)))
9471: REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
9472: piece,
9473: REG_NOTES (place));
9474: }
9475:
9476: place = 0;
9477: }
9478: }
9479: }
9480: break;
9481:
9482: default:
9483: /* Any other notes should not be present at this point in the
9484: compilation. */
9485: abort ();
9486: }
9487:
9488: if (place)
9489: {
9490: XEXP (note, 1) = REG_NOTES (place);
9491: REG_NOTES (place) = note;
9492: }
1.1.1.4 ! root 9493: else if ((REG_NOTE_KIND (note) == REG_DEAD
! 9494: || REG_NOTE_KIND (note) == REG_UNUSED)
! 9495: && GET_CODE (XEXP (note, 0)) == REG)
! 9496: reg_n_deaths[REGNO (XEXP (note, 0))]--;
1.1 root 9497:
9498: if (place2)
1.1.1.4 ! root 9499: {
! 9500: if ((REG_NOTE_KIND (note) == REG_DEAD
! 9501: || REG_NOTE_KIND (note) == REG_UNUSED)
! 9502: && GET_CODE (XEXP (note, 0)) == REG)
! 9503: reg_n_deaths[REGNO (XEXP (note, 0))]++;
! 9504:
! 9505: REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
! 9506: XEXP (note, 0), REG_NOTES (place2));
! 9507: }
1.1 root 9508: }
9509: }
9510:
9511: /* Similarly to above, distribute the LOG_LINKS that used to be present on
1.1.1.2 root 9512: I3, I2, and I1 to new locations. This is also called in one case to
9513: add a link pointing at I3 when I3's destination is changed. */
1.1 root 9514:
9515: static void
9516: distribute_links (links)
9517: rtx links;
9518: {
9519: rtx link, next_link;
9520:
9521: for (link = links; link; link = next_link)
9522: {
9523: rtx place = 0;
9524: rtx insn;
9525: rtx set, reg;
9526:
9527: next_link = XEXP (link, 1);
9528:
9529: /* If the insn that this link points to is a NOTE or isn't a single
9530: set, ignore it. In the latter case, it isn't clear what we
9531: can do other than ignore the link, since we can't tell which
9532: register it was for. Such links wouldn't be used by combine
9533: anyway.
9534:
9535: It is not possible for the destination of the target of the link to
9536: have been changed by combine. The only potential of this is if we
9537: replace I3, I2, and I1 by I3 and I2. But in that case the
9538: destination of I2 also remains unchanged. */
9539:
9540: if (GET_CODE (XEXP (link, 0)) == NOTE
9541: || (set = single_set (XEXP (link, 0))) == 0)
9542: continue;
9543:
9544: reg = SET_DEST (set);
9545: while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
9546: || GET_CODE (reg) == SIGN_EXTRACT
9547: || GET_CODE (reg) == STRICT_LOW_PART)
9548: reg = XEXP (reg, 0);
9549:
9550: /* A LOG_LINK is defined as being placed on the first insn that uses
9551: a register and points to the insn that sets the register. Start
9552: searching at the next insn after the target of the link and stop
9553: when we reach a set of the register or the end of the basic block.
9554:
9555: Note that this correctly handles the link that used to point from
1.1.1.2 root 9556: I3 to I2. Also note that not much searching is typically done here
1.1 root 9557: since most links don't point very far away. */
9558:
9559: for (insn = NEXT_INSN (XEXP (link, 0));
9560: (insn && GET_CODE (insn) != CODE_LABEL
9561: && GET_CODE (PREV_INSN (insn)) != JUMP_INSN);
9562: insn = NEXT_INSN (insn))
9563: if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
9564: && reg_overlap_mentioned_p (reg, PATTERN (insn)))
9565: {
9566: if (reg_referenced_p (reg, PATTERN (insn)))
9567: place = insn;
9568: break;
9569: }
9570:
9571: /* If we found a place to put the link, place it there unless there
9572: is already a link to the same insn as LINK at that point. */
9573:
9574: if (place)
9575: {
9576: rtx link2;
9577:
9578: for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
9579: if (XEXP (link2, 0) == XEXP (link, 0))
9580: break;
9581:
9582: if (link2 == 0)
9583: {
9584: XEXP (link, 1) = LOG_LINKS (place);
9585: LOG_LINKS (place) = link;
9586: }
9587: }
9588: }
9589: }
9590:
9591: void
9592: dump_combine_stats (file)
9593: FILE *file;
9594: {
9595: fprintf
9596: (file,
9597: ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
9598: combine_attempts, combine_merges, combine_extras, combine_successes);
9599: }
9600:
9601: void
9602: dump_combine_total_stats (file)
9603: FILE *file;
9604: {
9605: fprintf
9606: (file,
9607: "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
9608: total_attempts, total_merges, total_extras, total_successes);
9609: }
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