![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to combine.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [GCC 1.x] / gcc|
Return to combine.c CVS log | Up to [GCC 1.x] / gcc |
1.1 root 1: /* Optimize by combining instructions for GNU compiler.
1.1.1.2 root 2: Copyright (C) 1987, 1988 Free Software Foundation, Inc.
1.1 root 3:
4: This file is part of GNU CC.
5:
6: GNU CC is distributed in the hope that it will be useful,
7: but WITHOUT ANY WARRANTY. No author or distributor
8: accepts responsibility to anyone for the consequences of using it
9: or for whether it serves any particular purpose or works at all,
10: unless he says so in writing. Refer to the GNU CC General Public
11: License for full details.
12:
13: Everyone is granted permission to copy, modify and redistribute
14: GNU CC, but only under the conditions described in the
15: GNU CC General Public License. A copy of this license is
16: supposed to have been given to you along with GNU CC so you
17: can know your rights and responsibilities. It should be in a
18: file named COPYING. Among other things, the copyright notice
19: and this notice must be preserved on all copies. */
20:
21:
22: /* This module is essentially the "combiner" phase of the U. of Arizona
23: Portable Optimizer, but redone to work on our list-structured
24: representation for RTL instead of their string representation.
25:
26: The LOG_LINKS of each insn identify the most recent assignment
27: to each REG used in the insn. It is a list of previous insns,
28: each of which contains a SET for a REG that is used in this insn
29: and not used or set in between. LOG_LINKs never cross basic blocks.
30: They were set up by the preceding pass (lifetime analysis).
31:
32: We try to combine each pair of insns joined by a logical link.
33: We also try to combine triples of insns A, B and C when
34: C has a link back to B and B has a link back to A.
35:
36: LOG_LINKS does not have links for use of the CC0. They don't
37: need to, because the insn that sets the CC0 is always immediately
38: before the insn that tests it. So we always regard a branch
39: insn as having a logical link to the preceding insn.
40:
41: We check (with use_crosses_set_p) to avoid combining in such a way
42: as to move a computation to a place where its value would be different.
43:
44: Combination is done by mathematically substituting the previous
45: insn(s) values for the regs they set into the expressions in
46: the later insns that refer to these regs. If the result is a valid insn
47: for our target machine, according to the machine description,
48: we install it, delete the earlier insns, and update the data flow
49: information (LOG_LINKS and REG_NOTES) for what we did.
50:
51: To simplify substitution, we combine only when the earlier insn(s)
52: consist of only a single assignment. To simplify updating afterward,
53: we never combine when a subroutine call appears in the middle.
54:
55: Since we do not represent assignments to CC0 explicitly except when that
56: is all an insn does, there is no LOG_LINKS entry in an insn that uses
57: the condition code for the insn that set the condition code.
58: Fortunately, these two insns must be consecutive.
59: Therefore, every JUMP_INSN is taken to have an implicit logical link
60: to the preceding insn. This is not quite right, since non-jumps can
61: also use the condition code; but in practice such insns would not
62: combine anyway. */
63:
64: #include "config.h"
65: #include "rtl.h"
1.1.1.2 root 66: #include "flags.h"
1.1 root 67: #include "regs.h"
68: #include "basic-block.h"
69: #include "insn-config.h"
70: #include "recog.h"
71:
72: #define max(A,B) ((A) > (B) ? (A) : (B))
73: #define min(A,B) ((A) < (B) ? (A) : (B))
74:
1.1.1.2 root 75: /* It is not safe to use ordinary gen_lowpart in combine.
76: Use gen_lowpart_for_combine instead. See comments there. */
77: #define gen_lowpart dont_use_gen_lowpart_you_dummy
78:
1.1 root 79: /* Number of attempts to combine instructions in this function. */
80:
81: static int combine_attempts;
82:
83: /* Number of attempts that got as far as substitution in this function. */
84:
85: static int combine_merges;
86:
87: /* Number of instructions combined with added SETs in this function. */
88:
89: static int combine_extras;
90:
91: /* Number of instructions combined in this function. */
92:
93: static int combine_successes;
94:
95: /* Totals over entire compilation. */
96:
97: static int total_attempts, total_merges, total_extras, total_successes;
98:
99:
100: /* Vector mapping INSN_UIDs to cuids.
101: The cuids are like uids but increase monononically always.
102: Combine always uses cuids so that it can compare them.
103: But actually renumbering the uids, which we used to do,
104: proves to be a bad idea because it makes it hard to compare
105: the dumps produced by earlier passes with those from later passes. */
106:
107: static short *uid_cuid;
108:
109: /* Get the cuid of an insn. */
110:
111: #define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)])
112:
113:
114: /* Record last point of death of (hard or pseudo) register n. */
115:
116: static rtx *reg_last_death;
117:
118: /* Record last point of modification of (hard or pseudo) register n. */
119:
120: static rtx *reg_last_set;
121:
122: /* Record the cuid of the last insn that invalidated memory
123: (anything that writes memory, and subroutine calls). */
124:
125: static int mem_last_set;
126:
127: /* Record the cuid of the last CALL_INSN
128: so we can tell whether a potential combination crosses any calls. */
129:
130: static int last_call_cuid;
131:
132: /* When `subst' is called, this is the insn that is being modified
133: (by combining in a previous insn). The PATTERN of this insn
134: is still the old pattern partially modified and it should not be
135: looked at, but this may be used to examine the successors of the insn
136: to judge whether a simplification is valid. */
137:
138: static rtx subst_insn;
139:
140: /* Record one modification to rtl structure
141: to be undone by storing old_contents into *where. */
142:
143: struct undo
144: {
145: rtx *where;
146: rtx old_contents;
147: };
148:
149: /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
150: num_undo says how many are currently recorded.
151: storage is nonzero if we must undo the allocation of new storage.
152: The value of storage is what to pass to obfree. */
153:
154: #define MAX_UNDO 10
155:
156: struct undobuf
157: {
158: int num_undo;
159: char *storage;
160: struct undo undo[MAX_UNDO];
161: };
162:
163: static struct undobuf undobuf;
164:
1.1.1.2 root 165: /* Number of times the pseudo being substituted for
166: was found and replaced. */
167:
168: static int n_occurrences;
169:
1.1 root 170: static void move_deaths ();
1.1.1.4 root 171: void remove_death ();
1.1 root 172: static void record_dead_and_set_regs ();
173: int regno_dead_p ();
174: static int use_crosses_set_p ();
1.1.1.4 root 175: static int try_combine ();
1.1 root 176: static rtx subst ();
177: static void undo_all ();
1.1.1.2 root 178: static void copy_substitutions ();
1.1 root 179: static void add_links ();
180: static void add_incs ();
1.1.1.2 root 181: static int insn_has_inc_p ();
1.1 root 182: static int adjacent_insns_p ();
183: static rtx simplify_and_const_int ();
184: static rtx gen_lowpart_for_combine ();
185: static void simplify_set_cc0_and ();
186:
187: /* Main entry point for combiner. F is the first insn of the function.
188: NREGS is the first unused pseudo-reg number. */
189:
190: void
191: combine_instructions (f, nregs)
192: rtx f;
193: int nregs;
194: {
195: register rtx insn;
196: register int i;
197: register rtx links, nextlinks;
198: rtx prev;
199:
200: combine_attempts = 0;
201: combine_merges = 0;
202: combine_extras = 0;
203: combine_successes = 0;
204:
205: reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
206: reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
207: bzero (reg_last_death, nregs * sizeof (rtx));
208: bzero (reg_last_set, nregs * sizeof (rtx));
209:
210: init_recog ();
211:
212: /* Compute maximum uid value so uid_cuid can be allocated. */
213:
214: for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
215: if (INSN_UID (insn) > i)
216: i = INSN_UID (insn);
217:
218: uid_cuid = (short *) alloca ((i + 1) * sizeof (short));
219:
220: /* Compute the mapping from uids to cuids.
221: Cuids are numbers assigned to insns, like uids,
222: except that cuids increase monotonically through the code. */
223:
224: for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
225: INSN_CUID (insn) = ++i;
226:
227: /* Now scan all the insns in forward order. */
228:
229: last_call_cuid = 0;
230: mem_last_set = 0;
231: prev = 0;
232:
233: for (insn = f; insn; insn = NEXT_INSN (insn))
234: {
235: if (GET_CODE (insn) == INSN
236: || GET_CODE (insn) == CALL_INSN
237: || GET_CODE (insn) == JUMP_INSN)
238: {
239: retry:
240: /* Try this insn with each insn it links back to. */
241:
242: for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
243: if (try_combine (insn, XEXP (links, 0), 0))
244: goto retry;
245:
246: /* Try each sequence of three linked insns ending with this one. */
247:
248: for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
249: if (GET_CODE (XEXP (links, 0)) != NOTE)
250: for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
251: nextlinks = XEXP (nextlinks, 1))
252: if (try_combine (insn, XEXP (links, 0), XEXP (nextlinks, 0)))
253: goto retry;
254:
255: /* Try to combine a jump insn that uses CC0
256: with a preceding insn that sets CC0, and maybe with its
257: logical predecessor as well.
258: This is how we make decrement-and-branch insns.
259: We need this special code because data flow connections
260: via CC0 do not get entered in LOG_LINKS. */
261:
262: if (GET_CODE (insn) == JUMP_INSN
263: && prev != 0
264: && GET_CODE (prev) == INSN
265: && GET_CODE (PATTERN (prev)) == SET
266: && GET_CODE (SET_DEST (PATTERN (prev))) == CC0)
267: {
268: if (try_combine (insn, prev, 0))
269: goto retry;
270:
271: if (GET_CODE (prev) != NOTE)
272: for (nextlinks = LOG_LINKS (prev); nextlinks;
273: nextlinks = XEXP (nextlinks, 1))
274: if (try_combine (insn, prev, XEXP (nextlinks, 0)))
275: goto retry;
276: }
277: #if 0
278: /* Turned off because on 68020 it takes four insns to make
279: something like (a[b / 32] & (1 << (31 - (b % 32)))) != 0
280: that could actually be optimized, and that's an unlikely piece of code. */
281: /* If an insn gets or sets a bit field, try combining it
282: with two different insns whose results it uses. */
283: if (GET_CODE (insn) == INSN
284: && GET_CODE (PATTERN (insn)) == SET
285: && (GET_CODE (SET_DEST (PATTERN (insn))) == ZERO_EXTRACT
286: || GET_CODE (SET_DEST (PATTERN (insn))) == SIGN_EXTRACT
287: || GET_CODE (SET_SRC (PATTERN (insn))) == ZERO_EXTRACT
288: || GET_CODE (SET_SRC (PATTERN (insn))) == SIGN_EXTRACT))
289: {
290: for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
291: if (GET_CODE (XEXP (links, 0)) != NOTE)
292: for (nextlinks = XEXP (links, 1); nextlinks;
293: nextlinks = XEXP (nextlinks, 1))
294: if (try_combine (insn, XEXP (links, 0), XEXP (nextlinks, 0)))
295: goto retry;
296: }
297: #endif
298: record_dead_and_set_regs (insn);
299: prev = insn;
300: }
301: else if (GET_CODE (insn) != NOTE)
302: prev = 0;
303: }
304: total_attempts += combine_attempts;
305: total_merges += combine_merges;
306: total_extras += combine_extras;
307: total_successes += combine_successes;
308: }
309:
310: /* Try to combine the insns I1 and I2 into I3.
311: Here I1 appears earlier than I2, which is earlier than I3.
312: I1 can be zero; then we combine just I2 into I3.
313:
314: Return 1 if successful; if that happens, I1 and I2 are pseudo-deleted
315: by turning them into NOTEs, and I3 is modified.
316: Return 0 if the combination does not work. Then nothing is changed. */
317:
318: static int
319: try_combine (i3, i2, i1)
320: register rtx i3, i2, i1;
321: {
322: register rtx newpat;
323: int added_sets_1 = 0;
324: int added_sets_2 = 0;
325: int total_sets;
326: int i2_is_used;
327: register rtx link;
328: int insn_code_number;
329: int recog_flags = 0;
330: rtx i2dest, i2src;
331: rtx i1dest, i1src;
1.1.1.2 root 332: int maxreg;
1.1 root 333:
334: combine_attempts++;
335:
336: /* Don't combine with something already used up by combination. */
337:
338: if (GET_CODE (i2) == NOTE
339: || (i1 && GET_CODE (i1) == NOTE))
340: return 0;
341:
342: /* Don't combine across a CALL_INSN, because that would possibly
343: change whether the life span of some REGs crosses calls or not,
344: and it is a pain to update that information. */
345:
346: if (INSN_CUID (i2) < last_call_cuid
347: || (i1 && INSN_CUID (i1) < last_call_cuid))
348: return 0;
349:
350: /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
351: That REG must be either set or dead by the final instruction
352: (so that we can safely forget about setting it).
353: Also test use_crosses_set_p to make sure that the value
354: that is to be substituted for the register
355: does not use any registers whose values alter in between.
356: Do not try combining with moves from one register to another
357: since it is better to let them be tied by register allocation.
1.1.1.2 root 358: (There is a switch to permit such combination; except the insns
359: that copy a function value into another register are never combined
360: because moving that too far away from the function call could cause
361: something else to be stored in that register in the interim.)
1.1 root 362:
363: A set of a SUBREG is considered as if it were a set from
364: SUBREG. Thus, (SET (SUBREG:X (REG:Y...)) (something:X...))
365: is handled by substituting (SUBREG:Y (something:X...)) for (REG:Y...). */
366:
367: if (GET_CODE (PATTERN (i2)) != SET)
368: return 0;
369: i2dest = SET_DEST (PATTERN (i2));
370: i2src = SET_SRC (PATTERN (i2));
371: if (GET_CODE (i2dest) == SUBREG)
372: {
373: i2dest = SUBREG_REG (i2dest);
374: i2src = gen_rtx (SUBREG, GET_MODE (i2dest), i2src, 0);
375: }
1.1.1.4 root 376: /* Don't eliminate a store in the stack pointer. */
377: if (i2dest == stack_pointer_rtx)
378: return 0;
1.1 root 379: if (GET_CODE (i2dest) != CC0
380: && (GET_CODE (i2dest) != REG
1.1.1.2 root 381: || (GET_CODE (i2src) == REG
382: && (!flag_combine_regs
1.1.1.5 root 383: /* Don't substitute a function value reg for any other. */
384: || FUNCTION_VALUE_REGNO_P (REGNO (i2src))
385: /* Don't substitute a different reg into an increment. */
386: || find_reg_note (i3, REG_INC, i2dest)))
1.1.1.2 root 387: || GET_CODE (i2src) == CALL
1.1 root 388: || use_crosses_set_p (i2src, INSN_CUID (i2))))
389: return 0;
390:
391: if (i1 != 0)
392: {
393: if (GET_CODE (PATTERN (i1)) != SET)
394: return 0;
395: i1dest = SET_DEST (PATTERN (i1));
396: i1src = SET_SRC (PATTERN (i1));
397: if (GET_CODE (i1dest) == SUBREG)
398: {
399: i1dest = SUBREG_REG (i1dest);
400: i1src = gen_rtx (SUBREG, GET_MODE (i1dest), i1src, 0);
401: }
1.1.1.4 root 402: if (i1dest == stack_pointer_rtx)
403: return 0;
1.1 root 404: if (GET_CODE (i1dest) != CC0
405: && (GET_CODE (i1dest) != REG
1.1.1.2 root 406: || (GET_CODE (i1src) == REG
407: && (!flag_combine_regs
1.1.1.5 root 408: || FUNCTION_VALUE_REGNO_P (REGNO (i1src))
409: || find_reg_note (i3, REG_INC, i1dest)
410: || find_reg_note (i2, REG_INC, i1dest)))
1.1.1.2 root 411: || GET_CODE (i1src) == CALL
1.1 root 412: || use_crosses_set_p (i1src, INSN_CUID (i1))))
413: return 0;
414: }
415:
416: /* If I1 or I2 contains an autoincrement or autodecrement,
417: make sure that register is not used between there and I3.
418: Also insist that I3 not be a jump; if it were one
419: and the incremented register were spilled, we would lose. */
1.1.1.5 root 420: for (link = REG_NOTES (i2); link; link = XEXP (link, 1))
421: if (REG_NOTE_KIND (link) == REG_INC
422: && (GET_CODE (i3) == JUMP_INSN
423: || reg_used_between_p (XEXP (link, 0), i2, i3)
424: || reg_mentioned_p (XEXP (link, 0), i3)))
425: return 0;
1.1 root 426:
1.1.1.5 root 427: if (i1)
428: for (link = REG_NOTES (i1); link; link = XEXP (link, 1))
429: if (REG_NOTE_KIND (link) == REG_INC
430: && (GET_CODE (i3) == JUMP_INSN
431: || reg_used_between_p (XEXP (link, 0), i1, i3)
432: || reg_mentioned_p (XEXP (link, 0), i3)))
433: return 0;
1.1 root 434:
435: /* See if the SETs in i1 or i2 need to be kept around in the merged
436: instruction: whenever the value set there is still needed past i3. */
437: added_sets_2 = (GET_CODE (i2dest) != CC0
438: && ! dead_or_set_p (i3, i2dest));
439: if (i1)
440: added_sets_1 = ! (dead_or_set_p (i3, i1dest)
441: || dead_or_set_p (i2, i1dest));
442:
443: combine_merges++;
444:
445: undobuf.num_undo = 0;
446: undobuf.storage = 0;
447:
448: /* Substitute in the latest insn for the regs set by the earlier ones. */
449:
1.1.1.2 root 450: maxreg = max_reg_num ();
451:
1.1 root 452: subst_insn = i3;
1.1.1.2 root 453: n_occurrences = 0; /* `subst' counts here */
454:
1.1 root 455: newpat = subst (PATTERN (i3), i2dest, i2src);
456: /* Record whether i2's body now appears within i3's body. */
1.1.1.2 root 457: i2_is_used = n_occurrences;
1.1 root 458:
459: if (i1)
1.1.1.2 root 460: {
461: n_occurrences = 0;
462: newpat = subst (newpat, i1dest, i1src);
463: }
1.1 root 464:
465: if (GET_CODE (PATTERN (i3)) == SET
466: && SET_DEST (PATTERN (i3)) == cc0_rtx
1.1.1.2 root 467: && (GET_CODE (SET_SRC (PATTERN (i3))) == AND
468: || GET_CODE (SET_SRC (PATTERN (i3))) == LSHIFTRT)
1.1 root 469: && next_insn_tests_no_inequality (i3))
470: simplify_set_cc0_and (i3);
471:
1.1.1.2 root 472: if (max_reg_num () != maxreg)
473: abort ();
474:
1.1 root 475: /* If the actions of the earler insns must be kept
476: in addition to substituting them into the latest one,
477: we must make a new PARALLEL for the latest insn
478: to hold additional the SETs. */
479:
480: if (added_sets_1 || added_sets_2)
481: {
482: combine_extras++;
483:
484: /* Arrange to free later what we allocate now
485: if we don't accept this combination. */
486: if (!undobuf.storage)
487: undobuf.storage = (char *) oballoc (0);
488:
489: if (GET_CODE (newpat) == PARALLEL)
490: {
1.1.1.2 root 491: rtvec old = XVEC (newpat, 0);
1.1 root 492: total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1.1.1.2 root 493: newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
494: bcopy (&old->elem[0], &XVECEXP (newpat, 0, 0),
495: sizeof (old->elem[0]) * old->num_elem);
1.1 root 496: }
497: else
498: {
1.1.1.2 root 499: rtx old = newpat;
1.1 root 500: total_sets = 1 + added_sets_1 + added_sets_2;
1.1.1.2 root 501: newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
502: XVECEXP (newpat, 0, 0) = old;
1.1 root 503: }
504: if (added_sets_1)
505: {
506: XVECEXP (newpat, 0, --total_sets) = PATTERN (i1);
507: }
508: if (added_sets_2)
509: {
510: /* If there is no I1, use I2's body as is. */
511: if (i1 == 0
512: /* If I2 was stuck into I3, then anything within it has
513: already had I1 substituted into it when that was done to I3. */
514: || i2_is_used)
515: {
516: XVECEXP (newpat, 0, --total_sets) = PATTERN (i2);
517: }
518: else
519: XVECEXP (newpat, 0, --total_sets)
520: = subst (PATTERN (i2), i1dest, i1src);
521: }
522: }
523:
1.1.1.2 root 524: /* Fail if an autoincrement side-effect has been duplicated. */
525: if ((i2_is_used > 1 && find_reg_note (i2, REG_INC, 0) != 0)
526: || (i1 != 0 && n_occurrences > 1 && find_reg_note (i1, REG_INC, 0) != 0))
527: {
528: undo_all ();
529: return 0;
530: }
531:
1.1 root 532: /* Is the result of combination a valid instruction? */
533: insn_code_number = recog (newpat, i3);
534:
535: if (insn_code_number >= 0)
536: {
537: /* Yes. Install it. */
538: register int regno;
539: INSN_CODE (i3) = insn_code_number;
540: PATTERN (i3) = newpat;
1.1.1.2 root 541: /* If anything was substituted more than once,
542: copy it to avoid invalid shared rtl structure. */
543: copy_substitutions ();
544: /* The data flowing into I2 now flows into I3.
545: But we cannot always move all of I2's LOG_LINKS into I3,
546: since they must go to a setting of a REG from the
547: first use following. If I2 was the first use following a set,
548: I3 is now a use, but it is not the first use
549: if some instruction between I2 and I3 is also a use.
550: Here, for simplicity, we move all the links only if
551: there are no real insns between I2 and I3.
552: Otherwise, we move only links that correspond to regs
553: that used to die in I2. They are always safe to move. */
554: add_links (i3, i2, adjacent_insns_p (i2, i3));
1.1 root 555: /* Most REGs that previously died in I2 now die in I3. */
556: move_deaths (i2src, INSN_CUID (i2), i3);
557: if (GET_CODE (i2dest) == REG)
558: {
559: /* If the reg formerly set in I2 died only once and that was in I3,
560: zero its use count so it won't make `reload' do any work. */
561: regno = REGNO (i2dest);
562: if (! added_sets_2)
1.1.1.2 root 563: {
564: reg_n_sets[regno]--;
565: /* Used to check && regno_dead_p (regno, i3) also here. */
566: if (reg_n_sets[regno] == 0
567: && ! (basic_block_live_at_start[0][regno / HOST_BITS_PER_INT]
568: & (1 << (regno % HOST_BITS_PER_INT))))
569: reg_n_refs[regno] = 0;
570: }
1.1 root 571: /* If a ref to REGNO was substituted into I3 from I2,
572: then it still dies there if it previously did.
573: Otherwise either REGNO never did die in I3 so remove_death is safe
574: or this entire life of REGNO is gone so remove its death. */
575: if (!added_sets_2
576: && ! reg_mentioned_p (i2dest, PATTERN (i3)))
577: remove_death (regno, i3);
578: }
579: /* Any registers previously autoincremented in I2
580: are now incremented in I3. */
581: add_incs (i3, REG_NOTES (i2));
582: if (i1)
583: {
584: /* Likewise, merge the info from I1 and get rid of it. */
1.1.1.2 root 585: add_links (i3, i1,
586: adjacent_insns_p (i1, i2) && adjacent_insns_p (i2, i3));
1.1 root 587: move_deaths (i1src, INSN_CUID (i1), i3);
588: if (GET_CODE (i1dest) == REG)
589: {
590: regno = REGNO (i1dest);
591: if (! added_sets_1)
1.1.1.2 root 592: {
593: reg_n_sets[regno]--;
594: /* Used to also check && regno_dead_p (regno, i3) here. */
595:
596: if (reg_n_sets[regno] == 0
597: && ! (basic_block_live_at_start[0][regno / HOST_BITS_PER_INT]
598: & (1 << (regno % HOST_BITS_PER_INT))))
599:
600: reg_n_refs[regno] = 0;
601: }
1.1 root 602: /* If a ref to REGNO was substituted into I3 from I1,
603: then it still dies there if it previously did.
604: Else either REGNO never did die in I3 so remove_death is safe
605: or this entire life of REGNO is gone so remove its death. */
606: if (! added_sets_1
607: && ! reg_mentioned_p (i1dest, PATTERN (i3)))
608: remove_death (regno, i3);
609: }
610: add_incs (i3, REG_NOTES (i1));
611: LOG_LINKS (i1) = 0;
612: PUT_CODE (i1, NOTE);
613: NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
614: NOTE_SOURCE_FILE (i1) = 0;
615: }
1.1.1.2 root 616: /* Get rid of I2. */
617: LOG_LINKS (i2) = 0;
618: PUT_CODE (i2, NOTE);
619: NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
620: NOTE_SOURCE_FILE (i2) = 0;
1.1 root 621:
622: combine_successes++;
623: return 1;
624: }
625:
626: /* Failure: change I3 back the way it was. */
627: undo_all ();
628:
629: return 0;
630: }
631:
632: /* Undo all the modifications recorded in undobuf. */
633:
634: static void
635: undo_all ()
636: {
637: register int i;
638: if (undobuf.num_undo > MAX_UNDO)
639: undobuf.num_undo = MAX_UNDO;
640: for (i = undobuf.num_undo - 1; i >= 0; i--)
641: *undobuf.undo[i].where = undobuf.undo[i].old_contents;
642: if (undobuf.storage)
643: obfree (undobuf.storage);
644: undobuf.num_undo = 0;
645: undobuf.storage = 0;
646: }
647:
1.1.1.2 root 648: /* If this insn had more than one substitution,
649: copy all but one, so that no invalid shared substructure is introduced. */
650:
651: static void
652: copy_substitutions ()
653: {
654: register int i;
655: if (undobuf.num_undo > 1)
656: {
657: for (i = undobuf.num_undo - 1; i >= 1; i--)
658: *undobuf.undo[i].where = copy_rtx (*undobuf.undo[i].where);
659: }
660: }
661:
1.1 root 662: /* Throughout X, replace FROM with TO, and return the result.
663: The result is TO if X is FROM;
664: otherwise the result is X, but its contents may have been modified.
665: If they were modified, a record was made in undobuf so that
666: undo_all will (among other things) return X to its original state.
667:
668: If the number of changes necessary is too much to record to undo,
669: the excess changes are not made, so the result is invalid.
670: The changes already made can still be undone.
671: undobuf.num_undo is incremented for such changes, so by testing that
1.1.1.2 root 672: the caller can tell whether the result is valid.
673:
674: `n_occurrences' is incremented each time FROM is replaced. */
1.1 root 675:
676: static rtx
677: subst (x, from, to)
678: register rtx x, from, to;
679: {
680: register char *fmt;
681: register int len, i;
682: register enum rtx_code code;
1.1.1.2 root 683: char was_replaced[2];
1.1 root 684:
1.1.1.2 root 685: #define SUBST(INTO, NEWVAL) \
686: do { if (undobuf.num_undo < MAX_UNDO) \
687: { \
688: undobuf.undo[undobuf.num_undo].where = &INTO; \
689: undobuf.undo[undobuf.num_undo].old_contents = INTO; \
690: INTO = NEWVAL; \
691: } \
692: undobuf.num_undo++; } while (0)
693:
694: /* FAKE_EXTEND_SAFE_P (MODE, FROM) is 1 if (subreg:MODE FROM 0) is a safe
695: replacement for (zero_extend:MODE FROM) or (sign_extend:MODE FROM).
1.1.1.6 ! root 696: If it is 0, that cannot be done. We can now do this for any MEM
! 697: because (SUBREG (MEM...)) is guaranteed to cause the MEM to be reloaded.
! 698: If not for that, MEM's would very rarely be safe. */
1.1.1.2 root 699:
1.1.1.6 ! root 700: #define FAKE_EXTEND_SAFE_P(MODE, FROM) (GET_CODE (FROM) == REG || GET_CODE (FROM) == MEM)
1.1 root 701:
702: if (x == from)
703: return to;
704:
1.1.1.2 root 705: /* It is possible to have a subexpression appear twice in the insn.
706: Suppose that FROM is a register that appears within TO.
707: Then, after that subexpression has been scanned once by `subst',
708: the second time it is scanned, TO may be found. If we were
709: to scan TO here, we would find FROM within it and create a
710: self-referent rtl structure which is completely wrong. */
711: if (x == to)
712: return to;
713:
1.1 root 714: code = GET_CODE (x);
715:
716: /* A little bit of algebraic simplification here. */
717: switch (code)
718: {
719: /* This case has no effect except to speed things up. */
720: case REG:
721: case CONST_INT:
722: case CONST:
723: case SYMBOL_REF:
724: case LABEL_REF:
725: case PC:
726: case CC0:
727: return x;
1.1.1.2 root 728: }
729:
730: was_replaced[0] = 0;
731: was_replaced[1] = 0;
732:
733: len = GET_RTX_LENGTH (code);
734: fmt = GET_RTX_FORMAT (code);
735:
736: /* Don't replace FROM where it is being stored in rather than used. */
737: if (code == SET && SET_DEST (x) == from)
738: fmt = "ie";
739: if (code == SET && GET_CODE (SET_DEST (x)) == SUBREG
740: && SUBREG_REG (SET_DEST (x)) == from)
741: fmt = "ie";
742:
743: for (i = 0; i < len; i++)
744: {
745: if (fmt[i] == 'E')
746: {
747: register int j;
748: for (j = XVECLEN (x, i) - 1; j >= 0; j--)
749: {
750: register rtx new;
751: if (XVECEXP (x, i, j) == from)
752: new = to, n_occurrences++;
753: else
754: new = subst (XVECEXP (x, i, j), from, to);
755: if (new != XVECEXP (x, i, j))
756: SUBST (XVECEXP (x, i, j), new);
757: }
758: }
759: else if (fmt[i] == 'e')
760: {
761: register rtx new;
762:
763: if (XEXP (x, i) == from)
764: {
765: new = to;
766: n_occurrences++;
767: if (i < 2)
768: was_replaced[i] = 1;
769: }
770: else
771: new = subst (XEXP (x, i), from, to);
772:
773: if (new != XEXP (x, i))
774: SUBST (XEXP (x, i), new);
775: }
776: }
777:
778: /* A little bit of algebraic simplification here. */
779: switch (code)
780: {
781: case SUBREG:
782: /* Changing mode twice with SUBREG => just change it once,
783: or not at all if changing back to starting mode. */
784: if (SUBREG_REG (x) == to
785: && GET_CODE (to) == SUBREG
786: && SUBREG_WORD (x) == 0
787: && SUBREG_WORD (to) == 0)
788: {
789: if (GET_MODE (x) == GET_MODE (SUBREG_REG (to)))
790: return SUBREG_REG (to);
791: SUBST (SUBREG_REG (x), SUBREG_REG (to));
792: }
1.1.1.4 root 793: /* (subreg (sign_extend X)) is X, if it has same mode as X. */
794: if (SUBREG_REG (x) == to
795: && (GET_CODE (to) == SIGN_EXTEND || GET_CODE (to) == ZERO_EXTEND)
796: && SUBREG_WORD (x) == 0
797: && GET_MODE (x) == GET_MODE (XEXP (to, 0)))
798: return XEXP (to, 0);
1.1.1.2 root 799: break;
1.1 root 800:
801: case NOT:
1.1.1.4 root 802: /* (not (minus X 1)) can become (neg X). */
803: if (was_replaced[0]
804: && ((GET_CODE (to) == PLUS && INTVAL (XEXP (to, 1)) == -1)
805: || (GET_CODE (to) == MINUS && XEXP (to, 1) == const1_rtx)))
806: return gen_rtx (NEG, GET_MODE (to), XEXP (to, 0));
807: /* Don't let substitution introduce double-negatives. */
808: if (was_replaced[0]
809: && GET_CODE (to) == code)
810: return XEXP (to, 0);
811: break;
812:
1.1 root 813: case NEG:
1.1.1.4 root 814: /* (neg (minus X Y)) can become (minus Y X). */
815: if (was_replaced[0] && GET_CODE (to) == MINUS)
816: return gen_rtx (MINUS, GET_MODE (to),
817: XEXP (to, 1), XEXP (to, 0));
1.1 root 818: /* Don't let substitution introduce double-negatives. */
1.1.1.2 root 819: if (was_replaced[0]
1.1 root 820: && GET_CODE (to) == code)
821: return XEXP (to, 0);
822: break;
823:
1.1.1.2 root 824: case FLOAT_TRUNCATE:
825: /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
826: if (was_replaced[0]
827: && GET_CODE (to) == FLOAT_EXTEND
828: && GET_MODE (XEXP (to, 0)) == GET_MODE (x))
829: return XEXP (to, 0);
830: break;
831:
1.1 root 832: case PLUS:
833: /* In (plus <foo> (ashift <bar> <n>))
834: change the shift to a multiply so we can recognize
835: scaled indexed addresses. */
1.1.1.2 root 836: if ((was_replaced[0]
837: || was_replaced[1])
1.1 root 838: && GET_CODE (to) == ASHIFT
1.1.1.2 root 839: && GET_CODE (XEXP (to, 1)) == CONST_INT
840: && INTVAL (XEXP (to, 1)) < HOST_BITS_PER_INT)
841: {
842: rtx temp;
843: if (!undobuf.storage)
844: undobuf.storage = (char *) oballoc (0);
845: temp = gen_rtx (MULT, GET_MODE (to),
846: XEXP (to, 0),
847: gen_rtx (CONST_INT, VOIDmode,
848: 1 << INTVAL (XEXP (to, 1))));
849: if (was_replaced[0])
850: SUBST (XEXP (x, 0), temp);
851: else
852: SUBST (XEXP (x, 1), temp);
853: }
854: /* (plus X (neg Y)) becomes (minus X Y). */
855: if (GET_CODE (XEXP (x, 1)) == NEG)
856: {
857: if (!undobuf.storage)
858: undobuf.storage = (char *) oballoc (0);
859: return gen_rtx (MINUS, GET_MODE (x),
860: XEXP (x, 0), XEXP (XEXP (x, 1), 0));
861: }
862: /* (plus (neg X) Y) becomes (minus Y X). */
863: if (GET_CODE (XEXP (x, 0)) == NEG)
1.1 root 864: {
865: if (!undobuf.storage)
866: undobuf.storage = (char *) oballoc (0);
1.1.1.2 root 867: return gen_rtx (MINUS, GET_MODE (x),
868: XEXP (x, 1), XEXP (XEXP (x, 0), 0));
869: }
870: /* (plus (plus x c1) c2) => (plus x c1+c2) */
871: if (GET_CODE (XEXP (x, 1)) == CONST_INT
872: && GET_CODE (XEXP (x, 0)) == PLUS
873: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
874: {
875: int sum = (INTVAL (XEXP (x, 1))
876: + INTVAL (XEXP (XEXP (x, 0), 1)));
877: if (sum == 0)
878: return XEXP (XEXP (x, 0), 0);
879: if (!undobuf.storage)
880: undobuf.storage = (char *) oballoc (0);
881: SUBST (XEXP (x, 1), gen_rtx (CONST_INT, VOIDmode, sum));
882: SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
883: break;
1.1 root 884: }
885: /* If we have something (putative index) being added to a sum,
886: associate it so that any constant term is outermost.
887: That's because that's the way indexed addresses are
888: now supposed to appear. */
1.1.1.2 root 889: if (((was_replaced[0] && GET_CODE (XEXP (x, 1)) == PLUS)
890: || (was_replaced[1] && GET_CODE (XEXP (x, 0)) == PLUS))
1.1 root 891: ||
1.1.1.2 root 892: ((was_replaced[0] || was_replaced[1])
893: && GET_CODE (to) == PLUS))
1.1 root 894: {
895: rtx offset = 0, base, index;
1.1.1.2 root 896: if (GET_CODE (to) != PLUS)
1.1 root 897: {
1.1.1.2 root 898: index = to;
899: base = was_replaced[0] ? XEXP (x, 1) : XEXP (x, 0);
1.1 root 900: }
901: else
902: {
1.1.1.2 root 903: index = was_replaced[0] ? XEXP (x, 1) : XEXP (x, 0);
904: base = to;
1.1 root 905: }
906: if (CONSTANT_ADDRESS_P (XEXP (base, 0)))
907: {
908: offset = XEXP (base, 0);
909: base = XEXP (base, 1);
910: }
911: else if (CONSTANT_ADDRESS_P (XEXP (base, 1)))
912: {
913: offset = XEXP (base, 1);
914: base = XEXP (base, 0);
915: }
916: if (offset != 0)
917: {
918: if (!undobuf.storage)
919: undobuf.storage = (char *) oballoc (0);
1.1.1.2 root 920: if (GET_CODE (offset) == CONST_INT)
921: return plus_constant (gen_rtx (PLUS, GET_MODE (index),
922: base, index),
923: INTVAL (offset));
924: if (GET_CODE (index) == CONST_INT)
925: return plus_constant (gen_rtx (PLUS, GET_MODE (offset),
926: base, offset),
927: INTVAL (index));
928: return gen_rtx (PLUS, GET_MODE (index),
1.1 root 929: gen_rtx (PLUS, GET_MODE (index),
1.1.1.2 root 930: base, index),
931: offset);
1.1 root 932: }
933: }
934: break;
935:
936: case MINUS:
937: /* Can simplify (minus:VOIDmode (zero/sign_extend FOO) CONST)
938: (which is a compare instruction, not a subtract instruction)
939: to (minus FOO CONST) if CONST fits in FOO's mode
940: and we are only testing equality.
941: In fact, this is valid for zero_extend if what follows is an
942: unsigned comparison, and for sign_extend with a signed comparison. */
943: if (GET_MODE (x) == VOIDmode
1.1.1.2 root 944: && was_replaced[0]
1.1 root 945: && (GET_CODE (to) == ZERO_EXTEND || GET_CODE (to) == SIGN_EXTEND)
946: && next_insn_tests_no_inequality (subst_insn)
947: && GET_CODE (XEXP (x, 1)) == CONST_INT
1.1.1.2 root 948: /* This is overly cautious by one bit, but saves worrying about
949: whether it is zero-extension or sign extension. */
1.1 root 950: && ((unsigned) INTVAL (XEXP (x, 1))
1.1.1.2 root 951: < (1 << (GET_MODE_BITSIZE (GET_MODE (XEXP (to, 0))) - 1))))
952: SUBST (XEXP (x, 0), XEXP (to, 0));
1.1 root 953: break;
954:
955: case EQ:
956: case NE:
957: /* If comparing a subreg against zero, discard the subreg. */
1.1.1.2 root 958: if (was_replaced[0]
1.1 root 959: && GET_CODE (to) == SUBREG
960: && SUBREG_WORD (to) == 0
961: && XEXP (x, 1) == const0_rtx)
1.1.1.2 root 962: SUBST (XEXP (x, 0), SUBREG_REG (to));
1.1 root 963:
964: /* If comparing a ZERO_EXTRACT against zero,
965: canonicalize to a SIGN_EXTRACT,
966: since the two are equivalent here. */
1.1.1.2 root 967: if (was_replaced[0]
968: && GET_CODE (to) == ZERO_EXTRACT
1.1 root 969: && XEXP (x, 1) == const0_rtx)
970: {
971: if (!undobuf.storage)
972: undobuf.storage = (char *) oballoc (0);
1.1.1.2 root 973: SUBST (XEXP (x, 0),
974: gen_rtx (SIGN_EXTRACT, GET_MODE (to),
975: XEXP (to, 0), XEXP (to, 1),
976: XEXP (to, 2)));
1.1 root 977: }
978: /* If we are putting (ASHIFT 1 x) into (EQ (AND ... y) 0),
979: arrange to return (EQ (SIGN_EXTRACT y 1 x) 0),
980: which is what jump-on-bit instructions are written with. */
981: else if (XEXP (x, 1) == const0_rtx
982: && GET_CODE (XEXP (x, 0)) == AND
1.1.1.2 root 983: && (XEXP (XEXP (x, 0), 0) == to
984: || XEXP (XEXP (x, 0), 1) == to)
985: && GET_CODE (to) == ASHIFT
986: && XEXP (to, 0) == const1_rtx)
1.1 root 987: {
988: register rtx y = XEXP (XEXP (x, 0),
1.1.1.2 root 989: XEXP (XEXP (x, 0), 0) == to);
1.1 root 990: if (!undobuf.storage)
991: undobuf.storage = (char *) oballoc (0);
1.1.1.2 root 992: SUBST (XEXP (x, 0),
993: gen_rtx (SIGN_EXTRACT, GET_MODE (to),
994: y,
995: const1_rtx, XEXP (to, 1)));
1.1 root 996: }
997:
998: break;
999:
1000: case ZERO_EXTEND:
1.1.1.2 root 1001: if (was_replaced[0]
1.1 root 1002: && GET_CODE (to) == ZERO_EXTEND)
1.1.1.2 root 1003: SUBST (XEXP (x, 0), XEXP (to, 0));
1.1 root 1004: /* Zero-extending the result of an and with a constant can be done
1005: with a wider and. */
1.1.1.2 root 1006: if (was_replaced[0]
1.1 root 1007: && GET_CODE (to) == AND
1008: && GET_CODE (XEXP (to, 1)) == CONST_INT
1.1.1.2 root 1009: && FAKE_EXTEND_SAFE_P (GET_MODE (x), XEXP (to, 0))
1.1 root 1010: /* Avoid getting wrong result if the constant has high bits set
1011: that are irrelevant in the narrow mode where it is being used. */
1.1.1.2 root 1012: && 0 == (INTVAL (XEXP (to, 1))
1013: & ~ GET_MODE_MASK (GET_MODE (to))))
1.1 root 1014: {
1015: if (!undobuf.storage)
1016: undobuf.storage = (char *) oballoc (0);
1017: return gen_rtx (AND, GET_MODE (x),
1.1.1.2 root 1018: gen_lowpart_for_combine (GET_MODE (x), XEXP (to, 0)),
1.1 root 1019: XEXP (to, 1));
1.1.1.2 root 1020: }
1021: /* Change (zero_extend:M (subreg:N (zero_extract:M ...) 0))
1022: to (zero_extract:M ...) if the field extracted fits in mode N. */
1023: if (GET_CODE (XEXP (x, 0)) == SUBREG
1024: && GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTRACT
1025: && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1026: && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
1027: <= GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
1028: {
1029: return XEXP (XEXP (x, 0), 0);
1030: }
1.1 root 1031: break;
1032:
1033: case SIGN_EXTEND:
1.1.1.2 root 1034: if (was_replaced[0]
1.1 root 1035: && GET_CODE (to) == SIGN_EXTEND)
1.1.1.2 root 1036: SUBST (XEXP (x, 0), XEXP (to, 0));
1.1 root 1037: /* Sign-extending the result of an and with a constant can be done
1038: with a wider and, provided the high bit of the constant is 0. */
1.1.1.2 root 1039: if (was_replaced[0]
1.1 root 1040: && GET_CODE (to) == AND
1041: && GET_CODE (XEXP (to, 1)) == CONST_INT
1.1.1.2 root 1042: && FAKE_EXTEND_SAFE_P (GET_MODE (x), XEXP (to, 0))
1.1 root 1043: && ((INTVAL (XEXP (to, 1))
1.1.1.2 root 1044: & (-1 << (GET_MODE_BITSIZE (GET_MODE (to)) - 1)))
1.1 root 1045: == 0))
1046: {
1047: if (!undobuf.storage)
1048: undobuf.storage = (char *) oballoc (0);
1049: return gen_rtx (AND, GET_MODE (x),
1.1.1.2 root 1050: gen_lowpart_for_combine (GET_MODE (x), XEXP (to, 0)),
1.1 root 1051: XEXP (to, 1));
1052: }
1053: break;
1054:
1055: case SET:
1.1.1.2 root 1056: /* In (set (zero-extract <x> <n> <y>) (and <foo> <(2**n-1) | anything>))
1.1 root 1057: the `and' can be deleted. This can happen when storing a bit
1.1.1.2 root 1058: that came from a set-flag insn followed by masking to one bit. */
1.1 root 1059: if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
1.1.1.2 root 1060: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1061: && was_replaced[1]
1.1 root 1062: && GET_CODE (to) == AND
1.1.1.2 root 1063: && GET_CODE (XEXP (to, 1)) == CONST_INT
1064: && 0 == (((1 << INTVAL (XEXP (XEXP (x, 0), 1))) - 1)
1065: & ~ INTVAL (XEXP (to, 1))))
1.1 root 1066: {
1.1.1.2 root 1067: SUBST (XEXP (x, 1), XEXP (to, 0));
1068: }
1069: /* In (set (zero-extract <x> <n> <y>)
1070: (subreg (and <foo> <(2**n-1) | anything>)))
1071: the `and' can be deleted. */
1072: if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
1073: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1074: && GET_CODE (XEXP (x, 1)) == SUBREG
1075: && SUBREG_WORD (XEXP (x, 1)) == 0
1076: && GET_CODE (SUBREG_REG (XEXP (x, 1))) == AND
1077: && GET_CODE (XEXP (SUBREG_REG (XEXP (x, 1)), 1)) == CONST_INT
1078: && 0 == (((1 << INTVAL (XEXP (XEXP (x, 0), 1))) - 1)
1079: & ~ INTVAL (XEXP (SUBREG_REG (XEXP (x, 1)), 1))))
1080: {
1081: SUBST (SUBREG_REG (XEXP (x, 1)), XEXP (SUBREG_REG (XEXP (x, 1)), 0));
1082: }
1083: /* (set (zero_extract ...) (and/or/xor (zero_extract ...) const)),
1.1.1.5 root 1084: if both zero_extracts have the same location, size and position,
1.1.1.2 root 1085: can be changed to avoid the byte extracts. */
1086: if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
1087: || GET_CODE (XEXP (x, 0)) == SIGN_EXTRACT)
1088: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1089: && (GET_CODE (XEXP (x, 1)) == AND
1090: || GET_CODE (XEXP (x, 1)) == IOR
1091: || GET_CODE (XEXP (x, 1)) == XOR)
1.1.1.5 root 1092: && rtx_equal_p (XEXP (x, 0), XEXP (XEXP (x, 1), 0))
1.1.1.2 root 1093: && GET_CODE (XEXP (XEXP (x, 1), 0)) == GET_CODE (XEXP (x, 0))
1094: && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
1095: {
1096: #ifdef BITS_BIG_ENDIAN
1097: int shiftcount
1098: = GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
1099: - INTVAL (XEXP (XEXP (x, 0), 1)) - INTVAL (XEXP (XEXP (x, 0), 2));
1100: #else
1101: int shiftcount
1102: = INTVAL (XEXP (XEXP (x, 0), 2));
1103: #endif
1104: if (!undobuf.storage)
1105: undobuf.storage = (char *) oballoc (0);
1106: return
1107: gen_rtx (SET, VOIDmode,
1108: XEXP (XEXP (x, 0), 0),
1109: gen_rtx (GET_CODE (XEXP (x, 1)),
1110: GET_MODE (XEXP (XEXP (x, 0), 0)),
1111: XEXP (XEXP (XEXP (x, 1), 0), 0),
1112: gen_rtx (CONST_INT, VOIDmode,
1113: (INTVAL (XEXP (XEXP (x, 1), 1))
1114: << shiftcount)
1115: + (GET_CODE (XEXP (x, 1)) == AND
1116: ? (1 << shiftcount) - 1
1117: : 0))));
1118: }
1.1 root 1119: break;
1120:
1121: case AND:
1122: if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1123: {
1.1.1.2 root 1124: rtx tem = simplify_and_const_int (x, to);
1.1 root 1125: if (tem)
1126: return tem;
1127: }
1128: break;
1129:
1130: case FLOAT:
1131: /* (float (sign_extend <X>)) = (float <X>). */
1.1.1.2 root 1132: if (was_replaced[0]
1.1 root 1133: && GET_CODE (to) == SIGN_EXTEND)
1.1.1.2 root 1134: SUBST (XEXP (x, 0), XEXP (to, 0));
1.1 root 1135: break;
1136:
1137: case ZERO_EXTRACT:
1.1.1.2 root 1138: /* (ZERO_EXTRACT (TRUNCATE x)...)
1139: can become (ZERO_EXTRACT x ...). */
1140: if (was_replaced[0]
1141: && GET_CODE (to) == TRUNCATE)
1142: {
1143: #ifdef BITS_BIG_ENDIAN
1144: if (GET_CODE (XEXP (x, 2)) == CONST_INT)
1145: {
1146: if (!undobuf.storage)
1147: undobuf.storage = (char *) oballoc (0);
1148: /* On a big-endian machine, must increment the bit-number
1149: since sign bit is farther away in the pre-truncated value. */
1150: return gen_rtx (ZERO_EXTRACT, GET_MODE (x),
1151: XEXP (to, 0),
1152: XEXP (x, 1),
1153: gen_rtx (CONST_INT, VOIDmode,
1154: (INTVAL (XEXP (x, 2))
1155: + GET_MODE_BITSIZE (GET_MODE (XEXP (to, 0)))
1156: - GET_MODE_BITSIZE (GET_MODE (to)))));
1157: }
1158: #else
1159: SUBST (XEXP (x, 0), XEXP (to, 0));
1160: #endif
1161: }
1.1 root 1162: /* Extracting a single bit from the result of a shift:
1163: see which bit it was before the shift and extract that directly. */
1.1.1.2 root 1164: if (was_replaced[0]
1.1 root 1165: && (GET_CODE (to) == ASHIFTRT || GET_CODE (to) == LSHIFTRT
1166: || GET_CODE (to) == ASHIFT || GET_CODE (to) == LSHIFT)
1167: && GET_CODE (XEXP (to, 1)) == CONST_INT
1168: && XEXP (x, 1) == const1_rtx
1169: && GET_CODE (XEXP (x, 2)) == CONST_INT)
1170: {
1171: int shift = INTVAL (XEXP (to, 1));
1172: int newpos;
1173: if (GET_CODE (to) == ASHIFT || GET_CODE (to) == LSHIFT)
1174: shift = - shift;
1175: #ifdef BITS_BIG_ENDIAN
1176: shift = - shift;
1177: #endif
1178: newpos = INTVAL (XEXP (x, 2)) + shift;
1179: if (newpos >= 0 &&
1.1.1.2 root 1180: newpos < GET_MODE_BITSIZE (GET_MODE (to)))
1.1 root 1181: {
1182: if (!undobuf.storage)
1183: undobuf.storage = (char *) oballoc (0);
1184: return gen_rtx (ZERO_EXTRACT, GET_MODE (x),
1185: XEXP (to, 0), const1_rtx,
1186: gen_rtx (CONST_INT, VOIDmode, newpos));
1187: }
1188: }
1189: break;
1190:
1191: case LSHIFTRT:
1192: case ASHIFTRT:
1193: case ROTATE:
1194: case ROTATERT:
1195: #ifdef SHIFT_COUNT_TRUNCATED
1196: /* (lshift <X> (sign_extend <Y>)) = (lshift <X> <Y>) (most machines).
1197: True for all kinds of shifts and also for zero_extend. */
1.1.1.2 root 1198: if (was_replaced[1]
1.1 root 1199: && (GET_CODE (to) == SIGN_EXTEND
1.1.1.2 root 1200: || GET_CODE (to) == ZERO_EXTEND)
1201: && FAKE_EXTEND_SAFE_P (GET_MODE (to), XEXP (to, 0)))
1.1 root 1202: {
1203: if (!undobuf.storage)
1204: undobuf.storage = (char *) oballoc (0);
1.1.1.2 root 1205: SUBST (XEXP (x, 1),
1206: /* This is a perverse SUBREG, wider than its base. */
1207: gen_lowpart_for_combine (GET_MODE (to), XEXP (to, 0)));
1.1 root 1208: }
1209: #endif
1210: /* Two shifts in a row of same kind
1211: in same direction with constant counts
1212: may be combined. */
1.1.1.2 root 1213: if (was_replaced[0]
1.1 root 1214: && GET_CODE (to) == GET_CODE (x)
1215: && GET_CODE (XEXP (x, 1)) == CONST_INT
1216: && GET_CODE (XEXP (to, 1)) == CONST_INT
1217: && INTVAL (XEXP (to, 1)) > 0
1218: && INTVAL (XEXP (x, 1)) > 0
1219: && (INTVAL (XEXP (x, 1)) + INTVAL (XEXP (to, 1))
1.1.1.2 root 1220: < GET_MODE_BITSIZE (GET_MODE (x))))
1.1 root 1221: {
1222: if (!undobuf.storage)
1223: undobuf.storage = (char *) oballoc (0);
1224: return gen_rtx (GET_CODE (x), GET_MODE (x),
1225: XEXP (to, 0),
1226: gen_rtx (CONST_INT, VOIDmode,
1227: INTVAL (XEXP (x, 1))
1228: + INTVAL (XEXP (to, 1))));
1229: }
1230: break;
1231:
1232: case LSHIFT:
1233: case ASHIFT:
1234: #ifdef SHIFT_COUNT_TRUNCATED
1235: /* (lshift <X> (sign_extend <Y>)) = (lshift <X> <Y>) (most machines).
1236: True for all kinds of shifts and also for zero_extend. */
1.1.1.2 root 1237: if (was_replaced[1]
1.1 root 1238: && (GET_CODE (to) == SIGN_EXTEND
1.1.1.4 root 1239: || GET_CODE (to) == ZERO_EXTEND)
1240: && GET_CODE (to) == REG)
1.1 root 1241: {
1242: if (!undobuf.storage)
1243: undobuf.storage = (char *) oballoc (0);
1.1.1.2 root 1244: SUBST (XEXP (x, 1), gen_rtx (SUBREG, GET_MODE (to), XEXP (to, 0), 0));
1.1 root 1245: }
1246: #endif
1247: /* (lshift (and (lshiftrt <foo> <X>) <Y>) <X>)
1248: happens copying between bit fields in similar structures.
1249: It can be replaced by one and instruction.
1250: It does not matter whether the shifts are logical or arithmetic. */
1251: if (GET_CODE (XEXP (x, 0)) == AND
1252: && GET_CODE (XEXP (x, 1)) == CONST_INT
1253: && INTVAL (XEXP (x, 1)) > 0
1254: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1.1.1.2 root 1255: && XEXP (XEXP (x, 0), 0) == to
1.1 root 1256: && (GET_CODE (to) == LSHIFTRT
1257: || GET_CODE (to) == ASHIFTRT)
1258: #if 0
1259: /* I now believe this restriction is unnecessary.
1260: The outer shift will discard those bits in any case, right? */
1261:
1262: /* If inner shift is arithmetic, either it shifts left or
1263: the bits it shifts the sign into are zeroed by the and. */
1264: && (INTVAL (XEXP (x, 1)) < 0
1265: || ((unsigned) INTVAL (XEXP (XEXP (x, 0), 1))
1266: < 1 << (GET_MODE_BITSIZE (GET_MODE (x))
1267: - INTVAL (XEXP (x, 0)))))
1268: #endif
1269: && GET_CODE (XEXP (to, 1)) == CONST_INT
1270: && INTVAL (XEXP (x, 1)) == INTVAL (XEXP (to, 1)))
1271: {
1272: if (!undobuf.storage)
1273: undobuf.storage = (char *) oballoc (0);
1274: /* The constant in the new `and' is <Y> << <X>
1275: but clear out all bits that don't belong in our mode. */
1276: return gen_rtx (AND, GET_MODE (x), XEXP (to, 0),
1277: gen_rtx (CONST_INT, VOIDmode,
1278: (GET_MODE_MASK (GET_MODE (x))
1279: & ((GET_MODE_MASK (GET_MODE (x))
1280: & INTVAL (XEXP (XEXP (x, 0), 1)))
1281: << INTVAL (XEXP (x, 1))))));
1282: }
1283: /* Two shifts in a row in same direction with constant counts
1284: may be combined. */
1.1.1.2 root 1285: if (was_replaced[0]
1.1 root 1286: && (GET_CODE (to) == ASHIFT || GET_CODE (to) == LSHIFT)
1287: && GET_CODE (XEXP (x, 1)) == CONST_INT
1288: && GET_CODE (XEXP (to, 1)) == CONST_INT
1289: && INTVAL (XEXP (to, 1)) > 0
1290: && INTVAL (XEXP (x, 1)) > 0
1291: && (INTVAL (XEXP (x, 1)) + INTVAL (XEXP (to, 1))
1.1.1.2 root 1292: < GET_MODE_BITSIZE (GET_MODE (x))))
1.1 root 1293: {
1294: if (!undobuf.storage)
1295: undobuf.storage = (char *) oballoc (0);
1296: return gen_rtx (GET_CODE (x), GET_MODE (x),
1297: XEXP (to, 0),
1298: gen_rtx (CONST_INT, VOIDmode,
1299: INTVAL (XEXP (x, 1))
1300: + INTVAL (XEXP (to, 1))));
1301: }
1302: /* (ashift (ashiftrt <foo> <X>) <X>)
1303: (or, on some machines, (ashift (ashift <foo> <-X>) <X>) instead)
1304: happens if you divide by 2**N and then multiply by 2**N.
1305: It can be replaced by one `and' instruction.
1306: It does not matter whether the shifts are logical or arithmetic. */
1307: if (GET_CODE (XEXP (x, 1)) == CONST_INT
1308: && INTVAL (XEXP (x, 1)) > 0
1.1.1.2 root 1309: && was_replaced[0]
1.1 root 1310: && (((GET_CODE (to) == LSHIFTRT || GET_CODE (to) == ASHIFTRT)
1311: && GET_CODE (XEXP (to, 1)) == CONST_INT
1312: && INTVAL (XEXP (x, 1)) == INTVAL (XEXP (to, 1)))
1313: ||
1314: ((GET_CODE (to) == LSHIFT || GET_CODE (to) == ASHIFT)
1315: && GET_CODE (XEXP (to, 1)) == CONST_INT
1316: && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (to, 1)))))
1317: {
1318: if (!undobuf.storage)
1319: undobuf.storage = (char *) oballoc (0);
1.1.1.2 root 1320: /* The constant in the new `and' is -1 << <X>
1.1 root 1321: but clear out all bits that don't belong in our mode. */
1322: return gen_rtx (AND, GET_MODE (x), XEXP (to, 0),
1323: gen_rtx (CONST_INT, VOIDmode,
1324: (GET_MODE_MASK (GET_MODE (x))
1325: & (GET_MODE_MASK (GET_MODE (x))
1326: << INTVAL (XEXP (x, 1))))));
1327: }
1328:
1329: }
1330:
1331: return x;
1332: }
1333:
1334: /* This is the AND case of the function subst. */
1335:
1336: static rtx
1.1.1.2 root 1337: simplify_and_const_int (x, to)
1338: rtx x, to;
1.1 root 1339: {
1340: register rtx varop = XEXP (x, 0);
1341: register int constop = INTVAL (XEXP (x, 1));
1342:
1343: /* (and (subreg (and <foo> <constant>) 0) <constant>)
1344: results from an andsi followed by an andqi,
1345: which happens frequently when storing bit-fields
1346: on something whose result comes from an andsi. */
1347: if (GET_CODE (varop) == SUBREG
1.1.1.2 root 1348: && XEXP (varop, 0) == to
1.1 root 1349: && subreg_lowpart_p (varop)
1350: && GET_CODE (to) == AND
1351: && GET_CODE (XEXP (to, 1)) == CONST_INT
1352: /* Verify that the result of the outer `and'
1353: is not affected by any bits not defined in the inner `and'.
1354: True if the outer mode is narrower, or if the outer constant
1355: masks to zero all the bits that the inner mode doesn't have. */
1.1.1.2 root 1356: && (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (GET_MODE (to))
1357: || (constop & ~ GET_MODE_MASK (GET_MODE (to))) == 0))
1.1 root 1358: {
1359: if (!undobuf.storage)
1360: undobuf.storage = (char *) oballoc (0);
1361: return gen_rtx (AND, GET_MODE (x),
1.1.1.2 root 1362: gen_lowpart_for_combine (GET_MODE (x), XEXP (to, 0)),
1.1 root 1363: gen_rtx (CONST_INT, VOIDmode,
1364: constop
1365: /* Remember that the bits outside that mode
1366: are not being changed, so the effect
1367: is as if they were all 1. */
1368: & INTVAL (XEXP (to, 1))));
1369: }
1.1.1.2 root 1370: /* (and:SI (zero_extract:SI ...) <constant>)
1371: results from an andsi following a byte-fetch on risc machines.
1372: When the constant includes all bits extracted, eliminate the `and'. */
1373: if (GET_CODE (varop) == ZERO_EXTRACT
1374: && GET_CODE (XEXP (varop, 1)) == CONST_INT
1375: /* The `and' must not clear any bits that the extract can give. */
1376: && (~ constop & ((1 << INTVAL (XEXP (varop, 1))) - 1)) == 0)
1377: return varop;
1.1 root 1378: /* (and (zero_extend <foo>) <constant>)
1379: often results from storing in a bit-field something
1380: that was calculated as a short. Replace with a single `and'
1381: in whose constant all bits not in <foo>'s mode are zero. */
1.1.1.2 root 1382: if (varop == to
1383: && GET_CODE (to) == ZERO_EXTEND
1384: && FAKE_EXTEND_SAFE_P (GET_MODE (x), XEXP (to, 0)))
1.1 root 1385: {
1386: if (!undobuf.storage)
1387: undobuf.storage = (char *) oballoc (0);
1388: return gen_rtx (AND, GET_MODE (x),
1.1.1.2 root 1389: /* This is a perverse SUBREG, wider than its base. */
1390: gen_lowpart_for_combine (GET_MODE (x), XEXP (to, 0)),
1.1 root 1391: gen_rtx (CONST_INT, VOIDmode,
1.1.1.2 root 1392: constop & GET_MODE_MASK (GET_MODE (XEXP (to, 0)))));
1.1 root 1393: }
1394: /* (and (sign_extend <foo>) <constant>)
1395: can be replaced with (and (subreg <foo>) <constant>)
1396: if <constant> is narrower than <foo>'s mode,
1397: or with (zero_extend <foo>) if <constant> is a mask for that mode. */
1.1.1.2 root 1398: if (varop == to
1.1 root 1399: && GET_CODE (to) == SIGN_EXTEND
1.1.1.2 root 1400: && ((unsigned) constop <= GET_MODE_MASK (GET_MODE (XEXP (to, 0))))
1401: && FAKE_EXTEND_SAFE_P (GET_MODE (x), XEXP (to, 0)))
1.1 root 1402: {
1403: if (!undobuf.storage)
1404: undobuf.storage = (char *) oballoc (0);
1.1.1.2 root 1405: if (constop == GET_MODE_MASK (GET_MODE (XEXP (to, 0))))
1.1 root 1406: return gen_rtx (ZERO_EXTEND, GET_MODE (x), XEXP (to, 0));
1407: return gen_rtx (AND, GET_MODE (x),
1.1.1.2 root 1408: /* This is a perverse SUBREG, wider than its base. */
1409: gen_lowpart_for_combine (GET_MODE (x), XEXP (to, 0)),
1.1 root 1410: XEXP (x, 1));
1411: }
1412: /* (and (and <foo> <constant>) <constant>)
1413: comes from two and instructions in a row. */
1.1.1.2 root 1414: if (varop == to
1.1 root 1415: && GET_CODE (to) == AND
1416: && GET_CODE (XEXP (to, 1)) == CONST_INT)
1417: {
1418: if (!undobuf.storage)
1419: undobuf.storage = (char *) oballoc (0);
1420: return gen_rtx (AND, GET_MODE (x),
1421: XEXP (to, 0),
1422: gen_rtx (CONST_INT, VOIDmode,
1423: constop
1424: & INTVAL (XEXP (to, 1))));
1425: }
1426: /* (and (ashiftrt (ashift FOO N) N) CONST)
1427: may be simplified to (and FOO CONST) if CONST masks off the bits
1428: changed by the two shifts. */
1429: if (GET_CODE (varop) == ASHIFTRT
1430: && GET_CODE (XEXP (varop, 1)) == CONST_INT
1.1.1.2 root 1431: && XEXP (varop, 0) == to
1.1 root 1432: && GET_CODE (to) == ASHIFT
1433: && GET_CODE (XEXP (to, 1)) == CONST_INT
1434: && INTVAL (XEXP (varop, 1)) == INTVAL (XEXP (to, 1))
1435: && ((unsigned) constop >> INTVAL (XEXP (varop, 1))) == 0)
1436: {
1437: if (!undobuf.storage)
1438: undobuf.storage = (char *) oballoc (0);
1439: /* If CONST is a mask for the low byte,
1440: change this into a zero-extend instruction
1441: from just the low byte of FOO. */
1.1.1.2 root 1442: if (constop == GET_MODE_MASK (QImode))
1.1 root 1443: {
1444: rtx temp = gen_lowpart_for_combine (QImode, XEXP (to, 0));
1.1.1.2 root 1445: if (GET_CODE (temp) != CLOBBER)
1.1 root 1446: return gen_rtx (ZERO_EXTEND, GET_MODE (x), temp);
1447: }
1448: return gen_rtx (AND, GET_MODE (x),
1449: XEXP (to, 0), XEXP (x, 1));
1450: }
1.1.1.2 root 1451: /* (and x const) may be converted to (zero_extend (subreg x 0)). */
1.1.1.4 root 1452: if (constop == GET_MODE_MASK (QImode)
1453: && GET_CODE (varop) == REG)
1.1.1.2 root 1454: {
1455: if (!undobuf.storage)
1456: undobuf.storage = (char *) oballoc (0);
1457: return gen_rtx (ZERO_EXTEND, GET_MODE (x),
1458: gen_rtx (SUBREG, QImode, varop, 0));
1459: }
1.1.1.4 root 1460: if (constop == GET_MODE_MASK (HImode)
1461: && GET_CODE (varop) == REG)
1.1.1.2 root 1462: {
1463: if (!undobuf.storage)
1464: undobuf.storage = (char *) oballoc (0);
1465: return gen_rtx (ZERO_EXTEND, GET_MODE (x),
1466: gen_rtx (SUBREG, HImode, varop, 0));
1467: }
1.1 root 1468: /* No simplification applies. */
1469: return 0;
1470: }
1471:
1472: /* Like gen_lowpart but for use by combine. In combine it is not possible
1473: to create any new pseudoregs. However, it is safe to create
1474: invalid memory addresses, because combine will try to recognize
1475: them and all they will do is make the combine attempt fail.
1476:
1.1.1.2 root 1477: If for some reason this cannot do its job, an rtx
1478: (clobber (const_int 0)) is returned.
1479: An insn containing that will not be recognized. */
1480:
1481: #undef gen_lowpart
1.1 root 1482:
1483: static rtx
1484: gen_lowpart_for_combine (mode, x)
1485: enum machine_mode mode;
1486: register rtx x;
1487: {
1488: if (GET_CODE (x) == SUBREG || GET_CODE (x) == REG)
1489: return gen_lowpart (mode, x);
1.1.1.2 root 1490: if (GET_MODE (x) == mode || x->volatil)
1491: return gen_rtx (CLOBBER, VOIDmode, const0_rtx);
1.1 root 1492: if (GET_CODE (x) == MEM)
1493: {
1494: register int offset = 0;
1495: #ifdef WORDS_BIG_ENDIAN
1496: offset = (max (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
1497: - max (GET_MODE_SIZE (mode), UNITS_PER_WORD));
1498: #endif
1499: #ifdef BYTES_BIG_ENDIAN
1.1.1.2 root 1500: /* Adjust the address so that the address-after-the-data
1501: is unchanged. */
1502: offset -= (min (UNITS_PER_WORD, GET_MODE_SIZE (mode))
1503: - min (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
1.1 root 1504: #endif
1505: return gen_rtx (MEM, mode, plus_constant (XEXP (x, 0),
1506: offset));
1507: }
1508: else
1.1.1.2 root 1509: return gen_rtx (CLOBBER, VOIDmode, const0_rtx);
1.1 root 1510: }
1511:
1512: /* After substitution, if the resulting pattern looks like
1.1.1.2 root 1513: (set (cc0) (and ...)) or (set (cc0) (lshiftrt ...)),
1514: this function is called to simplify the
1.1 root 1515: pattern into a bit-field operation if possible. */
1516:
1517: static void
1518: simplify_set_cc0_and (insn)
1519: rtx insn;
1520: {
1521: register rtx value = XEXP (PATTERN (insn), 1);
1522: register rtx op0 = XEXP (value, 0);
1523: register rtx op1 = XEXP (value, 1);
1524: int offset = 0;
1525: rtx var = 0;
1526: rtx bitnum = 0;
1527: int temp;
1528: int unit;
1.1.1.2 root 1529: rtx newpat;
1530:
1531: if (GET_CODE (value) == AND)
1532: {
1533: op0 = XEXP (value, 0);
1534: op1 = XEXP (value, 1);
1535: }
1536: else if (GET_CODE (value) == LSHIFTRT)
1537: {
1538: /* If there is no AND, but there is a shift that discards
1539: all but the sign bit, we can pretend that the shift result
1540: is ANDed with 1. Otherwise we cannot handle just a shift. */
1541: if (GET_CODE (XEXP (value, 1)) == CONST_INT
1542: && (INTVAL (XEXP (value, 1))
1543: == GET_MODE_BITSIZE (GET_MODE (value)) - 1))
1544: {
1545: op0 = value;
1546: op1 = const1_rtx;
1547: }
1548: else
1549: return;
1550: }
1551: else
1552: abort ();
1.1 root 1553:
1554: /* Look for a constant power of 2 or a shifted 1
1555: on either side of the AND. Set VAR to the other side.
1556: Set BITNUM to the shift count of the 1 (as an rtx).
1557: Or, if bit number is constant, set OFFSET to the bit number. */
1558:
1559: switch (GET_CODE (op0))
1560: {
1561: case CONST_INT:
1562: temp = exact_log2 (INTVAL (op0));
1563: if (temp < 0)
1564: return;
1565: offset = temp;
1566: var = op1;
1567: break;
1568:
1569: case ASHIFT:
1570: case LSHIFT:
1571: if (XEXP (op0, 0) == const1_rtx)
1572: {
1573: bitnum = XEXP (op0, 1);
1574: var = op1;
1575: }
1576: }
1577: if (var == 0)
1578: switch (GET_CODE (op1))
1579: {
1580: case CONST_INT:
1581: temp = exact_log2 (INTVAL (op1));
1582: if (temp < 0)
1583: return;
1584: offset = temp;
1585: var = op0;
1586: break;
1587:
1588: case ASHIFT:
1589: case LSHIFT:
1590: if (XEXP (op1, 0) == const1_rtx)
1591: {
1592: bitnum = XEXP (op1, 1);
1593: var = op0;
1594: }
1595: }
1596:
1597: /* If VAR is 0, we didn't find something recognizable. */
1598: if (var == 0)
1599: return;
1600:
1601: if (!undobuf.storage)
1602: undobuf.storage = (char *) oballoc (0);
1603:
1604: /* If the bit position is currently exactly 0,
1605: extract a right-shift from the variable portion. */
1606: if (offset == 0
1607: && (GET_CODE (var) == ASHIFTRT || GET_CODE (var) == LSHIFTRT))
1608: {
1609: bitnum = XEXP (var, 1);
1610: var = XEXP (var, 0);
1611: }
1612:
1.1.1.2 root 1613: if (GET_CODE (var) == SUBREG && SUBREG_WORD (var) == 0)
1614: var = SUBREG_REG (var);
1615:
1616: /* Note that BITNUM and OFFSET are always little-endian thru here
1617: even on a big-endian machine. */
1618:
1.1 root 1619: #ifdef BITS_BIG_ENDIAN
1.1.1.2 root 1620: unit = GET_MODE_BITSIZE (GET_MODE (var)) - 1;
1.1 root 1621:
1622: if (bitnum != 0)
1623: bitnum = gen_rtx (MINUS, SImode,
1624: gen_rtx (CONST_INT, VOIDmode, unit), bitnum);
1625: else
1626: offset = unit - offset;
1627: #endif
1628:
1629: if (bitnum == 0)
1630: bitnum = gen_rtx (CONST_INT, VOIDmode, offset);
1631:
1.1.1.2 root 1632: newpat = gen_rtx (SET, VOIDmode, cc0_rtx,
1633: gen_rtx (ZERO_EXTRACT, VOIDmode, var, const1_rtx, bitnum));
1634: if (recog (newpat, insn) >= 0)
1.1 root 1635: {
1.1.1.2 root 1636: if (undobuf.num_undo < MAX_UNDO)
1637: {
1638: undobuf.undo[undobuf.num_undo].where = &XEXP (PATTERN (insn), 1);
1639: undobuf.undo[undobuf.num_undo].old_contents = value;
1640: XEXP (PATTERN (insn), 1) = XEXP (newpat, 1);
1641: }
1642: undobuf.num_undo++;
1.1 root 1643: }
1644: }
1645:
1646: /* Update the records of when each REG was most recently set or killed
1647: for the things done by INSN. This is the last thing done in processing
1648: INSN in the combiner loop.
1649:
1650: We update reg_last_set, reg_last_death, and also the similar information
1651: mem_last_set (which insn most recently modified memory)
1652: and last_call_cuid (which insn was the most recent subroutine call). */
1653:
1654: static void
1655: record_dead_and_set_regs (insn)
1656: rtx insn;
1657: {
1658: register rtx link;
1659: for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1660: {
1.1.1.2 root 1661: if (REG_NOTE_KIND (link) == REG_DEAD)
1.1 root 1662: reg_last_death[REGNO (XEXP (link, 0))] = insn;
1.1.1.2 root 1663: else if (REG_NOTE_KIND (link) == REG_INC)
1.1 root 1664: reg_last_set[REGNO (XEXP (link, 0))] = insn;
1665: }
1666:
1667: if (GET_CODE (insn) == CALL_INSN)
1668: last_call_cuid = mem_last_set = INSN_CUID (insn);
1669:
1670: if (GET_CODE (PATTERN (insn)) == PARALLEL)
1671: {
1672: register int i;
1673: for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
1674: {
1675: register rtx elt = XVECEXP (PATTERN (insn), 0, i);
1676: register enum rtx_code code = GET_CODE (elt);
1677: if (code == SET || code == CLOBBER)
1678: {
1679: if (GET_CODE (XEXP (elt, 0)) == REG)
1680: reg_last_set[REGNO (XEXP (elt, 0))] = insn;
1.1.1.2 root 1681: if (GET_CODE (XEXP (elt, 0)) == SUBREG
1682: && GET_CODE (SUBREG_REG (XEXP (elt, 0))) == REG)
1683: reg_last_set[REGNO (SUBREG_REG (XEXP (elt, 0)))] = insn;
1.1 root 1684: else if (GET_CODE (XEXP (elt, 0)) == MEM)
1685: mem_last_set = INSN_CUID (insn);
1686: }
1687: }
1688: }
1689: else if (GET_CODE (PATTERN (insn)) == SET
1690: || GET_CODE (PATTERN (insn)) == CLOBBER)
1691: {
1692: register rtx x = XEXP (PATTERN (insn), 0);
1693: if (GET_CODE (x) == REG)
1694: reg_last_set[REGNO (x)] = insn;
1.1.1.2 root 1695: if (GET_CODE (x) == SUBREG
1696: && GET_CODE (SUBREG_REG (x)) == REG)
1697: reg_last_set[REGNO (SUBREG_REG (x))] = insn;
1.1 root 1698: else if (GET_CODE (x) == MEM)
1699: mem_last_set = INSN_CUID (insn);
1700: }
1701: }
1702:
1703: /* Return nonzero if expression X refers to a REG or to memory
1704: that is set in an instruction more recent than FROM_CUID. */
1705:
1706: static int
1707: use_crosses_set_p (x, from_cuid)
1708: register rtx x;
1709: int from_cuid;
1710: {
1711: register char *fmt;
1712: register int i;
1713: register enum rtx_code code = GET_CODE (x);
1714:
1715: if (code == REG)
1716: {
1717: register int regno = REGNO (x);
1718: return (reg_last_set[regno]
1719: && INSN_CUID (reg_last_set[regno]) > from_cuid);
1720: }
1721:
1722: if (code == MEM && mem_last_set > from_cuid)
1723: return 1;
1724:
1725: fmt = GET_RTX_FORMAT (code);
1726:
1727: for (i = GET_RTX_LENGTH (code); i >= 0; i--)
1728: {
1729: if (fmt[i] == 'E')
1730: {
1731: register int j;
1732: for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1733: if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
1734: return 1;
1735: }
1736: else if (fmt[i] == 'e'
1737: && use_crosses_set_p (XEXP (x, i), from_cuid))
1738: return 1;
1739: }
1740: return 0;
1741: }
1742:
1743: /* Return nonzero if reg REGNO is marked as dying in INSN. */
1744:
1745: int
1746: regno_dead_p (regno, insn)
1747: int regno;
1748: rtx insn;
1749: {
1750: register rtx link;
1751:
1752: for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1.1.1.2 root 1753: if ((REG_NOTE_KIND (link) == REG_DEAD
1754: || REG_NOTE_KIND (link) == REG_INC)
1755: && REGNO (XEXP (link, 0)) == regno)
1.1 root 1756: return 1;
1757:
1758: return 0;
1759: }
1760:
1761: /* Remove register number REGNO from the dead registers list of INSN. */
1762:
1.1.1.4 root 1763: void
1.1 root 1764: remove_death (regno, insn)
1765: int regno;
1766: rtx insn;
1767: {
1768: register rtx link, next;
1769: while ((link = REG_NOTES (insn))
1.1.1.2 root 1770: && REG_NOTE_KIND (link) == REG_DEAD
1771: && REGNO (XEXP (link, 0)) == regno)
1.1 root 1772: REG_NOTES (insn) = XEXP (link, 1);
1773:
1774: if (link)
1775: while (next = XEXP (link, 1))
1776: {
1.1.1.2 root 1777: if (REG_NOTE_KIND (next) == REG_DEAD
1778: && REGNO (XEXP (next, 0)) == regno)
1.1 root 1779: XEXP (link, 1) = XEXP (next, 1);
1780: else
1781: link = next;
1782: }
1783: }
1784:
1785: /* Return nonzero if J is the first insn following I,
1786: not counting labels, line numbers, etc.
1787: We assume that J follows I. */
1788:
1789: static int
1790: adjacent_insns_p (i, j)
1791: rtx i, j;
1792: {
1793: register rtx insn;
1794: for (insn = NEXT_INSN (i); insn != j; insn = NEXT_INSN (insn))
1795: if (GET_CODE (insn) == INSN
1796: || GET_CODE (insn) == CALL_INSN
1797: || GET_CODE (insn) == JUMP_INSN)
1798: return 0;
1799: return 1;
1800: }
1801:
1.1.1.2 root 1802: /* Concatenate the list of logical links of OINSN
1.1 root 1803: into INSN's list of logical links.
1.1.1.2 root 1804: Modifies OINSN destructively.
1805:
1806: If ALL_LINKS is nonzero, move all the links that OINSN has.
1807: Otherwise, move only those that point to insns that set regs
1808: that die in the insn OINSN.
1809: Other links are clobbered so that they are no longer effective. */
1.1 root 1810:
1811: static void
1.1.1.2 root 1812: add_links (insn, oinsn, all_links)
1813: rtx insn, oinsn;
1814: int all_links;
1.1 root 1815: {
1.1.1.2 root 1816: register rtx links = LOG_LINKS (oinsn);
1817: if (! all_links)
1818: {
1819: rtx tail;
1820: for (tail = links; tail; tail = XEXP (tail, 1))
1821: {
1822: rtx target = XEXP (tail, 0);
1823: if (GET_CODE (target) != INSN
1824: || GET_CODE (PATTERN (target)) != SET
1825: || GET_CODE (SET_DEST (PATTERN (target))) != REG
1826: || ! dead_or_set_p (oinsn, SET_DEST (PATTERN (target))))
1827: /* OINSN is going to become a NOTE
1828: so a link pointing there will have no effect. */
1829: XEXP (tail, 0) = oinsn;
1830: }
1831: }
1.1 root 1832: if (LOG_LINKS (insn) == 0)
1833: LOG_LINKS (insn) = links;
1834: else
1835: {
1836: register rtx next, prev = LOG_LINKS (insn);
1837: while (next = XEXP (prev, 1))
1838: prev = next;
1839: XEXP (prev, 1) = links;
1840: }
1841: }
1842:
1843: /* Concatenate the any elements of the list of reg-notes INCS
1844: which are of type REG_INC
1845: into INSN's list of reg-notes. */
1846:
1847: static void
1848: add_incs (insn, incs)
1849: rtx insn, incs;
1850: {
1851: register rtx tail;
1852:
1853: for (tail = incs; tail; tail = XEXP (tail, 1))
1.1.1.2 root 1854: if (REG_NOTE_KIND (tail) == REG_INC)
1.1 root 1855: REG_NOTES (insn)
1856: = gen_rtx (EXPR_LIST, REG_INC, XEXP (tail, 0), REG_NOTES (insn));
1857: }
1858:
1859: /* For each register (hardware or pseudo) used within expression X,
1860: if its death is in an instruction with cuid
1861: between FROM_CUID (inclusive) and TO_INSN (exclusive),
1862: mark it as dead in TO_INSN instead.
1863:
1864: This is done when X is being merged by combination into TO_INSN. */
1865:
1866: static void
1867: move_deaths (x, from_cuid, to_insn)
1868: rtx x;
1869: int from_cuid;
1870: rtx to_insn;
1871: {
1872: register char *fmt;
1873: register int len, i;
1874: register enum rtx_code code = GET_CODE (x);
1875:
1876: if (code == REG)
1877: {
1878: register rtx where_dead = reg_last_death[REGNO (x)];
1879:
1880: if (where_dead && INSN_CUID (where_dead) >= from_cuid
1881: && INSN_CUID (where_dead) < INSN_CUID (to_insn))
1882: {
1883: remove_death (REGNO (x), reg_last_death[REGNO (x)]);
1884: if (! dead_or_set_p (to_insn, x))
1885: REG_NOTES (to_insn)
1886: = gen_rtx (EXPR_LIST, REG_DEAD, x, REG_NOTES (to_insn));
1887: }
1888: return;
1889: }
1890:
1891: len = GET_RTX_LENGTH (code);
1892: fmt = GET_RTX_FORMAT (code);
1893:
1894: for (i = 0; i < len; i++)
1895: {
1896: if (fmt[i] == 'E')
1897: {
1898: register int j;
1899: for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1900: move_deaths (XVECEXP (x, i, j), from_cuid, to_insn);
1901: }
1902: else if (fmt[i] == 'e')
1903: move_deaths (XEXP (x, i), from_cuid, to_insn);
1904: }
1905: }
1906:
1.1.1.2 root 1907: void
1.1 root 1908: dump_combine_stats (file)
1909: char *file;
1910: {
1911: fprintf
1912: (file,
1913: ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n"
1914: , combine_attempts, combine_merges, combine_extras, combine_successes);
1915: }
1916:
1.1.1.2 root 1917: void
1.1 root 1918: dump_combine_total_stats (file)
1919: char *file;
1920: {
1921: fprintf
1922: (file,
1923: "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
1924: total_attempts, total_merges, total_extras, total_successes);
1925: }
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.