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1.1 root 1: /* Optimize by combining instructions for GNU compiler. 1.1.1.7 ! root 2: Copyright (C) 1987, 1988, 1992, 1993, 1994 Free Software Foundation, Inc. 1.1 root 3: 4: This file is part of GNU CC. 5: 6: GNU CC is free software; you can redistribute it and/or modify 7: it under the terms of the GNU General Public License as published by 8: the Free Software Foundation; either version 2, or (at your option) 9: any later version. 10: 11: GNU CC is distributed in the hope that it will be useful, 12: but WITHOUT ANY WARRANTY; without even the implied warranty of 13: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14: GNU General Public License for more details. 15: 16: You should have received a copy of the GNU General Public License 17: along with GNU CC; see the file COPYING. If not, write to 18: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ 19: 20: 21: /* This module is essentially the "combiner" phase of the U. of Arizona 22: Portable Optimizer, but redone to work on our list-structured 23: representation for RTL instead of their string representation. 24: 25: The LOG_LINKS of each insn identify the most recent assignment 26: to each REG used in the insn. It is a list of previous insns, 27: each of which contains a SET for a REG that is used in this insn 28: and not used or set in between. LOG_LINKs never cross basic blocks. 29: They were set up by the preceding pass (lifetime analysis). 30: 31: We try to combine each pair of insns joined by a logical link. 32: We also try to combine triples of insns A, B and C when 33: C has a link back to B and B has a link back to A. 34: 35: LOG_LINKS does not have links for use of the CC0. They don't 36: need to, because the insn that sets the CC0 is always immediately 37: before the insn that tests it. So we always regard a branch 38: insn as having a logical link to the preceding insn. The same is true 39: for an insn explicitly using CC0. 40: 41: We check (with use_crosses_set_p) to avoid combining in such a way 42: as to move a computation to a place where its value would be different. 43: 44: Combination is done by mathematically substituting the previous 45: insn(s) values for the regs they set into the expressions in 46: the later insns that refer to these regs. If the result is a valid insn 47: for our target machine, according to the machine description, 48: we install it, delete the earlier insns, and update the data flow 49: information (LOG_LINKS and REG_NOTES) for what we did. 50: 51: There are a few exceptions where the dataflow information created by 52: flow.c aren't completely updated: 53: 54: - reg_live_length is not updated 55: - reg_n_refs is not adjusted in the rare case when a register is 56: no longer required in a computation 57: - there are extremely rare cases (see distribute_regnotes) when a 58: REG_DEAD note is lost 59: - a LOG_LINKS entry that refers to an insn with multiple SETs may be 60: removed because there is no way to know which register it was 61: linking 62: 63: To simplify substitution, we combine only when the earlier insn(s) 64: consist of only a single assignment. To simplify updating afterward, 65: we never combine when a subroutine call appears in the middle. 66: 67: Since we do not represent assignments to CC0 explicitly except when that 68: is all an insn does, there is no LOG_LINKS entry in an insn that uses 69: the condition code for the insn that set the condition code. 70: Fortunately, these two insns must be consecutive. 71: Therefore, every JUMP_INSN is taken to have an implicit logical link 72: to the preceding insn. This is not quite right, since non-jumps can 73: also use the condition code; but in practice such insns would not 74: combine anyway. */ 75: 76: #include "config.h" 1.1.1.7 ! root 77: #ifdef __STDC__ ! 78: #include <stdarg.h> ! 79: #else ! 80: #include <varargs.h> ! 81: #endif 1.1.1.6 root 82: 83: /* Must precede rtl.h for FFS. */ 84: #include <stdio.h> 85: 1.1 root 86: #include "rtl.h" 87: #include "flags.h" 88: #include "regs.h" 1.1.1.5 root 89: #include "hard-reg-set.h" 1.1 root 90: #include "expr.h" 91: #include "basic-block.h" 92: #include "insn-config.h" 93: #include "insn-flags.h" 94: #include "insn-codes.h" 95: #include "insn-attr.h" 96: #include "recog.h" 97: #include "real.h" 98: 99: /* It is not safe to use ordinary gen_lowpart in combine. 100: Use gen_lowpart_for_combine instead. See comments there. */ 101: #define gen_lowpart dont_use_gen_lowpart_you_dummy 102: 103: /* Number of attempts to combine instructions in this function. */ 104: 105: static int combine_attempts; 106: 107: /* Number of attempts that got as far as substitution in this function. */ 108: 109: static int combine_merges; 110: 111: /* Number of instructions combined with added SETs in this function. */ 112: 113: static int combine_extras; 114: 115: /* Number of instructions combined in this function. */ 116: 117: static int combine_successes; 118: 119: /* Totals over entire compilation. */ 120: 121: static int total_attempts, total_merges, total_extras, total_successes; 1.1.1.7 ! root 122: ! 123: /* Define a defulat value for REVERSIBLE_CC_MODE. ! 124: We can never assume that a condition code mode is safe to reverse unless ! 125: the md tells us so. */ ! 126: #ifndef REVERSIBLE_CC_MODE ! 127: #define REVERSIBLE_CC_MODE(MODE) 0 ! 128: #endif 1.1 root 129: 130: /* Vector mapping INSN_UIDs to cuids. 1.1.1.2 root 131: The cuids are like uids but increase monotonically always. 1.1 root 132: Combine always uses cuids so that it can compare them. 133: But actually renumbering the uids, which we used to do, 134: proves to be a bad idea because it makes it hard to compare 135: the dumps produced by earlier passes with those from later passes. */ 136: 137: static int *uid_cuid; 138: 139: /* Get the cuid of an insn. */ 140: 141: #define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)]) 142: 143: /* Maximum register number, which is the size of the tables below. */ 144: 145: static int combine_max_regno; 146: 147: /* Record last point of death of (hard or pseudo) register n. */ 148: 149: static rtx *reg_last_death; 150: 151: /* Record last point of modification of (hard or pseudo) register n. */ 152: 153: static rtx *reg_last_set; 154: 155: /* Record the cuid of the last insn that invalidated memory 156: (anything that writes memory, and subroutine calls, but not pushes). */ 157: 158: static int mem_last_set; 159: 160: /* Record the cuid of the last CALL_INSN 161: so we can tell whether a potential combination crosses any calls. */ 162: 163: static int last_call_cuid; 164: 165: /* When `subst' is called, this is the insn that is being modified 166: (by combining in a previous insn). The PATTERN of this insn 167: is still the old pattern partially modified and it should not be 168: looked at, but this may be used to examine the successors of the insn 169: to judge whether a simplification is valid. */ 170: 171: static rtx subst_insn; 172: 173: /* This is the lowest CUID that `subst' is currently dealing with. 174: get_last_value will not return a value if the register was set at or 175: after this CUID. If not for this mechanism, we could get confused if 176: I2 or I1 in try_combine were an insn that used the old value of a register 177: to obtain a new value. In that case, we might erroneously get the 178: new value of the register when we wanted the old one. */ 179: 180: static int subst_low_cuid; 181: 1.1.1.7 ! root 182: /* This contains any hard registers that are used in newpat; reg_dead_at_p ! 183: must consider all these registers to be always live. */ ! 184: ! 185: static HARD_REG_SET newpat_used_regs; ! 186: ! 187: /* This is an insn to which a LOG_LINKS entry has been added. If this ! 188: insn is the earlier than I2 or I3, combine should rescan starting at ! 189: that location. */ ! 190: ! 191: static rtx added_links_insn; ! 192: 1.1 root 193: /* This is the value of undobuf.num_undo when we started processing this 194: substitution. This will prevent gen_rtx_combine from re-used a piece 195: from the previous expression. Doing so can produce circular rtl 196: structures. */ 197: 198: static int previous_num_undos; 1.1.1.6 root 199: 200: /* Basic block number of the block in which we are performing combines. */ 201: static int this_basic_block; 1.1 root 202: 203: /* The next group of arrays allows the recording of the last value assigned 204: to (hard or pseudo) register n. We use this information to see if a 1.1.1.2 root 205: operation being processed is redundant given a prior operation performed 1.1 root 206: on the register. For example, an `and' with a constant is redundant if 207: all the zero bits are already known to be turned off. 208: 209: We use an approach similar to that used by cse, but change it in the 210: following ways: 211: 212: (1) We do not want to reinitialize at each label. 213: (2) It is useful, but not critical, to know the actual value assigned 214: to a register. Often just its form is helpful. 215: 216: Therefore, we maintain the following arrays: 217: 218: reg_last_set_value the last value assigned 219: reg_last_set_label records the value of label_tick when the 220: register was assigned 221: reg_last_set_table_tick records the value of label_tick when a 222: value using the register is assigned 223: reg_last_set_invalid set to non-zero when it is not valid 224: to use the value of this register in some 225: register's value 226: 227: To understand the usage of these tables, it is important to understand 228: the distinction between the value in reg_last_set_value being valid 229: and the register being validly contained in some other expression in the 230: table. 231: 232: Entry I in reg_last_set_value is valid if it is non-zero, and either 233: reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick. 234: 235: Register I may validly appear in any expression returned for the value 236: of another register if reg_n_sets[i] is 1. It may also appear in the 237: value for register J if reg_last_set_label[i] < reg_last_set_label[j] or 238: reg_last_set_invalid[j] is zero. 239: 240: If an expression is found in the table containing a register which may 241: not validly appear in an expression, the register is replaced by 242: something that won't match, (clobber (const_int 0)). 243: 244: reg_last_set_invalid[i] is set non-zero when register I is being assigned 245: to and reg_last_set_table_tick[i] == label_tick. */ 246: 247: /* Record last value assigned to (hard or pseudo) register n. */ 248: 249: static rtx *reg_last_set_value; 250: 251: /* Record the value of label_tick when the value for register n is placed in 252: reg_last_set_value[n]. */ 253: 1.1.1.5 root 254: static int *reg_last_set_label; 1.1 root 255: 256: /* Record the value of label_tick when an expression involving register n 257: is placed in reg_last_set_value. */ 258: 1.1.1.5 root 259: static int *reg_last_set_table_tick; 1.1 root 260: 261: /* Set non-zero if references to register n in expressions should not be 262: used. */ 263: 264: static char *reg_last_set_invalid; 265: 266: /* Incremented for each label. */ 267: 1.1.1.5 root 268: static int label_tick; 1.1 root 269: 270: /* Some registers that are set more than once and used in more than one 271: basic block are nevertheless always set in similar ways. For example, 272: a QImode register may be loaded from memory in two places on a machine 273: where byte loads zero extend. 274: 1.1.1.5 root 275: We record in the following array what we know about the nonzero 1.1 root 276: bits of a register, specifically which bits are known to be zero. 277: 278: If an entry is zero, it means that we don't know anything special. */ 279: 1.1.1.5 root 280: static unsigned HOST_WIDE_INT *reg_nonzero_bits; 1.1 root 281: 1.1.1.5 root 282: /* Mode used to compute significance in reg_nonzero_bits. It is the largest 1.1.1.4 root 283: integer mode that can fit in HOST_BITS_PER_WIDE_INT. */ 1.1 root 284: 1.1.1.5 root 285: static enum machine_mode nonzero_bits_mode; 1.1 root 286: 1.1.1.4 root 287: /* Nonzero if we know that a register has some leading bits that are always 288: equal to the sign bit. */ 289: 290: static char *reg_sign_bit_copies; 291: 1.1.1.5 root 292: /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used. 1.1.1.4 root 293: It is zero while computing them and after combine has completed. This 294: former test prevents propagating values based on previously set values, 295: which can be incorrect if a variable is modified in a loop. */ 1.1 root 296: 1.1.1.5 root 297: static int nonzero_sign_valid; 298: 299: /* These arrays are maintained in parallel with reg_last_set_value 300: and are used to store the mode in which the register was last set, 301: the bits that were known to be zero when it was last set, and the 302: number of sign bits copies it was known to have when it was last set. */ 303: 304: static enum machine_mode *reg_last_set_mode; 305: static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits; 306: static char *reg_last_set_sign_bit_copies; 1.1 root 307: 308: /* Record one modification to rtl structure 309: to be undone by storing old_contents into *where. 310: is_int is 1 if the contents are an int. */ 311: 312: struct undo 313: { 314: int is_int; 1.1.1.6 root 315: union {rtx r; int i;} old_contents; 316: union {rtx *r; int *i;} where; 1.1 root 317: }; 318: 319: /* Record a bunch of changes to be undone, up to MAX_UNDO of them. 320: num_undo says how many are currently recorded. 321: 322: storage is nonzero if we must undo the allocation of new storage. 323: The value of storage is what to pass to obfree. 324: 325: other_insn is nonzero if we have modified some other insn in the process 326: of working on subst_insn. It must be verified too. */ 327: 328: #define MAX_UNDO 50 329: 330: struct undobuf 331: { 332: int num_undo; 333: char *storage; 334: struct undo undo[MAX_UNDO]; 335: rtx other_insn; 336: }; 337: 338: static struct undobuf undobuf; 339: 1.1.1.4 root 340: /* Substitute NEWVAL, an rtx expression, into INTO, a place in some 1.1 root 341: insn. The substitution can be undone by undo_all. If INTO is already 1.1.1.4 root 342: set to NEWVAL, do not record this change. Because computing NEWVAL might 343: also call SUBST, we have to compute it before we put anything into 344: the undo table. */ 1.1 root 345: 346: #define SUBST(INTO, NEWVAL) \ 1.1.1.4 root 347: do { rtx _new = (NEWVAL); \ 348: if (undobuf.num_undo < MAX_UNDO) \ 1.1 root 349: { \ 350: undobuf.undo[undobuf.num_undo].is_int = 0; \ 1.1.1.6 root 351: undobuf.undo[undobuf.num_undo].where.r = &INTO; \ 352: undobuf.undo[undobuf.num_undo].old_contents.r = INTO; \ 1.1.1.4 root 353: INTO = _new; \ 1.1.1.6 root 354: if (undobuf.undo[undobuf.num_undo].old_contents.r != INTO) \ 1.1 root 355: undobuf.num_undo++; \ 356: } \ 357: } while (0) 358: 359: /* Similar to SUBST, but NEWVAL is an int. INTO will normally be an XINT 360: expression. 361: Note that substitution for the value of a CONST_INT is not safe. */ 362: 363: #define SUBST_INT(INTO, NEWVAL) \ 364: do { if (undobuf.num_undo < MAX_UNDO) \ 365: { \ 1.1.1.4 root 366: undobuf.undo[undobuf.num_undo].is_int = 1; \ 367: undobuf.undo[undobuf.num_undo].where.i = (int *) &INTO; \ 368: undobuf.undo[undobuf.num_undo].old_contents.i = INTO; \ 1.1 root 369: INTO = NEWVAL; \ 1.1.1.4 root 370: if (undobuf.undo[undobuf.num_undo].old_contents.i != INTO) \ 1.1 root 371: undobuf.num_undo++; \ 372: } \ 373: } while (0) 374: 375: /* Number of times the pseudo being substituted for 376: was found and replaced. */ 377: 378: static int n_occurrences; 379: 1.1.1.6 root 380: static void init_reg_last_arrays PROTO(()); 381: static void setup_incoming_promotions PROTO(()); 382: static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx)); 383: static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *)); 384: static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *)); 385: static rtx try_combine PROTO((rtx, rtx, rtx)); 386: static void undo_all PROTO((void)); 387: static rtx *find_split_point PROTO((rtx *, rtx)); 388: static rtx subst PROTO((rtx, rtx, rtx, int, int)); 1.1.1.7 ! root 389: static rtx simplify_rtx PROTO((rtx, enum machine_mode, int, int)); ! 390: static rtx simplify_if_then_else PROTO((rtx)); ! 391: static rtx simplify_set PROTO((rtx)); ! 392: static rtx simplify_logical PROTO((rtx, int)); 1.1.1.6 root 393: static rtx expand_compound_operation PROTO((rtx)); 394: static rtx expand_field_assignment PROTO((rtx)); 395: static rtx make_extraction PROTO((enum machine_mode, rtx, int, rtx, int, 396: int, int, int)); 1.1.1.7 ! root 397: static rtx extract_left_shift PROTO((rtx, int)); 1.1.1.6 root 398: static rtx make_compound_operation PROTO((rtx, enum rtx_code)); 399: static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *)); 400: static rtx force_to_mode PROTO((rtx, enum machine_mode, 401: unsigned HOST_WIDE_INT, rtx, int)); 1.1.1.7 ! root 402: static rtx if_then_else_cond PROTO((rtx, rtx *, rtx *)); 1.1.1.6 root 403: static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx)); 404: static rtx make_field_assignment PROTO((rtx)); 405: static rtx apply_distributive_law PROTO((rtx)); 406: static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx, 407: unsigned HOST_WIDE_INT)); 408: static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode)); 409: static int num_sign_bit_copies PROTO((rtx, enum machine_mode)); 410: static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *, 411: enum rtx_code, HOST_WIDE_INT, 412: enum machine_mode, int *)); 413: static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode, 414: rtx, int)); 415: static int recog_for_combine PROTO((rtx *, rtx, rtx *)); 416: static rtx gen_lowpart_for_combine PROTO((enum machine_mode, rtx)); 1.1.1.7 ! root 417: static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode, ! 418: ...)); 1.1.1.6 root 419: static rtx gen_binary PROTO((enum rtx_code, enum machine_mode, 420: rtx, rtx)); 1.1.1.7 ! root 421: static rtx gen_unary PROTO((enum rtx_code, enum machine_mode, ! 422: enum machine_mode, rtx)); 1.1.1.6 root 423: static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *)); 424: static int reversible_comparison_p PROTO((rtx)); 425: static void update_table_tick PROTO((rtx)); 426: static void record_value_for_reg PROTO((rtx, rtx, rtx)); 427: static void record_dead_and_set_regs_1 PROTO((rtx, rtx)); 428: static void record_dead_and_set_regs PROTO((rtx)); 429: static int get_last_value_validate PROTO((rtx *, int, int)); 430: static rtx get_last_value PROTO((rtx)); 431: static int use_crosses_set_p PROTO((rtx, int)); 432: static void reg_dead_at_p_1 PROTO((rtx, rtx)); 433: static int reg_dead_at_p PROTO((rtx, rtx)); 434: static void move_deaths PROTO((rtx, int, rtx, rtx *)); 435: static int reg_bitfield_target_p PROTO((rtx, rtx)); 436: static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx)); 437: static void distribute_links PROTO((rtx)); 1.1.1.7 ! root 438: static void mark_used_regs_combine PROTO((rtx)); 1.1 root 439: 440: /* Main entry point for combiner. F is the first insn of the function. 441: NREGS is the first unused pseudo-reg number. */ 442: 443: void 444: combine_instructions (f, nregs) 445: rtx f; 446: int nregs; 447: { 448: register rtx insn, next, prev; 449: register int i; 450: register rtx links, nextlinks; 451: 452: combine_attempts = 0; 453: combine_merges = 0; 454: combine_extras = 0; 455: combine_successes = 0; 1.1.1.5 root 456: undobuf.num_undo = previous_num_undos = 0; 1.1 root 457: 458: combine_max_regno = nregs; 459: 1.1.1.6 root 460: reg_nonzero_bits 461: = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT)); 462: reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char)); 463: 1.1.1.7 ! root 464: bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT)); 1.1.1.6 root 465: bzero (reg_sign_bit_copies, nregs * sizeof (char)); 466: 1.1 root 467: reg_last_death = (rtx *) alloca (nregs * sizeof (rtx)); 468: reg_last_set = (rtx *) alloca (nregs * sizeof (rtx)); 469: reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx)); 1.1.1.5 root 470: reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int)); 471: reg_last_set_label = (int *) alloca (nregs * sizeof (int)); 1.1.1.4 root 472: reg_last_set_invalid = (char *) alloca (nregs * sizeof (char)); 1.1.1.5 root 473: reg_last_set_mode 474: = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode)); 475: reg_last_set_nonzero_bits 476: = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT)); 477: reg_last_set_sign_bit_copies 478: = (char *) alloca (nregs * sizeof (char)); 479: 1.1.1.6 root 480: init_reg_last_arrays (); 1.1 root 481: 482: init_recog_no_volatile (); 483: 484: /* Compute maximum uid value so uid_cuid can be allocated. */ 485: 486: for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) 487: if (INSN_UID (insn) > i) 488: i = INSN_UID (insn); 489: 490: uid_cuid = (int *) alloca ((i + 1) * sizeof (int)); 491: 1.1.1.5 root 492: nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0); 1.1 root 493: 1.1.1.5 root 494: /* Don't use reg_nonzero_bits when computing it. This can cause problems 1.1 root 495: when, for example, we have j <<= 1 in a loop. */ 496: 1.1.1.5 root 497: nonzero_sign_valid = 0; 1.1 root 498: 499: /* Compute the mapping from uids to cuids. 500: Cuids are numbers assigned to insns, like uids, 501: except that cuids increase monotonically through the code. 502: 503: Scan all SETs and see if we can deduce anything about what 1.1.1.5 root 504: bits are known to be zero for some registers and how many copies 505: of the sign bit are known to exist for those registers. 506: 507: Also set any known values so that we can use it while searching 508: for what bits are known to be set. */ 509: 510: label_tick = 1; 511: 512: setup_incoming_promotions (); 1.1 root 513: 514: for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) 515: { 516: INSN_CUID (insn) = ++i; 1.1.1.5 root 517: subst_low_cuid = i; 518: subst_insn = insn; 519: 1.1 root 520: if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') 1.1.1.5 root 521: { 522: note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies); 523: record_dead_and_set_regs (insn); 524: } 525: 526: if (GET_CODE (insn) == CODE_LABEL) 527: label_tick++; 1.1 root 528: } 529: 1.1.1.5 root 530: nonzero_sign_valid = 1; 1.1 root 531: 532: /* Now scan all the insns in forward order. */ 533: 1.1.1.6 root 534: this_basic_block = -1; 1.1 root 535: label_tick = 1; 536: last_call_cuid = 0; 537: mem_last_set = 0; 1.1.1.6 root 538: init_reg_last_arrays (); 1.1.1.5 root 539: setup_incoming_promotions (); 1.1 root 540: 541: for (insn = f; insn; insn = next ? next : NEXT_INSN (insn)) 542: { 543: next = 0; 544: 1.1.1.6 root 545: /* If INSN starts a new basic block, update our basic block number. */ 546: if (this_basic_block + 1 < n_basic_blocks 547: && basic_block_head[this_basic_block + 1] == insn) 548: this_basic_block++; 549: 1.1 root 550: if (GET_CODE (insn) == CODE_LABEL) 551: label_tick++; 552: 1.1.1.6 root 553: else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') 1.1 root 554: { 555: /* Try this insn with each insn it links back to. */ 556: 557: for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 1.1.1.4 root 558: if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0) 1.1 root 559: goto retry; 560: 561: /* Try each sequence of three linked insns ending with this one. */ 562: 563: for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 564: for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks; 565: nextlinks = XEXP (nextlinks, 1)) 566: if ((next = try_combine (insn, XEXP (links, 0), 567: XEXP (nextlinks, 0))) != 0) 568: goto retry; 569: 570: #ifdef HAVE_cc0 571: /* Try to combine a jump insn that uses CC0 572: with a preceding insn that sets CC0, and maybe with its 573: logical predecessor as well. 574: This is how we make decrement-and-branch insns. 575: We need this special code because data flow connections 576: via CC0 do not get entered in LOG_LINKS. */ 577: 578: if (GET_CODE (insn) == JUMP_INSN 579: && (prev = prev_nonnote_insn (insn)) != 0 580: && GET_CODE (prev) == INSN 581: && sets_cc0_p (PATTERN (prev))) 582: { 1.1.1.4 root 583: if ((next = try_combine (insn, prev, NULL_RTX)) != 0) 1.1 root 584: goto retry; 585: 586: for (nextlinks = LOG_LINKS (prev); nextlinks; 587: nextlinks = XEXP (nextlinks, 1)) 588: if ((next = try_combine (insn, prev, 589: XEXP (nextlinks, 0))) != 0) 590: goto retry; 591: } 592: 593: /* Do the same for an insn that explicitly references CC0. */ 594: if (GET_CODE (insn) == INSN 595: && (prev = prev_nonnote_insn (insn)) != 0 596: && GET_CODE (prev) == INSN 597: && sets_cc0_p (PATTERN (prev)) 598: && GET_CODE (PATTERN (insn)) == SET 599: && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn)))) 600: { 1.1.1.4 root 601: if ((next = try_combine (insn, prev, NULL_RTX)) != 0) 1.1 root 602: goto retry; 603: 604: for (nextlinks = LOG_LINKS (prev); nextlinks; 605: nextlinks = XEXP (nextlinks, 1)) 606: if ((next = try_combine (insn, prev, 607: XEXP (nextlinks, 0))) != 0) 608: goto retry; 609: } 610: 611: /* Finally, see if any of the insns that this insn links to 612: explicitly references CC0. If so, try this insn, that insn, 1.1.1.2 root 613: and its predecessor if it sets CC0. */ 1.1 root 614: for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 615: if (GET_CODE (XEXP (links, 0)) == INSN 616: && GET_CODE (PATTERN (XEXP (links, 0))) == SET 617: && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0)))) 618: && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0 619: && GET_CODE (prev) == INSN 620: && sets_cc0_p (PATTERN (prev)) 621: && (next = try_combine (insn, XEXP (links, 0), prev)) != 0) 622: goto retry; 623: #endif 624: 625: /* Try combining an insn with two different insns whose results it 626: uses. */ 627: for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) 628: for (nextlinks = XEXP (links, 1); nextlinks; 629: nextlinks = XEXP (nextlinks, 1)) 630: if ((next = try_combine (insn, XEXP (links, 0), 631: XEXP (nextlinks, 0))) != 0) 632: goto retry; 633: 634: if (GET_CODE (insn) != NOTE) 635: record_dead_and_set_regs (insn); 636: 637: retry: 638: ; 639: } 640: } 641: 642: total_attempts += combine_attempts; 643: total_merges += combine_merges; 644: total_extras += combine_extras; 645: total_successes += combine_successes; 1.1.1.4 root 646: 1.1.1.5 root 647: nonzero_sign_valid = 0; 648: } 1.1.1.6 root 649: 650: /* Wipe the reg_last_xxx arrays in preparation for another pass. */ 651: 652: static void 653: init_reg_last_arrays () 654: { 655: int nregs = combine_max_regno; 656: 1.1.1.7 ! root 657: bzero ((char *) reg_last_death, nregs * sizeof (rtx)); ! 658: bzero ((char *) reg_last_set, nregs * sizeof (rtx)); ! 659: bzero ((char *) reg_last_set_value, nregs * sizeof (rtx)); ! 660: bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int)); ! 661: bzero ((char *) reg_last_set_label, nregs * sizeof (int)); 1.1.1.6 root 662: bzero (reg_last_set_invalid, nregs * sizeof (char)); 1.1.1.7 ! root 663: bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode)); ! 664: bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT)); 1.1.1.6 root 665: bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char)); 666: } 1.1.1.5 root 667: 668: /* Set up any promoted values for incoming argument registers. */ 669: 670: static void 671: setup_incoming_promotions () 672: { 673: #ifdef PROMOTE_FUNCTION_ARGS 674: int regno; 675: rtx reg; 676: enum machine_mode mode; 677: int unsignedp; 678: rtx first = get_insns (); 679: 680: for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 681: if (FUNCTION_ARG_REGNO_P (regno) 682: && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0) 683: record_value_for_reg (reg, first, 684: gen_rtx (unsignedp ? ZERO_EXTEND : SIGN_EXTEND, 685: GET_MODE (reg), 686: gen_rtx (CLOBBER, mode, const0_rtx))); 687: #endif 1.1 root 688: } 689: 690: /* Called via note_stores. If X is a pseudo that is used in more than 1.1.1.4 root 691: one basic block, is narrower that HOST_BITS_PER_WIDE_INT, and is being 1.1.1.5 root 692: set, record what bits are known zero. If we are clobbering X, 1.1 root 693: ignore this "set" because the clobbered value won't be used. 694: 695: If we are setting only a portion of X and we can't figure out what 696: portion, assume all bits will be used since we don't know what will 1.1.1.4 root 697: be happening. 698: 699: Similarly, set how many bits of X are known to be copies of the sign bit 700: at all locations in the function. This is the smallest number implied 701: by any set of X. */ 1.1 root 702: 703: static void 1.1.1.5 root 704: set_nonzero_bits_and_sign_copies (x, set) 1.1 root 705: rtx x; 706: rtx set; 707: { 1.1.1.4 root 708: int num; 709: 1.1 root 710: if (GET_CODE (x) == REG 711: && REGNO (x) >= FIRST_PSEUDO_REGISTER 712: && reg_n_sets[REGNO (x)] > 1 713: && reg_basic_block[REGNO (x)] < 0 1.1.1.5 root 714: /* If this register is undefined at the start of the file, we can't 715: say what its contents were. */ 716: && ! (basic_block_live_at_start[0][REGNO (x) / REGSET_ELT_BITS] 717: & ((REGSET_ELT_TYPE) 1 << (REGNO (x) % REGSET_ELT_BITS))) 1.1.1.4 root 718: && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT) 1.1 root 719: { 720: if (GET_CODE (set) == CLOBBER) 1.1.1.5 root 721: { 722: reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x)); 723: reg_sign_bit_copies[REGNO (x)] = 0; 724: return; 725: } 1.1 root 726: 727: /* If this is a complex assignment, see if we can convert it into a 1.1.1.2 root 728: simple assignment. */ 1.1 root 729: set = expand_field_assignment (set); 1.1.1.5 root 730: 731: /* If this is a simple assignment, or we have a paradoxical SUBREG, 732: set what we know about X. */ 733: 734: if (SET_DEST (set) == x 735: || (GET_CODE (SET_DEST (set)) == SUBREG 736: && (GET_MODE_SIZE (GET_MODE (SET_DEST (set))) 737: > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set))))) 738: && SUBREG_REG (SET_DEST (set)) == x)) 739: { 740: rtx src = SET_SRC (set); 741: 742: #ifdef SHORT_IMMEDIATES_SIGN_EXTEND 743: /* If X is narrower than a word and SRC is a non-negative 744: constant that would appear negative in the mode of X, 745: sign-extend it for use in reg_nonzero_bits because some 746: machines (maybe most) will actually do the sign-extension 747: and this is the conservative approach. 748: 749: ??? For 2.5, try to tighten up the MD files in this regard 750: instead of this kludge. */ 751: 752: if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD 753: && GET_CODE (src) == CONST_INT 754: && INTVAL (src) > 0 755: && 0 != (INTVAL (src) 756: & ((HOST_WIDE_INT) 1 1.1.1.7 ! root 757: << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) 1.1.1.5 root 758: src = GEN_INT (INTVAL (src) 759: | ((HOST_WIDE_INT) (-1) 760: << GET_MODE_BITSIZE (GET_MODE (x)))); 761: #endif 762: 763: reg_nonzero_bits[REGNO (x)] 764: |= nonzero_bits (src, nonzero_bits_mode); 1.1.1.4 root 765: num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x)); 766: if (reg_sign_bit_copies[REGNO (x)] == 0 767: || reg_sign_bit_copies[REGNO (x)] > num) 768: reg_sign_bit_copies[REGNO (x)] = num; 769: } 1.1 root 770: else 1.1.1.4 root 771: { 1.1.1.5 root 772: reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x)); 1.1.1.4 root 773: reg_sign_bit_copies[REGNO (x)] = 0; 774: } 1.1 root 775: } 776: } 777: 778: /* See if INSN can be combined into I3. PRED and SUCC are optionally 779: insns that were previously combined into I3 or that will be combined 780: into the merger of INSN and I3. 781: 782: Return 0 if the combination is not allowed for any reason. 783: 784: If the combination is allowed, *PDEST will be set to the single 785: destination of INSN and *PSRC to the single source, and this function 786: will return 1. */ 787: 788: static int 789: can_combine_p (insn, i3, pred, succ, pdest, psrc) 790: rtx insn; 791: rtx i3; 792: rtx pred, succ; 793: rtx *pdest, *psrc; 794: { 795: int i; 796: rtx set = 0, src, dest; 797: rtx p, link; 798: int all_adjacent = (succ ? (next_active_insn (insn) == succ 799: && next_active_insn (succ) == i3) 800: : next_active_insn (insn) == i3); 801: 802: /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0. 803: or a PARALLEL consisting of such a SET and CLOBBERs. 804: 805: If INSN has CLOBBER parallel parts, ignore them for our processing. 806: By definition, these happen during the execution of the insn. When it 807: is merged with another insn, all bets are off. If they are, in fact, 808: needed and aren't also supplied in I3, they may be added by 809: recog_for_combine. Otherwise, it won't match. 810: 811: We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED 812: note. 813: 814: Get the source and destination of INSN. If more than one, can't 815: combine. */ 816: 817: if (GET_CODE (PATTERN (insn)) == SET) 818: set = PATTERN (insn); 819: else if (GET_CODE (PATTERN (insn)) == PARALLEL 820: && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) 821: { 822: for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) 823: { 824: rtx elt = XVECEXP (PATTERN (insn), 0, i); 825: 826: switch (GET_CODE (elt)) 827: { 828: /* We can ignore CLOBBERs. */ 829: case CLOBBER: 830: break; 831: 832: case SET: 833: /* Ignore SETs whose result isn't used but not those that 834: have side-effects. */ 835: if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt)) 836: && ! side_effects_p (elt)) 837: break; 838: 839: /* If we have already found a SET, this is a second one and 840: so we cannot combine with this insn. */ 841: if (set) 842: return 0; 843: 844: set = elt; 845: break; 846: 847: default: 848: /* Anything else means we can't combine. */ 849: return 0; 850: } 851: } 852: 853: if (set == 0 854: /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs, 855: so don't do anything with it. */ 856: || GET_CODE (SET_SRC (set)) == ASM_OPERANDS) 857: return 0; 858: } 859: else 860: return 0; 861: 862: if (set == 0) 863: return 0; 864: 865: set = expand_field_assignment (set); 866: src = SET_SRC (set), dest = SET_DEST (set); 867: 868: /* Don't eliminate a store in the stack pointer. */ 869: if (dest == stack_pointer_rtx 870: /* If we couldn't eliminate a field assignment, we can't combine. */ 871: || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART 872: /* Don't combine with an insn that sets a register to itself if it has 873: a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */ 1.1.1.4 root 874: || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX)) 1.1 root 875: /* Can't merge a function call. */ 876: || GET_CODE (src) == CALL 1.1.1.7 ! root 877: /* Don't eliminate a function call argument. */ ! 878: || (GET_CODE (i3) == CALL_INSN ! 879: && (find_reg_fusage (i3, USE, dest) ! 880: || (GET_CODE (dest) == REG ! 881: && REGNO (dest) < FIRST_PSEUDO_REGISTER ! 882: && global_regs[REGNO (dest)]))) 1.1 root 883: /* Don't substitute into an incremented register. */ 884: || FIND_REG_INC_NOTE (i3, dest) 885: || (succ && FIND_REG_INC_NOTE (succ, dest)) 886: /* Don't combine the end of a libcall into anything. */ 1.1.1.4 root 887: || find_reg_note (insn, REG_RETVAL, NULL_RTX) 1.1 root 888: /* Make sure that DEST is not used after SUCC but before I3. */ 889: || (succ && ! all_adjacent 890: && reg_used_between_p (dest, succ, i3)) 891: /* Make sure that the value that is to be substituted for the register 892: does not use any registers whose values alter in between. However, 893: If the insns are adjacent, a use can't cross a set even though we 894: think it might (this can happen for a sequence of insns each setting 895: the same destination; reg_last_set of that register might point to 1.1.1.6 root 896: a NOTE). If INSN has a REG_EQUIV note, the register is always 897: equivalent to the memory so the substitution is valid even if there 898: are intervening stores. Also, don't move a volatile asm or 899: UNSPEC_VOLATILE across any other insns. */ 1.1 root 900: || (! all_adjacent 1.1.1.6 root 901: && (((GET_CODE (src) != MEM 902: || ! find_reg_note (insn, REG_EQUIV, src)) 903: && use_crosses_set_p (src, INSN_CUID (insn))) 1.1.1.5 root 904: || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src)) 905: || GET_CODE (src) == UNSPEC_VOLATILE)) 1.1 root 906: /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get 907: better register allocation by not doing the combine. */ 908: || find_reg_note (i3, REG_NO_CONFLICT, dest) 909: || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest)) 910: /* Don't combine across a CALL_INSN, because that would possibly 911: change whether the life span of some REGs crosses calls or not, 912: and it is a pain to update that information. 913: Exception: if source is a constant, moving it later can't hurt. 914: Accept that special case, because it helps -fforce-addr a lot. */ 915: || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src))) 916: return 0; 917: 918: /* DEST must either be a REG or CC0. */ 919: if (GET_CODE (dest) == REG) 920: { 921: /* If register alignment is being enforced for multi-word items in all 922: cases except for parameters, it is possible to have a register copy 923: insn referencing a hard register that is not allowed to contain the 924: mode being copied and which would not be valid as an operand of most 925: insns. Eliminate this problem by not combining with such an insn. 926: 927: Also, on some machines we don't want to extend the life of a hard 928: register. */ 929: 930: if (GET_CODE (src) == REG 931: && ((REGNO (dest) < FIRST_PSEUDO_REGISTER 932: && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest))) 1.1.1.7 ! root 933: /* Don't extend the life of a hard register unless it is ! 934: user variable (if we have few registers) or it can't ! 935: fit into the desired register (meaning something special ! 936: is going on). */ 1.1 root 937: || (REGNO (src) < FIRST_PSEUDO_REGISTER 1.1.1.7 ! root 938: && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)) ! 939: #ifdef SMALL_REGISTER_CLASSES ! 940: || ! REG_USERVAR_P (src) 1.1 root 941: #endif 1.1.1.7 ! root 942: )))) 1.1 root 943: return 0; 944: } 945: else if (GET_CODE (dest) != CC0) 946: return 0; 947: 1.1.1.4 root 948: /* Don't substitute for a register intended as a clobberable operand. 949: Similarly, don't substitute an expression containing a register that 950: will be clobbered in I3. */ 1.1 root 951: if (GET_CODE (PATTERN (i3)) == PARALLEL) 952: for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--) 953: if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER 1.1.1.4 root 954: && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), 955: src) 956: || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest))) 1.1 root 957: return 0; 958: 959: /* If INSN contains anything volatile, or is an `asm' (whether volatile 960: or not), reject, unless nothing volatile comes between it and I3, 961: with the exception of SUCC. */ 962: 963: if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src)) 964: for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) 965: if (GET_RTX_CLASS (GET_CODE (p)) == 'i' 966: && p != succ && volatile_refs_p (PATTERN (p))) 967: return 0; 968: 1.1.1.6 root 969: /* If there are any volatile insns between INSN and I3, reject, because 970: they might affect machine state. */ 971: 972: for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) 973: if (GET_RTX_CLASS (GET_CODE (p)) == 'i' 974: && p != succ && volatile_insn_p (PATTERN (p))) 975: return 0; 976: 1.1 root 977: /* If INSN or I2 contains an autoincrement or autodecrement, 978: make sure that register is not used between there and I3, 979: and not already used in I3 either. 980: Also insist that I3 not be a jump; if it were one 981: and the incremented register were spilled, we would lose. */ 982: 983: #ifdef AUTO_INC_DEC 984: for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 985: if (REG_NOTE_KIND (link) == REG_INC 986: && (GET_CODE (i3) == JUMP_INSN 987: || reg_used_between_p (XEXP (link, 0), insn, i3) 988: || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3)))) 989: return 0; 990: #endif 991: 992: #ifdef HAVE_cc0 993: /* Don't combine an insn that follows a CC0-setting insn. 994: An insn that uses CC0 must not be separated from the one that sets it. 995: We do, however, allow I2 to follow a CC0-setting insn if that insn 996: is passed as I1; in that case it will be deleted also. 997: We also allow combining in this case if all the insns are adjacent 998: because that would leave the two CC0 insns adjacent as well. 999: It would be more logical to test whether CC0 occurs inside I1 or I2, 1000: but that would be much slower, and this ought to be equivalent. */ 1001: 1002: p = prev_nonnote_insn (insn); 1003: if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p)) 1004: && ! all_adjacent) 1005: return 0; 1006: #endif 1007: 1008: /* If we get here, we have passed all the tests and the combination is 1009: to be allowed. */ 1010: 1011: *pdest = dest; 1012: *psrc = src; 1013: 1014: return 1; 1015: } 1016: 1017: /* LOC is the location within I3 that contains its pattern or the component 1018: of a PARALLEL of the pattern. We validate that it is valid for combining. 1019: 1020: One problem is if I3 modifies its output, as opposed to replacing it 1021: entirely, we can't allow the output to contain I2DEST or I1DEST as doing 1022: so would produce an insn that is not equivalent to the original insns. 1023: 1024: Consider: 1025: 1026: (set (reg:DI 101) (reg:DI 100)) 1027: (set (subreg:SI (reg:DI 101) 0) <foo>) 1028: 1029: This is NOT equivalent to: 1030: 1031: (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>) 1032: (set (reg:DI 101) (reg:DI 100))]) 1033: 1034: Not only does this modify 100 (in which case it might still be valid 1035: if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100. 1036: 1037: We can also run into a problem if I2 sets a register that I1 1038: uses and I1 gets directly substituted into I3 (not via I2). In that 1039: case, we would be getting the wrong value of I2DEST into I3, so we 1040: must reject the combination. This case occurs when I2 and I1 both 1041: feed into I3, rather than when I1 feeds into I2, which feeds into I3. 1042: If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source 1043: of a SET must prevent combination from occurring. 1044: 1045: On machines where SMALL_REGISTER_CLASSES is defined, we don't combine 1.1.1.7 ! root 1046: if the destination of a SET is a hard register that isn't a user ! 1047: variable. 1.1 root 1048: 1049: Before doing the above check, we first try to expand a field assignment 1050: into a set of logical operations. 1051: 1052: If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which 1053: we place a register that is both set and used within I3. If more than one 1054: such register is detected, we fail. 1055: 1056: Return 1 if the combination is valid, zero otherwise. */ 1057: 1058: static int 1059: combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed) 1060: rtx i3; 1061: rtx *loc; 1062: rtx i2dest; 1063: rtx i1dest; 1064: int i1_not_in_src; 1065: rtx *pi3dest_killed; 1066: { 1067: rtx x = *loc; 1068: 1069: if (GET_CODE (x) == SET) 1070: { 1071: rtx set = expand_field_assignment (x); 1072: rtx dest = SET_DEST (set); 1073: rtx src = SET_SRC (set); 1074: rtx inner_dest = dest, inner_src = src; 1075: 1076: SUBST (*loc, set); 1077: 1078: while (GET_CODE (inner_dest) == STRICT_LOW_PART 1079: || GET_CODE (inner_dest) == SUBREG 1080: || GET_CODE (inner_dest) == ZERO_EXTRACT) 1081: inner_dest = XEXP (inner_dest, 0); 1082: 1083: /* We probably don't need this any more now that LIMIT_RELOAD_CLASS 1084: was added. */ 1085: #if 0 1086: while (GET_CODE (inner_src) == STRICT_LOW_PART 1087: || GET_CODE (inner_src) == SUBREG 1088: || GET_CODE (inner_src) == ZERO_EXTRACT) 1089: inner_src = XEXP (inner_src, 0); 1090: 1091: /* If it is better that two different modes keep two different pseudos, 1092: avoid combining them. This avoids producing the following pattern 1093: on a 386: 1094: (set (subreg:SI (reg/v:QI 21) 0) 1095: (lshiftrt:SI (reg/v:SI 20) 1096: (const_int 24))) 1097: If that were made, reload could not handle the pair of 1098: reg 20/21, since it would try to get any GENERAL_REGS 1099: but some of them don't handle QImode. */ 1100: 1101: if (rtx_equal_p (inner_src, i2dest) 1102: && GET_CODE (inner_dest) == REG 1103: && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest))) 1104: return 0; 1105: #endif 1106: 1107: /* Check for the case where I3 modifies its output, as 1108: discussed above. */ 1109: if ((inner_dest != dest 1110: && (reg_overlap_mentioned_p (i2dest, inner_dest) 1111: || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest)))) 1.1.1.3 root 1112: /* This is the same test done in can_combine_p except that we 1113: allow a hard register with SMALL_REGISTER_CLASSES if SRC is a 1114: CALL operation. */ 1.1 root 1115: || (GET_CODE (inner_dest) == REG 1.1.1.2 root 1116: && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER 1.1.1.7 ! root 1117: && (! HARD_REGNO_MODE_OK (REGNO (inner_dest), ! 1118: GET_MODE (inner_dest)) 1.1.1.3 root 1119: #ifdef SMALL_REGISTER_CLASSES 1.1.1.7 ! root 1120: || (GET_CODE (src) != CALL && ! REG_USERVAR_P (inner_dest)) 1.1 root 1121: #endif 1.1.1.7 ! root 1122: )) 1.1 root 1123: || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))) 1124: return 0; 1125: 1126: /* If DEST is used in I3, it is being killed in this insn, 1.1.1.5 root 1127: so record that for later. 1128: Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the 1129: STACK_POINTER_REGNUM, since these are always considered to be 1130: live. Similarly for ARG_POINTER_REGNUM if it is fixed. */ 1.1 root 1131: if (pi3dest_killed && GET_CODE (dest) == REG 1.1.1.5 root 1132: && reg_referenced_p (dest, PATTERN (i3)) 1133: && REGNO (dest) != FRAME_POINTER_REGNUM 1.1.1.6 root 1134: #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 1135: && REGNO (dest) != HARD_FRAME_POINTER_REGNUM 1136: #endif 1.1.1.5 root 1137: #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM 1138: && (REGNO (dest) != ARG_POINTER_REGNUM 1139: || ! fixed_regs [REGNO (dest)]) 1140: #endif 1141: && REGNO (dest) != STACK_POINTER_REGNUM) 1.1 root 1142: { 1143: if (*pi3dest_killed) 1144: return 0; 1145: 1146: *pi3dest_killed = dest; 1147: } 1148: } 1149: 1150: else if (GET_CODE (x) == PARALLEL) 1151: { 1152: int i; 1153: 1154: for (i = 0; i < XVECLEN (x, 0); i++) 1155: if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, 1156: i1_not_in_src, pi3dest_killed)) 1157: return 0; 1158: } 1159: 1160: return 1; 1161: } 1162: 1163: /* Try to combine the insns I1 and I2 into I3. 1164: Here I1 and I2 appear earlier than I3. 1165: I1 can be zero; then we combine just I2 into I3. 1166: 1167: It we are combining three insns and the resulting insn is not recognized, 1168: try splitting it into two insns. If that happens, I2 and I3 are retained 1169: and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2 1170: are pseudo-deleted. 1171: 1.1.1.7 ! root 1172: Return 0 if the combination does not work. Then nothing is changed. ! 1173: If we did the combination, return the insn at which combine should ! 1174: resume scanning. */ 1.1 root 1175: 1176: static rtx 1177: try_combine (i3, i2, i1) 1178: register rtx i3, i2, i1; 1179: { 1180: /* New patterns for I3 and I3, respectively. */ 1181: rtx newpat, newi2pat = 0; 1182: /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */ 1183: int added_sets_1, added_sets_2; 1184: /* Total number of SETs to put into I3. */ 1185: int total_sets; 1186: /* Nonzero is I2's body now appears in I3. */ 1187: int i2_is_used; 1188: /* INSN_CODEs for new I3, new I2, and user of condition code. */ 1189: int insn_code_number, i2_code_number, other_code_number; 1190: /* Contains I3 if the destination of I3 is used in its source, which means 1191: that the old life of I3 is being killed. If that usage is placed into 1192: I2 and not in I3, a REG_DEAD note must be made. */ 1193: rtx i3dest_killed = 0; 1194: /* SET_DEST and SET_SRC of I2 and I1. */ 1195: rtx i2dest, i2src, i1dest = 0, i1src = 0; 1196: /* PATTERN (I2), or a copy of it in certain cases. */ 1197: rtx i2pat; 1198: /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */ 1.1.1.6 root 1199: int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0; 1.1 root 1200: int i1_feeds_i3 = 0; 1201: /* Notes that must be added to REG_NOTES in I3 and I2. */ 1202: rtx new_i3_notes, new_i2_notes; 1.1.1.6 root 1203: /* Notes that we substituted I3 into I2 instead of the normal case. */ 1204: int i3_subst_into_i2 = 0; 1.1.1.7 ! root 1205: /* Notes that I1, I2 or I3 is a MULT operation. */ ! 1206: int have_mult = 0; 1.1 root 1207: 1208: int maxreg; 1209: rtx temp; 1210: register rtx link; 1211: int i; 1212: 1213: /* If any of I1, I2, and I3 isn't really an insn, we can't do anything. 1214: This can occur when flow deletes an insn that it has merged into an 1215: auto-increment address. We also can't do anything if I3 has a 1216: REG_LIBCALL note since we don't want to disrupt the contiguity of a 1217: libcall. */ 1218: 1219: if (GET_RTX_CLASS (GET_CODE (i3)) != 'i' 1220: || GET_RTX_CLASS (GET_CODE (i2)) != 'i' 1221: || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i') 1.1.1.4 root 1222: || find_reg_note (i3, REG_LIBCALL, NULL_RTX)) 1.1 root 1223: return 0; 1224: 1225: combine_attempts++; 1226: 1227: undobuf.num_undo = previous_num_undos = 0; 1228: undobuf.other_insn = 0; 1229: 1230: /* Save the current high-water-mark so we can free storage if we didn't 1231: accept this combination. */ 1232: undobuf.storage = (char *) oballoc (0); 1233: 1.1.1.7 ! root 1234: /* Reset the hard register usage information. */ ! 1235: CLEAR_HARD_REG_SET (newpat_used_regs); ! 1236: 1.1 root 1237: /* If I1 and I2 both feed I3, they can be in any order. To simplify the 1238: code below, set I1 to be the earlier of the two insns. */ 1239: if (i1 && INSN_CUID (i1) > INSN_CUID (i2)) 1240: temp = i1, i1 = i2, i2 = temp; 1241: 1.1.1.7 ! root 1242: added_links_insn = 0; 1.1.1.6 root 1243: 1.1 root 1244: /* First check for one important special-case that the code below will 1245: not handle. Namely, the case where I1 is zero, I2 has multiple sets, 1246: and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case, 1247: we may be able to replace that destination with the destination of I3. 1248: This occurs in the common code where we compute both a quotient and 1249: remainder into a structure, in which case we want to do the computation 1250: directly into the structure to avoid register-register copies. 1251: 1252: We make very conservative checks below and only try to handle the 1253: most common cases of this. For example, we only handle the case 1254: where I2 and I3 are adjacent to avoid making difficult register 1255: usage tests. */ 1256: 1257: if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET 1258: && GET_CODE (SET_SRC (PATTERN (i3))) == REG 1259: && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER 1260: #ifdef SMALL_REGISTER_CLASSES 1261: && (GET_CODE (SET_DEST (PATTERN (i3))) != REG 1.1.1.7 ! root 1262: || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER ! 1263: || REG_USERVAR_P (SET_DEST (PATTERN (i3)))) 1.1 root 1264: #endif 1265: && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3))) 1266: && GET_CODE (PATTERN (i2)) == PARALLEL 1267: && ! side_effects_p (SET_DEST (PATTERN (i3))) 1.1.1.2 root 1268: /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code 1269: below would need to check what is inside (and reg_overlap_mentioned_p 1270: doesn't support those codes anyway). Don't allow those destinations; 1271: the resulting insn isn't likely to be recognized anyway. */ 1272: && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT 1273: && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART 1.1 root 1274: && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)), 1275: SET_DEST (PATTERN (i3))) 1276: && next_real_insn (i2) == i3) 1.1.1.2 root 1277: { 1278: rtx p2 = PATTERN (i2); 1.1 root 1279: 1.1.1.2 root 1280: /* Make sure that the destination of I3, 1281: which we are going to substitute into one output of I2, 1282: is not used within another output of I2. We must avoid making this: 1283: (parallel [(set (mem (reg 69)) ...) 1284: (set (reg 69) ...)]) 1285: which is not well-defined as to order of actions. 1286: (Besides, reload can't handle output reloads for this.) 1287: 1288: The problem can also happen if the dest of I3 is a memory ref, 1289: if another dest in I2 is an indirect memory ref. */ 1290: for (i = 0; i < XVECLEN (p2, 0); i++) 1291: if (GET_CODE (XVECEXP (p2, 0, i)) == SET 1292: && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)), 1293: SET_DEST (XVECEXP (p2, 0, i)))) 1294: break; 1295: 1296: if (i == XVECLEN (p2, 0)) 1297: for (i = 0; i < XVECLEN (p2, 0); i++) 1298: if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3))) 1299: { 1300: combine_merges++; 1301: 1302: subst_insn = i3; 1303: subst_low_cuid = INSN_CUID (i2); 1304: 1.1.1.6 root 1305: added_sets_2 = added_sets_1 = 0; 1.1.1.2 root 1306: i2dest = SET_SRC (PATTERN (i3)); 1307: 1308: /* Replace the dest in I2 with our dest and make the resulting 1309: insn the new pattern for I3. Then skip to where we 1310: validate the pattern. Everything was set up above. */ 1311: SUBST (SET_DEST (XVECEXP (p2, 0, i)), 1312: SET_DEST (PATTERN (i3))); 1.1 root 1313: 1.1.1.2 root 1314: newpat = p2; 1.1.1.6 root 1315: i3_subst_into_i2 = 1; 1.1.1.2 root 1316: goto validate_replacement; 1317: } 1318: } 1.1 root 1319: 1320: #ifndef HAVE_cc0 1321: /* If we have no I1 and I2 looks like: 1322: (parallel [(set (reg:CC X) (compare:CC OP (const_int 0))) 1323: (set Y OP)]) 1324: make up a dummy I1 that is 1325: (set Y OP) 1326: and change I2 to be 1327: (set (reg:CC X) (compare:CC Y (const_int 0))) 1328: 1329: (We can ignore any trailing CLOBBERs.) 1330: 1331: This undoes a previous combination and allows us to match a branch-and- 1332: decrement insn. */ 1333: 1334: if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL 1335: && XVECLEN (PATTERN (i2), 0) >= 2 1336: && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET 1337: && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)))) 1338: == MODE_CC) 1339: && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE 1340: && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx 1341: && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET 1342: && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG 1343: && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0), 1344: SET_SRC (XVECEXP (PATTERN (i2), 0, 1)))) 1345: { 1346: for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--) 1347: if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER) 1348: break; 1349: 1350: if (i == 1) 1351: { 1352: /* We make I1 with the same INSN_UID as I2. This gives it 1353: the same INSN_CUID for value tracking. Our fake I1 will 1354: never appear in the insn stream so giving it the same INSN_UID 1355: as I2 will not cause a problem. */ 1356: 1.1.1.7 ! root 1357: i1 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), 0, i2, ! 1358: XVECEXP (PATTERN (i2), 0, 1), -1, 0, 0); 1.1 root 1359: 1360: SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0)); 1361: SUBST (XEXP (SET_SRC (PATTERN (i2)), 0), 1362: SET_DEST (PATTERN (i1))); 1363: } 1364: } 1365: #endif 1366: 1367: /* Verify that I2 and I1 are valid for combining. */ 1.1.1.4 root 1368: if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src) 1369: || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src))) 1.1 root 1370: { 1371: undo_all (); 1372: return 0; 1373: } 1374: 1375: /* Record whether I2DEST is used in I2SRC and similarly for the other 1376: cases. Knowing this will help in register status updating below. */ 1377: i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src); 1378: i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src); 1379: i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src); 1380: 1.1.1.3 root 1381: /* See if I1 directly feeds into I3. It does if I1DEST is not used 1.1 root 1382: in I2SRC. */ 1383: i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src); 1384: 1385: /* Ensure that I3's pattern can be the destination of combines. */ 1386: if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, 1387: i1 && i2dest_in_i1src && i1_feeds_i3, 1388: &i3dest_killed)) 1389: { 1390: undo_all (); 1391: return 0; 1392: } 1393: 1.1.1.7 ! root 1394: /* See if any of the insns is a MULT operation. Unless one is, we will ! 1395: reject a combination that is, since it must be slower. Be conservative ! 1396: here. */ ! 1397: if (GET_CODE (i2src) == MULT ! 1398: || (i1 != 0 && GET_CODE (i1src) == MULT) ! 1399: || (GET_CODE (PATTERN (i3)) == SET ! 1400: && GET_CODE (SET_SRC (PATTERN (i3))) == MULT)) ! 1401: have_mult = 1; ! 1402: 1.1 root 1403: /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd. 1404: We used to do this EXCEPT in one case: I3 has a post-inc in an 1405: output operand. However, that exception can give rise to insns like 1406: mov r3,(r3)+ 1407: which is a famous insn on the PDP-11 where the value of r3 used as the 1.1.1.2 root 1408: source was model-dependent. Avoid this sort of thing. */ 1.1 root 1409: 1410: #if 0 1411: if (!(GET_CODE (PATTERN (i3)) == SET 1412: && GET_CODE (SET_SRC (PATTERN (i3))) == REG 1413: && GET_CODE (SET_DEST (PATTERN (i3))) == MEM 1414: && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC 1415: || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC))) 1416: /* It's not the exception. */ 1417: #endif 1418: #ifdef AUTO_INC_DEC 1419: for (link = REG_NOTES (i3); link; link = XEXP (link, 1)) 1420: if (REG_NOTE_KIND (link) == REG_INC 1421: && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2)) 1422: || (i1 != 0 1423: && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1))))) 1424: { 1425: undo_all (); 1426: return 0; 1427: } 1428: #endif 1429: 1430: /* See if the SETs in I1 or I2 need to be kept around in the merged 1431: instruction: whenever the value set there is still needed past I3. 1432: For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3. 1433: 1434: For the SET in I1, we have two cases: If I1 and I2 independently 1435: feed into I3, the set in I1 needs to be kept around if I1DEST dies 1436: or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set 1437: in I1 needs to be kept around unless I1DEST dies or is set in either 1438: I2 or I3. We can distinguish these cases by seeing if I2SRC mentions 1439: I1DEST. If so, we know I1 feeds into I2. */ 1440: 1441: added_sets_2 = ! dead_or_set_p (i3, i2dest); 1442: 1443: added_sets_1 1444: = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest) 1445: : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest))); 1446: 1447: /* If the set in I2 needs to be kept around, we must make a copy of 1448: PATTERN (I2), so that when we substitute I1SRC for I1DEST in 1.1.1.2 root 1449: PATTERN (I2), we are only substituting for the original I1DEST, not into 1.1 root 1450: an already-substituted copy. This also prevents making self-referential 1451: rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to 1452: I2DEST. */ 1453: 1454: i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL 1455: ? gen_rtx (SET, VOIDmode, i2dest, i2src) 1456: : PATTERN (i2)); 1457: 1458: if (added_sets_2) 1459: i2pat = copy_rtx (i2pat); 1460: 1461: combine_merges++; 1462: 1463: /* Substitute in the latest insn for the regs set by the earlier ones. */ 1464: 1465: maxreg = max_reg_num (); 1466: 1467: subst_insn = i3; 1468: 1469: /* It is possible that the source of I2 or I1 may be performing an 1470: unneeded operation, such as a ZERO_EXTEND of something that is known 1471: to have the high part zero. Handle that case by letting subst look at 1472: the innermost one of them. 1473: 1474: Another way to do this would be to have a function that tries to 1475: simplify a single insn instead of merging two or more insns. We don't 1476: do this because of the potential of infinite loops and because 1477: of the potential extra memory required. However, doing it the way 1478: we are is a bit of a kludge and doesn't catch all cases. 1479: 1480: But only do this if -fexpensive-optimizations since it slows things down 1481: and doesn't usually win. */ 1482: 1483: if (flag_expensive_optimizations) 1484: { 1485: /* Pass pc_rtx so no substitutions are done, just simplifications. 1486: The cases that we are interested in here do not involve the few 1487: cases were is_replaced is checked. */ 1488: if (i1) 1.1.1.4 root 1489: { 1490: subst_low_cuid = INSN_CUID (i1); 1491: i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0); 1492: } 1.1 root 1493: else 1.1.1.4 root 1494: { 1495: subst_low_cuid = INSN_CUID (i2); 1496: i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0); 1497: } 1.1 root 1498: 1499: previous_num_undos = undobuf.num_undo; 1500: } 1501: 1502: #ifndef HAVE_cc0 1503: /* Many machines that don't use CC0 have insns that can both perform an 1504: arithmetic operation and set the condition code. These operations will 1505: be represented as a PARALLEL with the first element of the vector 1506: being a COMPARE of an arithmetic operation with the constant zero. 1507: The second element of the vector will set some pseudo to the result 1508: of the same arithmetic operation. If we simplify the COMPARE, we won't 1509: match such a pattern and so will generate an extra insn. Here we test 1510: for this case, where both the comparison and the operation result are 1511: needed, and make the PARALLEL by just replacing I2DEST in I3SRC with 1512: I2SRC. Later we will make the PARALLEL that contains I2. */ 1513: 1514: if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET 1515: && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE 1516: && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx 1517: && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest)) 1518: { 1519: rtx *cc_use; 1520: enum machine_mode compare_mode; 1521: 1522: newpat = PATTERN (i3); 1523: SUBST (XEXP (SET_SRC (newpat), 0), i2src); 1524: 1525: i2_is_used = 1; 1526: 1527: #ifdef EXTRA_CC_MODES 1528: /* See if a COMPARE with the operand we substituted in should be done 1529: with the mode that is currently being used. If not, do the same 1530: processing we do in `subst' for a SET; namely, if the destination 1531: is used only once, try to replace it with a register of the proper 1532: mode and also replace the COMPARE. */ 1533: if (undobuf.other_insn == 0 1534: && (cc_use = find_single_use (SET_DEST (newpat), i3, 1535: &undobuf.other_insn)) 1.1.1.4 root 1536: && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use), 1537: i2src, const0_rtx)) 1.1 root 1538: != GET_MODE (SET_DEST (newpat)))) 1539: { 1540: int regno = REGNO (SET_DEST (newpat)); 1541: rtx new_dest = gen_rtx (REG, compare_mode, regno); 1542: 1543: if (regno < FIRST_PSEUDO_REGISTER 1544: || (reg_n_sets[regno] == 1 && ! added_sets_2 1545: && ! REG_USERVAR_P (SET_DEST (newpat)))) 1546: { 1547: if (regno >= FIRST_PSEUDO_REGISTER) 1548: SUBST (regno_reg_rtx[regno], new_dest); 1549: 1550: SUBST (SET_DEST (newpat), new_dest); 1551: SUBST (XEXP (*cc_use, 0), new_dest); 1552: SUBST (SET_SRC (newpat), 1553: gen_rtx_combine (COMPARE, compare_mode, 1554: i2src, const0_rtx)); 1555: } 1556: else 1557: undobuf.other_insn = 0; 1558: } 1559: #endif 1560: } 1561: else 1562: #endif 1563: { 1564: n_occurrences = 0; /* `subst' counts here */ 1565: 1566: /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we 1567: need to make a unique copy of I2SRC each time we substitute it 1568: to avoid self-referential rtl. */ 1569: 1.1.1.4 root 1570: subst_low_cuid = INSN_CUID (i2); 1.1 root 1571: newpat = subst (PATTERN (i3), i2dest, i2src, 0, 1572: ! i1_feeds_i3 && i1dest_in_i1src); 1573: previous_num_undos = undobuf.num_undo; 1574: 1575: /* Record whether i2's body now appears within i3's body. */ 1576: i2_is_used = n_occurrences; 1577: } 1578: 1579: /* If we already got a failure, don't try to do more. Otherwise, 1580: try to substitute in I1 if we have it. */ 1581: 1582: if (i1 && GET_CODE (newpat) != CLOBBER) 1583: { 1584: /* Before we can do this substitution, we must redo the test done 1585: above (see detailed comments there) that ensures that I1DEST 1586: isn't mentioned in any SETs in NEWPAT that are field assignments. */ 1587: 1.1.1.4 root 1588: if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 1589: 0, NULL_PTR)) 1.1 root 1590: { 1591: undo_all (); 1592: return 0; 1593: } 1594: 1595: n_occurrences = 0; 1.1.1.4 root 1596: subst_low_cuid = INSN_CUID (i1); 1.1 root 1597: newpat = subst (newpat, i1dest, i1src, 0, 0); 1598: previous_num_undos = undobuf.num_undo; 1599: } 1600: 1.1.1.3 root 1601: /* Fail if an autoincrement side-effect has been duplicated. Be careful 1602: to count all the ways that I2SRC and I1SRC can be used. */ 1.1.1.4 root 1603: if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0 1.1.1.3 root 1604: && i2_is_used + added_sets_2 > 1) 1.1.1.4 root 1605: || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0 1.1.1.3 root 1606: && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3) 1607: > 1)) 1.1 root 1608: /* Fail if we tried to make a new register (we used to abort, but there's 1609: really no reason to). */ 1610: || max_reg_num () != maxreg 1611: /* Fail if we couldn't do something and have a CLOBBER. */ 1.1.1.7 ! root 1612: || GET_CODE (newpat) == CLOBBER ! 1613: /* Fail if this new pattern is a MULT and we didn't have one before ! 1614: at the outer level. */ ! 1615: || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT ! 1616: && ! have_mult)) 1.1 root 1617: { 1618: undo_all (); 1619: return 0; 1620: } 1621: 1622: /* If the actions of the earlier insns must be kept 1623: in addition to substituting them into the latest one, 1624: we must make a new PARALLEL for the latest insn 1625: to hold additional the SETs. */ 1626: 1627: if (added_sets_1 || added_sets_2) 1628: { 1629: combine_extras++; 1630: 1631: if (GET_CODE (newpat) == PARALLEL) 1632: { 1633: rtvec old = XVEC (newpat, 0); 1634: total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2; 1635: newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets)); 1.1.1.7 ! root 1636: bcopy ((char *) &old->elem[0], (char *) &XVECEXP (newpat, 0, 0), 1.1 root 1637: sizeof (old->elem[0]) * old->num_elem); 1638: } 1639: else 1640: { 1641: rtx old = newpat; 1642: total_sets = 1 + added_sets_1 + added_sets_2; 1643: newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets)); 1644: XVECEXP (newpat, 0, 0) = old; 1645: } 1646: 1647: if (added_sets_1) 1648: XVECEXP (newpat, 0, --total_sets) 1649: = (GET_CODE (PATTERN (i1)) == PARALLEL 1650: ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1)); 1651: 1652: if (added_sets_2) 1653: { 1654: /* If there is no I1, use I2's body as is. We used to also not do 1655: the subst call below if I2 was substituted into I3, 1656: but that could lose a simplification. */ 1657: if (i1 == 0) 1658: XVECEXP (newpat, 0, --total_sets) = i2pat; 1659: else 1660: /* See comment where i2pat is assigned. */ 1661: XVECEXP (newpat, 0, --total_sets) 1662: = subst (i2pat, i1dest, i1src, 0, 0); 1663: } 1664: } 1665: 1666: /* We come here when we are replacing a destination in I2 with the 1667: destination of I3. */ 1668: validate_replacement: 1669: 1.1.1.7 ! root 1670: /* Note which hard regs this insn has as inputs. */ ! 1671: mark_used_regs_combine (newpat); ! 1672: 1.1 root 1673: /* Is the result of combination a valid instruction? */ 1674: insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 1675: 1676: /* If the result isn't valid, see if it is a PARALLEL of two SETs where 1677: the second SET's destination is a register that is unused. In that case, 1678: we just need the first SET. This can occur when simplifying a divmod 1679: insn. We *must* test for this case here because the code below that 1680: splits two independent SETs doesn't handle this case correctly when it 1681: updates the register status. Also check the case where the first 1682: SET's destination is unused. That would not cause incorrect code, but 1683: does cause an unneeded insn to remain. */ 1684: 1685: if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL 1686: && XVECLEN (newpat, 0) == 2 1687: && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 1688: && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 1689: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG 1690: && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1))) 1691: && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1))) 1692: && asm_noperands (newpat) < 0) 1693: { 1694: newpat = XVECEXP (newpat, 0, 0); 1695: insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 1696: } 1697: 1698: else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL 1699: && XVECLEN (newpat, 0) == 2 1700: && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 1701: && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 1702: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG 1703: && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0))) 1704: && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0))) 1705: && asm_noperands (newpat) < 0) 1706: { 1707: newpat = XVECEXP (newpat, 0, 1); 1708: insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 1709: } 1710: 1711: /* If we were combining three insns and the result is a simple SET 1712: with no ASM_OPERANDS that wasn't recognized, try to split it into two 1.1.1.3 root 1713: insns. There are two ways to do this. It can be split using a 1714: machine-specific method (like when you have an addition of a large 1715: constant) or by combine in the function find_split_point. */ 1716: 1.1 root 1717: if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET 1718: && asm_noperands (newpat) < 0) 1719: { 1.1.1.3 root 1720: rtx m_split, *split; 1.1.1.4 root 1721: rtx ni2dest = i2dest; 1.1.1.3 root 1722: 1723: /* See if the MD file can split NEWPAT. If it can't, see if letting it 1.1.1.4 root 1724: use I2DEST as a scratch register will help. In the latter case, 1725: convert I2DEST to the mode of the source of NEWPAT if we can. */ 1.1.1.3 root 1726: 1727: m_split = split_insns (newpat, i3); 1.1.1.4 root 1728: 1729: /* We can only use I2DEST as a scratch reg if it doesn't overlap any 1730: inputs of NEWPAT. */ 1731: 1732: /* ??? If I2DEST is not safe, and I1DEST exists, then it would be 1733: possible to try that as a scratch reg. This would require adding 1734: more code to make it work though. */ 1735: 1736: if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat)) 1737: { 1738: /* If I2DEST is a hard register or the only use of a pseudo, 1739: we can change its mode. */ 1740: if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest) 1741: && GET_MODE (SET_DEST (newpat)) != VOIDmode 1742: && GET_CODE (i2dest) == REG 1743: && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER 1744: || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2 1745: && ! REG_USERVAR_P (i2dest)))) 1746: ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)), 1747: REGNO (i2dest)); 1748: 1749: m_split = split_insns (gen_rtx (PARALLEL, VOIDmode, 1750: gen_rtvec (2, newpat, 1751: gen_rtx (CLOBBER, 1752: VOIDmode, 1753: ni2dest))), 1754: i3); 1755: } 1.1.1.3 root 1756: 1757: if (m_split && GET_CODE (m_split) == SEQUENCE 1758: && XVECLEN (m_split, 0) == 2 1759: && (next_real_insn (i2) == i3 1760: || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)), 1761: INSN_CUID (i2)))) 1762: { 1.1.1.4 root 1763: rtx i2set, i3set; 1764: rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1)); 1.1.1.3 root 1765: newi2pat = PATTERN (XVECEXP (m_split, 0, 0)); 1.1.1.4 root 1766: 1767: i3set = single_set (XVECEXP (m_split, 0, 1)); 1768: i2set = single_set (XVECEXP (m_split, 0, 0)); 1769: 1770: /* In case we changed the mode of I2DEST, replace it in the 1771: pseudo-register table here. We can't do it above in case this 1772: code doesn't get executed and we do a split the other way. */ 1773: 1774: if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) 1775: SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest); 1.1.1.3 root 1776: 1777: i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 1.1.1.4 root 1778: 1779: /* If I2 or I3 has multiple SETs, we won't know how to track 1780: register status, so don't use these insns. */ 1781: 1782: if (i2_code_number >= 0 && i2set && i3set) 1783: insn_code_number = recog_for_combine (&newi3pat, i3, 1784: &new_i3_notes); 1785: 1786: if (insn_code_number >= 0) 1787: newpat = newi3pat; 1788: 1789: /* It is possible that both insns now set the destination of I3. 1790: If so, we must show an extra use of it. */ 1791: 1792: if (insn_code_number >= 0 && GET_CODE (SET_DEST (i3set)) == REG 1793: && GET_CODE (SET_DEST (i2set)) == REG 1794: && REGNO (SET_DEST (i3set)) == REGNO (SET_DEST (i2set))) 1795: reg_n_sets[REGNO (SET_DEST (i2set))]++; 1.1.1.3 root 1796: } 1.1 root 1797: 1798: /* If we can split it and use I2DEST, go ahead and see if that 1799: helps things be recognized. Verify that none of the registers 1800: are set between I2 and I3. */ 1.1.1.4 root 1801: if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0 1.1 root 1802: #ifdef HAVE_cc0 1803: && GET_CODE (i2dest) == REG 1804: #endif 1805: /* We need I2DEST in the proper mode. If it is a hard register 1806: or the only use of a pseudo, we can change its mode. */ 1807: && (GET_MODE (*split) == GET_MODE (i2dest) 1808: || GET_MODE (*split) == VOIDmode 1809: || REGNO (i2dest) < FIRST_PSEUDO_REGISTER 1810: || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2 1811: && ! REG_USERVAR_P (i2dest))) 1812: && (next_real_insn (i2) == i3 1813: || ! use_crosses_set_p (*split, INSN_CUID (i2))) 1814: /* We can't overwrite I2DEST if its value is still used by 1815: NEWPAT. */ 1816: && ! reg_referenced_p (i2dest, newpat)) 1817: { 1818: rtx newdest = i2dest; 1.1.1.7 ! root 1819: enum rtx_code split_code = GET_CODE (*split); ! 1820: enum machine_mode split_mode = GET_MODE (*split); 1.1 root 1821: 1822: /* Get NEWDEST as a register in the proper mode. We have already 1823: validated that we can do this. */ 1.1.1.7 ! root 1824: if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode) 1.1 root 1825: { 1.1.1.7 ! root 1826: newdest = gen_rtx (REG, split_mode, REGNO (i2dest)); 1.1 root 1827: 1828: if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) 1829: SUBST (regno_reg_rtx[REGNO (i2dest)], newdest); 1830: } 1831: 1832: /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to 1833: an ASHIFT. This can occur if it was inside a PLUS and hence 1834: appeared to be a memory address. This is a kludge. */ 1.1.1.7 ! root 1835: if (split_code == MULT 1.1 root 1836: && GET_CODE (XEXP (*split, 1)) == CONST_INT 1837: && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0) 1.1.1.7 ! root 1838: { ! 1839: SUBST (*split, gen_rtx_combine (ASHIFT, split_mode, ! 1840: XEXP (*split, 0), GEN_INT (i))); ! 1841: /* Update split_code because we may not have a multiply ! 1842: anymore. */ ! 1843: split_code = GET_CODE (*split); ! 1844: } 1.1 root 1845: 1846: #ifdef INSN_SCHEDULING 1847: /* If *SPLIT is a paradoxical SUBREG, when we split it, it should 1848: be written as a ZERO_EXTEND. */ 1.1.1.7 ! root 1849: if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM) ! 1850: SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode, 1.1 root 1851: XEXP (*split, 0))); 1852: #endif 1853: 1854: newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split); 1855: SUBST (*split, newdest); 1856: i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 1.1.1.7 ! root 1857: ! 1858: /* If the split point was a MULT and we didn't have one before, ! 1859: don't use one now. */ ! 1860: if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult)) 1.1 root 1861: insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 1862: } 1863: } 1864: 1865: /* Check for a case where we loaded from memory in a narrow mode and 1866: then sign extended it, but we need both registers. In that case, 1867: we have a PARALLEL with both loads from the same memory location. 1868: We can split this into a load from memory followed by a register-register 1869: copy. This saves at least one insn, more if register allocation can 1.1.1.6 root 1870: eliminate the copy. 1871: 1872: We cannot do this if the destination of the second assignment is 1873: a register that we have already assumed is zero-extended. Similarly 1874: for a SUBREG of such a register. */ 1.1 root 1875: 1876: else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 1877: && GET_CODE (newpat) == PARALLEL 1878: && XVECLEN (newpat, 0) == 2 1879: && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 1880: && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND 1881: && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 1882: && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)), 1883: XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0)) 1884: && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), 1885: INSN_CUID (i2)) 1886: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT 1887: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART 1.1.1.6 root 1888: && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)), 1889: (GET_CODE (temp) == REG 1890: && reg_nonzero_bits[REGNO (temp)] != 0 1891: && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD 1892: && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT 1893: && (reg_nonzero_bits[REGNO (temp)] 1894: != GET_MODE_MASK (word_mode)))) 1895: && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG 1896: && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))), 1897: (GET_CODE (temp) == REG 1898: && reg_nonzero_bits[REGNO (temp)] != 0 1899: && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD 1900: && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT 1901: && (reg_nonzero_bits[REGNO (temp)] 1902: != GET_MODE_MASK (word_mode))))) 1.1 root 1903: && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)), 1904: SET_SRC (XVECEXP (newpat, 0, 1))) 1905: && ! find_reg_note (i3, REG_UNUSED, 1906: SET_DEST (XVECEXP (newpat, 0, 0)))) 1907: { 1.1.1.4 root 1908: rtx ni2dest; 1909: 1.1 root 1910: newi2pat = XVECEXP (newpat, 0, 0); 1.1.1.4 root 1911: ni2dest = SET_DEST (XVECEXP (newpat, 0, 0)); 1.1 root 1912: newpat = XVECEXP (newpat, 0, 1); 1913: SUBST (SET_SRC (newpat), 1.1.1.4 root 1914: gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest)); 1.1 root 1915: i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 1916: if (i2_code_number >= 0) 1917: insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 1.1.1.2 root 1918: 1919: if (insn_code_number >= 0) 1920: { 1921: rtx insn; 1922: rtx link; 1923: 1924: /* If we will be able to accept this, we have made a change to the 1925: destination of I3. This can invalidate a LOG_LINKS pointing 1926: to I3. No other part of combine.c makes such a transformation. 1927: 1928: The new I3 will have a destination that was previously the 1929: destination of I1 or I2 and which was used in i2 or I3. Call 1930: distribute_links to make a LOG_LINK from the next use of 1931: that destination. */ 1932: 1933: PATTERN (i3) = newpat; 1.1.1.4 root 1934: distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, NULL_RTX)); 1.1.1.2 root 1935: 1936: /* I3 now uses what used to be its destination and which is 1937: now I2's destination. That means we need a LOG_LINK from 1938: I3 to I2. But we used to have one, so we still will. 1939: 1940: However, some later insn might be using I2's dest and have 1941: a LOG_LINK pointing at I3. We must remove this link. 1942: The simplest way to remove the link is to point it at I1, 1943: which we know will be a NOTE. */ 1944: 1945: for (insn = NEXT_INSN (i3); 1.1.1.6 root 1946: insn && (this_basic_block == n_basic_blocks - 1 1947: || insn != basic_block_head[this_basic_block + 1]); 1.1.1.2 root 1948: insn = NEXT_INSN (insn)) 1949: { 1950: if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' 1.1.1.4 root 1951: && reg_referenced_p (ni2dest, PATTERN (insn))) 1.1.1.2 root 1952: { 1953: for (link = LOG_LINKS (insn); link; 1954: link = XEXP (link, 1)) 1955: if (XEXP (link, 0) == i3) 1956: XEXP (link, 0) = i1; 1957: 1958: break; 1959: } 1960: } 1961: } 1.1 root 1962: } 1963: 1964: /* Similarly, check for a case where we have a PARALLEL of two independent 1965: SETs but we started with three insns. In this case, we can do the sets 1966: as two separate insns. This case occurs when some SET allows two 1967: other insns to combine, but the destination of that SET is still live. */ 1968: 1969: else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 1970: && GET_CODE (newpat) == PARALLEL 1971: && XVECLEN (newpat, 0) == 2 1972: && GET_CODE (XVECEXP (newpat, 0, 0)) == SET 1973: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT 1974: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART 1975: && GET_CODE (XVECEXP (newpat, 0, 1)) == SET 1976: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT 1977: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART 1978: && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), 1979: INSN_CUID (i2)) 1980: /* Don't pass sets with (USE (MEM ...)) dests to the following. */ 1981: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE 1982: && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE 1983: && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)), 1984: XVECEXP (newpat, 0, 0)) 1985: && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)), 1986: XVECEXP (newpat, 0, 1))) 1987: { 1988: newi2pat = XVECEXP (newpat, 0, 1); 1989: newpat = XVECEXP (newpat, 0, 0); 1990: 1991: i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); 1992: if (i2_code_number >= 0) 1993: insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); 1994: } 1995: 1996: /* If it still isn't recognized, fail and change things back the way they 1997: were. */ 1998: if ((insn_code_number < 0 1999: /* Is the result a reasonable ASM_OPERANDS? */ 2000: && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2))) 2001: { 2002: undo_all (); 2003: return 0; 2004: } 2005: 2006: /* If we had to change another insn, make sure it is valid also. */ 2007: if (undobuf.other_insn) 2008: { 2009: rtx other_pat = PATTERN (undobuf.other_insn); 2010: rtx new_other_notes; 2011: rtx note, next; 2012: 1.1.1.7 ! root 2013: CLEAR_HARD_REG_SET (newpat_used_regs); ! 2014: 1.1 root 2015: other_code_number = recog_for_combine (&other_pat, undobuf.other_insn, 2016: &new_other_notes); 2017: 2018: if (other_code_number < 0 && ! check_asm_operands (other_pat)) 2019: { 2020: undo_all (); 2021: return 0; 2022: } 2023: 2024: PATTERN (undobuf.other_insn) = other_pat; 2025: 2026: /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they 2027: are still valid. Then add any non-duplicate notes added by 2028: recog_for_combine. */ 2029: for (note = REG_NOTES (undobuf.other_insn); note; note = next) 2030: { 2031: next = XEXP (note, 1); 2032: 2033: if (REG_NOTE_KIND (note) == REG_UNUSED 2034: && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn))) 1.1.1.4 root 2035: { 2036: if (GET_CODE (XEXP (note, 0)) == REG) 2037: reg_n_deaths[REGNO (XEXP (note, 0))]--; 2038: 2039: remove_note (undobuf.other_insn, note); 2040: } 1.1 root 2041: } 2042: 1.1.1.4 root 2043: for (note = new_other_notes; note; note = XEXP (note, 1)) 2044: if (GET_CODE (XEXP (note, 0)) == REG) 2045: reg_n_deaths[REGNO (XEXP (note, 0))]++; 2046: 1.1 root 2047: distribute_notes (new_other_notes, undobuf.other_insn, 1.1.1.4 root 2048: undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX); 1.1 root 2049: } 2050: 2051: /* We now know that we can do this combination. Merge the insns and 2052: update the status of registers and LOG_LINKS. */ 2053: 2054: { 2055: rtx i3notes, i2notes, i1notes = 0; 2056: rtx i3links, i2links, i1links = 0; 2057: rtx midnotes = 0; 2058: register int regno; 2059: /* Compute which registers we expect to eliminate. */ 2060: rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src 2061: ? 0 : i2dest); 2062: rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest; 2063: 2064: /* Get the old REG_NOTES and LOG_LINKS from all our insns and 2065: clear them. */ 2066: i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3); 2067: i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2); 2068: if (i1) 2069: i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1); 2070: 2071: /* Ensure that we do not have something that should not be shared but 2072: occurs multiple times in the new insns. Check this by first 1.1.1.2 root 2073: resetting all the `used' flags and then copying anything is shared. */ 1.1 root 2074: 2075: reset_used_flags (i3notes); 2076: reset_used_flags (i2notes); 2077: reset_used_flags (i1notes); 2078: reset_used_flags (newpat); 2079: reset_used_flags (newi2pat); 2080: if (undobuf.other_insn) 2081: reset_used_flags (PATTERN (undobuf.other_insn)); 2082: 2083: i3notes = copy_rtx_if_shared (i3notes); 2084: i2notes = copy_rtx_if_shared (i2notes); 2085: i1notes = copy_rtx_if_shared (i1notes); 2086: newpat = copy_rtx_if_shared (newpat); 2087: newi2pat = copy_rtx_if_shared (newi2pat); 2088: if (undobuf.other_insn) 2089: reset_used_flags (PATTERN (undobuf.other_insn)); 2090: 2091: INSN_CODE (i3) = insn_code_number; 2092: PATTERN (i3) = newpat; 2093: if (undobuf.other_insn) 2094: INSN_CODE (undobuf.other_insn) = other_code_number; 2095: 2096: /* We had one special case above where I2 had more than one set and 2097: we replaced a destination of one of those sets with the destination 2098: of I3. In that case, we have to update LOG_LINKS of insns later 1.1.1.6 root 2099: in this basic block. Note that this (expensive) case is rare. 1.1 root 2100: 1.1.1.6 root 2101: Also, in this case, we must pretend that all REG_NOTEs for I2 2102: actually came from I3, so that REG_UNUSED notes from I2 will be 2103: properly handled. */ 1.1 root 2104: 1.1.1.6 root 2105: if (i3_subst_into_i2) 2106: { 2107: for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++) 2108: if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG 2109: && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest 2110: && ! find_reg_note (i2, REG_UNUSED, 2111: SET_DEST (XVECEXP (PATTERN (i2), 0, i)))) 2112: for (temp = NEXT_INSN (i2); 2113: temp && (this_basic_block == n_basic_blocks - 1 2114: || basic_block_head[this_basic_block] != temp); 2115: temp = NEXT_INSN (temp)) 2116: if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i') 2117: for (link = LOG_LINKS (temp); link; link = XEXP (link, 1)) 2118: if (XEXP (link, 0) == i2) 2119: XEXP (link, 0) = i3; 1.1 root 2120: 1.1.1.6 root 2121: if (i3notes) 2122: { 2123: rtx link = i3notes; 2124: while (XEXP (link, 1)) 2125: link = XEXP (link, 1); 2126: XEXP (link, 1) = i2notes; 1.1 root 2127: } 1.1.1.6 root 2128: else 2129: i3notes = i2notes; 2130: i2notes = 0; 2131: } 1.1 root 2132: 2133: LOG_LINKS (i3) = 0; 2134: REG_NOTES (i3) = 0; 2135: LOG_LINKS (i2) = 0; 2136: REG_NOTES (i2) = 0; 2137: 2138: if (newi2pat) 2139: { 2140: INSN_CODE (i2) = i2_code_number; 2141: PATTERN (i2) = newi2pat; 2142: } 2143: else 2144: { 2145: PUT_CODE (i2, NOTE); 2146: NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED; 2147: NOTE_SOURCE_FILE (i2) = 0; 2148: } 2149: 2150: if (i1) 2151: { 2152: LOG_LINKS (i1) = 0; 2153: REG_NOTES (i1) = 0; 2154: PUT_CODE (i1, NOTE); 2155: NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED; 2156: NOTE_SOURCE_FILE (i1) = 0; 2157: } 2158: 2159: /* Get death notes for everything that is now used in either I3 or 2160: I2 and used to die in a previous insn. */ 2161: 2162: move_deaths (newpat, i1 ? INSN_CUID (i1) : INSN_CUID (i2), i3, &midnotes); 2163: if (newi2pat) 2164: move_deaths (newi2pat, INSN_CUID (i1), i2, &midnotes); 2165: 2166: /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */ 2167: if (i3notes) 1.1.1.4 root 2168: distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX, 2169: elim_i2, elim_i1); 1.1 root 2170: if (i2notes) 1.1.1.4 root 2171: distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX, 2172: elim_i2, elim_i1); 1.1 root 2173: if (i1notes) 1.1.1.4 root 2174: distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX, 2175: elim_i2, elim_i1); 1.1 root 2176: if (midnotes) 1.1.1.4 root 2177: distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, 2178: elim_i2, elim_i1); 1.1 root 2179: 2180: /* Distribute any notes added to I2 or I3 by recog_for_combine. We 2181: know these are REG_UNUSED and want them to go to the desired insn, 1.1.1.4 root 2182: so we always pass it as i3. We have not counted the notes in 2183: reg_n_deaths yet, so we need to do so now. */ 2184: 1.1 root 2185: if (newi2pat && new_i2_notes) 1.1.1.4 root 2186: { 2187: for (temp = new_i2_notes; temp; temp = XEXP (temp, 1)) 2188: if (GET_CODE (XEXP (temp, 0)) == REG) 2189: reg_n_deaths[REGNO (XEXP (temp, 0))]++; 2190: 2191: distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX); 2192: } 2193: 1.1 root 2194: if (new_i3_notes) 1.1.1.4 root 2195: { 2196: for (temp = new_i3_notes; temp; temp = XEXP (temp, 1)) 2197: if (GET_CODE (XEXP (temp, 0)) == REG) 2198: reg_n_deaths[REGNO (XEXP (temp, 0))]++; 2199: 2200: distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX); 2201: } 1.1 root 2202: 2203: /* If I3DEST was used in I3SRC, it really died in I3. We may need to 1.1.1.4 root 2204: put a REG_DEAD note for it somewhere. Similarly for I2 and I1. 2205: Show an additional death due to the REG_DEAD note we make here. If 2206: we discard it in distribute_notes, we will decrement it again. */ 2207: 1.1 root 2208: if (i3dest_killed) 1.1.1.4 root 2209: { 2210: if (GET_CODE (i3dest_killed) == REG) 2211: reg_n_deaths[REGNO (i3dest_killed)]++; 2212: 2213: distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed, 2214: NULL_RTX), 2215: NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, 2216: NULL_RTX, NULL_RTX); 2217: } 2218: 2219: /* For I2 and I1, we have to be careful. If NEWI2PAT exists and sets 2220: I2DEST or I1DEST, the death must be somewhere before I2, not I3. If 2221: we passed I3 in that case, it might delete I2. */ 2222: 1.1 root 2223: if (i2dest_in_i2src) 1.1.1.4 root 2224: { 2225: if (GET_CODE (i2dest) == REG) 2226: reg_n_deaths[REGNO (i2dest)]++; 2227: 2228: if (newi2pat && reg_set_p (i2dest, newi2pat)) 2229: distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX), 2230: NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX); 2231: else 2232: distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX), 2233: NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, 2234: NULL_RTX, NULL_RTX); 2235: } 2236: 1.1 root 2237: if (i1dest_in_i1src) 1.1.1.4 root 2238: { 2239: if (GET_CODE (i1dest) == REG) 2240: reg_n_deaths[REGNO (i1dest)]++; 2241: 2242: if (newi2pat && reg_set_p (i1dest, newi2pat)) 2243: distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX), 2244: NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX); 2245: else 2246: distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX), 2247: NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, 2248: NULL_RTX, NULL_RTX); 2249: } 1.1 root 2250: 2251: distribute_links (i3links); 2252: distribute_links (i2links); 2253: distribute_links (i1links); 2254: 2255: if (GET_CODE (i2dest) == REG) 2256: { 1.1.1.4 root 2257: rtx link; 2258: rtx i2_insn = 0, i2_val = 0, set; 2259: 2260: /* The insn that used to set this register doesn't exist, and 2261: this life of the register may not exist either. See if one of 2262: I3's links points to an insn that sets I2DEST. If it does, 2263: that is now the last known value for I2DEST. If we don't update 2264: this and I2 set the register to a value that depended on its old 1.1 root 2265: contents, we will get confused. If this insn is used, thing 2266: will be set correctly in combine_instructions. */ 1.1.1.4 root 2267: 2268: for (link = LOG_LINKS (i3); link; link = XEXP (link, 1)) 2269: if ((set = single_set (XEXP (link, 0))) != 0 2270: && rtx_equal_p (i2dest, SET_DEST (set))) 2271: i2_insn = XEXP (link, 0), i2_val = SET_SRC (set); 2272: 2273: record_value_for_reg (i2dest, i2_insn, i2_val); 1.1 root 2274: 2275: /* If the reg formerly set in I2 died only once and that was in I3, 2276: zero its use count so it won't make `reload' do any work. */ 1.1.1.7 ! root 2277: if (! added_sets_2 && newi2pat == 0 && ! i2dest_in_i2src) 1.1 root 2278: { 2279: regno = REGNO (i2dest); 2280: reg_n_sets[regno]--; 2281: if (reg_n_sets[regno] == 0 1.1.1.4 root 2282: && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS] 2283: & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS)))) 1.1 root 2284: reg_n_refs[regno] = 0; 2285: } 2286: } 2287: 2288: if (i1 && GET_CODE (i1dest) == REG) 2289: { 1.1.1.4 root 2290: rtx link; 2291: rtx i1_insn = 0, i1_val = 0, set; 2292: 2293: for (link = LOG_LINKS (i3); link; link = XEXP (link, 1)) 2294: if ((set = single_set (XEXP (link, 0))) != 0 2295: && rtx_equal_p (i1dest, SET_DEST (set))) 2296: i1_insn = XEXP (link, 0), i1_val = SET_SRC (set); 2297: 2298: record_value_for_reg (i1dest, i1_insn, i1_val); 2299: 1.1 root 2300: regno = REGNO (i1dest); 1.1.1.7 ! root 2301: if (! added_sets_1 && ! i1dest_in_i1src) 1.1 root 2302: { 2303: reg_n_sets[regno]--; 2304: if (reg_n_sets[regno] == 0 1.1.1.4 root 2305: && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS] 2306: & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS)))) 1.1 root 2307: reg_n_refs[regno] = 0; 2308: } 2309: } 2310: 1.1.1.5 root 2311: /* Update reg_nonzero_bits et al for any changes that may have been made 1.1.1.4 root 2312: to this insn. */ 2313: 1.1.1.5 root 2314: note_stores (newpat, set_nonzero_bits_and_sign_copies); 1.1.1.4 root 2315: if (newi2pat) 1.1.1.5 root 2316: note_stores (newi2pat, set_nonzero_bits_and_sign_copies); 1.1.1.4 root 2317: 1.1 root 2318: /* If I3 is now an unconditional jump, ensure that it has a 2319: BARRIER following it since it may have initially been a 1.1.1.4 root 2320: conditional jump. It may also be the last nonnote insn. */ 1.1 root 2321: 2322: if ((GET_CODE (newpat) == RETURN || simplejump_p (i3)) 1.1.1.4 root 2323: && ((temp = next_nonnote_insn (i3)) == NULL_RTX 2324: || GET_CODE (temp) != BARRIER)) 1.1 root 2325: emit_barrier_after (i3); 2326: } 2327: 2328: combine_successes++; 2329: 1.1.1.7 ! root 2330: if (added_links_insn ! 2331: && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2)) ! 2332: && INSN_CUID (added_links_insn) < INSN_CUID (i3)) ! 2333: return added_links_insn; ! 2334: else ! 2335: return newi2pat ? i2 : i3; 1.1 root 2336: } 2337: 2338: /* Undo all the modifications recorded in undobuf. */ 2339: 2340: static void 2341: undo_all () 2342: { 2343: register int i; 2344: if (undobuf.num_undo > MAX_UNDO) 2345: undobuf.num_undo = MAX_UNDO; 2346: for (i = undobuf.num_undo - 1; i >= 0; i--) 1.1.1.4 root 2347: { 2348: if (undobuf.undo[i].is_int) 2349: *undobuf.undo[i].where.i = undobuf.undo[i].old_contents.i; 2350: else 1.1.1.6 root 2351: *undobuf.undo[i].where.r = undobuf.undo[i].old_contents.r; 1.1.1.4 root 2352: 2353: } 1.1 root 2354: 2355: obfree (undobuf.storage); 2356: undobuf.num_undo = 0; 2357: } 2358: 2359: /* Find the innermost point within the rtx at LOC, possibly LOC itself, 1.1.1.4 root 2360: where we have an arithmetic expression and return that point. LOC will 2361: be inside INSN. 1.1 root 2362: 2363: try_combine will call this function to see if an insn can be split into 2364: two insns. */ 2365: 2366: static rtx * 1.1.1.4 root 2367: find_split_point (loc, insn) 1.1 root 2368: rtx *loc; 1.1.1.4 root 2369: rtx insn; 1.1 root 2370: { 2371: rtx x = *loc; 2372: enum rtx_code code = GET_CODE (x); 2373: rtx *split; 2374: int len = 0, pos, unsignedp; 2375: rtx inner; 2376: 2377: /* First special-case some codes. */ 2378: switch (code) 2379: { 2380: case SUBREG: 2381: #ifdef INSN_SCHEDULING 2382: /* If we are making a paradoxical SUBREG invalid, it becomes a split 2383: point. */ 2384: if (GET_CODE (SUBREG_REG (x)) == MEM) 2385: return loc; 2386: #endif 1.1.1.4 root 2387: return find_split_point (&SUBREG_REG (x), insn); 1.1 root 2388: 2389: case MEM: 1.1.1.3 root 2390: #ifdef HAVE_lo_sum 1.1 root 2391: /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it 2392: using LO_SUM and HIGH. */ 2393: if (GET_CODE (XEXP (x, 0)) == CONST 2394: || GET_CODE (XEXP (x, 0)) == SYMBOL_REF) 2395: { 2396: SUBST (XEXP (x, 0), 2397: gen_rtx_combine (LO_SUM, Pmode, 2398: gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)), 2399: XEXP (x, 0))); 2400: return &XEXP (XEXP (x, 0), 0); 2401: } 2402: #endif 2403: 1.1.1.3 root 2404: /* If we have a PLUS whose second operand is a constant and the 2405: address is not valid, perhaps will can split it up using 2406: the machine-specific way to split large constants. We use 2407: the first psuedo-reg (one of the virtual regs) as a placeholder; 2408: it will not remain in the result. */ 2409: if (GET_CODE (XEXP (x, 0)) == PLUS 2410: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 2411: && ! memory_address_p (GET_MODE (x), XEXP (x, 0))) 2412: { 2413: rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER]; 2414: rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)), 2415: subst_insn); 2416: 2417: /* This should have produced two insns, each of which sets our 2418: placeholder. If the source of the second is a valid address, 2419: we can make put both sources together and make a split point 2420: in the middle. */ 2421: 2422: if (seq && XVECLEN (seq, 0) == 2 2423: && GET_CODE (XVECEXP (seq, 0, 0)) == INSN 2424: && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET 2425: && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg 2426: && ! reg_mentioned_p (reg, 2427: SET_SRC (PATTERN (XVECEXP (seq, 0, 0)))) 2428: && GET_CODE (XVECEXP (seq, 0, 1)) == INSN 2429: && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET 2430: && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg 2431: && memory_address_p (GET_MODE (x), 2432: SET_SRC (PATTERN (XVECEXP (seq, 0, 1))))) 2433: { 2434: rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0))); 2435: rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1))); 2436: 2437: /* Replace the placeholder in SRC2 with SRC1. If we can 2438: find where in SRC2 it was placed, that can become our 2439: split point and we can replace this address with SRC2. 2440: Just try two obvious places. */ 2441: 2442: src2 = replace_rtx (src2, reg, src1); 2443: split = 0; 2444: if (XEXP (src2, 0) == src1) 2445: split = &XEXP (src2, 0); 2446: else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e' 2447: && XEXP (XEXP (src2, 0), 0) == src1) 2448: split = &XEXP (XEXP (src2, 0), 0); 2449: 2450: if (split) 2451: { 2452: SUBST (XEXP (x, 0), src2); 2453: return split; 2454: } 2455: } 1.1.1.4 root 2456: 2457: /* If that didn't work, perhaps the first operand is complex and 2458: needs to be computed separately, so make a split point there. 2459: This will occur on machines that just support REG + CONST 2460: and have a constant moved through some previous computation. */ 2461: 2462: else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o' 2463: && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG 2464: && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0)))) 2465: == 'o'))) 2466: return &XEXP (XEXP (x, 0), 0); 1.1.1.3 root 2467: } 2468: break; 2469: 1.1 root 2470: case SET: 2471: #ifdef HAVE_cc0 2472: /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a 2473: ZERO_EXTRACT, the most likely reason why this doesn't match is that 2474: we need to put the operand into a register. So split at that 2475: point. */ 2476: 2477: if (SET_DEST (x) == cc0_rtx 2478: && GET_CODE (SET_SRC (x)) != COMPARE 2479: && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT 2480: && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o' 2481: && ! (GET_CODE (SET_SRC (x)) == SUBREG 2482: && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o')) 2483: return &SET_SRC (x); 2484: #endif 2485: 2486: /* See if we can split SET_SRC as it stands. */ 1.1.1.4 root 2487: split = find_split_point (&SET_SRC (x), insn); 1.1 root 2488: if (split && split != &SET_SRC (x)) 2489: return split; 2490: 2491: /* See if this is a bitfield assignment with everything constant. If 2492: so, this is an IOR of an AND, so split it into that. */ 2493: if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT 2494: && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))) 1.1.1.4 root 2495: <= HOST_BITS_PER_WIDE_INT) 1.1 root 2496: && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT 2497: && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT 2498: && GET_CODE (SET_SRC (x)) == CONST_INT 2499: && ((INTVAL (XEXP (SET_DEST (x), 1)) 2500: + INTVAL (XEXP (SET_DEST (x), 2))) 2501: <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))) 2502: && ! side_effects_p (XEXP (SET_DEST (x), 0))) 2503: { 2504: int pos = INTVAL (XEXP (SET_DEST (x), 2)); 2505: int len = INTVAL (XEXP (SET_DEST (x), 1)); 2506: int src = INTVAL (SET_SRC (x)); 2507: rtx dest = XEXP (SET_DEST (x), 0); 2508: enum machine_mode mode = GET_MODE (dest); 1.1.1.4 root 2509: unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1; 1.1 root 2510: 2511: #if BITS_BIG_ENDIAN 2512: pos = GET_MODE_BITSIZE (mode) - len - pos; 2513: #endif 2514: 2515: if (src == mask) 2516: SUBST (SET_SRC (x), 1.1.1.4 root 2517: gen_binary (IOR, mode, dest, GEN_INT (src << pos))); 1.1 root 2518: else 2519: SUBST (SET_SRC (x), 2520: gen_binary (IOR, mode, 2521: gen_binary (AND, mode, dest, 1.1.1.4 root 2522: GEN_INT (~ (mask << pos) 2523: & GET_MODE_MASK (mode))), 2524: GEN_INT (src << pos))); 1.1 root 2525: 2526: SUBST (SET_DEST (x), dest); 2527: 1.1.1.4 root 2528: split = find_split_point (&SET_SRC (x), insn); 1.1 root 2529: if (split && split != &SET_SRC (x)) 2530: return split; 2531: } 2532: 2533: /* Otherwise, see if this is an operation that we can split into two. 2534: If so, try to split that. */ 2535: code = GET_CODE (SET_SRC (x)); 2536: 2537: switch (code) 2538: { 1.1.1.4 root 2539: case AND: 2540: /* If we are AND'ing with a large constant that is only a single 2541: bit and the result is only being used in a context where we 2542: need to know if it is zero or non-zero, replace it with a bit 2543: extraction. This will avoid the large constant, which might 2544: have taken more than one insn to make. If the constant were 2545: not a valid argument to the AND but took only one insn to make, 2546: this is no worse, but if it took more than one insn, it will 2547: be better. */ 2548: 2549: if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT 2550: && GET_CODE (XEXP (SET_SRC (x), 0)) == REG 2551: && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7 2552: && GET_CODE (SET_DEST (x)) == REG 2553: && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0 2554: && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE) 2555: && XEXP (*split, 0) == SET_DEST (x) 2556: && XEXP (*split, 1) == const0_rtx) 2557: { 2558: SUBST (SET_SRC (x), 2559: make_extraction (GET_MODE (SET_DEST (x)), 2560: XEXP (SET_SRC (x), 0), 2561: pos, NULL_RTX, 1, 1, 0, 0)); 2562: return find_split_point (loc, insn); 2563: } 2564: break; 2565: 1.1 root 2566: case SIGN_EXTEND: 2567: inner = XEXP (SET_SRC (x), 0); 2568: pos = 0; 2569: len = GET_MODE_BITSIZE (GET_MODE (inner)); 2570: unsignedp = 0; 2571: break; 2572: 2573: case SIGN_EXTRACT: 2574: case ZERO_EXTRACT: 2575: if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT 2576: && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT) 2577: { 2578: inner = XEXP (SET_SRC (x), 0); 2579: len = INTVAL (XEXP (SET_SRC (x), 1)); 2580: pos = INTVAL (XEXP (SET_SRC (x), 2)); 2581: 2582: #if BITS_BIG_ENDIAN 2583: pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos; 2584: #endif 2585: unsignedp = (code == ZERO_EXTRACT); 2586: } 2587: break; 2588: } 2589: 2590: if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner))) 2591: { 2592: enum machine_mode mode = GET_MODE (SET_SRC (x)); 2593: 1.1.1.4 root 2594: /* For unsigned, we have a choice of a shift followed by an 2595: AND or two shifts. Use two shifts for field sizes where the 2596: constant might be too large. We assume here that we can 2597: always at least get 8-bit constants in an AND insn, which is 2598: true for every current RISC. */ 2599: 2600: if (unsignedp && len <= 8) 1.1 root 2601: { 2602: SUBST (SET_SRC (x), 2603: gen_rtx_combine 2604: (AND, mode, 2605: gen_rtx_combine (LSHIFTRT, mode, 2606: gen_lowpart_for_combine (mode, inner), 1.1.1.4 root 2607: GEN_INT (pos)), 2608: GEN_INT (((HOST_WIDE_INT) 1 << len) - 1))); 1.1 root 2609: 1.1.1.4 root 2610: split = find_split_point (&SET_SRC (x), insn); 1.1 root 2611: if (split && split != &SET_SRC (x)) 2612: return split; 2613: } 2614: else 2615: { 2616: SUBST (SET_SRC (x), 2617: gen_rtx_combine 1.1.1.4 root 2618: (unsignedp ? LSHIFTRT : ASHIFTRT, mode, 1.1 root 2619: gen_rtx_combine (ASHIFT, mode, 2620: gen_lowpart_for_combine (mode, inner), 1.1.1.4 root 2621: GEN_INT (GET_MODE_BITSIZE (mode) 2622: - len - pos)), 2623: GEN_INT (GET_MODE_BITSIZE (mode) - len))); 1.1 root 2624: 1.1.1.4 root 2625: split = find_split_point (&SET_SRC (x), insn); 1.1 root 2626: if (split && split != &SET_SRC (x)) 2627: return split; 2628: } 2629: } 2630: 2631: /* See if this is a simple operation with a constant as the second 2632: operand. It might be that this constant is out of range and hence 2633: could be used as a split point. */ 2634: if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2' 2635: || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c' 2636: || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<') 2637: && CONSTANT_P (XEXP (SET_SRC (x), 1)) 2638: && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o' 2639: || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG 2640: && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0)))) 2641: == 'o')))) 2642: return &XEXP (SET_SRC (x), 1); 2643: 2644: /* Finally, see if this is a simple operation with its first operand 2645: not in a register. The operation might require this operand in a 2646: register, so return it as a split point. We can always do this 2647: because if the first operand were another operation, we would have 2648: already found it as a split point. */ 2649: if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2' 2650: || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c' 2651: || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<' 2652: || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1') 2653: && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode)) 2654: return &XEXP (SET_SRC (x), 0); 2655: 2656: return 0; 2657: 2658: case AND: 2659: case IOR: 2660: /* We write NOR as (and (not A) (not B)), but if we don't have a NOR, 2661: it is better to write this as (not (ior A B)) so we can split it. 2662: Similarly for IOR. */ 2663: if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT) 2664: { 2665: SUBST (*loc, 2666: gen_rtx_combine (NOT, GET_MODE (x), 2667: gen_rtx_combine (code == IOR ? AND : IOR, 2668: GET_MODE (x), 2669: XEXP (XEXP (x, 0), 0), 2670: XEXP (XEXP (x, 1), 0)))); 1.1.1.4 root 2671: return find_split_point (loc, insn); 1.1 root 2672: } 2673: 2674: /* Many RISC machines have a large set of logical insns. If the 2675: second operand is a NOT, put it first so we will try to split the 2676: other operand first. */ 2677: if (GET_CODE (XEXP (x, 1)) == NOT) 2678: { 2679: rtx tem = XEXP (x, 0); 2680: SUBST (XEXP (x, 0), XEXP (x, 1)); 2681: SUBST (XEXP (x, 1), tem); 2682: } 2683: break; 2684: } 2685: 2686: /* Otherwise, select our actions depending on our rtx class. */ 2687: switch (GET_RTX_CLASS (code)) 2688: { 2689: case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */ 2690: case '3': 1.1.1.4 root 2691: split = find_split_point (&XEXP (x, 2), insn); 1.1 root 2692: if (split) 2693: return split; 2694: /* ... fall through ... */ 2695: case '2': 2696: case 'c': 2697: case '<': 1.1.1.4 root 2698: split = find_split_point (&XEXP (x, 1), insn); 1.1 root 2699: if (split) 2700: return split; 2701: /* ... fall through ... */ 2702: case '1': 2703: /* Some machines have (and (shift ...) ...) insns. If X is not 2704: an AND, but XEXP (X, 0) is, use it as our split point. */ 2705: if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND) 2706: return &XEXP (x, 0); 2707: 1.1.1.4 root 2708: split = find_split_point (&XEXP (x, 0), insn); 1.1 root 2709: if (split) 2710: return split; 2711: return loc; 2712: } 2713: 2714: /* Otherwise, we don't have a split point. */ 2715: return 0; 2716: } 2717: 2718: /* Throughout X, replace FROM with TO, and return the result. 2719: The result is TO if X is FROM; 2720: otherwise the result is X, but its contents may have been modified. 2721: If they were modified, a record was made in undobuf so that 2722: undo_all will (among other things) return X to its original state. 2723: 2724: If the number of changes necessary is too much to record to undo, 2725: the excess changes are not made, so the result is invalid. 2726: The changes already made can still be undone. 2727: undobuf.num_undo is incremented for such changes, so by testing that 2728: the caller can tell whether the result is valid. 2729: 2730: `n_occurrences' is incremented each time FROM is replaced. 2731: 2732: IN_DEST is non-zero if we are processing the SET_DEST of a SET. 2733: 1.1.1.2 root 2734: UNIQUE_COPY is non-zero if each substitution must be unique. We do this 1.1 root 2735: by copying if `n_occurrences' is non-zero. */ 2736: 2737: static rtx 2738: subst (x, from, to, in_dest, unique_copy) 2739: register rtx x, from, to; 2740: int in_dest; 2741: int unique_copy; 2742: { 1.1.1.7 ! root 2743: register enum rtx_code code = GET_CODE (x); ! 2744: enum machine_mode op0_mode = VOIDmode; 1.1 root 2745: register char *fmt; 2746: register int len, i; 1.1.1.7 ! root 2747: rtx new; 1.1 root 2748: 2749: /* Two expressions are equal if they are identical copies of a shared 2750: RTX or if they are both registers with the same register number 2751: and mode. */ 2752: 2753: #define COMBINE_RTX_EQUAL_P(X,Y) \ 2754: ((X) == (Y) \ 2755: || (GET_CODE (X) == REG && GET_CODE (Y) == REG \ 2756: && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y))) 2757: 2758: if (! in_dest && COMBINE_RTX_EQUAL_P (x, from)) 2759: { 2760: n_occurrences++; 2761: return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to); 2762: } 2763: 2764: /* If X and FROM are the same register but different modes, they will 2765: not have been seen as equal above. However, flow.c will make a 2766: LOG_LINKS entry for that case. If we do nothing, we will try to 2767: rerecognize our original insn and, when it succeeds, we will 2768: delete the feeding insn, which is incorrect. 2769: 2770: So force this insn not to match in this (rare) case. */ 2771: if (! in_dest && code == REG && GET_CODE (from) == REG 2772: && REGNO (x) == REGNO (from)) 2773: return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx); 2774: 2775: /* If this is an object, we are done unless it is a MEM or LO_SUM, both 2776: of which may contain things that can be combined. */ 2777: if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o') 2778: return x; 2779: 2780: /* It is possible to have a subexpression appear twice in the insn. 2781: Suppose that FROM is a register that appears within TO. 2782: Then, after that subexpression has been scanned once by `subst', 2783: the second time it is scanned, TO may be found. If we were 2784: to scan TO here, we would find FROM within it and create a 2785: self-referent rtl structure which is completely wrong. */ 2786: if (COMBINE_RTX_EQUAL_P (x, to)) 2787: return to; 2788: 2789: len = GET_RTX_LENGTH (code); 2790: fmt = GET_RTX_FORMAT (code); 2791: 2792: /* We don't need to process a SET_DEST that is a register, CC0, or PC, so 2793: set up to skip this common case. All other cases where we want to 2794: suppress replacing something inside a SET_SRC are handled via the 2795: IN_DEST operand. */ 2796: if (code == SET 2797: && (GET_CODE (SET_DEST (x)) == REG 2798: || GET_CODE (SET_DEST (x)) == CC0 2799: || GET_CODE (SET_DEST (x)) == PC)) 2800: fmt = "ie"; 2801: 2802: /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a constant. */ 2803: if (fmt[0] == 'e') 2804: op0_mode = GET_MODE (XEXP (x, 0)); 2805: 2806: for (i = 0; i < len; i++) 2807: { 2808: if (fmt[i] == 'E') 2809: { 2810: register int j; 2811: for (j = XVECLEN (x, i) - 1; j >= 0; j--) 2812: { 2813: if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from)) 2814: { 2815: new = (unique_copy && n_occurrences ? copy_rtx (to) : to); 2816: n_occurrences++; 2817: } 2818: else 2819: { 2820: new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy); 2821: 2822: /* If this substitution failed, this whole thing fails. */ 2823: if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx) 2824: return new; 2825: } 2826: 2827: SUBST (XVECEXP (x, i, j), new); 2828: } 2829: } 2830: else if (fmt[i] == 'e') 2831: { 2832: if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from)) 2833: { 1.1.1.6 root 2834: /* In general, don't install a subreg involving two modes not 2835: tieable. It can worsen register allocation, and can even 2836: make invalid reload insns, since the reg inside may need to 2837: be copied from in the outside mode, and that may be invalid 2838: if it is an fp reg copied in integer mode. 2839: 2840: We allow two exceptions to this: It is valid if it is inside 2841: another SUBREG and the mode of that SUBREG and the mode of 2842: the inside of TO is tieable and it is valid if X is a SET 2843: that copies FROM to CC0. */ 2844: if (GET_CODE (to) == SUBREG 2845: && ! MODES_TIEABLE_P (GET_MODE (to), 2846: GET_MODE (SUBREG_REG (to))) 2847: && ! (code == SUBREG 1.1.1.7 ! root 2848: && MODES_TIEABLE_P (GET_MODE (x), ! 2849: GET_MODE (SUBREG_REG (to)))) 1.1.1.6 root 2850: #ifdef HAVE_cc0 2851: && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx) 2852: #endif 2853: ) 2854: return gen_rtx (CLOBBER, VOIDmode, const0_rtx); 2855: 1.1 root 2856: new = (unique_copy && n_occurrences ? copy_rtx (to) : to); 2857: n_occurrences++; 2858: } 2859: else 2860: /* If we are in a SET_DEST, suppress most cases unless we 2861: have gone inside a MEM, in which case we want to 2862: simplify the address. We assume here that things that 2863: are actually part of the destination have their inner 2864: parts in the first expression. This is true for SUBREG, 2865: STRICT_LOW_PART, and ZERO_EXTRACT, which are the only 2866: things aside from REG and MEM that should appear in a 2867: SET_DEST. */ 2868: new = subst (XEXP (x, i), from, to, 2869: (((in_dest 2870: && (code == SUBREG || code == STRICT_LOW_PART 2871: || code == ZERO_EXTRACT)) 2872: || code == SET) 2873: && i == 0), unique_copy); 2874: 2875: /* If we found that we will have to reject this combination, 2876: indicate that by returning the CLOBBER ourselves, rather than 2877: an expression containing it. This will speed things up as 2878: well as prevent accidents where two CLOBBERs are considered 2879: to be equal, thus producing an incorrect simplification. */ 2880: 2881: if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx) 2882: return new; 2883: 2884: SUBST (XEXP (x, i), new); 2885: } 2886: } 2887: 1.1.1.7 ! root 2888: /* Try to simplify X. If the simplification changed the code, it is likely ! 2889: that further simplification will help, so loop, but limit the number ! 2890: of repetitions that will be performed. */ ! 2891: ! 2892: for (i = 0; i < 4; i++) ! 2893: { ! 2894: /* If X is sufficiently simple, don't bother trying to do anything ! 2895: with it. */ ! 2896: if (code != CONST_INT && code != REG && code != CLOBBER) ! 2897: x = simplify_rtx (x, op0_mode, i == 3, in_dest); 1.1.1.4 root 2898: 1.1.1.7 ! root 2899: if (GET_CODE (x) == code) ! 2900: break; 1.1.1.4 root 2901: 1.1.1.7 ! root 2902: code = GET_CODE (x); 1.1.1.4 root 2903: 1.1.1.7 ! root 2904: /* We no longer know the original mode of operand 0 since we ! 2905: have changed the form of X) */ ! 2906: op0_mode = VOIDmode; ! 2907: } ! 2908: ! 2909: return x; ! 2910: } ! 2911: ! 2912: /* Simplify X, a piece of RTL. We just operate on the expression at the ! 2913: outer level; call `subst' to simplify recursively. Return the new ! 2914: expression. ! 2915: ! 2916: OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this ! 2917: will be the iteration even if an expression with a code different from ! 2918: X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */ ! 2919: ! 2920: static rtx ! 2921: simplify_rtx (x, op0_mode, last, in_dest) ! 2922: rtx x; ! 2923: enum machine_mode op0_mode; ! 2924: int last; ! 2925: int in_dest; ! 2926: { ! 2927: enum rtx_code code = GET_CODE (x); ! 2928: enum machine_mode mode = GET_MODE (x); ! 2929: rtx temp; ! 2930: int i; 1.1.1.4 root 2931: 1.1 root 2932: /* If this is a commutative operation, put a constant last and a complex 2933: expression first. We don't need to do this for comparisons here. */ 2934: if (GET_RTX_CLASS (code) == 'c' 2935: && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT) 2936: || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o' 2937: && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o') 2938: || (GET_CODE (XEXP (x, 0)) == SUBREG 2939: && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o' 2940: && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'))) 2941: { 2942: temp = XEXP (x, 0); 2943: SUBST (XEXP (x, 0), XEXP (x, 1)); 2944: SUBST (XEXP (x, 1), temp); 2945: } 2946: 1.1.1.4 root 2947: /* If this is a PLUS, MINUS, or MULT, and the first operand is the 2948: sign extension of a PLUS with a constant, reverse the order of the sign 2949: extension and the addition. Note that this not the same as the original 2950: code, but overflow is undefined for signed values. Also note that the 2951: PLUS will have been partially moved "inside" the sign-extension, so that 2952: the first operand of X will really look like: 2953: (ashiftrt (plus (ashift A C4) C5) C4). 2954: We convert this to 2955: (plus (ashiftrt (ashift A C4) C2) C4) 2956: and replace the first operand of X with that expression. Later parts 2957: of this function may simplify the expression further. 2958: 2959: For example, if we start with (mult (sign_extend (plus A C1)) C2), 2960: we swap the SIGN_EXTEND and PLUS. Later code will apply the 2961: distributive law to produce (plus (mult (sign_extend X) C1) C3). 2962: 2963: We do this to simplify address expressions. */ 2964: 2965: if ((code == PLUS || code == MINUS || code == MULT) 2966: && GET_CODE (XEXP (x, 0)) == ASHIFTRT 2967: && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS 2968: && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT 2969: && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT 2970: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 2971: && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1) 2972: && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT 2973: && (temp = simplify_binary_operation (ASHIFTRT, mode, 2974: XEXP (XEXP (XEXP (x, 0), 0), 1), 2975: XEXP (XEXP (x, 0), 1))) != 0) 2976: { 2977: rtx new 2978: = simplify_shift_const (NULL_RTX, ASHIFT, mode, 2979: XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0), 2980: INTVAL (XEXP (XEXP (x, 0), 1))); 2981: 2982: new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new, 2983: INTVAL (XEXP (XEXP (x, 0), 1))); 2984: 2985: SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp)); 2986: } 2987: 2988: /* If this is a simple operation applied to an IF_THEN_ELSE, try 2989: applying it to the arms of the IF_THEN_ELSE. This often simplifies 1.1.1.7 ! root 2990: things. Check for cases where both arms are testing the same ! 2991: condition. 1.1.1.4 root 2992: 1.1.1.7 ! root 2993: Don't do anything if all operands are very simple. */ ! 2994: ! 2995: if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c' ! 2996: || GET_RTX_CLASS (code) == '<') ! 2997: && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o' ! 2998: && ! (GET_CODE (XEXP (x, 0)) == SUBREG ! 2999: && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) ! 3000: == 'o'))) ! 3001: || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o' ! 3002: && ! (GET_CODE (XEXP (x, 1)) == SUBREG ! 3003: && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1)))) ! 3004: == 'o'))))) ! 3005: || (GET_RTX_CLASS (code) == '1' ! 3006: && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o' ! 3007: && ! (GET_CODE (XEXP (x, 0)) == SUBREG ! 3008: && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) ! 3009: == 'o')))))) ! 3010: { ! 3011: rtx cond, true, false; ! 3012: ! 3013: cond = if_then_else_cond (x, &true, &false); ! 3014: if (cond != 0) ! 3015: { ! 3016: rtx cop1 = const0_rtx; ! 3017: enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1); ! 3018: ! 3019: /* Simplify the alternative arms; this may collapse the true and ! 3020: false arms to store-flag values. */ ! 3021: true = subst (true, pc_rtx, pc_rtx, 0, 0); ! 3022: false = subst (false, pc_rtx, pc_rtx, 0, 0); ! 3023: ! 3024: /* Restarting if we generate a store-flag expression will cause ! 3025: us to loop. Just drop through in this case. */ ! 3026: ! 3027: /* If the result values are STORE_FLAG_VALUE and zero, we can ! 3028: just make the comparison operation. */ ! 3029: if (true == const_true_rtx && false == const0_rtx) ! 3030: x = gen_binary (cond_code, mode, cond, cop1); ! 3031: else if (true == const0_rtx && false == const_true_rtx) ! 3032: x = gen_binary (reverse_condition (cond_code), mode, cond, cop1); ! 3033: ! 3034: /* Likewise, we can make the negate of a comparison operation ! 3035: if the result values are - STORE_FLAG_VALUE and zero. */ ! 3036: else if (GET_CODE (true) == CONST_INT ! 3037: && INTVAL (true) == - STORE_FLAG_VALUE ! 3038: && false == const0_rtx) ! 3039: x = gen_unary (NEG, mode, mode, ! 3040: gen_binary (cond_code, mode, cond, cop1)); ! 3041: else if (GET_CODE (false) == CONST_INT ! 3042: && INTVAL (false) == - STORE_FLAG_VALUE ! 3043: && true == const0_rtx) ! 3044: x = gen_unary (NEG, mode, mode, ! 3045: gen_binary (reverse_condition (cond_code), ! 3046: mode, cond, cop1)); ! 3047: else ! 3048: return gen_rtx (IF_THEN_ELSE, mode, ! 3049: gen_binary (cond_code, VOIDmode, cond, cop1), ! 3050: true, false); 1.1.1.4 root 3051: 1.1.1.7 ! root 3052: code = GET_CODE (x); ! 3053: op0_mode = VOIDmode; ! 3054: } 1.1.1.4 root 3055: } 3056: 1.1 root 3057: /* Try to fold this expression in case we have constants that weren't 3058: present before. */ 3059: temp = 0; 3060: switch (GET_RTX_CLASS (code)) 3061: { 3062: case '1': 3063: temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode); 3064: break; 3065: case '<': 3066: temp = simplify_relational_operation (code, op0_mode, 3067: XEXP (x, 0), XEXP (x, 1)); 1.1.1.4 root 3068: #ifdef FLOAT_STORE_FLAG_VALUE 3069: if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 3070: temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x)) 3071: : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x))); 3072: #endif 1.1 root 3073: break; 3074: case 'c': 3075: case '2': 3076: temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1)); 3077: break; 3078: case 'b': 3079: case '3': 3080: temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0), 3081: XEXP (x, 1), XEXP (x, 2)); 3082: break; 3083: } 3084: 3085: if (temp) 1.1.1.4 root 3086: x = temp, code = GET_CODE (temp); 1.1 root 3087: 3088: /* First see if we can apply the inverse distributive law. */ 1.1.1.6 root 3089: if (code == PLUS || code == MINUS 3090: || code == AND || code == IOR || code == XOR) 1.1 root 3091: { 3092: x = apply_distributive_law (x); 3093: code = GET_CODE (x); 3094: } 3095: 3096: /* If CODE is an associative operation not otherwise handled, see if we 3097: can associate some operands. This can win if they are constants or 3098: if they are logically related (i.e. (a & b) & a. */ 3099: if ((code == PLUS || code == MINUS 3100: || code == MULT || code == AND || code == IOR || code == XOR 3101: || code == DIV || code == UDIV 3102: || code == SMAX || code == SMIN || code == UMAX || code == UMIN) 1.1.1.6 root 3103: && INTEGRAL_MODE_P (mode)) 1.1 root 3104: { 3105: if (GET_CODE (XEXP (x, 0)) == code) 3106: { 3107: rtx other = XEXP (XEXP (x, 0), 0); 3108: rtx inner_op0 = XEXP (XEXP (x, 0), 1); 3109: rtx inner_op1 = XEXP (x, 1); 3110: rtx inner; 3111: 3112: /* Make sure we pass the constant operand if any as the second 3113: one if this is a commutative operation. */ 3114: if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c') 3115: { 3116: rtx tem = inner_op0; 3117: inner_op0 = inner_op1; 3118: inner_op1 = tem; 3119: } 3120: inner = simplify_binary_operation (code == MINUS ? PLUS 3121: : code == DIV ? MULT 3122: : code == UDIV ? MULT 3123: : code, 3124: mode, inner_op0, inner_op1); 3125: 3126: /* For commutative operations, try the other pair if that one 3127: didn't simplify. */ 3128: if (inner == 0 && GET_RTX_CLASS (code) == 'c') 3129: { 3130: other = XEXP (XEXP (x, 0), 1); 3131: inner = simplify_binary_operation (code, mode, 3132: XEXP (XEXP (x, 0), 0), 3133: XEXP (x, 1)); 3134: } 3135: 3136: if (inner) 1.1.1.7 ! root 3137: return gen_binary (code, mode, other, inner); 1.1 root 3138: } 3139: } 3140: 3141: /* A little bit of algebraic simplification here. */ 3142: switch (code) 3143: { 3144: case MEM: 3145: /* Ensure that our address has any ASHIFTs converted to MULT in case 3146: address-recognizing predicates are called later. */ 3147: temp = make_compound_operation (XEXP (x, 0), MEM); 3148: SUBST (XEXP (x, 0), temp); 3149: break; 3150: 3151: case SUBREG: 3152: /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG 3153: is paradoxical. If we can't do that safely, then it becomes 3154: something nonsensical so that this combination won't take place. */ 3155: 3156: if (GET_CODE (SUBREG_REG (x)) == MEM 3157: && (GET_MODE_SIZE (mode) 3158: <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))) 3159: { 3160: rtx inner = SUBREG_REG (x); 3161: int endian_offset = 0; 3162: /* Don't change the mode of the MEM 3163: if that would change the meaning of the address. */ 3164: if (MEM_VOLATILE_P (SUBREG_REG (x)) 3165: || mode_dependent_address_p (XEXP (inner, 0))) 3166: return gen_rtx (CLOBBER, mode, const0_rtx); 3167: 3168: #if BYTES_BIG_ENDIAN 3169: if (GET_MODE_SIZE (mode) < UNITS_PER_WORD) 3170: endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode); 3171: if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD) 3172: endian_offset -= UNITS_PER_WORD - GET_MODE_SIZE (GET_MODE (inner)); 3173: #endif 3174: /* Note if the plus_constant doesn't make a valid address 3175: then this combination won't be accepted. */ 3176: x = gen_rtx (MEM, mode, 3177: plus_constant (XEXP (inner, 0), 3178: (SUBREG_WORD (x) * UNITS_PER_WORD 3179: + endian_offset))); 3180: MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner); 3181: RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner); 3182: MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner); 3183: return x; 3184: } 3185: 3186: /* If we are in a SET_DEST, these other cases can't apply. */ 3187: if (in_dest) 3188: return x; 3189: 3190: /* Changing mode twice with SUBREG => just change it once, 3191: or not at all if changing back to starting mode. */ 3192: if (GET_CODE (SUBREG_REG (x)) == SUBREG) 3193: { 3194: if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x))) 3195: && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0) 3196: return SUBREG_REG (SUBREG_REG (x)); 3197: 3198: SUBST_INT (SUBREG_WORD (x), 3199: SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x))); 3200: SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x))); 3201: } 3202: 3203: /* SUBREG of a hard register => just change the register number 3204: and/or mode. If the hard register is not valid in that mode, 1.1.1.4 root 3205: suppress this combination. If the hard register is the stack, 3206: frame, or argument pointer, leave this as a SUBREG. */ 1.1 root 3207: 3208: if (GET_CODE (SUBREG_REG (x)) == REG 1.1.1.4 root 3209: && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER 3210: && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM 1.1.1.6 root 3211: #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 3212: && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM 3213: #endif 1.1.1.4 root 3214: #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM 3215: && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM 3216: #endif 3217: && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM) 1.1 root 3218: { 3219: if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x), 3220: mode)) 3221: return gen_rtx (REG, mode, 3222: REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)); 3223: else 3224: return gen_rtx (CLOBBER, mode, const0_rtx); 3225: } 3226: 3227: /* For a constant, try to pick up the part we want. Handle a full 1.1.1.3 root 3228: word and low-order part. Only do this if we are narrowing 3229: the constant; if it is being widened, we have no idea what 3230: the extra bits will have been set to. */ 1.1 root 3231: 3232: if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode 3233: && GET_MODE_SIZE (mode) == UNITS_PER_WORD 1.1.1.3 root 3234: && GET_MODE_SIZE (op0_mode) < UNITS_PER_WORD 1.1 root 3235: && GET_MODE_CLASS (mode) == MODE_INT) 3236: { 3237: temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x), 1.1.1.4 root 3238: 0, op0_mode); 1.1 root 3239: if (temp) 3240: return temp; 3241: } 3242: 1.1.1.5 root 3243: /* If we want a subreg of a constant, at offset 0, 3244: take the low bits. On a little-endian machine, that's 3245: always valid. On a big-endian machine, it's valid 3246: only if the constant's mode fits in one word. */ 1.1.1.3 root 3247: if (CONSTANT_P (SUBREG_REG (x)) && subreg_lowpart_p (x) 1.1.1.5 root 3248: && GET_MODE_SIZE (mode) < GET_MODE_SIZE (op0_mode) 3249: #if WORDS_BIG_ENDIAN 3250: && GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD 3251: #endif 3252: ) 1.1 root 3253: return gen_lowpart_for_combine (mode, SUBREG_REG (x)); 3254: 1.1.1.7 ! root 3255: /* A paradoxical SUBREG of a VOIDmode constant is the same constant, ! 3256: since we are saying that the high bits don't matter. */ ! 3257: if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode ! 3258: && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode)) ! 3259: return SUBREG_REG (x); ! 3260: ! 3261: /* Note that we cannot do any narrowing for non-constants since ! 3262: we might have been counting on using the fact that some bits were ! 3263: zero. We now do this in the SET. */ 1.1.1.4 root 3264: 1.1 root 3265: break; 3266: 3267: case NOT: 3268: /* (not (plus X -1)) can become (neg X). */ 3269: if (GET_CODE (XEXP (x, 0)) == PLUS 3270: && XEXP (XEXP (x, 0), 1) == constm1_rtx) 1.1.1.7 ! root 3271: return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0)); 1.1 root 3272: 3273: /* Similarly, (not (neg X)) is (plus X -1). */ 3274: if (GET_CODE (XEXP (x, 0)) == NEG) 1.1.1.7 ! root 3275: return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), ! 3276: constm1_rtx); 1.1 root 3277: 1.1.1.4 root 3278: /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */ 3279: if (GET_CODE (XEXP (x, 0)) == XOR 3280: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3281: && (temp = simplify_unary_operation (NOT, mode, 3282: XEXP (XEXP (x, 0), 1), 3283: mode)) != 0) 1.1.1.7 ! root 3284: return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp); 1.1.1.4 root 3285: 1.1 root 3286: /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands 3287: other than 1, but that is not valid. We could do a similar 3288: simplification for (not (lshiftrt C X)) where C is just the sign bit, 3289: but this doesn't seem common enough to bother with. */ 3290: if (GET_CODE (XEXP (x, 0)) == ASHIFT 3291: && XEXP (XEXP (x, 0), 0) == const1_rtx) 1.1.1.7 ! root 3292: return gen_rtx (ROTATE, mode, gen_unary (NOT, mode, mode, const1_rtx), ! 3293: XEXP (XEXP (x, 0), 1)); 1.1 root 3294: 3295: if (GET_CODE (XEXP (x, 0)) == SUBREG 3296: && subreg_lowpart_p (XEXP (x, 0)) 3297: && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) 3298: < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0))))) 3299: && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT 3300: && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx) 3301: { 3302: enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0))); 3303: 3304: x = gen_rtx (ROTATE, inner_mode, 1.1.1.7 ! root 3305: gen_unary (NOT, inner_mode, inner_mode, const1_rtx), 1.1 root 3306: XEXP (SUBREG_REG (XEXP (x, 0)), 1)); 1.1.1.7 ! root 3307: return gen_lowpart_for_combine (mode, x); 1.1 root 3308: } 3309: 3310: #if STORE_FLAG_VALUE == -1 3311: /* (not (comparison foo bar)) can be done by reversing the comparison 3312: code if valid. */ 3313: if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' 3314: && reversible_comparison_p (XEXP (x, 0))) 3315: return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))), 3316: mode, XEXP (XEXP (x, 0), 0), 3317: XEXP (XEXP (x, 0), 1)); 1.1.1.5 root 3318: 3319: /* (ashiftrt foo C) where C is the number of bits in FOO minus 1 3320: is (lt foo (const_int 0)), so we can perform the above 3321: simplification. */ 3322: 3323: if (XEXP (x, 1) == const1_rtx 3324: && GET_CODE (XEXP (x, 0)) == ASHIFTRT 3325: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3326: && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1) 3327: return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx); 1.1 root 3328: #endif 3329: 3330: /* Apply De Morgan's laws to reduce number of patterns for machines 3331: with negating logical insns (and-not, nand, etc.). If result has 3332: only one NOT, put it first, since that is how the patterns are 3333: coded. */ 3334: 3335: if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND) 3336: { 3337: rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1); 3338: 3339: if (GET_CODE (in1) == NOT) 3340: in1 = XEXP (in1, 0); 3341: else 3342: in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1); 3343: 3344: if (GET_CODE (in2) == NOT) 3345: in2 = XEXP (in2, 0); 3346: else if (GET_CODE (in2) == CONST_INT 1.1.1.4 root 3347: && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 3348: in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2)); 1.1 root 3349: else 3350: in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2); 3351: 3352: if (GET_CODE (in2) == NOT) 3353: { 3354: rtx tem = in2; 3355: in2 = in1; in1 = tem; 3356: } 3357: 1.1.1.7 ! root 3358: return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR, ! 3359: mode, in1, in2); 1.1 root 3360: } 3361: break; 3362: 3363: case NEG: 3364: /* (neg (plus X 1)) can become (not X). */ 3365: if (GET_CODE (XEXP (x, 0)) == PLUS 3366: && XEXP (XEXP (x, 0), 1) == const1_rtx) 1.1.1.7 ! root 3367: return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0)); 1.1 root 3368: 3369: /* Similarly, (neg (not X)) is (plus X 1). */ 3370: if (GET_CODE (XEXP (x, 0)) == NOT) 1.1.1.7 ! root 3371: return plus_constant (XEXP (XEXP (x, 0), 0), 1); 1.1 root 3372: 3373: /* (neg (minus X Y)) can become (minus Y X). */ 3374: if (GET_CODE (XEXP (x, 0)) == MINUS 1.1.1.6 root 3375: && (! FLOAT_MODE_P (mode) 1.1 root 3376: /* x-y != -(y-x) with IEEE floating point. */ 1.1.1.7 ! root 3377: || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT ! 3378: || flag_fast_math)) ! 3379: return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1), ! 3380: XEXP (XEXP (x, 0), 0)); 1.1 root 3381: 1.1.1.4 root 3382: /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */ 3383: if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx 1.1.1.5 root 3384: && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1) 1.1.1.7 ! root 3385: return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx); 1.1.1.4 root 3386: 1.1 root 3387: /* NEG commutes with ASHIFT since it is multiplication. Only do this 3388: if we can then eliminate the NEG (e.g., 3389: if the operand is a constant). */ 3390: 3391: if (GET_CODE (XEXP (x, 0)) == ASHIFT) 3392: { 3393: temp = simplify_unary_operation (NEG, mode, 3394: XEXP (XEXP (x, 0), 0), mode); 3395: if (temp) 3396: { 3397: SUBST (XEXP (XEXP (x, 0), 0), temp); 3398: return XEXP (x, 0); 3399: } 3400: } 3401: 3402: temp = expand_compound_operation (XEXP (x, 0)); 3403: 3404: /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be 3405: replaced by (lshiftrt X C). This will convert 3406: (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */ 3407: 3408: if (GET_CODE (temp) == ASHIFTRT 3409: && GET_CODE (XEXP (temp, 1)) == CONST_INT 3410: && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1) 1.1.1.7 ! root 3411: return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0), ! 3412: INTVAL (XEXP (temp, 1))); 1.1 root 3413: 1.1.1.5 root 3414: /* If X has only a single bit that might be nonzero, say, bit I, convert 1.1 root 3415: (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of 3416: MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to 3417: (sign_extract X 1 Y). But only do this if TEMP isn't a register 3418: or a SUBREG of one since we'd be making the expression more 3419: complex if it was just a register. */ 3420: 3421: if (GET_CODE (temp) != REG 3422: && ! (GET_CODE (temp) == SUBREG 3423: && GET_CODE (SUBREG_REG (temp)) == REG) 1.1.1.5 root 3424: && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0) 1.1 root 3425: { 3426: rtx temp1 = simplify_shift_const 1.1.1.4 root 3427: (NULL_RTX, ASHIFTRT, mode, 3428: simplify_shift_const (NULL_RTX, ASHIFT, mode, temp, 1.1 root 3429: GET_MODE_BITSIZE (mode) - 1 - i), 3430: GET_MODE_BITSIZE (mode) - 1 - i); 3431: 3432: /* If all we did was surround TEMP with the two shifts, we 3433: haven't improved anything, so don't use it. Otherwise, 3434: we are better off with TEMP1. */ 3435: if (GET_CODE (temp1) != ASHIFTRT 3436: || GET_CODE (XEXP (temp1, 0)) != ASHIFT 3437: || XEXP (XEXP (temp1, 0), 0) != temp) 1.1.1.7 ! root 3438: return temp1; 1.1 root 3439: } 3440: break; 3441: 3442: case FLOAT_TRUNCATE: 3443: /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */ 3444: if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND 3445: && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode) 3446: return XEXP (XEXP (x, 0), 0); 1.1.1.7 ! root 3447: ! 3448: /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is ! 3449: (OP:SF foo:SF) if OP is NEG or ABS. */ ! 3450: if ((GET_CODE (XEXP (x, 0)) == ABS ! 3451: || GET_CODE (XEXP (x, 0)) == NEG) ! 3452: && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND ! 3453: && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode) ! 3454: return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode, ! 3455: XEXP (XEXP (XEXP (x, 0), 0), 0)); ! 3456: ! 3457: /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0)) ! 3458: is (float_truncate:SF x). */ ! 3459: if (GET_CODE (XEXP (x, 0)) == SUBREG ! 3460: && subreg_lowpart_p (XEXP (x, 0)) ! 3461: && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE) ! 3462: return SUBREG_REG (XEXP (x, 0)); 1.1 root 3463: break; 3464: 3465: #ifdef HAVE_cc0 3466: case COMPARE: 3467: /* Convert (compare FOO (const_int 0)) to FOO unless we aren't 3468: using cc0, in which case we want to leave it as a COMPARE 3469: so we can distinguish it from a register-register-copy. */ 3470: if (XEXP (x, 1) == const0_rtx) 3471: return XEXP (x, 0); 3472: 3473: /* In IEEE floating point, x-0 is not the same as x. */ 3474: if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT 1.1.1.7 ! root 3475: || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))) ! 3476: || flag_fast_math) 1.1 root 3477: && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0)))) 3478: return XEXP (x, 0); 3479: break; 3480: #endif 3481: 3482: case CONST: 3483: /* (const (const X)) can become (const X). Do it this way rather than 3484: returning the inner CONST since CONST can be shared with a 3485: REG_EQUAL note. */ 3486: if (GET_CODE (XEXP (x, 0)) == CONST) 3487: SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); 3488: break; 3489: 3490: #ifdef HAVE_lo_sum 3491: case LO_SUM: 3492: /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we 3493: can add in an offset. find_split_point will split this address up 3494: again if it doesn't match. */ 3495: if (GET_CODE (XEXP (x, 0)) == HIGH 3496: && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))) 3497: return XEXP (x, 1); 3498: break; 3499: #endif 3500: 3501: case PLUS: 3502: /* If we have (plus (plus (A const) B)), associate it so that CONST is 3503: outermost. That's because that's the way indexed addresses are 3504: supposed to appear. This code used to check many more cases, but 3505: they are now checked elsewhere. */ 3506: if (GET_CODE (XEXP (x, 0)) == PLUS 3507: && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1))) 3508: return gen_binary (PLUS, mode, 3509: gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), 3510: XEXP (x, 1)), 3511: XEXP (XEXP (x, 0), 1)); 3512: 3513: /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>) 3514: when c is (const_int (pow2 + 1) / 2) is a sign extension of a 3515: bit-field and can be replaced by either a sign_extend or a 3516: sign_extract. The `and' may be a zero_extend. */ 3517: if (GET_CODE (XEXP (x, 0)) == XOR 3518: && GET_CODE (XEXP (x, 1)) == CONST_INT 3519: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3520: && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1)) 3521: && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0 1.1.1.4 root 3522: && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 1.1 root 3523: && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND 3524: && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT 3525: && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) 1.1.1.4 root 3526: == ((HOST_WIDE_INT) 1 << (i + 1)) - 1)) 1.1 root 3527: || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND 3528: && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0))) 3529: == i + 1)))) 1.1.1.7 ! root 3530: return simplify_shift_const ! 3531: (NULL_RTX, ASHIFTRT, mode, ! 3532: simplify_shift_const (NULL_RTX, ASHIFT, mode, ! 3533: XEXP (XEXP (XEXP (x, 0), 0), 0), ! 3534: GET_MODE_BITSIZE (mode) - (i + 1)), ! 3535: GET_MODE_BITSIZE (mode) - (i + 1)); 1.1 root 3536: 1.1.1.6 root 3537: /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if 3538: C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE 3539: is 1. This produces better code than the alternative immediately 3540: below. */ 3541: if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' 3542: && reversible_comparison_p (XEXP (x, 0)) 3543: && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx) 3544: || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))) 1.1.1.7 ! root 3545: return ! 3546: gen_unary (NEG, mode, mode, ! 3547: gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))), ! 3548: mode, XEXP (XEXP (x, 0), 0), ! 3549: XEXP (XEXP (x, 0), 1))); 1.1.1.6 root 3550: 3551: /* If only the low-order bit of X is possibly nonzero, (plus x -1) 1.1 root 3552: can become (ashiftrt (ashift (xor x 1) C) C) where C is 3553: the bitsize of the mode - 1. This allows simplification of 3554: "a = (b & 8) == 0;" */ 3555: if (XEXP (x, 1) == constm1_rtx 3556: && GET_CODE (XEXP (x, 0)) != REG 3557: && ! (GET_CODE (XEXP (x,0)) == SUBREG 3558: && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG) 1.1.1.5 root 3559: && nonzero_bits (XEXP (x, 0), mode) == 1) 1.1.1.7 ! root 3560: return simplify_shift_const (NULL_RTX, ASHIFTRT, mode, ! 3561: simplify_shift_const (NULL_RTX, ASHIFT, mode, ! 3562: gen_rtx_combine (XOR, mode, ! 3563: XEXP (x, 0), const1_rtx), ! 3564: GET_MODE_BITSIZE (mode) - 1), ! 3565: GET_MODE_BITSIZE (mode) - 1); 1.1.1.4 root 3566: 3567: /* If we are adding two things that have no bits in common, convert 3568: the addition into an IOR. This will often be further simplified, 3569: for example in cases like ((a & 1) + (a & 2)), which can 3570: become a & 3. */ 3571: 3572: if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 1.1.1.5 root 3573: && (nonzero_bits (XEXP (x, 0), mode) 3574: & nonzero_bits (XEXP (x, 1), mode)) == 0) 1.1.1.7 ! root 3575: return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1)); 1.1 root 3576: break; 3577: 3578: case MINUS: 1.1.1.6 root 3579: #if STORE_FLAG_VALUE == 1 3580: /* (minus 1 (comparison foo bar)) can be done by reversing the comparison 3581: code if valid. */ 3582: if (XEXP (x, 0) == const1_rtx 3583: && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<' 3584: && reversible_comparison_p (XEXP (x, 1))) 3585: return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))), 3586: mode, XEXP (XEXP (x, 1), 0), 3587: XEXP (XEXP (x, 1), 1)); 3588: #endif 3589: 1.1 root 3590: /* (minus <foo> (and <foo> (const_int -pow2))) becomes 3591: (and <foo> (const_int pow2-1)) */ 3592: if (GET_CODE (XEXP (x, 1)) == AND 3593: && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT 3594: && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0 3595: && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) 1.1.1.7 ! root 3596: return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0), ! 3597: - INTVAL (XEXP (XEXP (x, 1), 1)) - 1); ! 3598: ! 3599: /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for ! 3600: integers. */ ! 3601: if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode)) ! 3602: return gen_binary (MINUS, mode, ! 3603: gen_binary (MINUS, mode, XEXP (x, 0), ! 3604: XEXP (XEXP (x, 1), 0)), ! 3605: XEXP (XEXP (x, 1), 1)); 1.1 root 3606: break; 3607: 3608: case MULT: 3609: /* If we have (mult (plus A B) C), apply the distributive law and then 3610: the inverse distributive law to see if things simplify. This 3611: occurs mostly in addresses, often when unrolling loops. */ 3612: 3613: if (GET_CODE (XEXP (x, 0)) == PLUS) 3614: { 3615: x = apply_distributive_law 3616: (gen_binary (PLUS, mode, 3617: gen_binary (MULT, mode, 3618: XEXP (XEXP (x, 0), 0), XEXP (x, 1)), 3619: gen_binary (MULT, mode, 3620: XEXP (XEXP (x, 0), 1), XEXP (x, 1)))); 3621: 3622: if (GET_CODE (x) != MULT) 1.1.1.7 ! root 3623: return x; 1.1 root 3624: } 3625: break; 3626: 3627: case UDIV: 3628: /* If this is a divide by a power of two, treat it as a shift if 3629: its first operand is a shift. */ 3630: if (GET_CODE (XEXP (x, 1)) == CONST_INT 3631: && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0 3632: && (GET_CODE (XEXP (x, 0)) == ASHIFT 3633: || GET_CODE (XEXP (x, 0)) == LSHIFTRT 3634: || GET_CODE (XEXP (x, 0)) == ASHIFTRT 3635: || GET_CODE (XEXP (x, 0)) == ROTATE 3636: || GET_CODE (XEXP (x, 0)) == ROTATERT)) 1.1.1.7 ! root 3637: return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i); 1.1 root 3638: break; 3639: 3640: case EQ: case NE: 3641: case GT: case GTU: case GE: case GEU: 3642: case LT: case LTU: case LE: case LEU: 3643: /* If the first operand is a condition code, we can't do anything 3644: with it. */ 3645: if (GET_CODE (XEXP (x, 0)) == COMPARE 3646: || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC 3647: #ifdef HAVE_cc0 3648: && XEXP (x, 0) != cc0_rtx 3649: #endif 3650: )) 3651: { 3652: rtx op0 = XEXP (x, 0); 3653: rtx op1 = XEXP (x, 1); 3654: enum rtx_code new_code; 3655: 3656: if (GET_CODE (op0) == COMPARE) 3657: op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); 3658: 3659: /* Simplify our comparison, if possible. */ 3660: new_code = simplify_comparison (code, &op0, &op1); 3661: 3662: #if STORE_FLAG_VALUE == 1 3663: /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X 1.1.1.5 root 3664: if only the low-order bit is possibly nonzero in X (such as when 1.1.1.6 root 3665: X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to 3666: (xor X 1) or (minus 1 X); we use the former. Finally, if X is 3667: known to be either 0 or -1, NE becomes a NEG and EQ becomes 3668: (plus X 1). 3669: 3670: Remove any ZERO_EXTRACT we made when thinking this was a 3671: comparison. It may now be simpler to use, e.g., an AND. If a 3672: ZERO_EXTRACT is indeed appropriate, it will be placed back by 3673: the call to make_compound_operation in the SET case. */ 3674: 1.1.1.3 root 3675: if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 1.1 root 3676: && op1 == const0_rtx 1.1.1.6 root 3677: && nonzero_bits (op0, mode) == 1) 1.1.1.5 root 3678: return gen_lowpart_for_combine (mode, 3679: expand_compound_operation (op0)); 1.1.1.6 root 3680: 3681: else if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 3682: && op1 == const0_rtx 3683: && (num_sign_bit_copies (op0, mode) 3684: == GET_MODE_BITSIZE (mode))) 3685: { 3686: op0 = expand_compound_operation (op0); 1.1.1.7 ! root 3687: return gen_unary (NEG, mode, mode, ! 3688: gen_lowpart_for_combine (mode, op0)); 1.1.1.6 root 3689: } 3690: 1.1.1.3 root 3691: else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 1.1 root 3692: && op1 == const0_rtx 1.1.1.6 root 3693: && nonzero_bits (op0, mode) == 1) 1.1.1.5 root 3694: { 3695: op0 = expand_compound_operation (op0); 1.1.1.7 ! root 3696: return gen_binary (XOR, mode, ! 3697: gen_lowpart_for_combine (mode, op0), ! 3698: const1_rtx); 1.1.1.6 root 3699: } 1.1.1.5 root 3700: 1.1.1.6 root 3701: else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 3702: && op1 == const0_rtx 3703: && (num_sign_bit_copies (op0, mode) 3704: == GET_MODE_BITSIZE (mode))) 3705: { 3706: op0 = expand_compound_operation (op0); 1.1.1.7 ! root 3707: return plus_constant (gen_lowpart_for_combine (mode, op0), 1); 1.1.1.5 root 3708: } 1.1 root 3709: #endif 3710: 3711: #if STORE_FLAG_VALUE == -1 1.1.1.6 root 3712: /* If STORE_FLAG_VALUE is -1, we have cases similar to 3713: those above. */ 1.1.1.3 root 3714: if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 1.1 root 3715: && op1 == const0_rtx 1.1.1.6 root 3716: && (num_sign_bit_copies (op0, mode) 3717: == GET_MODE_BITSIZE (mode))) 3718: return gen_lowpart_for_combine (mode, 3719: expand_compound_operation (op0)); 3720: 3721: else if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 3722: && op1 == const0_rtx 3723: && nonzero_bits (op0, mode) == 1) 3724: { 3725: op0 = expand_compound_operation (op0); 1.1.1.7 ! root 3726: return gen_unary (NEG, mode, mode, ! 3727: gen_lowpart_for_combine (mode, op0)); 1.1.1.6 root 3728: } 3729: 3730: else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 3731: && op1 == const0_rtx 3732: && (num_sign_bit_copies (op0, mode) 3733: == GET_MODE_BITSIZE (mode))) 1.1 root 3734: { 1.1.1.5 root 3735: op0 = expand_compound_operation (op0); 1.1.1.7 ! root 3736: return gen_unary (NOT, mode, mode, ! 3737: gen_lowpart_for_combine (mode, op0)); 1.1.1.6 root 3738: } 3739: 3740: /* If X is 0/1, (eq X 0) is X-1. */ 3741: else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT 3742: && op1 == const0_rtx 3743: && nonzero_bits (op0, mode) == 1) 3744: { 3745: op0 = expand_compound_operation (op0); 1.1.1.7 ! root 3746: return plus_constant (gen_lowpart_for_combine (mode, op0), -1); 1.1 root 3747: } 3748: #endif 3749: 3750: /* If STORE_FLAG_VALUE says to just test the sign bit and X has just 1.1.1.5 root 3751: one bit that might be nonzero, we can convert (ne x 0) to 3752: (ashift x c) where C puts the bit in the sign bit. Remove any 3753: AND with STORE_FLAG_VALUE when we are done, since we are only 3754: going to test the sign bit. */ 1.1.1.3 root 3755: if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 1.1.1.4 root 3756: && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 3757: && (STORE_FLAG_VALUE 3758: == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)) 1.1 root 3759: && op1 == const0_rtx 3760: && mode == GET_MODE (op0) 1.1.1.6 root 3761: && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0) 1.1 root 3762: { 1.1.1.5 root 3763: x = simplify_shift_const (NULL_RTX, ASHIFT, mode, 3764: expand_compound_operation (op0), 1.1 root 3765: GET_MODE_BITSIZE (mode) - 1 - i); 3766: if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx) 3767: return XEXP (x, 0); 3768: else 3769: return x; 3770: } 3771: 3772: /* If the code changed, return a whole new comparison. */ 3773: if (new_code != code) 3774: return gen_rtx_combine (new_code, mode, op0, op1); 3775: 3776: /* Otherwise, keep this operation, but maybe change its operands. 3777: This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */ 3778: SUBST (XEXP (x, 0), op0); 3779: SUBST (XEXP (x, 1), op1); 3780: } 3781: break; 3782: 3783: case IF_THEN_ELSE: 1.1.1.7 ! root 3784: return simplify_if_then_else (x); 1.1.1.4 root 3785: 1.1.1.7 ! root 3786: case ZERO_EXTRACT: ! 3787: case SIGN_EXTRACT: ! 3788: case ZERO_EXTEND: ! 3789: case SIGN_EXTEND: ! 3790: /* If we are processing SET_DEST, we are done. */ ! 3791: if (in_dest) ! 3792: return x; 1.1.1.4 root 3793: 1.1.1.7 ! root 3794: return expand_compound_operation (x); 1.1.1.4 root 3795: 1.1.1.7 ! root 3796: case SET: ! 3797: return simplify_set (x); 1.1.1.4 root 3798: 1.1.1.7 ! root 3799: case AND: ! 3800: case IOR: ! 3801: case XOR: ! 3802: return simplify_logical (x, last); 1.1.1.4 root 3803: 1.1.1.7 ! root 3804: case ABS: ! 3805: /* (abs (neg <foo>)) -> (abs <foo>) */ ! 3806: if (GET_CODE (XEXP (x, 0)) == NEG) ! 3807: SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); 1.1.1.4 root 3808: 1.1.1.7 ! root 3809: /* If operand is something known to be positive, ignore the ABS. */ ! 3810: if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS ! 3811: || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) ! 3812: <= HOST_BITS_PER_WIDE_INT) ! 3813: && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0))) ! 3814: & ((HOST_WIDE_INT) 1 ! 3815: << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))) ! 3816: == 0))) ! 3817: return XEXP (x, 0); 1.1.1.4 root 3818: 3819: 1.1.1.7 ! root 3820: /* If operand is known to be only -1 or 0, convert ABS to NEG. */ ! 3821: if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode)) ! 3822: return gen_rtx_combine (NEG, mode, XEXP (x, 0)); 1.1.1.4 root 3823: 1.1.1.7 ! root 3824: break; 1.1.1.4 root 3825: 1.1.1.7 ! root 3826: case FFS: ! 3827: /* (ffs (*_extend <X>)) = (ffs <X>) */ ! 3828: if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND ! 3829: || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND) ! 3830: SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); ! 3831: break; 1.1.1.6 root 3832: 1.1.1.7 ! root 3833: case FLOAT: ! 3834: /* (float (sign_extend <X>)) = (float <X>). */ ! 3835: if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) ! 3836: SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); 1.1 root 3837: break; 3838: 1.1.1.7 ! root 3839: case ASHIFT: ! 3840: case LSHIFTRT: ! 3841: case ASHIFTRT: ! 3842: case ROTATE: ! 3843: case ROTATERT: ! 3844: /* If this is a shift by a constant amount, simplify it. */ ! 3845: if (GET_CODE (XEXP (x, 1)) == CONST_INT) ! 3846: return simplify_shift_const (x, code, mode, XEXP (x, 0), ! 3847: INTVAL (XEXP (x, 1))); ! 3848: ! 3849: #ifdef SHIFT_COUNT_TRUNCATED ! 3850: else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG) ! 3851: SUBST (XEXP (x, 1), ! 3852: force_to_mode (XEXP (x, 1), GET_MODE (x), ! 3853: ((HOST_WIDE_INT) 1 ! 3854: << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x)))) ! 3855: - 1, ! 3856: NULL_RTX, 0)); ! 3857: #endif ! 3858: 1.1 root 3859: break; 1.1.1.7 ! root 3860: } 1.1 root 3861: 1.1.1.7 ! root 3862: return x; ! 3863: } ! 3864: ! 3865: /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */ ! 3866: ! 3867: static rtx ! 3868: simplify_if_then_else (x) ! 3869: rtx x; ! 3870: { ! 3871: enum machine_mode mode = GET_MODE (x); ! 3872: rtx cond = XEXP (x, 0); ! 3873: rtx true = XEXP (x, 1); ! 3874: rtx false = XEXP (x, 2); ! 3875: enum rtx_code true_code = GET_CODE (cond); ! 3876: int comparison_p = GET_RTX_CLASS (true_code) == '<'; ! 3877: rtx temp; ! 3878: int i; ! 3879: ! 3880: /* Simplify storing of the truth value. */ ! 3881: if (comparison_p && true == const_true_rtx && false == const0_rtx) ! 3882: return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1)); ! 3883: ! 3884: /* Also when the truth value has to be reversed. */ ! 3885: if (comparison_p && reversible_comparison_p (cond) ! 3886: && true == const0_rtx && false == const_true_rtx) ! 3887: return gen_binary (reverse_condition (true_code), ! 3888: mode, XEXP (cond, 0), XEXP (cond, 1)); ! 3889: ! 3890: /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used ! 3891: in it is being compared against certain values. Get the true and false ! 3892: comparisons and see if that says anything about the value of each arm. */ ! 3893: ! 3894: if (comparison_p && reversible_comparison_p (cond) ! 3895: && GET_CODE (XEXP (cond, 0)) == REG) ! 3896: { ! 3897: HOST_WIDE_INT nzb; ! 3898: rtx from = XEXP (cond, 0); ! 3899: enum rtx_code false_code = reverse_condition (true_code); ! 3900: rtx true_val = XEXP (cond, 1); ! 3901: rtx false_val = true_val; ! 3902: int swapped = 0; ! 3903: ! 3904: /* If FALSE_CODE is EQ, swap the codes and arms. */ ! 3905: ! 3906: if (false_code == EQ) ! 3907: { ! 3908: swapped = 1, true_code = EQ, false_code = NE; ! 3909: temp = true, true = false, false = temp; ! 3910: } ! 3911: ! 3912: /* If we are comparing against zero and the expression being tested has ! 3913: only a single bit that might be nonzero, that is its value when it is ! 3914: not equal to zero. Similarly if it is known to be -1 or 0. */ ! 3915: ! 3916: if (true_code == EQ && true_val == const0_rtx ! 3917: && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0) ! 3918: false_code = EQ, false_val = GEN_INT (nzb); ! 3919: else if (true_code == EQ && true_val == const0_rtx ! 3920: && (num_sign_bit_copies (from, GET_MODE (from)) ! 3921: == GET_MODE_BITSIZE (GET_MODE (from)))) ! 3922: false_code = EQ, false_val = constm1_rtx; ! 3923: ! 3924: /* Now simplify an arm if we know the value of the register in the ! 3925: branch and it is used in the arm. Be careful due to the potential ! 3926: of locally-shared RTL. */ ! 3927: ! 3928: if (reg_mentioned_p (from, true)) ! 3929: true = subst (known_cond (copy_rtx (true), true_code, from, true_val), ! 3930: pc_rtx, pc_rtx, 0, 0); ! 3931: if (reg_mentioned_p (from, false)) ! 3932: false = subst (known_cond (copy_rtx (false), false_code, ! 3933: from, false_val), ! 3934: pc_rtx, pc_rtx, 0, 0); ! 3935: ! 3936: SUBST (XEXP (x, 1), swapped ? false : true); ! 3937: SUBST (XEXP (x, 2), swapped ? true : false); ! 3938: ! 3939: true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond); ! 3940: } ! 3941: ! 3942: /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be ! 3943: reversed, do so to avoid needing two sets of patterns for ! 3944: subtract-and-branch insns. Similarly if we have a constant in the true ! 3945: arm, the false arm is the same as the first operand of the comparison, or ! 3946: the false arm is more complicated than the true arm. */ ! 3947: ! 3948: if (comparison_p && reversible_comparison_p (cond) ! 3949: && (true == pc_rtx ! 3950: || (CONSTANT_P (true) ! 3951: && GET_CODE (false) != CONST_INT && false != pc_rtx) ! 3952: || true == const0_rtx ! 3953: || (GET_RTX_CLASS (GET_CODE (true)) == 'o' ! 3954: && GET_RTX_CLASS (GET_CODE (false)) != 'o') ! 3955: || (GET_CODE (true) == SUBREG ! 3956: && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o' ! 3957: && GET_RTX_CLASS (GET_CODE (false)) != 'o') ! 3958: || reg_mentioned_p (true, false) ! 3959: || rtx_equal_p (false, XEXP (cond, 0)))) ! 3960: { ! 3961: true_code = reverse_condition (true_code); ! 3962: SUBST (XEXP (x, 0), ! 3963: gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0), ! 3964: XEXP (cond, 1))); ! 3965: ! 3966: SUBST (XEXP (x, 1), false); ! 3967: SUBST (XEXP (x, 2), true); ! 3968: ! 3969: temp = true, true = false, false = temp, cond = XEXP (x, 0); ! 3970: } ! 3971: ! 3972: /* If the two arms are identical, we don't need the comparison. */ ! 3973: ! 3974: if (rtx_equal_p (true, false) && ! side_effects_p (cond)) ! 3975: return true; ! 3976: ! 3977: /* Look for cases where we have (abs x) or (neg (abs X)). */ ! 3978: ! 3979: if (GET_MODE_CLASS (mode) == MODE_INT ! 3980: && GET_CODE (false) == NEG ! 3981: && rtx_equal_p (true, XEXP (false, 0)) ! 3982: && comparison_p ! 3983: && rtx_equal_p (true, XEXP (cond, 0)) ! 3984: && ! side_effects_p (true)) ! 3985: switch (true_code) ! 3986: { ! 3987: case GT: ! 3988: case GE: ! 3989: return gen_unary (ABS, mode, mode, true); ! 3990: case LT: ! 3991: case LE: ! 3992: return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true)); ! 3993: } ! 3994: ! 3995: /* Look for MIN or MAX. */ ! 3996: ! 3997: if ((! FLOAT_MODE_P (mode) | flag_fast_math) ! 3998: && comparison_p ! 3999: && rtx_equal_p (XEXP (cond, 0), true) ! 4000: && rtx_equal_p (XEXP (cond, 1), false) ! 4001: && ! side_effects_p (cond)) ! 4002: switch (true_code) ! 4003: { ! 4004: case GE: ! 4005: case GT: ! 4006: return gen_binary (SMAX, mode, true, false); ! 4007: case LE: ! 4008: case LT: ! 4009: return gen_binary (SMIN, mode, true, false); ! 4010: case GEU: ! 4011: case GTU: ! 4012: return gen_binary (UMAX, mode, true, false); ! 4013: case LEU: ! 4014: case LTU: ! 4015: return gen_binary (UMIN, mode, true, false); ! 4016: } ! 4017: ! 4018: #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1 ! 4019: ! 4020: /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its ! 4021: second operand is zero, this can be done as (OP Z (mult COND C2)) where ! 4022: C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or ! 4023: SIGN_EXTEND as long as Z is already extended (so we don't destroy it). ! 4024: We can do this kind of thing in some cases when STORE_FLAG_VALUE is ! 4025: neither of the above, but it isn't worth checking for. */ ! 4026: ! 4027: if (comparison_p && mode != VOIDmode && ! side_effects_p (x)) ! 4028: { ! 4029: rtx t = make_compound_operation (true, SET); ! 4030: rtx f = make_compound_operation (false, SET); ! 4031: rtx cond_op0 = XEXP (cond, 0); ! 4032: rtx cond_op1 = XEXP (cond, 1); ! 4033: enum rtx_code op, extend_op = NIL; ! 4034: enum machine_mode m = mode; ! 4035: rtx z = 0, c1; ! 4036: ! 4037: if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS ! 4038: || GET_CODE (t) == IOR || GET_CODE (t) == XOR ! 4039: || GET_CODE (t) == ASHIFT ! 4040: || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT) ! 4041: && rtx_equal_p (XEXP (t, 0), f)) ! 4042: c1 = XEXP (t, 1), op = GET_CODE (t), z = f; ! 4043: ! 4044: /* If an identity-zero op is commutative, check whether there ! 4045: would be a match if we swapped the operands. */ ! 4046: else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR ! 4047: || GET_CODE (t) == XOR) ! 4048: && rtx_equal_p (XEXP (t, 1), f)) ! 4049: c1 = XEXP (t, 0), op = GET_CODE (t), z = f; ! 4050: else if (GET_CODE (t) == SIGN_EXTEND ! 4051: && (GET_CODE (XEXP (t, 0)) == PLUS ! 4052: || GET_CODE (XEXP (t, 0)) == MINUS ! 4053: || GET_CODE (XEXP (t, 0)) == IOR ! 4054: || GET_CODE (XEXP (t, 0)) == XOR ! 4055: || GET_CODE (XEXP (t, 0)) == ASHIFT ! 4056: || GET_CODE (XEXP (t, 0)) == LSHIFTRT ! 4057: || GET_CODE (XEXP (t, 0)) == ASHIFTRT) ! 4058: && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG ! 4059: && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) ! 4060: && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) ! 4061: && (num_sign_bit_copies (f, GET_MODE (f)) ! 4062: > (GET_MODE_BITSIZE (mode) ! 4063: - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0)))))) ! 4064: { ! 4065: c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); ! 4066: extend_op = SIGN_EXTEND; ! 4067: m = GET_MODE (XEXP (t, 0)); ! 4068: } ! 4069: else if (GET_CODE (t) == SIGN_EXTEND ! 4070: && (GET_CODE (XEXP (t, 0)) == PLUS ! 4071: || GET_CODE (XEXP (t, 0)) == IOR ! 4072: || GET_CODE (XEXP (t, 0)) == XOR) ! 4073: && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG ! 4074: && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) ! 4075: && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) ! 4076: && (num_sign_bit_copies (f, GET_MODE (f)) ! 4077: > (GET_MODE_BITSIZE (mode) ! 4078: - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1)))))) ! 4079: { ! 4080: c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); ! 4081: extend_op = SIGN_EXTEND; ! 4082: m = GET_MODE (XEXP (t, 0)); ! 4083: } ! 4084: else if (GET_CODE (t) == ZERO_EXTEND ! 4085: && (GET_CODE (XEXP (t, 0)) == PLUS ! 4086: || GET_CODE (XEXP (t, 0)) == MINUS ! 4087: || GET_CODE (XEXP (t, 0)) == IOR ! 4088: || GET_CODE (XEXP (t, 0)) == XOR ! 4089: || GET_CODE (XEXP (t, 0)) == ASHIFT ! 4090: || GET_CODE (XEXP (t, 0)) == LSHIFTRT ! 4091: || GET_CODE (XEXP (t, 0)) == ASHIFTRT) ! 4092: && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG ! 4093: && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT ! 4094: && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) ! 4095: && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) ! 4096: && ((nonzero_bits (f, GET_MODE (f)) ! 4097: & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0)))) ! 4098: == 0)) ! 4099: { ! 4100: c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); ! 4101: extend_op = ZERO_EXTEND; ! 4102: m = GET_MODE (XEXP (t, 0)); ! 4103: } ! 4104: else if (GET_CODE (t) == ZERO_EXTEND ! 4105: && (GET_CODE (XEXP (t, 0)) == PLUS ! 4106: || GET_CODE (XEXP (t, 0)) == IOR ! 4107: || GET_CODE (XEXP (t, 0)) == XOR) ! 4108: && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG ! 4109: && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT ! 4110: && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) ! 4111: && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) ! 4112: && ((nonzero_bits (f, GET_MODE (f)) ! 4113: & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1)))) ! 4114: == 0)) ! 4115: { ! 4116: c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); ! 4117: extend_op = ZERO_EXTEND; ! 4118: m = GET_MODE (XEXP (t, 0)); ! 4119: } ! 4120: ! 4121: if (z) ! 4122: { ! 4123: temp = subst (gen_binary (true_code, m, cond_op0, cond_op1), ! 4124: pc_rtx, pc_rtx, 0, 0); ! 4125: temp = gen_binary (MULT, m, temp, ! 4126: gen_binary (MULT, m, c1, const_true_rtx)); ! 4127: temp = subst (temp, pc_rtx, pc_rtx, 0, 0); ! 4128: temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp); ! 4129: ! 4130: if (extend_op != NIL) ! 4131: temp = gen_unary (extend_op, mode, m, temp); ! 4132: ! 4133: return temp; ! 4134: } ! 4135: } ! 4136: #endif ! 4137: ! 4138: /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or ! 4139: 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the ! 4140: negation of a single bit, we can convert this operation to a shift. We ! 4141: can actually do this more generally, but it doesn't seem worth it. */ ! 4142: ! 4143: if (true_code == NE && XEXP (cond, 1) == const0_rtx ! 4144: && false == const0_rtx && GET_CODE (true) == CONST_INT ! 4145: && ((1 == nonzero_bits (XEXP (cond, 0), mode) ! 4146: && (i = exact_log2 (INTVAL (true))) >= 0) ! 4147: || ((num_sign_bit_copies (XEXP (cond, 0), mode) ! 4148: == GET_MODE_BITSIZE (mode)) ! 4149: && (i = exact_log2 (- INTVAL (true))) >= 0))) ! 4150: return ! 4151: simplify_shift_const (NULL_RTX, ASHIFT, mode, ! 4152: gen_lowpart_for_combine (mode, XEXP (cond, 0)), i); ! 4153: ! 4154: return x; ! 4155: } ! 4156: ! 4157: /* Simplify X, a SET expression. Return the new expression. */ ! 4158: ! 4159: static rtx ! 4160: simplify_set (x) ! 4161: rtx x; ! 4162: { ! 4163: rtx src = SET_SRC (x); ! 4164: rtx dest = SET_DEST (x); ! 4165: enum machine_mode mode ! 4166: = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest); ! 4167: rtx other_insn; ! 4168: rtx *cc_use; ! 4169: ! 4170: /* (set (pc) (return)) gets written as (return). */ ! 4171: if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN) ! 4172: return src; ! 4173: ! 4174: /* Now that we know for sure which bits of SRC we are using, see if we can ! 4175: simplify the expression for the object knowing that we only need the ! 4176: low-order bits. */ ! 4177: ! 4178: if (GET_MODE_CLASS (mode) == MODE_INT) ! 4179: src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0); ! 4180: ! 4181: /* If we are setting CC0 or if the source is a COMPARE, look for the use of ! 4182: the comparison result and try to simplify it unless we already have used ! 4183: undobuf.other_insn. */ ! 4184: if ((GET_CODE (src) == COMPARE 1.1 root 4185: #ifdef HAVE_cc0 1.1.1.7 ! root 4186: || dest == cc0_rtx 1.1 root 4187: #endif 1.1.1.7 ! root 4188: ) ! 4189: && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0 ! 4190: && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn) ! 4191: && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<' ! 4192: && rtx_equal_p (XEXP (*cc_use, 0), dest)) ! 4193: { ! 4194: enum rtx_code old_code = GET_CODE (*cc_use); ! 4195: enum rtx_code new_code; ! 4196: rtx op0, op1; ! 4197: int other_changed = 0; ! 4198: enum machine_mode compare_mode = GET_MODE (dest); 1.1 root 4199: 1.1.1.7 ! root 4200: if (GET_CODE (src) == COMPARE) ! 4201: op0 = XEXP (src, 0), op1 = XEXP (src, 1); ! 4202: else ! 4203: op0 = src, op1 = const0_rtx; 1.1 root 4204: 1.1.1.7 ! root 4205: /* Simplify our comparison, if possible. */ ! 4206: new_code = simplify_comparison (old_code, &op0, &op1); 1.1 root 4207: 1.1.1.5 root 4208: #ifdef EXTRA_CC_MODES 1.1.1.7 ! root 4209: /* If this machine has CC modes other than CCmode, check to see if we ! 4210: need to use a different CC mode here. */ ! 4211: compare_mode = SELECT_CC_MODE (new_code, op0, op1); 1.1.1.5 root 4212: #endif /* EXTRA_CC_MODES */ 1.1 root 4213: 1.1.1.5 root 4214: #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES) 1.1.1.7 ! root 4215: /* If the mode changed, we have to change SET_DEST, the mode in the ! 4216: compare, and the mode in the place SET_DEST is used. If SET_DEST is ! 4217: a hard register, just build new versions with the proper mode. If it ! 4218: is a pseudo, we lose unless it is only time we set the pseudo, in ! 4219: which case we can safely change its mode. */ ! 4220: if (compare_mode != GET_MODE (dest)) ! 4221: { ! 4222: int regno = REGNO (dest); ! 4223: rtx new_dest = gen_rtx (REG, compare_mode, regno); 1.1 root 4224: 1.1.1.7 ! root 4225: if (regno < FIRST_PSEUDO_REGISTER ! 4226: || (reg_n_sets[regno] == 1 && ! REG_USERVAR_P (dest))) ! 4227: { ! 4228: if (regno >= FIRST_PSEUDO_REGISTER) ! 4229: SUBST (regno_reg_rtx[regno], new_dest); ! 4230: ! 4231: SUBST (SET_DEST (x), new_dest); ! 4232: SUBST (XEXP (*cc_use, 0), new_dest); ! 4233: other_changed = 1; ! 4234: ! 4235: dest = new_dest; 1.1 root 4236: } 1.1.1.7 ! root 4237: } 1.1 root 4238: #endif 4239: 1.1.1.7 ! root 4240: /* If the code changed, we have to build a new comparison in ! 4241: undobuf.other_insn. */ ! 4242: if (new_code != old_code) ! 4243: { ! 4244: unsigned HOST_WIDE_INT mask; 1.1 root 4245: 1.1.1.7 ! root 4246: SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use), ! 4247: dest, const0_rtx)); 1.1 root 4248: 1.1.1.7 ! root 4249: /* If the only change we made was to change an EQ into an NE or ! 4250: vice versa, OP0 has only one bit that might be nonzero, and OP1 ! 4251: is zero, check if changing the user of the condition code will ! 4252: produce a valid insn. If it won't, we can keep the original code ! 4253: in that insn by surrounding our operation with an XOR. */ 1.1 root 4254: 1.1.1.7 ! root 4255: if (((old_code == NE && new_code == EQ) ! 4256: || (old_code == EQ && new_code == NE)) ! 4257: && ! other_changed && op1 == const0_rtx ! 4258: && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT ! 4259: && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0) ! 4260: { ! 4261: rtx pat = PATTERN (other_insn), note = 0; 1.1 root 4262: 1.1.1.7 ! root 4263: if ((recog_for_combine (&pat, other_insn, ¬e) < 0 ! 4264: && ! check_asm_operands (pat))) ! 4265: { ! 4266: PUT_CODE (*cc_use, old_code); ! 4267: other_insn = 0; 1.1 root 4268: 1.1.1.7 ! root 4269: op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask)); ! 4270: } 1.1 root 4271: } 4272: 1.1.1.7 ! root 4273: other_changed = 1; ! 4274: } ! 4275: ! 4276: if (other_changed) ! 4277: undobuf.other_insn = other_insn; 1.1 root 4278: 4279: #ifdef HAVE_cc0 1.1.1.7 ! root 4280: /* If we are now comparing against zero, change our source if ! 4281: needed. If we do not use cc0, we always have a COMPARE. */ ! 4282: if (op1 == const0_rtx && dest == cc0_rtx) ! 4283: { ! 4284: SUBST (SET_SRC (x), op0); ! 4285: src = op0; ! 4286: } ! 4287: else 1.1 root 4288: #endif 4289: 1.1.1.7 ! root 4290: /* Otherwise, if we didn't previously have a COMPARE in the ! 4291: correct mode, we need one. */ ! 4292: if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode) ! 4293: { ! 4294: SUBST (SET_SRC (x), ! 4295: gen_rtx_combine (COMPARE, compare_mode, op0, op1)); ! 4296: src = SET_SRC (x); 1.1 root 4297: } 4298: else 4299: { 1.1.1.7 ! root 4300: /* Otherwise, update the COMPARE if needed. */ ! 4301: SUBST (XEXP (src, 0), op0); ! 4302: SUBST (XEXP (src, 1), op1); ! 4303: } ! 4304: } ! 4305: else ! 4306: { ! 4307: /* Get SET_SRC in a form where we have placed back any ! 4308: compound expressions. Then do the checks below. */ ! 4309: src = make_compound_operation (src, SET); ! 4310: SUBST (SET_SRC (x), src); ! 4311: } ! 4312: ! 4313: /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation, ! 4314: and X being a REG or (subreg (reg)), we may be able to convert this to ! 4315: (set (subreg:m2 x) (op)). ! 4316: ! 4317: We can always do this if M1 is narrower than M2 because that means that ! 4318: we only care about the low bits of the result. ! 4319: ! 4320: However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot ! 4321: perform a narrower operation that requested since the high-order bits will ! 4322: be undefined. On machine where it is defined, this transformation is safe ! 4323: as long as M1 and M2 have the same number of words. */ 1.1.1.4 root 4324: 1.1.1.7 ! root 4325: if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) ! 4326: && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o' ! 4327: && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1)) ! 4328: / UNITS_PER_WORD) ! 4329: == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))) ! 4330: + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)) 1.1.1.6 root 4331: #ifndef WORD_REGISTER_OPERATIONS 1.1.1.7 ! root 4332: && (GET_MODE_SIZE (GET_MODE (src)) ! 4333: < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))) 1.1.1.4 root 4334: #endif 1.1.1.7 ! root 4335: && (GET_CODE (dest) == REG ! 4336: || (GET_CODE (dest) == SUBREG ! 4337: && GET_CODE (SUBREG_REG (dest)) == REG))) ! 4338: { ! 4339: SUBST (SET_DEST (x), ! 4340: gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)), ! 4341: dest)); ! 4342: SUBST (SET_SRC (x), SUBREG_REG (src)); ! 4343: ! 4344: src = SET_SRC (x), dest = SET_DEST (x); ! 4345: } 1.1.1.4 root 4346: 1.1.1.6 root 4347: #ifdef LOAD_EXTEND_OP 1.1.1.7 ! root 4348: /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this ! 4349: would require a paradoxical subreg. Replace the subreg with a ! 4350: zero_extend to avoid the reload that would otherwise be required. */ ! 4351: ! 4352: if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) ! 4353: && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL ! 4354: && SUBREG_WORD (src) == 0 ! 4355: && (GET_MODE_SIZE (GET_MODE (src)) ! 4356: > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))) ! 4357: && GET_CODE (SUBREG_REG (src)) == MEM) ! 4358: { ! 4359: SUBST (SET_SRC (x), ! 4360: gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))), ! 4361: GET_MODE (src), XEXP (src, 0))); ! 4362: ! 4363: src = SET_SRC (x); ! 4364: } ! 4365: #endif ! 4366: ! 4367: /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we ! 4368: are comparing an item known to be 0 or -1 against 0, use a logical ! 4369: operation instead. Check for one of the arms being an IOR of the other ! 4370: arm with some value. We compute three terms to be IOR'ed together. In ! 4371: practice, at most two will be nonzero. Then we do the IOR's. */ ! 4372: ! 4373: if (GET_CODE (dest) != PC ! 4374: && GET_CODE (src) == IF_THEN_ELSE ! 4375: #ifdef HAVE_conditional_move ! 4376: && ! HAVE_conditional_move ! 4377: #endif ! 4378: && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT ! 4379: && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE) ! 4380: && XEXP (XEXP (src, 0), 1) == const0_rtx ! 4381: && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0)) ! 4382: && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0), ! 4383: GET_MODE (XEXP (XEXP (src, 0), 0))) ! 4384: == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0)))) ! 4385: && ! side_effects_p (src)) ! 4386: { ! 4387: rtx true = (GET_CODE (XEXP (src, 0)) == NE ! 4388: ? XEXP (src, 1) : XEXP (src, 2)); ! 4389: rtx false = (GET_CODE (XEXP (src, 0)) == NE ! 4390: ? XEXP (src, 2) : XEXP (src, 1)); ! 4391: rtx term1 = const0_rtx, term2, term3; ! 4392: ! 4393: if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false)) ! 4394: term1 = false, true = XEXP (true, 1), false = const0_rtx; ! 4395: else if (GET_CODE (true) == IOR ! 4396: && rtx_equal_p (XEXP (true, 1), false)) ! 4397: term1 = false, true = XEXP (true, 0), false = const0_rtx; ! 4398: else if (GET_CODE (false) == IOR ! 4399: && rtx_equal_p (XEXP (false, 0), true)) ! 4400: term1 = true, false = XEXP (false, 1), true = const0_rtx; ! 4401: else if (GET_CODE (false) == IOR ! 4402: && rtx_equal_p (XEXP (false, 1), true)) ! 4403: term1 = true, false = XEXP (false, 0), true = const0_rtx; ! 4404: ! 4405: term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true); ! 4406: term3 = gen_binary (AND, GET_MODE (src), ! 4407: gen_unary (NOT, GET_MODE (src), GET_MODE (src), ! 4408: XEXP (XEXP (src, 0), 0)), ! 4409: false); ! 4410: ! 4411: SUBST (SET_SRC (x), ! 4412: gen_binary (IOR, GET_MODE (src), ! 4413: gen_binary (IOR, GET_MODE (src), term1, term2), ! 4414: term3)); ! 4415: ! 4416: src = SET_SRC (x); ! 4417: } ! 4418: ! 4419: /* If either SRC or DEST is a CLOBBER of (const_int 0), make this ! 4420: whole thing fail. */ ! 4421: if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx) ! 4422: return src; ! 4423: else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx) ! 4424: return dest; ! 4425: else ! 4426: /* Convert this into a field assignment operation, if possible. */ ! 4427: return make_field_assignment (x); ! 4428: } ! 4429: ! 4430: /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified ! 4431: result. LAST is nonzero if this is the last retry. */ 1.1.1.4 root 4432: 1.1.1.7 ! root 4433: static rtx ! 4434: simplify_logical (x, last) ! 4435: rtx x; ! 4436: int last; ! 4437: { ! 4438: enum machine_mode mode = GET_MODE (x); ! 4439: rtx op0 = XEXP (x, 0); ! 4440: rtx op1 = XEXP (x, 1); 1.1 root 4441: 1.1.1.7 ! root 4442: switch (GET_CODE (x)) ! 4443: { 1.1 root 4444: case AND: 1.1.1.7 ! root 4445: /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single ! 4446: insn (and may simplify more). */ ! 4447: if (GET_CODE (op0) == XOR ! 4448: && rtx_equal_p (XEXP (op0, 0), op1) ! 4449: && ! side_effects_p (op1)) ! 4450: x = gen_binary (AND, mode, ! 4451: gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1); ! 4452: ! 4453: if (GET_CODE (op0) == XOR ! 4454: && rtx_equal_p (XEXP (op0, 1), op1) ! 4455: && ! side_effects_p (op1)) ! 4456: x = gen_binary (AND, mode, ! 4457: gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1); ! 4458: ! 4459: /* Similarly for (~ (A ^ B)) & A. */ ! 4460: if (GET_CODE (op0) == NOT ! 4461: && GET_CODE (XEXP (op0, 0)) == XOR ! 4462: && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1) ! 4463: && ! side_effects_p (op1)) ! 4464: x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1); ! 4465: ! 4466: if (GET_CODE (op0) == NOT ! 4467: && GET_CODE (XEXP (op0, 0)) == XOR ! 4468: && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1) ! 4469: && ! side_effects_p (op1)) ! 4470: x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1); ! 4471: ! 4472: if (GET_CODE (op1) == CONST_INT) 1.1 root 4473: { 1.1.1.7 ! root 4474: x = simplify_and_const_int (x, mode, op0, INTVAL (op1)); 1.1 root 4475: 4476: /* If we have (ior (and (X C1) C2)) and the next restart would be 4477: the last, simplify this by making C1 as small as possible 4478: and then exit. */ 1.1.1.7 ! root 4479: if (last ! 4480: && GET_CODE (x) == IOR && GET_CODE (op0) == AND ! 4481: && GET_CODE (XEXP (op0, 1)) == CONST_INT ! 4482: && GET_CODE (op1) == CONST_INT) ! 4483: return gen_binary (IOR, mode, ! 4484: gen_binary (AND, mode, XEXP (op0, 0), ! 4485: GEN_INT (INTVAL (XEXP (op0, 1)) ! 4486: & ~ INTVAL (op1))), op1); 1.1 root 4487: 4488: if (GET_CODE (x) != AND) 1.1.1.7 ! root 4489: return x; 1.1 root 4490: } 4491: 4492: /* Convert (A | B) & A to A. */ 1.1.1.7 ! root 4493: if (GET_CODE (op0) == IOR ! 4494: && (rtx_equal_p (XEXP (op0, 0), op1) ! 4495: || rtx_equal_p (XEXP (op0, 1), op1)) ! 4496: && ! side_effects_p (XEXP (op0, 0)) ! 4497: && ! side_effects_p (XEXP (op0, 1))) ! 4498: return op1; 1.1.1.4 root 4499: 4500: /* In the following group of tests (and those in case IOR below), 1.1 root 4501: we start with some combination of logical operations and apply 4502: the distributive law followed by the inverse distributive law. 4503: Most of the time, this results in no change. However, if some of 4504: the operands are the same or inverses of each other, simplifications 4505: will result. 4506: 4507: For example, (and (ior A B) (not B)) can occur as the result of 4508: expanding a bit field assignment. When we apply the distributive 4509: law to this, we get (ior (and (A (not B))) (and (B (not B)))), 1.1.1.7 ! root 4510: which then simplifies to (and (A (not B))). 1.1 root 4511: 1.1.1.7 ! root 4512: If we have (and (ior A B) C), apply the distributive law and then 1.1 root 4513: the inverse distributive law to see if things simplify. */ 4514: 1.1.1.7 ! root 4515: if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR) 1.1 root 4516: { 4517: x = apply_distributive_law 1.1.1.7 ! root 4518: (gen_binary (GET_CODE (op0), mode, ! 4519: gen_binary (AND, mode, XEXP (op0, 0), op1), ! 4520: gen_binary (AND, mode, XEXP (op0, 1), op1))); 1.1 root 4521: if (GET_CODE (x) != AND) 1.1.1.7 ! root 4522: return x; 1.1 root 4523: } 4524: 1.1.1.7 ! root 4525: if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR) ! 4526: return apply_distributive_law ! 4527: (gen_binary (GET_CODE (op1), mode, ! 4528: gen_binary (AND, mode, XEXP (op1, 0), op0), ! 4529: gen_binary (AND, mode, XEXP (op1, 1), op0))); 1.1 root 4530: 4531: /* Similarly, taking advantage of the fact that 4532: (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */ 4533: 1.1.1.7 ! root 4534: if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR) ! 4535: return apply_distributive_law ! 4536: (gen_binary (XOR, mode, ! 4537: gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)), ! 4538: gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 1)))); 1.1 root 4539: 1.1.1.7 ! root 4540: else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR) ! 4541: return apply_distributive_law ! 4542: (gen_binary (XOR, mode, ! 4543: gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)), ! 4544: gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 1)))); 1.1 root 4545: break; 4546: 4547: case IOR: 1.1.1.5 root 4548: /* (ior A C) is C if all bits of A that might be nonzero are on in C. */ 1.1.1.7 ! root 4549: if (GET_CODE (op1) == CONST_INT 1.1.1.4 root 4550: && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 1.1.1.7 ! root 4551: && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0) ! 4552: return op1; 1.1.1.4 root 4553: 1.1 root 4554: /* Convert (A & B) | A to A. */ 1.1.1.7 ! root 4555: if (GET_CODE (op0) == AND ! 4556: && (rtx_equal_p (XEXP (op0, 0), op1) ! 4557: || rtx_equal_p (XEXP (op0, 1), op1)) ! 4558: && ! side_effects_p (XEXP (op0, 0)) ! 4559: && ! side_effects_p (XEXP (op0, 1))) ! 4560: return op1; 1.1 root 4561: 4562: /* If we have (ior (and A B) C), apply the distributive law and then 4563: the inverse distributive law to see if things simplify. */ 4564: 1.1.1.7 ! root 4565: if (GET_CODE (op0) == AND) 1.1 root 4566: { 4567: x = apply_distributive_law 4568: (gen_binary (AND, mode, 1.1.1.7 ! root 4569: gen_binary (IOR, mode, XEXP (op0, 0), op1), ! 4570: gen_binary (IOR, mode, XEXP (op0, 1), op1))); 1.1 root 4571: 4572: if (GET_CODE (x) != IOR) 1.1.1.7 ! root 4573: return x; 1.1 root 4574: } 4575: 1.1.1.7 ! root 4576: if (GET_CODE (op1) == AND) 1.1 root 4577: { 4578: x = apply_distributive_law 4579: (gen_binary (AND, mode, 1.1.1.7 ! root 4580: gen_binary (IOR, mode, XEXP (op1, 0), op0), ! 4581: gen_binary (IOR, mode, XEXP (op1, 1), op0))); 1.1 root 4582: 4583: if (GET_CODE (x) != IOR) 1.1.1.7 ! root 4584: return x; 1.1 root 4585: } 4586: 4587: /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the 4588: mode size to (rotate A CX). */ 4589: 1.1.1.7 ! root 4590: if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT) ! 4591: || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT)) ! 4592: && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0)) ! 4593: && GET_CODE (XEXP (op0, 1)) == CONST_INT ! 4594: && GET_CODE (XEXP (op1, 1)) == CONST_INT ! 4595: && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1)) 1.1 root 4596: == GET_MODE_BITSIZE (mode))) 1.1.1.7 ! root 4597: return gen_rtx (ROTATE, mode, XEXP (op0, 0), ! 4598: (GET_CODE (op0) == ASHIFT ! 4599: ? XEXP (op0, 1) : XEXP (op1, 1))); ! 4600: ! 4601: /* If OP0 is (ashiftrt (plus ...) C), it might actually be ! 4602: a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS ! 4603: does not affect any of the bits in OP1, it can really be done ! 4604: as a PLUS and we can associate. We do this by seeing if OP1 ! 4605: can be safely shifted left C bits. */ ! 4606: if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT ! 4607: && GET_CODE (XEXP (op0, 0)) == PLUS ! 4608: && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT ! 4609: && GET_CODE (XEXP (op0, 1)) == CONST_INT ! 4610: && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT) 1.1 root 4611: { 1.1.1.7 ! root 4612: int count = INTVAL (XEXP (op0, 1)); ! 4613: HOST_WIDE_INT mask = INTVAL (op1) << count; 1.1 root 4614: 1.1.1.7 ! root 4615: if (mask >> count == INTVAL (op1) ! 4616: && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0) ! 4617: { ! 4618: SUBST (XEXP (XEXP (op0, 0), 1), ! 4619: GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask)); ! 4620: return op0; ! 4621: } 1.1 root 4622: } 4623: break; 4624: 4625: case XOR: 4626: /* Convert (XOR (NOT x) (NOT y)) to (XOR x y). 4627: Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for 4628: (NOT y). */ 1.1.1.7 ! root 4629: { ! 4630: int num_negated = 0; 1.1 root 4631: 1.1.1.7 ! root 4632: if (GET_CODE (op0) == NOT) ! 4633: num_negated++, op0 = XEXP (op0, 0); ! 4634: if (GET_CODE (op1) == NOT) ! 4635: num_negated++, op1 = XEXP (op1, 0); 1.1 root 4636: 1.1.1.7 ! root 4637: if (num_negated == 2) ! 4638: { ! 4639: SUBST (XEXP (x, 0), op0); ! 4640: SUBST (XEXP (x, 1), op1); ! 4641: } ! 4642: else if (num_negated == 1) ! 4643: return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1)); ! 4644: } 1.1 root 4645: 1.1.1.7 ! root 4646: /* Convert (xor (and A B) B) to (and (not A) B). The latter may ! 4647: correspond to a machine insn or result in further simplifications ! 4648: if B is a constant. */ 1.1.1.3 root 4649: 1.1.1.7 ! root 4650: if (GET_CODE (op0) == AND ! 4651: && rtx_equal_p (XEXP (op0, 1), op1) ! 4652: && ! side_effects_p (op1)) ! 4653: return gen_binary (AND, mode, ! 4654: gen_unary (NOT, mode, mode, XEXP (op0, 0)), ! 4655: op1); ! 4656: ! 4657: else if (GET_CODE (op0) == AND ! 4658: && rtx_equal_p (XEXP (op0, 0), op1) ! 4659: && ! side_effects_p (op1)) ! 4660: return gen_binary (AND, mode, ! 4661: gen_unary (NOT, mode, mode, XEXP (op0, 1)), ! 4662: op1); 1.1 root 4663: 1.1.1.7 ! root 4664: #if STORE_FLAG_VALUE == 1 ! 4665: /* (xor (comparison foo bar) (const_int 1)) can become the reversed ! 4666: comparison. */ ! 4667: if (op1 == const1_rtx ! 4668: && GET_RTX_CLASS (GET_CODE (op0)) == '<' ! 4669: && reversible_comparison_p (op0)) ! 4670: return gen_rtx_combine (reverse_condition (GET_CODE (op0)), ! 4671: mode, XEXP (op0, 0), XEXP (op0, 1)); 1.1.1.4 root 4672: 1.1.1.7 ! root 4673: /* (lshiftrt foo C) where C is the number of bits in FOO minus 1 ! 4674: is (lt foo (const_int 0)), so we can perform the above ! 4675: simplification. */ ! 4676: ! 4677: if (op1 == const1_rtx ! 4678: && GET_CODE (op0) == LSHIFTRT ! 4679: && GET_CODE (XEXP (op0, 1)) == CONST_INT ! 4680: && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1) ! 4681: return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx); 1.1.1.4 root 4682: #endif 4683: 1.1.1.7 ! root 4684: /* (xor (comparison foo bar) (const_int sign-bit)) ! 4685: when STORE_FLAG_VALUE is the sign bit. */ ! 4686: if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT ! 4687: && (STORE_FLAG_VALUE ! 4688: == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)) ! 4689: && op1 == const_true_rtx ! 4690: && GET_RTX_CLASS (GET_CODE (op0)) == '<' ! 4691: && reversible_comparison_p (op0)) ! 4692: return gen_rtx_combine (reverse_condition (GET_CODE (op0)), ! 4693: mode, XEXP (op0, 0), XEXP (op0, 1)); 1.1 root 4694: break; 4695: } 4696: 4697: return x; 4698: } 4699: 4700: /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound 4701: operations" because they can be replaced with two more basic operations. 4702: ZERO_EXTEND is also considered "compound" because it can be replaced with 4703: an AND operation, which is simpler, though only one operation. 4704: 4705: The function expand_compound_operation is called with an rtx expression 4706: and will convert it to the appropriate shifts and AND operations, 4707: simplifying at each stage. 4708: 4709: The function make_compound_operation is called to convert an expression 4710: consisting of shifts and ANDs into the equivalent compound expression. 4711: It is the inverse of this function, loosely speaking. */ 4712: 4713: static rtx 4714: expand_compound_operation (x) 4715: rtx x; 4716: { 4717: int pos = 0, len; 4718: int unsignedp = 0; 4719: int modewidth; 4720: rtx tem; 4721: 4722: switch (GET_CODE (x)) 4723: { 4724: case ZERO_EXTEND: 4725: unsignedp = 1; 4726: case SIGN_EXTEND: 1.1.1.3 root 4727: /* We can't necessarily use a const_int for a multiword mode; 4728: it depends on implicitly extending the value. 4729: Since we don't know the right way to extend it, 4730: we can't tell whether the implicit way is right. 4731: 4732: Even for a mode that is no wider than a const_int, 4733: we can't win, because we need to sign extend one of its bits through 4734: the rest of it, and we don't know which bit. */ 1.1 root 4735: if (GET_CODE (XEXP (x, 0)) == CONST_INT) 1.1.1.3 root 4736: return x; 1.1 root 4737: 1.1.1.7 ! root 4738: /* Return if (subreg:MODE FROM 0) is not a safe replacement for ! 4739: (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM ! 4740: because (SUBREG (MEM...)) is guaranteed to cause the MEM to be ! 4741: reloaded. If not for that, MEM's would very rarely be safe. ! 4742: ! 4743: Reject MODEs bigger than a word, because we might not be able ! 4744: to reference a two-register group starting with an arbitrary register ! 4745: (and currently gen_lowpart might crash for a SUBREG). */ ! 4746: ! 4747: if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD) 1.1 root 4748: return x; 4749: 4750: len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))); 4751: /* If the inner object has VOIDmode (the only way this can happen 4752: is if it is a ASM_OPERANDS), we can't do anything since we don't 4753: know how much masking to do. */ 4754: if (len == 0) 4755: return x; 4756: 4757: break; 4758: 4759: case ZERO_EXTRACT: 4760: unsignedp = 1; 4761: case SIGN_EXTRACT: 4762: /* If the operand is a CLOBBER, just return it. */ 4763: if (GET_CODE (XEXP (x, 0)) == CLOBBER) 4764: return XEXP (x, 0); 4765: 4766: if (GET_CODE (XEXP (x, 1)) != CONST_INT 4767: || GET_CODE (XEXP (x, 2)) != CONST_INT 4768: || GET_MODE (XEXP (x, 0)) == VOIDmode) 4769: return x; 4770: 4771: len = INTVAL (XEXP (x, 1)); 4772: pos = INTVAL (XEXP (x, 2)); 4773: 4774: /* If this goes outside the object being extracted, replace the object 4775: with a (use (mem ...)) construct that only combine understands 4776: and is used only for this purpose. */ 4777: if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))) 4778: SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0))); 4779: 4780: #if BITS_BIG_ENDIAN 4781: pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos; 4782: #endif 4783: break; 4784: 4785: default: 4786: return x; 4787: } 4788: 4789: /* If we reach here, we want to return a pair of shifts. The inner 4790: shift is a left shift of BITSIZE - POS - LEN bits. The outer 4791: shift is a right shift of BITSIZE - LEN bits. It is arithmetic or 4792: logical depending on the value of UNSIGNEDP. 4793: 4794: If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be 4795: converted into an AND of a shift. 4796: 4797: We must check for the case where the left shift would have a negative 4798: count. This can happen in a case like (x >> 31) & 255 on machines 4799: that can't shift by a constant. On those machines, we would first 4800: combine the shift with the AND to produce a variable-position 4801: extraction. Then the constant of 31 would be substituted in to produce 4802: a such a position. */ 4803: 4804: modewidth = GET_MODE_BITSIZE (GET_MODE (x)); 4805: if (modewidth >= pos - len) 1.1.1.4 root 4806: tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT, 1.1 root 4807: GET_MODE (x), 1.1.1.4 root 4808: simplify_shift_const (NULL_RTX, ASHIFT, 4809: GET_MODE (x), 1.1 root 4810: XEXP (x, 0), 4811: modewidth - pos - len), 4812: modewidth - len); 4813: 1.1.1.4 root 4814: else if (unsignedp && len < HOST_BITS_PER_WIDE_INT) 4815: tem = simplify_and_const_int (NULL_RTX, GET_MODE (x), 4816: simplify_shift_const (NULL_RTX, LSHIFTRT, 1.1 root 4817: GET_MODE (x), 4818: XEXP (x, 0), pos), 1.1.1.4 root 4819: ((HOST_WIDE_INT) 1 << len) - 1); 1.1 root 4820: else 4821: /* Any other cases we can't handle. */ 4822: return x; 4823: 4824: 4825: /* If we couldn't do this for some reason, return the original 4826: expression. */ 4827: if (GET_CODE (tem) == CLOBBER) 4828: return x; 4829: 4830: return tem; 4831: } 4832: 4833: /* X is a SET which contains an assignment of one object into 4834: a part of another (such as a bit-field assignment, STRICT_LOW_PART, 4835: or certain SUBREGS). If possible, convert it into a series of 4836: logical operations. 4837: 4838: We half-heartedly support variable positions, but do not at all 4839: support variable lengths. */ 4840: 4841: static rtx 4842: expand_field_assignment (x) 4843: rtx x; 4844: { 4845: rtx inner; 4846: rtx pos; /* Always counts from low bit. */ 4847: int len; 4848: rtx mask; 4849: enum machine_mode compute_mode; 4850: 4851: /* Loop until we find something we can't simplify. */ 4852: while (1) 4853: { 4854: if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART 4855: && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG) 4856: { 4857: inner = SUBREG_REG (XEXP (SET_DEST (x), 0)); 4858: len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))); 4859: pos = const0_rtx; 4860: } 4861: else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT 4862: && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT) 4863: { 4864: inner = XEXP (SET_DEST (x), 0); 4865: len = INTVAL (XEXP (SET_DEST (x), 1)); 4866: pos = XEXP (SET_DEST (x), 2); 4867: 4868: /* If the position is constant and spans the width of INNER, 4869: surround INNER with a USE to indicate this. */ 4870: if (GET_CODE (pos) == CONST_INT 4871: && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner))) 4872: inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner); 4873: 4874: #if BITS_BIG_ENDIAN 4875: if (GET_CODE (pos) == CONST_INT) 1.1.1.4 root 4876: pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len 4877: - INTVAL (pos)); 1.1 root 4878: else if (GET_CODE (pos) == MINUS 4879: && GET_CODE (XEXP (pos, 1)) == CONST_INT 4880: && (INTVAL (XEXP (pos, 1)) 4881: == GET_MODE_BITSIZE (GET_MODE (inner)) - len)) 4882: /* If position is ADJUST - X, new position is X. */ 4883: pos = XEXP (pos, 0); 4884: else 4885: pos = gen_binary (MINUS, GET_MODE (pos), 1.1.1.4 root 4886: GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) 4887: - len), 4888: pos); 1.1 root 4889: #endif 4890: } 4891: 4892: /* A SUBREG between two modes that occupy the same numbers of words 4893: can be done by moving the SUBREG to the source. */ 4894: else if (GET_CODE (SET_DEST (x)) == SUBREG 4895: && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) 4896: + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) 4897: == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) 4898: + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))) 4899: { 4900: x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)), 4901: gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))), 4902: SET_SRC (x))); 4903: continue; 4904: } 4905: else 4906: break; 4907: 4908: while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) 4909: inner = SUBREG_REG (inner); 4910: 4911: compute_mode = GET_MODE (inner); 4912: 4913: /* Compute a mask of LEN bits, if we can do this on the host machine. */ 1.1.1.4 root 4914: if (len < HOST_BITS_PER_WIDE_INT) 4915: mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1); 1.1 root 4916: else 4917: break; 4918: 4919: /* Now compute the equivalent expression. Make a copy of INNER 4920: for the SET_DEST in case it is a MEM into which we will substitute; 4921: we don't want shared RTL in that case. */ 4922: x = gen_rtx (SET, VOIDmode, copy_rtx (inner), 4923: gen_binary (IOR, compute_mode, 4924: gen_binary (AND, compute_mode, 4925: gen_unary (NOT, compute_mode, 1.1.1.7 ! root 4926: compute_mode, 1.1 root 4927: gen_binary (ASHIFT, 4928: compute_mode, 4929: mask, pos)), 4930: inner), 4931: gen_binary (ASHIFT, compute_mode, 4932: gen_binary (AND, compute_mode, 4933: gen_lowpart_for_combine 4934: (compute_mode, 4935: SET_SRC (x)), 4936: mask), 4937: pos))); 4938: } 4939: 4940: return x; 4941: } 4942: 1.1.1.5 root 4943: /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero, 4944: it is an RTX that represents a variable starting position; otherwise, 4945: POS is the (constant) starting bit position (counted from the LSB). 1.1 root 4946: 4947: INNER may be a USE. This will occur when we started with a bitfield 4948: that went outside the boundary of the object in memory, which is 4949: allowed on most machines. To isolate this case, we produce a USE 4950: whose mode is wide enough and surround the MEM with it. The only 4951: code that understands the USE is this routine. If it is not removed, 4952: it will cause the resulting insn not to match. 4953: 4954: UNSIGNEDP is non-zero for an unsigned reference and zero for a 4955: signed reference. 4956: 4957: IN_DEST is non-zero if this is a reference in the destination of a 4958: SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero, 4959: a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will 4960: be used. 4961: 4962: IN_COMPARE is non-zero if we are in a COMPARE. This means that a 4963: ZERO_EXTRACT should be built even for bits starting at bit 0. 4964: 4965: MODE is the desired mode of the result (if IN_DEST == 0). */ 4966: 4967: static rtx 4968: make_extraction (mode, inner, pos, pos_rtx, len, 4969: unsignedp, in_dest, in_compare) 4970: enum machine_mode mode; 4971: rtx inner; 4972: int pos; 4973: rtx pos_rtx; 4974: int len; 4975: int unsignedp; 4976: int in_dest, in_compare; 4977: { 1.1.1.4 root 4978: /* This mode describes the size of the storage area 4979: to fetch the overall value from. Within that, we 4980: ignore the POS lowest bits, etc. */ 1.1 root 4981: enum machine_mode is_mode = GET_MODE (inner); 4982: enum machine_mode inner_mode; 4983: enum machine_mode wanted_mem_mode = byte_mode; 4984: enum machine_mode pos_mode = word_mode; 4985: enum machine_mode extraction_mode = word_mode; 4986: enum machine_mode tmode = mode_for_size (len, MODE_INT, 1); 4987: int spans_byte = 0; 4988: rtx new = 0; 1.1.1.5 root 4989: rtx orig_pos_rtx = pos_rtx; 1.1.1.6 root 4990: int orig_pos; 1.1 root 4991: 4992: /* Get some information about INNER and get the innermost object. */ 4993: if (GET_CODE (inner) == USE) 1.1.1.4 root 4994: /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */ 1.1 root 4995: /* We don't need to adjust the position because we set up the USE 4996: to pretend that it was a full-word object. */ 4997: spans_byte = 1, inner = XEXP (inner, 0); 4998: else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) 1.1.1.4 root 4999: { 5000: /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...), 5001: consider just the QI as the memory to extract from. 5002: The subreg adds or removes high bits; its mode is 5003: irrelevant to the meaning of this extraction, 5004: since POS and LEN count from the lsb. */ 5005: if (GET_CODE (SUBREG_REG (inner)) == MEM) 5006: is_mode = GET_MODE (SUBREG_REG (inner)); 5007: inner = SUBREG_REG (inner); 5008: } 1.1 root 5009: 5010: inner_mode = GET_MODE (inner); 5011: 5012: if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT) 1.1.1.5 root 5013: pos = INTVAL (pos_rtx), pos_rtx = 0; 1.1 root 5014: 5015: /* See if this can be done without an extraction. We never can if the 5016: width of the field is not the same as that of some integer mode. For 5017: registers, we can only avoid the extraction if the position is at the 5018: low-order bit and this is either not in the destination or we have the 5019: appropriate STRICT_LOW_PART operation available. 5020: 5021: For MEM, we can avoid an extract if the field starts on an appropriate 5022: boundary and we can change the mode of the memory reference. However, 5023: we cannot directly access the MEM if we have a USE and the underlying 5024: MEM is not TMODE. This combination means that MEM was being used in a 5025: context where bits outside its mode were being referenced; that is only 5026: valid in bit-field insns. */ 5027: 5028: if (tmode != BLKmode 5029: && ! (spans_byte && inner_mode != tmode) 1.1.1.5 root 5030: && ((pos_rtx == 0 && pos == 0 && GET_CODE (inner) != MEM 1.1 root 5031: && (! in_dest 1.1.1.4 root 5032: || (GET_CODE (inner) == REG 5033: && (movstrict_optab->handlers[(int) tmode].insn_code 5034: != CODE_FOR_nothing)))) 1.1.1.5 root 5035: || (GET_CODE (inner) == MEM && pos_rtx == 0 1.1.1.2 root 5036: && (pos 5037: % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode) 5038: : BITS_PER_UNIT)) == 0 1.1 root 5039: /* We can't do this if we are widening INNER_MODE (it 5040: may not be aligned, for one thing). */ 5041: && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode) 5042: && (inner_mode == tmode 5043: || (! mode_dependent_address_p (XEXP (inner, 0)) 5044: && ! MEM_VOLATILE_P (inner)))))) 5045: { 5046: /* If INNER is a MEM, make a new MEM that encompasses just the desired 5047: field. If the original and current mode are the same, we need not 5048: adjust the offset. Otherwise, we do if bytes big endian. 5049: 5050: If INNER is not a MEM, get a piece consisting of the just the field 1.1.1.4 root 5051: of interest (in this case POS must be 0). */ 1.1 root 5052: 5053: if (GET_CODE (inner) == MEM) 5054: { 1.1.1.4 root 5055: int offset; 5056: /* POS counts from lsb, but make OFFSET count in memory order. */ 5057: if (BYTES_BIG_ENDIAN) 5058: offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT; 5059: else 5060: offset = pos / BITS_PER_UNIT; 1.1 root 5061: 5062: new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset)); 5063: RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner); 5064: MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner); 5065: MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner); 5066: } 1.1.1.4 root 5067: else if (GET_CODE (inner) == REG) 1.1.1.7 ! root 5068: { ! 5069: /* We can't call gen_lowpart_for_combine here since we always want ! 5070: a SUBREG and it would sometimes return a new hard register. */ ! 5071: if (tmode != inner_mode) ! 5072: new = gen_rtx (SUBREG, tmode, inner, ! 5073: (WORDS_BIG_ENDIAN ! 5074: && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD ! 5075: ? ((GET_MODE_SIZE (inner_mode) ! 5076: - GET_MODE_SIZE (tmode)) ! 5077: / UNITS_PER_WORD) ! 5078: : 0)); ! 5079: else ! 5080: new = inner; ! 5081: } 1.1 root 5082: else 1.1.1.6 root 5083: new = force_to_mode (inner, tmode, 5084: len >= HOST_BITS_PER_WIDE_INT 5085: ? GET_MODE_MASK (tmode) 5086: : ((HOST_WIDE_INT) 1 << len) - 1, 5087: NULL_RTX, 0); 1.1 root 5088: 5089: /* If this extraction is going into the destination of a SET, 5090: make a STRICT_LOW_PART unless we made a MEM. */ 5091: 5092: if (in_dest) 5093: return (GET_CODE (new) == MEM ? new 1.1.1.4 root 5094: : (GET_CODE (new) != SUBREG 5095: ? gen_rtx (CLOBBER, tmode, const0_rtx) 5096: : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new))); 1.1 root 5097: 5098: /* Otherwise, sign- or zero-extend unless we already are in the 5099: proper mode. */ 5100: 5101: return (mode == tmode ? new 5102: : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND, 5103: mode, new)); 5104: } 5105: 1.1.1.4 root 5106: /* Unless this is a COMPARE or we have a funny memory reference, 5107: don't do anything with zero-extending field extracts starting at 5108: the low-order bit since they are simple AND operations. */ 1.1.1.5 root 5109: if (pos_rtx == 0 && pos == 0 && ! in_dest 5110: && ! in_compare && ! spans_byte && unsignedp) 1.1 root 5111: return 0; 5112: 1.1.1.7 ! root 5113: /* Unless we are allowed to span bytes, reject this if we would be ! 5114: spanning bytes or if the position is not a constant and the length ! 5115: is not 1. In all other cases, we would only be going outside ! 5116: out object in cases when an original shift would have been ! 5117: undefined. */ ! 5118: if (! spans_byte ! 5119: && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode)) ! 5120: || (pos_rtx != 0 && len != 1))) ! 5121: return 0; ! 5122: 1.1 root 5123: /* Get the mode to use should INNER be a MEM, the mode for the position, 5124: and the mode for the result. */ 5125: #ifdef HAVE_insv 5126: if (in_dest) 5127: { 5128: wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_insv][0]; 5129: pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2]; 5130: extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3]; 5131: } 5132: #endif 5133: 5134: #ifdef HAVE_extzv 5135: if (! in_dest && unsignedp) 5136: { 5137: wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extzv][1]; 5138: pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3]; 5139: extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0]; 5140: } 5141: #endif 5142: 5143: #ifdef HAVE_extv 5144: if (! in_dest && ! unsignedp) 5145: { 5146: wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extv][1]; 5147: pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3]; 5148: extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0]; 5149: } 5150: #endif 5151: 5152: /* Never narrow an object, since that might not be safe. */ 5153: 5154: if (mode != VOIDmode 5155: && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode)) 5156: extraction_mode = mode; 5157: 5158: if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode 5159: && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx))) 5160: pos_mode = GET_MODE (pos_rtx); 5161: 5162: /* If this is not from memory or we have to change the mode of memory and 5163: cannot, the desired mode is EXTRACTION_MODE. */ 5164: if (GET_CODE (inner) != MEM 5165: || (inner_mode != wanted_mem_mode 5166: && (mode_dependent_address_p (XEXP (inner, 0)) 5167: || MEM_VOLATILE_P (inner)))) 5168: wanted_mem_mode = extraction_mode; 5169: 1.1.1.6 root 5170: orig_pos = pos; 5171: 1.1 root 5172: #if BITS_BIG_ENDIAN 5173: /* If position is constant, compute new position. Otherwise, build 5174: subtraction. */ 1.1.1.5 root 5175: if (pos_rtx == 0) 1.1 root 5176: pos = (MAX (GET_MODE_BITSIZE (is_mode), GET_MODE_BITSIZE (wanted_mem_mode)) 5177: - len - pos); 5178: else 5179: pos_rtx 5180: = gen_rtx_combine (MINUS, GET_MODE (pos_rtx), 1.1.1.4 root 5181: GEN_INT (MAX (GET_MODE_BITSIZE (is_mode), 5182: GET_MODE_BITSIZE (wanted_mem_mode)) 5183: - len), 5184: pos_rtx); 1.1 root 5185: #endif 5186: 5187: /* If INNER has a wider mode, make it smaller. If this is a constant 5188: extract, try to adjust the byte to point to the byte containing 5189: the value. */ 5190: if (wanted_mem_mode != VOIDmode 5191: && GET_MODE_SIZE (wanted_mem_mode) < GET_MODE_SIZE (is_mode) 5192: && ((GET_CODE (inner) == MEM 5193: && (inner_mode == wanted_mem_mode 5194: || (! mode_dependent_address_p (XEXP (inner, 0)) 5195: && ! MEM_VOLATILE_P (inner)))))) 5196: { 5197: int offset = 0; 5198: 5199: /* The computations below will be correct if the machine is big 5200: endian in both bits and bytes or little endian in bits and bytes. 5201: If it is mixed, we must adjust. */ 5202: 5203: /* If bytes are big endian and we had a paradoxical SUBREG, we must 5204: adjust OFFSET to compensate. */ 5205: #if BYTES_BIG_ENDIAN 5206: if (! spans_byte 5207: && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode)) 5208: offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode); 5209: #endif 5210: 5211: /* If this is a constant position, we can move to the desired byte. */ 1.1.1.5 root 5212: if (pos_rtx == 0) 1.1 root 5213: { 5214: offset += pos / BITS_PER_UNIT; 5215: pos %= GET_MODE_BITSIZE (wanted_mem_mode); 5216: } 5217: 1.1.1.5 root 5218: #if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN 5219: if (! spans_byte && is_mode != wanted_mem_mode) 5220: offset = (GET_MODE_SIZE (is_mode) 5221: - GET_MODE_SIZE (wanted_mem_mode) - offset); 5222: #endif 5223: 1.1 root 5224: if (offset != 0 || inner_mode != wanted_mem_mode) 5225: { 5226: rtx newmem = gen_rtx (MEM, wanted_mem_mode, 5227: plus_constant (XEXP (inner, 0), offset)); 5228: RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner); 5229: MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner); 5230: MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner); 5231: inner = newmem; 5232: } 5233: } 5234: 5235: /* If INNER is not memory, we can always get it into the proper mode. */ 5236: else if (GET_CODE (inner) != MEM) 1.1.1.4 root 5237: inner = force_to_mode (inner, extraction_mode, 1.1.1.6 root 5238: pos_rtx || len + orig_pos >= HOST_BITS_PER_WIDE_INT 5239: ? GET_MODE_MASK (extraction_mode) 5240: : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos, 5241: NULL_RTX, 0); 1.1 root 5242: 5243: /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we 5244: have to zero extend. Otherwise, we can just use a SUBREG. */ 1.1.1.5 root 5245: if (pos_rtx != 0 1.1 root 5246: && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx))) 5247: pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx); 1.1.1.5 root 5248: else if (pos_rtx != 0 1.1 root 5249: && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx))) 5250: pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx); 5251: 1.1.1.5 root 5252: /* Make POS_RTX unless we already have it and it is correct. If we don't 5253: have a POS_RTX but we do have an ORIG_POS_RTX, the latter must 5254: be a CONST_INT. */ 5255: if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos) 5256: pos_rtx = orig_pos_rtx; 5257: 5258: else if (pos_rtx == 0) 1.1.1.4 root 5259: pos_rtx = GEN_INT (pos); 1.1 root 5260: 5261: /* Make the required operation. See if we can use existing rtx. */ 5262: new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT, 1.1.1.4 root 5263: extraction_mode, inner, GEN_INT (len), pos_rtx); 1.1 root 5264: if (! in_dest) 5265: new = gen_lowpart_for_combine (mode, new); 5266: 5267: return new; 5268: } 5269: 1.1.1.7 ! root 5270: /* See if X contains an ASHIFT of COUNT or more bits that can be commuted ! 5271: with any other operations in X. Return X without that shift if so. */ ! 5272: ! 5273: static rtx ! 5274: extract_left_shift (x, count) ! 5275: rtx x; ! 5276: int count; ! 5277: { ! 5278: enum rtx_code code = GET_CODE (x); ! 5279: enum machine_mode mode = GET_MODE (x); ! 5280: rtx tem; ! 5281: ! 5282: switch (code) ! 5283: { ! 5284: case ASHIFT: ! 5285: /* This is the shift itself. If it is wide enough, we will return ! 5286: either the value being shifted if the shift count is equal to ! 5287: COUNT or a shift for the difference. */ ! 5288: if (GET_CODE (XEXP (x, 1)) == CONST_INT ! 5289: && INTVAL (XEXP (x, 1)) >= count) ! 5290: return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), ! 5291: INTVAL (XEXP (x, 1)) - count); ! 5292: break; ! 5293: ! 5294: case NEG: case NOT: ! 5295: if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0) ! 5296: return gen_unary (code, mode, mode, tem); ! 5297: ! 5298: break; ! 5299: ! 5300: case PLUS: case IOR: case XOR: case AND: ! 5301: /* If we can safely shift this constant and we find the inner shift, ! 5302: make a new operation. */ ! 5303: if (GET_CODE (XEXP (x,1)) == CONST_INT ! 5304: && (INTVAL (XEXP (x, 1)) & (((HOST_WIDE_INT) 1 << count)) - 1) == 0 ! 5305: && (tem = extract_left_shift (XEXP (x, 0), count)) != 0) ! 5306: return gen_binary (code, mode, tem, ! 5307: GEN_INT (INTVAL (XEXP (x, 1)) >> count)); ! 5308: ! 5309: break; ! 5310: } ! 5311: ! 5312: return 0; ! 5313: } ! 5314: 1.1 root 5315: /* Look at the expression rooted at X. Look for expressions 5316: equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND. 5317: Form these expressions. 5318: 5319: Return the new rtx, usually just X. 5320: 5321: Also, for machines like the Vax that don't have logical shift insns, 5322: try to convert logical to arithmetic shift operations in cases where 5323: they are equivalent. This undoes the canonicalizations to logical 5324: shifts done elsewhere. 5325: 5326: We try, as much as possible, to re-use rtl expressions to save memory. 5327: 5328: IN_CODE says what kind of expression we are processing. Normally, it is 1.1.1.4 root 5329: SET. In a memory address (inside a MEM, PLUS or minus, the latter two 5330: being kludges), it is MEM. When processing the arguments of a comparison 1.1 root 5331: or a COMPARE against zero, it is COMPARE. */ 5332: 5333: static rtx 5334: make_compound_operation (x, in_code) 5335: rtx x; 5336: enum rtx_code in_code; 5337: { 5338: enum rtx_code code = GET_CODE (x); 5339: enum machine_mode mode = GET_MODE (x); 5340: int mode_width = GET_MODE_BITSIZE (mode); 1.1.1.7 ! root 5341: rtx rhs, lhs; 1.1 root 5342: enum rtx_code next_code; 1.1.1.7 ! root 5343: int i; 1.1 root 5344: rtx new = 0; 1.1.1.5 root 5345: rtx tem; 1.1 root 5346: char *fmt; 5347: 5348: /* Select the code to be used in recursive calls. Once we are inside an 5349: address, we stay there. If we have a comparison, set to COMPARE, 5350: but once inside, go back to our default of SET. */ 5351: 1.1.1.4 root 5352: next_code = (code == MEM || code == PLUS || code == MINUS ? MEM 1.1 root 5353: : ((code == COMPARE || GET_RTX_CLASS (code) == '<') 5354: && XEXP (x, 1) == const0_rtx) ? COMPARE 5355: : in_code == COMPARE ? SET : in_code); 5356: 5357: /* Process depending on the code of this operation. If NEW is set 5358: non-zero, it will be returned. */ 5359: 5360: switch (code) 5361: { 5362: case ASHIFT: 5363: /* Convert shifts by constants into multiplications if inside 5364: an address. */ 5365: if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT 1.1.1.4 root 5366: && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT 1.1 root 5367: && INTVAL (XEXP (x, 1)) >= 0) 1.1.1.5 root 5368: { 5369: new = make_compound_operation (XEXP (x, 0), next_code); 5370: new = gen_rtx_combine (MULT, mode, new, 5371: GEN_INT ((HOST_WIDE_INT) 1 5372: << INTVAL (XEXP (x, 1)))); 5373: } 1.1 root 5374: break; 5375: 5376: case AND: 5377: /* If the second operand is not a constant, we can't do anything 5378: with it. */ 5379: if (GET_CODE (XEXP (x, 1)) != CONST_INT) 5380: break; 5381: 5382: /* If the constant is a power of two minus one and the first operand 5383: is a logical right shift, make an extraction. */ 5384: if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 5385: && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) 1.1.1.5 root 5386: { 5387: new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); 5388: new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1, 5389: 0, in_code == COMPARE); 5390: } 1.1.1.2 root 5391: 1.1 root 5392: /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */ 5393: else if (GET_CODE (XEXP (x, 0)) == SUBREG 5394: && subreg_lowpart_p (XEXP (x, 0)) 5395: && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT 5396: && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) 1.1.1.5 root 5397: { 5398: new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0), 5399: next_code); 1.1.1.7 ! root 5400: new = make_extraction (mode, new, 0, 1.1.1.5 root 5401: XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1, 5402: 0, in_code == COMPARE); 5403: } 1.1.1.7 ! root 5404: /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */ 1.1.1.6 root 5405: else if ((GET_CODE (XEXP (x, 0)) == XOR 5406: || GET_CODE (XEXP (x, 0)) == IOR) 5407: && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT 5408: && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT 5409: && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) 5410: { 5411: /* Apply the distributive law, and then try to make extractions. */ 5412: new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode, 5413: gen_rtx (AND, mode, XEXP (XEXP (x, 0), 0), 5414: XEXP (x, 1)), 5415: gen_rtx (AND, mode, XEXP (XEXP (x, 0), 1), 5416: XEXP (x, 1))); 5417: new = make_compound_operation (new, in_code); 5418: } 1.1.1.3 root 5419: 5420: /* If we are have (and (rotate X C) M) and C is larger than the number 5421: of bits in M, this is an extraction. */ 5422: 5423: else if (GET_CODE (XEXP (x, 0)) == ROTATE 5424: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 5425: && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0 5426: && i <= INTVAL (XEXP (XEXP (x, 0), 1))) 1.1.1.5 root 5427: { 5428: new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); 5429: new = make_extraction (mode, new, 5430: (GET_MODE_BITSIZE (mode) 5431: - INTVAL (XEXP (XEXP (x, 0), 1))), 5432: NULL_RTX, i, 1, 0, in_code == COMPARE); 5433: } 1.1.1.3 root 5434: 5435: /* On machines without logical shifts, if the operand of the AND is 1.1 root 5436: a logical shift and our mask turns off all the propagated sign 5437: bits, we can replace the logical shift with an arithmetic shift. */ 1.1.1.4 root 5438: else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing 5439: && (lshr_optab->handlers[(int) mode].insn_code 5440: == CODE_FOR_nothing) 1.1 root 5441: && GET_CODE (XEXP (x, 0)) == LSHIFTRT 5442: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 5443: && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 1.1.1.4 root 5444: && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT 5445: && mode_width <= HOST_BITS_PER_WIDE_INT) 1.1 root 5446: { 1.1.1.4 root 5447: unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 1.1 root 5448: 5449: mask >>= INTVAL (XEXP (XEXP (x, 0), 1)); 5450: if ((INTVAL (XEXP (x, 1)) & ~mask) == 0) 5451: SUBST (XEXP (x, 0), 1.1.1.5 root 5452: gen_rtx_combine (ASHIFTRT, mode, 5453: make_compound_operation (XEXP (XEXP (x, 0), 0), 5454: next_code), 1.1 root 5455: XEXP (XEXP (x, 0), 1))); 5456: } 5457: 5458: /* If the constant is one less than a power of two, this might be 5459: representable by an extraction even if no shift is present. 5460: If it doesn't end up being a ZERO_EXTEND, we will ignore it unless 5461: we are in a COMPARE. */ 5462: else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) 1.1.1.5 root 5463: new = make_extraction (mode, 5464: make_compound_operation (XEXP (x, 0), 5465: next_code), 5466: 0, NULL_RTX, i, 1, 0, in_code == COMPARE); 1.1 root 5467: 5468: /* If we are in a comparison and this is an AND with a power of two, 5469: convert this into the appropriate bit extract. */ 5470: else if (in_code == COMPARE 5471: && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0) 1.1.1.5 root 5472: new = make_extraction (mode, 5473: make_compound_operation (XEXP (x, 0), 5474: next_code), 5475: i, NULL_RTX, 1, 1, 0, 1); 1.1 root 5476: 5477: break; 5478: 5479: case LSHIFTRT: 5480: /* If the sign bit is known to be zero, replace this with an 5481: arithmetic shift. */ 1.1.1.4 root 5482: if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing 5483: && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing 5484: && mode_width <= HOST_BITS_PER_WIDE_INT 1.1.1.5 root 5485: && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0) 1.1 root 5486: { 1.1.1.5 root 5487: new = gen_rtx_combine (ASHIFTRT, mode, 5488: make_compound_operation (XEXP (x, 0), 5489: next_code), 5490: XEXP (x, 1)); 1.1 root 5491: break; 5492: } 5493: 5494: /* ... fall through ... */ 5495: 5496: case ASHIFTRT: 1.1.1.7 ! root 5497: lhs = XEXP (x, 0); ! 5498: rhs = XEXP (x, 1); ! 5499: 1.1 root 5500: /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1, 5501: this is a SIGN_EXTRACT. */ 1.1.1.7 ! root 5502: if (GET_CODE (rhs) == CONST_INT ! 5503: && GET_CODE (lhs) == ASHIFT ! 5504: && GET_CODE (XEXP (lhs, 1)) == CONST_INT ! 5505: && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))) 1.1.1.5 root 5506: { 1.1.1.7 ! root 5507: new = make_compound_operation (XEXP (lhs, 0), next_code); 1.1.1.5 root 5508: new = make_extraction (mode, new, 1.1.1.7 ! root 5509: INTVAL (rhs) - INTVAL (XEXP (lhs, 1)), ! 5510: NULL_RTX, mode_width - INTVAL (rhs), 1.1.1.4 root 5511: code == LSHIFTRT, 0, in_code == COMPARE); 5512: } 5513: 1.1.1.7 ! root 5514: /* See if we have operations between an ASHIFTRT and an ASHIFT. ! 5515: If so, try to merge the shifts into a SIGN_EXTEND. We could ! 5516: also do this for some cases of SIGN_EXTRACT, but it doesn't ! 5517: seem worth the effort; the case checked for occurs on Alpha. */ ! 5518: ! 5519: if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o' ! 5520: && ! (GET_CODE (lhs) == SUBREG ! 5521: && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o')) ! 5522: && GET_CODE (rhs) == CONST_INT ! 5523: && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT ! 5524: && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0) ! 5525: new = make_extraction (mode, make_compound_operation (new, next_code), ! 5526: 0, NULL_RTX, mode_width - INTVAL (rhs), ! 5527: code == LSHIFTRT, 0, in_code == COMPARE); ! 5528: 1.1 root 5529: break; 1.1.1.5 root 5530: 5531: case SUBREG: 5532: /* Call ourselves recursively on the inner expression. If we are 5533: narrowing the object and it has a different RTL code from 5534: what it originally did, do this SUBREG as a force_to_mode. */ 5535: 5536: tem = make_compound_operation (SUBREG_REG (x), in_code); 5537: if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x)) 5538: && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem)) 5539: && subreg_lowpart_p (x)) 5540: { 5541: rtx newer = force_to_mode (tem, mode, 1.1.1.6 root 5542: GET_MODE_MASK (mode), NULL_RTX, 0); 1.1.1.5 root 5543: 5544: /* If we have something other than a SUBREG, we might have 5545: done an expansion, so rerun outselves. */ 5546: if (GET_CODE (newer) != SUBREG) 5547: newer = make_compound_operation (newer, in_code); 5548: 5549: return newer; 5550: } 1.1 root 5551: } 5552: 5553: if (new) 5554: { 1.1.1.4 root 5555: x = gen_lowpart_for_combine (mode, new); 1.1 root 5556: code = GET_CODE (x); 5557: } 5558: 5559: /* Now recursively process each operand of this operation. */ 5560: fmt = GET_RTX_FORMAT (code); 5561: for (i = 0; i < GET_RTX_LENGTH (code); i++) 5562: if (fmt[i] == 'e') 5563: { 5564: new = make_compound_operation (XEXP (x, i), next_code); 5565: SUBST (XEXP (x, i), new); 5566: } 5567: 5568: return x; 5569: } 5570: 5571: /* Given M see if it is a value that would select a field of bits 5572: within an item, but not the entire word. Return -1 if not. 5573: Otherwise, return the starting position of the field, where 0 is the 5574: low-order bit. 5575: 5576: *PLEN is set to the length of the field. */ 5577: 5578: static int 5579: get_pos_from_mask (m, plen) 1.1.1.4 root 5580: unsigned HOST_WIDE_INT m; 1.1 root 5581: int *plen; 5582: { 5583: /* Get the bit number of the first 1 bit from the right, -1 if none. */ 5584: int pos = exact_log2 (m & - m); 5585: 5586: if (pos < 0) 5587: return -1; 5588: 5589: /* Now shift off the low-order zero bits and see if we have a power of 5590: two minus 1. */ 5591: *plen = exact_log2 ((m >> pos) + 1); 5592: 5593: if (*plen <= 0) 5594: return -1; 5595: 5596: return pos; 5597: } 5598: 1.1.1.6 root 5599: /* See if X can be simplified knowing that we will only refer to it in 5600: MODE and will only refer to those bits that are nonzero in MASK. 5601: If other bits are being computed or if masking operations are done 5602: that select a superset of the bits in MASK, they can sometimes be 5603: ignored. 5604: 5605: Return a possibly simplified expression, but always convert X to 5606: MODE. If X is a CONST_INT, AND the CONST_INT with MASK. 1.1.1.2 root 5607: 5608: Also, if REG is non-zero and X is a register equal in value to REG, 1.1.1.6 root 5609: replace X with REG. 5610: 5611: If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK 5612: are all off in X. This is used when X will be complemented, by either 1.1.1.7 ! root 5613: NOT, NEG, or XOR. */ 1.1.1.2 root 5614: 5615: static rtx 1.1.1.6 root 5616: force_to_mode (x, mode, mask, reg, just_select) 1.1.1.2 root 5617: rtx x; 5618: enum machine_mode mode; 1.1.1.6 root 5619: unsigned HOST_WIDE_INT mask; 1.1.1.2 root 5620: rtx reg; 1.1.1.6 root 5621: int just_select; 1.1.1.2 root 5622: { 5623: enum rtx_code code = GET_CODE (x); 1.1.1.7 ! root 5624: int next_select = just_select || code == XOR || code == NOT || code == NEG; 1.1.1.6 root 5625: enum machine_mode op_mode; 5626: unsigned HOST_WIDE_INT fuller_mask, nonzero; 5627: rtx op0, op1, temp; 5628: 1.1.1.7 ! root 5629: /* If this is a CALL, don't do anything. Some of the code below ! 5630: will do the wrong thing since the mode of a CALL is VOIDmode. */ ! 5631: if (code == CALL) ! 5632: return x; ! 5633: 1.1.1.6 root 5634: /* We want to perform the operation is its present mode unless we know 5635: that the operation is valid in MODE, in which case we do the operation 5636: in MODE. */ 1.1.1.7 ! root 5637: op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x)) ! 5638: && code_to_optab[(int) code] != 0 1.1.1.6 root 5639: && (code_to_optab[(int) code]->handlers[(int) mode].insn_code 5640: != CODE_FOR_nothing)) 5641: ? mode : GET_MODE (x)); 5642: 5643: /* It is not valid to do a right-shift in a narrower mode 5644: than the one it came in with. */ 5645: if ((code == LSHIFTRT || code == ASHIFTRT) 5646: && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x))) 5647: op_mode = GET_MODE (x); 5648: 5649: /* Truncate MASK to fit OP_MODE. */ 5650: if (op_mode) 5651: mask &= GET_MODE_MASK (op_mode); 5652: 5653: /* When we have an arithmetic operation, or a shift whose count we 5654: do not know, we need to assume that all bit the up to the highest-order 5655: bit in MASK will be needed. This is how we form such a mask. */ 5656: if (op_mode) 5657: fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT 5658: ? GET_MODE_MASK (op_mode) 5659: : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1); 5660: else 5661: fuller_mask = ~ (HOST_WIDE_INT) 0; 1.1.1.2 root 5662: 1.1.1.6 root 5663: /* Determine what bits of X are guaranteed to be (non)zero. */ 5664: nonzero = nonzero_bits (x, mode); 5665: 5666: /* If none of the bits in X are needed, return a zero. */ 5667: if (! just_select && (nonzero & mask) == 0) 5668: return const0_rtx; 1.1.1.2 root 5669: 1.1.1.6 root 5670: /* If X is a CONST_INT, return a new one. Do this here since the 5671: test below will fail. */ 5672: if (GET_CODE (x) == CONST_INT) 5673: { 5674: HOST_WIDE_INT cval = INTVAL (x) & mask; 5675: int width = GET_MODE_BITSIZE (mode); 5676: 5677: /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative 5678: number, sign extend it. */ 5679: if (width > 0 && width < HOST_BITS_PER_WIDE_INT 5680: && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) 5681: cval |= (HOST_WIDE_INT) -1 << width; 5682: 5683: return GEN_INT (cval); 5684: } 5685: 1.1.1.7 ! root 5686: /* If X is narrower than MODE and we want all the bits in X's mode, just ! 5687: get X in the proper mode. */ ! 5688: if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode) ! 5689: && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0) 1.1.1.2 root 5690: return gen_lowpart_for_combine (mode, x); 5691: 1.1.1.7 ! root 5692: /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in ! 5693: MASK are already known to be zero in X, we need not do anything. */ ! 5694: if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0) 1.1.1.6 root 5695: return x; 5696: 1.1.1.2 root 5697: switch (code) 5698: { 1.1.1.6 root 5699: case CLOBBER: 5700: /* If X is a (clobber (const_int)), return it since we know we are 5701: generating something that won't match. */ 5702: return x; 5703: 5704: #if ! BITS_BIG_ENDIAN 5705: case USE: 5706: /* X is a (use (mem ..)) that was made from a bit-field extraction that 5707: spanned the boundary of the MEM. If we are now masking so it is 5708: within that boundary, we don't need the USE any more. */ 5709: if ((mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) 5710: return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select); 5711: #endif 5712: 1.1.1.2 root 5713: case SIGN_EXTEND: 5714: case ZERO_EXTEND: 5715: case ZERO_EXTRACT: 5716: case SIGN_EXTRACT: 5717: x = expand_compound_operation (x); 5718: if (GET_CODE (x) != code) 1.1.1.6 root 5719: return force_to_mode (x, mode, mask, reg, next_select); 1.1.1.2 root 5720: break; 5721: 5722: case REG: 5723: if (reg != 0 && (rtx_equal_p (get_last_value (reg), x) 5724: || rtx_equal_p (reg, get_last_value (x)))) 5725: x = reg; 5726: break; 5727: 5728: case SUBREG: 1.1.1.6 root 5729: if (subreg_lowpart_p (x) 1.1.1.7 ! root 5730: /* We can ignore the effect of this SUBREG if it narrows the mode or ! 5731: if the constant masks to zero all the bits the mode doesn't ! 5732: have. */ 1.1.1.6 root 5733: && ((GET_MODE_SIZE (GET_MODE (x)) 5734: < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 5735: || (0 == (mask 5736: & GET_MODE_MASK (GET_MODE (x)) 1.1.1.7 ! root 5737: & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))))))) 1.1.1.6 root 5738: return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select); 1.1.1.2 root 5739: break; 5740: 5741: case AND: 1.1.1.6 root 5742: /* If this is an AND with a constant, convert it into an AND 5743: whose constant is the AND of that constant with MASK. If it 5744: remains an AND of MASK, delete it since it is redundant. */ 1.1.1.2 root 5745: 1.1.1.6 root 5746: if (GET_CODE (XEXP (x, 1)) == CONST_INT 5747: && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT) 1.1.1.2 root 5748: { 1.1.1.6 root 5749: x = simplify_and_const_int (x, op_mode, XEXP (x, 0), 5750: mask & INTVAL (XEXP (x, 1))); 1.1.1.2 root 5751: 5752: /* If X is still an AND, see if it is an AND with a mask that 1.1.1.7 ! root 5753: is just some low-order bits. If so, and it is MASK, we don't ! 5754: need it. */ 1.1.1.2 root 5755: 5756: if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT 1.1.1.6 root 5757: && INTVAL (XEXP (x, 1)) == mask) 1.1.1.2 root 5758: x = XEXP (x, 0); 1.1.1.4 root 5759: 1.1.1.7 ! root 5760: /* If it remains an AND, try making another AND with the bits ! 5761: in the mode mask that aren't in MASK turned on. If the ! 5762: constant in the AND is wide enough, this might make a ! 5763: cheaper constant. */ ! 5764: ! 5765: if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT ! 5766: && GET_MODE_MASK (GET_MODE (x)) != mask) ! 5767: { ! 5768: HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1)) ! 5769: | (GET_MODE_MASK (GET_MODE (x)) & ~ mask)); ! 5770: int width = GET_MODE_BITSIZE (GET_MODE (x)); ! 5771: rtx y; ! 5772: ! 5773: /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative ! 5774: number, sign extend it. */ ! 5775: if (width > 0 && width < HOST_BITS_PER_WIDE_INT ! 5776: && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) ! 5777: cval |= (HOST_WIDE_INT) -1 << width; ! 5778: ! 5779: y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval)); ! 5780: if (rtx_cost (y, SET) < rtx_cost (x, SET)) ! 5781: x = y; ! 5782: } ! 5783: 1.1.1.4 root 5784: break; 1.1.1.2 root 5785: } 5786: 1.1.1.6 root 5787: goto binop; 1.1.1.2 root 5788: 5789: case PLUS: 1.1.1.6 root 5790: /* In (and (plus FOO C1) M), if M is a mask that just turns off 5791: low-order bits (as in an alignment operation) and FOO is already 5792: aligned to that boundary, mask C1 to that boundary as well. 5793: This may eliminate that PLUS and, later, the AND. */ 5794: if (GET_CODE (XEXP (x, 1)) == CONST_INT 5795: && exact_log2 (- mask) >= 0 5796: && (nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0 5797: && (INTVAL (XEXP (x, 1)) & ~ mask) != 0) 5798: return force_to_mode (plus_constant (XEXP (x, 0), 5799: INTVAL (XEXP (x, 1)) & mask), 5800: mode, mask, reg, next_select); 5801: 5802: /* ... fall through ... */ 5803: 1.1.1.2 root 5804: case MINUS: 5805: case MULT: 1.1.1.6 root 5806: /* For PLUS, MINUS and MULT, we need any bits less significant than the 5807: most significant bit in MASK since carries from those bits will 5808: affect the bits we are interested in. */ 5809: mask = fuller_mask; 5810: goto binop; 5811: 1.1.1.2 root 5812: case IOR: 5813: case XOR: 1.1.1.6 root 5814: /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and 5815: LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...) 5816: operation which may be a bitfield extraction. Ensure that the 5817: constant we form is not wider than the mode of X. */ 5818: 5819: if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 5820: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 5821: && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 5822: && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT 5823: && GET_CODE (XEXP (x, 1)) == CONST_INT 5824: && ((INTVAL (XEXP (XEXP (x, 0), 1)) 5825: + floor_log2 (INTVAL (XEXP (x, 1)))) 5826: < GET_MODE_BITSIZE (GET_MODE (x))) 5827: && (INTVAL (XEXP (x, 1)) 5828: & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x)) == 0)) 5829: { 5830: temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask) 5831: << INTVAL (XEXP (XEXP (x, 0), 1))); 5832: temp = gen_binary (GET_CODE (x), GET_MODE (x), 5833: XEXP (XEXP (x, 0), 0), temp); 5834: x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (x, 1)); 5835: return force_to_mode (x, mode, mask, reg, next_select); 5836: } 5837: 5838: binop: 1.1.1.2 root 5839: /* For most binary operations, just propagate into the operation and 1.1.1.6 root 5840: change the mode if we have an operation of that mode. */ 1.1.1.2 root 5841: 1.1.1.6 root 5842: op0 = gen_lowpart_for_combine (op_mode, 5843: force_to_mode (XEXP (x, 0), mode, mask, 5844: reg, next_select)); 5845: op1 = gen_lowpart_for_combine (op_mode, 5846: force_to_mode (XEXP (x, 1), mode, mask, 5847: reg, next_select)); 5848: 5849: /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside 5850: MASK since OP1 might have been sign-extended but we never want 5851: to turn on extra bits, since combine might have previously relied 5852: on them being off. */ 5853: if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR) 5854: && (INTVAL (op1) & mask) != 0) 5855: op1 = GEN_INT (INTVAL (op1) & mask); 5856: 5857: if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) 5858: x = gen_binary (code, op_mode, op0, op1); 1.1.1.4 root 5859: break; 1.1.1.2 root 5860: 5861: case ASHIFT: 5862: /* For left shifts, do the same, but just for the first operand. 1.1.1.5 root 5863: However, we cannot do anything with shifts where we cannot 5864: guarantee that the counts are smaller than the size of the mode 5865: because such a count will have a different meaning in a 1.1.1.6 root 5866: wider mode. */ 1.1.1.5 root 5867: 5868: if (! (GET_CODE (XEXP (x, 1)) == CONST_INT 1.1.1.6 root 5869: && INTVAL (XEXP (x, 1)) >= 0 1.1.1.5 root 5870: && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode)) 5871: && ! (GET_MODE (XEXP (x, 1)) != VOIDmode 5872: && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1))) 5873: < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode)))) 5874: break; 5875: 1.1.1.6 root 5876: /* If the shift count is a constant and we can do arithmetic in 5877: the mode of the shift, refine which bits we need. Otherwise, use the 5878: conservative form of the mask. */ 5879: if (GET_CODE (XEXP (x, 1)) == CONST_INT 5880: && INTVAL (XEXP (x, 1)) >= 0 5881: && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode) 5882: && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT) 5883: mask >>= INTVAL (XEXP (x, 1)); 5884: else 5885: mask = fuller_mask; 5886: 5887: op0 = gen_lowpart_for_combine (op_mode, 5888: force_to_mode (XEXP (x, 0), op_mode, 5889: mask, reg, next_select)); 1.1.1.2 root 5890: 1.1.1.6 root 5891: if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) 5892: x = gen_binary (code, op_mode, op0, XEXP (x, 1)); 1.1.1.4 root 5893: break; 1.1.1.2 root 5894: 5895: case LSHIFTRT: 1.1.1.6 root 5896: /* Here we can only do something if the shift count is a constant, 5897: this shift constant is valid for the host, and we can do arithmetic 5898: in OP_MODE. */ 1.1.1.2 root 5899: 5900: if (GET_CODE (XEXP (x, 1)) == CONST_INT 1.1.1.6 root 5901: && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT 5902: && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT) 1.1.1.4 root 5903: { 1.1.1.6 root 5904: rtx inner = XEXP (x, 0); 1.1.1.4 root 5905: 1.1.1.6 root 5906: /* Select the mask of the bits we need for the shift operand. */ 5907: mask <<= INTVAL (XEXP (x, 1)); 5908: 5909: /* We can only change the mode of the shift if we can do arithmetic 5910: in the mode of the shift and MASK is no wider than the width of 5911: OP_MODE. */ 5912: if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT 5913: || (mask & ~ GET_MODE_MASK (op_mode)) != 0) 1.1.1.4 root 5914: op_mode = GET_MODE (x); 5915: 1.1.1.6 root 5916: inner = force_to_mode (inner, op_mode, mask, reg, next_select); 5917: 5918: if (GET_MODE (x) != op_mode || inner != XEXP (x, 0)) 5919: x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1)); 1.1.1.4 root 5920: } 1.1.1.6 root 5921: 5922: /* If we have (and (lshiftrt FOO C1) C2) where the combination of the 5923: shift and AND produces only copies of the sign bit (C2 is one less 5924: than a power of two), we can do this with just a shift. */ 5925: 5926: if (GET_CODE (x) == LSHIFTRT 5927: && GET_CODE (XEXP (x, 1)) == CONST_INT 5928: && ((INTVAL (XEXP (x, 1)) 5929: + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))) 5930: >= GET_MODE_BITSIZE (GET_MODE (x))) 5931: && exact_log2 (mask + 1) >= 0 5932: && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))) 5933: >= exact_log2 (mask + 1))) 5934: x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), 5935: GEN_INT (GET_MODE_BITSIZE (GET_MODE (x)) 5936: - exact_log2 (mask + 1))); 1.1.1.4 root 5937: break; 5938: 5939: case ASHIFTRT: 1.1.1.6 root 5940: /* If we are just looking for the sign bit, we don't need this shift at 5941: all, even if it has a variable count. */ 5942: if (mask == ((HOST_WIDE_INT) 1 5943: << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))) 5944: return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select); 5945: 5946: /* If this is a shift by a constant, get a mask that contains those bits 5947: that are not copies of the sign bit. We then have two cases: If 5948: MASK only includes those bits, this can be a logical shift, which may 5949: allow simplifications. If MASK is a single-bit field not within 5950: those bits, we are requesting a copy of the sign bit and hence can 5951: shift the sign bit to the appropriate location. */ 5952: 5953: if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0 5954: && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) 5955: { 5956: int i = -1; 5957: 5958: nonzero = GET_MODE_MASK (GET_MODE (x)); 5959: nonzero >>= INTVAL (XEXP (x, 1)); 5960: 5961: if ((mask & ~ nonzero) == 0 5962: || (i = exact_log2 (mask)) >= 0) 5963: { 5964: x = simplify_shift_const 5965: (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0), 5966: i < 0 ? INTVAL (XEXP (x, 1)) 5967: : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i); 5968: 5969: if (GET_CODE (x) != ASHIFTRT) 5970: return force_to_mode (x, mode, mask, reg, next_select); 5971: } 5972: } 5973: 5974: /* If MASK is 1, convert this to a LSHIFTRT. This can be done 5975: even if the shift count isn't a constant. */ 5976: if (mask == 1) 5977: x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1)); 5978: 1.1.1.4 root 5979: /* If this is a sign-extension operation that just affects bits 1.1.1.6 root 5980: we don't care about, remove it. Be sure the call above returned 5981: something that is still a shift. */ 1.1.1.4 root 5982: 1.1.1.6 root 5983: if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT) 5984: && GET_CODE (XEXP (x, 1)) == CONST_INT 1.1.1.4 root 5985: && INTVAL (XEXP (x, 1)) >= 0 1.1.1.6 root 5986: && (INTVAL (XEXP (x, 1)) 5987: <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1)) 1.1.1.4 root 5988: && GET_CODE (XEXP (x, 0)) == ASHIFT 5989: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 5990: && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1))) 1.1.1.6 root 5991: return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask, 5992: reg, next_select); 5993: 1.1.1.2 root 5994: break; 5995: 1.1.1.6 root 5996: case ROTATE: 5997: case ROTATERT: 5998: /* If the shift count is constant and we can do computations 5999: in the mode of X, compute where the bits we care about are. 6000: Otherwise, we can't do anything. Don't change the mode of 6001: the shift or propagate MODE into the shift, though. */ 6002: if (GET_CODE (XEXP (x, 1)) == CONST_INT 6003: && INTVAL (XEXP (x, 1)) >= 0) 6004: { 6005: temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE, 6006: GET_MODE (x), GEN_INT (mask), 6007: XEXP (x, 1)); 1.1.1.7 ! root 6008: if (temp && GET_CODE(temp) == CONST_INT) 1.1.1.6 root 6009: SUBST (XEXP (x, 0), 6010: force_to_mode (XEXP (x, 0), GET_MODE (x), 6011: INTVAL (temp), reg, next_select)); 6012: } 6013: break; 6014: 1.1.1.2 root 6015: case NEG: 1.1.1.7 ! root 6016: /* If we just want the low-order bit, the NEG isn't needed since it ! 6017: won't change the low-order bit. */ ! 6018: if (mask == 1) ! 6019: return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select); ! 6020: 1.1.1.6 root 6021: /* We need any bits less significant than the most significant bit in 6022: MASK since carries from those bits will affect the bits we are 6023: interested in. */ 6024: mask = fuller_mask; 6025: goto unop; 6026: 1.1.1.2 root 6027: case NOT: 1.1.1.6 root 6028: /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the 6029: same as the XOR case above. Ensure that the constant we form is not 6030: wider than the mode of X. */ 6031: 6032: if (GET_CODE (XEXP (x, 0)) == LSHIFTRT 6033: && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 6034: && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 6035: && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask) 6036: < GET_MODE_BITSIZE (GET_MODE (x))) 6037: && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT) 6038: { 6039: temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1))); 6040: temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp); 6041: x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1)); 6042: 6043: return force_to_mode (x, mode, mask, reg, next_select); 6044: } 6045: 6046: unop: 6047: op0 = gen_lowpart_for_combine (op_mode, 6048: force_to_mode (XEXP (x, 0), mode, mask, 6049: reg, next_select)); 6050: if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) 1.1.1.7 ! root 6051: x = gen_unary (code, op_mode, op_mode, op0); 1.1.1.6 root 6052: break; 6053: 6054: case NE: 6055: /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included 6056: in STORE_FLAG_VALUE and FOO has no bits that might be nonzero not 6057: in CONST. */ 6058: if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 0) == const0_rtx 6059: && (nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0) 6060: return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select); 6061: 1.1.1.4 root 6062: break; 6063: 6064: case IF_THEN_ELSE: 6065: /* We have no way of knowing if the IF_THEN_ELSE can itself be 6066: written in a narrower mode. We play it safe and do not do so. */ 6067: 6068: SUBST (XEXP (x, 1), 6069: gen_lowpart_for_combine (GET_MODE (x), 6070: force_to_mode (XEXP (x, 1), mode, 1.1.1.6 root 6071: mask, reg, next_select))); 1.1.1.4 root 6072: SUBST (XEXP (x, 2), 6073: gen_lowpart_for_combine (GET_MODE (x), 6074: force_to_mode (XEXP (x, 2), mode, 1.1.1.6 root 6075: mask, reg,next_select))); 1.1.1.4 root 6076: break; 1.1.1.2 root 6077: } 6078: 1.1.1.4 root 6079: /* Ensure we return a value of the proper mode. */ 1.1.1.2 root 6080: return gen_lowpart_for_combine (mode, x); 6081: } 6082: 1.1.1.7 ! root 6083: /* Return nonzero if X is an expression that has one of two values depending on ! 6084: whether some other value is zero or nonzero. In that case, we return the ! 6085: value that is being tested, *PTRUE is set to the value if the rtx being ! 6086: returned has a nonzero value, and *PFALSE is set to the other alternative. ! 6087: ! 6088: If we return zero, we set *PTRUE and *PFALSE to X. */ ! 6089: ! 6090: static rtx ! 6091: if_then_else_cond (x, ptrue, pfalse) ! 6092: rtx x; ! 6093: rtx *ptrue, *pfalse; ! 6094: { ! 6095: enum machine_mode mode = GET_MODE (x); ! 6096: enum rtx_code code = GET_CODE (x); ! 6097: int size = GET_MODE_BITSIZE (mode); ! 6098: rtx cond0, cond1, true0, true1, false0, false1; ! 6099: unsigned HOST_WIDE_INT nz; ! 6100: ! 6101: /* If this is a unary operation whose operand has one of two values, apply ! 6102: our opcode to compute those values. */ ! 6103: if (GET_RTX_CLASS (code) == '1' ! 6104: && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0) ! 6105: { ! 6106: *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0); ! 6107: *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0); ! 6108: return cond0; ! 6109: } ! 6110: ! 6111: /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would ! 6112: make can't possibly match and would supress other optimizations. */ ! 6113: else if (code == COMPARE) ! 6114: ; ! 6115: ! 6116: /* If this is a binary operation, see if either side has only one of two ! 6117: values. If either one does or if both do and they are conditional on ! 6118: the same value, compute the new true and false values. */ ! 6119: else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2' ! 6120: || GET_RTX_CLASS (code) == '<') ! 6121: { ! 6122: cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0); ! 6123: cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1); ! 6124: ! 6125: if ((cond0 != 0 || cond1 != 0) ! 6126: && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1))) ! 6127: { ! 6128: *ptrue = gen_binary (code, mode, true0, true1); ! 6129: *pfalse = gen_binary (code, mode, false0, false1); ! 6130: return cond0 ? cond0 : cond1; ! 6131: } ! 6132: ! 6133: #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1 ! 6134: ! 6135: /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the ! 6136: operands is zero when the other is non-zero, and vice-versa. */ ! 6137: ! 6138: if ((code == PLUS || code == IOR || code == XOR || code == MINUS ! 6139: || code == UMAX) ! 6140: && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) ! 6141: { ! 6142: rtx op0 = XEXP (XEXP (x, 0), 1); ! 6143: rtx op1 = XEXP (XEXP (x, 1), 1); ! 6144: ! 6145: cond0 = XEXP (XEXP (x, 0), 0); ! 6146: cond1 = XEXP (XEXP (x, 1), 0); ! 6147: ! 6148: if (GET_RTX_CLASS (GET_CODE (cond0)) == '<' ! 6149: && GET_RTX_CLASS (GET_CODE (cond1)) == '<' ! 6150: && reversible_comparison_p (cond1) ! 6151: && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1)) ! 6152: && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) ! 6153: && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) ! 6154: || ((swap_condition (GET_CODE (cond0)) ! 6155: == reverse_condition (GET_CODE (cond1))) ! 6156: && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) ! 6157: && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) ! 6158: && ! side_effects_p (x)) ! 6159: { ! 6160: *ptrue = gen_binary (MULT, mode, op0, const_true_rtx); ! 6161: *pfalse = gen_binary (MULT, mode, ! 6162: (code == MINUS ! 6163: ? gen_unary (NEG, mode, mode, op1) : op1), ! 6164: const_true_rtx); ! 6165: return cond0; ! 6166: } ! 6167: } ! 6168: ! 6169: /* Similarly for MULT, AND and UMIN, execpt that for these the result ! 6170: is always zero. */ ! 6171: if ((code == MULT || code == AND || code == UMIN) ! 6172: && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) ! 6173: { ! 6174: cond0 = XEXP (XEXP (x, 0), 0); ! 6175: cond1 = XEXP (XEXP (x, 1), 0); ! 6176: ! 6177: if (GET_RTX_CLASS (GET_CODE (cond0)) == '<' ! 6178: && GET_RTX_CLASS (GET_CODE (cond1)) == '<' ! 6179: && reversible_comparison_p (cond1) ! 6180: && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1)) ! 6181: && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) ! 6182: && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) ! 6183: || ((swap_condition (GET_CODE (cond0)) ! 6184: == reverse_condition (GET_CODE (cond1))) ! 6185: && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) ! 6186: && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) ! 6187: && ! side_effects_p (x)) ! 6188: { ! 6189: *ptrue = *pfalse = const0_rtx; ! 6190: return cond0; ! 6191: } ! 6192: } ! 6193: #endif ! 6194: } ! 6195: ! 6196: else if (code == IF_THEN_ELSE) ! 6197: { ! 6198: /* If we have IF_THEN_ELSE already, extract the condition and ! 6199: canonicalize it if it is NE or EQ. */ ! 6200: cond0 = XEXP (x, 0); ! 6201: *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2); ! 6202: if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx) ! 6203: return XEXP (cond0, 0); ! 6204: else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx) ! 6205: { ! 6206: *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1); ! 6207: return XEXP (cond0, 0); ! 6208: } ! 6209: else ! 6210: return cond0; ! 6211: } ! 6212: ! 6213: /* If X is a normal SUBREG with both inner and outer modes integral, ! 6214: we can narrow both the true and false values of the inner expression, ! 6215: if there is a condition. */ ! 6216: else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT ! 6217: && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT ! 6218: && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) ! 6219: && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x), ! 6220: &true0, &false0))) ! 6221: { ! 6222: *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0); ! 6223: *pfalse ! 6224: = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0); ! 6225: ! 6226: return cond0; ! 6227: } ! 6228: ! 6229: /* If X is a constant, this isn't special and will cause confusions ! 6230: if we treat it as such. Likewise if it is equivalent to a constant. */ ! 6231: else if (CONSTANT_P (x) ! 6232: || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0))) ! 6233: ; ! 6234: ! 6235: /* If X is known to be either 0 or -1, those are the true and ! 6236: false values when testing X. */ ! 6237: else if (num_sign_bit_copies (x, mode) == size) ! 6238: { ! 6239: *ptrue = constm1_rtx, *pfalse = const0_rtx; ! 6240: return x; ! 6241: } ! 6242: ! 6243: /* Likewise for 0 or a single bit. */ ! 6244: else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0) ! 6245: { ! 6246: *ptrue = GEN_INT (nz), *pfalse = const0_rtx; ! 6247: return x; ! 6248: } ! 6249: ! 6250: /* Otherwise fail; show no condition with true and false values the same. */ ! 6251: *ptrue = *pfalse = x; ! 6252: return 0; ! 6253: } ! 6254: 1.1.1.4 root 6255: /* Return the value of expression X given the fact that condition COND 6256: is known to be true when applied to REG as its first operand and VAL 6257: as its second. X is known to not be shared and so can be modified in 6258: place. 6259: 6260: We only handle the simplest cases, and specifically those cases that 6261: arise with IF_THEN_ELSE expressions. */ 6262: 6263: static rtx 6264: known_cond (x, cond, reg, val) 6265: rtx x; 6266: enum rtx_code cond; 6267: rtx reg, val; 6268: { 6269: enum rtx_code code = GET_CODE (x); 1.1.1.7 ! root 6270: rtx temp; 1.1.1.4 root 6271: char *fmt; 6272: int i, j; 6273: 6274: if (side_effects_p (x)) 6275: return x; 6276: 6277: if (cond == EQ && rtx_equal_p (x, reg)) 6278: return val; 6279: 6280: /* If X is (abs REG) and we know something about REG's relationship 6281: with zero, we may be able to simplify this. */ 6282: 6283: if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx) 6284: switch (cond) 6285: { 6286: case GE: case GT: case EQ: 6287: return XEXP (x, 0); 6288: case LT: case LE: 1.1.1.7 ! root 6289: return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)), ! 6290: XEXP (x, 0)); 1.1.1.4 root 6291: } 6292: 6293: /* The only other cases we handle are MIN, MAX, and comparisons if the 6294: operands are the same as REG and VAL. */ 6295: 6296: else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c') 6297: { 6298: if (rtx_equal_p (XEXP (x, 0), val)) 6299: cond = swap_condition (cond), temp = val, val = reg, reg = temp; 6300: 6301: if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val)) 6302: { 6303: if (GET_RTX_CLASS (code) == '<') 6304: return (comparison_dominates_p (cond, code) ? const_true_rtx 6305: : (comparison_dominates_p (cond, 6306: reverse_condition (code)) 6307: ? const0_rtx : x)); 6308: 6309: else if (code == SMAX || code == SMIN 6310: || code == UMIN || code == UMAX) 6311: { 6312: int unsignedp = (code == UMIN || code == UMAX); 6313: 6314: if (code == SMAX || code == UMAX) 6315: cond = reverse_condition (cond); 6316: 6317: switch (cond) 6318: { 6319: case GE: case GT: 6320: return unsignedp ? x : XEXP (x, 1); 6321: case LE: case LT: 6322: return unsignedp ? x : XEXP (x, 0); 6323: case GEU: case GTU: 6324: return unsignedp ? XEXP (x, 1) : x; 6325: case LEU: case LTU: 6326: return unsignedp ? XEXP (x, 0) : x; 6327: } 6328: } 6329: } 6330: } 6331: 6332: fmt = GET_RTX_FORMAT (code); 6333: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 6334: { 6335: if (fmt[i] == 'e') 6336: SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val)); 6337: else if (fmt[i] == 'E') 6338: for (j = XVECLEN (x, i) - 1; j >= 0; j--) 6339: SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j), 6340: cond, reg, val)); 6341: } 6342: 6343: return x; 6344: } 6345: 1.1 root 6346: /* See if X, a SET operation, can be rewritten as a bit-field assignment. 6347: Return that assignment if so. 6348: 6349: We only handle the most common cases. */ 6350: 6351: static rtx 6352: make_field_assignment (x) 6353: rtx x; 6354: { 6355: rtx dest = SET_DEST (x); 6356: rtx src = SET_SRC (x); 1.1.1.2 root 6357: rtx assign; 1.1.1.4 root 6358: HOST_WIDE_INT c1; 6359: int pos, len; 1.1.1.2 root 6360: rtx other; 6361: enum machine_mode mode; 1.1 root 6362: 6363: /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is 6364: a clear of a one-bit field. We will have changed it to 6365: (and (rotate (const_int -2) POS) DEST), so check for that. Also check 6366: for a SUBREG. */ 6367: 6368: if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE 6369: && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT 6370: && INTVAL (XEXP (XEXP (src, 0), 0)) == -2 1.1.1.2 root 6371: && (rtx_equal_p (dest, XEXP (src, 1)) 6372: || rtx_equal_p (dest, get_last_value (XEXP (src, 1))) 6373: || rtx_equal_p (get_last_value (dest), XEXP (src, 1)))) 1.1 root 6374: { 1.1.1.5 root 6375: assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), 1.1 root 6376: 1, 1, 1, 0); 1.1.1.2 root 6377: return gen_rtx (SET, VOIDmode, assign, const0_rtx); 1.1 root 6378: } 6379: 6380: else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG 6381: && subreg_lowpart_p (XEXP (src, 0)) 6382: && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0))) 6383: < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0))))) 6384: && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE 6385: && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2 1.1.1.2 root 6386: && (rtx_equal_p (dest, XEXP (src, 1)) 6387: || rtx_equal_p (dest, get_last_value (XEXP (src, 1))) 6388: || rtx_equal_p (get_last_value (dest), XEXP (src, 1)))) 1.1 root 6389: { 1.1.1.5 root 6390: assign = make_extraction (VOIDmode, dest, 0, 1.1 root 6391: XEXP (SUBREG_REG (XEXP (src, 0)), 1), 6392: 1, 1, 1, 0); 1.1.1.2 root 6393: return gen_rtx (SET, VOIDmode, assign, const0_rtx); 1.1 root 6394: } 6395: 6396: /* If SRC is (ior (ashift (const_int 1) POS DEST)), this is a set of a 6397: one-bit field. */ 6398: else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT 6399: && XEXP (XEXP (src, 0), 0) == const1_rtx 1.1.1.2 root 6400: && (rtx_equal_p (dest, XEXP (src, 1)) 6401: || rtx_equal_p (dest, get_last_value (XEXP (src, 1))) 6402: || rtx_equal_p (get_last_value (dest), XEXP (src, 1)))) 1.1 root 6403: { 1.1.1.5 root 6404: assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), 1.1 root 6405: 1, 1, 1, 0); 1.1.1.2 root 6406: return gen_rtx (SET, VOIDmode, assign, const1_rtx); 1.1 root 6407: } 6408: 1.1.1.2 root 6409: /* The other case we handle is assignments into a constant-position 6410: field. They look like (ior (and DEST C1) OTHER). If C1 represents 6411: a mask that has all one bits except for a group of zero bits and 6412: OTHER is known to have zeros where C1 has ones, this is such an 6413: assignment. Compute the position and length from C1. Shift OTHER 6414: to the appropriate position, force it to the required mode, and 6415: make the extraction. Check for the AND in both operands. */ 6416: 6417: if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == AND 6418: && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT 6419: && (rtx_equal_p (XEXP (XEXP (src, 0), 0), dest) 6420: || rtx_equal_p (XEXP (XEXP (src, 0), 0), get_last_value (dest)) 6421: || rtx_equal_p (get_last_value (XEXP (XEXP (src, 0), 1)), dest))) 6422: c1 = INTVAL (XEXP (XEXP (src, 0), 1)), other = XEXP (src, 1); 6423: else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 1)) == AND 6424: && GET_CODE (XEXP (XEXP (src, 1), 1)) == CONST_INT 6425: && (rtx_equal_p (XEXP (XEXP (src, 1), 0), dest) 6426: || rtx_equal_p (XEXP (XEXP (src, 1), 0), get_last_value (dest)) 6427: || rtx_equal_p (get_last_value (XEXP (XEXP (src, 1), 0)), 6428: dest))) 6429: c1 = INTVAL (XEXP (XEXP (src, 1), 1)), other = XEXP (src, 0); 6430: else 6431: return x; 1.1 root 6432: 1.1.1.6 root 6433: pos = get_pos_from_mask (c1 ^ GET_MODE_MASK (GET_MODE (dest)), &len); 1.1.1.2 root 6434: if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest)) 1.1.1.4 root 6435: || (GET_MODE_BITSIZE (GET_MODE (other)) <= HOST_BITS_PER_WIDE_INT 1.1.1.5 root 6436: && (c1 & nonzero_bits (other, GET_MODE (other))) != 0)) 1.1.1.2 root 6437: return x; 1.1 root 6438: 1.1.1.4 root 6439: assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0); 1.1 root 6440: 1.1.1.2 root 6441: /* The mode to use for the source is the mode of the assignment, or of 6442: what is inside a possible STRICT_LOW_PART. */ 6443: mode = (GET_CODE (assign) == STRICT_LOW_PART 6444: ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign)); 1.1 root 6445: 1.1.1.2 root 6446: /* Shift OTHER right POS places and make it the source, restricting it 6447: to the proper length and mode. */ 1.1 root 6448: 1.1.1.4 root 6449: src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT, 6450: GET_MODE (src), other, pos), 1.1.1.6 root 6451: mode, 6452: GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT 6453: ? GET_MODE_MASK (mode) 6454: : ((HOST_WIDE_INT) 1 << len) - 1, 6455: dest, 0); 1.1 root 6456: 1.1.1.2 root 6457: return gen_rtx_combine (SET, VOIDmode, assign, src); 1.1 root 6458: } 6459: 6460: /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c) 6461: if so. */ 6462: 6463: static rtx 6464: apply_distributive_law (x) 6465: rtx x; 6466: { 6467: enum rtx_code code = GET_CODE (x); 6468: rtx lhs, rhs, other; 6469: rtx tem; 6470: enum rtx_code inner_code; 6471: 1.1.1.5 root 6472: /* Distributivity is not true for floating point. 6473: It can change the value. So don't do it. 6474: -- rms and [email protected]. */ 1.1.1.6 root 6475: if (FLOAT_MODE_P (GET_MODE (x))) 1.1.1.5 root 6476: return x; 6477: 1.1 root 6478: /* The outer operation can only be one of the following: */ 6479: if (code != IOR && code != AND && code != XOR 6480: && code != PLUS && code != MINUS) 6481: return x; 6482: 6483: lhs = XEXP (x, 0), rhs = XEXP (x, 1); 6484: 1.1.1.2 root 6485: /* If either operand is a primitive we can't do anything, so get out fast. */ 1.1 root 6486: if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o' 1.1.1.2 root 6487: || GET_RTX_CLASS (GET_CODE (rhs)) == 'o') 1.1 root 6488: return x; 6489: 6490: lhs = expand_compound_operation (lhs); 6491: rhs = expand_compound_operation (rhs); 6492: inner_code = GET_CODE (lhs); 6493: if (inner_code != GET_CODE (rhs)) 6494: return x; 6495: 6496: /* See if the inner and outer operations distribute. */ 6497: switch (inner_code) 6498: { 6499: case LSHIFTRT: 6500: case ASHIFTRT: 6501: case AND: 6502: case IOR: 6503: /* These all distribute except over PLUS. */ 6504: if (code == PLUS || code == MINUS) 6505: return x; 6506: break; 6507: 6508: case MULT: 6509: if (code != PLUS && code != MINUS) 6510: return x; 6511: break; 6512: 6513: case ASHIFT: 1.1.1.7 ! root 6514: /* This is also a multiply, so it distributes over everything. */ 1.1 root 6515: break; 6516: 6517: case SUBREG: 1.1.1.2 root 6518: /* Non-paradoxical SUBREGs distributes over all operations, provided 6519: the inner modes and word numbers are the same, this is an extraction 1.1.1.3 root 6520: of a low-order part, we don't convert an fp operation to int or 6521: vice versa, and we would not be converting a single-word 1.1.1.2 root 6522: operation into a multi-word operation. The latter test is not 1.1.1.3 root 6523: required, but it prevents generating unneeded multi-word operations. 1.1.1.2 root 6524: Some of the previous tests are redundant given the latter test, but 6525: are retained because they are required for correctness. 6526: 6527: We produce the result slightly differently in this case. */ 6528: 6529: if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs)) 6530: || SUBREG_WORD (lhs) != SUBREG_WORD (rhs) 6531: || ! subreg_lowpart_p (lhs) 1.1.1.3 root 6532: || (GET_MODE_CLASS (GET_MODE (lhs)) 6533: != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs)))) 1.1.1.2 root 6534: || (GET_MODE_SIZE (GET_MODE (lhs)) 6535: < GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs)))) 6536: || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD) 1.1 root 6537: return x; 6538: 6539: tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)), 6540: SUBREG_REG (lhs), SUBREG_REG (rhs)); 6541: return gen_lowpart_for_combine (GET_MODE (x), tem); 6542: 6543: default: 6544: return x; 6545: } 6546: 6547: /* Set LHS and RHS to the inner operands (A and B in the example 6548: above) and set OTHER to the common operand (C in the example). 6549: These is only one way to do this unless the inner operation is 6550: commutative. */ 6551: if (GET_RTX_CLASS (inner_code) == 'c' 6552: && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0))) 6553: other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1); 6554: else if (GET_RTX_CLASS (inner_code) == 'c' 6555: && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1))) 6556: other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0); 6557: else if (GET_RTX_CLASS (inner_code) == 'c' 6558: && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0))) 6559: other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1); 6560: else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1))) 6561: other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0); 6562: else 6563: return x; 6564: 6565: /* Form the new inner operation, seeing if it simplifies first. */ 6566: tem = gen_binary (code, GET_MODE (x), lhs, rhs); 6567: 6568: /* There is one exception to the general way of distributing: 6569: (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */ 6570: if (code == XOR && inner_code == IOR) 6571: { 6572: inner_code = AND; 1.1.1.7 ! root 6573: other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other); 1.1 root 6574: } 6575: 6576: /* We may be able to continuing distributing the result, so call 6577: ourselves recursively on the inner operation before forming the 6578: outer operation, which we return. */ 6579: return gen_binary (inner_code, GET_MODE (x), 6580: apply_distributive_law (tem), other); 6581: } 6582: 6583: /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done 6584: in MODE. 6585: 6586: Return an equivalent form, if different from X. Otherwise, return X. If 6587: X is zero, we are to always construct the equivalent form. */ 6588: 6589: static rtx 6590: simplify_and_const_int (x, mode, varop, constop) 6591: rtx x; 6592: enum machine_mode mode; 6593: rtx varop; 1.1.1.4 root 6594: unsigned HOST_WIDE_INT constop; 1.1 root 6595: { 1.1.1.5 root 6596: unsigned HOST_WIDE_INT nonzero; 1.1.1.6 root 6597: int i; 1.1 root 6598: 1.1.1.6 root 6599: /* Simplify VAROP knowing that we will be only looking at some of the 6600: bits in it. */ 6601: varop = force_to_mode (varop, mode, constop, NULL_RTX, 0); 6602: 6603: /* If VAROP is a CLOBBER, we will fail so return it; if it is a 6604: CONST_INT, we are done. */ 6605: if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT) 6606: return varop; 1.1 root 6607: 1.1.1.5 root 6608: /* See what bits may be nonzero in VAROP. Unlike the general case of 6609: a call to nonzero_bits, here we don't care about bits outside 6610: MODE. */ 6611: 6612: nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode); 1.1 root 6613: 6614: /* Turn off all bits in the constant that are known to already be zero. 1.1.1.5 root 6615: Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS 1.1 root 6616: which is tested below. */ 6617: 1.1.1.5 root 6618: constop &= nonzero; 1.1 root 6619: 6620: /* If we don't have any bits left, return zero. */ 6621: if (constop == 0) 6622: return const0_rtx; 6623: 1.1.1.6 root 6624: /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is 6625: a power of two, we can replace this with a ASHIFT. */ 6626: if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1 6627: && (i = exact_log2 (constop)) >= 0) 6628: return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i); 6629: 6630: /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR 6631: or XOR, then try to apply the distributive law. This may eliminate 6632: operations if either branch can be simplified because of the AND. 6633: It may also make some cases more complex, but those cases probably 6634: won't match a pattern either with or without this. */ 6635: 6636: if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR) 6637: return 6638: gen_lowpart_for_combine 6639: (mode, 6640: apply_distributive_law 6641: (gen_binary (GET_CODE (varop), GET_MODE (varop), 6642: simplify_and_const_int (NULL_RTX, GET_MODE (varop), 6643: XEXP (varop, 0), constop), 6644: simplify_and_const_int (NULL_RTX, GET_MODE (varop), 6645: XEXP (varop, 1), constop)))); 6646: 1.1 root 6647: /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG 6648: if we already had one (just check for the simplest cases). */ 6649: if (x && GET_CODE (XEXP (x, 0)) == SUBREG 6650: && GET_MODE (XEXP (x, 0)) == mode 6651: && SUBREG_REG (XEXP (x, 0)) == varop) 6652: varop = XEXP (x, 0); 6653: else 6654: varop = gen_lowpart_for_combine (mode, varop); 6655: 6656: /* If we can't make the SUBREG, try to return what we were given. */ 6657: if (GET_CODE (varop) == CLOBBER) 6658: return x ? x : varop; 6659: 6660: /* If we are only masking insignificant bits, return VAROP. */ 1.1.1.5 root 6661: if (constop == nonzero) 1.1 root 6662: x = varop; 6663: 6664: /* Otherwise, return an AND. See how much, if any, of X we can use. */ 6665: else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode) 1.1.1.6 root 6666: x = gen_binary (AND, mode, varop, GEN_INT (constop)); 1.1 root 6667: 6668: else 6669: { 6670: if (GET_CODE (XEXP (x, 1)) != CONST_INT 6671: || INTVAL (XEXP (x, 1)) != constop) 1.1.1.4 root 6672: SUBST (XEXP (x, 1), GEN_INT (constop)); 1.1 root 6673: 6674: SUBST (XEXP (x, 0), varop); 6675: } 6676: 6677: return x; 6678: } 6679: 6680: /* Given an expression, X, compute which bits in X can be non-zero. 6681: We don't care about bits outside of those defined in MODE. 6682: 6683: For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is 6684: a shift, AND, or zero_extract, we can do better. */ 6685: 1.1.1.4 root 6686: static unsigned HOST_WIDE_INT 1.1.1.5 root 6687: nonzero_bits (x, mode) 1.1 root 6688: rtx x; 6689: enum machine_mode mode; 6690: { 1.1.1.5 root 6691: unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode); 6692: unsigned HOST_WIDE_INT inner_nz; 1.1 root 6693: enum rtx_code code; 6694: int mode_width = GET_MODE_BITSIZE (mode); 6695: rtx tem; 6696: 1.1.1.7 ! root 6697: /* For floating-point values, assume all bits are needed. */ ! 6698: if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode)) ! 6699: return nonzero; ! 6700: 1.1 root 6701: /* If X is wider than MODE, use its mode instead. */ 6702: if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width) 6703: { 6704: mode = GET_MODE (x); 1.1.1.5 root 6705: nonzero = GET_MODE_MASK (mode); 1.1 root 6706: mode_width = GET_MODE_BITSIZE (mode); 6707: } 6708: 1.1.1.4 root 6709: if (mode_width > HOST_BITS_PER_WIDE_INT) 1.1 root 6710: /* Our only callers in this case look for single bit values. So 6711: just return the mode mask. Those tests will then be false. */ 1.1.1.5 root 6712: return nonzero; 1.1 root 6713: 1.1.1.6 root 6714: #ifndef WORD_REGISTER_OPERATIONS 6715: /* If MODE is wider than X, but both are a single word for both the host 6716: and target machines, we can compute this from which bits of the 6717: object might be nonzero in its own mode, taking into account the fact 6718: that on many CISC machines, accessing an object in a wider mode 6719: causes the high-order bits to become undefined. So they are 6720: not known to be zero. */ 6721: 6722: if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode 6723: && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD 6724: && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 6725: && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x))) 6726: { 6727: nonzero &= nonzero_bits (x, GET_MODE (x)); 6728: nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)); 6729: return nonzero; 6730: } 6731: #endif 6732: 1.1 root 6733: code = GET_CODE (x); 6734: switch (code) 6735: { 6736: case REG: 6737: #ifdef STACK_BOUNDARY 6738: /* If this is the stack pointer, we may know something about its 6739: alignment. If PUSH_ROUNDING is defined, it is possible for the 6740: stack to be momentarily aligned only to that amount, so we pick 6741: the least alignment. */ 6742: 6743: if (x == stack_pointer_rtx) 6744: { 6745: int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT; 6746: 6747: #ifdef PUSH_ROUNDING 6748: sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment); 6749: #endif 6750: 1.1.1.5 root 6751: return nonzero & ~ (sp_alignment - 1); 1.1 root 6752: } 6753: #endif 6754: 1.1.1.5 root 6755: /* If X is a register whose nonzero bits value is current, use it. 6756: Otherwise, if X is a register whose value we can find, use that 6757: value. Otherwise, use the previously-computed global nonzero bits 6758: for this register. */ 6759: 6760: if (reg_last_set_value[REGNO (x)] != 0 6761: && reg_last_set_mode[REGNO (x)] == mode 6762: && (reg_n_sets[REGNO (x)] == 1 6763: || reg_last_set_label[REGNO (x)] == label_tick) 6764: && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid) 6765: return reg_last_set_nonzero_bits[REGNO (x)]; 1.1 root 6766: 6767: tem = get_last_value (x); 1.1.1.5 root 6768: 1.1 root 6769: if (tem) 1.1.1.5 root 6770: { 6771: #ifdef SHORT_IMMEDIATES_SIGN_EXTEND 6772: /* If X is narrower than MODE and TEM is a non-negative 6773: constant that would appear negative in the mode of X, 6774: sign-extend it for use in reg_nonzero_bits because some 6775: machines (maybe most) will actually do the sign-extension 6776: and this is the conservative approach. 6777: 6778: ??? For 2.5, try to tighten up the MD files in this regard 6779: instead of this kludge. */ 6780: 6781: if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width 6782: && GET_CODE (tem) == CONST_INT 6783: && INTVAL (tem) > 0 6784: && 0 != (INTVAL (tem) 6785: & ((HOST_WIDE_INT) 1 1.1.1.7 ! root 6786: << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) 1.1.1.5 root 6787: tem = GEN_INT (INTVAL (tem) 6788: | ((HOST_WIDE_INT) (-1) 6789: << GET_MODE_BITSIZE (GET_MODE (x)))); 6790: #endif 6791: return nonzero_bits (tem, mode); 6792: } 6793: else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)]) 6794: return reg_nonzero_bits[REGNO (x)] & nonzero; 1.1 root 6795: else 1.1.1.5 root 6796: return nonzero; 1.1 root 6797: 6798: case CONST_INT: 1.1.1.5 root 6799: #ifdef SHORT_IMMEDIATES_SIGN_EXTEND 6800: /* If X is negative in MODE, sign-extend the value. */ 1.1.1.7 ! root 6801: if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD ! 6802: && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1)))) ! 6803: return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width)); 1.1.1.5 root 6804: #endif 6805: 1.1 root 6806: return INTVAL (x); 6807: 6808: case MEM: 1.1.1.6 root 6809: #ifdef LOAD_EXTEND_OP 1.1 root 6810: /* In many, if not most, RISC machines, reading a byte from memory 6811: zeros the rest of the register. Noticing that fact saves a lot 6812: of extra zero-extends. */ 1.1.1.6 root 6813: if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND) 6814: nonzero &= GET_MODE_MASK (GET_MODE (x)); 1.1 root 6815: #endif 1.1.1.6 root 6816: break; 1.1 root 6817: 6818: case EQ: case NE: 6819: case GT: case GTU: 6820: case LT: case LTU: 6821: case GE: case GEU: 6822: case LE: case LEU: 1.1.1.3 root 6823: 1.1.1.6 root 6824: /* If this produces an integer result, we know which bits are set. 6825: Code here used to clear bits outside the mode of X, but that is 6826: now done above. */ 1.1 root 6827: 1.1.1.6 root 6828: if (GET_MODE_CLASS (mode) == MODE_INT 6829: && mode_width <= HOST_BITS_PER_WIDE_INT) 6830: nonzero = STORE_FLAG_VALUE; 1.1 root 6831: break; 6832: 6833: case NEG: 1.1.1.4 root 6834: if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x)) 6835: == GET_MODE_BITSIZE (GET_MODE (x))) 1.1.1.5 root 6836: nonzero = 1; 1.1 root 6837: 6838: if (GET_MODE_SIZE (GET_MODE (x)) < mode_width) 1.1.1.5 root 6839: nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x))); 1.1 root 6840: break; 1.1.1.4 root 6841: 6842: case ABS: 6843: if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x)) 6844: == GET_MODE_BITSIZE (GET_MODE (x))) 1.1.1.5 root 6845: nonzero = 1; 1.1.1.4 root 6846: break; 1.1 root 6847: 6848: case TRUNCATE: 1.1.1.5 root 6849: nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode)); 1.1 root 6850: break; 6851: 6852: case ZERO_EXTEND: 1.1.1.5 root 6853: nonzero &= nonzero_bits (XEXP (x, 0), mode); 1.1 root 6854: if (GET_MODE (XEXP (x, 0)) != VOIDmode) 1.1.1.5 root 6855: nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0))); 1.1 root 6856: break; 6857: 6858: case SIGN_EXTEND: 6859: /* If the sign bit is known clear, this is the same as ZERO_EXTEND. 6860: Otherwise, show all the bits in the outer mode but not the inner 6861: may be non-zero. */ 1.1.1.5 root 6862: inner_nz = nonzero_bits (XEXP (x, 0), mode); 1.1 root 6863: if (GET_MODE (XEXP (x, 0)) != VOIDmode) 6864: { 1.1.1.5 root 6865: inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0))); 6866: if (inner_nz & 1.1.1.4 root 6867: (((HOST_WIDE_INT) 1 6868: << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))) 1.1.1.5 root 6869: inner_nz |= (GET_MODE_MASK (mode) 1.1 root 6870: & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))); 6871: } 6872: 1.1.1.5 root 6873: nonzero &= inner_nz; 1.1 root 6874: break; 6875: 6876: case AND: 1.1.1.5 root 6877: nonzero &= (nonzero_bits (XEXP (x, 0), mode) 6878: & nonzero_bits (XEXP (x, 1), mode)); 1.1 root 6879: break; 6880: 1.1.1.4 root 6881: case XOR: case IOR: 6882: case UMIN: case UMAX: case SMIN: case SMAX: 1.1.1.5 root 6883: nonzero &= (nonzero_bits (XEXP (x, 0), mode) 6884: | nonzero_bits (XEXP (x, 1), mode)); 1.1 root 6885: break; 6886: 6887: case PLUS: case MINUS: 6888: case MULT: 6889: case DIV: case UDIV: 6890: case MOD: case UMOD: 6891: /* We can apply the rules of arithmetic to compute the number of 6892: high- and low-order zero bits of these operations. We start by 6893: computing the width (position of the highest-order non-zero bit) 6894: and the number of low-order zero bits for each value. */ 6895: { 1.1.1.5 root 6896: unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode); 6897: unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode); 6898: int width0 = floor_log2 (nz0) + 1; 6899: int width1 = floor_log2 (nz1) + 1; 6900: int low0 = floor_log2 (nz0 & -nz0); 6901: int low1 = floor_log2 (nz1 & -nz1); 1.1.1.7 ! root 6902: HOST_WIDE_INT op0_maybe_minusp ! 6903: = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1))); ! 6904: HOST_WIDE_INT op1_maybe_minusp ! 6905: = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1))); 1.1 root 6906: int result_width = mode_width; 6907: int result_low = 0; 6908: 6909: switch (code) 6910: { 6911: case PLUS: 6912: result_width = MAX (width0, width1) + 1; 6913: result_low = MIN (low0, low1); 6914: break; 6915: case MINUS: 6916: result_low = MIN (low0, low1); 6917: break; 6918: case MULT: 6919: result_width = width0 + width1; 6920: result_low = low0 + low1; 6921: break; 6922: case DIV: 6923: if (! op0_maybe_minusp && ! op1_maybe_minusp) 6924: result_width = width0; 6925: break; 6926: case UDIV: 6927: result_width = width0; 6928: break; 6929: case MOD: 6930: if (! op0_maybe_minusp && ! op1_maybe_minusp) 6931: result_width = MIN (width0, width1); 6932: result_low = MIN (low0, low1); 6933: break; 6934: case UMOD: 6935: result_width = MIN (width0, width1); 6936: result_low = MIN (low0, low1); 6937: break; 6938: } 6939: 6940: if (result_width < mode_width) 1.1.1.5 root 6941: nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1; 1.1 root 6942: 6943: if (result_low > 0) 1.1.1.5 root 6944: nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1); 1.1 root 6945: } 6946: break; 6947: 6948: case ZERO_EXTRACT: 6949: if (GET_CODE (XEXP (x, 1)) == CONST_INT 1.1.1.4 root 6950: && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) 1.1.1.5 root 6951: nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1; 1.1 root 6952: break; 6953: 6954: case SUBREG: 1.1.1.4 root 6955: /* If this is a SUBREG formed for a promoted variable that has 6956: been zero-extended, we know that at least the high-order bits 6957: are zero, though others might be too. */ 6958: 6959: if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x)) 1.1.1.5 root 6960: nonzero = (GET_MODE_MASK (GET_MODE (x)) 6961: & nonzero_bits (SUBREG_REG (x), GET_MODE (x))); 1.1.1.4 root 6962: 1.1 root 6963: /* If the inner mode is a single word for both the host and target 6964: machines, we can compute this from which bits of the inner 1.1.1.5 root 6965: object might be nonzero. */ 1.1 root 6966: if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD 1.1.1.4 root 6967: && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) 6968: <= HOST_BITS_PER_WIDE_INT)) 1.1 root 6969: { 1.1.1.5 root 6970: nonzero &= nonzero_bits (SUBREG_REG (x), mode); 1.1.1.6 root 6971: 6972: #ifndef WORD_REGISTER_OPERATIONS 1.1 root 6973: /* On many CISC machines, accessing an object in a wider mode 6974: causes the high-order bits to become undefined. So they are 6975: not known to be zero. */ 6976: if (GET_MODE_SIZE (GET_MODE (x)) 6977: > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 1.1.1.5 root 6978: nonzero |= (GET_MODE_MASK (GET_MODE (x)) 6979: & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))); 1.1 root 6980: #endif 6981: } 6982: break; 6983: 6984: case ASHIFTRT: 6985: case LSHIFTRT: 6986: case ASHIFT: 6987: case ROTATE: 1.1.1.5 root 6988: /* The nonzero bits are in two classes: any bits within MODE 1.1 root 6989: that aren't in GET_MODE (x) are always significant. The rest of the 1.1.1.5 root 6990: nonzero bits are those that are significant in the operand of 1.1 root 6991: the shift when shifted the appropriate number of bits. This 6992: shows that high-order bits are cleared by the right shift and 6993: low-order bits by left shifts. */ 6994: if (GET_CODE (XEXP (x, 1)) == CONST_INT 6995: && INTVAL (XEXP (x, 1)) >= 0 1.1.1.4 root 6996: && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) 1.1 root 6997: { 6998: enum machine_mode inner_mode = GET_MODE (x); 6999: int width = GET_MODE_BITSIZE (inner_mode); 7000: int count = INTVAL (XEXP (x, 1)); 1.1.1.4 root 7001: unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode); 1.1.1.5 root 7002: unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode); 7003: unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask; 1.1.1.4 root 7004: unsigned HOST_WIDE_INT outer = 0; 1.1 root 7005: 7006: if (mode_width > width) 1.1.1.5 root 7007: outer = (op_nonzero & nonzero & ~ mode_mask); 1.1 root 7008: 7009: if (code == LSHIFTRT) 7010: inner >>= count; 7011: else if (code == ASHIFTRT) 7012: { 7013: inner >>= count; 7014: 1.1.1.5 root 7015: /* If the sign bit may have been nonzero before the shift, we 1.1 root 7016: need to mark all the places it could have been copied to 1.1.1.5 root 7017: by the shift as possibly nonzero. */ 1.1.1.4 root 7018: if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count))) 7019: inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count); 1.1 root 7020: } 1.1.1.7 ! root 7021: else if (code == ASHIFT) 1.1 root 7022: inner <<= count; 7023: else 7024: inner = ((inner << (count % width) 7025: | (inner >> (width - (count % width)))) & mode_mask); 7026: 1.1.1.5 root 7027: nonzero &= (outer | inner); 1.1 root 7028: } 7029: break; 7030: 7031: case FFS: 7032: /* This is at most the number of bits in the mode. */ 1.1.1.5 root 7033: nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1; 1.1.1.4 root 7034: break; 7035: 7036: case IF_THEN_ELSE: 1.1.1.5 root 7037: nonzero &= (nonzero_bits (XEXP (x, 1), mode) 7038: | nonzero_bits (XEXP (x, 2), mode)); 1.1 root 7039: break; 7040: } 7041: 1.1.1.5 root 7042: return nonzero; 1.1 root 7043: } 7044: 1.1.1.4 root 7045: /* Return the number of bits at the high-order end of X that are known to 1.1.1.6 root 7046: be equal to the sign bit. X will be used in mode MODE; if MODE is 7047: VOIDmode, X will be used in its own mode. The returned value will always 7048: be between 1 and the number of bits in MODE. */ 1.1.1.4 root 7049: 7050: static int 7051: num_sign_bit_copies (x, mode) 7052: rtx x; 7053: enum machine_mode mode; 7054: { 7055: enum rtx_code code = GET_CODE (x); 7056: int bitwidth; 7057: int num0, num1, result; 1.1.1.5 root 7058: unsigned HOST_WIDE_INT nonzero; 1.1.1.4 root 7059: rtx tem; 7060: 7061: /* If we weren't given a mode, use the mode of X. If the mode is still 1.1.1.7 ! root 7062: VOIDmode, we don't know anything. Likewise if one of the modes is ! 7063: floating-point. */ 1.1.1.4 root 7064: 7065: if (mode == VOIDmode) 7066: mode = GET_MODE (x); 7067: 1.1.1.7 ! root 7068: if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x))) 1.1.1.4 root 7069: return 1; 7070: 7071: bitwidth = GET_MODE_BITSIZE (mode); 7072: 1.1.1.6 root 7073: /* For a smaller object, just ignore the high bits. */ 7074: if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x))) 7075: return MAX (1, (num_sign_bit_copies (x, GET_MODE (x)) 7076: - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth))); 7077: 1.1.1.7 ! root 7078: #ifndef WORD_REGISTER_OPERATIONS ! 7079: /* If this machine does not do all register operations on the entire ! 7080: register and MODE is wider than the mode of X, we can say nothing ! 7081: at all about the high-order bits. */ ! 7082: if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x))) ! 7083: return 1; ! 7084: #endif ! 7085: 1.1.1.4 root 7086: switch (code) 7087: { 7088: case REG: 1.1.1.5 root 7089: 7090: if (reg_last_set_value[REGNO (x)] != 0 7091: && reg_last_set_mode[REGNO (x)] == mode 7092: && (reg_n_sets[REGNO (x)] == 1 7093: || reg_last_set_label[REGNO (x)] == label_tick) 7094: && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid) 7095: return reg_last_set_sign_bit_copies[REGNO (x)]; 1.1.1.4 root 7096: 7097: tem = get_last_value (x); 7098: if (tem != 0) 7099: return num_sign_bit_copies (tem, mode); 1.1.1.5 root 7100: 7101: if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0) 7102: return reg_sign_bit_copies[REGNO (x)]; 1.1.1.4 root 7103: break; 7104: 7105: case MEM: 1.1.1.6 root 7106: #ifdef LOAD_EXTEND_OP 1.1.1.4 root 7107: /* Some RISC machines sign-extend all loads of smaller than a word. */ 1.1.1.6 root 7108: if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND) 7109: return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1); 1.1.1.4 root 7110: #endif 1.1.1.6 root 7111: break; 1.1.1.4 root 7112: 7113: case CONST_INT: 7114: /* If the constant is negative, take its 1's complement and remask. 7115: Then see how many zero bits we have. */ 1.1.1.5 root 7116: nonzero = INTVAL (x) & GET_MODE_MASK (mode); 1.1.1.4 root 7117: if (bitwidth <= HOST_BITS_PER_WIDE_INT 1.1.1.5 root 7118: && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) 7119: nonzero = (~ nonzero) & GET_MODE_MASK (mode); 1.1.1.4 root 7120: 1.1.1.5 root 7121: return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1); 1.1.1.4 root 7122: 7123: case SUBREG: 7124: /* If this is a SUBREG for a promoted object that is sign-extended 7125: and we are looking at it in a wider mode, we know that at least the 7126: high-order bits are known to be sign bit copies. */ 7127: 7128: if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x)) 1.1.1.5 root 7129: return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1, 7130: num_sign_bit_copies (SUBREG_REG (x), mode)); 1.1.1.4 root 7131: 7132: /* For a smaller object, just ignore the high bits. */ 7133: if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))) 7134: { 7135: num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode); 7136: return MAX (1, (num0 7137: - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) 7138: - bitwidth))); 7139: } 7140: 1.1.1.6 root 7141: #ifdef WORD_REGISTER_OPERATIONS 7142: /* For paradoxical SUBREGs on machines where all register operations 7143: affect the entire register, just look inside. Note that we are 7144: passing MODE to the recursive call, so the number of sign bit copies 7145: will remain relative to that mode, not the inner mode. */ 1.1.1.4 root 7146: 7147: if (GET_MODE_SIZE (GET_MODE (x)) 7148: > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 7149: return num_sign_bit_copies (SUBREG_REG (x), mode); 7150: #endif 7151: break; 7152: 7153: case SIGN_EXTRACT: 7154: if (GET_CODE (XEXP (x, 1)) == CONST_INT) 7155: return MAX (1, bitwidth - INTVAL (XEXP (x, 1))); 7156: break; 7157: 7158: case SIGN_EXTEND: 7159: return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 7160: + num_sign_bit_copies (XEXP (x, 0), VOIDmode)); 7161: 7162: case TRUNCATE: 7163: /* For a smaller object, just ignore the high bits. */ 7164: num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode); 7165: return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) 7166: - bitwidth))); 7167: 7168: case NOT: 7169: return num_sign_bit_copies (XEXP (x, 0), mode); 7170: 7171: case ROTATE: case ROTATERT: 7172: /* If we are rotating left by a number of bits less than the number 7173: of sign bit copies, we can just subtract that amount from the 7174: number. */ 7175: if (GET_CODE (XEXP (x, 1)) == CONST_INT 7176: && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth) 7177: { 7178: num0 = num_sign_bit_copies (XEXP (x, 0), mode); 7179: return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1)) 7180: : bitwidth - INTVAL (XEXP (x, 1)))); 7181: } 7182: break; 7183: 7184: case NEG: 7185: /* In general, this subtracts one sign bit copy. But if the value 7186: is known to be positive, the number of sign bit copies is the 1.1.1.5 root 7187: same as that of the input. Finally, if the input has just one bit 7188: that might be nonzero, all the bits are copies of the sign bit. */ 7189: nonzero = nonzero_bits (XEXP (x, 0), mode); 7190: if (nonzero == 1) 1.1.1.4 root 7191: return bitwidth; 7192: 7193: num0 = num_sign_bit_copies (XEXP (x, 0), mode); 7194: if (num0 > 1 7195: && bitwidth <= HOST_BITS_PER_WIDE_INT 1.1.1.5 root 7196: && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero)) 1.1.1.4 root 7197: num0--; 7198: 7199: return num0; 7200: 7201: case IOR: case AND: case XOR: 7202: case SMIN: case SMAX: case UMIN: case UMAX: 7203: /* Logical operations will preserve the number of sign-bit copies. 7204: MIN and MAX operations always return one of the operands. */ 7205: num0 = num_sign_bit_copies (XEXP (x, 0), mode); 7206: num1 = num_sign_bit_copies (XEXP (x, 1), mode); 7207: return MIN (num0, num1); 7208: 7209: case PLUS: case MINUS: 7210: /* For addition and subtraction, we can have a 1-bit carry. However, 7211: if we are subtracting 1 from a positive number, there will not 7212: be such a carry. Furthermore, if the positive number is known to 7213: be 0 or 1, we know the result is either -1 or 0. */ 7214: 7215: if (code == PLUS && XEXP (x, 1) == constm1_rtx 1.1.1.5 root 7216: && bitwidth <= HOST_BITS_PER_WIDE_INT) 7217: { 7218: nonzero = nonzero_bits (XEXP (x, 0), mode); 7219: if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0) 7220: return (nonzero == 1 || nonzero == 0 ? bitwidth 7221: : bitwidth - floor_log2 (nonzero) - 1); 1.1.1.4 root 7222: } 7223: 7224: num0 = num_sign_bit_copies (XEXP (x, 0), mode); 7225: num1 = num_sign_bit_copies (XEXP (x, 1), mode); 7226: return MAX (1, MIN (num0, num1) - 1); 7227: 7228: case MULT: 7229: /* The number of bits of the product is the sum of the number of 7230: bits of both terms. However, unless one of the terms if known 7231: to be positive, we must allow for an additional bit since negating 7232: a negative number can remove one sign bit copy. */ 7233: 7234: num0 = num_sign_bit_copies (XEXP (x, 0), mode); 7235: num1 = num_sign_bit_copies (XEXP (x, 1), mode); 7236: 7237: result = bitwidth - (bitwidth - num0) - (bitwidth - num1); 7238: if (result > 0 1.1.1.5 root 7239: && bitwidth <= HOST_BITS_PER_WIDE_INT 7240: && ((nonzero_bits (XEXP (x, 0), mode) 1.1.1.4 root 7241: & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) 1.1.1.5 root 7242: && (nonzero_bits (XEXP (x, 1), mode) 1.1.1.4 root 7243: & ((HOST_WIDE_INT) 1 << (bitwidth - 1)) != 0)) 7244: result--; 7245: 7246: return MAX (1, result); 7247: 7248: case UDIV: 7249: /* The result must be <= the first operand. */ 7250: return num_sign_bit_copies (XEXP (x, 0), mode); 7251: 7252: case UMOD: 7253: /* The result must be <= the scond operand. */ 7254: return num_sign_bit_copies (XEXP (x, 1), mode); 7255: 7256: case DIV: 7257: /* Similar to unsigned division, except that we have to worry about 7258: the case where the divisor is negative, in which case we have 7259: to add 1. */ 7260: result = num_sign_bit_copies (XEXP (x, 0), mode); 7261: if (result > 1 7262: && bitwidth <= HOST_BITS_PER_WIDE_INT 1.1.1.5 root 7263: && (nonzero_bits (XEXP (x, 1), mode) 1.1.1.4 root 7264: & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) 7265: result --; 7266: 7267: return result; 7268: 7269: case MOD: 7270: result = num_sign_bit_copies (XEXP (x, 1), mode); 7271: if (result > 1 7272: && bitwidth <= HOST_BITS_PER_WIDE_INT 1.1.1.5 root 7273: && (nonzero_bits (XEXP (x, 1), mode) 1.1.1.4 root 7274: & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) 7275: result --; 7276: 7277: return result; 7278: 7279: case ASHIFTRT: 7280: /* Shifts by a constant add to the number of bits equal to the 7281: sign bit. */ 7282: num0 = num_sign_bit_copies (XEXP (x, 0), mode); 7283: if (GET_CODE (XEXP (x, 1)) == CONST_INT 7284: && INTVAL (XEXP (x, 1)) > 0) 7285: num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1))); 7286: 7287: return num0; 7288: 7289: case ASHIFT: 7290: /* Left shifts destroy copies. */ 7291: if (GET_CODE (XEXP (x, 1)) != CONST_INT 7292: || INTVAL (XEXP (x, 1)) < 0 7293: || INTVAL (XEXP (x, 1)) >= bitwidth) 7294: return 1; 7295: 7296: num0 = num_sign_bit_copies (XEXP (x, 0), mode); 7297: return MAX (1, num0 - INTVAL (XEXP (x, 1))); 7298: 7299: case IF_THEN_ELSE: 7300: num0 = num_sign_bit_copies (XEXP (x, 1), mode); 7301: num1 = num_sign_bit_copies (XEXP (x, 2), mode); 7302: return MIN (num0, num1); 7303: 7304: #if STORE_FLAG_VALUE == -1 7305: case EQ: case NE: case GE: case GT: case LE: case LT: 7306: case GEU: case GTU: case LEU: case LTU: 7307: return bitwidth; 7308: #endif 7309: } 7310: 7311: /* If we haven't been able to figure it out by one of the above rules, 7312: see if some of the high-order bits are known to be zero. If so, 7313: count those bits and return one less than that amount. If we can't 7314: safely compute the mask for this mode, always return BITWIDTH. */ 7315: 7316: if (bitwidth > HOST_BITS_PER_WIDE_INT) 7317: return 1; 7318: 1.1.1.5 root 7319: nonzero = nonzero_bits (x, mode); 7320: return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1)) 7321: ? 1 : bitwidth - floor_log2 (nonzero) - 1); 1.1.1.4 root 7322: } 7323: 7324: /* Return the number of "extended" bits there are in X, when interpreted 7325: as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For 7326: unsigned quantities, this is the number of high-order zero bits. 7327: For signed quantities, this is the number of copies of the sign bit 7328: minus 1. In both case, this function returns the number of "spare" 7329: bits. For example, if two quantities for which this function returns 7330: at least 1 are added, the addition is known not to overflow. 7331: 7332: This function will always return 0 unless called during combine, which 7333: implies that it must be called from a define_split. */ 7334: 7335: int 7336: extended_count (x, mode, unsignedp) 7337: rtx x; 7338: enum machine_mode mode; 7339: int unsignedp; 7340: { 1.1.1.5 root 7341: if (nonzero_sign_valid == 0) 1.1.1.4 root 7342: return 0; 7343: 7344: return (unsignedp 7345: ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT 7346: && (GET_MODE_BITSIZE (mode) - 1 1.1.1.5 root 7347: - floor_log2 (nonzero_bits (x, mode)))) 1.1.1.4 root 7348: : num_sign_bit_copies (x, mode) - 1); 7349: } 7350: 1.1 root 7351: /* This function is called from `simplify_shift_const' to merge two 7352: outer operations. Specifically, we have already found that we need 7353: to perform operation *POP0 with constant *PCONST0 at the outermost 7354: position. We would now like to also perform OP1 with constant CONST1 7355: (with *POP0 being done last). 7356: 7357: Return 1 if we can do the operation and update *POP0 and *PCONST0 with 7358: the resulting operation. *PCOMP_P is set to 1 if we would need to 7359: complement the innermost operand, otherwise it is unchanged. 7360: 7361: MODE is the mode in which the operation will be done. No bits outside 7362: the width of this mode matter. It is assumed that the width of this mode 1.1.1.4 root 7363: is smaller than or equal to HOST_BITS_PER_WIDE_INT. 1.1 root 7364: 7365: If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS, 7366: IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper 7367: result is simply *PCONST0. 7368: 7369: If the resulting operation cannot be expressed as one operation, we 7370: return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */ 7371: 7372: static int 7373: merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p) 7374: enum rtx_code *pop0; 1.1.1.4 root 7375: HOST_WIDE_INT *pconst0; 1.1 root 7376: enum rtx_code op1; 1.1.1.4 root 7377: HOST_WIDE_INT const1; 1.1 root 7378: enum machine_mode mode; 7379: int *pcomp_p; 7380: { 7381: enum rtx_code op0 = *pop0; 1.1.1.4 root 7382: HOST_WIDE_INT const0 = *pconst0; 1.1 root 7383: 7384: const0 &= GET_MODE_MASK (mode); 7385: const1 &= GET_MODE_MASK (mode); 7386: 7387: /* If OP0 is an AND, clear unimportant bits in CONST1. */ 7388: if (op0 == AND) 7389: const1 &= const0; 7390: 7391: /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or 7392: if OP0 is SET. */ 7393: 7394: if (op1 == NIL || op0 == SET) 7395: return 1; 7396: 7397: else if (op0 == NIL) 7398: op0 = op1, const0 = const1; 7399: 7400: else if (op0 == op1) 7401: { 7402: switch (op0) 7403: { 7404: case AND: 7405: const0 &= const1; 7406: break; 7407: case IOR: 7408: const0 |= const1; 7409: break; 7410: case XOR: 7411: const0 ^= const1; 7412: break; 7413: case PLUS: 7414: const0 += const1; 7415: break; 7416: case NEG: 7417: op0 = NIL; 7418: break; 7419: } 7420: } 7421: 7422: /* Otherwise, if either is a PLUS or NEG, we can't do anything. */ 7423: else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG) 7424: return 0; 7425: 7426: /* If the two constants aren't the same, we can't do anything. The 7427: remaining six cases can all be done. */ 7428: else if (const0 != const1) 7429: return 0; 7430: 7431: else 7432: switch (op0) 7433: { 7434: case IOR: 7435: if (op1 == AND) 7436: /* (a & b) | b == b */ 7437: op0 = SET; 7438: else /* op1 == XOR */ 7439: /* (a ^ b) | b == a | b */ 7440: ; 7441: break; 7442: 7443: case XOR: 7444: if (op1 == AND) 7445: /* (a & b) ^ b == (~a) & b */ 7446: op0 = AND, *pcomp_p = 1; 7447: else /* op1 == IOR */ 7448: /* (a | b) ^ b == a & ~b */ 7449: op0 = AND, *pconst0 = ~ const0; 7450: break; 7451: 7452: case AND: 7453: if (op1 == IOR) 7454: /* (a | b) & b == b */ 7455: op0 = SET; 7456: else /* op1 == XOR */ 7457: /* (a ^ b) & b) == (~a) & b */ 7458: *pcomp_p = 1; 7459: break; 7460: } 7461: 7462: /* Check for NO-OP cases. */ 7463: const0 &= GET_MODE_MASK (mode); 7464: if (const0 == 0 7465: && (op0 == IOR || op0 == XOR || op0 == PLUS)) 7466: op0 = NIL; 7467: else if (const0 == 0 && op0 == AND) 7468: op0 = SET; 7469: else if (const0 == GET_MODE_MASK (mode) && op0 == AND) 7470: op0 = NIL; 7471: 7472: *pop0 = op0; 7473: *pconst0 = const0; 7474: 7475: return 1; 7476: } 7477: 7478: /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift. 7479: The result of the shift is RESULT_MODE. X, if non-zero, is an expression 7480: that we started with. 7481: 7482: The shift is normally computed in the widest mode we find in VAROP, as 7483: long as it isn't a different number of words than RESULT_MODE. Exceptions 7484: are ASHIFTRT and ROTATE, which are always done in their original mode, */ 7485: 7486: static rtx 7487: simplify_shift_const (x, code, result_mode, varop, count) 7488: rtx x; 7489: enum rtx_code code; 7490: enum machine_mode result_mode; 7491: rtx varop; 7492: int count; 7493: { 7494: enum rtx_code orig_code = code; 7495: int orig_count = count; 7496: enum machine_mode mode = result_mode; 7497: enum machine_mode shift_mode, tmode; 7498: int mode_words 7499: = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD; 7500: /* We form (outer_op (code varop count) (outer_const)). */ 7501: enum rtx_code outer_op = NIL; 1.1.1.6 root 7502: HOST_WIDE_INT outer_const = 0; 1.1 root 7503: rtx const_rtx; 7504: int complement_p = 0; 7505: rtx new; 7506: 7507: /* If we were given an invalid count, don't do anything except exactly 7508: what was requested. */ 7509: 7510: if (count < 0 || count > GET_MODE_BITSIZE (mode)) 7511: { 7512: if (x) 7513: return x; 7514: 1.1.1.4 root 7515: return gen_rtx (code, mode, varop, GEN_INT (count)); 1.1 root 7516: } 7517: 7518: /* Unless one of the branches of the `if' in this loop does a `continue', 7519: we will `break' the loop after the `if'. */ 7520: 7521: while (count != 0) 7522: { 7523: /* If we have an operand of (clobber (const_int 0)), just return that 7524: value. */ 7525: if (GET_CODE (varop) == CLOBBER) 7526: return varop; 7527: 7528: /* If we discovered we had to complement VAROP, leave. Making a NOT 7529: here would cause an infinite loop. */ 7530: if (complement_p) 7531: break; 7532: 7533: /* Convert ROTATETRT to ROTATE. */ 7534: if (code == ROTATERT) 7535: code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count; 7536: 7537: /* We need to determine what mode we will do the shift in. If the 7538: shift is a ASHIFTRT or ROTATE, we must always do it in the mode it 7539: was originally done in. Otherwise, we can do it in MODE, the widest 7540: mode encountered. */ 7541: shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode); 7542: 7543: /* Handle cases where the count is greater than the size of the mode 7544: minus 1. For ASHIFT, use the size minus one as the count (this can 7545: occur when simplifying (lshiftrt (ashiftrt ..))). For rotates, 7546: take the count modulo the size. For other shifts, the result is 7547: zero. 7548: 7549: Since these shifts are being produced by the compiler by combining 7550: multiple operations, each of which are defined, we know what the 7551: result is supposed to be. */ 7552: 7553: if (count > GET_MODE_BITSIZE (shift_mode) - 1) 7554: { 7555: if (code == ASHIFTRT) 7556: count = GET_MODE_BITSIZE (shift_mode) - 1; 7557: else if (code == ROTATE || code == ROTATERT) 7558: count %= GET_MODE_BITSIZE (shift_mode); 7559: else 7560: { 7561: /* We can't simply return zero because there may be an 7562: outer op. */ 7563: varop = const0_rtx; 7564: count = 0; 7565: break; 7566: } 7567: } 7568: 7569: /* Negative counts are invalid and should not have been made (a 7570: programmer-specified negative count should have been handled 7571: above). */ 7572: else if (count < 0) 7573: abort (); 7574: 1.1.1.4 root 7575: /* An arithmetic right shift of a quantity known to be -1 or 0 7576: is a no-op. */ 7577: if (code == ASHIFTRT 7578: && (num_sign_bit_copies (varop, shift_mode) 7579: == GET_MODE_BITSIZE (shift_mode))) 7580: { 7581: count = 0; 7582: break; 7583: } 7584: 1.1.1.5 root 7585: /* If we are doing an arithmetic right shift and discarding all but 7586: the sign bit copies, this is equivalent to doing a shift by the 7587: bitsize minus one. Convert it into that shift because it will often 7588: allow other simplifications. */ 7589: 7590: if (code == ASHIFTRT 7591: && (count + num_sign_bit_copies (varop, shift_mode) 7592: >= GET_MODE_BITSIZE (shift_mode))) 7593: count = GET_MODE_BITSIZE (shift_mode) - 1; 7594: 1.1 root 7595: /* We simplify the tests below and elsewhere by converting 7596: ASHIFTRT to LSHIFTRT if we know the sign bit is clear. 7597: `make_compound_operation' will convert it to a ASHIFTRT for 7598: those machines (such as Vax) that don't have a LSHIFTRT. */ 1.1.1.4 root 7599: if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT 1.1 root 7600: && code == ASHIFTRT 1.1.1.5 root 7601: && ((nonzero_bits (varop, shift_mode) 1.1.1.4 root 7602: & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1))) 7603: == 0)) 1.1 root 7604: code = LSHIFTRT; 7605: 7606: switch (GET_CODE (varop)) 7607: { 7608: case SIGN_EXTEND: 7609: case ZERO_EXTEND: 7610: case SIGN_EXTRACT: 7611: case ZERO_EXTRACT: 7612: new = expand_compound_operation (varop); 7613: if (new != varop) 7614: { 7615: varop = new; 7616: continue; 7617: } 7618: break; 7619: 7620: case MEM: 7621: /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH 7622: minus the width of a smaller mode, we can do this with a 7623: SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */ 7624: if ((code == ASHIFTRT || code == LSHIFTRT) 7625: && ! mode_dependent_address_p (XEXP (varop, 0)) 7626: && ! MEM_VOLATILE_P (varop) 7627: && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, 7628: MODE_INT, 1)) != BLKmode) 7629: { 7630: #if BYTES_BIG_ENDIAN 7631: new = gen_rtx (MEM, tmode, XEXP (varop, 0)); 7632: #else 7633: new = gen_rtx (MEM, tmode, 7634: plus_constant (XEXP (varop, 0), 7635: count / BITS_PER_UNIT)); 7636: RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop); 7637: MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop); 7638: MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop); 7639: #endif 7640: varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND 7641: : ZERO_EXTEND, mode, new); 7642: count = 0; 7643: continue; 7644: } 7645: break; 7646: 7647: case USE: 7648: /* Similar to the case above, except that we can only do this if 7649: the resulting mode is the same as that of the underlying 7650: MEM and adjust the address depending on the *bits* endianness 7651: because of the way that bit-field extract insns are defined. */ 7652: if ((code == ASHIFTRT || code == LSHIFTRT) 7653: && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, 7654: MODE_INT, 1)) != BLKmode 7655: && tmode == GET_MODE (XEXP (varop, 0))) 7656: { 7657: #if BITS_BIG_ENDIAN 7658: new = XEXP (varop, 0); 7659: #else 7660: new = copy_rtx (XEXP (varop, 0)); 7661: SUBST (XEXP (new, 0), 7662: plus_constant (XEXP (new, 0), 7663: count / BITS_PER_UNIT)); 7664: #endif 7665: 7666: varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND 7667: : ZERO_EXTEND, mode, new); 7668: count = 0; 7669: continue; 7670: } 7671: break; 7672: 7673: case SUBREG: 7674: /* If VAROP is a SUBREG, strip it as long as the inner operand has 7675: the same number of words as what we've seen so far. Then store 7676: the widest mode in MODE. */ 1.1.1.4 root 7677: if (subreg_lowpart_p (varop) 7678: && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) 7679: > GET_MODE_SIZE (GET_MODE (varop))) 1.1 root 7680: && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) 7681: + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) 7682: == mode_words)) 7683: { 7684: varop = SUBREG_REG (varop); 7685: if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode)) 7686: mode = GET_MODE (varop); 7687: continue; 7688: } 7689: break; 7690: 7691: case MULT: 7692: /* Some machines use MULT instead of ASHIFT because MULT 7693: is cheaper. But it is still better on those machines to 7694: merge two shifts into one. */ 7695: if (GET_CODE (XEXP (varop, 1)) == CONST_INT 7696: && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0) 7697: { 7698: varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0), 1.1.1.4 root 7699: GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));; 1.1 root 7700: continue; 7701: } 7702: break; 7703: 7704: case UDIV: 7705: /* Similar, for when divides are cheaper. */ 7706: if (GET_CODE (XEXP (varop, 1)) == CONST_INT 7707: && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0) 7708: { 7709: varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0), 1.1.1.4 root 7710: GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1))))); 1.1 root 7711: continue; 7712: } 7713: break; 7714: 7715: case ASHIFTRT: 7716: /* If we are extracting just the sign bit of an arithmetic right 7717: shift, that shift is not needed. */ 7718: if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1) 7719: { 7720: varop = XEXP (varop, 0); 7721: continue; 7722: } 7723: 7724: /* ... fall through ... */ 7725: 7726: case LSHIFTRT: 7727: case ASHIFT: 7728: case ROTATE: 7729: /* Here we have two nested shifts. The result is usually the 7730: AND of a new shift with a mask. We compute the result below. */ 7731: if (GET_CODE (XEXP (varop, 1)) == CONST_INT 7732: && INTVAL (XEXP (varop, 1)) >= 0 7733: && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop)) 1.1.1.4 root 7734: && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT 7735: && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 1.1 root 7736: { 7737: enum rtx_code first_code = GET_CODE (varop); 7738: int first_count = INTVAL (XEXP (varop, 1)); 1.1.1.4 root 7739: unsigned HOST_WIDE_INT mask; 1.1 root 7740: rtx mask_rtx; 7741: 7742: /* We have one common special case. We can't do any merging if 7743: the inner code is an ASHIFTRT of a smaller mode. However, if 7744: we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2) 7745: with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2), 7746: we can convert it to 7747: (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1). 7748: This simplifies certain SIGN_EXTEND operations. */ 7749: if (code == ASHIFT && first_code == ASHIFTRT 7750: && (GET_MODE_BITSIZE (result_mode) 7751: - GET_MODE_BITSIZE (GET_MODE (varop))) == count) 7752: { 7753: /* C3 has the low-order C1 bits zero. */ 7754: 1.1.1.4 root 7755: mask = (GET_MODE_MASK (mode) 7756: & ~ (((HOST_WIDE_INT) 1 << first_count) - 1)); 1.1 root 7757: 1.1.1.4 root 7758: varop = simplify_and_const_int (NULL_RTX, result_mode, 1.1 root 7759: XEXP (varop, 0), mask); 1.1.1.4 root 7760: varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode, 1.1 root 7761: varop, count); 7762: count = first_count; 7763: code = ASHIFTRT; 7764: continue; 7765: } 7766: 1.1.1.4 root 7767: /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more 7768: than C1 high-order bits equal to the sign bit, we can convert 7769: this to either an ASHIFT or a ASHIFTRT depending on the 7770: two counts. 1.1 root 7771: 7772: We cannot do this if VAROP's mode is not SHIFT_MODE. */ 7773: 7774: if (code == ASHIFTRT && first_code == ASHIFT 7775: && GET_MODE (varop) == shift_mode 1.1.1.4 root 7776: && (num_sign_bit_copies (XEXP (varop, 0), shift_mode) 7777: > first_count)) 1.1 root 7778: { 1.1.1.4 root 7779: count -= first_count; 7780: if (count < 0) 7781: count = - count, code = ASHIFT; 7782: varop = XEXP (varop, 0); 7783: continue; 1.1 root 7784: } 7785: 7786: /* There are some cases we can't do. If CODE is ASHIFTRT, 7787: we can only do this if FIRST_CODE is also ASHIFTRT. 7788: 7789: We can't do the case when CODE is ROTATE and FIRST_CODE is 7790: ASHIFTRT. 7791: 7792: If the mode of this shift is not the mode of the outer shift, 7793: we can't do this if either shift is ASHIFTRT or ROTATE. 7794: 7795: Finally, we can't do any of these if the mode is too wide 7796: unless the codes are the same. 7797: 7798: Handle the case where the shift codes are the same 7799: first. */ 7800: 7801: if (code == first_code) 7802: { 7803: if (GET_MODE (varop) != result_mode 7804: && (code == ASHIFTRT || code == ROTATE)) 7805: break; 7806: 7807: count += first_count; 7808: varop = XEXP (varop, 0); 7809: continue; 7810: } 7811: 7812: if (code == ASHIFTRT 7813: || (code == ROTATE && first_code == ASHIFTRT) 1.1.1.4 root 7814: || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT 1.1 root 7815: || (GET_MODE (varop) != result_mode 7816: && (first_code == ASHIFTRT || first_code == ROTATE 7817: || code == ROTATE))) 7818: break; 7819: 7820: /* To compute the mask to apply after the shift, shift the 1.1.1.5 root 7821: nonzero bits of the inner shift the same way the 1.1 root 7822: outer shift will. */ 7823: 1.1.1.5 root 7824: mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop))); 1.1 root 7825: 7826: mask_rtx 7827: = simplify_binary_operation (code, result_mode, mask_rtx, 1.1.1.4 root 7828: GEN_INT (count)); 1.1 root 7829: 7830: /* Give up if we can't compute an outer operation to use. */ 7831: if (mask_rtx == 0 7832: || GET_CODE (mask_rtx) != CONST_INT 7833: || ! merge_outer_ops (&outer_op, &outer_const, AND, 7834: INTVAL (mask_rtx), 7835: result_mode, &complement_p)) 7836: break; 7837: 7838: /* If the shifts are in the same direction, we add the 7839: counts. Otherwise, we subtract them. */ 7840: if ((code == ASHIFTRT || code == LSHIFTRT) 7841: == (first_code == ASHIFTRT || first_code == LSHIFTRT)) 7842: count += first_count; 7843: else 7844: count -= first_count; 7845: 7846: /* If COUNT is positive, the new shift is usually CODE, 7847: except for the two exceptions below, in which case it is 7848: FIRST_CODE. If the count is negative, FIRST_CODE should 7849: always be used */ 7850: if (count > 0 7851: && ((first_code == ROTATE && code == ASHIFT) 7852: || (first_code == ASHIFTRT && code == LSHIFTRT))) 7853: code = first_code; 7854: else if (count < 0) 7855: code = first_code, count = - count; 7856: 7857: varop = XEXP (varop, 0); 7858: continue; 7859: } 7860: 7861: /* If we have (A << B << C) for any shift, we can convert this to 7862: (A << C << B). This wins if A is a constant. Only try this if 7863: B is not a constant. */ 7864: 7865: else if (GET_CODE (varop) == code 7866: && GET_CODE (XEXP (varop, 1)) != CONST_INT 7867: && 0 != (new 7868: = simplify_binary_operation (code, mode, 7869: XEXP (varop, 0), 1.1.1.4 root 7870: GEN_INT (count)))) 1.1 root 7871: { 7872: varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1)); 7873: count = 0; 7874: continue; 7875: } 7876: break; 7877: 7878: case NOT: 7879: /* Make this fit the case below. */ 7880: varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0), 1.1.1.4 root 7881: GEN_INT (GET_MODE_MASK (mode))); 1.1 root 7882: continue; 7883: 7884: case IOR: 7885: case AND: 7886: case XOR: 7887: /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C) 7888: with C the size of VAROP - 1 and the shift is logical if 7889: STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, 7890: we have an (le X 0) operation. If we have an arithmetic shift 7891: and STORE_FLAG_VALUE is 1 or we have a logical shift with 7892: STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */ 7893: 7894: if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS 7895: && XEXP (XEXP (varop, 0), 1) == constm1_rtx 7896: && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 7897: && (code == LSHIFTRT || code == ASHIFTRT) 7898: && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1 7899: && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) 7900: { 7901: count = 0; 7902: varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1), 7903: const0_rtx); 7904: 7905: if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) 7906: varop = gen_rtx_combine (NEG, GET_MODE (varop), varop); 7907: 7908: continue; 7909: } 7910: 7911: /* If we have (shift (logical)), move the logical to the outside 7912: to allow it to possibly combine with another logical and the 7913: shift to combine with another shift. This also canonicalizes to 7914: what a ZERO_EXTRACT looks like. Also, some machines have 7915: (and (shift)) insns. */ 7916: 7917: if (GET_CODE (XEXP (varop, 1)) == CONST_INT 7918: && (new = simplify_binary_operation (code, result_mode, 7919: XEXP (varop, 1), 1.1.1.4 root 7920: GEN_INT (count))) != 0 1.1.1.7 ! root 7921: && GET_CODE(new) == CONST_INT 1.1 root 7922: && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop), 7923: INTVAL (new), result_mode, &complement_p)) 7924: { 7925: varop = XEXP (varop, 0); 7926: continue; 7927: } 7928: 7929: /* If we can't do that, try to simplify the shift in each arm of the 7930: logical expression, make a new logical expression, and apply 7931: the inverse distributive law. */ 7932: { 1.1.1.6 root 7933: rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode, 1.1 root 7934: XEXP (varop, 0), count); 1.1.1.6 root 7935: rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode, 1.1 root 7936: XEXP (varop, 1), count); 7937: 1.1.1.7 ! root 7938: varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs); 1.1 root 7939: varop = apply_distributive_law (varop); 7940: 7941: count = 0; 7942: } 7943: break; 7944: 7945: case EQ: 1.1.1.7 ! root 7946: /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE 1.1 root 7947: says that the sign bit can be tested, FOO has mode MODE, C is 1.1.1.7 ! root 7948: GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit ! 7949: that may be nonzero. */ ! 7950: if (code == LSHIFTRT 1.1 root 7951: && XEXP (varop, 1) == const0_rtx 7952: && GET_MODE (XEXP (varop, 0)) == result_mode 7953: && count == GET_MODE_BITSIZE (result_mode) - 1 1.1.1.4 root 7954: && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT 1.1 root 7955: && ((STORE_FLAG_VALUE 1.1.1.4 root 7956: & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1)))) 1.1.1.5 root 7957: && nonzero_bits (XEXP (varop, 0), result_mode) == 1 1.1.1.4 root 7958: && merge_outer_ops (&outer_op, &outer_const, XOR, 7959: (HOST_WIDE_INT) 1, result_mode, 7960: &complement_p)) 1.1 root 7961: { 7962: varop = XEXP (varop, 0); 7963: count = 0; 7964: continue; 7965: } 7966: break; 7967: 7968: case NEG: 1.1.1.4 root 7969: /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less 7970: than the number of bits in the mode is equivalent to A. */ 7971: if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1 1.1.1.5 root 7972: && nonzero_bits (XEXP (varop, 0), result_mode) == 1) 1.1 root 7973: { 1.1.1.4 root 7974: varop = XEXP (varop, 0); 1.1 root 7975: count = 0; 7976: continue; 7977: } 7978: 7979: /* NEG commutes with ASHIFT since it is multiplication. Move the 7980: NEG outside to allow shifts to combine. */ 7981: if (code == ASHIFT 1.1.1.4 root 7982: && merge_outer_ops (&outer_op, &outer_const, NEG, 7983: (HOST_WIDE_INT) 0, result_mode, 7984: &complement_p)) 1.1 root 7985: { 7986: varop = XEXP (varop, 0); 7987: continue; 7988: } 7989: break; 7990: 7991: case PLUS: 1.1.1.4 root 7992: /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C 7993: is one less than the number of bits in the mode is 7994: equivalent to (xor A 1). */ 1.1 root 7995: if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1 7996: && XEXP (varop, 1) == constm1_rtx 1.1.1.5 root 7997: && nonzero_bits (XEXP (varop, 0), result_mode) == 1 1.1.1.4 root 7998: && merge_outer_ops (&outer_op, &outer_const, XOR, 7999: (HOST_WIDE_INT) 1, result_mode, 8000: &complement_p)) 1.1 root 8001: { 8002: count = 0; 8003: varop = XEXP (varop, 0); 8004: continue; 8005: } 8006: 1.1.1.3 root 8007: /* If we have (xshiftrt (plus FOO BAR) C), and the only bits 1.1.1.5 root 8008: that might be nonzero in BAR are those being shifted out and those 1.1.1.3 root 8009: bits are known zero in FOO, we can replace the PLUS with FOO. 8010: Similarly in the other operand order. This code occurs when 8011: we are computing the size of a variable-size array. */ 8012: 8013: if ((code == ASHIFTRT || code == LSHIFTRT) 1.1.1.4 root 8014: && count < HOST_BITS_PER_WIDE_INT 1.1.1.5 root 8015: && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0 8016: && (nonzero_bits (XEXP (varop, 1), result_mode) 8017: & nonzero_bits (XEXP (varop, 0), result_mode)) == 0) 1.1.1.3 root 8018: { 8019: varop = XEXP (varop, 0); 8020: continue; 8021: } 8022: else if ((code == ASHIFTRT || code == LSHIFTRT) 1.1.1.4 root 8023: && count < HOST_BITS_PER_WIDE_INT 8024: && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT 1.1.1.5 root 8025: && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) 1.1.1.3 root 8026: >> count) 1.1.1.5 root 8027: && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) 8028: & nonzero_bits (XEXP (varop, 1), 1.1.1.3 root 8029: result_mode))) 8030: { 8031: varop = XEXP (varop, 1); 8032: continue; 8033: } 8034: 1.1 root 8035: /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */ 8036: if (code == ASHIFT 8037: && GET_CODE (XEXP (varop, 1)) == CONST_INT 8038: && (new = simplify_binary_operation (ASHIFT, result_mode, 8039: XEXP (varop, 1), 1.1.1.4 root 8040: GEN_INT (count))) != 0 1.1.1.7 ! root 8041: && GET_CODE(new) == CONST_INT 1.1 root 8042: && merge_outer_ops (&outer_op, &outer_const, PLUS, 8043: INTVAL (new), result_mode, &complement_p)) 8044: { 8045: varop = XEXP (varop, 0); 8046: continue; 8047: } 8048: break; 8049: 8050: case MINUS: 8051: /* If we have (xshiftrt (minus (ashiftrt X C)) X) C) 8052: with C the size of VAROP - 1 and the shift is logical if 8053: STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, 8054: we have a (gt X 0) operation. If the shift is arithmetic with 8055: STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1, 8056: we have a (neg (gt X 0)) operation. */ 8057: 8058: if (GET_CODE (XEXP (varop, 0)) == ASHIFTRT 8059: && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1 8060: && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) 8061: && (code == LSHIFTRT || code == ASHIFTRT) 8062: && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT 8063: && INTVAL (XEXP (XEXP (varop, 0), 1)) == count 8064: && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) 8065: { 8066: count = 0; 8067: varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1), 8068: const0_rtx); 8069: 8070: if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) 8071: varop = gen_rtx_combine (NEG, GET_MODE (varop), varop); 8072: 8073: continue; 8074: } 8075: break; 8076: } 8077: 8078: break; 8079: } 8080: 8081: /* We need to determine what mode to do the shift in. If the shift is 8082: a ASHIFTRT or ROTATE, we must always do it in the mode it was originally 8083: done in. Otherwise, we can do it in MODE, the widest mode encountered. 8084: The code we care about is that of the shift that will actually be done, 8085: not the shift that was originally requested. */ 8086: shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode); 8087: 8088: /* We have now finished analyzing the shift. The result should be 8089: a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If 8090: OUTER_OP is non-NIL, it is an operation that needs to be applied 8091: to the result of the shift. OUTER_CONST is the relevant constant, 8092: but we must turn off all bits turned off in the shift. 8093: 8094: If we were passed a value for X, see if we can use any pieces of 8095: it. If not, make new rtx. */ 8096: 8097: if (x && GET_RTX_CLASS (GET_CODE (x)) == '2' 8098: && GET_CODE (XEXP (x, 1)) == CONST_INT 8099: && INTVAL (XEXP (x, 1)) == count) 8100: const_rtx = XEXP (x, 1); 8101: else 1.1.1.4 root 8102: const_rtx = GEN_INT (count); 1.1 root 8103: 8104: if (x && GET_CODE (XEXP (x, 0)) == SUBREG 8105: && GET_MODE (XEXP (x, 0)) == shift_mode 8106: && SUBREG_REG (XEXP (x, 0)) == varop) 8107: varop = XEXP (x, 0); 8108: else if (GET_MODE (varop) != shift_mode) 8109: varop = gen_lowpart_for_combine (shift_mode, varop); 8110: 8111: /* If we can't make the SUBREG, try to return what we were given. */ 8112: if (GET_CODE (varop) == CLOBBER) 8113: return x ? x : varop; 8114: 8115: new = simplify_binary_operation (code, shift_mode, varop, const_rtx); 8116: if (new != 0) 8117: x = new; 8118: else 8119: { 8120: if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode) 8121: x = gen_rtx_combine (code, shift_mode, varop, const_rtx); 8122: 8123: SUBST (XEXP (x, 0), varop); 8124: SUBST (XEXP (x, 1), const_rtx); 8125: } 8126: 1.1.1.6 root 8127: /* If we have an outer operation and we just made a shift, it is 8128: possible that we could have simplified the shift were it not 8129: for the outer operation. So try to do the simplification 8130: recursively. */ 8131: 8132: if (outer_op != NIL && GET_CODE (x) == code 8133: && GET_CODE (XEXP (x, 1)) == CONST_INT) 8134: x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0), 8135: INTVAL (XEXP (x, 1))); 8136: 1.1 root 8137: /* If we were doing a LSHIFTRT in a wider mode than it was originally, 8138: turn off all the bits that the shift would have turned off. */ 8139: if (orig_code == LSHIFTRT && result_mode != shift_mode) 1.1.1.4 root 8140: x = simplify_and_const_int (NULL_RTX, shift_mode, x, 1.1 root 8141: GET_MODE_MASK (result_mode) >> orig_count); 8142: 8143: /* Do the remainder of the processing in RESULT_MODE. */ 8144: x = gen_lowpart_for_combine (result_mode, x); 8145: 8146: /* If COMPLEMENT_P is set, we have to complement X before doing the outer 8147: operation. */ 8148: if (complement_p) 1.1.1.7 ! root 8149: x = gen_unary (NOT, result_mode, result_mode, x); 1.1 root 8150: 8151: if (outer_op != NIL) 8152: { 1.1.1.4 root 8153: if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT) 1.1 root 8154: outer_const &= GET_MODE_MASK (result_mode); 8155: 8156: if (outer_op == AND) 1.1.1.4 root 8157: x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const); 1.1 root 8158: else if (outer_op == SET) 8159: /* This means that we have determined that the result is 8160: equivalent to a constant. This should be rare. */ 1.1.1.4 root 8161: x = GEN_INT (outer_const); 1.1 root 8162: else if (GET_RTX_CLASS (outer_op) == '1') 1.1.1.7 ! root 8163: x = gen_unary (outer_op, result_mode, result_mode, x); 1.1 root 8164: else 1.1.1.4 root 8165: x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const)); 1.1 root 8166: } 8167: 8168: return x; 8169: } 8170: 8171: /* Like recog, but we receive the address of a pointer to a new pattern. 8172: We try to match the rtx that the pointer points to. 8173: If that fails, we may try to modify or replace the pattern, 8174: storing the replacement into the same pointer object. 8175: 8176: Modifications include deletion or addition of CLOBBERs. 8177: 8178: PNOTES is a pointer to a location where any REG_UNUSED notes added for 8179: the CLOBBERs are placed. 8180: 8181: The value is the final insn code from the pattern ultimately matched, 8182: or -1. */ 8183: 8184: static int 8185: recog_for_combine (pnewpat, insn, pnotes) 8186: rtx *pnewpat; 8187: rtx insn; 8188: rtx *pnotes; 8189: { 8190: register rtx pat = *pnewpat; 8191: int insn_code_number; 8192: int num_clobbers_to_add = 0; 8193: int i; 8194: rtx notes = 0; 8195: 1.1.1.6 root 8196: /* If PAT is a PARALLEL, check to see if it contains the CLOBBER 8197: we use to indicate that something didn't match. If we find such a 8198: thing, force rejection. */ 8199: if (GET_CODE (pat) == PARALLEL) 8200: for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) 8201: if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER 8202: && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx) 8203: return -1; 8204: 1.1 root 8205: /* Is the result of combination a valid instruction? */ 8206: insn_code_number = recog (pat, insn, &num_clobbers_to_add); 8207: 8208: /* If it isn't, there is the possibility that we previously had an insn 8209: that clobbered some register as a side effect, but the combined 8210: insn doesn't need to do that. So try once more without the clobbers 8211: unless this represents an ASM insn. */ 8212: 8213: if (insn_code_number < 0 && ! check_asm_operands (pat) 8214: && GET_CODE (pat) == PARALLEL) 8215: { 8216: int pos; 8217: 8218: for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++) 8219: if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER) 8220: { 8221: if (i != pos) 8222: SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i)); 8223: pos++; 8224: } 8225: 8226: SUBST_INT (XVECLEN (pat, 0), pos); 8227: 8228: if (pos == 1) 8229: pat = XVECEXP (pat, 0, 0); 8230: 8231: insn_code_number = recog (pat, insn, &num_clobbers_to_add); 8232: } 8233: 8234: /* If we had any clobbers to add, make a new pattern than contains 8235: them. Then check to make sure that all of them are dead. */ 8236: if (num_clobbers_to_add) 8237: { 8238: rtx newpat = gen_rtx (PARALLEL, VOIDmode, 8239: gen_rtvec (GET_CODE (pat) == PARALLEL 8240: ? XVECLEN (pat, 0) + num_clobbers_to_add 8241: : num_clobbers_to_add + 1)); 8242: 8243: if (GET_CODE (pat) == PARALLEL) 8244: for (i = 0; i < XVECLEN (pat, 0); i++) 8245: XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i); 8246: else 8247: XVECEXP (newpat, 0, 0) = pat; 8248: 8249: add_clobbers (newpat, insn_code_number); 8250: 8251: for (i = XVECLEN (newpat, 0) - num_clobbers_to_add; 8252: i < XVECLEN (newpat, 0); i++) 8253: { 8254: if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG 8255: && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn)) 8256: return -1; 8257: notes = gen_rtx (EXPR_LIST, REG_UNUSED, 8258: XEXP (XVECEXP (newpat, 0, i), 0), notes); 8259: } 8260: pat = newpat; 8261: } 8262: 8263: *pnewpat = pat; 8264: *pnotes = notes; 8265: 8266: return insn_code_number; 8267: } 8268: 8269: /* Like gen_lowpart but for use by combine. In combine it is not possible 8270: to create any new pseudoregs. However, it is safe to create 8271: invalid memory addresses, because combine will try to recognize 8272: them and all they will do is make the combine attempt fail. 8273: 8274: If for some reason this cannot do its job, an rtx 8275: (clobber (const_int 0)) is returned. 8276: An insn containing that will not be recognized. */ 8277: 8278: #undef gen_lowpart 8279: 8280: static rtx 8281: gen_lowpart_for_combine (mode, x) 8282: enum machine_mode mode; 8283: register rtx x; 8284: { 8285: rtx result; 8286: 8287: if (GET_MODE (x) == mode) 8288: return x; 8289: 1.1.1.5 root 8290: /* We can only support MODE being wider than a word if X is a 8291: constant integer or has a mode the same size. */ 8292: 8293: if (GET_MODE_SIZE (mode) > UNITS_PER_WORD 8294: && ! ((GET_MODE (x) == VOIDmode 8295: && (GET_CODE (x) == CONST_INT 8296: || GET_CODE (x) == CONST_DOUBLE)) 8297: || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode))) 1.1 root 8298: return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx); 8299: 8300: /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart 8301: won't know what to do. So we will strip off the SUBREG here and 8302: process normally. */ 8303: if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM) 8304: { 8305: x = SUBREG_REG (x); 8306: if (GET_MODE (x) == mode) 8307: return x; 8308: } 8309: 8310: result = gen_lowpart_common (mode, x); 8311: if (result) 8312: return result; 8313: 8314: if (GET_CODE (x) == MEM) 8315: { 8316: register int offset = 0; 8317: rtx new; 8318: 8319: /* Refuse to work on a volatile memory ref or one with a mode-dependent 8320: address. */ 8321: if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0))) 8322: return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx); 8323: 8324: /* If we want to refer to something bigger than the original memref, 8325: generate a perverse subreg instead. That will force a reload 8326: of the original memref X. */ 8327: if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)) 8328: return gen_rtx (SUBREG, mode, x, 0); 8329: 8330: #if WORDS_BIG_ENDIAN 8331: offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) 8332: - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); 8333: #endif 8334: #if BYTES_BIG_ENDIAN 8335: /* Adjust the address so that the address-after-the-data 8336: is unchanged. */ 8337: offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)) 8338: - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x)))); 8339: #endif 8340: new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset)); 8341: RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x); 8342: MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x); 8343: MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x); 8344: return new; 8345: } 8346: 8347: /* If X is a comparison operator, rewrite it in a new mode. This 8348: probably won't match, but may allow further simplifications. */ 8349: else if (GET_RTX_CLASS (GET_CODE (x)) == '<') 8350: return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1)); 8351: 8352: /* If we couldn't simplify X any other way, just enclose it in a 8353: SUBREG. Normally, this SUBREG won't match, but some patterns may 1.1.1.3 root 8354: include an explicit SUBREG or we may simplify it further in combine. */ 1.1 root 8355: else 1.1.1.2 root 8356: { 8357: int word = 0; 8358: 8359: if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) 8360: word = ((GET_MODE_SIZE (GET_MODE (x)) 8361: - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)) 8362: / UNITS_PER_WORD); 8363: return gen_rtx (SUBREG, mode, x, word); 8364: } 1.1 root 8365: } 8366: 8367: /* Make an rtx expression. This is a subset of gen_rtx and only supports 8368: expressions of 1, 2, or 3 operands, each of which are rtx expressions. 8369: 8370: If the identical expression was previously in the insn (in the undobuf), 8371: it will be returned. Only if it is not found will a new expression 8372: be made. */ 8373: 8374: /*VARARGS2*/ 8375: static rtx 1.1.1.7 ! root 8376: gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...)) 1.1 root 8377: { 1.1.1.7 ! root 8378: #ifndef __STDC__ 1.1 root 8379: enum rtx_code code; 8380: enum machine_mode mode; 1.1.1.7 ! root 8381: #endif ! 8382: va_list p; 1.1 root 8383: int n_args; 8384: rtx args[3]; 8385: int i, j; 8386: char *fmt; 8387: rtx rt; 8388: 1.1.1.7 ! root 8389: VA_START (p, mode); ! 8390: ! 8391: #ifndef __STDC__ 1.1 root 8392: code = va_arg (p, enum rtx_code); 8393: mode = va_arg (p, enum machine_mode); 1.1.1.7 ! root 8394: #endif ! 8395: 1.1 root 8396: n_args = GET_RTX_LENGTH (code); 8397: fmt = GET_RTX_FORMAT (code); 8398: 8399: if (n_args == 0 || n_args > 3) 8400: abort (); 8401: 8402: /* Get each arg and verify that it is supposed to be an expression. */ 8403: for (j = 0; j < n_args; j++) 8404: { 8405: if (*fmt++ != 'e') 8406: abort (); 8407: 8408: args[j] = va_arg (p, rtx); 8409: } 8410: 8411: /* See if this is in undobuf. Be sure we don't use objects that came 8412: from another insn; this could produce circular rtl structures. */ 8413: 8414: for (i = previous_num_undos; i < undobuf.num_undo; i++) 8415: if (!undobuf.undo[i].is_int 1.1.1.6 root 8416: && GET_CODE (undobuf.undo[i].old_contents.r) == code 8417: && GET_MODE (undobuf.undo[i].old_contents.r) == mode) 1.1 root 8418: { 8419: for (j = 0; j < n_args; j++) 1.1.1.6 root 8420: if (XEXP (undobuf.undo[i].old_contents.r, j) != args[j]) 1.1 root 8421: break; 8422: 8423: if (j == n_args) 1.1.1.6 root 8424: return undobuf.undo[i].old_contents.r; 1.1 root 8425: } 8426: 8427: /* Otherwise make a new rtx. We know we have 1, 2, or 3 args. 8428: Use rtx_alloc instead of gen_rtx because it's faster on RISC. */ 8429: rt = rtx_alloc (code); 8430: PUT_MODE (rt, mode); 8431: XEXP (rt, 0) = args[0]; 8432: if (n_args > 1) 8433: { 8434: XEXP (rt, 1) = args[1]; 8435: if (n_args > 2) 8436: XEXP (rt, 2) = args[2]; 8437: } 8438: return rt; 8439: } 8440: 8441: /* These routines make binary and unary operations by first seeing if they 8442: fold; if not, a new expression is allocated. */ 8443: 8444: static rtx 8445: gen_binary (code, mode, op0, op1) 8446: enum rtx_code code; 8447: enum machine_mode mode; 8448: rtx op0, op1; 8449: { 8450: rtx result; 1.1.1.4 root 8451: rtx tem; 8452: 8453: if (GET_RTX_CLASS (code) == 'c' 8454: && (GET_CODE (op0) == CONST_INT 8455: || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT))) 8456: tem = op0, op0 = op1, op1 = tem; 1.1 root 8457: 8458: if (GET_RTX_CLASS (code) == '<') 8459: { 8460: enum machine_mode op_mode = GET_MODE (op0); 1.1.1.7 ! root 8461: ! 8462: /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get ! 8463: just (REL_OP X Y). */ ! 8464: if (GET_CODE (op0) == COMPARE && op1 == const0_rtx) ! 8465: { ! 8466: op1 = XEXP (op0, 1); ! 8467: op0 = XEXP (op0, 0); ! 8468: op_mode = GET_MODE (op0); ! 8469: } ! 8470: 1.1 root 8471: if (op_mode == VOIDmode) 8472: op_mode = GET_MODE (op1); 8473: result = simplify_relational_operation (code, op_mode, op0, op1); 8474: } 8475: else 8476: result = simplify_binary_operation (code, mode, op0, op1); 8477: 8478: if (result) 8479: return result; 8480: 8481: /* Put complex operands first and constants second. */ 8482: if (GET_RTX_CLASS (code) == 'c' 8483: && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT) 8484: || (GET_RTX_CLASS (GET_CODE (op0)) == 'o' 8485: && GET_RTX_CLASS (GET_CODE (op1)) != 'o') 8486: || (GET_CODE (op0) == SUBREG 8487: && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o' 8488: && GET_RTX_CLASS (GET_CODE (op1)) != 'o'))) 8489: return gen_rtx_combine (code, mode, op1, op0); 8490: 8491: return gen_rtx_combine (code, mode, op0, op1); 8492: } 8493: 8494: static rtx 1.1.1.7 ! root 8495: gen_unary (code, mode, op0_mode, op0) 1.1 root 8496: enum rtx_code code; 1.1.1.7 ! root 8497: enum machine_mode mode, op0_mode; 1.1 root 8498: rtx op0; 8499: { 1.1.1.7 ! root 8500: rtx result = simplify_unary_operation (code, mode, op0, op0_mode); 1.1 root 8501: 8502: if (result) 8503: return result; 8504: 8505: return gen_rtx_combine (code, mode, op0); 8506: } 8507: 8508: /* Simplify a comparison between *POP0 and *POP1 where CODE is the 8509: comparison code that will be tested. 8510: 8511: The result is a possibly different comparison code to use. *POP0 and 8512: *POP1 may be updated. 8513: 8514: It is possible that we might detect that a comparison is either always 8515: true or always false. However, we do not perform general constant 1.1.1.2 root 8516: folding in combine, so this knowledge isn't useful. Such tautologies 1.1 root 8517: should have been detected earlier. Hence we ignore all such cases. */ 8518: 8519: static enum rtx_code 8520: simplify_comparison (code, pop0, pop1) 8521: enum rtx_code code; 8522: rtx *pop0; 8523: rtx *pop1; 8524: { 8525: rtx op0 = *pop0; 8526: rtx op1 = *pop1; 8527: rtx tem, tem1; 8528: int i; 8529: enum machine_mode mode, tmode; 8530: 8531: /* Try a few ways of applying the same transformation to both operands. */ 8532: while (1) 8533: { 1.1.1.7 ! root 8534: #ifndef WORD_REGISTER_OPERATIONS ! 8535: /* The test below this one won't handle SIGN_EXTENDs on these machines, ! 8536: so check specially. */ ! 8537: if (code != GTU && code != GEU && code != LTU && code != LEU ! 8538: && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT ! 8539: && GET_CODE (XEXP (op0, 0)) == ASHIFT ! 8540: && GET_CODE (XEXP (op1, 0)) == ASHIFT ! 8541: && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG ! 8542: && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG ! 8543: && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))) ! 8544: == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0)))) ! 8545: && GET_CODE (XEXP (op0, 1)) == CONST_INT ! 8546: && GET_CODE (XEXP (op1, 1)) == CONST_INT ! 8547: && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT ! 8548: && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT ! 8549: && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1)) ! 8550: && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1)) ! 8551: && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1)) ! 8552: && (INTVAL (XEXP (op0, 1)) ! 8553: == (GET_MODE_BITSIZE (GET_MODE (op0)) ! 8554: - (GET_MODE_BITSIZE ! 8555: (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))))))) ! 8556: { ! 8557: op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0)); ! 8558: op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0)); ! 8559: } ! 8560: #endif ! 8561: 1.1 root 8562: /* If both operands are the same constant shift, see if we can ignore the 8563: shift. We can if the shift is a rotate or if the bits shifted out of 1.1.1.5 root 8564: this shift are known to be zero for both inputs and if the type of 1.1 root 8565: comparison is compatible with the shift. */ 8566: if (GET_CODE (op0) == GET_CODE (op1) 1.1.1.4 root 8567: && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT 1.1 root 8568: && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ)) 1.1.1.7 ! root 8569: || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT) 1.1 root 8570: && (code != GT && code != LT && code != GE && code != LE)) 8571: || (GET_CODE (op0) == ASHIFTRT 8572: && (code != GTU && code != LTU 8573: && code != GEU && code != GEU))) 8574: && GET_CODE (XEXP (op0, 1)) == CONST_INT 8575: && INTVAL (XEXP (op0, 1)) >= 0 1.1.1.4 root 8576: && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT 1.1 root 8577: && XEXP (op0, 1) == XEXP (op1, 1)) 8578: { 8579: enum machine_mode mode = GET_MODE (op0); 1.1.1.4 root 8580: unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 1.1 root 8581: int shift_count = INTVAL (XEXP (op0, 1)); 8582: 8583: if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT) 8584: mask &= (mask >> shift_count) << shift_count; 1.1.1.7 ! root 8585: else if (GET_CODE (op0) == ASHIFT) 1.1 root 8586: mask = (mask & (mask << shift_count)) >> shift_count; 8587: 1.1.1.5 root 8588: if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0 8589: && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0) 1.1 root 8590: op0 = XEXP (op0, 0), op1 = XEXP (op1, 0); 8591: else 8592: break; 8593: } 8594: 8595: /* If both operands are AND's of a paradoxical SUBREG by constant, the 8596: SUBREGs are of the same mode, and, in both cases, the AND would 8597: be redundant if the comparison was done in the narrower mode, 8598: do the comparison in the narrower mode (e.g., we are AND'ing with 1 1.1.1.5 root 8599: and the operand's possibly nonzero bits are 0xffffff01; in that case 8600: if we only care about QImode, we don't need the AND). This case 8601: occurs if the output mode of an scc insn is not SImode and 1.1.1.7 ! root 8602: STORE_FLAG_VALUE == 1 (e.g., the 386). ! 8603: ! 8604: Similarly, check for a case where the AND's are ZERO_EXTEND ! 8605: operations from some narrower mode even though a SUBREG is not ! 8606: present. */ 1.1 root 8607: 8608: else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND 8609: && GET_CODE (XEXP (op0, 1)) == CONST_INT 1.1.1.7 ! root 8610: && GET_CODE (XEXP (op1, 1)) == CONST_INT) ! 8611: { ! 8612: rtx inner_op0 = XEXP (op0, 0); ! 8613: rtx inner_op1 = XEXP (op1, 0); ! 8614: HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1)); ! 8615: HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1)); ! 8616: int changed = 0; ! 8617: ! 8618: if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG ! 8619: && (GET_MODE_SIZE (GET_MODE (inner_op0)) ! 8620: > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0)))) ! 8621: && (GET_MODE (SUBREG_REG (inner_op0)) ! 8622: == GET_MODE (SUBREG_REG (inner_op1))) ! 8623: && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) ! 8624: <= HOST_BITS_PER_WIDE_INT) ! 8625: && (0 == (~c0) & nonzero_bits (SUBREG_REG (inner_op0), ! 8626: GET_MODE (SUBREG_REG (op0)))) ! 8627: && (0 == (~c1) & nonzero_bits (SUBREG_REG (inner_op1), ! 8628: GET_MODE (SUBREG_REG (inner_op1))))) ! 8629: { ! 8630: op0 = SUBREG_REG (inner_op0); ! 8631: op1 = SUBREG_REG (inner_op1); ! 8632: ! 8633: /* The resulting comparison is always unsigned since we masked ! 8634: off the original sign bit. */ ! 8635: code = unsigned_condition (code); ! 8636: ! 8637: changed = 1; ! 8638: } ! 8639: ! 8640: else if (c0 == c1) ! 8641: for (tmode = GET_CLASS_NARROWEST_MODE ! 8642: (GET_MODE_CLASS (GET_MODE (op0))); ! 8643: tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode)) ! 8644: if (c0 == GET_MODE_MASK (tmode)) ! 8645: { ! 8646: op0 = gen_lowpart_for_combine (tmode, inner_op0); ! 8647: op1 = gen_lowpart_for_combine (tmode, inner_op1); ! 8648: code = unsigned_condition (code); ! 8649: changed = 1; ! 8650: break; ! 8651: } ! 8652: ! 8653: if (! changed) ! 8654: break; 1.1 root 8655: } 1.1.1.7 ! root 8656: ! 8657: /* If both operands are NOT, we can strip off the outer operation ! 8658: and adjust the comparison code for swapped operands; similarly for ! 8659: NEG, except that this must be an equality comparison. */ ! 8660: else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT) ! 8661: || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG ! 8662: && (code == EQ || code == NE))) ! 8663: op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code); ! 8664: 1.1 root 8665: else 8666: break; 8667: } 8668: 8669: /* If the first operand is a constant, swap the operands and adjust the 8670: comparison code appropriately. */ 8671: if (CONSTANT_P (op0)) 8672: { 8673: tem = op0, op0 = op1, op1 = tem; 8674: code = swap_condition (code); 8675: } 8676: 8677: /* We now enter a loop during which we will try to simplify the comparison. 8678: For the most part, we only are concerned with comparisons with zero, 8679: but some things may really be comparisons with zero but not start 8680: out looking that way. */ 8681: 8682: while (GET_CODE (op1) == CONST_INT) 8683: { 8684: enum machine_mode mode = GET_MODE (op0); 8685: int mode_width = GET_MODE_BITSIZE (mode); 1.1.1.4 root 8686: unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); 1.1 root 8687: int equality_comparison_p; 8688: int sign_bit_comparison_p; 8689: int unsigned_comparison_p; 1.1.1.4 root 8690: HOST_WIDE_INT const_op; 1.1 root 8691: 8692: /* We only want to handle integral modes. This catches VOIDmode, 8693: CCmode, and the floating-point modes. An exception is that we 8694: can handle VOIDmode if OP0 is a COMPARE or a comparison 8695: operation. */ 8696: 8697: if (GET_MODE_CLASS (mode) != MODE_INT 8698: && ! (mode == VOIDmode 8699: && (GET_CODE (op0) == COMPARE 8700: || GET_RTX_CLASS (GET_CODE (op0)) == '<'))) 8701: break; 8702: 8703: /* Get the constant we are comparing against and turn off all bits 8704: not on in our mode. */ 8705: const_op = INTVAL (op1); 1.1.1.4 root 8706: if (mode_width <= HOST_BITS_PER_WIDE_INT) 1.1.1.3 root 8707: const_op &= mask; 1.1 root 8708: 8709: /* If we are comparing against a constant power of two and the value 1.1.1.5 root 8710: being compared can only have that single bit nonzero (e.g., it was 1.1 root 8711: `and'ed with that bit), we can replace this with a comparison 8712: with zero. */ 8713: if (const_op 8714: && (code == EQ || code == NE || code == GE || code == GEU 8715: || code == LT || code == LTU) 1.1.1.4 root 8716: && mode_width <= HOST_BITS_PER_WIDE_INT 1.1 root 8717: && exact_log2 (const_op) >= 0 1.1.1.5 root 8718: && nonzero_bits (op0, mode) == const_op) 1.1 root 8719: { 8720: code = (code == EQ || code == GE || code == GEU ? NE : EQ); 8721: op1 = const0_rtx, const_op = 0; 8722: } 8723: 1.1.1.4 root 8724: /* Similarly, if we are comparing a value known to be either -1 or 8725: 0 with -1, change it to the opposite comparison against zero. */ 8726: 8727: if (const_op == -1 8728: && (code == EQ || code == NE || code == GT || code == LE 8729: || code == GEU || code == LTU) 8730: && num_sign_bit_copies (op0, mode) == mode_width) 8731: { 8732: code = (code == EQ || code == LE || code == GEU ? NE : EQ); 8733: op1 = const0_rtx, const_op = 0; 8734: } 8735: 1.1 root 8736: /* Do some canonicalizations based on the comparison code. We prefer 1.1.1.3 root 8737: comparisons against zero and then prefer equality comparisons. 8738: If we can reduce the size of a constant, we will do that too. */ 1.1 root 8739: 8740: switch (code) 8741: { 8742: case LT: 1.1.1.3 root 8743: /* < C is equivalent to <= (C - 1) */ 8744: if (const_op > 0) 1.1 root 8745: { 1.1.1.3 root 8746: const_op -= 1; 1.1.1.4 root 8747: op1 = GEN_INT (const_op); 1.1 root 8748: code = LE; 8749: /* ... fall through to LE case below. */ 8750: } 8751: else 8752: break; 8753: 8754: case LE: 1.1.1.3 root 8755: /* <= C is equivalent to < (C + 1); we do this for C < 0 */ 8756: if (const_op < 0) 8757: { 8758: const_op += 1; 1.1.1.4 root 8759: op1 = GEN_INT (const_op); 1.1.1.3 root 8760: code = LT; 8761: } 1.1 root 8762: 8763: /* If we are doing a <= 0 comparison on a value known to have 8764: a zero sign bit, we can replace this with == 0. */ 8765: else if (const_op == 0 1.1.1.4 root 8766: && mode_width <= HOST_BITS_PER_WIDE_INT 1.1.1.5 root 8767: && (nonzero_bits (op0, mode) 1.1.1.4 root 8768: & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0) 1.1 root 8769: code = EQ; 8770: break; 8771: 8772: case GE: 1.1.1.3 root 8773: /* >= C is equivalent to > (C - 1). */ 8774: if (const_op > 0) 1.1 root 8775: { 1.1.1.3 root 8776: const_op -= 1; 1.1.1.4 root 8777: op1 = GEN_INT (const_op); 1.1 root 8778: code = GT; 8779: /* ... fall through to GT below. */ 8780: } 8781: else 8782: break; 8783: 8784: case GT: 1.1.1.3 root 8785: /* > C is equivalent to >= (C + 1); we do this for C < 0*/ 8786: if (const_op < 0) 8787: { 8788: const_op += 1; 1.1.1.4 root 8789: op1 = GEN_INT (const_op); 1.1.1.3 root 8790: code = GE; 8791: } 1.1 root 8792: 8793: /* If we are doing a > 0 comparison on a value known to have 8794: a zero sign bit, we can replace this with != 0. */ 8795: else if (const_op == 0 1.1.1.4 root 8796: && mode_width <= HOST_BITS_PER_WIDE_INT 1.1.1.5 root 8797: && (nonzero_bits (op0, mode) 1.1.1.4 root 8798: & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0) 1.1 root 8799: code = NE; 8800: break; 8801: 8802: case LTU: 1.1.1.3 root 8803: /* < C is equivalent to <= (C - 1). */ 8804: if (const_op > 0) 8805: { 8806: const_op -= 1; 1.1.1.4 root 8807: op1 = GEN_INT (const_op); 1.1.1.3 root 8808: code = LEU; 8809: /* ... fall through ... */ 8810: } 1.1.1.4 root 8811: 8812: /* (unsigned) < 0x80000000 is equivalent to >= 0. */ 8813: else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)) 8814: { 8815: const_op = 0, op1 = const0_rtx; 8816: code = GE; 8817: break; 8818: } 1.1.1.3 root 8819: else 8820: break; 1.1 root 8821: 8822: case LEU: 8823: /* unsigned <= 0 is equivalent to == 0 */ 8824: if (const_op == 0) 8825: code = EQ; 1.1.1.4 root 8826: 8827: /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */ 8828: else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1) 8829: { 8830: const_op = 0, op1 = const0_rtx; 8831: code = GE; 8832: } 1.1 root 8833: break; 8834: 1.1.1.3 root 8835: case GEU: 8836: /* >= C is equivalent to < (C - 1). */ 8837: if (const_op > 1) 8838: { 8839: const_op -= 1; 1.1.1.4 root 8840: op1 = GEN_INT (const_op); 1.1.1.3 root 8841: code = GTU; 8842: /* ... fall through ... */ 8843: } 1.1.1.4 root 8844: 8845: /* (unsigned) >= 0x80000000 is equivalent to < 0. */ 8846: else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)) 8847: { 8848: const_op = 0, op1 = const0_rtx; 8849: code = LT; 1.1.1.7 ! root 8850: break; 1.1.1.4 root 8851: } 1.1.1.3 root 8852: else 8853: break; 8854: 1.1 root 8855: case GTU: 8856: /* unsigned > 0 is equivalent to != 0 */ 8857: if (const_op == 0) 8858: code = NE; 1.1.1.4 root 8859: 8860: /* (unsigned) > 0x7fffffff is equivalent to < 0. */ 8861: else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1) 8862: { 8863: const_op = 0, op1 = const0_rtx; 8864: code = LT; 8865: } 1.1 root 8866: break; 8867: } 8868: 8869: /* Compute some predicates to simplify code below. */ 8870: 8871: equality_comparison_p = (code == EQ || code == NE); 8872: sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0); 8873: unsigned_comparison_p = (code == LTU || code == LEU || code == GTU 8874: || code == LEU); 8875: 1.1.1.6 root 8876: /* If this is a sign bit comparison and we can do arithmetic in 8877: MODE, say that we will only be needing the sign bit of OP0. */ 8878: if (sign_bit_comparison_p 8879: && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 8880: op0 = force_to_mode (op0, mode, 8881: ((HOST_WIDE_INT) 1 8882: << (GET_MODE_BITSIZE (mode) - 1)), 8883: NULL_RTX, 0); 8884: 1.1 root 8885: /* Now try cases based on the opcode of OP0. If none of the cases 8886: does a "continue", we exit this loop immediately after the 8887: switch. */ 8888: 8889: switch (GET_CODE (op0)) 8890: { 8891: case ZERO_EXTRACT: 8892: /* If we are extracting a single bit from a variable position in 8893: a constant that has only a single bit set and are comparing it 8894: with zero, we can convert this into an equality comparison 8895: between the position and the location of the single bit. We can't 8896: do this if bit endian and we don't have an extzv since we then 8897: can't know what mode to use for the endianness adjustment. */ 8898: 8899: #if ! BITS_BIG_ENDIAN || defined (HAVE_extzv) 8900: if (GET_CODE (XEXP (op0, 0)) == CONST_INT 8901: && XEXP (op0, 1) == const1_rtx 8902: && equality_comparison_p && const_op == 0 8903: && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0) 8904: { 8905: #if BITS_BIG_ENDIAN 8906: i = (GET_MODE_BITSIZE 8907: (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i); 8908: #endif 8909: 8910: op0 = XEXP (op0, 2); 1.1.1.4 root 8911: op1 = GEN_INT (i); 1.1 root 8912: const_op = i; 8913: 8914: /* Result is nonzero iff shift count is equal to I. */ 8915: code = reverse_condition (code); 8916: continue; 8917: } 8918: #endif 8919: 8920: /* ... fall through ... */ 8921: 8922: case SIGN_EXTRACT: 8923: tem = expand_compound_operation (op0); 8924: if (tem != op0) 8925: { 8926: op0 = tem; 8927: continue; 8928: } 8929: break; 8930: 8931: case NOT: 8932: /* If testing for equality, we can take the NOT of the constant. */ 8933: if (equality_comparison_p 8934: && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0) 8935: { 8936: op0 = XEXP (op0, 0); 8937: op1 = tem; 8938: continue; 8939: } 8940: 8941: /* If just looking at the sign bit, reverse the sense of the 8942: comparison. */ 8943: if (sign_bit_comparison_p) 8944: { 8945: op0 = XEXP (op0, 0); 8946: code = (code == GE ? LT : GE); 8947: continue; 8948: } 8949: break; 8950: 8951: case NEG: 8952: /* If testing for equality, we can take the NEG of the constant. */ 8953: if (equality_comparison_p 8954: && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0) 8955: { 8956: op0 = XEXP (op0, 0); 8957: op1 = tem; 8958: continue; 8959: } 8960: 8961: /* The remaining cases only apply to comparisons with zero. */ 8962: if (const_op != 0) 8963: break; 8964: 8965: /* When X is ABS or is known positive, 8966: (neg X) is < 0 if and only if X != 0. */ 8967: 8968: if (sign_bit_comparison_p 8969: && (GET_CODE (XEXP (op0, 0)) == ABS 1.1.1.4 root 8970: || (mode_width <= HOST_BITS_PER_WIDE_INT 1.1.1.5 root 8971: && (nonzero_bits (XEXP (op0, 0), mode) 1.1.1.4 root 8972: & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0))) 1.1 root 8973: { 8974: op0 = XEXP (op0, 0); 8975: code = (code == LT ? NE : EQ); 8976: continue; 8977: } 8978: 1.1.1.5 root 8979: /* If we have NEG of something whose two high-order bits are the 8980: same, we know that "(-a) < 0" is equivalent to "a > 0". */ 8981: if (num_sign_bit_copies (op0, mode) >= 2) 1.1 root 8982: { 8983: op0 = XEXP (op0, 0); 8984: code = swap_condition (code); 8985: continue; 8986: } 8987: break; 8988: 8989: case ROTATE: 8990: /* If we are testing equality and our count is a constant, we 8991: can perform the inverse operation on our RHS. */ 8992: if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT 8993: && (tem = simplify_binary_operation (ROTATERT, mode, 8994: op1, XEXP (op0, 1))) != 0) 8995: { 8996: op0 = XEXP (op0, 0); 8997: op1 = tem; 8998: continue; 8999: } 9000: 9001: /* If we are doing a < 0 or >= 0 comparison, it means we are testing 9002: a particular bit. Convert it to an AND of a constant of that 9003: bit. This will be converted into a ZERO_EXTRACT. */ 9004: if (const_op == 0 && sign_bit_comparison_p 9005: && GET_CODE (XEXP (op0, 1)) == CONST_INT 1.1.1.4 root 9006: && mode_width <= HOST_BITS_PER_WIDE_INT) 1.1 root 9007: { 1.1.1.4 root 9008: op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 9009: ((HOST_WIDE_INT) 1 9010: << (mode_width - 1 9011: - INTVAL (XEXP (op0, 1))))); 1.1 root 9012: code = (code == LT ? NE : EQ); 9013: continue; 9014: } 9015: 9016: /* ... fall through ... */ 9017: 9018: case ABS: 9019: /* ABS is ignorable inside an equality comparison with zero. */ 9020: if (const_op == 0 && equality_comparison_p) 9021: { 9022: op0 = XEXP (op0, 0); 9023: continue; 9024: } 9025: break; 9026: 9027: 9028: case SIGN_EXTEND: 9029: /* Can simplify (compare (zero/sign_extend FOO) CONST) 9030: to (compare FOO CONST) if CONST fits in FOO's mode and we 9031: are either testing inequality or have an unsigned comparison 9032: with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */ 9033: if (! unsigned_comparison_p 9034: && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) 1.1.1.4 root 9035: <= HOST_BITS_PER_WIDE_INT) 9036: && ((unsigned HOST_WIDE_INT) const_op 9037: < (((HOST_WIDE_INT) 1 9038: << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1))))) 1.1 root 9039: { 9040: op0 = XEXP (op0, 0); 9041: continue; 9042: } 9043: break; 9044: 9045: case SUBREG: 1.1.1.4 root 9046: /* Check for the case where we are comparing A - C1 with C2, 9047: both constants are smaller than 1/2 the maxium positive 9048: value in MODE, and the comparison is equality or unsigned. 9049: In that case, if A is either zero-extended to MODE or has 9050: sufficient sign bits so that the high-order bit in MODE 9051: is a copy of the sign in the inner mode, we can prove that it is 9052: safe to do the operation in the wider mode. This simplifies 9053: many range checks. */ 9054: 9055: if (mode_width <= HOST_BITS_PER_WIDE_INT 9056: && subreg_lowpart_p (op0) 9057: && GET_CODE (SUBREG_REG (op0)) == PLUS 9058: && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT 9059: && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0 9060: && (- INTVAL (XEXP (SUBREG_REG (op0), 1)) 9061: < GET_MODE_MASK (mode) / 2) 1.1.1.5 root 9062: && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2 9063: && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0), 9064: GET_MODE (SUBREG_REG (op0))) 1.1.1.4 root 9065: & ~ GET_MODE_MASK (mode)) 9066: || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0), 9067: GET_MODE (SUBREG_REG (op0))) 9068: > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) 9069: - GET_MODE_BITSIZE (mode))))) 9070: { 9071: op0 = SUBREG_REG (op0); 9072: continue; 9073: } 9074: 9075: /* If the inner mode is narrower and we are extracting the low part, 9076: we can treat the SUBREG as if it were a ZERO_EXTEND. */ 9077: if (subreg_lowpart_p (op0) 9078: && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width) 9079: /* Fall through */ ; 9080: else 1.1 root 9081: break; 9082: 9083: /* ... fall through ... */ 9084: 9085: case ZERO_EXTEND: 9086: if ((unsigned_comparison_p || equality_comparison_p) 9087: && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) 1.1.1.4 root 9088: <= HOST_BITS_PER_WIDE_INT) 9089: && ((unsigned HOST_WIDE_INT) const_op 1.1 root 9090: < GET_MODE_MASK (GET_MODE (XEXP (op0, 0))))) 9091: { 9092: op0 = XEXP (op0, 0); 9093: continue; 9094: } 9095: break; 9096: 9097: case PLUS: 1.1.1.5 root 9098: /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do 1.1.1.2 root 9099: this for equality comparisons due to pathological cases involving 1.1 root 9100: overflows. */ 1.1.1.5 root 9101: if (equality_comparison_p 9102: && 0 != (tem = simplify_binary_operation (MINUS, mode, 9103: op1, XEXP (op0, 1)))) 1.1 root 9104: { 9105: op0 = XEXP (op0, 0); 9106: op1 = tem; 9107: continue; 9108: } 9109: 9110: /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */ 9111: if (const_op == 0 && XEXP (op0, 1) == constm1_rtx 9112: && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p) 9113: { 9114: op0 = XEXP (XEXP (op0, 0), 0); 9115: code = (code == LT ? EQ : NE); 9116: continue; 9117: } 9118: break; 9119: 9120: case MINUS: 1.1.1.5 root 9121: /* (eq (minus A B) C) -> (eq A (plus B C)) or 9122: (eq B (minus A C)), whichever simplifies. We can only do 9123: this for equality comparisons due to pathological cases involving 9124: overflows. */ 9125: if (equality_comparison_p 9126: && 0 != (tem = simplify_binary_operation (PLUS, mode, 9127: XEXP (op0, 1), op1))) 9128: { 9129: op0 = XEXP (op0, 0); 9130: op1 = tem; 9131: continue; 9132: } 9133: 9134: if (equality_comparison_p 9135: && 0 != (tem = simplify_binary_operation (MINUS, mode, 9136: XEXP (op0, 0), op1))) 9137: { 9138: op0 = XEXP (op0, 1); 9139: op1 = tem; 9140: continue; 9141: } 9142: 1.1 root 9143: /* The sign bit of (minus (ashiftrt X C) X), where C is the number 9144: of bits in X minus 1, is one iff X > 0. */ 9145: if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT 9146: && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT 9147: && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1 9148: && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) 9149: { 9150: op0 = XEXP (op0, 1); 9151: code = (code == GE ? LE : GT); 9152: continue; 9153: } 9154: break; 9155: 9156: case XOR: 9157: /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification 9158: if C is zero or B is a constant. */ 9159: if (equality_comparison_p 9160: && 0 != (tem = simplify_binary_operation (XOR, mode, 9161: XEXP (op0, 1), op1))) 9162: { 9163: op0 = XEXP (op0, 0); 9164: op1 = tem; 9165: continue; 9166: } 9167: break; 9168: 9169: case EQ: case NE: 9170: case LT: case LTU: case LE: case LEU: 9171: case GT: case GTU: case GE: case GEU: 9172: /* We can't do anything if OP0 is a condition code value, rather 9173: than an actual data value. */ 9174: if (const_op != 0 9175: #ifdef HAVE_cc0 9176: || XEXP (op0, 0) == cc0_rtx 9177: #endif 9178: || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC) 9179: break; 9180: 9181: /* Get the two operands being compared. */ 9182: if (GET_CODE (XEXP (op0, 0)) == COMPARE) 9183: tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1); 9184: else 9185: tem = XEXP (op0, 0), tem1 = XEXP (op0, 1); 9186: 9187: /* Check for the cases where we simply want the result of the 9188: earlier test or the opposite of that result. */ 9189: if (code == NE 9190: || (code == EQ && reversible_comparison_p (op0)) 1.1.1.4 root 9191: || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT 1.1.1.3 root 9192: && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT 1.1 root 9193: && (STORE_FLAG_VALUE 1.1.1.4 root 9194: & (((HOST_WIDE_INT) 1 9195: << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1)))) 1.1 root 9196: && (code == LT 9197: || (code == GE && reversible_comparison_p (op0))))) 9198: { 9199: code = (code == LT || code == NE 9200: ? GET_CODE (op0) : reverse_condition (GET_CODE (op0))); 9201: op0 = tem, op1 = tem1; 9202: continue; 9203: } 9204: break; 9205: 9206: case IOR: 9207: /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero 9208: iff X <= 0. */ 9209: if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS 9210: && XEXP (XEXP (op0, 0), 1) == constm1_rtx 9211: && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) 9212: { 9213: op0 = XEXP (op0, 1); 9214: code = (code == GE ? GT : LE); 9215: continue; 9216: } 9217: break; 9218: 9219: case AND: 9220: /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This 9221: will be converted to a ZERO_EXTRACT later. */ 9222: if (const_op == 0 && equality_comparison_p 1.1.1.7 ! root 9223: && GET_CODE (XEXP (op0, 0)) == ASHIFT 1.1 root 9224: && XEXP (XEXP (op0, 0), 0) == const1_rtx) 9225: { 9226: op0 = simplify_and_const_int 9227: (op0, mode, gen_rtx_combine (LSHIFTRT, mode, 9228: XEXP (op0, 1), 9229: XEXP (XEXP (op0, 0), 1)), 1.1.1.4 root 9230: (HOST_WIDE_INT) 1); 1.1 root 9231: continue; 9232: } 9233: 9234: /* If we are comparing (and (lshiftrt X C1) C2) for equality with 9235: zero and X is a comparison and C1 and C2 describe only bits set 9236: in STORE_FLAG_VALUE, we can compare with X. */ 9237: if (const_op == 0 && equality_comparison_p 1.1.1.4 root 9238: && mode_width <= HOST_BITS_PER_WIDE_INT 1.1 root 9239: && GET_CODE (XEXP (op0, 1)) == CONST_INT 9240: && GET_CODE (XEXP (op0, 0)) == LSHIFTRT 9241: && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT 9242: && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0 1.1.1.4 root 9243: && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT) 1.1 root 9244: { 9245: mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) 9246: << INTVAL (XEXP (XEXP (op0, 0), 1))); 9247: if ((~ STORE_FLAG_VALUE & mask) == 0 9248: && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<' 9249: || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0 9250: && GET_RTX_CLASS (GET_CODE (tem)) == '<'))) 9251: { 9252: op0 = XEXP (XEXP (op0, 0), 0); 9253: continue; 9254: } 9255: } 9256: 9257: /* If we are doing an equality comparison of an AND of a bit equal 9258: to the sign bit, replace this with a LT or GE comparison of 9259: the underlying value. */ 9260: if (equality_comparison_p 9261: && const_op == 0 9262: && GET_CODE (XEXP (op0, 1)) == CONST_INT 1.1.1.4 root 9263: && mode_width <= HOST_BITS_PER_WIDE_INT 1.1 root 9264: && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) 1.1.1.4 root 9265: == (HOST_WIDE_INT) 1 << (mode_width - 1))) 1.1 root 9266: { 9267: op0 = XEXP (op0, 0); 9268: code = (code == EQ ? GE : LT); 9269: continue; 9270: } 9271: 9272: /* If this AND operation is really a ZERO_EXTEND from a narrower 9273: mode, the constant fits within that mode, and this is either an 9274: equality or unsigned comparison, try to do this comparison in 9275: the narrower mode. */ 9276: if ((equality_comparison_p || unsigned_comparison_p) 9277: && GET_CODE (XEXP (op0, 1)) == CONST_INT 9278: && (i = exact_log2 ((INTVAL (XEXP (op0, 1)) 9279: & GET_MODE_MASK (mode)) 9280: + 1)) >= 0 9281: && const_op >> i == 0 9282: && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode) 9283: { 9284: op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0)); 9285: continue; 9286: } 9287: break; 9288: 9289: case ASHIFT: 1.1.1.7 ! root 9290: /* If we have (compare (ashift FOO N) (const_int C)) and 1.1 root 9291: the high order N bits of FOO (N+1 if an inequality comparison) 1.1.1.5 root 9292: are known to be zero, we can do this by comparing FOO with C 1.1 root 9293: shifted right N bits so long as the low-order N bits of C are 9294: zero. */ 9295: if (GET_CODE (XEXP (op0, 1)) == CONST_INT 9296: && INTVAL (XEXP (op0, 1)) >= 0 9297: && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p) 1.1.1.4 root 9298: < HOST_BITS_PER_WIDE_INT) 9299: && ((const_op 1.1.1.6 root 9300: & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0) 1.1.1.4 root 9301: && mode_width <= HOST_BITS_PER_WIDE_INT 1.1.1.5 root 9302: && (nonzero_bits (XEXP (op0, 0), mode) 1.1 root 9303: & ~ (mask >> (INTVAL (XEXP (op0, 1)) 9304: + ! equality_comparison_p))) == 0) 9305: { 9306: const_op >>= INTVAL (XEXP (op0, 1)); 1.1.1.4 root 9307: op1 = GEN_INT (const_op); 1.1 root 9308: op0 = XEXP (op0, 0); 9309: continue; 9310: } 9311: 1.1.1.2 root 9312: /* If we are doing a sign bit comparison, it means we are testing 1.1 root 9313: a particular bit. Convert it to the appropriate AND. */ 1.1.1.2 root 9314: if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT 1.1.1.4 root 9315: && mode_width <= HOST_BITS_PER_WIDE_INT) 1.1 root 9316: { 1.1.1.4 root 9317: op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 9318: ((HOST_WIDE_INT) 1 9319: << (mode_width - 1 9320: - INTVAL (XEXP (op0, 1))))); 1.1 root 9321: code = (code == LT ? NE : EQ); 9322: continue; 9323: } 1.1.1.2 root 9324: 9325: /* If this an equality comparison with zero and we are shifting 9326: the low bit to the sign bit, we can convert this to an AND of the 9327: low-order bit. */ 9328: if (const_op == 0 && equality_comparison_p 9329: && GET_CODE (XEXP (op0, 1)) == CONST_INT 9330: && INTVAL (XEXP (op0, 1)) == mode_width - 1) 9331: { 1.1.1.4 root 9332: op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 9333: (HOST_WIDE_INT) 1); 1.1.1.2 root 9334: continue; 9335: } 1.1 root 9336: break; 9337: 9338: case ASHIFTRT: 1.1.1.4 root 9339: /* If this is an equality comparison with zero, we can do this 9340: as a logical shift, which might be much simpler. */ 9341: if (equality_comparison_p && const_op == 0 9342: && GET_CODE (XEXP (op0, 1)) == CONST_INT) 9343: { 9344: op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, 9345: XEXP (op0, 0), 9346: INTVAL (XEXP (op0, 1))); 9347: continue; 9348: } 9349: 1.1 root 9350: /* If OP0 is a sign extension and CODE is not an unsigned comparison, 9351: do the comparison in a narrower mode. */ 9352: if (! unsigned_comparison_p 9353: && GET_CODE (XEXP (op0, 1)) == CONST_INT 9354: && GET_CODE (XEXP (op0, 0)) == ASHIFT 9355: && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1) 9356: && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 1.1.1.4 root 9357: MODE_INT, 1)) != BLKmode 9358: && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode) 9359: || ((unsigned HOST_WIDE_INT) - const_op 9360: <= GET_MODE_MASK (tmode)))) 1.1 root 9361: { 9362: op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0)); 9363: continue; 9364: } 9365: 9366: /* ... fall through ... */ 9367: case LSHIFTRT: 9368: /* If we have (compare (xshiftrt FOO N) (const_int C)) and 1.1.1.5 root 9369: the low order N bits of FOO are known to be zero, we can do this 1.1 root 9370: by comparing FOO with C shifted left N bits so long as no 9371: overflow occurs. */ 9372: if (GET_CODE (XEXP (op0, 1)) == CONST_INT 9373: && INTVAL (XEXP (op0, 1)) >= 0 1.1.1.4 root 9374: && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT 9375: && mode_width <= HOST_BITS_PER_WIDE_INT 1.1.1.5 root 9376: && (nonzero_bits (XEXP (op0, 0), mode) 1.1.1.4 root 9377: & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0 1.1 root 9378: && (const_op == 0 9379: || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1)) 9380: < mode_width))) 9381: { 9382: const_op <<= INTVAL (XEXP (op0, 1)); 1.1.1.4 root 9383: op1 = GEN_INT (const_op); 1.1 root 9384: op0 = XEXP (op0, 0); 9385: continue; 9386: } 9387: 9388: /* If we are using this shift to extract just the sign bit, we 9389: can replace this with an LT or GE comparison. */ 9390: if (const_op == 0 9391: && (equality_comparison_p || sign_bit_comparison_p) 9392: && GET_CODE (XEXP (op0, 1)) == CONST_INT 9393: && INTVAL (XEXP (op0, 1)) == mode_width - 1) 9394: { 9395: op0 = XEXP (op0, 0); 9396: code = (code == NE || code == GT ? LT : GE); 9397: continue; 9398: } 9399: break; 9400: } 9401: 9402: break; 9403: } 9404: 9405: /* Now make any compound operations involved in this comparison. Then, 9406: check for an outmost SUBREG on OP0 that isn't doing anything or is 9407: paradoxical. The latter case can only occur when it is known that the 9408: "extra" bits will be zero. Therefore, it is safe to remove the SUBREG. 9409: We can never remove a SUBREG for a non-equality comparison because the 9410: sign bit is in a different place in the underlying object. */ 9411: 9412: op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET); 9413: op1 = make_compound_operation (op1, SET); 9414: 9415: if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0) 9416: && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT 9417: && (code == NE || code == EQ) 9418: && ((GET_MODE_SIZE (GET_MODE (op0)) 9419: > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0)))))) 9420: { 9421: op0 = SUBREG_REG (op0); 9422: op1 = gen_lowpart_for_combine (GET_MODE (op0), op1); 9423: } 9424: 9425: else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0) 9426: && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT 9427: && (code == NE || code == EQ) 1.1.1.4 root 9428: && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) 9429: <= HOST_BITS_PER_WIDE_INT) 1.1.1.5 root 9430: && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0))) 1.1 root 9431: & ~ GET_MODE_MASK (GET_MODE (op0))) == 0 9432: && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), 9433: op1), 1.1.1.5 root 9434: (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0))) 1.1 root 9435: & ~ GET_MODE_MASK (GET_MODE (op0))) == 0)) 9436: op0 = SUBREG_REG (op0), op1 = tem; 9437: 9438: /* We now do the opposite procedure: Some machines don't have compare 9439: insns in all modes. If OP0's mode is an integer mode smaller than a 9440: word and we can't do a compare in that mode, see if there is a larger 1.1.1.4 root 9441: mode for which we can do the compare. There are a number of cases in 9442: which we can use the wider mode. */ 1.1 root 9443: 9444: mode = GET_MODE (op0); 9445: if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT 9446: && GET_MODE_SIZE (mode) < UNITS_PER_WORD 9447: && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing) 9448: for (tmode = GET_MODE_WIDER_MODE (mode); 1.1.1.4 root 9449: (tmode != VOIDmode 9450: && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT); 1.1 root 9451: tmode = GET_MODE_WIDER_MODE (tmode)) 1.1.1.4 root 9452: if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing) 9453: { 1.1.1.5 root 9454: /* If the only nonzero bits in OP0 and OP1 are those in the 1.1.1.4 root 9455: narrower mode and this is an equality or unsigned comparison, 9456: we can use the wider mode. Similarly for sign-extended 1.1.1.7 ! root 9457: values, in which case it is true for all comparisons. */ 1.1.1.4 root 9458: if (((code == EQ || code == NE 9459: || code == GEU || code == GTU || code == LEU || code == LTU) 1.1.1.5 root 9460: && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0 9461: && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0) 1.1.1.7 ! root 9462: || ((num_sign_bit_copies (op0, tmode) ! 9463: > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode)) 1.1.1.4 root 9464: && (num_sign_bit_copies (op1, tmode) 9465: > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode)))) 9466: { 9467: op0 = gen_lowpart_for_combine (tmode, op0); 9468: op1 = gen_lowpart_for_combine (tmode, op1); 9469: break; 1.1 root 9470: } 9471: 1.1.1.4 root 9472: /* If this is a test for negative, we can make an explicit 9473: test of the sign bit. */ 9474: 9475: if (op1 == const0_rtx && (code == LT || code == GE) 9476: && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) 9477: { 9478: op0 = gen_binary (AND, tmode, 9479: gen_lowpart_for_combine (tmode, op0), 9480: GEN_INT ((HOST_WIDE_INT) 1 9481: << (GET_MODE_BITSIZE (mode) - 1))); 9482: code = (code == LT) ? NE : EQ; 9483: break; 9484: } 1.1 root 9485: } 9486: 1.1.1.7 ! root 9487: #ifdef CANONICALIZE_COMPARISON ! 9488: /* If this machine only supports a subset of valid comparisons, see if we ! 9489: can convert an unsupported one into a supported one. */ ! 9490: CANONICALIZE_COMPARISON (code, op0, op1); ! 9491: #endif ! 9492: 1.1 root 9493: *pop0 = op0; 9494: *pop1 = op1; 9495: 9496: return code; 9497: } 9498: 9499: /* Return 1 if we know that X, a comparison operation, is not operating 9500: on a floating-point value or is EQ or NE, meaning that we can safely 9501: reverse it. */ 9502: 9503: static int 9504: reversible_comparison_p (x) 9505: rtx x; 9506: { 9507: if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT 1.1.1.7 ! root 9508: || flag_fast_math 1.1 root 9509: || GET_CODE (x) == NE || GET_CODE (x) == EQ) 9510: return 1; 9511: 9512: switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0)))) 9513: { 9514: case MODE_INT: 1.1.1.6 root 9515: case MODE_PARTIAL_INT: 9516: case MODE_COMPLEX_INT: 1.1 root 9517: return 1; 9518: 9519: case MODE_CC: 1.1.1.7 ! root 9520: /* If the mode of the condition codes tells us that this is safe, ! 9521: we need look no further. */ ! 9522: if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0)))) ! 9523: return 1; ! 9524: ! 9525: /* Otherwise try and find where the condition codes were last set and ! 9526: use that. */ 1.1 root 9527: x = get_last_value (XEXP (x, 0)); 9528: return (x && GET_CODE (x) == COMPARE 1.1.1.6 root 9529: && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))); 1.1 root 9530: } 9531: 9532: return 0; 9533: } 9534: 9535: /* Utility function for following routine. Called when X is part of a value 9536: being stored into reg_last_set_value. Sets reg_last_set_table_tick 9537: for each register mentioned. Similar to mention_regs in cse.c */ 9538: 9539: static void 9540: update_table_tick (x) 9541: rtx x; 9542: { 9543: register enum rtx_code code = GET_CODE (x); 9544: register char *fmt = GET_RTX_FORMAT (code); 9545: register int i; 9546: 9547: if (code == REG) 9548: { 9549: int regno = REGNO (x); 9550: int endregno = regno + (regno < FIRST_PSEUDO_REGISTER 9551: ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); 9552: 9553: for (i = regno; i < endregno; i++) 9554: reg_last_set_table_tick[i] = label_tick; 9555: 9556: return; 9557: } 9558: 9559: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 9560: /* Note that we can't have an "E" in values stored; see 9561: get_last_value_validate. */ 9562: if (fmt[i] == 'e') 9563: update_table_tick (XEXP (x, i)); 9564: } 9565: 9566: /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we 9567: are saying that the register is clobbered and we no longer know its 1.1.1.5 root 9568: value. If INSN is zero, don't update reg_last_set; this is only permitted 9569: with VALUE also zero and is used to invalidate the register. */ 1.1 root 9570: 9571: static void 9572: record_value_for_reg (reg, insn, value) 9573: rtx reg; 9574: rtx insn; 9575: rtx value; 9576: { 9577: int regno = REGNO (reg); 9578: int endregno = regno + (regno < FIRST_PSEUDO_REGISTER 9579: ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1); 9580: int i; 9581: 9582: /* If VALUE contains REG and we have a previous value for REG, substitute 9583: the previous value. */ 9584: if (value && insn && reg_overlap_mentioned_p (reg, value)) 9585: { 9586: rtx tem; 9587: 9588: /* Set things up so get_last_value is allowed to see anything set up to 9589: our insn. */ 9590: subst_low_cuid = INSN_CUID (insn); 9591: tem = get_last_value (reg); 9592: 9593: if (tem) 9594: value = replace_rtx (copy_rtx (value), reg, tem); 9595: } 9596: 9597: /* For each register modified, show we don't know its value, that 1.1.1.6 root 9598: we don't know about its bitwise content, that its value has been 9599: updated, and that we don't know the location of the death of the 9600: register. */ 1.1 root 9601: for (i = regno; i < endregno; i ++) 9602: { 9603: if (insn) 9604: reg_last_set[i] = insn; 9605: reg_last_set_value[i] = 0; 1.1.1.6 root 9606: reg_last_set_mode[i] = 0; 9607: reg_last_set_nonzero_bits[i] = 0; 9608: reg_last_set_sign_bit_copies[i] = 0; 1.1 root 9609: reg_last_death[i] = 0; 9610: } 9611: 9612: /* Mark registers that are being referenced in this value. */ 9613: if (value) 9614: update_table_tick (value); 9615: 9616: /* Now update the status of each register being set. 9617: If someone is using this register in this block, set this register 9618: to invalid since we will get confused between the two lives in this 9619: basic block. This makes using this register always invalid. In cse, we 9620: scan the table to invalidate all entries using this register, but this 9621: is too much work for us. */ 9622: 9623: for (i = regno; i < endregno; i++) 9624: { 9625: reg_last_set_label[i] = label_tick; 9626: if (value && reg_last_set_table_tick[i] == label_tick) 9627: reg_last_set_invalid[i] = 1; 9628: else 9629: reg_last_set_invalid[i] = 0; 9630: } 9631: 9632: /* The value being assigned might refer to X (like in "x++;"). In that 9633: case, we must replace it with (clobber (const_int 0)) to prevent 9634: infinite loops. */ 9635: if (value && ! get_last_value_validate (&value, 9636: reg_last_set_label[regno], 0)) 9637: { 9638: value = copy_rtx (value); 9639: if (! get_last_value_validate (&value, reg_last_set_label[regno], 1)) 9640: value = 0; 9641: } 9642: 1.1.1.5 root 9643: /* For the main register being modified, update the value, the mode, the 9644: nonzero bits, and the number of sign bit copies. */ 9645: 1.1 root 9646: reg_last_set_value[regno] = value; 9647: 1.1.1.5 root 9648: if (value) 9649: { 9650: subst_low_cuid = INSN_CUID (insn); 9651: reg_last_set_mode[regno] = GET_MODE (reg); 9652: reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg)); 9653: reg_last_set_sign_bit_copies[regno] 9654: = num_sign_bit_copies (value, GET_MODE (reg)); 9655: } 1.1 root 9656: } 9657: 9658: /* Used for communication between the following two routines. */ 9659: static rtx record_dead_insn; 9660: 9661: /* Called via note_stores from record_dead_and_set_regs to handle one 9662: SET or CLOBBER in an insn. */ 9663: 9664: static void 9665: record_dead_and_set_regs_1 (dest, setter) 9666: rtx dest, setter; 9667: { 1.1.1.7 ! root 9668: if (GET_CODE (dest) == SUBREG) ! 9669: dest = SUBREG_REG (dest); ! 9670: 1.1 root 9671: if (GET_CODE (dest) == REG) 9672: { 9673: /* If we are setting the whole register, we know its value. Otherwise 9674: show that we don't know the value. We can handle SUBREG in 9675: some cases. */ 9676: if (GET_CODE (setter) == SET && dest == SET_DEST (setter)) 9677: record_value_for_reg (dest, record_dead_insn, SET_SRC (setter)); 9678: else if (GET_CODE (setter) == SET 9679: && GET_CODE (SET_DEST (setter)) == SUBREG 9680: && SUBREG_REG (SET_DEST (setter)) == dest 1.1.1.7 ! root 9681: && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD 1.1 root 9682: && subreg_lowpart_p (SET_DEST (setter))) 1.1.1.4 root 9683: record_value_for_reg (dest, record_dead_insn, 9684: gen_lowpart_for_combine (GET_MODE (dest), 9685: SET_SRC (setter))); 1.1 root 9686: else 1.1.1.4 root 9687: record_value_for_reg (dest, record_dead_insn, NULL_RTX); 1.1 root 9688: } 9689: else if (GET_CODE (dest) == MEM 9690: /* Ignore pushes, they clobber nothing. */ 9691: && ! push_operand (dest, GET_MODE (dest))) 9692: mem_last_set = INSN_CUID (record_dead_insn); 9693: } 9694: 9695: /* Update the records of when each REG was most recently set or killed 9696: for the things done by INSN. This is the last thing done in processing 9697: INSN in the combiner loop. 9698: 1.1.1.6 root 9699: We update reg_last_set, reg_last_set_value, reg_last_set_mode, 9700: reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death, 9701: and also the similar information mem_last_set (which insn most recently 9702: modified memory) and last_call_cuid (which insn was the most recent 9703: subroutine call). */ 1.1 root 9704: 9705: static void 9706: record_dead_and_set_regs (insn) 9707: rtx insn; 9708: { 9709: register rtx link; 1.1.1.5 root 9710: int i; 9711: 1.1 root 9712: for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 9713: { 1.1.1.5 root 9714: if (REG_NOTE_KIND (link) == REG_DEAD 9715: && GET_CODE (XEXP (link, 0)) == REG) 9716: { 9717: int regno = REGNO (XEXP (link, 0)); 9718: int endregno 9719: = regno + (regno < FIRST_PSEUDO_REGISTER 9720: ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0))) 9721: : 1); 9722: 9723: for (i = regno; i < endregno; i++) 9724: reg_last_death[i] = insn; 9725: } 1.1 root 9726: else if (REG_NOTE_KIND (link) == REG_INC) 1.1.1.4 root 9727: record_value_for_reg (XEXP (link, 0), insn, NULL_RTX); 1.1 root 9728: } 9729: 9730: if (GET_CODE (insn) == CALL_INSN) 1.1.1.5 root 9731: { 9732: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 9733: if (call_used_regs[i]) 9734: { 9735: reg_last_set_value[i] = 0; 1.1.1.6 root 9736: reg_last_set_mode[i] = 0; 9737: reg_last_set_nonzero_bits[i] = 0; 9738: reg_last_set_sign_bit_copies[i] = 0; 1.1.1.5 root 9739: reg_last_death[i] = 0; 9740: } 9741: 9742: last_call_cuid = mem_last_set = INSN_CUID (insn); 9743: } 1.1 root 9744: 9745: record_dead_insn = insn; 9746: note_stores (PATTERN (insn), record_dead_and_set_regs_1); 9747: } 9748: 9749: /* Utility routine for the following function. Verify that all the registers 9750: mentioned in *LOC are valid when *LOC was part of a value set when 9751: label_tick == TICK. Return 0 if some are not. 9752: 9753: If REPLACE is non-zero, replace the invalid reference with 9754: (clobber (const_int 0)) and return 1. This replacement is useful because 9755: we often can get useful information about the form of a value (e.g., if 9756: it was produced by a shift that always produces -1 or 0) even though 9757: we don't know exactly what registers it was produced from. */ 9758: 9759: static int 9760: get_last_value_validate (loc, tick, replace) 9761: rtx *loc; 9762: int tick; 9763: int replace; 9764: { 9765: rtx x = *loc; 9766: char *fmt = GET_RTX_FORMAT (GET_CODE (x)); 9767: int len = GET_RTX_LENGTH (GET_CODE (x)); 9768: int i; 9769: 9770: if (GET_CODE (x) == REG) 9771: { 9772: int regno = REGNO (x); 9773: int endregno = regno + (regno < FIRST_PSEUDO_REGISTER 9774: ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); 9775: int j; 9776: 9777: for (j = regno; j < endregno; j++) 9778: if (reg_last_set_invalid[j] 9779: /* If this is a pseudo-register that was only set once, it is 9780: always valid. */ 9781: || (! (regno >= FIRST_PSEUDO_REGISTER && reg_n_sets[regno] == 1) 9782: && reg_last_set_label[j] > tick)) 9783: { 9784: if (replace) 9785: *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx); 9786: return replace; 9787: } 9788: 9789: return 1; 9790: } 9791: 9792: for (i = 0; i < len; i++) 9793: if ((fmt[i] == 'e' 9794: && get_last_value_validate (&XEXP (x, i), tick, replace) == 0) 9795: /* Don't bother with these. They shouldn't occur anyway. */ 9796: || fmt[i] == 'E') 9797: return 0; 9798: 9799: /* If we haven't found a reason for it to be invalid, it is valid. */ 9800: return 1; 9801: } 9802: 9803: /* Get the last value assigned to X, if known. Some registers 9804: in the value may be replaced with (clobber (const_int 0)) if their value 9805: is known longer known reliably. */ 9806: 9807: static rtx 9808: get_last_value (x) 9809: rtx x; 9810: { 9811: int regno; 9812: rtx value; 9813: 9814: /* If this is a non-paradoxical SUBREG, get the value of its operand and 9815: then convert it to the desired mode. If this is a paradoxical SUBREG, 9816: we cannot predict what values the "extra" bits might have. */ 9817: if (GET_CODE (x) == SUBREG 9818: && subreg_lowpart_p (x) 9819: && (GET_MODE_SIZE (GET_MODE (x)) 9820: <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 9821: && (value = get_last_value (SUBREG_REG (x))) != 0) 9822: return gen_lowpart_for_combine (GET_MODE (x), value); 9823: 9824: if (GET_CODE (x) != REG) 9825: return 0; 9826: 9827: regno = REGNO (x); 9828: value = reg_last_set_value[regno]; 9829: 1.1.1.4 root 9830: /* If we don't have a value or if it isn't for this basic block, return 0. */ 1.1 root 9831: 9832: if (value == 0 9833: || (reg_n_sets[regno] != 1 1.1.1.5 root 9834: && reg_last_set_label[regno] != label_tick)) 1.1 root 9835: return 0; 9836: 1.1.1.4 root 9837: /* If the value was set in a later insn that the ones we are processing, 9838: we can't use it even if the register was only set once, but make a quick 9839: check to see if the previous insn set it to something. This is commonly 9840: the case when the same pseudo is used by repeated insns. */ 9841: 9842: if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid) 9843: { 9844: rtx insn, set; 9845: 1.1.1.7 ! root 9846: for (insn = prev_nonnote_insn (subst_insn); ! 9847: insn && INSN_CUID (insn) >= subst_low_cuid; ! 9848: insn = prev_nonnote_insn (insn)) ! 9849: ; 1.1.1.4 root 9850: 9851: if (insn 9852: && (set = single_set (insn)) != 0 9853: && rtx_equal_p (SET_DEST (set), x)) 9854: { 9855: value = SET_SRC (set); 9856: 9857: /* Make sure that VALUE doesn't reference X. Replace any 9858: expliit references with a CLOBBER. If there are any remaining 9859: references (rare), don't use the value. */ 9860: 9861: if (reg_mentioned_p (x, value)) 9862: value = replace_rtx (copy_rtx (value), x, 9863: gen_rtx (CLOBBER, GET_MODE (x), const0_rtx)); 9864: 9865: if (reg_overlap_mentioned_p (x, value)) 9866: return 0; 9867: } 9868: else 9869: return 0; 9870: } 9871: 9872: /* If the value has all its registers valid, return it. */ 1.1 root 9873: if (get_last_value_validate (&value, reg_last_set_label[regno], 0)) 9874: return value; 9875: 9876: /* Otherwise, make a copy and replace any invalid register with 9877: (clobber (const_int 0)). If that fails for some reason, return 0. */ 9878: 9879: value = copy_rtx (value); 9880: if (get_last_value_validate (&value, reg_last_set_label[regno], 1)) 9881: return value; 9882: 9883: return 0; 9884: } 9885: 9886: /* Return nonzero if expression X refers to a REG or to memory 9887: that is set in an instruction more recent than FROM_CUID. */ 9888: 9889: static int 9890: use_crosses_set_p (x, from_cuid) 9891: register rtx x; 9892: int from_cuid; 9893: { 9894: register char *fmt; 9895: register int i; 9896: register enum rtx_code code = GET_CODE (x); 9897: 9898: if (code == REG) 9899: { 9900: register int regno = REGNO (x); 1.1.1.6 root 9901: int endreg = regno + (regno < FIRST_PSEUDO_REGISTER 9902: ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); 9903: 1.1 root 9904: #ifdef PUSH_ROUNDING 9905: /* Don't allow uses of the stack pointer to be moved, 9906: because we don't know whether the move crosses a push insn. */ 9907: if (regno == STACK_POINTER_REGNUM) 9908: return 1; 9909: #endif 1.1.1.6 root 9910: for (;regno < endreg; regno++) 9911: if (reg_last_set[regno] 9912: && INSN_CUID (reg_last_set[regno]) > from_cuid) 9913: return 1; 9914: return 0; 1.1 root 9915: } 9916: 9917: if (code == MEM && mem_last_set > from_cuid) 9918: return 1; 9919: 9920: fmt = GET_RTX_FORMAT (code); 9921: 9922: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 9923: { 9924: if (fmt[i] == 'E') 9925: { 9926: register int j; 9927: for (j = XVECLEN (x, i) - 1; j >= 0; j--) 9928: if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid)) 9929: return 1; 9930: } 9931: else if (fmt[i] == 'e' 9932: && use_crosses_set_p (XEXP (x, i), from_cuid)) 9933: return 1; 9934: } 9935: return 0; 9936: } 9937: 9938: /* Define three variables used for communication between the following 9939: routines. */ 9940: 9941: static int reg_dead_regno, reg_dead_endregno; 9942: static int reg_dead_flag; 9943: 9944: /* Function called via note_stores from reg_dead_at_p. 9945: 9946: If DEST is within [reg_dead_rengno, reg_dead_endregno), set 9947: reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */ 9948: 9949: static void 9950: reg_dead_at_p_1 (dest, x) 9951: rtx dest; 9952: rtx x; 9953: { 9954: int regno, endregno; 9955: 9956: if (GET_CODE (dest) != REG) 9957: return; 9958: 9959: regno = REGNO (dest); 9960: endregno = regno + (regno < FIRST_PSEUDO_REGISTER 9961: ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1); 9962: 9963: if (reg_dead_endregno > regno && reg_dead_regno < endregno) 9964: reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1; 9965: } 9966: 9967: /* Return non-zero if REG is known to be dead at INSN. 9968: 9969: We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER 9970: referencing REG, it is dead. If we hit a SET referencing REG, it is 9971: live. Otherwise, see if it is live or dead at the start of the basic 1.1.1.7 ! root 9972: block we are in. Hard regs marked as being live in NEWPAT_USED_REGS ! 9973: must be assumed to be always live. */ 1.1 root 9974: 9975: static int 9976: reg_dead_at_p (reg, insn) 9977: rtx reg; 9978: rtx insn; 9979: { 9980: int block, i; 9981: 9982: /* Set variables for reg_dead_at_p_1. */ 9983: reg_dead_regno = REGNO (reg); 9984: reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER 9985: ? HARD_REGNO_NREGS (reg_dead_regno, 9986: GET_MODE (reg)) 9987: : 1); 9988: 9989: reg_dead_flag = 0; 9990: 1.1.1.7 ! root 9991: /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */ ! 9992: if (reg_dead_regno < FIRST_PSEUDO_REGISTER) ! 9993: { ! 9994: for (i = reg_dead_regno; i < reg_dead_endregno; i++) ! 9995: if (TEST_HARD_REG_BIT (newpat_used_regs, i)) ! 9996: return 0; ! 9997: } ! 9998: 1.1 root 9999: /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or 10000: beginning of function. */ 10001: for (; insn && GET_CODE (insn) != CODE_LABEL; 10002: insn = prev_nonnote_insn (insn)) 10003: { 10004: note_stores (PATTERN (insn), reg_dead_at_p_1); 10005: if (reg_dead_flag) 10006: return reg_dead_flag == 1 ? 1 : 0; 10007: 10008: if (find_regno_note (insn, REG_DEAD, reg_dead_regno)) 10009: return 1; 10010: } 10011: 10012: /* Get the basic block number that we were in. */ 10013: if (insn == 0) 10014: block = 0; 10015: else 10016: { 10017: for (block = 0; block < n_basic_blocks; block++) 10018: if (insn == basic_block_head[block]) 10019: break; 10020: 10021: if (block == n_basic_blocks) 10022: return 0; 10023: } 10024: 10025: for (i = reg_dead_regno; i < reg_dead_endregno; i++) 1.1.1.4 root 10026: if (basic_block_live_at_start[block][i / REGSET_ELT_BITS] 10027: & ((REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS))) 1.1 root 10028: return 0; 10029: 10030: return 1; 10031: } 10032: 1.1.1.7 ! root 10033: /* Note hard registers in X that are used. This code is similar to ! 10034: that in flow.c, but much simpler since we don't care about pseudos. */ ! 10035: ! 10036: static void ! 10037: mark_used_regs_combine (x) ! 10038: rtx x; ! 10039: { ! 10040: register RTX_CODE code = GET_CODE (x); ! 10041: register int regno; ! 10042: int i; ! 10043: ! 10044: switch (code) ! 10045: { ! 10046: case LABEL_REF: ! 10047: case SYMBOL_REF: ! 10048: case CONST_INT: ! 10049: case CONST: ! 10050: case CONST_DOUBLE: ! 10051: case PC: ! 10052: case ADDR_VEC: ! 10053: case ADDR_DIFF_VEC: ! 10054: case ASM_INPUT: ! 10055: #ifdef HAVE_cc0 ! 10056: /* CC0 must die in the insn after it is set, so we don't need to take ! 10057: special note of it here. */ ! 10058: case CC0: ! 10059: #endif ! 10060: return; ! 10061: ! 10062: case CLOBBER: ! 10063: /* If we are clobbering a MEM, mark any hard registers inside the ! 10064: address as used. */ ! 10065: if (GET_CODE (XEXP (x, 0)) == MEM) ! 10066: mark_used_regs_combine (XEXP (XEXP (x, 0), 0)); ! 10067: return; ! 10068: ! 10069: case REG: ! 10070: regno = REGNO (x); ! 10071: /* A hard reg in a wide mode may really be multiple registers. ! 10072: If so, mark all of them just like the first. */ ! 10073: if (regno < FIRST_PSEUDO_REGISTER) ! 10074: { ! 10075: /* None of this applies to the stack, frame or arg pointers */ ! 10076: if (regno == STACK_POINTER_REGNUM ! 10077: #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM ! 10078: || regno == HARD_FRAME_POINTER_REGNUM ! 10079: #endif ! 10080: #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM ! 10081: || (regno == ARG_POINTER_REGNUM && fixed_regs[regno]) ! 10082: #endif ! 10083: || regno == FRAME_POINTER_REGNUM) ! 10084: return; ! 10085: ! 10086: i = HARD_REGNO_NREGS (regno, GET_MODE (x)); ! 10087: while (i-- > 0) ! 10088: SET_HARD_REG_BIT (newpat_used_regs, regno + i); ! 10089: } ! 10090: return; ! 10091: ! 10092: case SET: ! 10093: { ! 10094: /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in ! 10095: the address. */ ! 10096: register rtx testreg = SET_DEST (x); ! 10097: ! 10098: while (GET_CODE (testreg) == SUBREG ! 10099: || GET_CODE (testreg) == ZERO_EXTRACT ! 10100: || GET_CODE (testreg) == SIGN_EXTRACT ! 10101: || GET_CODE (testreg) == STRICT_LOW_PART) ! 10102: testreg = XEXP (testreg, 0); ! 10103: ! 10104: if (GET_CODE (testreg) == MEM) ! 10105: mark_used_regs_combine (XEXP (testreg, 0)); ! 10106: ! 10107: mark_used_regs_combine (SET_SRC (x)); ! 10108: return; ! 10109: } ! 10110: } ! 10111: ! 10112: /* Recursively scan the operands of this expression. */ ! 10113: ! 10114: { ! 10115: register char *fmt = GET_RTX_FORMAT (code); ! 10116: ! 10117: for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) ! 10118: { ! 10119: if (fmt[i] == 'e') ! 10120: mark_used_regs_combine (XEXP (x, i)); ! 10121: else if (fmt[i] == 'E') ! 10122: { ! 10123: register int j; ! 10124: ! 10125: for (j = 0; j < XVECLEN (x, i); j++) ! 10126: mark_used_regs_combine (XVECEXP (x, i, j)); ! 10127: } ! 10128: } ! 10129: } ! 10130: } ! 10131: ! 10132: 1.1 root 10133: /* Remove register number REGNO from the dead registers list of INSN. 10134: 10135: Return the note used to record the death, if there was one. */ 10136: 10137: rtx 10138: remove_death (regno, insn) 10139: int regno; 10140: rtx insn; 10141: { 10142: register rtx note = find_regno_note (insn, REG_DEAD, regno); 10143: 10144: if (note) 1.1.1.4 root 10145: { 10146: reg_n_deaths[regno]--; 10147: remove_note (insn, note); 10148: } 1.1 root 10149: 10150: return note; 10151: } 10152: 10153: /* For each register (hardware or pseudo) used within expression X, if its 10154: death is in an instruction with cuid between FROM_CUID (inclusive) and 10155: TO_INSN (exclusive), put a REG_DEAD note for that register in the 10156: list headed by PNOTES. 10157: 10158: This is done when X is being merged by combination into TO_INSN. These 10159: notes will then be distributed as needed. */ 10160: 10161: static void 10162: move_deaths (x, from_cuid, to_insn, pnotes) 10163: rtx x; 10164: int from_cuid; 10165: rtx to_insn; 10166: rtx *pnotes; 10167: { 10168: register char *fmt; 10169: register int len, i; 10170: register enum rtx_code code = GET_CODE (x); 10171: 10172: if (code == REG) 10173: { 10174: register int regno = REGNO (x); 10175: register rtx where_dead = reg_last_death[regno]; 10176: 10177: if (where_dead && INSN_CUID (where_dead) >= from_cuid 10178: && INSN_CUID (where_dead) < INSN_CUID (to_insn)) 10179: { 1.1.1.5 root 10180: rtx note = remove_death (regno, where_dead); 1.1 root 10181: 10182: /* It is possible for the call above to return 0. This can occur 10183: when reg_last_death points to I2 or I1 that we combined with. 1.1.1.5 root 10184: In that case make a new note. 1.1 root 10185: 1.1.1.5 root 10186: We must also check for the case where X is a hard register 10187: and NOTE is a death note for a range of hard registers 10188: including X. In that case, we must put REG_DEAD notes for 10189: the remaining registers in place of NOTE. */ 10190: 10191: if (note != 0 && regno < FIRST_PSEUDO_REGISTER 10192: && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) 10193: != GET_MODE_SIZE (GET_MODE (x)))) 10194: { 10195: int deadregno = REGNO (XEXP (note, 0)); 10196: int deadend 10197: = (deadregno + HARD_REGNO_NREGS (deadregno, 10198: GET_MODE (XEXP (note, 0)))); 10199: int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); 10200: int i; 10201: 10202: for (i = deadregno; i < deadend; i++) 10203: if (i < regno || i >= ourend) 10204: REG_NOTES (where_dead) 10205: = gen_rtx (EXPR_LIST, REG_DEAD, 1.1.1.7 ! root 10206: gen_rtx (REG, reg_raw_mode[i], i), 1.1.1.5 root 10207: REG_NOTES (where_dead)); 10208: } 10209: 10210: if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x)) 1.1 root 10211: { 10212: XEXP (note, 1) = *pnotes; 10213: *pnotes = note; 10214: } 10215: else 10216: *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes); 1.1.1.4 root 10217: 10218: reg_n_deaths[regno]++; 1.1 root 10219: } 10220: 10221: return; 10222: } 10223: 10224: else if (GET_CODE (x) == SET) 10225: { 10226: rtx dest = SET_DEST (x); 10227: 10228: move_deaths (SET_SRC (x), from_cuid, to_insn, pnotes); 10229: 1.1.1.3 root 10230: /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG 10231: that accesses one word of a multi-word item, some 10232: piece of everything register in the expression is used by 10233: this insn, so remove any old death. */ 10234: 10235: if (GET_CODE (dest) == ZERO_EXTRACT 10236: || GET_CODE (dest) == STRICT_LOW_PART 10237: || (GET_CODE (dest) == SUBREG 10238: && (((GET_MODE_SIZE (GET_MODE (dest)) 10239: + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 10240: == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) 10241: + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))) 10242: { 10243: move_deaths (dest, from_cuid, to_insn, pnotes); 10244: return; 10245: } 10246: 10247: /* If this is some other SUBREG, we know it replaces the entire 10248: value, so use that as the destination. */ 10249: if (GET_CODE (dest) == SUBREG) 10250: dest = SUBREG_REG (dest); 10251: 10252: /* If this is a MEM, adjust deaths of anything used in the address. 10253: For a REG (the only other possibility), the entire value is 10254: being replaced so the old value is not used in this insn. */ 1.1 root 10255: 10256: if (GET_CODE (dest) == MEM) 10257: move_deaths (XEXP (dest, 0), from_cuid, to_insn, pnotes); 10258: return; 10259: } 10260: 10261: else if (GET_CODE (x) == CLOBBER) 10262: return; 10263: 10264: len = GET_RTX_LENGTH (code); 10265: fmt = GET_RTX_FORMAT (code); 10266: 10267: for (i = 0; i < len; i++) 10268: { 10269: if (fmt[i] == 'E') 10270: { 10271: register int j; 10272: for (j = XVECLEN (x, i) - 1; j >= 0; j--) 10273: move_deaths (XVECEXP (x, i, j), from_cuid, to_insn, pnotes); 10274: } 10275: else if (fmt[i] == 'e') 10276: move_deaths (XEXP (x, i), from_cuid, to_insn, pnotes); 10277: } 10278: } 10279: 1.1.1.3 root 10280: /* Return 1 if X is the target of a bit-field assignment in BODY, the 10281: pattern of an insn. X must be a REG. */ 1.1 root 10282: 10283: static int 1.1.1.3 root 10284: reg_bitfield_target_p (x, body) 10285: rtx x; 1.1 root 10286: rtx body; 10287: { 10288: int i; 10289: 10290: if (GET_CODE (body) == SET) 1.1.1.3 root 10291: { 10292: rtx dest = SET_DEST (body); 10293: rtx target; 10294: int regno, tregno, endregno, endtregno; 10295: 10296: if (GET_CODE (dest) == ZERO_EXTRACT) 10297: target = XEXP (dest, 0); 10298: else if (GET_CODE (dest) == STRICT_LOW_PART) 10299: target = SUBREG_REG (XEXP (dest, 0)); 10300: else 10301: return 0; 10302: 10303: if (GET_CODE (target) == SUBREG) 10304: target = SUBREG_REG (target); 10305: 10306: if (GET_CODE (target) != REG) 10307: return 0; 10308: 10309: tregno = REGNO (target), regno = REGNO (x); 10310: if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER) 10311: return target == x; 10312: 10313: endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target)); 10314: endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); 10315: 10316: return endregno > tregno && regno < endtregno; 10317: } 1.1 root 10318: 10319: else if (GET_CODE (body) == PARALLEL) 10320: for (i = XVECLEN (body, 0) - 1; i >= 0; i--) 1.1.1.3 root 10321: if (reg_bitfield_target_p (x, XVECEXP (body, 0, i))) 1.1 root 10322: return 1; 10323: 10324: return 0; 10325: } 10326: 10327: /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them 10328: as appropriate. I3 and I2 are the insns resulting from the combination 10329: insns including FROM (I2 may be zero). 10330: 10331: ELIM_I2 and ELIM_I1 are either zero or registers that we know will 10332: not need REG_DEAD notes because they are being substituted for. This 10333: saves searching in the most common cases. 10334: 10335: Each note in the list is either ignored or placed on some insns, depending 10336: on the type of note. */ 10337: 10338: static void 10339: distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1) 10340: rtx notes; 10341: rtx from_insn; 10342: rtx i3, i2; 10343: rtx elim_i2, elim_i1; 10344: { 10345: rtx note, next_note; 10346: rtx tem; 10347: 10348: for (note = notes; note; note = next_note) 10349: { 10350: rtx place = 0, place2 = 0; 10351: 10352: /* If this NOTE references a pseudo register, ensure it references 10353: the latest copy of that register. */ 10354: if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG 10355: && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER) 10356: XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))]; 10357: 10358: next_note = XEXP (note, 1); 10359: switch (REG_NOTE_KIND (note)) 10360: { 10361: case REG_UNUSED: 1.1.1.7 ! root 10362: /* Any clobbers for i3 may still exist, and so we must process 1.1.1.6 root 10363: REG_UNUSED notes from that insn. 10364: 10365: Any clobbers from i2 or i1 can only exist if they were added by 10366: recog_for_combine. In that case, recog_for_combine created the 10367: necessary REG_UNUSED notes. Trying to keep any original 10368: REG_UNUSED notes from these insns can cause incorrect output 10369: if it is for the same register as the original i3 dest. 10370: In that case, we will notice that the register is set in i3, 10371: and then add a REG_UNUSED note for the destination of i3, which 1.1.1.7 ! root 10372: is wrong. However, it is possible to have REG_UNUSED notes from ! 10373: i2 or i1 for register which were both used and clobbered, so ! 10374: we keep notes from i2 or i1 if they will turn into REG_DEAD ! 10375: notes. */ 1.1.1.6 root 10376: 1.1 root 10377: /* If this register is set or clobbered in I3, put the note there 10378: unless there is one already. */ 1.1.1.7 ! root 10379: if (reg_set_p (XEXP (note, 0), PATTERN (i3))) 1.1 root 10380: { 1.1.1.7 ! root 10381: if (from_insn != i3) ! 10382: break; ! 10383: 1.1 root 10384: if (! (GET_CODE (XEXP (note, 0)) == REG 10385: ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0))) 10386: : find_reg_note (i3, REG_UNUSED, XEXP (note, 0)))) 10387: place = i3; 10388: } 10389: /* Otherwise, if this register is used by I3, then this register 10390: now dies here, so we must put a REG_DEAD note here unless there 10391: is one already. */ 10392: else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)) 10393: && ! (GET_CODE (XEXP (note, 0)) == REG 10394: ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0))) 10395: : find_reg_note (i3, REG_DEAD, XEXP (note, 0)))) 10396: { 10397: PUT_REG_NOTE_KIND (note, REG_DEAD); 10398: place = i3; 10399: } 10400: break; 10401: 10402: case REG_EQUAL: 10403: case REG_EQUIV: 10404: case REG_NONNEG: 10405: /* These notes say something about results of an insn. We can 10406: only support them if they used to be on I3 in which case they 1.1.1.4 root 10407: remain on I3. Otherwise they are ignored. 10408: 10409: If the note refers to an expression that is not a constant, we 10410: must also ignore the note since we cannot tell whether the 10411: equivalence is still true. It might be possible to do 10412: slightly better than this (we only have a problem if I2DEST 10413: or I1DEST is present in the expression), but it doesn't 10414: seem worth the trouble. */ 10415: 10416: if (from_insn == i3 10417: && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0)))) 1.1 root 10418: place = i3; 10419: break; 10420: 10421: case REG_INC: 10422: case REG_NO_CONFLICT: 10423: case REG_LABEL: 10424: /* These notes say something about how a register is used. They must 10425: be present on any use of the register in I2 or I3. */ 10426: if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))) 10427: place = i3; 10428: 10429: if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2))) 10430: { 10431: if (place) 10432: place2 = i2; 10433: else 10434: place = i2; 10435: } 10436: break; 10437: 10438: case REG_WAS_0: 10439: /* It is too much trouble to try to see if this note is still 10440: correct in all situations. It is better to simply delete it. */ 10441: break; 10442: 10443: case REG_RETVAL: 10444: /* If the insn previously containing this note still exists, 10445: put it back where it was. Otherwise move it to the previous 10446: insn. Adjust the corresponding REG_LIBCALL note. */ 10447: if (GET_CODE (from_insn) != NOTE) 10448: place = from_insn; 10449: else 10450: { 1.1.1.4 root 10451: tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX); 1.1 root 10452: place = prev_real_insn (from_insn); 10453: if (tem && place) 10454: XEXP (tem, 0) = place; 10455: } 10456: break; 10457: 10458: case REG_LIBCALL: 10459: /* This is handled similarly to REG_RETVAL. */ 10460: if (GET_CODE (from_insn) != NOTE) 10461: place = from_insn; 10462: else 10463: { 1.1.1.4 root 10464: tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX); 1.1 root 10465: place = next_real_insn (from_insn); 10466: if (tem && place) 10467: XEXP (tem, 0) = place; 10468: } 10469: break; 10470: 10471: case REG_DEAD: 10472: /* If the register is used as an input in I3, it dies there. 10473: Similarly for I2, if it is non-zero and adjacent to I3. 10474: 10475: If the register is not used as an input in either I3 or I2 10476: and it is not one of the registers we were supposed to eliminate, 10477: there are two possibilities. We might have a non-adjacent I2 10478: or we might have somehow eliminated an additional register 10479: from a computation. For example, we might have had A & B where 10480: we discover that B will always be zero. In this case we will 10481: eliminate the reference to A. 10482: 10483: In both cases, we must search to see if we can find a previous 10484: use of A and put the death note there. */ 10485: 1.1.1.7 ! root 10486: if (from_insn ! 10487: && GET_CODE (from_insn) == CALL_INSN ! 10488: && find_reg_fusage (from_insn, USE, XEXP (note, 0))) ! 10489: place = from_insn; ! 10490: else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))) 1.1 root 10491: place = i3; 10492: else if (i2 != 0 && next_nonnote_insn (i2) == i3 10493: && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) 10494: place = i2; 10495: 10496: if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1) 10497: break; 10498: 1.1.1.4 root 10499: /* If the register is used in both I2 and I3 and it dies in I3, 10500: we might have added another reference to it. If reg_n_refs 10501: was 2, bump it to 3. This has to be correct since the 10502: register must have been set somewhere. The reason this is 10503: done is because local-alloc.c treats 2 references as a 10504: special case. */ 10505: 10506: if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG 10507: && reg_n_refs[REGNO (XEXP (note, 0))]== 2 10508: && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) 10509: reg_n_refs[REGNO (XEXP (note, 0))] = 3; 10510: 1.1 root 10511: if (place == 0) 10512: for (tem = prev_nonnote_insn (i3); 10513: tem && (GET_CODE (tem) == INSN 10514: || GET_CODE (tem) == CALL_INSN); 10515: tem = prev_nonnote_insn (tem)) 10516: { 10517: /* If the register is being set at TEM, see if that is all 10518: TEM is doing. If so, delete TEM. Otherwise, make this 10519: into a REG_UNUSED note instead. */ 10520: if (reg_set_p (XEXP (note, 0), PATTERN (tem))) 10521: { 10522: rtx set = single_set (tem); 10523: 1.1.1.2 root 10524: /* Verify that it was the set, and not a clobber that 10525: modified the register. */ 10526: 10527: if (set != 0 && ! side_effects_p (SET_SRC (set)) 10528: && rtx_equal_p (XEXP (note, 0), SET_DEST (set))) 1.1 root 10529: { 10530: /* Move the notes and links of TEM elsewhere. 10531: This might delete other dead insns recursively. 10532: First set the pattern to something that won't use 10533: any register. */ 10534: 10535: PATTERN (tem) = pc_rtx; 10536: 1.1.1.4 root 10537: distribute_notes (REG_NOTES (tem), tem, tem, 10538: NULL_RTX, NULL_RTX, NULL_RTX); 1.1 root 10539: distribute_links (LOG_LINKS (tem)); 10540: 10541: PUT_CODE (tem, NOTE); 10542: NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED; 10543: NOTE_SOURCE_FILE (tem) = 0; 10544: } 10545: else 10546: { 10547: PUT_REG_NOTE_KIND (note, REG_UNUSED); 10548: 10549: /* If there isn't already a REG_UNUSED note, put one 10550: here. */ 10551: if (! find_regno_note (tem, REG_UNUSED, 10552: REGNO (XEXP (note, 0)))) 10553: place = tem; 10554: break; 10555: } 10556: } 1.1.1.7 ! root 10557: else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem)) ! 10558: || (GET_CODE (tem) == CALL_INSN ! 10559: && find_reg_fusage (tem, USE, XEXP (note, 0)))) 1.1 root 10560: { 10561: place = tem; 10562: break; 10563: } 10564: } 10565: 10566: /* If the register is set or already dead at PLACE, we needn't do 10567: anything with this note if it is still a REG_DEAD note. 10568: 10569: Note that we cannot use just `dead_or_set_p' here since we can 10570: convert an assignment to a register into a bit-field assignment. 10571: Therefore, we must also omit the note if the register is the 10572: target of a bitfield assignment. */ 10573: 10574: if (place && REG_NOTE_KIND (note) == REG_DEAD) 10575: { 10576: int regno = REGNO (XEXP (note, 0)); 10577: 10578: if (dead_or_set_p (place, XEXP (note, 0)) 10579: || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place))) 10580: { 10581: /* Unless the register previously died in PLACE, clear 10582: reg_last_death. [I no longer understand why this is 10583: being done.] */ 10584: if (reg_last_death[regno] != place) 10585: reg_last_death[regno] = 0; 10586: place = 0; 10587: } 10588: else 10589: reg_last_death[regno] = place; 10590: 10591: /* If this is a death note for a hard reg that is occupying 10592: multiple registers, ensure that we are still using all 10593: parts of the object. If we find a piece of the object 10594: that is unused, we must add a USE for that piece before 10595: PLACE and put the appropriate REG_DEAD note on it. 10596: 10597: An alternative would be to put a REG_UNUSED for the pieces 10598: on the insn that set the register, but that can't be done if 10599: it is not in the same block. It is simpler, though less 10600: efficient, to add the USE insns. */ 10601: 10602: if (place && regno < FIRST_PSEUDO_REGISTER 10603: && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1) 10604: { 10605: int endregno 10606: = regno + HARD_REGNO_NREGS (regno, 10607: GET_MODE (XEXP (note, 0))); 10608: int all_used = 1; 10609: int i; 10610: 10611: for (i = regno; i < endregno; i++) 1.1.1.7 ! root 10612: if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0) ! 10613: && ! find_regno_fusage (place, USE, i)) 1.1 root 10614: { 1.1.1.7 ! root 10615: rtx piece = gen_rtx (REG, reg_raw_mode[i], i); 1.1.1.3 root 10616: rtx p; 10617: 10618: /* See if we already placed a USE note for this 10619: register in front of PLACE. */ 10620: for (p = place; 10621: GET_CODE (PREV_INSN (p)) == INSN 10622: && GET_CODE (PATTERN (PREV_INSN (p))) == USE; 10623: p = PREV_INSN (p)) 10624: if (rtx_equal_p (piece, 10625: XEXP (PATTERN (PREV_INSN (p)), 0))) 10626: { 10627: p = 0; 10628: break; 10629: } 10630: 10631: if (p) 10632: { 10633: rtx use_insn 10634: = emit_insn_before (gen_rtx (USE, VOIDmode, 10635: piece), 10636: p); 10637: REG_NOTES (use_insn) 10638: = gen_rtx (EXPR_LIST, REG_DEAD, piece, 10639: REG_NOTES (use_insn)); 10640: } 1.1 root 10641: 1.1.1.2 root 10642: all_used = 0; 1.1 root 10643: } 10644: 1.1.1.5 root 10645: /* Check for the case where the register dying partially 10646: overlaps the register set by this insn. */ 10647: if (all_used) 10648: for (i = regno; i < endregno; i++) 10649: if (dead_or_set_regno_p (place, i)) 10650: { 10651: all_used = 0; 10652: break; 10653: } 10654: 1.1 root 10655: if (! all_used) 10656: { 10657: /* Put only REG_DEAD notes for pieces that are 10658: still used and that are not already dead or set. */ 10659: 10660: for (i = regno; i < endregno; i++) 10661: { 1.1.1.7 ! root 10662: rtx piece = gen_rtx (REG, reg_raw_mode[i], i); 1.1 root 10663: 1.1.1.7 ! root 10664: if ((reg_referenced_p (piece, PATTERN (place)) ! 10665: || (GET_CODE (place) == CALL_INSN ! 10666: && find_reg_fusage (place, USE, piece))) 1.1 root 10667: && ! dead_or_set_p (place, piece) 10668: && ! reg_bitfield_target_p (piece, 10669: PATTERN (place))) 10670: REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD, 10671: piece, 10672: REG_NOTES (place)); 10673: } 10674: 10675: place = 0; 10676: } 10677: } 10678: } 10679: break; 10680: 10681: default: 10682: /* Any other notes should not be present at this point in the 10683: compilation. */ 10684: abort (); 10685: } 10686: 10687: if (place) 10688: { 10689: XEXP (note, 1) = REG_NOTES (place); 10690: REG_NOTES (place) = note; 10691: } 1.1.1.4 root 10692: else if ((REG_NOTE_KIND (note) == REG_DEAD 10693: || REG_NOTE_KIND (note) == REG_UNUSED) 10694: && GET_CODE (XEXP (note, 0)) == REG) 10695: reg_n_deaths[REGNO (XEXP (note, 0))]--; 1.1 root 10696: 10697: if (place2) 1.1.1.4 root 10698: { 10699: if ((REG_NOTE_KIND (note) == REG_DEAD 10700: || REG_NOTE_KIND (note) == REG_UNUSED) 10701: && GET_CODE (XEXP (note, 0)) == REG) 10702: reg_n_deaths[REGNO (XEXP (note, 0))]++; 10703: 10704: REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note), 10705: XEXP (note, 0), REG_NOTES (place2)); 10706: } 1.1 root 10707: } 10708: } 10709: 10710: /* Similarly to above, distribute the LOG_LINKS that used to be present on 1.1.1.2 root 10711: I3, I2, and I1 to new locations. This is also called in one case to 10712: add a link pointing at I3 when I3's destination is changed. */ 1.1 root 10713: 10714: static void 10715: distribute_links (links) 10716: rtx links; 10717: { 10718: rtx link, next_link; 10719: 10720: for (link = links; link; link = next_link) 10721: { 10722: rtx place = 0; 10723: rtx insn; 10724: rtx set, reg; 10725: 10726: next_link = XEXP (link, 1); 10727: 10728: /* If the insn that this link points to is a NOTE or isn't a single 10729: set, ignore it. In the latter case, it isn't clear what we 10730: can do other than ignore the link, since we can't tell which 10731: register it was for. Such links wouldn't be used by combine 10732: anyway. 10733: 10734: It is not possible for the destination of the target of the link to 10735: have been changed by combine. The only potential of this is if we 10736: replace I3, I2, and I1 by I3 and I2. But in that case the 10737: destination of I2 also remains unchanged. */ 10738: 10739: if (GET_CODE (XEXP (link, 0)) == NOTE 10740: || (set = single_set (XEXP (link, 0))) == 0) 10741: continue; 10742: 10743: reg = SET_DEST (set); 10744: while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT 10745: || GET_CODE (reg) == SIGN_EXTRACT 10746: || GET_CODE (reg) == STRICT_LOW_PART) 10747: reg = XEXP (reg, 0); 10748: 10749: /* A LOG_LINK is defined as being placed on the first insn that uses 10750: a register and points to the insn that sets the register. Start 10751: searching at the next insn after the target of the link and stop 10752: when we reach a set of the register or the end of the basic block. 10753: 10754: Note that this correctly handles the link that used to point from 1.1.1.2 root 10755: I3 to I2. Also note that not much searching is typically done here 1.1 root 10756: since most links don't point very far away. */ 10757: 10758: for (insn = NEXT_INSN (XEXP (link, 0)); 1.1.1.6 root 10759: (insn && (this_basic_block == n_basic_blocks - 1 10760: || basic_block_head[this_basic_block + 1] != insn)); 1.1 root 10761: insn = NEXT_INSN (insn)) 10762: if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' 10763: && reg_overlap_mentioned_p (reg, PATTERN (insn))) 10764: { 10765: if (reg_referenced_p (reg, PATTERN (insn))) 10766: place = insn; 10767: break; 10768: } 1.1.1.7 ! root 10769: else if (GET_CODE (insn) == CALL_INSN ! 10770: && find_reg_fusage (insn, USE, reg)) ! 10771: { ! 10772: place = insn; ! 10773: break; ! 10774: } 1.1 root 10775: 10776: /* If we found a place to put the link, place it there unless there 10777: is already a link to the same insn as LINK at that point. */ 10778: 10779: if (place) 10780: { 10781: rtx link2; 10782: 10783: for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1)) 10784: if (XEXP (link2, 0) == XEXP (link, 0)) 10785: break; 10786: 10787: if (link2 == 0) 10788: { 10789: XEXP (link, 1) = LOG_LINKS (place); 10790: LOG_LINKS (place) = link; 1.1.1.7 ! root 10791: ! 10792: /* Set added_links_insn to the earliest insn we added a ! 10793: link to. */ ! 10794: if (added_links_insn == 0 ! 10795: || INSN_CUID (added_links_insn) > INSN_CUID (place)) ! 10796: added_links_insn = place; 1.1 root 10797: } 10798: } 10799: } 10800: } 10801: 10802: void 10803: dump_combine_stats (file) 10804: FILE *file; 10805: { 10806: fprintf 10807: (file, 10808: ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n", 10809: combine_attempts, combine_merges, combine_extras, combine_successes); 10810: } 10811: 10812: void 10813: dump_combine_total_stats (file) 10814: FILE *file; 10815: { 10816: fprintf 10817: (file, 10818: "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n", 10819: total_attempts, total_merges, total_extras, total_successes); 10820: }
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