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1.1 ! root 1: ;;- Machine description for GNU compiler ! 2: ;;- MIL-STD-1750A version. ! 3: ;; Copyright (C) 1994 Free Software Foundation, Inc. ! 4: ;; Contributed by O.M.Kellogg, DASA ([email protected]). ! 5: ! 6: ;; This file is part of GNU CC. ! 7: ! 8: ;; GNU CC is free software; you can redistribute it and/or modify ! 9: ;; it under the terms of the GNU General Public License as published by ! 10: ;; the Free Software Foundation; either version 1, or (at your option) ! 11: ;; any later version. ! 12: ! 13: ;; GNU CC is distributed in the hope that it will be useful, ! 14: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ! 15: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! 16: ;; GNU General Public License for more details. ! 17: ! 18: ;; You should have received a copy of the GNU General Public License ! 19: ;; along with GNU CC; see the file COPYING. If not, write to ! 20: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ! 21: ! 22: ! 23: ;;- instruction definitions ! 24: ! 25: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ! 26: ! 27: ;;- When naming insn's (operand 0 of define_insn) be careful about using ! 28: ;;- names from other targets machine descriptions. ! 29: ! 30: ;; MIL-STD-1750 specific remarks: ! 31: ;; ! 32: ;; 1) BITS_PER_UNIT = 16 ! 33: ;; ! 34: ;; 2) GCC to MIL-STD-1750 data type mappings: ! 35: ;; QImode => single integer (16 bits or 1 reg). ! 36: ;; HImode => double integer (32 bits or 2 regs). ! 37: ;; HFmode => single precision float (32 bits or 2 regs). ! 38: ;; TQFmode => extended precision float (48 bits or 3 regs). ! 39: ;; ! 40: ;; 3) Immediate integer operands Constraints: ! 41: ;; 'I' 1 .. 16 ! 42: ;; 'J' -1 ..-16 ! 43: ;; 'K' 0 .. 15 ! 44: ;; 'L' 0 .. 255 ! 45: ;; 'M' -32768 .. 32767 ! 46: ;; 'O' => 0 (for optimizations and GCC quirks) ! 47: ;; ! 48: ;; Further notes: ! 49: ;;- Assembly output ending in ".M" are macros in file M1750.INC ! 50: ! 51: ! 52: ;; stackpush ! 53: (define_insn "" ! 54: [(set (match_operand:QI 0 "push_operand" "=<") ! 55: (match_operand:QI 1 "general_operand" "r"))] ! 56: "" ! 57: "pshm r%1,r%1") ! 58: ! 59: (define_insn "" ! 60: [(set (match_operand:HI 0 "push_operand" "=<") ! 61: (match_operand:HI 1 "general_operand" "r"))] ! 62: "" ! 63: "* ! 64: { ! 65: rtx new_operands[2]; ! 66: new_operands[0] = operands[1]; ! 67: new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+1); ! 68: } ") ! 69: ! 70: (define_insn "" ! 71: [(set (match_operand:HF 0 "push_operand" "=<") ! 72: (match_operand:HF 1 "general_operand" "r"))] ! 73: "" ! 74: "* ! 75: { ! 76: rtx new_operands[2]; ! 77: new_operands[0] = operands[1]; ! 78: new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+1); ! 79: output_asm_insn(\"pshm r%0,r%1\",new_operands); ! 80: return \"\;\"; ! 81: } ") ! 82: ! 83: (define_insn "" ! 84: [(set (match_operand:TQF 0 "push_operand" "=<") ! 85: (match_operand:TQF 1 "general_operand" "r"))] ! 86: "" ! 87: "* ! 88: { ! 89: rtx new_operands[2]; ! 90: new_operands[0] = operands[1]; ! 91: new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+2); ! 92: output_asm_insn(\"pshm r%0,r%1\",new_operands); ! 93: return \"\;\"; ! 94: } ") ! 95: ! 96: ;; stackpop ! 97: (define_insn "" ! 98: [(set (match_operand:QI 0 "general_operand" "=r") ! 99: (match_operand:QI 1 "push_operand" ">"))] ! 100: "" ! 101: "popm r%1,r%1") ! 102: ! 103: (define_insn "" ! 104: [(set (match_operand:HI 0 "general_operand" "=r") ! 105: (match_operand:HI 1 "push_operand" ">"))] ! 106: "" ! 107: "* ! 108: { ! 109: rtx new_operands[2]; ! 110: new_operands[0] = operands[0]; ! 111: new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+1); ! 112: output_asm_insn(\"popm r%0,r%1\",new_operands); ! 113: return \"\;\"; ! 114: } ") ! 115: ! 116: (define_insn "" ! 117: [(set (match_operand:HF 0 "general_operand" "=r") ! 118: (match_operand:HF 1 "push_operand" ">"))] ! 119: "" ! 120: "* ! 121: { ! 122: rtx new_operands[2]; ! 123: new_operands[0] = operands[0]; ! 124: new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+1); ! 125: output_asm_insn(\"popm r%0,r%1\",new_operands); ! 126: return \"\;\"; ! 127: } ") ! 128: ! 129: (define_insn "" ! 130: [(set (match_operand:TQF 0 "general_operand" "=r") ! 131: (match_operand:TQF 1 "push_operand" ">"))] ! 132: "" ! 133: "* ! 134: { ! 135: rtx new_operands[2]; ! 136: new_operands[0] = operands[0]; ! 137: new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+2); ! 138: output_asm_insn(\"popm r%0,r%1\",new_operands); ! 139: return \"\;\"; ! 140: } ") ! 141: ! 142: ;; Test operations. These shouldn't really occur for 1750: ! 143: ;; all important instructions set the cc's (see NOTICE_UPDATE_CC) ! 144: ! 145: (define_insn "tstqi" ! 146: [(set (cc0) ! 147: (match_operand:QI 0 "register_operand" "r"))] ! 148: "" ! 149: "lr r%0,r%0 ; from tstqi") ! 150: ! 151: (define_insn "tsthi" ! 152: [(set (cc0) ! 153: (match_operand:HI 0 "register_operand" "r"))] ! 154: "" ! 155: "dlr r%0,r%0 ; from tsthi") ! 156: ! 157: (define_insn "tsthf" ! 158: [(set (cc0) ! 159: (match_operand:HF 0 "register_operand" "r"))] ! 160: "" ! 161: "dlr r%0,r%0 ; from tsthf") ! 162: ! 163: ;; This one is happy with "roughly zero" :-) (should be improved) ! 164: (define_insn "tsttqf" ! 165: [(set (cc0) ! 166: (match_operand:TQF 0 "register_operand" "r"))] ! 167: "" ! 168: "dlr r%0,r%0 ; from tsttqf") ! 169: ! 170: ! 171: ;; block move. ! 172: ! 173: ; there is a problem with this insn in gcc-2.2.3 ! 174: ; (clobber (match_dup 2)) does not prevent use of this operand later ! 175: ; ! 176: (define_insn "movstrqi" ! 177: [(set (mem:BLK (match_operand:QI 0 "register_operand" "r")) ! 178: (mem:BLK (match_operand:QI 1 "register_operand" "r"))) ! 179: (use (match_operand:QI 2 "register_operand" "r")) ! 180: (use (match_operand:QI 3 "immediate_operand" "")) ! 181: (clobber (match_dup 0)) ! 182: (clobber (match_dup 1)) ! 183: (clobber (match_dup 2))] ! 184: "" ! 185: "* return (char *)movcnt_regno_adjust(operands); ") ! 186: ! 187: ! 188: ;; compare instructions. ! 189: ! 190: (define_insn "cmpqi" ! 191: [(set (cc0) ! 192: (compare (match_operand:QI 0 "register_operand" "r,r,r,r,r") ! 193: (match_operand:QI 1 "general_operand" "I,J,i,r,m")))] ! 194: "" ! 195: "@ ! 196: cisp r%0,%1 ! 197: cisn r%0,%J1 ! 198: cim r%0,%1 ! 199: cr r%0,r%1 ! 200: c r%0,%1 ") ! 201: ! 202: (define_insn "cmphi" ! 203: [(set (cc0) ! 204: (compare (match_operand:HI 0 "general_operand" "r,r") ! 205: (match_operand:HI 1 "general_operand" "r,m")))] ! 206: "" ! 207: "@ ! 208: dcr r%0,r%1 ! 209: dc r%0,%1 ") ! 210: ! 211: (define_insn "cmphf" ! 212: [(set (cc0) ! 213: (compare (match_operand:HF 0 "general_operand" "r,r") ! 214: (match_operand:HF 1 "general_operand" "r,m")))] ! 215: "" ! 216: "@ ! 217: fcr r%0,r%1 ! 218: fc r%0,%1 ") ! 219: ! 220: (define_insn "cmptqf" ! 221: [(set (cc0) ! 222: (compare (match_operand:TQF 0 "general_operand" "r,r") ! 223: (match_operand:TQF 1 "general_operand" "r,m")))] ! 224: "" ! 225: "@ ! 226: efcr r%0,r%1 ! 227: efc r%0,%1 ") ! 228: ! 229: ! 230: ;; truncation instructions ! 231: ;;- 1750: any needed? ! 232: ! 233: (define_insn "trunchiqi2" ! 234: [(set (match_operand:QI 0 "register_operand" "=r") ! 235: (truncate:QI ! 236: (match_operand:HI 1 "register_operand" "r")))] ! 237: "" ! 238: "* ! 239: { ! 240: REGNO(operands[1]) += 1; ! 241: return \"lr r%0,r%1 ;trunchiqi2\"; ! 242: } ") ! 243: ! 244: ;; zero extension instructions ! 245: ! 246: (define_insn "zero_extendqihi2" ! 247: [(set (match_operand:HI 0 "register_operand" "=r,r,r") ! 248: (zero_extend:HI (match_operand:QI 1 "general_operand" "r,m,i")))] ! 249: "" ! 250: "* ! 251: { ! 252: output_asm_insn(\"xorr r%0,r%0 ;zero_extendqihi2\",operands); ! 253: REGNO(operands[0]) += 1; ! 254: switch (which_alternative) ! 255: { ! 256: case 0: ! 257: return \"lr r%0,r%1\"; ! 258: case 1: ! 259: return \"l r%0,%1\"; ! 260: case 2: ! 261: return \"lim r%0,%1\"; ! 262: } ! 263: } ") ! 264: ! 265: ;; sign extension instructions ! 266: ! 267: (define_insn "extendqihi2" ! 268: [(set (match_operand:HI 0 "register_operand" "=r,r,r") ! 269: (sign_extend:HI (match_operand:QI 1 "general_operand" "r,m,i")) )] ! 270: "" ! 271: "@ ! 272: lr r%0,r%1 ;extendqihi2\;dsra r%0,16 ! 273: l r%0,%1 ;extendqihi2\;dsra r%0,16 ! 274: lim r%0,%1 ;extendqihi2\;dsra r%0,16 ") ! 275: ! 276: ! 277: ;; Conversions between float and double. ! 278: ! 279: ; 1750 HF-to-TQF extend: just append 16 bits (least signif.) with all bits zero ! 280: (define_insn "extendhftqf2" ! 281: [(set (match_operand:TQF 0 "register_operand" "=r,r") ! 282: (float_extend:TQF ! 283: (match_operand:HF 1 "general_operand" "r,m")))] ! 284: "" ! 285: "* ! 286: { ! 287: REGNO(operands[0]) += 2; ! 288: output_asm_insn(\"xorr r%0,r%0 ;extendhftqf2\",operands); ! 289: REGNO(operands[0]) -= 2; ! 290: if (which_alternative == 0) ! 291: return \"dlr r%0,r%1\"; ! 292: else ! 293: return \"dl r%0,%1\"; ! 294: } ") ! 295: ! 296: ; 1750 TQF-to-HF truncate is a no-op: just leave away the least signif. 16 bits ! 297: (define_insn "trunctqfhf2" ! 298: [(set (match_operand:HF 0 "register_operand" "=r,r") ! 299: (float_truncate:HF ! 300: (match_operand:TQF 1 "general_operand" "r,m")))] ! 301: "" ! 302: "@ ! 303: dlr r%0,r%1 ;trunctqfhf2 ! 304: dl r%0,%1 ;trunctqfhf2 ") ! 305: ! 306: ! 307: ;; Conversion between fixed point and floating point. ! 308: ! 309: (define_insn "floatqihf2" ! 310: [(set (match_operand:HF 0 "register_operand" "=r") ! 311: (float:HF (match_operand:QI 1 "register_operand" "r")))] ! 312: "" ! 313: "flt r%0,r%1") ! 314: ! 315: (define_insn "floathitqf2" ! 316: [(set (match_operand:TQF 0 "register_operand" "=r") ! 317: (float:TQF (match_operand:HI 1 "register_operand" "r")))] ! 318: "" ! 319: "eflt r%0,r%1") ! 320: ! 321: ! 322: ;; Convert floats to ints ! 323: ! 324: (define_insn "fix_trunchfqi2" ! 325: [(set (match_operand:QI 0 "register_operand" "=r") ! 326: (fix:QI (fix:HF (match_operand:HF 1 "register_operand" "r"))))] ! 327: "" ! 328: "fix r%0,r%1") ! 329: ! 330: (define_insn "fix_trunctqfhi2" ! 331: [(set (match_operand:HI 0 "register_operand" "=r") ! 332: (fix:HI (fix:TQF (match_operand:TQF 1 "register_operand" "r"))))] ! 333: "" ! 334: "efix r%0,r%1") ! 335: ! 336: ! 337: ;; Move instructions ! 338: ! 339: ;; We can't deal with normal byte-size characters, only with WIDE characters! ! 340: ;; This may appear as a serious restriction, but it also opens the doors ! 341: ;; for ISO 10646 :-) ! 342: ! 343: ;; 16-bit moves ! 344: ! 345: (define_insn "movqi" ! 346: [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,r,r,m,m") ! 347: (match_operand:QI 1 "general_operand" "O,I,J,M,i,r,m,r,K"))] ! 348: "" ! 349: "@ ! 350: xorr r%0,r%0 ! 351: lisp r%0,%1 ! 352: lisn r%0,%J1 ! 353: lim r%0,%1 ; 'M' constraint ! 354: lim r%0,%1 ; 'i' constraint ! 355: lr r%0,r%1 ! 356: l r%0,%1 ! 357: st r%1,%0 ! 358: stc %1,%0 ") ! 359: ! 360: ;; 32-bit moves ! 361: ! 362: ;; Set HIreg to constant ! 363: (define_insn "" ! 364: [(set (match_operand:HI 0 "register_operand" "=r") ! 365: (match_operand 1 "immediate_operand" "i"))] ! 366: "" ! 367: "* ! 368: if (GET_CODE(operands[1]) == CONST_INT) ! 369: { ! 370: int val = INTVAL(operands[1]); ! 371: if (val >= 0) ! 372: { ! 373: if (val <= 65535) ! 374: { ! 375: output_asm_insn(\"xorr r%0,r%0 ;movhi cst->reg\",operands); ! 376: operands[0] = gen_rtx(REG,QImode,REGNO(operands[0]) + 1); ! 377: if (val == 0) ! 378: return \"xorr r%0,r%0\"; ! 379: else if (val <= 16) ! 380: return \"lisp r%0,%1\"; ! 381: else ! 382: return \"lim r%0,%1\"; ! 383: } ! 384: } ! 385: else if (val >= -16) ! 386: return \"lisn r%0,%J1\;dsra r%0,16 ;movhi cst\"; ! 387: INTVAL(operands[1]) >>= 16; ! 388: output_asm_insn(\"lim r%0,%1 ;movhi cst->reg\",operands); ! 389: REGNO(operands[0]) += 1; ! 390: INTVAL(operands[1]) = val & 0xFFFF; ! 391: return \"lim r%0,%1\"; ! 392: } ! 393: return \"lim r%0,%1\;dsra r%0,16 ;movhi cst\"; ! 394: ") ! 395: ! 396: (define_insn "movhi" ! 397: [(set (match_operand:HI 0 "general_operand" "=r,r,m") ! 398: (match_operand:HI 1 "general_operand" "r,m,r"))] ! 399: "" ! 400: "@ ! 401: dlr r%0,r%1 ! 402: dl r%0,%1 ! 403: dst r%1,%0 ") ! 404: ! 405: ! 406: ;; Single-Float moves are *same* as HImode moves: ! 407: ! 408: ;(define_insn "movhf" ! 409: ; [(set (match_operand:HF 0 "general_operand" "=r,r,r,m") ! 410: ; (match_operand:HF 1 "general_operand" "F,r,m,r"))] ! 411: ; "" ! 412: ; "@ ! 413: ; %D1\;dl r%0,%F1 ! 414: ; dlr r%0,r%1 ! 415: ; dl r%0,%1 ! 416: ; dst r%1,%0 ") ! 417: ! 418: (define_insn "movhf" ! 419: [(set (match_operand:HF 0 "general_operand" "=r,r,m") ! 420: (match_operand:HF 1 "general_operand" "r,m,r"))] ! 421: "" ! 422: "@ ! 423: dlr r%0,r%1 ! 424: dl r%0,%1 ! 425: dst r%1,%0 ") ! 426: ! 427: ! 428: ;; Longfloat moves ! 429: ! 430: ;(define_insn "movtqf" ! 431: ; [(set (match_operand:TQF 0 "general_operand" "=r,r,r,m") ! 432: ; (match_operand:TQF 1 "general_operand" "F,r,m,r"))] ! 433: ; "" ! 434: ; "@ ! 435: ; %E1\;efl r%0,%G1 ! 436: ; eflr.m %0,%1 ! 437: ; efl r%0,%1 ! 438: ; efst r%1,%0 ") ! 439: ! 440: (define_insn "movtqf" ! 441: [(set (match_operand:TQF 0 "general_operand" "=r,r,m") ! 442: (match_operand:TQF 1 "general_operand" "r,m,r"))] ! 443: "" ! 444: "@ ! 445: eflr.m %0,%1 ! 446: efl r%0,%1 ! 447: efst r%1,%0 ") ! 448: ! 449: ! 450: ;; add instructions ! 451: ! 452: ;; single integer ! 453: ! 454: ;; Use "LIM Ra,sym,Rb" for adding a symbol value to a register and ! 455: ;; transferring the result to a different register. ! 456: ;(define_insn "" ! 457: ; [(set (match_operand:QI 0 "register_operand" "=r") ! 458: ; (plus:QI (match_operand:QI 1 "register_operand" "b") ! 459: ; (match_operand:QI 2 "immediate_operand" "i")))] ! 460: ; "REGNO(operands[0]) != REGNO(operands[1])" ! 461: ; "lim r%0,%2,r%1 ;md special addqi") ! 462: ! 463: (define_insn "addqi3" ! 464: [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,m,m") ! 465: (plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0,0,0,0") ! 466: (match_operand:QI 2 "general_operand" "I,J,i,r,m,I,J")))] ! 467: "" ! 468: "* ! 469: switch (which_alternative) ! 470: { ! 471: case 0: ! 472: return \"aisp r%0,%2\"; ! 473: case 1: ! 474: return \"sisp r%0,%J2\"; ! 475: case 2: ! 476: if (INTVAL(operands[2]) < 0) ! 477: return \"sim r%0,%J2\"; ! 478: else ! 479: return \"aim r%0,%2\"; ! 480: case 3: ! 481: return \"ar r%0,r%2\"; ! 482: case 4: ! 483: return \"a r%0,%2\"; ! 484: case 5: ! 485: return \"incm %2,%0\"; ! 486: case 6: ! 487: return \"decm %J2,%0\"; ! 488: } ") ! 489: ! 490: ;; double integer ! 491: (define_insn "addhi3" ! 492: [(set (match_operand:HI 0 "register_operand" "=r,r") ! 493: (plus:HI (match_operand:HI 1 "register_operand" "%0,0") ! 494: (match_operand:HI 2 "general_operand" "r,m")))] ! 495: "" ! 496: "@ ! 497: dar r%0,r%2 ! 498: da r%0,%2 ") ! 499: ! 500: (define_insn "addhf3" ! 501: [(set (match_operand:HF 0 "register_operand" "=r,r") ! 502: (plus:HF (match_operand:HF 1 "register_operand" "%0,0") ! 503: (match_operand:HF 2 "general_operand" "m,r")))] ! 504: "" ! 505: "@ ! 506: fa r%0,%2 ! 507: far r%0,r%2 ") ! 508: ! 509: (define_insn "addtqf3" ! 510: [(set (match_operand:TQF 0 "register_operand" "=r,r") ! 511: (plus:TQF (match_operand:TQF 1 "register_operand" "%0,0") ! 512: (match_operand:TQF 2 "general_operand" "m,r")))] ! 513: "" ! 514: "@ ! 515: efa r%0,%2 ! 516: efar r%0,r%2 ") ! 517: ! 518: ! 519: ;; subtract instructions ! 520: ! 521: ;; single integer ! 522: (define_insn "subqi3" ! 523: [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,m") ! 524: (minus:QI (match_operand:QI 1 "general_operand" "0,0,0,0,0") ! 525: (match_operand:QI 2 "general_operand" "I,i,r,m,I")))] ! 526: "" ! 527: "@ ! 528: sisp r%0,%2 ! 529: sim r%0,%2 ! 530: sr r%0,r%2 ! 531: s r%0,%2 ! 532: decm %2,%0 ") ! 533: ! 534: ;; double integer ! 535: (define_insn "subhi3" ! 536: [(set (match_operand:HI 0 "register_operand" "=r,r") ! 537: (minus:HI (match_operand:HI 1 "register_operand" "0,0") ! 538: (match_operand:HI 2 "general_operand" "r,m")))] ! 539: "" ! 540: "@ ! 541: dsr r%0,r%2 ! 542: ds r%0,%2 ") ! 543: ! 544: (define_insn "subhf3" ! 545: [(set (match_operand:HF 0 "register_operand" "=r,r") ! 546: (minus:HF (match_operand:HF 1 "register_operand" "0,0") ! 547: (match_operand:HF 2 "general_operand" "r,m")))] ! 548: "" ! 549: "@ ! 550: fsr r%0,r%2 ! 551: fs r%0,%2 ") ! 552: ! 553: (define_insn "subtqf3" ! 554: [(set (match_operand:TQF 0 "register_operand" "=r,r") ! 555: (minus:TQF (match_operand:TQF 1 "register_operand" "0,0") ! 556: (match_operand:TQF 2 "general_operand" "r,m")))] ! 557: "" ! 558: "@ ! 559: efsr r%0,r%2 ! 560: efs r%0,%2 ") ! 561: ! 562: ! 563: ;; multiply instructions ! 564: ! 565: (define_insn "mulqi3" ! 566: [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r") ! 567: (mult:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0") ! 568: (match_operand:QI 2 "general_operand" "I,J,M,r,m")))] ! 569: "" ! 570: "@ ! 571: misp r%0,%2 ! 572: misn r%0,%J2 ! 573: msim r%0,%2 ! 574: msr r%0,r%2 ! 575: ms r%0,%2 ") ! 576: ! 577: ! 578: ; 32-bit product ! 579: (define_insn "mulqihi3" ! 580: [(set (match_operand:HI 0 "register_operand" "=r,r,r") ! 581: (mult:HI (match_operand:QI 1 "register_operand" "%0,0,0") ! 582: (match_operand:QI 2 "general_operand" "M,r,m")))] ! 583: "" ! 584: "@ ! 585: mim r%0,%1 ! 586: mr r%0,r%2 ! 587: m r%0,%2 ") ! 588: ! 589: (define_insn "mulhi3" ! 590: [(set (match_operand:HI 0 "register_operand" "=r,r") ! 591: (mult:HI (match_operand:HI 1 "register_operand" "%0,0") ! 592: (match_operand:HI 2 "general_operand" "r,m")))] ! 593: "" ! 594: "@ ! 595: dmr r%0,r%2 ! 596: dm r%0,%2 ") ! 597: ! 598: ; not available on 1750: "umulhi3","umulhisi3","umulsi3" (unsigned multiply's) ! 599: ! 600: (define_insn "mulhf3" ! 601: [(set (match_operand:HF 0 "register_operand" "=r,r") ! 602: (mult:HF (match_operand:HF 1 "register_operand" "%0,0") ! 603: (match_operand:HF 2 "general_operand" "r,m")))] ! 604: "" ! 605: "@ ! 606: fmr r%0,r%2 ! 607: fm r%0,%2 ") ! 608: ! 609: (define_insn "multqf3" ! 610: [(set (match_operand:TQF 0 "register_operand" "=r,r") ! 611: (mult:TQF (match_operand:TQF 1 "register_operand" "%0,0") ! 612: (match_operand:TQF 2 "general_operand" "r,m")))] ! 613: "" ! 614: "@ ! 615: efmr r%0,r%2 ! 616: efm r%0,%2 ") ! 617: ! 618: ! 619: ;; divide instructions ! 620: ;; The 1750 16bit integer division instructions deliver a 16-bit ! 621: ;; quotient and a 16-bit remainder, where the remainder is in the next higher ! 622: ;; register number above the quotient. For now, we haven't found a way ! 623: ;; to give the reload pass knowledge of this property. So we make do with ! 624: ;; whatever registers the allocator wants, and willy-nilly output a pair of ! 625: ;; register-copy ops when needed. (See mod_regno_adjust() in file aux-output.c) ! 626: ;; A comment in the description of `divmodM4' suggests that one leave the divM3 ! 627: ;; undefined when there is a divmodM4 available. ! 628: ! 629: (define_insn "divmodqi4" ! 630: [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r") ! 631: (div:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0") ! 632: (match_operand:QI 2 "general_operand" "I,J,M,r,m"))) ! 633: (set (match_operand:QI 3 "register_operand" "=r,r,r,r,r") ! 634: (mod:QI (match_dup 1) (match_dup 2)))] ! 635: "" ! 636: "* ! 637: { ! 638: char *istr; ! 639: switch(which_alternative) ! 640: { ! 641: case 0: ! 642: istr = \"disp\"; ! 643: break; ! 644: case 1: ! 645: INTVAL(operands[2]) = - INTVAL(operands[2]); /* to be corrected */ ! 646: istr = \"disn\"; ! 647: break; ! 648: case 2: ! 649: istr = \"dvim\"; ! 650: break; ! 651: case 3: ! 652: istr = \"dvr \"; ! 653: break; ! 654: case 4: ! 655: istr = \"dv \"; ! 656: break; ! 657: } ! 658: return (char *)mod_regno_adjust(istr,operands); ! 659: }") ! 660: ! 661: ;; Division for other types is straightforward. ! 662: ! 663: (define_insn "divhi3" ! 664: [(set (match_operand:HI 0 "register_operand" "=r,r") ! 665: (div:HI (match_operand:HI 1 "register_operand" "0,0") ! 666: (match_operand:HI 2 "general_operand" "r,m")))] ! 667: "" ! 668: "@ ! 669: ddr r%0,r%2 ! 670: dd r%0,%2 ") ! 671: ! 672: (define_insn "divhf3" ! 673: [(set (match_operand:HF 0 "register_operand" "=r,r") ! 674: (div:HF (match_operand:HF 1 "register_operand" "0,0") ! 675: (match_operand:HF 2 "general_operand" "r,m")))] ! 676: "" ! 677: "@ ! 678: fdr r%0,r%2 ! 679: fd r%0,%2 ") ! 680: ! 681: (define_insn "divtqf3" ! 682: [(set (match_operand:TQF 0 "register_operand" "=r,r") ! 683: (div:TQF (match_operand:TQF 1 "register_operand" "0,0") ! 684: (match_operand:TQF 2 "general_operand" "r,m")))] ! 685: "" ! 686: "@ ! 687: efdr r%0,r%2 ! 688: efd r%0,%2 ") ! 689: ! 690: ! 691: ;; Other arithmetic instructions: ! 692: ! 693: ;; Absolute value ! 694: ! 695: (define_insn "absqi2" ! 696: [(set (match_operand:QI 0 "register_operand" "=r") ! 697: (abs:QI (match_operand:QI 1 "register_operand" "r")))] ! 698: "" ! 699: "abs r%0,r%1") ! 700: ! 701: (define_insn "abshi2" ! 702: [(set (match_operand:HI 0 "register_operand" "=r") ! 703: (abs:HI (match_operand:HI 1 "register_operand" "r")))] ! 704: "" ! 705: "dabs r%0,r%1") ! 706: ! 707: (define_insn "abshf2" ! 708: [(set (match_operand:HF 0 "register_operand" "=r") ! 709: (abs:HF (match_operand:HF 1 "register_operand" "r")))] ! 710: "" ! 711: "fabs r%0,r%1") ! 712: ! 713: ! 714: ;; Negation ! 715: ! 716: (define_insn "negqi2" ! 717: [(set (match_operand:QI 0 "register_operand" "=r") ! 718: (neg:QI (match_operand:QI 1 "register_operand" "r")))] ! 719: "" ! 720: "neg r%0,r%1") ! 721: ! 722: (define_insn "neghi2" ! 723: [(set (match_operand:HI 0 "register_operand" "=r") ! 724: (neg:HI (match_operand:HI 1 "register_operand" "r")))] ! 725: "" ! 726: "dneg r%0,r%1") ! 727: ! 728: (define_insn "neghf2" ! 729: [(set (match_operand:HF 0 "register_operand" "=r") ! 730: (neg:HF (match_operand:HF 1 "register_operand" "r")))] ! 731: "" ! 732: "fneg r%0,r%1") ! 733: ! 734: ; The 1750A does not have an extended float negate instruction, so simulate. ! 735: (define_expand "negtqf2" ! 736: [(set (match_operand:TQF 0 "register_operand" "=&r") ! 737: (neg:TQF (match_operand:TQF 1 "register_operand" "r")))] ! 738: "" ! 739: " ! 740: emit_insn(gen_rtx(SET,VOIDmode,operands[0],CONST0_RTX(TQFmode))); ! 741: emit_insn(gen_rtx(SET,VOIDmode,operands[0], ! 742: gen_rtx(MINUS,TQFmode,operands[0],operands[1]))); ! 743: DONE; ! 744: ") ! 745: ! 746: ! 747: ;; bit-logical instructions ! 748: ! 749: ;; AND ! 750: ! 751: (define_insn "andqi3" ! 752: [(set (match_operand:QI 0 "general_operand" "=r,r,r") ! 753: (and:QI (match_operand:QI 1 "general_operand" "%0,0,0") ! 754: (match_operand:QI 2 "general_operand" "M,r,m")))] ! 755: "" ! 756: "@ ! 757: andm r%0,%2 ! 758: andr r%0,r%2 ! 759: and r%0,%2 ") ! 760: ! 761: ; This sets incorrect condition codes. See notice_update_cc() ! 762: (define_insn "andhi3" ! 763: [(set (match_operand:HI 0 "register_operand" "=r") ! 764: (and:HI (match_operand:HI 1 "register_operand" "%0") ! 765: (match_operand:HI 2 "register_operand" "r")))] ! 766: "" ! 767: "danr.m %0,%2") ! 768: ! 769: ;; OR ! 770: ! 771: (define_insn "iorqi3" ! 772: [(set (match_operand:QI 0 "general_operand" "=r,r,r") ! 773: (ior:QI (match_operand:QI 1 "general_operand" "%0,0,0") ! 774: (match_operand:QI 2 "general_operand" "M,r,m")))] ! 775: "" ! 776: "@ ! 777: orim r%0,%2 ! 778: orr r%0,r%2 ! 779: or r%0,%2 ") ! 780: ! 781: ; This sets incorrect condition codes. See notice_update_cc() ! 782: (define_insn "iorhi3" ! 783: [(set (match_operand:HI 0 "register_operand" "=r") ! 784: (ior:HI (match_operand:HI 1 "register_operand" "%0") ! 785: (match_operand:HI 2 "register_operand" "r")))] ! 786: "" ! 787: "dorr.m %0,%2") ! 788: ! 789: ;; XOR ! 790: ! 791: (define_insn "xorqi3" ! 792: [(set (match_operand:QI 0 "register_operand" "=r,r,r") ! 793: (xor:QI (match_operand:QI 1 "register_operand" "%0,0,0") ! 794: (match_operand:QI 2 "general_operand" "M,r,m")))] ! 795: "" ! 796: "@ ! 797: xorm r%0,%2 ! 798: xorr r%0,r%2 ! 799: xor r%0,%2 ") ! 800: ! 801: ; This sets incorrect condition codes. See notice_update_cc() ! 802: (define_insn "xorhi3" ! 803: [(set (match_operand:HI 0 "register_operand" "=r") ! 804: (xor:HI (match_operand:HI 1 "register_operand" "%0") ! 805: (match_operand:HI 2 "register_operand" "r")))] ! 806: "" ! 807: "dxrr.m %0,%2") ! 808: ! 809: ;; NAND ! 810: ! 811: (define_insn "" ! 812: [(set (match_operand:QI 0 "register_operand" "=r,r,r") ! 813: (ior:QI (not:QI (match_operand:QI 1 "register_operand" "%0,0,0")) ! 814: (not:QI (match_operand:QI 2 "general_operand" "M,r,m"))))] ! 815: "" ! 816: "@ ! 817: nim r%0,%2 ! 818: nr r%0,r%2 ! 819: n r%0,%2 ") ! 820: ! 821: ; This sets incorrect condition codes. See notice_update_cc() ! 822: (define_insn "" ! 823: [(set (match_operand:HI 0 "register_operand" "=r") ! 824: (ior:HI (not:HI (match_operand:HI 1 "register_operand" "%0")) ! 825: (not:HI (match_operand:HI 2 "register_operand" "r"))))] ! 826: "" ! 827: "dnr.m %0,%2") ! 828: ! 829: ;; NOT ! 830: ! 831: (define_insn "one_cmplqi2" ! 832: [(set (match_operand:QI 0 "register_operand" "=r") ! 833: (not:QI (match_operand:QI 1 "register_operand" "0")))] ! 834: "" ! 835: "nr r%0,r%0") ! 836: ! 837: ; This sets incorrect condition codes. See notice_update_cc() ! 838: (define_insn "one_cmplhi2" ! 839: [(set (match_operand:HI 0 "register_operand" "=r") ! 840: (not:HI (match_operand:HI 1 "register_operand" "0")))] ! 841: "" ! 842: "dnr.m %0,%0") ! 843: ! 844: ! 845: ;; Shift instructions ! 846: ! 847: ; (What to the 1750 is logical-shift-left, GCC likes to call "arithmetic") ! 848: (define_insn "ashlqi3" ! 849: [(set (match_operand:QI 0 "register_operand" "=r,r,r") ! 850: (ashift:QI (match_operand:QI 1 "register_operand" "0,0,0") ! 851: (match_operand:QI 2 "general_operand" "O,I,r")))] ! 852: "" ! 853: "@ ! 854: ; optimized away an SLL r%0,0 ! 855: sll r%0,%2 ! 856: slr r%0,r%2 ") ! 857: ! 858: (define_insn "ashlhi3" ! 859: [(set (match_operand:HI 0 "register_operand" "=r,r") ! 860: (ashift:HI (match_operand:HI 1 "register_operand" "0,0") ! 861: (match_operand:QI 2 "general_operand" "L,r")))] ! 862: "" ; the 'L' constraint is a slight imprecise... ! 863: "@ ! 864: dsll r%0,%2 ! 865: dslr r%0,r%2 ") ! 866: ! 867: (define_insn "lshrqi3" ! 868: [(set (match_operand:QI 0 "register_operand" "=r,r") ! 869: (lshiftrt:QI (match_operand:QI 1 "register_operand" "0,0") ! 870: (match_operand:QI 2 "general_operand" "I,r")))] ! 871: "" ! 872: "@ ! 873: srl r%0,%2 ! 874: neg r%2,r%2\;slr r%0,r%2 ") ! 875: ! 876: (define_insn "lshrhi3" ! 877: [(set (match_operand:HI 0 "register_operand" "=r,r") ! 878: (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0") ! 879: (match_operand:QI 2 "general_operand" "L,r")))] ! 880: "" ; the 'L' constraint is a slight imprecise... ! 881: "@ ! 882: dsrl r%0,%2 ! 883: neg r%2,r%2\;dslr r%0,r%2 ") ! 884: ! 885: (define_insn "ashrqi3" ! 886: [(set (match_operand:QI 0 "register_operand" "=r,r") ! 887: (ashiftrt:QI (match_operand:QI 1 "register_operand" "0,0") ! 888: (match_operand:QI 2 "general_operand" "I,r")))] ! 889: "" ! 890: "@ ! 891: sra r%0,%2 ! 892: neg r%2,r%2\;sar r%0,r%2 ") ! 893: ! 894: (define_insn "ashrhi3" ! 895: [(set (match_operand:HI 0 "register_operand" "=r,r") ! 896: (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0") ! 897: (match_operand:QI 2 "general_operand" "I,r")))] ! 898: "" ! 899: "@ ! 900: dsra r%0,%2 ! 901: neg r%2,r%2\;dsar r%0,r%2 ") ! 902: ! 903: ! 904: ;; rotate instructions ! 905: ! 906: (define_insn "rotlqi3" ! 907: [(set (match_operand:QI 0 "register_operand" "=r,r") ! 908: (rotate:QI (match_operand:QI 1 "register_operand" "0,0") ! 909: (match_operand:QI 2 "general_operand" "I,r")))] ! 910: "" ! 911: "@ ! 912: slc r%0,%2 ! 913: scr r%0,r%2 ") ! 914: ! 915: (define_insn "rotlhi3" ! 916: [(set (match_operand:HI 0 "register_operand" "=r,r") ! 917: (rotate:HI (match_operand:HI 1 "register_operand" "0,0") ! 918: (match_operand:QI 2 "general_operand" "I,r")))] ! 919: "" ! 920: "@ ! 921: dslc r%0,%2 ! 922: dscr r%0,r%2 ") ! 923: ! 924: (define_insn "rotrqi3" ! 925: [(set (match_operand:QI 0 "register_operand" "=r,r") ! 926: (rotatert:QI (match_operand:QI 1 "register_operand" "0,0") ! 927: (match_operand:QI 2 "general_operand" "I,r")))] ! 928: "" ! 929: "@ ! 930: slc r%0,%2 ! 931: neg r%2,r%2\;scr r%0,r%2 ") ! 932: ! 933: (define_insn "rotrhi3" ! 934: [(set (match_operand:HI 0 "register_operand" "=r,r") ! 935: (rotatert:HI (match_operand:HI 1 "register_operand" "0,0") ! 936: (match_operand:QI 2 "general_operand" "I,r")))] ! 937: "" ! 938: "@ ! 939: dslc r%0,%2 ! 940: neg r%2,r%2\;dscr r%0,r%2 ") ! 941: ! 942: ! 943: ! 944: ;; Special cases of bit-field insns which we should ! 945: ;; recognize in preference to the general case. ! 946: ;; These handle aligned 8-bit and 16-bit fields, ! 947: ;; which can usually be done with move instructions. ! 948: ; 1750: t.b.d. ! 949: ;******************** ! 950: ! 951: ;; Bit field instructions, general cases. ! 952: ;; "o,d" constraint causes a nonoffsetable memref to match the "o" ! 953: ;; so that its address is reloaded. ! 954: ! 955: ;; (define_insn "extv" ... ! 956: ! 957: ;; (define_insn "extzv" ... ! 958: ! 959: ;; (define_insn "insv" ... ! 960: ! 961: ;; Now recognize bit field insns that operate on registers ! 962: ;; (or at least were intended to do so). ! 963: ;[unnamed only] ! 964: ! 965: ;; Special patterns for optimizing bit-field instructions. ! 966: ;************************************** ! 967: ! 968: ; cc status test ops n.a. on 1750 ......... e.g. "sleu" on 68k: ! 969: ; [(set (match_operand:QI 0 "general_operand" "=d") ! 970: ; (leu (cc0) (const_int 0)))] ! 971: ; "" ! 972: ; "* cc_status = cc_prev_status; ! 973: ; return \"sls %0\"; ") ! 974: ! 975: ! 976: ;; Basic conditional jump instructions. ! 977: ! 978: (define_insn "beq" ! 979: [(set (pc) ! 980: (if_then_else (eq (cc0) ! 981: (const_int 0)) ! 982: (label_ref (match_operand 0 "" "")) ! 983: (pc)))] ! 984: "" ! 985: "* return (char *)branch_or_jump(\"ez\",CODE_LABEL_NUMBER(operands[0])); ! 986: ") ! 987: ! 988: (define_insn "bne" ! 989: [(set (pc) ! 990: (if_then_else (ne (cc0) ! 991: (const_int 0)) ! 992: (label_ref (match_operand 0 "" "")) ! 993: (pc)))] ! 994: "" ! 995: "* return (char *)branch_or_jump(\"nz\",CODE_LABEL_NUMBER(operands[0])); ! 996: ") ! 997: ! 998: (define_insn "bgt" ! 999: [(set (pc) ! 1000: (if_then_else (gt (cc0) ! 1001: (const_int 0)) ! 1002: (label_ref (match_operand 0 "" "")) ! 1003: (pc)))] ! 1004: "" ! 1005: "* return (char *)branch_or_jump(\"gt\",CODE_LABEL_NUMBER(operands[0])); ! 1006: ") ! 1007: ! 1008: (define_insn "blt" ! 1009: [(set (pc) ! 1010: (if_then_else (lt (cc0) ! 1011: (const_int 0)) ! 1012: (label_ref (match_operand 0 "" "")) ! 1013: (pc)))] ! 1014: "" ! 1015: "* return (char *)branch_or_jump(\"lt\",CODE_LABEL_NUMBER(operands[0])); ! 1016: ") ! 1017: ! 1018: (define_insn "bge" ! 1019: [(set (pc) ! 1020: (if_then_else (ge (cc0) ! 1021: (const_int 0)) ! 1022: (label_ref (match_operand 0 "" "")) ! 1023: (pc)))] ! 1024: "" ! 1025: "* return (char *)branch_or_jump(\"ge\",CODE_LABEL_NUMBER(operands[0])); ! 1026: ") ! 1027: ! 1028: (define_insn "ble" ! 1029: [(set (pc) ! 1030: (if_then_else (le (cc0) ! 1031: (const_int 0)) ! 1032: (label_ref (match_operand 0 "" "")) ! 1033: (pc)))] ! 1034: "" ! 1035: "* return (char *)branch_or_jump(\"le\",CODE_LABEL_NUMBER(operands[0])); ! 1036: ") ! 1037: ! 1038: ! 1039: ; no unsigned branches available on 1750. But GCC still needs them, so faking: ! 1040: ! 1041: (define_insn "bgtu" ! 1042: [(set (pc) ! 1043: (if_then_else (gtu (cc0) ! 1044: (const_int 0)) ! 1045: (label_ref (match_operand 0 "" "")) ! 1046: (pc)))] ! 1047: "" ! 1048: "jc gt,%l0 ; Warning: this should be an *unsigned* test!") ! 1049: ! 1050: (define_insn "bltu" ! 1051: [(set (pc) ! 1052: (if_then_else (ltu (cc0) ! 1053: (const_int 0)) ! 1054: (label_ref (match_operand 0 "" "")) ! 1055: (pc)))] ! 1056: "" ! 1057: "jc lt,%l0 ; Warning: this should be an *unsigned* test!") ! 1058: ! 1059: (define_insn "bgeu" ! 1060: [(set (pc) ! 1061: (if_then_else (geu (cc0) ! 1062: (const_int 0)) ! 1063: (label_ref (match_operand 0 "" "")) ! 1064: (pc)))] ! 1065: "" ! 1066: "jc ge,%l0 ; Warning: this should be an *unsigned* test!") ! 1067: ! 1068: (define_insn "bleu" ! 1069: [(set (pc) ! 1070: (if_then_else (leu (cc0) ! 1071: (const_int 0)) ! 1072: (label_ref (match_operand 0 "" "")) ! 1073: (pc)))] ! 1074: "" ! 1075: "jc le,%l0 ; Warning: this should be an *unsigned* test!") ! 1076: ! 1077: ! 1078: ;; Negated conditional jump instructions. ! 1079: ! 1080: (define_insn "" ! 1081: [(set (pc) ! 1082: (if_then_else (eq (cc0) ! 1083: (const_int 0)) ! 1084: (pc) ! 1085: (label_ref (match_operand 0 "" ""))))] ! 1086: "" ! 1087: "* return (char *)branch_or_jump(\"nz\",CODE_LABEL_NUMBER(operands[0])); ! 1088: ") ! 1089: ! 1090: (define_insn "" ! 1091: [(set (pc) ! 1092: (if_then_else (ne (cc0) ! 1093: (const_int 0)) ! 1094: (pc) ! 1095: (label_ref (match_operand 0 "" ""))))] ! 1096: "" ! 1097: "* return (char *)branch_or_jump(\"ez\",CODE_LABEL_NUMBER(operands[0])); ! 1098: ") ! 1099: ! 1100: (define_insn "" ! 1101: [(set (pc) ! 1102: (if_then_else (gt (cc0) ! 1103: (const_int 0)) ! 1104: (pc) ! 1105: (label_ref (match_operand 0 "" ""))))] ! 1106: "" ! 1107: "* return (char *)branch_or_jump(\"le\",CODE_LABEL_NUMBER(operands[0])); ! 1108: ") ! 1109: ! 1110: (define_insn "" ! 1111: [(set (pc) ! 1112: (if_then_else (lt (cc0) ! 1113: (const_int 0)) ! 1114: (pc) ! 1115: (label_ref (match_operand 0 "" ""))))] ! 1116: "" ! 1117: "* return (char *)branch_or_jump(\"ge\",CODE_LABEL_NUMBER(operands[0])); ! 1118: ") ! 1119: ! 1120: (define_insn "" ! 1121: [(set (pc) ! 1122: (if_then_else (ge (cc0) ! 1123: (const_int 0)) ! 1124: (pc) ! 1125: (label_ref (match_operand 0 "" ""))))] ! 1126: "" ! 1127: "* return (char *)branch_or_jump(\"lt\",CODE_LABEL_NUMBER(operands[0])); ! 1128: ") ! 1129: ! 1130: (define_insn "" ! 1131: [(set (pc) ! 1132: (if_then_else (le (cc0) ! 1133: (const_int 0)) ! 1134: (pc) ! 1135: (label_ref (match_operand 0 "" ""))))] ! 1136: "" ! 1137: "* return (char *)branch_or_jump(\"gt\",CODE_LABEL_NUMBER(operands[0])); ! 1138: ") ! 1139: ! 1140: ! 1141: ;; Negated unsigned conditional jump instructions (faked for 1750). ! 1142: ! 1143: (define_insn "" ! 1144: [(set (pc) ! 1145: (if_then_else (gtu (cc0) ! 1146: (const_int 0)) ! 1147: (pc) ! 1148: (label_ref (match_operand 0 "" ""))))] ! 1149: "" ! 1150: "jc le,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!") ! 1151: ! 1152: (define_insn "" ! 1153: [(set (pc) ! 1154: (if_then_else (ltu (cc0) ! 1155: (const_int 0)) ! 1156: (pc) ! 1157: (label_ref (match_operand 0 "" ""))))] ! 1158: "" ! 1159: "jc ge,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!") ! 1160: ! 1161: (define_insn "" ! 1162: [(set (pc) ! 1163: (if_then_else (geu (cc0) ! 1164: (const_int 0)) ! 1165: (pc) ! 1166: (label_ref (match_operand 0 "" ""))))] ! 1167: "" ! 1168: "jc lt,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!") ! 1169: ! 1170: (define_insn "" ! 1171: [(set (pc) ! 1172: (if_then_else (leu (cc0) ! 1173: (const_int 0)) ! 1174: (pc) ! 1175: (label_ref (match_operand 0 "" ""))))] ! 1176: "" ! 1177: "jc gt,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!") ! 1178: ! 1179: ;; Tablejump ! 1180: ;; 1750 note: CASE_VECTOR_PC_RELATIVE is not defined ! 1181: (define_insn "tablejump" ! 1182: [(set (pc) ! 1183: (match_operand:QI 0 "register_operand" "b")) ! 1184: (use (label_ref (match_operand 1 "" "")))] ! 1185: "" ! 1186: "jc 15,0,r%0 ; tablejump label_ref=%1") ! 1187: ! 1188: ! 1189: ;; Unconditional jump ! 1190: (define_insn "jump" ! 1191: [(set (pc) ! 1192: (label_ref (match_operand 0 "" "")))] ! 1193: "" ! 1194: "jc uc,%0") ! 1195: ! 1196: ;; Call subroutine, returning value in operand 0 ! 1197: ;; (which must be a hard register). ! 1198: (define_insn "call_value" ! 1199: [(set (match_operand 0 "register_operand" "r") ! 1200: (call (match_operand:QI 1 "memory_operand" "m") ! 1201: (match_operand:QI 2 "general_operand" "g")))] ! 1202: ;; Operand 2 not really used for 1750. ! 1203: "" ! 1204: "sjs r15,%1 ; return value in R0") ! 1205: ! 1206: ;; Call subroutine with no return value. ! 1207: ! 1208: ;; Operand 1 not really used in MIL-STD-1750. ! 1209: (define_insn "" ! 1210: [(call (match_operand:QI 0 "memory_operand" "mp") ! 1211: (match_operand:QI 1 "general_operand" ""))] ! 1212: "" ! 1213: "sjs r15,%0 ; no return value") ! 1214: ! 1215: ;;;;;;;;;;;; 1750: NOT READY YET. ! 1216: (define_insn "call" ! 1217: [(call (match_operand:QI 0 "" "") ! 1218: (match_operand:QI 1 "" ""))] ! 1219: "" ! 1220: "ANYCALL %0") ! 1221: ! 1222: ! 1223: ; (define_insn "return" ! 1224: ; [(return)] ! 1225: ; "" ! 1226: ; "* ! 1227: ; { ! 1228: ; rtx oprnd = gen_rtx(CONST_INT,VOIDmode,get_frame_size()); ! 1229: ; output_asm_insn(\"ret.m %0\",&oprnd); ! 1230: ; return \"\;\"; ! 1231: ; } ") ! 1232: ! 1233: (define_insn "indirect_jump" ! 1234: [(set (pc) (match_operand:QI 0 "address_operand" "p"))] ! 1235: "" ! 1236: "jci 15,%0") ! 1237: ! 1238: (define_insn "nop" ! 1239: [(const_int 0)] ! 1240: "" ! 1241: "nop") ! 1242: ! 1243: ! 1244: ;; Subtract One and Jump (if non-zero) ! 1245: (define_peephole ! 1246: [(set (match_operand:QI 0 "register_operand" "=r") ! 1247: (plus:QI (match_operand:QI 1 "register_operand" "%0") ! 1248: (match_operand:QI 2 "immediate_operand" "J"))) ! 1249: (set (cc0) (match_dup 0)) ! 1250: (set (pc) ! 1251: (if_then_else (ne (cc0) (const_int 0)) ! 1252: (label_ref (match_operand 3 "" "")) ! 1253: (pc))) ! 1254: ] ! 1255: "INTVAL(operands[2]) == -1" ! 1256: "soj r%0,%3") ! 1257: ! 1258: ;;;End. ! 1259:
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