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1.1 root 1: ;;- Machine description for GNU compiler
2: ;;- MIL-STD-1750A version.
1.1.1.2 ! root 3: ;; Copyright (C) 1994, 1995 Free Software Foundation, Inc.
! 4: ;; Contributed by O.M.Kellogg, DASA ([email protected]).
1.1 root 5:
6: ;; This file is part of GNU CC.
7:
8: ;; GNU CC is free software; you can redistribute it and/or modify
9: ;; it under the terms of the GNU General Public License as published by
10: ;; the Free Software Foundation; either version 1, or (at your option)
11: ;; any later version.
12:
13: ;; GNU CC is distributed in the hope that it will be useful,
14: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16: ;; GNU General Public License for more details.
17:
18: ;; You should have received a copy of the GNU General Public License
19: ;; along with GNU CC; see the file COPYING. If not, write to
1.1.1.2 ! root 20: ;; the Free Software Foundation, 59 Temple Place - Suite 330,
! 21: ;; Boston, MA 02111-1307, USA.
1.1 root 22:
23:
24: ;;- instruction definitions
25:
26: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
27:
28: ;;- When naming insn's (operand 0 of define_insn) be careful about using
29: ;;- names from other targets machine descriptions.
30:
31: ;; MIL-STD-1750 specific remarks:
32: ;;
33: ;; 1) BITS_PER_UNIT = 16
34: ;;
35: ;; 2) GCC to MIL-STD-1750 data type mappings:
36: ;; QImode => single integer (16 bits or 1 reg).
37: ;; HImode => double integer (32 bits or 2 regs).
38: ;; HFmode => single precision float (32 bits or 2 regs).
39: ;; TQFmode => extended precision float (48 bits or 3 regs).
40: ;;
41: ;; 3) Immediate integer operands Constraints:
42: ;; 'I' 1 .. 16
43: ;; 'J' -1 ..-16
44: ;; 'K' 0 .. 15
45: ;; 'L' 0 .. 255
46: ;; 'M' -32768 .. 32767
47: ;; 'O' => 0 (for optimizations and GCC quirks)
48: ;;
49: ;; Further notes:
50: ;;- Assembly output ending in ".M" are macros in file M1750.INC
51:
52:
53: ;; stackpush
54: (define_insn ""
55: [(set (match_operand:QI 0 "push_operand" "=<")
56: (match_operand:QI 1 "general_operand" "r"))]
57: ""
1.1.1.2 ! root 58: "pshm r%1,r%1 ; stackptr = R%0")
1.1 root 59:
60: (define_insn ""
61: [(set (match_operand:HI 0 "push_operand" "=<")
62: (match_operand:HI 1 "general_operand" "r"))]
63: ""
64: "*
65: {
1.1.1.2 ! root 66: rtx new_operands[3];
! 67: new_operands[2] = operands[0];
1.1 root 68: new_operands[0] = operands[1];
69: new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+1);
1.1.1.2 ! root 70: output_asm_insn(\"pshm r%0,r%1 ; stackptr = r%2\",new_operands);
! 71: return \";\";
1.1 root 72: } ")
73:
74: (define_insn ""
75: [(set (match_operand:HF 0 "push_operand" "=<")
76: (match_operand:HF 1 "general_operand" "r"))]
77: ""
78: "*
79: {
1.1.1.2 ! root 80: rtx new_operands[3];
! 81: new_operands[2] = operands[0];
1.1 root 82: new_operands[0] = operands[1];
83: new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+1);
1.1.1.2 ! root 84: output_asm_insn(\"pshm r%0,r%1 ; stackptr = r%2\",new_operands);
! 85: return \";\";
1.1 root 86: } ")
87:
88: (define_insn ""
89: [(set (match_operand:TQF 0 "push_operand" "=<")
90: (match_operand:TQF 1 "general_operand" "r"))]
91: ""
92: "*
93: {
1.1.1.2 ! root 94: rtx new_operands[3];
! 95: new_operands[2] = operands[0];
1.1 root 96: new_operands[0] = operands[1];
97: new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+2);
1.1.1.2 ! root 98: output_asm_insn(\"pshm r%0,r%1 ; stackptr = r%2\",new_operands);
! 99: return \";\";
1.1 root 100: } ")
101:
102: ;; stackpop
103: (define_insn ""
104: [(set (match_operand:QI 0 "general_operand" "=r")
105: (match_operand:QI 1 "push_operand" ">"))]
106: ""
107: "popm r%1,r%1")
108:
109: (define_insn ""
110: [(set (match_operand:HI 0 "general_operand" "=r")
111: (match_operand:HI 1 "push_operand" ">"))]
112: ""
113: "*
114: {
115: rtx new_operands[2];
116: new_operands[0] = operands[0];
117: new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+1);
118: output_asm_insn(\"popm r%0,r%1\",new_operands);
1.1.1.2 ! root 119: return \";\";
1.1 root 120: } ")
121:
122: (define_insn ""
123: [(set (match_operand:HF 0 "general_operand" "=r")
124: (match_operand:HF 1 "push_operand" ">"))]
125: ""
126: "*
127: {
128: rtx new_operands[2];
129: new_operands[0] = operands[0];
130: new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+1);
131: output_asm_insn(\"popm r%0,r%1\",new_operands);
1.1.1.2 ! root 132: return \";\";
1.1 root 133: } ")
134:
135: (define_insn ""
136: [(set (match_operand:TQF 0 "general_operand" "=r")
137: (match_operand:TQF 1 "push_operand" ">"))]
138: ""
139: "*
140: {
141: rtx new_operands[2];
142: new_operands[0] = operands[0];
143: new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+2);
144: output_asm_insn(\"popm r%0,r%1\",new_operands);
1.1.1.2 ! root 145: return \";\";
1.1 root 146: } ")
147:
148: ;; Test operations. These shouldn't really occur for 1750:
149: ;; all important instructions set the cc's (see NOTICE_UPDATE_CC)
150:
151: (define_insn "tstqi"
152: [(set (cc0)
153: (match_operand:QI 0 "register_operand" "r"))]
154: ""
155: "lr r%0,r%0 ; from tstqi")
156:
157: (define_insn "tsthi"
158: [(set (cc0)
159: (match_operand:HI 0 "register_operand" "r"))]
160: ""
161: "dlr r%0,r%0 ; from tsthi")
162:
163: (define_insn "tsthf"
164: [(set (cc0)
165: (match_operand:HF 0 "register_operand" "r"))]
166: ""
167: "dlr r%0,r%0 ; from tsthf")
168:
169: ;; This one is happy with "roughly zero" :-) (should be improved)
170: (define_insn "tsttqf"
171: [(set (cc0)
172: (match_operand:TQF 0 "register_operand" "r"))]
173: ""
174: "dlr r%0,r%0 ; from tsttqf")
175:
176:
177: ;; block move.
178:
179: ; there is a problem with this insn in gcc-2.2.3
180: ; (clobber (match_dup 2)) does not prevent use of this operand later
181: ;
182: (define_insn "movstrqi"
183: [(set (mem:BLK (match_operand:QI 0 "register_operand" "r"))
184: (mem:BLK (match_operand:QI 1 "register_operand" "r")))
185: (use (match_operand:QI 2 "register_operand" "r"))
186: (use (match_operand:QI 3 "immediate_operand" ""))
187: (clobber (match_dup 0))
188: (clobber (match_dup 1))
189: (clobber (match_dup 2))]
190: ""
191: "* return (char *)movcnt_regno_adjust(operands); ")
192:
193:
194: ;; compare instructions.
195:
196: (define_insn "cmpqi"
197: [(set (cc0)
198: (compare (match_operand:QI 0 "register_operand" "r,r,r,r,r")
199: (match_operand:QI 1 "general_operand" "I,J,i,r,m")))]
200: ""
1.1.1.2 ! root 201: "*
! 202: {
! 203: if (next_cc_user_is_unsigned (insn))
! 204: switch (which_alternative)
! 205: {
! 206: case 0:
! 207: case 1:
! 208: case 2:
! 209: return \"ucim.m %0,%1\";
! 210: case 3:
! 211: return \"ucr.m %0,%1\";
! 212: case 4:
! 213: return \"uc.m %0,%1\";
! 214: }
! 215: else
! 216: switch (which_alternative)
! 217: {
! 218: case 0:
! 219: return \"cisp r%0,%1\";
! 220: case 1:
! 221: return \"cisn r%0,%J1\";
! 222: case 2:
! 223: return \"cim r%0,%1\";
! 224: case 3:
! 225: return \"cr r%0,r%1\";
! 226: case 4:
! 227: return \"c r%0,%1\";
! 228: }
! 229: } ")
1.1 root 230:
231: (define_insn "cmphi"
232: [(set (cc0)
233: (compare (match_operand:HI 0 "general_operand" "r,r")
234: (match_operand:HI 1 "general_operand" "r,m")))]
235: ""
236: "@
237: dcr r%0,r%1
238: dc r%0,%1 ")
239:
240: (define_insn "cmphf"
241: [(set (cc0)
1.1.1.2 ! root 242: (compare (match_operand:HF 0 "general_operand" "r,z,r")
! 243: (match_operand:HF 1 "general_operand" "r,Q,m")))]
1.1 root 244: ""
245: "@
246: fcr r%0,r%1
1.1.1.2 ! root 247: fcb %Q1
1.1 root 248: fc r%0,%1 ")
249:
250: (define_insn "cmptqf"
251: [(set (cc0)
252: (compare (match_operand:TQF 0 "general_operand" "r,r")
253: (match_operand:TQF 1 "general_operand" "r,m")))]
254: ""
255: "@
256: efcr r%0,r%1
257: efc r%0,%1 ")
258:
259:
260: ;; truncation instructions
261: ;;- 1750: any needed?
262:
263: (define_insn "trunchiqi2"
264: [(set (match_operand:QI 0 "register_operand" "=r")
265: (truncate:QI
266: (match_operand:HI 1 "register_operand" "r")))]
267: ""
268: "*
269: {
1.1.1.2 ! root 270: rtx new_operands[2];
! 271: new_operands[0] = operands[0];
! 272: new_operands[1] = gen_rtx (REG, HImode, REGNO(operands[1]) + 1);
! 273: output_asm_insn(\"lr r%0,r%1 ;trunchiqi2\",new_operands);
! 274: return \";\";
1.1 root 275: } ")
276:
277: ;; zero extension instructions
278:
279: (define_insn "zero_extendqihi2"
280: [(set (match_operand:HI 0 "register_operand" "=r,r,r")
281: (zero_extend:HI (match_operand:QI 1 "general_operand" "r,m,i")))]
282: ""
283: "*
284: {
1.1.1.2 ! root 285: rtx new_opnds[2];
1.1 root 286: output_asm_insn(\"xorr r%0,r%0 ;zero_extendqihi2\",operands);
1.1.1.2 ! root 287: new_opnds[0] = gen_rtx (REG, HImode, REGNO(operands[0]) + 1);
! 288: new_opnds[1] = operands[1];
1.1 root 289: switch (which_alternative)
290: {
291: case 0:
1.1.1.2 ! root 292: output_asm_insn(\"lr r%0,r%1\",new_opnds);
! 293: break;
1.1 root 294: case 1:
1.1.1.2 ! root 295: output_asm_insn(\"l r%0,%1\",new_opnds);
! 296: break;
1.1 root 297: case 2:
1.1.1.2 ! root 298: output_asm_insn(\"lim r%0,%1\",new_opnds);
! 299: break;
1.1 root 300: }
1.1.1.2 ! root 301: return \";\";
1.1 root 302: } ")
303:
304: ;; sign extension instructions
305:
306: (define_insn "extendqihi2"
307: [(set (match_operand:HI 0 "register_operand" "=r,r,r")
308: (sign_extend:HI (match_operand:QI 1 "general_operand" "r,m,i")) )]
309: ""
310: "@
311: lr r%0,r%1 ;extendqihi2\;dsra r%0,16
312: l r%0,%1 ;extendqihi2\;dsra r%0,16
313: lim r%0,%1 ;extendqihi2\;dsra r%0,16 ")
314:
315:
316: ;; Conversions between float and double.
317:
318: ; 1750 HF-to-TQF extend: just append 16 bits (least signif.) with all bits zero
319: (define_insn "extendhftqf2"
320: [(set (match_operand:TQF 0 "register_operand" "=r,r")
1.1.1.2 ! root 321: (float_extend:TQF (match_operand:HF 1 "general_operand" "r,m")))]
1.1 root 322: ""
323: "*
324: {
1.1.1.2 ! root 325: rtx new_opnds[2];
! 326: new_opnds[0] = gen_rtx (REG, QImode, REGNO(operands[0]) + 2);
! 327: new_opnds[1] = operands[1];
! 328: output_asm_insn(\"xorr r%0,r%0 ;extendhftqf2\",new_opnds);
1.1 root 329: if (which_alternative == 0)
1.1.1.2 ! root 330: return \"dlr r%0,r%1 ; put condition codes back on track\";
1.1 root 331: else
1.1.1.2 ! root 332: return \"dl r%0,%1 ; put condition codes back on track\";
1.1 root 333: } ")
334:
335: ; 1750 TQF-to-HF truncate is a no-op: just leave away the least signif. 16 bits
336: (define_insn "trunctqfhf2"
337: [(set (match_operand:HF 0 "register_operand" "=r,r")
338: (float_truncate:HF
339: (match_operand:TQF 1 "general_operand" "r,m")))]
340: ""
341: "@
342: dlr r%0,r%1 ;trunctqfhf2
343: dl r%0,%1 ;trunctqfhf2 ")
344:
345:
346: ;; Conversion between fixed point and floating point.
347:
348: (define_insn "floatqihf2"
349: [(set (match_operand:HF 0 "register_operand" "=r")
350: (float:HF (match_operand:QI 1 "register_operand" "r")))]
351: ""
352: "flt r%0,r%1")
353:
354: (define_insn "floathitqf2"
355: [(set (match_operand:TQF 0 "register_operand" "=r")
356: (float:TQF (match_operand:HI 1 "register_operand" "r")))]
357: ""
358: "eflt r%0,r%1")
359:
360:
361: ;; Convert floats to ints
362:
363: (define_insn "fix_trunchfqi2"
364: [(set (match_operand:QI 0 "register_operand" "=r")
365: (fix:QI (fix:HF (match_operand:HF 1 "register_operand" "r"))))]
366: ""
367: "fix r%0,r%1")
368:
369: (define_insn "fix_trunctqfhi2"
370: [(set (match_operand:HI 0 "register_operand" "=r")
371: (fix:HI (fix:TQF (match_operand:TQF 1 "register_operand" "r"))))]
372: ""
373: "efix r%0,r%1")
374:
375:
376: ;; Move instructions
377:
378: ;; We can't deal with normal byte-size characters, only with WIDE characters!
379: ;; This may appear as a serious restriction, but it also opens the doors
380: ;; for ISO 10646 :-)
381:
382: ;; 16-bit moves
383:
384: (define_insn "movqi"
1.1.1.2 ! root 385: [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,r,t,r,Q,m,m")
! 386: (match_operand:QI 1 "general_operand" "O,I,J,M,i,r,Q,m,t,r,K"))]
1.1 root 387: ""
388: "@
389: xorr r%0,r%0
390: lisp r%0,%1
391: lisn r%0,%J1
392: lim r%0,%1 ; 'M' constraint
393: lim r%0,%1 ; 'i' constraint
394: lr r%0,r%1
1.1.1.2 ! root 395: lb %Q1
1.1 root 396: l r%0,%1
1.1.1.2 ! root 397: stb %Q0
1.1 root 398: st r%1,%0
399: stc %1,%0 ")
400:
401: ;; 32-bit moves
402:
1.1.1.2 ! root 403: ; Set HIreg to constant
1.1 root 404: (define_insn ""
405: [(set (match_operand:HI 0 "register_operand" "=r")
1.1.1.2 ! root 406: (match_operand:HI 1 "immediate_operand" "i"))]
1.1 root 407: ""
408: "*
409: {
1.1.1.2 ! root 410: rtx new_opnds[2];
1.1 root 411: int val = INTVAL(operands[1]);
412: if (val >= 0)
413: {
414: if (val <= 65535)
415: {
1.1.1.2 ! root 416: new_opnds[0] = gen_rtx(REG,QImode,REGNO(operands[0]));
! 417: new_opnds[1] = operands[1];
! 418: output_asm_insn(\"xorr r%0,r%0 ;movhi cst->reg\",new_opnds);
! 419: REGNO(new_opnds[0]) += 1;
1.1 root 420: if (val == 0)
1.1.1.2 ! root 421: output_asm_insn(\"xorr r%0,r%0\",new_opnds);
1.1 root 422: else if (val <= 16)
1.1.1.2 ! root 423: output_asm_insn(\"lisp r%0,%1\",new_opnds);
1.1 root 424: else
1.1.1.2 ! root 425: output_asm_insn(\"lim r%0,%1\",new_opnds);
! 426: return \";\";
1.1 root 427: }
428: }
429: else if (val >= -16)
430: return \"lisn r%0,%J1\;dsra r%0,16 ;movhi cst\";
1.1.1.2 ! root 431: new_opnds[0] = gen_rtx(REG, QImode, REGNO(operands[0]));
! 432: new_opnds[1] = gen_rtx(CONST_INT,VOIDmode,(INTVAL(operands[1])) >> 16);
! 433: output_asm_insn(\"lim r%0,%1 ;movhi cst->reg\",new_opnds);
! 434: INTVAL(new_opnds[1]) = val & 0xFFFF;
! 435: REGNO(new_opnds[0]) += 1;
! 436: output_asm_insn(\"lim r%0,%1\",new_opnds);
! 437: return \";\";
1.1 root 438: }
439: ")
440:
441: (define_insn "movhi"
1.1.1.2 ! root 442: [(set (match_operand:HI 0 "general_operand" "=r,z,r,Q,m")
! 443: (match_operand:HI 1 "general_operand" "r,Q,m,z,r"))]
1.1 root 444: ""
445: "@
1.1.1.2 ! root 446: dlr r%0,r%1
! 447: dlb %Q1
! 448: dl r%0,%1
! 449: dstb %Q0
! 450: dst r%1,%0 ")
1.1 root 451:
452:
453: ;; Single-Float moves are *same* as HImode moves:
454:
455: ;(define_insn "movhf"
456: ; [(set (match_operand:HF 0 "general_operand" "=r,r,r,m")
457: ; (match_operand:HF 1 "general_operand" "F,r,m,r"))]
458: ; ""
459: ; "@
460: ; %D1\;dl r%0,%F1
461: ; dlr r%0,r%1
462: ; dl r%0,%1
463: ; dst r%1,%0 ")
464:
465: (define_insn "movhf"
1.1.1.2 ! root 466: [(set (match_operand:HF 0 "general_operand" "=r,z,r,Q,m")
! 467: (match_operand:HF 1 "general_operand" "r,Q,m,z,r"))]
1.1 root 468: ""
469: "@
1.1.1.2 ! root 470: dlr r%0,r%1
! 471: dlb %Q1
! 472: dl r%0,%1
! 473: dstb %Q0
! 474: dst r%1,%0 ")
1.1 root 475:
476:
477: ;; Longfloat moves
478:
479: ;(define_insn "movtqf"
480: ; [(set (match_operand:TQF 0 "general_operand" "=r,r,r,m")
481: ; (match_operand:TQF 1 "general_operand" "F,r,m,r"))]
482: ; ""
483: ; "@
484: ; %E1\;efl r%0,%G1
485: ; eflr.m %0,%1
486: ; efl r%0,%1
487: ; efst r%1,%0 ")
488:
489: (define_insn "movtqf"
490: [(set (match_operand:TQF 0 "general_operand" "=r,r,m")
491: (match_operand:TQF 1 "general_operand" "r,m,r"))]
492: ""
493: "@
494: eflr.m %0,%1
495: efl r%0,%1
496: efst r%1,%0 ")
497:
498:
499: ;; add instructions
500:
501: ;; single integer
502:
503: (define_insn "addqi3"
1.1.1.2 ! root 504: [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,t,r,m,m")
! 505: (plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0,0,0,0,0")
! 506: (match_operand:QI 2 "general_operand" "I,J,i,r,Q,m,I,J")))]
1.1 root 507: ""
508: "*
509: switch (which_alternative)
510: {
511: case 0:
512: return \"aisp r%0,%2\";
513: case 1:
514: return \"sisp r%0,%J2\";
515: case 2:
516: if (INTVAL(operands[2]) < 0)
517: return \"sim r%0,%J2\";
518: else
519: return \"aim r%0,%2\";
520: case 3:
521: return \"ar r%0,r%2\";
522: case 4:
1.1.1.2 ! root 523: return \"ab %Q2\";
1.1 root 524: case 5:
1.1.1.2 ! root 525: return \"a r%0,%2\";
1.1 root 526: case 6:
1.1.1.2 ! root 527: return \"incm %2,%0\";
! 528: case 7:
1.1 root 529: return \"decm %J2,%0\";
530: } ")
531:
532: ;; double integer
533: (define_insn "addhi3"
534: [(set (match_operand:HI 0 "register_operand" "=r,r")
535: (plus:HI (match_operand:HI 1 "register_operand" "%0,0")
536: (match_operand:HI 2 "general_operand" "r,m")))]
537: ""
538: "@
539: dar r%0,r%2
540: da r%0,%2 ")
541:
542: (define_insn "addhf3"
1.1.1.2 ! root 543: [(set (match_operand:HF 0 "register_operand" "=r,z,r")
! 544: (plus:HF (match_operand:HF 1 "register_operand" "%0,0,0")
! 545: (match_operand:HF 2 "general_operand" "r,Q,m")))]
1.1 root 546: ""
547: "@
1.1.1.2 ! root 548: far r%0,r%2
! 549: fab %Q2
! 550: fa r%0,%2 ")
1.1 root 551:
552: (define_insn "addtqf3"
553: [(set (match_operand:TQF 0 "register_operand" "=r,r")
554: (plus:TQF (match_operand:TQF 1 "register_operand" "%0,0")
1.1.1.2 ! root 555: (match_operand:TQF 2 "general_operand" "r,m")))]
1.1 root 556: ""
557: "@
1.1.1.2 ! root 558: efar r%0,r%2
! 559: efa r%0,%2 ")
1.1 root 560:
561:
562: ;; subtract instructions
563:
564: ;; single integer
565: (define_insn "subqi3"
1.1.1.2 ! root 566: [(set (match_operand:QI 0 "general_operand" "=r,r,r,t,r,m")
! 567: (minus:QI (match_operand:QI 1 "general_operand" "0,0,0,0,0,0")
! 568: (match_operand:QI 2 "general_operand" "I,i,r,Q,m,I")))]
1.1 root 569: ""
570: "@
571: sisp r%0,%2
572: sim r%0,%2
573: sr r%0,r%2
1.1.1.2 ! root 574: sbb %Q2
1.1 root 575: s r%0,%2
576: decm %2,%0 ")
577:
578: ;; double integer
579: (define_insn "subhi3"
580: [(set (match_operand:HI 0 "register_operand" "=r,r")
581: (minus:HI (match_operand:HI 1 "register_operand" "0,0")
582: (match_operand:HI 2 "general_operand" "r,m")))]
583: ""
584: "@
585: dsr r%0,r%2
586: ds r%0,%2 ")
587:
588: (define_insn "subhf3"
1.1.1.2 ! root 589: [(set (match_operand:HF 0 "register_operand" "=r,z,r")
! 590: (minus:HF (match_operand:HF 1 "register_operand" "0,0,0")
! 591: (match_operand:HF 2 "general_operand" "r,Q,m")))]
1.1 root 592: ""
593: "@
594: fsr r%0,r%2
1.1.1.2 ! root 595: fsb %Q2
1.1 root 596: fs r%0,%2 ")
597:
598: (define_insn "subtqf3"
599: [(set (match_operand:TQF 0 "register_operand" "=r,r")
600: (minus:TQF (match_operand:TQF 1 "register_operand" "0,0")
601: (match_operand:TQF 2 "general_operand" "r,m")))]
602: ""
603: "@
604: efsr r%0,r%2
605: efs r%0,%2 ")
606:
607:
608: ;; multiply instructions
609:
610: (define_insn "mulqi3"
611: [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
612: (mult:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0")
613: (match_operand:QI 2 "general_operand" "I,J,M,r,m")))]
614: ""
615: "@
616: misp r%0,%2
617: misn r%0,%J2
618: msim r%0,%2
619: msr r%0,r%2
620: ms r%0,%2 ")
621:
622:
623: ; 32-bit product
624: (define_insn "mulqihi3"
1.1.1.2 ! root 625: [(set (match_operand:HI 0 "register_operand" "=r,r,t,r")
! 626: (mult:HI (match_operand:QI 1 "register_operand" "%0,0,0,0")
! 627: (match_operand:QI 2 "general_operand" "M,r,Q,m")))]
1.1 root 628: ""
629: "@
630: mim r%0,%1
631: mr r%0,r%2
1.1.1.2 ! root 632: mb %Q2
1.1 root 633: m r%0,%2 ")
634:
635: (define_insn "mulhi3"
636: [(set (match_operand:HI 0 "register_operand" "=r,r")
637: (mult:HI (match_operand:HI 1 "register_operand" "%0,0")
638: (match_operand:HI 2 "general_operand" "r,m")))]
639: ""
640: "@
641: dmr r%0,r%2
642: dm r%0,%2 ")
643:
644: ; not available on 1750: "umulhi3","umulhisi3","umulsi3" (unsigned multiply's)
645:
646: (define_insn "mulhf3"
1.1.1.2 ! root 647: [(set (match_operand:HF 0 "register_operand" "=r,z,r")
! 648: (mult:HF (match_operand:HF 1 "register_operand" "%0,0,0")
! 649: (match_operand:HF 2 "general_operand" "r,Q,m")))]
1.1 root 650: ""
651: "@
652: fmr r%0,r%2
1.1.1.2 ! root 653: fmb %Q2
1.1 root 654: fm r%0,%2 ")
655:
656: (define_insn "multqf3"
657: [(set (match_operand:TQF 0 "register_operand" "=r,r")
658: (mult:TQF (match_operand:TQF 1 "register_operand" "%0,0")
659: (match_operand:TQF 2 "general_operand" "r,m")))]
660: ""
661: "@
662: efmr r%0,r%2
663: efm r%0,%2 ")
664:
665:
666: ;; divide instructions
667: ;; The 1750 16bit integer division instructions deliver a 16-bit
668: ;; quotient and a 16-bit remainder, where the remainder is in the next higher
669: ;; register number above the quotient. For now, we haven't found a way
670: ;; to give the reload pass knowledge of this property. So we make do with
671: ;; whatever registers the allocator wants, and willy-nilly output a pair of
672: ;; register-copy ops when needed. (See mod_regno_adjust() in file aux-output.c)
673: ;; A comment in the description of `divmodM4' suggests that one leave the divM3
674: ;; undefined when there is a divmodM4 available.
675:
676: (define_insn "divmodqi4"
677: [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
678: (div:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0")
679: (match_operand:QI 2 "general_operand" "I,J,M,r,m")))
680: (set (match_operand:QI 3 "register_operand" "=r,r,r,r,r")
681: (mod:QI (match_dup 1) (match_dup 2)))]
682: ""
683: "*
684: {
685: char *istr;
686: switch(which_alternative)
687: {
688: case 0:
689: istr = \"disp\";
690: break;
691: case 1:
1.1.1.2 ! root 692: {
! 693: rtx new_opnds[4];
! 694: new_opnds[0] = operands[0];
! 695: new_opnds[1] = operands[1];
! 696: new_opnds[2] = gen_rtx (CONST_INT, VOIDmode, -INTVAL(operands[2]));
! 697: new_opnds[3] = operands[3];
! 698: istr = \"disn\";
! 699: return (char *)mod_regno_adjust(istr,new_opnds);
! 700: }
1.1 root 701: break;
702: case 2:
703: istr = \"dvim\";
704: break;
705: case 3:
706: istr = \"dvr \";
707: break;
708: case 4:
709: istr = \"dv \";
710: break;
711: }
712: return (char *)mod_regno_adjust(istr,operands);
713: }")
714:
715: ;; Division for other types is straightforward.
716:
717: (define_insn "divhi3"
718: [(set (match_operand:HI 0 "register_operand" "=r,r")
719: (div:HI (match_operand:HI 1 "register_operand" "0,0")
720: (match_operand:HI 2 "general_operand" "r,m")))]
721: ""
722: "@
723: ddr r%0,r%2
724: dd r%0,%2 ")
725:
726: (define_insn "divhf3"
1.1.1.2 ! root 727: [(set (match_operand:HF 0 "register_operand" "=r,z,r")
! 728: (div:HF (match_operand:HF 1 "register_operand" "0,0,0")
! 729: (match_operand:HF 2 "general_operand" "r,Q,m")))]
1.1 root 730: ""
731: "@
732: fdr r%0,r%2
1.1.1.2 ! root 733: fdb %Q2
1.1 root 734: fd r%0,%2 ")
735:
736: (define_insn "divtqf3"
737: [(set (match_operand:TQF 0 "register_operand" "=r,r")
738: (div:TQF (match_operand:TQF 1 "register_operand" "0,0")
739: (match_operand:TQF 2 "general_operand" "r,m")))]
740: ""
741: "@
742: efdr r%0,r%2
743: efd r%0,%2 ")
744:
745:
746: ;; Other arithmetic instructions:
747:
748: ;; Absolute value
749:
750: (define_insn "absqi2"
751: [(set (match_operand:QI 0 "register_operand" "=r")
752: (abs:QI (match_operand:QI 1 "register_operand" "r")))]
753: ""
754: "abs r%0,r%1")
755:
756: (define_insn "abshi2"
757: [(set (match_operand:HI 0 "register_operand" "=r")
758: (abs:HI (match_operand:HI 1 "register_operand" "r")))]
759: ""
760: "dabs r%0,r%1")
761:
762: (define_insn "abshf2"
763: [(set (match_operand:HF 0 "register_operand" "=r")
764: (abs:HF (match_operand:HF 1 "register_operand" "r")))]
765: ""
766: "fabs r%0,r%1")
767:
768:
769: ;; Negation
770:
771: (define_insn "negqi2"
772: [(set (match_operand:QI 0 "register_operand" "=r")
773: (neg:QI (match_operand:QI 1 "register_operand" "r")))]
774: ""
775: "neg r%0,r%1")
776:
777: (define_insn "neghi2"
778: [(set (match_operand:HI 0 "register_operand" "=r")
779: (neg:HI (match_operand:HI 1 "register_operand" "r")))]
780: ""
781: "dneg r%0,r%1")
782:
783: (define_insn "neghf2"
784: [(set (match_operand:HF 0 "register_operand" "=r")
785: (neg:HF (match_operand:HF 1 "register_operand" "r")))]
786: ""
787: "fneg r%0,r%1")
788:
789: ; The 1750A does not have an extended float negate instruction, so simulate.
790: (define_expand "negtqf2"
791: [(set (match_operand:TQF 0 "register_operand" "=&r")
792: (neg:TQF (match_operand:TQF 1 "register_operand" "r")))]
793: ""
794: "
795: emit_insn(gen_rtx(SET,VOIDmode,operands[0],CONST0_RTX(TQFmode)));
796: emit_insn(gen_rtx(SET,VOIDmode,operands[0],
797: gen_rtx(MINUS,TQFmode,operands[0],operands[1])));
798: DONE;
799: ")
800:
801:
802: ;; bit-logical instructions
803:
804: ;; AND
805:
806: (define_insn "andqi3"
1.1.1.2 ! root 807: [(set (match_operand:QI 0 "general_operand" "=r,r,t,r")
! 808: (and:QI (match_operand:QI 1 "general_operand" "%0,0,0,0")
! 809: (match_operand:QI 2 "general_operand" "M,r,Q,m")))]
1.1 root 810: ""
811: "@
812: andm r%0,%2
813: andr r%0,r%2
1.1.1.2 ! root 814: andb %Q2
1.1 root 815: and r%0,%2 ")
816:
817: ; This sets incorrect condition codes. See notice_update_cc()
818: (define_insn "andhi3"
819: [(set (match_operand:HI 0 "register_operand" "=r")
820: (and:HI (match_operand:HI 1 "register_operand" "%0")
821: (match_operand:HI 2 "register_operand" "r")))]
822: ""
823: "danr.m %0,%2")
824:
825: ;; OR
826:
827: (define_insn "iorqi3"
1.1.1.2 ! root 828: [(set (match_operand:QI 0 "general_operand" "=r,r,t,r")
! 829: (ior:QI (match_operand:QI 1 "general_operand" "%0,0,0,0")
! 830: (match_operand:QI 2 "general_operand" "M,r,Q,m")))]
1.1 root 831: ""
832: "@
833: orim r%0,%2
834: orr r%0,r%2
1.1.1.2 ! root 835: orb %Q2
1.1 root 836: or r%0,%2 ")
837:
838: ; This sets incorrect condition codes. See notice_update_cc()
839: (define_insn "iorhi3"
840: [(set (match_operand:HI 0 "register_operand" "=r")
841: (ior:HI (match_operand:HI 1 "register_operand" "%0")
842: (match_operand:HI 2 "register_operand" "r")))]
843: ""
844: "dorr.m %0,%2")
845:
846: ;; XOR
847:
848: (define_insn "xorqi3"
849: [(set (match_operand:QI 0 "register_operand" "=r,r,r")
850: (xor:QI (match_operand:QI 1 "register_operand" "%0,0,0")
851: (match_operand:QI 2 "general_operand" "M,r,m")))]
852: ""
853: "@
854: xorm r%0,%2
855: xorr r%0,r%2
856: xor r%0,%2 ")
857:
858: ; This sets incorrect condition codes. See notice_update_cc()
859: (define_insn "xorhi3"
860: [(set (match_operand:HI 0 "register_operand" "=r")
861: (xor:HI (match_operand:HI 1 "register_operand" "%0")
862: (match_operand:HI 2 "register_operand" "r")))]
863: ""
864: "dxrr.m %0,%2")
865:
866: ;; NAND
867:
868: (define_insn ""
869: [(set (match_operand:QI 0 "register_operand" "=r,r,r")
870: (ior:QI (not:QI (match_operand:QI 1 "register_operand" "%0,0,0"))
871: (not:QI (match_operand:QI 2 "general_operand" "M,r,m"))))]
872: ""
873: "@
874: nim r%0,%2
875: nr r%0,r%2
876: n r%0,%2 ")
877:
878: ; This sets incorrect condition codes. See notice_update_cc()
879: (define_insn ""
880: [(set (match_operand:HI 0 "register_operand" "=r")
881: (ior:HI (not:HI (match_operand:HI 1 "register_operand" "%0"))
882: (not:HI (match_operand:HI 2 "register_operand" "r"))))]
883: ""
884: "dnr.m %0,%2")
885:
886: ;; NOT
887:
888: (define_insn "one_cmplqi2"
889: [(set (match_operand:QI 0 "register_operand" "=r")
890: (not:QI (match_operand:QI 1 "register_operand" "0")))]
891: ""
892: "nr r%0,r%0")
893:
894: ; This sets incorrect condition codes. See notice_update_cc()
895: (define_insn "one_cmplhi2"
896: [(set (match_operand:HI 0 "register_operand" "=r")
897: (not:HI (match_operand:HI 1 "register_operand" "0")))]
898: ""
899: "dnr.m %0,%0")
900:
901:
902: ;; Shift instructions
903:
904: ; (What to the 1750 is logical-shift-left, GCC likes to call "arithmetic")
905: (define_insn "ashlqi3"
1.1.1.2 ! root 906: [(set (match_operand:QI 0 "register_operand" "=r,r")
! 907: (ashift:QI (match_operand:QI 1 "register_operand" "0,0")
! 908: (match_operand:QI 2 "nonmemory_operand" "I,r")))]
1.1 root 909: ""
910: "@
911: sll r%0,%2
912: slr r%0,r%2 ")
913:
914: (define_insn "ashlhi3"
915: [(set (match_operand:HI 0 "register_operand" "=r,r")
916: (ashift:HI (match_operand:HI 1 "register_operand" "0,0")
1.1.1.2 ! root 917: (match_operand:QI 2 "nonmemory_operand" "L,r")))]
1.1 root 918: "" ; the 'L' constraint is a slight imprecise...
1.1.1.2 ! root 919: "*
! 920: if (which_alternative == 1)
! 921: return \"dslr r%0,r%2\";
! 922: else if (INTVAL(operands[2]) <= 16)
! 923: return \"dsll r%0,%2\";
! 924: else
! 925: {
! 926: rtx new_opnds[2];
! 927: new_opnds[0] = gen_rtx (REG, QImode, REGNO(operands[0]));
! 928: new_opnds[1] = gen_rtx (REG, QImode, REGNO(operands[0]) + 1);
! 929: output_asm_insn(\"lr r%0,r%1 ; ashlhi3 shiftcount > 16\",new_opnds);
! 930: new_opnds[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL(operands[2]) - 16);
! 931: output_asm_insn(\"sll r%0,%1\",new_opnds);
! 932: return \";\";
! 933: } ")
! 934:
! 935:
! 936: ;; Right shift by a variable shiftcount works by negating the shift count,
! 937: ;; then emitting a right shift with the shift count negated. This means
! 938: ;; that all actual shift counts in the RTL will be positive. This
! 939: ;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
! 940: ;; which isn't valid.
! 941: (define_expand "lshrqi3"
! 942: [(set (match_operand:QI 0 "general_operand" "=r")
! 943: (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
! 944: (match_operand:QI 2 "nonmemory_operand" "g")))]
! 945: ""
! 946: "
! 947: {
! 948: if (GET_CODE (operands[2]) != CONST_INT)
! 949: operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
! 950: }")
1.1 root 951:
1.1.1.2 ! root 952: (define_insn ""
! 953: [(set (match_operand:QI 0 "register_operand" "=r")
! 954: (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
! 955: (match_operand:QI 2 "immediate_operand" "I")))]
1.1 root 956: ""
1.1.1.2 ! root 957: "srl r%0,%2")
1.1 root 958:
1.1.1.2 ! root 959: (define_insn ""
! 960: [(set (match_operand:QI 0 "register_operand" "=r")
! 961: (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
! 962: (neg:QI (match_operand:QI 2 "register_operand" "r"))))]
! 963: ""
! 964: "slr r%0,r%2 ")
1.1 root 965:
1.1.1.2 ! root 966: ;; Same thing for HImode.
! 967:
! 968: (define_expand "lshrhi3"
! 969: [(set (match_operand:HI 0 "register_operand" "=r")
! 970: (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
! 971: (match_operand:QI 2 "nonmemory_operand" "g")))]
1.1 root 972: ""
1.1.1.2 ! root 973: "
! 974: {
! 975: if (GET_CODE (operands[2]) != CONST_INT)
! 976: operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
! 977: }")
1.1 root 978:
1.1.1.2 ! root 979: (define_insn ""
! 980: [(set (match_operand:HI 0 "register_operand" "=r")
! 981: (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
! 982: (match_operand:QI 2 "immediate_operand" "L")))]
1.1 root 983: ""
1.1.1.2 ! root 984: "*
! 985: {
! 986: rtx new_opnds[2];
! 987: int amount = INTVAL(operands[2]);
! 988: if (amount <= 16)
! 989: return \"dsrl r%0,%2\";
! 990: output_asm_insn(\"dsrl r%0,16 ; lshrhi3 shiftcount > 16\",operands);
! 991: new_opnds[0] = gen_rtx (REG, QImode, REGNO(operands[0]) + 1);
! 992: new_opnds[1] = gen_rtx (CONST_INT, VOIDmode, amount - 16);
! 993: output_asm_insn(\"srl r%0,%1\",new_opnds);
! 994: return \";\";
! 995: } ")
! 996:
! 997: (define_insn ""
! 998: [(set (match_operand:HI 0 "register_operand" "=r")
! 999: (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
! 1000: (neg:QI (match_operand:QI 2 "register_operand" "r"))))]
! 1001: ""
! 1002: "dslr r%0,r%2 ")
! 1003:
! 1004: ;; Same applies for arithmetic shift right.
! 1005: (define_expand "ashrqi3"
! 1006: [(set (match_operand:QI 0 "general_operand" "=r")
! 1007: (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
! 1008: (match_operand:QI 2 "nonmemory_operand" "g")))]
! 1009: ""
! 1010: "
! 1011: {
! 1012: if (GET_CODE (operands[2]) != CONST_INT)
! 1013: operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
! 1014: }")
! 1015:
! 1016: (define_insn ""
! 1017: [(set (match_operand:QI 0 "register_operand" "=r")
! 1018: (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
! 1019: (match_operand:QI 2 "immediate_operand" "I")))]
! 1020: ""
! 1021: "sra r%0,%2")
! 1022:
! 1023: (define_insn ""
! 1024: [(set (match_operand:QI 0 "register_operand" "=r")
! 1025: (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
! 1026: (neg:QI (match_operand:QI 2 "register_operand" "r"))))]
! 1027: ""
! 1028: "sar r%0,r%2 ")
! 1029:
! 1030: ;; HImode arithmetic shift right.
! 1031: (define_expand "ashrhi3"
! 1032: [(set (match_operand:HI 0 "general_operand" "=r")
! 1033: (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
! 1034: (match_operand:QI 2 "nonmemory_operand" "g")))]
! 1035: ""
! 1036: "
! 1037: {
! 1038: if (GET_CODE (operands[2]) != CONST_INT)
! 1039: operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
! 1040: }")
! 1041:
! 1042: (define_insn ""
! 1043: [(set (match_operand:HI 0 "register_operand" "=r")
! 1044: (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
! 1045: (match_operand:QI 2 "immediate_operand" "L")))]
! 1046: ""
! 1047: "*
! 1048: {
! 1049: rtx new_opnds[2];
! 1050: int amount = INTVAL(operands[2]);
! 1051: if (amount <= 16)
! 1052: return \"dsra r%0,%2\";
! 1053: output_asm_insn(\"dsra r%0,16 ; ashrhi3 shiftcount > 16\",operands);
! 1054: new_opnds[0] = gen_rtx (REG, QImode, REGNO(operands[0]) + 1);
! 1055: new_opnds[1] = gen_rtx (CONST_INT, VOIDmode, amount - 16);
! 1056: output_asm_insn(\"sra r%0,%1\",new_opnds);
! 1057: return \";\";
! 1058: } ")
! 1059:
! 1060: (define_insn ""
! 1061: [(set (match_operand:HI 0 "register_operand" "=r")
! 1062: (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
! 1063: (neg:QI (match_operand:QI 2 "register_operand" "r"))))]
! 1064: ""
! 1065: "dsar r%0,r%2 ")
1.1 root 1066:
1067:
1068: ;; rotate instructions
1069:
1070: (define_insn "rotlqi3"
1071: [(set (match_operand:QI 0 "register_operand" "=r,r")
1072: (rotate:QI (match_operand:QI 1 "register_operand" "0,0")
1.1.1.2 ! root 1073: (match_operand:QI 2 "nonmemory_operand" "I,r")))]
1.1 root 1074: ""
1075: "@
1076: slc r%0,%2
1077: scr r%0,r%2 ")
1078:
1079: (define_insn "rotlhi3"
1080: [(set (match_operand:HI 0 "register_operand" "=r,r")
1081: (rotate:HI (match_operand:HI 1 "register_operand" "0,0")
1.1.1.2 ! root 1082: (match_operand:QI 2 "nonmemory_operand" "I,r")))]
1.1 root 1083: ""
1084: "@
1085: dslc r%0,%2
1086: dscr r%0,r%2 ")
1087:
1088: (define_insn "rotrqi3"
1.1.1.2 ! root 1089: [(set (match_operand:QI 0 "register_operand" "=r")
! 1090: (rotatert:QI (match_operand:QI 1 "register_operand" "0")
! 1091: (match_operand:QI 2 "register_operand" "r")))]
1.1 root 1092: ""
1.1.1.2 ! root 1093: "neg r%2,r%2\;scr r%0,r%2 ")
1.1 root 1094:
1095: (define_insn "rotrhi3"
1.1.1.2 ! root 1096: [(set (match_operand:HI 0 "register_operand" "=r")
! 1097: (rotatert:HI (match_operand:HI 1 "register_operand" "0")
! 1098: (match_operand:QI 2 "nonmemory_operand" "r")))]
1.1 root 1099: ""
1.1.1.2 ! root 1100: "neg r%2,r%2\;dscr r%0,r%2 ")
1.1 root 1101:
1102:
1103:
1104: ;; Special cases of bit-field insns which we should
1105: ;; recognize in preference to the general case.
1106: ;; These handle aligned 8-bit and 16-bit fields,
1107: ;; which can usually be done with move instructions.
1108: ; 1750: t.b.d.
1109: ;********************
1110:
1111: ;; Bit field instructions, general cases.
1112: ;; "o,d" constraint causes a nonoffsetable memref to match the "o"
1113: ;; so that its address is reloaded.
1114:
1115: ;; (define_insn "extv" ...
1116:
1117: ;; (define_insn "extzv" ...
1118:
1119: ;; (define_insn "insv" ...
1120:
1121: ;; Now recognize bit field insns that operate on registers
1122: ;; (or at least were intended to do so).
1123: ;[unnamed only]
1124:
1125: ;; Special patterns for optimizing bit-field instructions.
1126: ;**************************************
1127:
1128: ; cc status test ops n.a. on 1750 ......... e.g. "sleu" on 68k:
1129: ; [(set (match_operand:QI 0 "general_operand" "=d")
1130: ; (leu (cc0) (const_int 0)))]
1131: ; ""
1132: ; "* cc_status = cc_prev_status;
1133: ; return \"sls %0\"; ")
1134:
1135:
1136: ;; Basic conditional jump instructions.
1137:
1138: (define_insn "beq"
1139: [(set (pc)
1140: (if_then_else (eq (cc0)
1141: (const_int 0))
1142: (label_ref (match_operand 0 "" ""))
1143: (pc)))]
1144: ""
1145: "* return (char *)branch_or_jump(\"ez\",CODE_LABEL_NUMBER(operands[0]));
1146: ")
1147:
1148: (define_insn "bne"
1149: [(set (pc)
1150: (if_then_else (ne (cc0)
1151: (const_int 0))
1152: (label_ref (match_operand 0 "" ""))
1153: (pc)))]
1154: ""
1155: "* return (char *)branch_or_jump(\"nz\",CODE_LABEL_NUMBER(operands[0]));
1156: ")
1157:
1158: (define_insn "bgt"
1159: [(set (pc)
1160: (if_then_else (gt (cc0)
1161: (const_int 0))
1162: (label_ref (match_operand 0 "" ""))
1163: (pc)))]
1164: ""
1165: "* return (char *)branch_or_jump(\"gt\",CODE_LABEL_NUMBER(operands[0]));
1166: ")
1167:
1168: (define_insn "blt"
1169: [(set (pc)
1170: (if_then_else (lt (cc0)
1171: (const_int 0))
1172: (label_ref (match_operand 0 "" ""))
1173: (pc)))]
1174: ""
1175: "* return (char *)branch_or_jump(\"lt\",CODE_LABEL_NUMBER(operands[0]));
1176: ")
1177:
1178: (define_insn "bge"
1179: [(set (pc)
1180: (if_then_else (ge (cc0)
1181: (const_int 0))
1182: (label_ref (match_operand 0 "" ""))
1183: (pc)))]
1184: ""
1185: "* return (char *)branch_or_jump(\"ge\",CODE_LABEL_NUMBER(operands[0]));
1186: ")
1187:
1188: (define_insn "ble"
1189: [(set (pc)
1190: (if_then_else (le (cc0)
1191: (const_int 0))
1192: (label_ref (match_operand 0 "" ""))
1193: (pc)))]
1194: ""
1195: "* return (char *)branch_or_jump(\"le\",CODE_LABEL_NUMBER(operands[0]));
1196: ")
1197:
1198:
1199: ; no unsigned branches available on 1750. But GCC still needs them, so faking:
1200:
1201: (define_insn "bgtu"
1202: [(set (pc)
1203: (if_then_else (gtu (cc0)
1204: (const_int 0))
1205: (label_ref (match_operand 0 "" ""))
1206: (pc)))]
1207: ""
1208: "jc gt,%l0 ; Warning: this should be an *unsigned* test!")
1209:
1210: (define_insn "bltu"
1211: [(set (pc)
1212: (if_then_else (ltu (cc0)
1213: (const_int 0))
1214: (label_ref (match_operand 0 "" ""))
1215: (pc)))]
1216: ""
1217: "jc lt,%l0 ; Warning: this should be an *unsigned* test!")
1218:
1219: (define_insn "bgeu"
1220: [(set (pc)
1221: (if_then_else (geu (cc0)
1222: (const_int 0))
1223: (label_ref (match_operand 0 "" ""))
1224: (pc)))]
1225: ""
1226: "jc ge,%l0 ; Warning: this should be an *unsigned* test!")
1227:
1228: (define_insn "bleu"
1229: [(set (pc)
1230: (if_then_else (leu (cc0)
1231: (const_int 0))
1232: (label_ref (match_operand 0 "" ""))
1233: (pc)))]
1234: ""
1235: "jc le,%l0 ; Warning: this should be an *unsigned* test!")
1236:
1237:
1238: ;; Negated conditional jump instructions.
1239:
1240: (define_insn ""
1241: [(set (pc)
1242: (if_then_else (eq (cc0)
1243: (const_int 0))
1244: (pc)
1245: (label_ref (match_operand 0 "" ""))))]
1246: ""
1247: "* return (char *)branch_or_jump(\"nz\",CODE_LABEL_NUMBER(operands[0]));
1248: ")
1249:
1250: (define_insn ""
1251: [(set (pc)
1252: (if_then_else (ne (cc0)
1253: (const_int 0))
1254: (pc)
1255: (label_ref (match_operand 0 "" ""))))]
1256: ""
1257: "* return (char *)branch_or_jump(\"ez\",CODE_LABEL_NUMBER(operands[0]));
1258: ")
1259:
1260: (define_insn ""
1261: [(set (pc)
1262: (if_then_else (gt (cc0)
1263: (const_int 0))
1264: (pc)
1265: (label_ref (match_operand 0 "" ""))))]
1266: ""
1267: "* return (char *)branch_or_jump(\"le\",CODE_LABEL_NUMBER(operands[0]));
1268: ")
1269:
1270: (define_insn ""
1271: [(set (pc)
1272: (if_then_else (lt (cc0)
1273: (const_int 0))
1274: (pc)
1275: (label_ref (match_operand 0 "" ""))))]
1276: ""
1277: "* return (char *)branch_or_jump(\"ge\",CODE_LABEL_NUMBER(operands[0]));
1278: ")
1279:
1280: (define_insn ""
1281: [(set (pc)
1282: (if_then_else (ge (cc0)
1283: (const_int 0))
1284: (pc)
1285: (label_ref (match_operand 0 "" ""))))]
1286: ""
1287: "* return (char *)branch_or_jump(\"lt\",CODE_LABEL_NUMBER(operands[0]));
1288: ")
1289:
1290: (define_insn ""
1291: [(set (pc)
1292: (if_then_else (le (cc0)
1293: (const_int 0))
1294: (pc)
1295: (label_ref (match_operand 0 "" ""))))]
1296: ""
1297: "* return (char *)branch_or_jump(\"gt\",CODE_LABEL_NUMBER(operands[0]));
1298: ")
1299:
1300:
1301: ;; Negated unsigned conditional jump instructions (faked for 1750).
1302:
1303: (define_insn ""
1304: [(set (pc)
1305: (if_then_else (gtu (cc0)
1306: (const_int 0))
1307: (pc)
1308: (label_ref (match_operand 0 "" ""))))]
1309: ""
1310: "jc le,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
1311:
1312: (define_insn ""
1313: [(set (pc)
1314: (if_then_else (ltu (cc0)
1315: (const_int 0))
1316: (pc)
1317: (label_ref (match_operand 0 "" ""))))]
1318: ""
1319: "jc ge,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
1320:
1321: (define_insn ""
1322: [(set (pc)
1323: (if_then_else (geu (cc0)
1324: (const_int 0))
1325: (pc)
1326: (label_ref (match_operand 0 "" ""))))]
1327: ""
1328: "jc lt,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
1329:
1330: (define_insn ""
1331: [(set (pc)
1332: (if_then_else (leu (cc0)
1333: (const_int 0))
1334: (pc)
1335: (label_ref (match_operand 0 "" ""))))]
1336: ""
1337: "jc gt,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
1338:
1339: ;; Tablejump
1340: ;; 1750 note: CASE_VECTOR_PC_RELATIVE is not defined
1341: (define_insn "tablejump"
1342: [(set (pc)
1343: (match_operand:QI 0 "register_operand" "b"))
1344: (use (label_ref (match_operand 1 "" "")))]
1345: ""
1346: "jc 15,0,r%0 ; tablejump label_ref=%1")
1347:
1348:
1349: ;; Unconditional jump
1350: (define_insn "jump"
1351: [(set (pc)
1352: (label_ref (match_operand 0 "" "")))]
1353: ""
1.1.1.2 ! root 1354: "jc 15,%0")
1.1 root 1355:
1356: ;; Call subroutine, returning value in operand 0
1357: ;; (which must be a hard register).
1358: (define_insn "call_value"
1359: [(set (match_operand 0 "register_operand" "r")
1360: (call (match_operand:QI 1 "memory_operand" "m")
1361: (match_operand:QI 2 "general_operand" "g")))]
1362: ;; Operand 2 not really used for 1750.
1363: ""
1364: "sjs r15,%1 ; return value in R0")
1365:
1366: ;; Call subroutine with no return value.
1367:
1368: ;; Operand 1 not really used in MIL-STD-1750.
1369: (define_insn ""
1370: [(call (match_operand:QI 0 "memory_operand" "mp")
1371: (match_operand:QI 1 "general_operand" ""))]
1372: ""
1373: "sjs r15,%0 ; no return value")
1374:
1375: ;;;;;;;;;;;; 1750: NOT READY YET.
1376: (define_insn "call"
1377: [(call (match_operand:QI 0 "" "")
1378: (match_operand:QI 1 "" ""))]
1379: ""
1380: "ANYCALL %0")
1381:
1382:
1383: ; (define_insn "return"
1384: ; [(return)]
1385: ; ""
1386: ; "*
1387: ; {
1388: ; rtx oprnd = gen_rtx(CONST_INT,VOIDmode,get_frame_size());
1389: ; output_asm_insn(\"ret.m %0\",&oprnd);
1390: ; return \"\;\";
1391: ; } ")
1392:
1393: (define_insn "indirect_jump"
1394: [(set (pc) (match_operand:QI 0 "address_operand" "p"))]
1395: ""
1396: "jci 15,%0")
1397:
1398: (define_insn "nop"
1399: [(const_int 0)]
1400: ""
1401: "nop")
1402:
1403:
1404: ;; Subtract One and Jump (if non-zero)
1405: (define_peephole
1406: [(set (match_operand:QI 0 "register_operand" "=r")
1407: (plus:QI (match_operand:QI 1 "register_operand" "%0")
1408: (match_operand:QI 2 "immediate_operand" "J")))
1409: (set (cc0) (match_dup 0))
1410: (set (pc)
1411: (if_then_else (ne (cc0) (const_int 0))
1412: (label_ref (match_operand 3 "" ""))
1413: (pc)))
1414: ]
1415: "INTVAL(operands[2]) == -1"
1416: "soj r%0,%3")
1417:
1.1.1.2 ! root 1418: ;; Combine a Load Register with subsequent increment/decrement into a LIM
! 1419: (define_peephole
! 1420: [(set (match_operand:QI 0 "register_operand" "=r")
! 1421: (match_operand:QI 1 "register_operand" "b"))
! 1422: (set (match_dup 0)
! 1423: (plus:QI (match_dup 0)
! 1424: (match_operand:QI 2 "immediate_operand" "i")))]
! 1425: "REGNO(operands[1]) > 0"
! 1426: "lim r%0,%2,r%1 ; LR,inc/dec peephole")
1.1 root 1427:
1.1.1.2 ! root 1428: ;; Eliminate the redundant load in a store/load sequence
! 1429: (define_peephole
! 1430: [(set (mem:QI (plus:QI (match_operand:QI 0 "register_operand" "r")
! 1431: (match_operand:QI 1 "immediate_operand" "i")))
! 1432: (match_operand:QI 2 "register_operand" "r"))
! 1433: (set (match_operand:QI 3 "register_operand" "=r")
! 1434: (mem:QI (plus:QI (match_dup 0)
! 1435: (match_dup 1))))
! 1436: ]
! 1437: "REGNO(operands[2]) == REGNO(operands[3])"
! 1438: "st r%2,%1,r%0 ; eliminated previous redundant load")
! 1439:
! 1440: ;;;End.
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