--- gcc/config/a29k.h	2018/04/24 17:51:34	1.1.1.1
+++ gcc/config/a29k.h	2018/04/24 17:59:12	1.1.1.3
@@ -99,7 +99,7 @@ extern int target_flags;
 
 #define TARGET_DEFAULT 3
 
-/* Define this to change the optimizations peformed by default.  */
+/* Define this to change the optimizations performed by default.  */
 
 #define OPTIMIZATION_OPTIONS(LEVEL)	\
 {					\
@@ -141,7 +141,7 @@ extern int target_flags;
    for them.  Might as well be consistent with bytes. */
 #define WORDS_BIG_ENDIAN 1
 
-/* number of bits in an addressible storage unit */
+/* number of bits in an addressable storage unit */
 #define BITS_PER_UNIT 8
 
 /* Width in bits of a "word", which is the contents of a machine register.
@@ -172,6 +172,9 @@ extern int target_flags;
 /* Every structure's size must be a multiple of this.  */
 #define STRUCTURE_SIZE_BOUNDARY 8
 
+/* A bitfield declared as `int' forces `int' alignment for the struct.  */
+#define PCC_BITFIELD_TYPE_MATTERS 1
+
 /* No data type wants to be aligned rounder than this.  */
 #define BIGGEST_ALIGNMENT 32
 
@@ -186,14 +189,14 @@ extern int target_flags;
    && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
    && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
 
-/* Define this if move instructions will actually fail to work
+/* Set this non-zero if move instructions will actually fail to work
    when given unaligned data.  */
-/* #define STRICT_ALIGNMENT */
+#define STRICT_ALIGNMENT 0
 
-/* Define this if unaligned move instructions are extremely slow.
+/* Set this non-zero if unaligned move instructions are extremely slow.
 
    On the 29k, they trap.  */
-#define SLOW_UNALIGNED_ACCESS
+#define SLOW_UNALIGNED_ACCESS 1
 
 /* Standard register usage.  */
 
@@ -383,6 +386,10 @@ extern int target_flags;
    registers cannot hold floating-point values and the accumulators cannot
    hold integer values.
 
+   DImode and larger values should start at an even register just like
+   DFmode values, even though the instruction set doesn't require it, in order
+   to prevent reload from aborting due to a modes_equiv_for_class_p failure.
+
    (I'd like to use the "?:" syntax to make this more readable, but Sun's
    compiler doesn't seem to accept it.)  */
 #define HARD_REGNO_MODE_OK(REGNO, MODE)  				\
@@ -393,8 +400,7 @@ extern int target_flags;
        && GET_MODE_CLASS (MODE) != MODE_FLOAT				\
        && GET_MODE_CLASS (MODE) != MODE_COMPLEX_FLOAT)			\
    || ((REGNO) < R_BP							\
-       && ((((REGNO) & 1) == 0) || GET_MODE_CLASS (MODE) == MODE_INT	\
-	   || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT			\
+       && ((((REGNO) & 1) == 0)						\
 	   || GET_MODE_UNIT_SIZE (MODE) <= UNITS_PER_WORD)))
 
 /* Value is 1 if it is a good idea to tie two pseudo registers
@@ -1218,7 +1224,7 @@ extern char *a29k_function_name;
    instruction are those involving floating-point or address.  So 
    only these need be expensive.  */
 
-#define CONST_COSTS(RTX,CODE) \
+#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
   case CONST_INT:						\
     return 0;							\
   case CONST:							\
@@ -1236,7 +1242,7 @@ extern char *a29k_function_name;
 
    The multiply cost depends on whether this is a 29050 or not.  */
 
-#define RTX_COSTS(X,CODE)				\
+#define RTX_COSTS(X,CODE,OUTER_CODE)			\
   case MULT:						\
     return TARGET_29050 ? COSTS_N_INSNS (2) : COSTS_N_INSNS (40);  \
   case DIV:						\
@@ -1271,6 +1277,9 @@ extern char *a29k_function_name;
 
 #define ASM_APP_OFF ""
 
+/* The next few macros don't have tabs on most machines, but
+   at least one 29K assembler wants them.  */
+
 /* Output before instructions.  */
 
 #define TEXT_SECTION_ASM_OP "\t.text"
@@ -1523,9 +1532,9 @@ extern int a29k_debug_reg_map[];
   {"const_16__operand", {CONST_INT, ASHIFT}},			\
   {"const_24__operand", {CONST_INT, ASHIFT}},			\
   {"float_const_operand", {CONST_DOUBLE}},			\
-  {"gen_reg_operand", {SUBREG, REG}},				\
-  {"gen_reg_or_float_constant_operand", {SUBREG, REG, CONST_DOUBLE}}, \
-  {"gen_reg_or_integer_constant_operand", {SUBREG, REG,		\
+  {"gpc_reg_operand", {SUBREG, REG}},				\
+  {"gpc_reg_or_float_constant_operand", {SUBREG, REG, CONST_DOUBLE}}, \
+  {"gpc_reg_or_integer_constant_operand", {SUBREG, REG,		\
 					   CONST_INT, CONST_DOUBLE}}, \
   {"spec_reg_operand", {REG}},					\
   {"accum_reg_operand", {REG}},					\