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1.1 root 1: /* Definitions of target machine for GNU compiler, for AMD Am29000 CPU.
2: Copyright (C) 1988, 1990, 1991 Free Software Foundation, Inc.
3: Contributed by Richard Kenner ([email protected])
4:
5: This file is part of GNU CC.
6:
7: GNU CC is free software; you can redistribute it and/or modify
8: it under the terms of the GNU General Public License as published by
9: the Free Software Foundation; either version 2, or (at your option)
10: any later version.
11:
12: GNU CC is distributed in the hope that it will be useful,
13: but WITHOUT ANY WARRANTY; without even the implied warranty of
14: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: GNU General Public License for more details.
16:
17: You should have received a copy of the GNU General Public License
18: along with GNU CC; see the file COPYING. If not, write to
19: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
20:
21:
22: /* Names to predefine in the preprocessor for this target machine. */
23:
24: #define CPP_PREDEFINES "-D_AM29K -D_AM29000 -D_EPI"
25:
26: /* Print subsidiary information on the compiler version in use. */
27: #define TARGET_VERSION
28:
29: /* Pass -w to assembler. */
30: #define ASM_SPEC "-w"
31:
32: /* Run-time compilation parameters selecting different hardware subsets. */
33:
34: extern int target_flags;
35:
36: /* Macro to define tables used to set the flags.
37: This is a list in braces of pairs in braces,
38: each pair being { "NAME", VALUE }
39: where VALUE is the bits to set or minus the bits to clear.
40: An empty string NAME is used to identify the default VALUE. */
41:
42: /* This means that the DW bit will be enabled, to allow direct loads
43: of bytes. */
44:
45: #define TARGET_DW_ENABLE (target_flags & 1)
46:
47: /* This means that the external hardware does supports byte writes. */
48:
49: #define TARGET_BYTE_WRITES (target_flags & 2)
50:
51: /* This means that a "small memory model" has been selected where all
52: function addresses are known to be within 256K. This allows CALL to be
53: used. */
54:
55: #define TARGET_SMALL_MEMORY (target_flags & 4)
56:
57: /* This means that we are compiling for a 29050. */
58:
59: #define TARGET_29050 (target_flags & 8)
60:
61: /* This means that we are compiling for the kernel which means that we use
62: gr64-gr95 instead of gr96-126. */
63:
64: #define TARGET_KERNEL_REGISTERS (target_flags & 16)
65:
66: /* This means that a call to "__msp_check" should be inserted after each stack
67: adjustment to check for stack overflow. */
68:
69: #define TARGET_STACK_CHECK (target_flags & 32)
70:
71: /* This handles 29k processors which cannot handle the separation
72: of a mtsrim insns and a storem insn (most 29000 chips to date, but
73: not the 29050. */
74:
75: #define TARGET_NO_STOREM_BUG (target_flags & 64)
76:
77: /* This forces the compiler not to use incoming argument registers except
78: for copying out arguments. It helps detect problems when a function is
79: called with fewer arguments than it is declared with. */
80:
81: #define TARGET_NO_REUSE_ARGS (target_flags & 128)
82:
83: #define TARGET_SWITCHES \
84: { {"dw", 1}, \
85: {"ndw", -1}, \
86: {"bw", 2}, \
87: {"nbw", - (1|2)}, \
88: {"small", 4}, \
89: {"large", -4}, \
90: {"29050", 8+64}, \
91: {"29000", -8}, \
92: {"kernel-registers", 16}, \
93: {"user-registers", -16}, \
94: {"stack-check", 32}, \
95: {"no-storem-bug", 64}, \
96: {"reuse-arg-regs", -128}, \
97: {"no-reuse-arg-regs", 128}, \
98: {"", TARGET_DEFAULT}}
99:
100: #define TARGET_DEFAULT 3
101:
1.1.1.2 root 102: /* Define this to change the optimizations performed by default. */
1.1 root 103:
104: #define OPTIMIZATION_OPTIONS(LEVEL) \
105: { \
106: if ((LEVEL) > 0) \
107: { \
108: flag_force_addr = 1; \
109: flag_force_mem = 1; \
110: flag_omit_frame_pointer = 1; \
111: } \
112: }
113:
114: /* target machine storage layout */
115:
116: /* Define the types for size_t, ptrdiff_t, and wchar_t. These are the
117: same as those used by EPI. The type for wchar_t does not make much
118: sense, but is what is used. */
119:
120: #define SIZE_TYPE "unsigned int"
121: #define PTRDIFF_TYPE "int"
122: #define WCHAR_TYPE "char"
123: #define WCHAR_TYPE_SIZE BITS_PER_UNIT
124:
125: /* Define this if most significant bit is lowest numbered
126: in instructions that operate on numbered bit-fields.
127: This is arbitrary on the 29k since it has no actual bit-field insns.
128: It is better to define this as TRUE because BYTES_BIG_ENDIAN is TRUE
129: and we want to be able to convert BP position to bit position with
130: just a shift. */
131: #define BITS_BIG_ENDIAN 1
132:
133: /* Define this if most significant byte of a word is the lowest numbered.
134: This is true on 29k. */
135: #define BYTES_BIG_ENDIAN 1
136:
137: /* Define this if most significant word of a multiword number is lowest
138: numbered.
139:
140: For 29k we can decide arbitrarily since there are no machine instructions
141: for them. Might as well be consistent with bytes. */
142: #define WORDS_BIG_ENDIAN 1
143:
1.1.1.2 root 144: /* number of bits in an addressable storage unit */
1.1 root 145: #define BITS_PER_UNIT 8
146:
147: /* Width in bits of a "word", which is the contents of a machine register.
148: Note that this is not necessarily the width of data type `int';
149: if using 16-bit ints on a 68000, this would still be 32.
150: But on a machine with 16-bit registers, this would be 16. */
151: #define BITS_PER_WORD 32
152:
153: /* Width of a word, in units (bytes). */
154: #define UNITS_PER_WORD 4
155:
156: /* Width in bits of a pointer.
157: See also the macro `Pmode' defined below. */
158: #define POINTER_SIZE 32
159:
160: /* Allocation boundary (in *bits*) for storing arguments in argument list. */
161: #define PARM_BOUNDARY 32
162:
163: /* Boundary (in *bits*) on which stack pointer should be aligned. */
164: #define STACK_BOUNDARY 64
165:
166: /* Allocation boundary (in *bits*) for the code of a function. */
167: #define FUNCTION_BOUNDARY 32
168:
169: /* Alignment of field after `int : 0' in a structure. */
170: #define EMPTY_FIELD_BOUNDARY 32
171:
172: /* Every structure's size must be a multiple of this. */
173: #define STRUCTURE_SIZE_BOUNDARY 8
174:
1.1.1.2 root 175: /* A bitfield declared as `int' forces `int' alignment for the struct. */
176: #define PCC_BITFIELD_TYPE_MATTERS 1
177:
1.1 root 178: /* No data type wants to be aligned rounder than this. */
179: #define BIGGEST_ALIGNMENT 32
180:
181: /* Make strings word-aligned so strcpy from constants will be faster. */
182: #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
183: (TREE_CODE (EXP) == STRING_CST \
184: && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
185:
186: /* Make arrays of chars word-aligned for the same reasons. */
187: #define DATA_ALIGNMENT(TYPE, ALIGN) \
188: (TREE_CODE (TYPE) == ARRAY_TYPE \
189: && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
190: && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
191:
1.1.1.2 root 192: /* Set this non-zero if move instructions will actually fail to work
1.1 root 193: when given unaligned data. */
1.1.1.2 root 194: #define STRICT_ALIGNMENT 0
1.1 root 195:
1.1.1.2 root 196: /* Set this non-zero if unaligned move instructions are extremely slow.
1.1 root 197:
198: On the 29k, they trap. */
1.1.1.2 root 199: #define SLOW_UNALIGNED_ACCESS 1
1.1 root 200:
201: /* Standard register usage. */
202:
203: /* Number of actual hardware registers.
204: The hardware registers are assigned numbers for the compiler
205: from 0 to just below FIRST_PSEUDO_REGISTER.
206: All registers that the compiler knows about must be given numbers,
207: even those that are not normally considered general registers.
208:
209: 29k has 256 registers, of which 62 are not defined. gr0 and gr1 are
210: not produced in generated RTL so we can start at gr96, and call it
211: register zero.
212:
213: So 0-31 are gr96-gr127, lr0-lr127 are 32-159. To represent the input
214: arguments, whose register numbers we won't know until we are done,
215: use register 160-175. They cannot be modified. Similarly, 176 is used
216: for the frame pointer. It is assigned the last local register number
217: once the number of registers used is known.
218:
219: We use 177, 178, 179, and 180 for the special registers BP, FC, CR, and Q,
220: respectively. Registers 181 through 199 are used for the other special
221: registers that may be used by the programmer, but are never used by the
222: compiler.
223:
224: Registers 200-203 are the four floating-point accumulator register in
225: the 29050.
226:
227: When -mkernel-registers is specified, we still use the same register
228: map but change the names so 0-31 print as gr64-gr95. */
229:
230: #define FIRST_PSEUDO_REGISTER 204
231:
232: /* Because of the large number of registers on the 29k, we define macros
233: to refer to each group of registers and then define the number for some
234: registers used in the calling sequence. */
235:
236: #define R_GR(N) ((N) - 96) /* gr96 is register number 0 */
237: #define R_LR(N) ((N) + 32) /* lr0 is register number 32 */
238: #define R_FP 176 /* frame pointer is register 176 */
239: #define R_AR(N) ((N) + 160) /* first incoming arg reg is 160 */
240:
241: /* Define the numbers of the special registers. */
242: #define R_BP 177
243: #define R_FC 178
244: #define R_CR 179
245: #define R_Q 180
246:
247: /* These special registers are not used by the compiler, but may be referenced
248: by the programmer via asm declarations. */
249:
250: #define R_VAB 181
251: #define R_OPS 182
252: #define R_CPS 183
253: #define R_CFG 184
254: #define R_CHA 185
255: #define R_CHD 186
256: #define R_CHC 187
257: #define R_RBP 188
258: #define R_TMC 189
259: #define R_TMR 190
260: #define R_PC0 191
261: #define R_PC1 192
262: #define R_PC2 193
263: #define R_MMU 194
264: #define R_LRU 195
265: #define R_FPE 196
266: #define R_INT 197
267: #define R_FPS 198
268: #define R_EXO 199
269:
270: /* Define the number for floating-point accumulator N. */
271: #define R_ACC(N) ((N) + 200)
272:
273: /* Now define the registers used in the calling sequence. */
274: #define R_TAV R_GR (121)
275: #define R_TPC R_GR (122)
276: #define R_LRP R_GR (123)
277: #define R_SLP R_GR (124)
278: #define R_MSP R_GR (125)
279: #define R_RAB R_GR (126)
280: #define R_RFB R_GR (127)
281:
282: /* 1 for registers that have pervasive standard uses
283: and are not available for the register allocator. */
284:
285: #define FIXED_REGISTERS \
286: {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
287: 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, \
288: 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
289: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
290: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
291: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
292: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
293: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
294: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
295: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
296: 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
297: 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
298: 1, 1, 1, 1, 1, 1, 1, 1, \
299: 0, 0, 0, 0 }
300:
301: /* 1 for registers not available across function calls.
302: These must include the FIXED_REGISTERS and also any
303: registers that can be used without being saved.
304: The latter must include the registers where values are returned
305: and the register where structure-value addresses are passed.
306: Aside from that, you can include as many other registers as you like. */
307: #define CALL_USED_REGISTERS \
308: {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
309: 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
310: 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
311: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
312: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
313: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
314: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
315: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
316: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
317: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
318: 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
319: 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
320: 1, 1, 1, 1, 1, 1, 1, 1, \
321: 1, 1, 1, 1 }
322:
323: /* List the order in which to allocate registers. Each register must be
324: listed once, even those in FIXED_REGISTERS.
325:
326: We allocate in the following order:
327: gr116-gr120 (not used for anything but temps)
328: gr96-gr111 (function return values, reverse order)
329: argument registers (160-175)
330: lr0-lr127 (locals, saved)
331: acc3-0 (acc0 special)
332: everything else */
333:
334: #define REG_ALLOC_ORDER \
335: {R_GR (116), R_GR (117), R_GR (118), R_GR (119), R_GR (120), \
336: R_GR (111), R_GR (110), R_GR (109), R_GR (108), R_GR (107), \
337: R_GR (106), R_GR (105), R_GR (104), R_GR (103), R_GR (102), \
338: R_GR (101), R_GR (100), R_GR (99), R_GR (98), R_GR (97), R_GR (96), \
339: R_AR (0), R_AR (1), R_AR (2), R_AR (3), R_AR (4), R_AR (5), \
340: R_AR (6), R_AR (7), R_AR (8), R_AR (9), R_AR (10), R_AR (11), \
341: R_AR (12), R_AR (13), R_AR (14), R_AR (15), \
342: R_LR (0), R_LR (1), R_LR (2), R_LR (3), R_LR (4), R_LR (5), \
343: R_LR (6), R_LR (7), R_LR (8), R_LR (9), R_LR (10), R_LR (11), \
344: R_LR (12), R_LR (13), R_LR (14), R_LR (15), R_LR (16), R_LR (17), \
345: R_LR (18), R_LR (19), R_LR (20), R_LR (21), R_LR (22), R_LR (23), \
346: R_LR (24), R_LR (25), R_LR (26), R_LR (27), R_LR (28), R_LR (29), \
347: R_LR (30), R_LR (31), R_LR (32), R_LR (33), R_LR (34), R_LR (35), \
348: R_LR (36), R_LR (37), R_LR (38), R_LR (39), R_LR (40), R_LR (41), \
349: R_LR (42), R_LR (43), R_LR (44), R_LR (45), R_LR (46), R_LR (47), \
350: R_LR (48), R_LR (49), R_LR (50), R_LR (51), R_LR (52), R_LR (53), \
351: R_LR (54), R_LR (55), R_LR (56), R_LR (57), R_LR (58), R_LR (59), \
352: R_LR (60), R_LR (61), R_LR (62), R_LR (63), R_LR (64), R_LR (65), \
353: R_LR (66), R_LR (67), R_LR (68), R_LR (69), R_LR (70), R_LR (71), \
354: R_LR (72), R_LR (73), R_LR (74), R_LR (75), R_LR (76), R_LR (77), \
355: R_LR (78), R_LR (79), R_LR (80), R_LR (81), R_LR (82), R_LR (83), \
356: R_LR (84), R_LR (85), R_LR (86), R_LR (87), R_LR (88), R_LR (89), \
357: R_LR (90), R_LR (91), R_LR (92), R_LR (93), R_LR (94), R_LR (95), \
358: R_LR (96), R_LR (97), R_LR (98), R_LR (99), R_LR (100), R_LR (101), \
359: R_LR (102), R_LR (103), R_LR (104), R_LR (105), R_LR (106), \
360: R_LR (107), R_LR (108), R_LR (109), R_LR (110), R_LR (111), \
361: R_LR (112), R_LR (113), R_LR (114), R_LR (115), R_LR (116), \
362: R_LR (117), R_LR (118), R_LR (119), R_LR (120), R_LR (121), \
363: R_LR (122), R_LR (123), R_LR (124), R_LR (124), R_LR (126), \
364: R_LR (127), \
365: R_ACC (3), R_ACC (2), R_ACC (1), R_ACC (0), \
366: R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (121), \
367: R_GR (122), R_GR (123), R_GR (124), R_GR (125), R_GR (126), \
368: R_GR (127), \
369: R_FP, R_BP, R_FC, R_CR, R_Q, \
370: R_VAB, R_OPS, R_CPS, R_CFG, R_CHA, R_CHD, R_CHC, R_RBP, R_TMC, \
371: R_TMR, R_PC0, R_PC1, R_PC2, R_MMU, R_LRU, R_FPE, R_INT, R_FPS, \
372: R_EXO }
373:
374: /* Return number of consecutive hard regs needed starting at reg REGNO
375: to hold something of mode MODE.
376: This is ordinarily the length in words of a value of mode MODE
377: but can be less for certain modes in special long registers. */
378:
379: #define HARD_REGNO_NREGS(REGNO, MODE) \
380: ((REGNO) >= R_ACC (0) ? 1 \
381: : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
382:
383: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
384: On 29k, the cpu registers can hold any mode. But a double-precision
385: floating-point value should start at an even register. The special
386: registers cannot hold floating-point values and the accumulators cannot
387: hold integer values.
388:
1.1.1.3 ! root 389: DImode and larger values should start at an even register just like
! 390: DFmode values, even though the instruction set doesn't require it, in order
! 391: to prevent reload from aborting due to a modes_equiv_for_class_p failure.
! 392:
1.1 root 393: (I'd like to use the "?:" syntax to make this more readable, but Sun's
394: compiler doesn't seem to accept it.) */
395: #define HARD_REGNO_MODE_OK(REGNO, MODE) \
396: (((REGNO) >= R_ACC (0) \
397: && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
398: || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)) \
399: || ((REGNO) >= R_BP && (REGNO) < R_ACC (0) \
400: && GET_MODE_CLASS (MODE) != MODE_FLOAT \
401: && GET_MODE_CLASS (MODE) != MODE_COMPLEX_FLOAT) \
402: || ((REGNO) < R_BP \
1.1.1.3 ! root 403: && ((((REGNO) & 1) == 0) \
1.1 root 404: || GET_MODE_UNIT_SIZE (MODE) <= UNITS_PER_WORD)))
405:
406: /* Value is 1 if it is a good idea to tie two pseudo registers
407: when one has mode MODE1 and one has mode MODE2.
408: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
409: for any hard reg, then this must be 0 for correct output.
410:
411: On the 29k, normally we'd just have problems with DFmode because of the
412: even alignment. However, we also have to be a bit concerned about
413: the special register's restriction to non-floating and the floating-point
414: accumulator's restriction to only floating. This probably won't
415: cause any great inefficiencies in practice. */
416: #define MODES_TIEABLE_P(MODE1, MODE2) \
417: ((MODE1) == (MODE2) \
418: || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
419: && GET_MODE_CLASS (MODE1) != MODE_COMPLEX_FLOAT \
420: && GET_MODE_CLASS (MODE2) != MODE_FLOAT \
421: && GET_MODE_CLASS (MODE2) != MODE_COMPLEX_FLOAT))
422:
423: /* Specify the registers used for certain standard purposes.
424: The values of these macros are register numbers. */
425:
426: /* 29k pc isn't overloaded on a register that the compiler knows about. */
427: /* #define PC_REGNUM */
428:
429: /* Register to use for pushing function arguments. */
430: #define STACK_POINTER_REGNUM R_GR (125)
431:
432: /* Base register for access to local variables of the function. */
433: #define FRAME_POINTER_REGNUM R_FP
434:
435: /* Value should be nonzero if functions must have frame pointers.
436: Zero means the frame pointer need not be set up (and parms
437: may be accessed via the stack pointer) in functions that seem suitable.
438: This is computed in `reload', in reload1.c. */
439: #define FRAME_POINTER_REQUIRED 0
440:
441: /* Base register for access to arguments of the function. */
442: #define ARG_POINTER_REGNUM R_FP
443:
444: /* Register in which static-chain is passed to a function. */
445: #define STATIC_CHAIN_REGNUM R_SLP
446:
447: /* Register in which address to store a structure value
448: is passed to a function. */
449: #define STRUCT_VALUE_REGNUM R_LRP
450:
451: /* Define the classes of registers for register constraints in the
452: machine description. Also define ranges of constants.
453:
454: One of the classes must always be named ALL_REGS and include all hard regs.
455: If there is more than one class, another class must be named NO_REGS
456: and contain no registers.
457:
458: The name GENERAL_REGS must be the name of a class (or an alias for
459: another name such as ALL_REGS). This is the class of registers
460: that is allowed by "g" or "r" in a register constraint.
461: Also, registers outside this class are allocated only when
462: instructions express preferences for them.
463:
464: The classes must be numbered in nondecreasing order; that is,
465: a larger-numbered class must never be contained completely
466: in a smaller-numbered class.
467:
468: For any two classes, it is very desirable that there be another
469: class that represents their union.
470:
471: The 29k has six registers classes: GENERAL_REGS, SPECIAL_REGS,
472: BP_REGS, Q_REGS, ACCUM_REGS, and ACCUM0_REGS. BP_REGS contains just BP and
473: is used for the extract and insert operations to allow combinations; Q
474: contains just the Q register. The latter two classes are used to represent
475: the floating-point accumulator registers in the 29050. We also define the
476: union class FLOAT_REGS to represent any register that can be used to hold a
477: floating-point value. The union of SPECIAL_REGS and ACCUM_REGS isn't
478: useful as the former cannot contain floating-point and the latter can only
479: contain floating-point. */
480:
481: enum reg_class { NO_REGS, GENERAL_REGS, BP_REGS, Q_REGS, SPECIAL_REGS,
482: ACCUM0_REGS, ACCUM_REGS, FLOAT_REGS, ALL_REGS,
483: LIM_REG_CLASSES };
484:
485: #define N_REG_CLASSES (int) LIM_REG_CLASSES
486:
487: /* Give names of register classes as strings for dump file. */
488:
489: #define REG_CLASS_NAMES \
490: {"NO_REGS", "GENERAL_REGS", "BP_REGS", "Q_REGS", "SPECIAL_REGS", \
491: "ACCUM0_REGS", "ACCUM_REGS", "FLOAT_REGS", "ALL_REGS" }
492:
493: /* Define which registers fit in which classes.
494: This is an initializer for a vector of HARD_REG_SET
495: of length N_REG_CLASSES. */
496:
497: #define REG_CLASS_CONTENTS \
498: { {0, 0, 0, 0, 0, 0, 0}, \
499: {~0, ~0, ~0, ~0, ~0, ~ 0xfffe0000, 0}, \
500: {0, 0, 0, 0, 0, 0x20000, 0}, \
501: {0, 0, 0, 0, 0, 0x100000, 0}, \
502: {0, 0, 0, 0, 0, 0xfffe0000, 0xff}, \
503: {0, 0, 0, 0, 0, 0, 0x100}, \
504: {0, 0, 0, 0, 0, 0, 0xf00}, \
505: {~0, ~0, ~0, ~0, ~0, ~ 0xfffe0000, 0xf00}, \
506: {~0, ~0, ~0, ~0, ~0, ~0, ~0} }
507:
508: /* The same information, inverted:
509: Return the class number of the smallest class containing
510: reg number REGNO. This could be a conditional expression
511: or could index an array. */
512:
513: #define REGNO_REG_CLASS(REGNO) \
514: ((REGNO) == R_BP ? BP_REGS \
515: : (REGNO) == R_Q ? Q_REGS \
516: : (REGNO) > R_BP && (REGNO) <= R_EXO ? SPECIAL_REGS \
517: : (REGNO) == R_ACC (0) ? ACCUM0_REGS \
518: : (REGNO) > R_ACC (0) ? ACCUM_REGS \
519: : GENERAL_REGS)
520:
521: /* The class value for index registers, and the one for base regs. */
522: #define INDEX_REG_CLASS NO_REGS
523: #define BASE_REG_CLASS GENERAL_REGS
524:
525: /* Get reg_class from a letter such as appears in the machine description. */
526:
527: #define REG_CLASS_FROM_LETTER(C) \
528: ((C) == 'r' ? GENERAL_REGS \
529: : (C) == 'b' ? BP_REGS \
530: : (C) == 'q' ? Q_REGS \
531: : (C) == 'h' ? SPECIAL_REGS \
532: : (C) == 'a' ? ACCUM_REGS \
533: : (C) == 'A' ? ACCUM0_REGS \
534: : (C) == 'f' ? FLOAT_REGS \
535: : NO_REGS)
536:
537: /* Define this macro to change register usage conditional on target flags.
538:
539: On the 29k, we use this to change the register names for kernel mapping. */
540:
541: #define CONDITIONAL_REGISTER_USAGE \
542: { \
543: static char *kernel_names[] = {"gr64", "gr65", "gr66", "gr67", \
544: "gr68", "gr69", "gr70", "gr71", \
545: "gr72", "gr73", "gr74", "gr75", \
546: "gr76", "gr77", "gr78", "gr79", \
547: "gr80", "gr81", "gr82", "gr83", \
548: "gr84", "gr85", "gr86", "gr87", \
549: "gr88", "gr89", "gr90", "gr91", \
550: "gr92", "gr93", "gr94", "gr95"}; \
551: int i; \
552: \
553: if (TARGET_KERNEL_REGISTERS) \
554: for (i = 0; i < 32; i++) \
555: reg_names[i] = kernel_names[i]; \
556: }
557:
558: /* The letters I, J, K, L, M, N, O, and P in a register constraint string
559: can be used to stand for particular ranges of immediate operands.
560: This macro defines what the ranges are.
561: C is the letter, and VALUE is a constant value.
562: Return 1 if VALUE is in the range specified by C.
563:
564: For 29k:
565: `I' is used for the range of constants most insns can contain.
566: `J' is for the few 16-bit insns.
567: `K' is a constant whose high-order 24 bits are all one
568: `L' is a HImode constant whose high-order 8 bits are all one
569: `M' is a 32-bit constant whose high-order 16 bits are all one (for CONSTN)
570: `N' is a 32-bit constant whose negative is 8 bits
571: `O' is the 32-bit constant 0x80000000, any constant with low-order
572: 16 bits zero for 29050.
573: `P' is a HImode constant whose negative is 8 bits */
574:
575: #define CONST_OK_FOR_LETTER_P(VALUE, C) \
576: ((C) == 'I' ? (unsigned) (VALUE) < 0x100 \
577: : (C) == 'J' ? (unsigned) (VALUE) < 0x10000 \
578: : (C) == 'K' ? ((VALUE) & 0xffffff00) == 0xffffff00 \
579: : (C) == 'L' ? ((VALUE) & 0xff00) == 0xff00 \
580: : (C) == 'M' ? ((VALUE) & 0xffff0000) == 0xffff0000 \
581: : (C) == 'N' ? ((VALUE) < 0 && (VALUE) > -256) \
582: : (C) == 'O' ? ((VALUE) == 0x80000000 \
583: || (TARGET_29050 && ((VALUE) & 0xffff) == 0)) \
584: : (C) == 'P' ? (((VALUE) | 0xffff0000) < 0 \
585: && ((VALUE) | 0xffff0000) > -256) \
586: : 0)
587:
588: /* Similar, but for floating constants, and defining letters G and H.
589: Here VALUE is the CONST_DOUBLE rtx itself.
590: All floating-point constants are valid on 29k. */
591:
592: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1
593:
594: /* Given an rtx X being reloaded into a reg required to be
595: in class CLASS, return the class of reg to actually use.
596: In general this is just CLASS; but on some machines
597: in some cases it is preferable to use a more restrictive class. */
598:
599: #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
600:
601: /* Return the register class of a scratch register needed to copy IN into
602: or out of a register in CLASS in MODE. If it can be done directly,
603: NO_REGS is returned. */
604:
605: #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
606: secondary_reload_class (CLASS, MODE, IN)
607:
608: /* Return the maximum number of consecutive registers
609: needed to represent mode MODE in a register of class CLASS.
610:
611: On 29k, this is the size of MODE in words except that the floating-point
612: accumulators only require one word for anything they can hold. */
613:
614: #define CLASS_MAX_NREGS(CLASS, MODE) \
615: (((CLASS) == ACCUM_REGS || (CLASS) == ACCUM0_REGS) ? 1 \
616: : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
617:
618: /* Define the cost of moving between registers of various classes. Everything
619: involving a general register is cheap, but moving between the other types
620: (even within a class) is two insns. */
621:
622: #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
623: ((CLASS1) == GENERAL_REGS || (CLASS2) == GENERAL_REGS ? 2 : 4)
624:
625: /* Stack layout; function entry, exit and calling. */
626:
627: /* Define this if pushing a word on the stack
628: makes the stack pointer a smaller address. */
629: #define STACK_GROWS_DOWNWARD
630:
631: /* Define this if the nominal address of the stack frame
632: is at the high-address end of the local variables;
633: that is, each additional local variable allocated
634: goes at a more negative offset in the frame. */
635: #define FRAME_GROWS_DOWNWARD
636:
637: /* Offset within stack frame to start allocating local variables at.
638: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
639: first local allocated. Otherwise, it is the offset to the BEGINNING
640: of the first local allocated. */
641:
642: #define STARTING_FRAME_OFFSET (- current_function_pretend_args_size)
643:
644: /* If we generate an insn to push BYTES bytes,
645: this says how many the stack pointer really advances by.
646: On 29k, don't define this because there are no push insns. */
647: /* #define PUSH_ROUNDING(BYTES) */
648:
649: /* Define this if the maximum size of all the outgoing args is to be
650: accumulated and pushed during the prologue. The amount can be
651: found in the variable current_function_outgoing_args_size. */
652: #define ACCUMULATE_OUTGOING_ARGS
653:
654: /* Offset of first parameter from the argument pointer register value. */
655:
656: #define FIRST_PARM_OFFSET(FNDECL) (- current_function_pretend_args_size)
657:
658: /* Define this if stack space is still allocated for a parameter passed
659: in a register. */
660: /* #define REG_PARM_STACK_SPACE */
661:
662: /* Value is the number of bytes of arguments automatically
663: popped when returning from a subroutine call.
664: FUNTYPE is the data type of the function (as a tree),
665: or for a library call it is an identifier node for the subroutine name.
666: SIZE is the number of bytes of arguments passed on the stack. */
667:
668: #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0
669:
670: /* Define how to find the value returned by a function.
671: VALTYPE is the data type of the value (as a tree).
672: If the precise function being called is known, FUNC is its FUNCTION_DECL;
673: otherwise, FUNC is 0.
674:
675: On 29k the value is found in gr96. */
676:
677: #define FUNCTION_VALUE(VALTYPE, FUNC) \
678: gen_rtx (REG, TYPE_MODE (VALTYPE), R_GR (96))
679:
680: /* Define how to find the value returned by a library function
681: assuming the value has mode MODE. */
682:
683: #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, R_GR (96))
684:
685: /* 1 if N is a possible register number for a function value
686: as seen by the caller.
687: On 29k, gr96-gr111 are used. */
688:
689: #define FUNCTION_VALUE_REGNO_P(N) ((N) < R_GR (112))
690:
691: /* 1 if N is a possible register number for function argument passing.
692: On 29k, these are lr2-lr17. */
693:
694: #define FUNCTION_ARG_REGNO_P(N) ((N) <= R_LR (17) && (N) >= R_LR (2))
695:
696: /* Define a data type for recording info about an argument list
697: during the scan of that argument list. This data type should
698: hold all necessary information about the function itself
699: and about the args processed so far, enough to enable macros
700: such as FUNCTION_ARG to determine where the next arg should go.
701:
702: On 29k, this is a single integer, which is a number of words
703: of arguments scanned so far.
704: Thus 16 or more means all following args should go on the stack. */
705:
706: #define CUMULATIVE_ARGS int
707:
708: /* Initialize a variable CUM of type CUMULATIVE_ARGS
709: for a call to a function whose data type is FNTYPE.
710: For a library call, FNTYPE is 0. */
711:
712: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) (CUM) = 0
713:
714: /* Same, but called for incoming args.
715:
716: On the 29k, we use this to set all argument registers to fixed and
717: set the last 16 local regs (lr112-lr127) to available. Some
718: will later be changed to call-saved by FUNCTION_INCOMING_ARG. */
719:
720: #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,IGNORE) \
721: { int i; \
722: for (i = R_AR (0); i < R_AR (16); i++) \
723: { \
724: fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; \
725: SET_HARD_REG_BIT (fixed_reg_set, i); \
726: SET_HARD_REG_BIT (call_used_reg_set, i); \
727: SET_HARD_REG_BIT (call_fixed_reg_set, i); \
728: } \
729: for (i = R_LR (112); i < R_LR (128); i++) \
730: { \
731: fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 0; \
732: CLEAR_HARD_REG_BIT (fixed_reg_set, i); \
733: CLEAR_HARD_REG_BIT (call_used_reg_set, i); \
734: CLEAR_HARD_REG_BIT (call_fixed_reg_set, i); \
735: } \
736: (CUM) = 0; \
737: }
738:
739: /* Define intermediate macro to compute the size (in registers) of an argument
740: for the 29k. */
741:
742: #define A29K_ARG_SIZE(MODE, TYPE, NAMED) \
743: (! (NAMED) ? 0 \
744: : (MODE) != BLKmode \
745: ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
746: : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
747:
748: /* Update the data in CUM to advance over an argument
749: of mode MODE and data type TYPE.
750: (TYPE is null for libcalls where that information may not be available.) */
751:
752: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
753: if (MUST_PASS_IN_STACK (MODE, TYPE)) \
754: (CUM) = 16; \
755: else \
756: (CUM) += A29K_ARG_SIZE (MODE, TYPE, NAMED)
757:
758: /* Determine where to put an argument to a function.
759: Value is zero to push the argument on the stack,
760: or a hard register in which to store the argument.
761:
762: MODE is the argument's machine mode.
763: TYPE is the data type of the argument (as a tree).
764: This is null for libcalls where that information may
765: not be available.
766: CUM is a variable of type CUMULATIVE_ARGS which gives info about
767: the preceding args and about the function being called.
768: NAMED is nonzero if this argument is a named parameter
769: (otherwise it is an extra parameter matching an ellipsis).
770:
771: On 29k the first 16 words of args are normally in registers
772: and the rest are pushed. */
773:
774: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
775: ((CUM) < 16 && (NAMED) && ! MUST_PASS_IN_STACK (MODE, TYPE) \
776: ? gen_rtx(REG, (MODE), R_LR (2) + (CUM)) : 0)
777:
778: /* Define where a function finds its arguments.
779: This is different from FUNCTION_ARG because of register windows.
780:
781: On the 29k, we hack this to call a function that sets the used registers
782: as non-fixed and not used by calls. */
783:
784: #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
785: ((CUM) < 16 && (NAMED) && ! MUST_PASS_IN_STACK (MODE, TYPE) \
786: ? gen_rtx (REG, MODE, \
787: incoming_reg (CUM, A29K_ARG_SIZE (MODE, TYPE, NAMED))) \
788: : 0)
789:
790: /* This indicates that an argument is to be passed with an invisible reference
791: (i.e., a pointer to the object is passed).
792:
793: On the 29k, we do this if it must be passed on the stack. */
794:
795: #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
796: (MUST_PASS_IN_STACK (MODE, TYPE))
797:
798: /* Specify the padding direction of arguments.
799:
800: On the 29k, we must pad upwards in order to be able to pass args in
801: registers. */
802:
803: #define FUNCTION_ARG_PADDING(MODE, TYPE) upward
804:
805: /* For an arg passed partly in registers and partly in memory,
806: this is the number of registers used.
807: For args passed entirely in registers or entirely in memory, zero. */
808:
809: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
810: ((CUM) < 16 && 16 < (CUM) + A29K_ARG_SIZE (MODE, TYPE, NAMED) && (NAMED) \
811: ? 16 - (CUM) : 0)
812:
813: /* Perform any needed actions needed for a function that is receiving a
814: variable number of arguments.
815:
816: CUM is as above.
817:
818: MODE and TYPE are the mode and type of the current parameter.
819:
820: PRETEND_SIZE is a variable that should be set to the amount of stack
821: that must be pushed by the prolog to pretend that our caller pushed
822: it.
823:
824: Normally, this macro will push all remaining incoming registers on the
825: stack and set PRETEND_SIZE to the length of the registers pushed. */
826:
827: #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
828: { if ((CUM) < 16) \
829: { \
830: int first_reg_offset = (CUM); \
831: \
832: if (MUST_PASS_IN_STACK (MODE, TYPE)) \
833: first_reg_offset += A29K_ARG_SIZE (TYPE_MODE (TYPE), TYPE, 1); \
834: \
835: if (first_reg_offset > 16) \
836: first_reg_offset = 16; \
837: \
838: if (! (NO_RTL) && first_reg_offset != 16) \
839: move_block_from_reg \
840: (R_AR (0) + first_reg_offset, \
841: gen_rtx (MEM, BLKmode, virtual_incoming_args_rtx), \
842: 16 - first_reg_offset); \
843: PRETEND_SIZE = (16 - first_reg_offset) * UNITS_PER_WORD; \
844: } \
845: }
846:
847: /* Define the information needed to generate branch and scc insns. This is
848: stored from the compare operation. Note that we can't use "rtx" here
849: since it hasn't been defined! */
850:
851: extern struct rtx_def *a29k_compare_op0, *a29k_compare_op1;
852: extern int a29k_compare_fp_p;
853:
854: /* This macro produces the initial definition of a function name.
855:
856: For the 29k, we need the prolog to contain one or two words prior to
857: the declaration of the function name. So just store away the name and
858: write it as part of the prolog. */
859:
860: extern char *a29k_function_name;
861:
862: #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
863: a29k_function_name = NAME;
864:
865: /* This macro generates the assembly code for function entry.
866: FILE is a stdio stream to output the code to.
867: SIZE is an int: how many units of temporary storage to allocate.
868: Refer to the array `regs_ever_live' to determine which registers
869: to save; `regs_ever_live[I]' is nonzero if register number I
870: is ever used in the function. This macro is responsible for
871: knowing which registers should not be saved even if used. */
872:
873: #define FUNCTION_PROLOGUE(FILE, SIZE) output_prolog (FILE, SIZE)
874:
875: /* Output assembler code to FILE to increment profiler label # LABELNO
876: for profiling a function entry. */
877:
878: #define FUNCTION_PROFILER(FILE, LABELNO)
879:
880: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
881: the stack pointer does not matter. The value is tested only in
882: functions that have frame pointers.
883: No definition is equivalent to always zero. */
884:
885: #define EXIT_IGNORE_STACK 1
886:
887: /* This macro generates the assembly code for function exit,
888: on machines that need it. If FUNCTION_EPILOGUE is not defined
889: then individual return instructions are generated for each
890: return statement. Args are same as for FUNCTION_PROLOGUE.
891:
892: The function epilogue should not depend on the current stack pointer!
893: It should use the frame pointer only. This is mandatory because
894: of alloca; we also take advantage of it to omit stack adjustments
895: before returning. */
896:
897: #define FUNCTION_EPILOGUE(FILE, SIZE) output_epilog (FILE, SIZE)
898:
899: /* Define the number of delay slots needed for the function epilogue.
900:
901: On the 29k, we need a slot except when we have a register stack adjustment,
902: have a memory stack adjustment, and have no frame pointer. */
903:
904: #define DELAY_SLOTS_FOR_EPILOGUE \
905: (! (needs_regstack_p () \
906: && (get_frame_size () + current_function_pretend_args_size \
907: + current_function_outgoing_args_size) != 0 \
908: && ! frame_pointer_needed))
909:
910: /* Define whether INSN can be placed in delay slot N for the epilogue.
911:
912: On the 29k, we must be able to place it in a delay slot, it must
913: not use sp if the frame pointer cannot be eliminated, and it cannot
914: use local regs if we need to push the register stack. */
915:
916: #define ELIGIBLE_FOR_EPILOGUE_DELAY(INSN,N) \
917: (get_attr_in_delay_slot (INSN) == IN_DELAY_SLOT_YES \
918: && ! (frame_pointer_needed \
919: && reg_mentioned_p (stack_pointer_rtx, PATTERN (INSN))) \
920: && ! (needs_regstack_p () && uses_local_reg_p (PATTERN (INSN))))
921:
922: /* Output assembler code for a block containing the constant parts
923: of a trampoline, leaving space for the variable parts.
924:
925: The trampoline should set the static chain pointer to value placed
926: into the trampoline and should branch to the specified routine. We
927: use gr121 (tav) as a temporary. */
928:
929: #define TRAMPOLINE_TEMPLATE(FILE) \
930: { \
931: fprintf (FILE, "\tconst %s,0\n", reg_names[R_TAV]); \
932: fprintf (FILE, "\tconsth %s,0\n", reg_names[R_TAV]); \
933: fprintf (FILE, "\tconst %s,0\n", reg_names[R_SLP]); \
934: fprintf (FILE, "\tjmpi %s\n", reg_names[R_TAV]); \
935: fprintf (FILE, "\tconsth %s,0\n", reg_names[R_SLP]); \
936: }
937:
938: /* Length in units of the trampoline for entering a nested function. */
939:
940: #define TRAMPOLINE_SIZE 20
941:
942: /* Emit RTL insns to initialize the variable parts of a trampoline.
943: FNADDR is an RTX for the address of the function's pure code.
944: CXT is an RTX for the static chain value for the function.
945:
946: We do this on the 29k by writing the bytes of the addresses into the
947: trampoline one byte at a time. */
948:
949: #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
950: { \
951: INITIALIZE_TRAMPOLINE_VALUE (TRAMP, FNADDR, 0, 4); \
952: INITIALIZE_TRAMPOLINE_VALUE (TRAMP, CXT, 8, 16); \
953: }
954:
955: /* Define a sub-macro to initialize one value into the trampoline.
956: We specify the offsets of the CONST and CONSTH instructions, respectively
957: and copy the value a byte at a time into these instructions. */
958:
959: #define INITIALIZE_TRAMPOLINE_VALUE(TRAMP, VALUE, CONST, CONSTH) \
960: { \
961: rtx _addr, _temp; \
962: rtx _val = force_reg (SImode, VALUE); \
963: \
964: _addr = memory_address (QImode, plus_constant (TRAMP, (CONST) + 3)); \
965: emit_move_insn (gen_rtx (MEM, QImode, _addr), \
966: gen_lowpart (QImode, _val)); \
967: \
968: _temp = expand_shift (RSHIFT_EXPR, SImode, _val, \
969: build_int_2 (8, 0), 0, 1); \
970: _addr = memory_address (QImode, plus_constant (TRAMP, (CONST) + 1)); \
971: emit_move_insn (gen_rtx (MEM, QImode, _addr), \
972: gen_lowpart (QImode, _temp)); \
973: \
974: _temp = expand_shift (RSHIFT_EXPR, SImode, _temp, \
975: build_int_2 (8, 0), _temp, 1); \
976: _addr = memory_address (QImode, plus_constant (TRAMP, (CONSTH) + 3)); \
977: emit_move_insn (gen_rtx (MEM, QImode, _addr), \
978: gen_lowpart (QImode, _temp)); \
979: \
980: _temp = expand_shift (RSHIFT_EXPR, SImode, _temp, \
981: build_int_2 (8, 0), _temp, 1); \
982: _addr = memory_address (QImode, plus_constant (TRAMP, (CONSTH) + 1)); \
983: emit_move_insn (gen_rtx (MEM, QImode, _addr), \
984: gen_lowpart (QImode, _temp)); \
985: }
986:
987: /* Addressing modes, and classification of registers for them. */
988:
989: /* #define HAVE_POST_INCREMENT */
990: /* #define HAVE_POST_DECREMENT */
991:
992: /* #define HAVE_PRE_DECREMENT */
993: /* #define HAVE_PRE_INCREMENT */
994:
995: /* Macros to check register numbers against specific register classes. */
996:
997: /* These assume that REGNO is a hard or pseudo reg number.
998: They give nonzero only if REGNO is a hard reg of the suitable class
999: or a pseudo reg currently allocated to a suitable hard reg.
1000: Since they use reg_renumber, they are safe only once reg_renumber
1001: has been allocated, which happens in local-alloc.c. */
1002:
1003: #define REGNO_OK_FOR_INDEX_P(REGNO) 0
1004: #define REGNO_OK_FOR_BASE_P(REGNO) 1
1005:
1006: /* Given the value returned from get_frame_size, compute the actual size
1007: of the frame we will allocate. We include the pretend and outgoing
1008: arg sizes and round to a doubleword. */
1009:
1010: #define ACTUAL_FRAME_SIZE(SIZE) \
1011: (((SIZE) + current_function_pretend_args_size \
1012: + current_function_outgoing_args_size + 7) & ~7)
1013:
1014: /* Define the initial offset between the frame and stack pointer. */
1015:
1016: #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
1017: (DEPTH) = ACTUAL_FRAME_SIZE (get_frame_size ())
1018:
1019: /* Maximum number of registers that can appear in a valid memory address. */
1020: #define MAX_REGS_PER_ADDRESS 1
1021:
1022: /* Recognize any constant value that is a valid address.
1023:
1024: None are on the 29K. */
1025: #define CONSTANT_ADDRESS_P(X) 0
1026:
1027: /* Include all constant integers and constant doubles */
1028: #define LEGITIMATE_CONSTANT_P(X) 1
1029:
1030: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1031: and check its validity for a certain class.
1032: We have two alternate definitions for each of them.
1033: The usual definition accepts all pseudo regs; the other rejects
1034: them unless they have been allocated suitable hard regs.
1035: The symbol REG_OK_STRICT causes the latter definition to be used.
1036:
1037: Most source files want to accept pseudo regs in the hope that
1038: they will get allocated to the class that the insn wants them to be in.
1039: Source files for reload pass need to be strict.
1040: After reload, it makes no difference, since pseudo regs have
1041: been eliminated by then. */
1042:
1043: #ifndef REG_OK_STRICT
1044:
1045: /* Nonzero if X is a hard reg that can be used as an index
1046: or if it is a pseudo reg. */
1047: #define REG_OK_FOR_INDEX_P(X) 0
1048: /* Nonzero if X is a hard reg that can be used as a base reg
1049: or if it is a pseudo reg. */
1050: #define REG_OK_FOR_BASE_P(X) 1
1051:
1052: #else
1053:
1054: /* Nonzero if X is a hard reg that can be used as an index. */
1055: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1056: /* Nonzero if X is a hard reg that can be used as a base reg. */
1057: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1058:
1059: #endif
1060:
1061: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1062: that is a valid memory address for an instruction.
1063: The MODE argument is the machine mode for the MEM expression
1064: that wants to use this address.
1065:
1066: On the 29k, a legitimate address is a register and so is a
1067: constant of less than 256. */
1068:
1069: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1070: { if (REG_P (X) && REG_OK_FOR_BASE_P (X)) \
1071: goto ADDR; \
1072: if (GET_CODE (X) == CONST_INT \
1073: && (unsigned) INTVAL (X) < 0x100) \
1074: goto ADDR; \
1075: }
1076:
1077: /* Try machine-dependent ways of modifying an illegitimate address
1078: to be legitimate. If we find one, return the new, valid address.
1079: This macro is used in only one place: `memory_address' in explow.c.
1080:
1081: OLDX is the address as it was before break_out_memory_refs was called.
1082: In some cases it is useful to look at this to decide what needs to be done.
1083:
1084: MODE and WIN are passed so that this macro can use
1085: GO_IF_LEGITIMATE_ADDRESS.
1086:
1087: It is always safe for this macro to do nothing. It exists to recognize
1088: opportunities to optimize the output.
1089:
1090: For the 29k, we need not do anything. However, if we don't,
1091: `memory_address' will try lots of things to get a valid address, most of
1092: which will result in dead code and extra pseudos. So we make the address
1093: valid here.
1094:
1095: This is easy: The only valid addresses are an offset from a register
1096: and we know the address isn't valid. So just call either `force_operand'
1097: or `force_reg' unless this is a (plus (reg ...) (const_int 0)). */
1098:
1099: #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1100: { if (GET_CODE (X) == PLUS && XEXP (X, 1) == const0_rtx) \
1101: X = XEXP (x, 0); \
1102: if (GET_CODE (X) == MULT || GET_CODE (X) == PLUS) \
1103: X = force_operand (X, 0); \
1104: else \
1105: X = force_reg (Pmode, X); \
1106: goto WIN; \
1107: }
1108:
1109: /* Go to LABEL if ADDR (a legitimate address expression)
1110: has an effect that depends on the machine mode it is used for.
1111: On the 29k this is never true. */
1112:
1113: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1114:
1115: /* Compute the cost of an address. For the 29k, all valid addresses are
1116: the same cost. */
1117:
1118: #define ADDRESS_COST(X) 0
1119:
1120: /* Define this if some processing needs to be done immediately before
1121: emitting code for an insn. */
1122:
1123: /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
1124:
1125: /* Specify the machine mode that this machine uses
1126: for the index in the tablejump instruction. */
1127: #define CASE_VECTOR_MODE SImode
1128:
1129: /* Define this if the tablejump instruction expects the table
1130: to contain offsets from the address of the table.
1131: Do not define this if the table should contain absolute addresses. */
1132: /* #define CASE_VECTOR_PC_RELATIVE */
1133:
1134: /* Specify the tree operation to be used to convert reals to integers. */
1135: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1136:
1137: /* This is the kind of divide that is easiest to do in the general case. */
1138: #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1139:
1140: /* Define this as 1 if `char' should by default be signed; else as 0. */
1141: #define DEFAULT_SIGNED_CHAR 0
1142:
1143: /* This flag, if defined, says the same insns that convert to a signed fixnum
1144: also convert validly to an unsigned one.
1145:
1146: We actually lie a bit here as overflow conditions are different. But
1147: they aren't being checked anyway. */
1148:
1149: #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
1150:
1151: /* Max number of bytes we can move to of from memory
1152: in one reasonably fast instruction.
1153:
1154: For the 29k, we will define movti, so put this at 4 words. */
1155: #define MOVE_MAX 16
1156:
1157: /* Largest number of bytes of an object that can be placed in a register.
1158: On the 29k we have plenty of registers, so use TImode. */
1159: #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1160:
1161: /* Nonzero if access to memory by bytes is no faster than for words.
1162: Also non-zero if doing byte operations (specifically shifts) in registers
1163: is undesirable.
1164:
1165: On the 29k, large masks are expensive, so we want to use bytes to
1166: manipulate fields. */
1167: #define SLOW_BYTE_ACCESS 0
1168:
1169: /* Define if normal loads of shorter-than-word items from memory clears
1170: the rest of the bigs in the register. */
1171: #define BYTE_LOADS_ZERO_EXTEND
1172:
1173: /* This uses COFF, so it wants SDB format. */
1174: #define SDB_DEBUGGING_INFO
1175:
1176: /* Define this to be the delimiter between SDB sub-sections. The default
1177: is ";". */
1178: #define SDB_DELIM "\n"
1179:
1180: /* Do not break .stabs pseudos into continuations. */
1181: #define DBX_CONTIN_LENGTH 0
1182:
1183: /* Don't try to use the `x' type-cross-reference character in DBX data.
1184: Also has the consequence of putting each struct, union or enum
1185: into a separate .stabs, containing only cross-refs to the others. */
1186: #define DBX_NO_XREFS
1187:
1188: /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1189: is done just by pretending it is already truncated. */
1190: #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1191:
1192: /* We assume that the store-condition-codes instructions store 0 for false
1193: and some other value for true. This is the value stored for true. */
1194:
1195: #define STORE_FLAG_VALUE 0x80000000
1196:
1197: /* Specify the machine mode that pointers have.
1198: After generation of rtl, the compiler makes no further distinction
1199: between pointers and any other objects of this machine mode. */
1200: #define Pmode SImode
1201:
1202: /* Mode of a function address in a call instruction (for indexing purposes).
1203:
1204: Doesn't matter on 29k. */
1205: #define FUNCTION_MODE SImode
1206:
1207: /* Define this if addresses of constant functions
1208: shouldn't be put through pseudo regs where they can be cse'd.
1209: Desirable on machines where ordinary constants are expensive
1210: but a CALL with constant address is cheap. */
1211: #define NO_FUNCTION_CSE
1212:
1213: /* Define this if shift instructions ignore all but the low-order
1214: few bits. */
1215: #define SHIFT_COUNT_TRUNCATED
1216:
1217: /* Compute the cost of computing a constant rtl expression RTX
1218: whose rtx-code is CODE. The body of this macro is a portion
1219: of a switch statement. If the code is computed here,
1220: return it with a return statement. Otherwise, break from the switch.
1221:
1222: We only care about the cost if it is valid in an insn. The only
1223: constants that cause an insn to generate more than one machine
1224: instruction are those involving floating-point or address. So
1225: only these need be expensive. */
1226:
1.1.1.3 ! root 1227: #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1.1 root 1228: case CONST_INT: \
1229: return 0; \
1230: case CONST: \
1231: case LABEL_REF: \
1232: case SYMBOL_REF: \
1233: return 6; \
1234: case CONST_DOUBLE: \
1235: return GET_MODE (RTX) == SFmode ? 6 : 8;
1236:
1237: /* Provide the costs of a rtl expression. This is in the body of a
1238: switch on CODE.
1239:
1240: All MEMs cost the same if they are valid. This is used to ensure
1241: that (mem (symbol_ref ...)) is placed into a CALL when valid.
1242:
1243: The multiply cost depends on whether this is a 29050 or not. */
1244:
1.1.1.3 ! root 1245: #define RTX_COSTS(X,CODE,OUTER_CODE) \
1.1 root 1246: case MULT: \
1247: return TARGET_29050 ? COSTS_N_INSNS (2) : COSTS_N_INSNS (40); \
1248: case DIV: \
1249: case UDIV: \
1250: case MOD: \
1251: case UMOD: \
1252: return COSTS_N_INSNS (50); \
1253: case MEM: \
1254: return COSTS_N_INSNS (2);
1255:
1256: /* Control the assembler format that we output. */
1257:
1258: /* Output at beginning of assembler file. */
1259:
1260: #define ASM_FILE_START(FILE) \
1261: { char *p, *after_dir = main_input_filename; \
1262: if (TARGET_29050) \
1263: fprintf (FILE, "\t.cputype 29050\n"); \
1264: for (p = main_input_filename; *p; p++) \
1265: if (*p == '/') \
1266: after_dir = p + 1; \
1267: fprintf (FILE, "\t.file \"%s\"\n", after_dir); \
1268: fprintf (FILE, "\t.sect .lit,lit\n"); }
1269:
1270: /* Output to assembler file text saying following lines
1271: may contain character constants, extra white space, comments, etc. */
1272:
1273: #define ASM_APP_ON ""
1274:
1275: /* Output to assembler file text saying following lines
1276: no longer contain unusual constructs. */
1277:
1278: #define ASM_APP_OFF ""
1279:
1.1.1.3 ! root 1280: /* The next few macros don't have tabs on most machines, but
! 1281: at least one 29K assembler wants them. */
! 1282:
1.1 root 1283: /* Output before instructions. */
1284:
1.1.1.3 ! root 1285: #define TEXT_SECTION_ASM_OP "\t.text"
1.1 root 1286:
1287: /* Output before read-only data. */
1288:
1.1.1.3 ! root 1289: #define READONLY_DATA_SECTION_ASM_OP "\t.use .lit"
1.1 root 1290:
1291: /* Output before writable data. */
1292:
1.1.1.3 ! root 1293: #define DATA_SECTION_ASM_OP "\t.data"
1.1 root 1294:
1295: /* Define an extra section for read-only data, a routine to enter it, and
1296: indicate that it is for read-only data. */
1297:
1298: #define EXTRA_SECTIONS readonly_data
1299:
1300: #define EXTRA_SECTION_FUNCTIONS \
1301: void \
1302: literal_section () \
1303: { \
1304: if (in_section != readonly_data) \
1305: { \
1306: fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \
1307: in_section = readonly_data; \
1308: } \
1309: } \
1310:
1311: #define READONLY_DATA_SECTION literal_section
1312:
1313: /* How to refer to registers in assembler output.
1314: This sequence is indexed by compiler's hard-register-number (see above). */
1315:
1316: #define REGISTER_NAMES \
1317: {"gr96", "gr97", "gr98", "gr99", "gr100", "gr101", "gr102", "gr103", "gr104", \
1318: "gr105", "gr106", "gr107", "gr108", "gr109", "gr110", "gr111", "gr112", \
1319: "gr113", "gr114", "gr115", "gr116", "gr117", "gr118", "gr119", "gr120", \
1320: "gr121", "gr122", "gr123", "gr124", "gr125", "gr126", "gr127", \
1321: "lr0", "lr1", "lr2", "lr3", "lr4", "lr5", "lr6", "lr7", "lr8", "lr9", \
1322: "lr10", "lr11", "lr12", "lr13", "lr14", "lr15", "lr16", "lr17", "lr18", \
1323: "lr19", "lr20", "lr21", "lr22", "lr23", "lr24", "lr25", "lr26", "lr27", \
1324: "lr28", "lr29", "lr30", "lr31", "lr32", "lr33", "lr34", "lr35", "lr36", \
1325: "lr37", "lr38", "lr39", "lr40", "lr41", "lr42", "lr43", "lr44", "lr45", \
1326: "lr46", "lr47", "lr48", "lr49", "lr50", "lr51", "lr52", "lr53", "lr54", \
1327: "lr55", "lr56", "lr57", "lr58", "lr59", "lr60", "lr61", "lr62", "lr63", \
1328: "lr64", "lr65", "lr66", "lr67", "lr68", "lr69", "lr70", "lr71", "lr72", \
1329: "lr73", "lr74", "lr75", "lr76", "lr77", "lr78", "lr79", "lr80", "lr81", \
1330: "lr82", "lr83", "lr84", "lr85", "lr86", "lr87", "lr88", "lr89", "lr90", \
1331: "lr91", "lr92", "lr93", "lr94", "lr95", "lr96", "lr97", "lr98", "lr99", \
1332: "lr100", "lr101", "lr102", "lr103", "lr104", "lr105", "lr106", "lr107", \
1333: "lr108", "lr109", "lr110", "lr111", "lr112", "lr113", "lr114", "lr115", \
1334: "lr116", "lr117", "lr118", "lr119", "lr120", "lr121", "lr122", "lr123", \
1335: "lr124", "lr125", "lr126", "lr127", \
1336: "AI0", "AI1", "AI2", "AI3", "AI4", "AI5", "AI6", "AI7", "AI8", "AI9", \
1337: "AI10", "AI11", "AI12", "AI13", "AI14", "AI15", "FP", \
1338: "bp", "fc", "cr", "q", \
1339: "vab", "ops", "cps", "cfg", "cha", "chd", "chc", "rbp", "tmc", "tmr", \
1340: "pc0", "pc1", "pc2", "mmu", "lru", "fpe", "int", "fps", "exo", \
1341: "0", "1", "2", "3" }
1342:
1343: /* How to renumber registers for dbx and gdb. */
1344:
1345: extern int a29k_debug_reg_map[];
1346: #define DBX_REGISTER_NUMBER(REGNO) a29k_debug_reg_map[REGNO]
1347:
1348: /* This is how to output the definition of a user-level label named NAME,
1349: such as the label on a static function or variable NAME. */
1350:
1351: #define ASM_OUTPUT_LABEL(FILE,NAME) \
1352: do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1353:
1354: /* This is how to output a command to make the user-level label named NAME
1355: defined for reference from other files. */
1356:
1357: #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1358: do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1359:
1360: /* This is how to output a reference to a user-level label named NAME.
1361: `assemble_name' uses this. */
1362:
1363: #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1364: fprintf (FILE, "_%s", NAME)
1365:
1366: /* This is how to output an internal numbered label where
1367: PREFIX is the class of label and NUM is the number within the class. */
1368:
1369: #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1370: fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1371:
1372: /* This is how to output a label for a jump table. Arguments are the same as
1373: for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
1374: passed. */
1375:
1376: #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \
1377: { ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
1378:
1379: /* This is how to store into the string LABEL
1380: the symbol_ref name of an internal numbered label where
1381: PREFIX is the class of label and NUM is the number within the class.
1382: This is suitable for output with `assemble_name'. */
1383:
1384: #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1385: sprintf (LABEL, "*%s%d", PREFIX, NUM)
1386:
1387: /* This is how to output an assembler line defining a `double' constant. */
1388:
1389: #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1390: fprintf (FILE, "\t.double %.20e\n", (VALUE))
1391:
1392: /* This is how to output an assembler line defining a `float' constant. */
1393:
1394: #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1395: fprintf (FILE, "\t.float %.20e\n", (VALUE))
1396:
1397: /* This is how to output an assembler line defining an `int' constant. */
1398:
1399: #define ASM_OUTPUT_INT(FILE,VALUE) \
1400: ( fprintf (FILE, "\t.word "), \
1401: output_addr_const (FILE, (VALUE)), \
1402: fprintf (FILE, "\n"))
1403:
1404: /* Likewise for `char' and `short' constants. */
1405:
1406: #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1407: ( fprintf (FILE, "\t.hword "), \
1408: output_addr_const (FILE, (VALUE)), \
1409: fprintf (FILE, "\n"))
1410:
1411: #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1412: ( fprintf (FILE, "\t.byte "), \
1413: output_addr_const (FILE, (VALUE)), \
1414: fprintf (FILE, "\n"))
1415:
1416: /* This is how to output an insn to push a register on the stack.
1417: It need not be very fast code. */
1418:
1419: #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1420: fprintf (FILE, "\tsub %s,%s,4\n\tstore 0,0,%s,%s\n", \
1421: reg_names[R_MSP], reg_names[R_MSP], reg_names[REGNO], \
1422: reg_names[R_MSP]);
1423:
1424: /* This is how to output an insn to pop a register from the stack.
1425: It need not be very fast code. */
1426:
1427: #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1428: fprintf (FILE, "\tload 0,0,%s,%s\n\tadd %s,%s,4\n", \
1429: reg_names[REGNO], reg_names[R_MSP], reg_names[R_MSP], \
1430: reg_names[R_MSP]);
1431:
1432: /* This is how to output an assembler line for a numeric constant byte. */
1433:
1434: #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1435: fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1436:
1437: /* This is how to output an element of a case-vector that is absolute. */
1438:
1439: #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1440: fprintf (FILE, "\t.word L%d\n", VALUE)
1441:
1442: /* This is how to output an element of a case-vector that is relative.
1443: (29k does not use such vectors,
1444: but we must define this macro anyway.) */
1445:
1446: #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) abort ()
1447:
1448: /* This is how to output an assembler line
1449: that says to advance the location counter
1450: to a multiple of 2**LOG bytes. */
1451:
1452: #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1453: if ((LOG) != 0) \
1454: fprintf (FILE, "\t.align %d\n", 1 << (LOG))
1455:
1456: #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1457: fprintf (FILE, "\t.block %d\n", (SIZE))
1458:
1459: /* This says how to output an assembler line
1460: to define a global common symbol. */
1461:
1462: #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1463: ( fputs ("\t.comm ", (FILE)), \
1464: assemble_name ((FILE), (NAME)), \
1465: fprintf ((FILE), ",%d\n", (SIZE)))
1466:
1467: /* This says how to output an assembler line
1468: to define a local common symbol. */
1469:
1470: #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
1471: ( fputs ("\t.lcomm ", (FILE)), \
1472: assemble_name ((FILE), (NAME)), \
1473: fprintf ((FILE), ",%d\n", (SIZE)))
1474:
1475: /* Store in OUTPUT a string (made with alloca) containing
1476: an assembler-name for a local static variable named NAME.
1477: LABELNO is an integer which is different for each call. */
1478:
1479: #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1480: ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1481: sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1482:
1483: /* Define the parentheses used to group arithmetic operations
1484: in assembler code. */
1485:
1486: #define ASM_OPEN_PAREN "("
1487: #define ASM_CLOSE_PAREN ")"
1488:
1489: /* Define results of standard character escape sequences. */
1490: #define TARGET_BELL 007
1491: #define TARGET_BS 010
1492: #define TARGET_TAB 011
1493: #define TARGET_NEWLINE 012
1494: #define TARGET_VT 013
1495: #define TARGET_FF 014
1496: #define TARGET_CR 015
1497:
1498: /* Print operand X (an rtx) in assembler syntax to file FILE.
1499: CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1500: For `%' followed by punctuation, CODE is the punctuation and X is null. */
1501:
1502: #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1503:
1504: /* Determine which codes are valid without a following integer. These must
1505: not be alphabetic.
1506:
1507: We support `#' which is null if a delay slot exists, otherwise
1508: "\n\tnop" and `*' which prints the register name for TPC (gr122). */
1509:
1510: #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '#' || (CODE) == '*')
1511:
1512: /* Print a memory address as an operand to reference that memory location. */
1513:
1514: #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1515: { register rtx addr = ADDR; \
1516: if (!REG_P (addr) \
1517: && ! (GET_CODE (addr) == CONST_INT \
1518: && INTVAL (addr) >= 0 && INTVAL (addr) < 256)) \
1519: abort (); \
1520: output_operand (addr, 0); \
1521: }
1522: /* Define the codes that are matched by predicates in a29k.c. */
1523:
1524: #define PREDICATE_CODES \
1525: {"cint_8_operand", {CONST_INT}}, \
1526: {"cint_16_operand", {CONST_INT}}, \
1527: {"long_const_operand", {CONST_INT, CONST, CONST_DOUBLE, \
1528: LABEL_REF, SYMBOL_REF}}, \
1529: {"shift_constant_operand", {CONST_INT, ASHIFT}}, \
1530: {"const_0__operand", {CONST_INT, ASHIFT}}, \
1531: {"const_8__operand", {CONST_INT, ASHIFT}}, \
1532: {"const_16__operand", {CONST_INT, ASHIFT}}, \
1533: {"const_24__operand", {CONST_INT, ASHIFT}}, \
1534: {"float_const_operand", {CONST_DOUBLE}}, \
1.1.1.3 ! root 1535: {"gpc_reg_operand", {SUBREG, REG}}, \
! 1536: {"gpc_reg_or_float_constant_operand", {SUBREG, REG, CONST_DOUBLE}}, \
! 1537: {"gpc_reg_or_integer_constant_operand", {SUBREG, REG, \
1.1 root 1538: CONST_INT, CONST_DOUBLE}}, \
1539: {"spec_reg_operand", {REG}}, \
1540: {"accum_reg_operand", {REG}}, \
1541: {"srcb_operand", {SUBREG, REG, CONST_INT}}, \
1542: {"reg_or_immediate_operand", {SUBREG, REG, CONST_INT, CONST, \
1543: CONST_DOUBLE, CONST, SYMBOL_REF, LABEL_REF}}, \
1544: {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \
1545: {"and_operand", {SUBREG, REG, CONST_INT}}, \
1546: {"add_operand", {SUBREG, REG, CONST_INT}}, \
1547: {"in_operand", {SUBREG, MEM, REG, CONST_INT, CONST, SYMBOL_REF, \
1548: LABEL_REF, CONST_DOUBLE}}, \
1549: {"out_operand", {SUBREG, REG, MEM}}, \
1550: {"extend_operator", {ZERO_EXTEND, SIGN_EXTEND}}, \
1551: {"fp_comparison_operator", {EQ, GT, GE}}, \
1552: {"branch_operator", {GE, LT}}, \
1553: {"epilogue_operand", {CODE_LABEL}},
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