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1.1 ! root 1: ;;- Machine description for AMD Am29000 for GNU C compiler ! 2: ;; Copyright (C) 1991 Free Software Foundation, Inc. ! 3: ;; Contributed by Richard Kenner ([email protected]) ! 4: ! 5: ;; This file is part of GNU CC. ! 6: ! 7: ;; GNU CC is free software; you can redistribute it and/or modify ! 8: ;; it under the terms of the GNU General Public License as published by ! 9: ;; the Free Software Foundation; either version 2, or (at your option) ! 10: ;; any later version. ! 11: ! 12: ;; GNU CC is distributed in the hope that it will be useful, ! 13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ! 14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! 15: ;; GNU General Public License for more details. ! 16: ! 17: ;; You should have received a copy of the GNU General Public License ! 18: ;; along with GNU CC; see the file COPYING. If not, write to ! 19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ! 20: ! 21: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ! 22: ! 23: ;; The insns in this file are presented in the same order as the AMD 29000 ! 24: ;; User's Manual (i.e., alphabetical by machine op-code). ! 25: ;; ! 26: ;; DEFINE_EXPAND's are located near the first occurrance of the major insn ! 27: ;; that they generate. ! 28: ! 29: ;; The only attribute we have is the type. We only care about calls, branches, ! 30: ;; loads, stores, floating-point operations, and multi-word insns. ! 31: ;; Everything else is miscellaneous. ! 32: ! 33: (define_attr "type" ! 34: "call,branch,load,store,fadd,fmul,fam,fdiv,dmul,dam,ddiv,multi,misc" ! 35: (const_string "misc")) ! 36: ! 37: ;; ASM insns cannot go into a delay slot, so call them "multi". ! 38: (define_asm_attributes [(set_attr "type" "multi")]) ! 39: ! 40: (define_attr "in_delay_slot" "yes,no" ! 41: (if_then_else (eq_attr "type" "call,branch,multi") (const_string "no") ! 42: (const_string "yes"))) ! 43: ! 44: ;; Branch and call insns require a single delay slot. Annulling is not ! 45: ;; supported. ! 46: (define_delay (eq_attr "type" "call,branch") ! 47: [(eq_attr "in_delay_slot" "yes") (nil) (nil)]) ! 48: ! 49: ;; Define the function unit usages. We first define memory as a unit. ! 50: (define_function_unit "memory" 1 2 (eq_attr "type" "load") 6 11) ! 51: (define_function_unit "memory" 1 2 (eq_attr "type" "store") 1 0) ! 52: ! 53: ;; Now define the function units for the floating-point support. Most ! 54: ;; units are pipelined and can accept an input every cycle. ! 55: ;; ! 56: ;; Note that we have an inaccuracy here. If a fmac insn is issued, followed ! 57: ;; 2 cycles later by a fadd, there will be a conflict for the floating ! 58: ;; adder that we can't represent. Also, all insns will conflict for the ! 59: ;; floating-point rounder. It isn't clear how to represent this. ! 60: ! 61: (define_function_unit "multiplier" 1 0 (eq_attr "type" "fmul") 3 0) ! 62: (define_function_unit "multiplier" 1 0 (eq_attr "type" "dmul") 6 8) ! 63: (define_function_unit "multiplier" 1 0 (eq_attr "type" "fam") 6 8) ! 64: (define_function_unit "multiplier" 1 0 (eq_attr "type" "dam") 9 8) ! 65: ! 66: (define_function_unit "adder" 1 0 (eq_attr "type" "fadd,fam,dam") 3 0) ! 67: ! 68: (define_function_unit "divider" 1 1 (eq_attr "type" "fdiv") 11 20) ! 69: (define_function_unit "divider" 1 1 (eq_attr "type" "ddiv") 18 34) ! 70: ! 71: ;; ADD ! 72: (define_insn "addsi3" ! 73: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") ! 74: (plus:SI (match_operand:SI 1 "gen_reg_operand" "%r,r") ! 75: (match_operand:SI 2 "add_operand" "rI,N")))] ! 76: "" ! 77: "@ ! 78: add %0,%1,%2 ! 79: sub %0,%1,%n2") ! 80: ! 81: (define_insn "adddi3" ! 82: [(set (match_operand:DI 0 "gen_reg_operand" "=r") ! 83: (plus:DI (match_operand:DI 1 "gen_reg_operand" "%r") ! 84: (match_operand:DI 2 "gen_reg_operand" "r")))] ! 85: "" ! 86: "add %L0,%L1,%L2\;addc %0,%1,%2" ! 87: [(set_attr "type" "multi")]) ! 88: ! 89: ;; AND/ANDN ! 90: (define_insn "andsi3" ! 91: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") ! 92: (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r") ! 93: (match_operand:SI 2 "and_operand" "rI,K")))] ! 94: "" ! 95: "@ ! 96: and %0,%1,%2 ! 97: andn %0,%1,%C2") ! 98: ! 99: (define_insn "" ! 100: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 101: (and:SI (not:SI (match_operand:SI 1 "srcb_operand" "rI")) ! 102: (match_operand:SI 2 "gen_reg_operand" "r")))] ! 103: "" ! 104: "andn %0,%2,%1") ! 105: ! 106: ! 107: ;; CALLI ! 108: ;; ! 109: ;; Start with a subroutine to write out CLOBBERs starting at lr2 up to, ! 110: ;; but not including, the next parameter register. If operand[0] is null, ! 111: ;; it means that all the argument registers have been used. ! 112: (define_expand "clobbers_to" ! 113: [(clobber (match_operand:SI 0 "" ""))] ! 114: "" ! 115: " ! 116: { ! 117: int i; ! 118: int high_regno; ! 119: ! 120: if (operands[0] == 0) ! 121: high_regno = R_LR (18); ! 122: else if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) < R_LR (0) ! 123: || REGNO (operands[0]) > R_LR (18)) ! 124: abort (); ! 125: else ! 126: high_regno = REGNO (operands[0]); ! 127: ! 128: for (i = R_LR (2); i < high_regno; i++) ! 129: emit_insn (gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, i))); ! 130: ! 131: DONE; ! 132: }") ! 133: ! 134: (define_expand "call" ! 135: [(parallel [(call (match_operand:SI 0 "" "") ! 136: (match_operand 1 "" "")) ! 137: (clobber (reg:SI 32))]) ! 138: (match_operand 2 "" "")] ! 139: "" ! 140: " ! 141: { ! 142: if (GET_CODE (operands[0]) != MEM) ! 143: abort (); ! 144: ! 145: if (! TARGET_SMALL_MEMORY ! 146: && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) ! 147: operands[0] = gen_rtx (MEM, GET_MODE (operands[0]), ! 148: force_reg (Pmode, XEXP (operands[0], 0))); ! 149: ! 150: operands[2] = gen_clobbers_to (operands[2]); ! 151: }") ! 152: ! 153: (define_insn "" ! 154: [(call (match_operand:SI 0 "memory_operand" "m") ! 155: (match_operand 1 "" "")) ! 156: (clobber (reg:SI 32))] ! 157: "" ! 158: "calli lr0,%0%#" ! 159: [(set_attr "type" "call")]) ! 160: ! 161: (define_expand "call_value" ! 162: [(parallel [(set (match_operand:SI 0 "gen_reg_operand" "") ! 163: (call (match_operand:SI 1 "" "") ! 164: (match_operand 2 "" ""))) ! 165: (clobber (reg:SI 32))]) ! 166: (match_operand 3 "" "")] ! 167: "" ! 168: " ! 169: { ! 170: if (GET_CODE (operands[1]) != MEM) ! 171: abort (); ! 172: ! 173: if (! TARGET_SMALL_MEMORY ! 174: && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) ! 175: operands[1] = gen_rtx (MEM, GET_MODE (operands[1]), ! 176: force_reg (Pmode, XEXP (operands[1], 0))); ! 177: ! 178: operands[3] = gen_clobbers_to (operands[3]); ! 179: }") ! 180: ! 181: (define_insn "" ! 182: [(set (match_operand 0 "gen_reg_operand" "=r") ! 183: (call (match_operand:SI 1 "memory_operand" "m") ! 184: (match_operand 2 "" ""))) ! 185: (clobber (reg:SI 32))] ! 186: "" ! 187: "calli lr0,%1%#" ! 188: [(set_attr "type" "call")]) ! 189: ! 190: (define_insn "" ! 191: [(call (mem:SI (match_operand:SI 0 "immediate_operand" "i")) ! 192: (match_operand:SI 1 "general_operand" "g")) ! 193: (clobber (reg:SI 32))] ! 194: "GET_CODE (operands[0]) == SYMBOL_REF ! 195: && (TARGET_SMALL_MEMORY ! 196: || ! strcmp (XSTR (operands[0], 0), current_function_name))" ! 197: "call lr0,%F0" ! 198: [(set_attr "type" "call")]) ! 199: ! 200: (define_insn "" ! 201: [(set (match_operand 0 "gen_reg_operand" "=r") ! 202: (call (mem:SI (match_operand:SI 1 "immediate_operand" "i")) ! 203: (match_operand:SI 2 "general_operand" "g"))) ! 204: (clobber (reg:SI 32))] ! 205: "GET_CODE (operands[1]) == SYMBOL_REF ! 206: && (TARGET_SMALL_MEMORY ! 207: || ! strcmp (XSTR (operands[1], 0), current_function_name))" ! 208: "call lr0,%F1" ! 209: [(set_attr "type" "call")]) ! 210: ! 211: (define_expand "probe" ! 212: [(call (mem:SI (symbol_ref:SI "_msp_check")) ! 213: (const_int 1))] ! 214: "TARGET_STACK_CHECK" ! 215: "") ! 216: ! 217: ;; This is used for internal routine calls via TPC. Currently used only ! 218: ;; in probe, above. ! 219: (define_insn "" ! 220: [(call (mem:SI (match_operand:SI 0 "immediate_operand" "s")) ! 221: (const_int 1))] ! 222: "" ! 223: "call %*,%0" ! 224: [(set_attr "type" "call")]) ! 225: ! 226: ;; CONST, CONSTH, CONSTN ! 227: ;; ! 228: ;; Many of these are generated from move insns. ! 229: (define_insn "" ! 230: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 231: (and:SI (match_operand:SI 1 "immediate_operand" "i") ! 232: (const_int 65535)))] ! 233: "" ! 234: "const %0,%1") ! 235: ! 236: (define_insn "" ! 237: [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r") ! 238: (const_int 16) ! 239: (match_operand:SI 1 "const_0_operand" "")) ! 240: (ashiftrt:SI (match_operand:SI 2 "immediate_operand" "i") ! 241: (const_int 16)))] ! 242: "" ! 243: "consth %0,%2") ! 244: ! 245: (define_insn "" ! 246: [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r") ! 247: (const_int 16) ! 248: (match_operand:SI 1 "const_0_operand" "")) ! 249: (match_operand:SI 2 "cint_16_operand" "J"))] ! 250: "" ! 251: "* ! 252: { operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) << 16); ! 253: return \"consth %0,%2\"; ! 254: }") ! 255: ! 256: (define_insn "" ! 257: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 258: (ior:SI (and:SI (match_operand:SI 1 "gen_reg_operand" "0") ! 259: (const_int 65535)) ! 260: (match_operand:SI 2 "const_int_operand" "n")))] ! 261: "(INTVAL (operands[1]) & 0xffff) == 0" ! 262: "consth %0,%2") ! 263: ! 264: (define_insn "" ! 265: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 266: (ior:SI (and:SI (match_operand:SI 1 "gen_reg_operand" "0") ! 267: (const_int 65535)) ! 268: (and:SI (match_operand:SI 2 "immediate_operand" "i") ! 269: (const_int -65536))))] ! 270: "" ! 271: "consth %0,%2") ! 272: ! 273: ! 274: ;; CONVERT ! 275: (define_insn "fix_truncsfsi2" ! 276: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 277: (fix:SI (match_operand:SF 1 "register_operand" "r")))] ! 278: "" ! 279: "convert %0,%1,0,3,0,1") ! 280: ! 281: (define_insn "fix_truncdfsi2" ! 282: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 283: (fix:SI (match_operand:DF 1 "register_operand" "r")))] ! 284: "" ! 285: "convert %0,%1,0,3,0,2") ! 286: ! 287: (define_insn "fixuns_truncsfsi2" ! 288: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 289: (unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))] ! 290: "" ! 291: "convert %0,%1,1,3,0,1") ! 292: ! 293: (define_insn "fixuns_truncdfsi2" ! 294: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 295: (unsigned_fix:SI (match_operand:DF 1 "register_operand" "r")))] ! 296: "" ! 297: "convert %0,%1,1,3,0,2") ! 298: ! 299: (define_insn "truncdfsf2" ! 300: [(set (match_operand:SF 0 "register_operand" "=r") ! 301: (float_truncate:SF (match_operand:DF 1 "register_operand" "r")))] ! 302: "" ! 303: "convert %0,%1,0,4,1,2") ! 304: ! 305: (define_insn "extendsfdf2" ! 306: [(set (match_operand:DF 0 "register_operand" "=r") ! 307: (float_extend:DF (match_operand:SF 1 "register_operand" "r")))] ! 308: "" ! 309: "convert %0,%1,0,4,2,1") ! 310: ! 311: (define_insn "floatsisf2" ! 312: [(set (match_operand:SF 0 "register_operand" "=r") ! 313: (float:SF (match_operand:SI 1 "gen_reg_operand" "r")))] ! 314: "" ! 315: "convert %0,%1,0,4,1,0") ! 316: ! 317: (define_insn "floatsidf2" ! 318: [(set (match_operand:DF 0 "register_operand" "=r") ! 319: (float:DF (match_operand:SI 1 "gen_reg_operand" "r")))] ! 320: "" ! 321: "convert %0,%1,0,4,2,0") ! 322: ! 323: (define_insn "floatunssisf2" ! 324: [(set (match_operand:SF 0 "register_operand" "=r") ! 325: (unsigned_float:SF (match_operand:SI 1 "gen_reg_operand" "r")))] ! 326: "" ! 327: "convert %0,%1,1,4,1,0") ! 328: ! 329: (define_insn "floatunssidf2" ! 330: [(set (match_operand:DF 0 "register_operand" "=r") ! 331: (unsigned_float:DF (match_operand:SI 1 "gen_reg_operand" "r")))] ! 332: "" ! 333: "convert %0,%1,1,4,2,0") ! 334: ! 335: ;; CPxxx, DEQ, DGT, DGE, FEQ, FGT, FGE ! 336: (define_insn "" ! 337: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 338: (match_operator 3 "comparison_operator" ! 339: [(match_operand:SI 1 "gen_reg_operand" "r") ! 340: (match_operand:SI 2 "srcb_operand" "rI")]))] ! 341: "" ! 342: "cp%J3 %0,%1,%2") ! 343: ! 344: (define_insn "" ! 345: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 346: (match_operator 3 "fp_comparison_operator" ! 347: [(match_operand:SF 1 "register_operand" "r") ! 348: (match_operand:SF 2 "register_operand" "r")]))] ! 349: "" ! 350: "f%J3 %0,%1,%2" ! 351: [(set_attr "type" "fadd")]) ! 352: ! 353: (define_insn "" ! 354: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 355: (match_operator 3 "fp_comparison_operator" ! 356: [(match_operand:DF 1 "register_operand" "r") ! 357: (match_operand:DF 2 "register_operand" "r")]))] ! 358: "" ! 359: "d%J3 %0,%1,%2" ! 360: [(set_attr "type" "fadd")]) ! 361: ! 362: ;; DADD ! 363: (define_expand "adddf3" ! 364: [(set (match_operand:DF 0 "register_operand" "") ! 365: (plus:DF (match_operand:DF 1 "register_operand" "") ! 366: (match_operand:DF 2 "register_operand" "")))] ! 367: "" ! 368: "") ! 369: ! 370: (define_insn "" ! 371: [(set (match_operand:DF 0 "register_operand" "=r") ! 372: (plus:DF (match_operand:DF 1 "register_operand" "%r") ! 373: (match_operand:DF 2 "register_operand" "r")))] ! 374: "! TARGET_29050 " ! 375: "dadd %0,%1,%2" ! 376: [(set_attr "type" "fadd")]) ! 377: ! 378: (define_insn "" ! 379: [(set (match_operand:DF 0 "register_operand" "=r,a") ! 380: (plus:DF (match_operand:DF 1 "register_operand" "%r,r") ! 381: (match_operand:DF 2 "register_operand" "r,0")))] ! 382: "TARGET_29050" ! 383: "@ ! 384: dadd %0,%1,%2 ! 385: dmac 8,%0,%1,0" ! 386: [(set_attr "type" "fadd,dam")]) ! 387: ! 388: ;; DDIV ! 389: (define_insn "divdf3" ! 390: [(set (match_operand:DF 0 "register_operand" "=r") ! 391: (div:DF (match_operand:DF 1 "register_operand" "=r") ! 392: (match_operand:DF 2 "register_operand" "r")))] ! 393: "" ! 394: "ddiv %0,%1,%2" ! 395: [(set_attr "type" "ddiv")]) ! 396: ! 397: ;; DIVIDE ! 398: ;; ! 399: ;; We must set Q to the sign extension of the dividend first. For MOD, we ! 400: ;; must get the remainder from Q. ! 401: ;; ! 402: ;; For divmod: operand 1 is divided by operand 2; quotient goes to operand ! 403: ;; 0 and remainder to operand 3. ! 404: (define_expand "divmodsi4" ! 405: [(set (match_dup 4) ! 406: (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "") ! 407: (const_int 31))) ! 408: (parallel [(set (match_operand:SI 0 "gen_reg_operand" "") ! 409: (div:SI (match_dup 1) ! 410: (match_operand:SI 2 "gen_reg_operand" ""))) ! 411: (set (match_operand:SI 3 "gen_reg_operand" "") ! 412: (mod:SI (match_dup 1) ! 413: (match_dup 2))) ! 414: (use (match_dup 4))])] ! 415: "" ! 416: " ! 417: { ! 418: operands[4] = gen_reg_rtx (SImode); ! 419: }") ! 420: ! 421: (define_insn "" ! 422: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 423: (div:SI (match_operand:SI 1 "gen_reg_operand" "r") ! 424: (match_operand:SI 2 "gen_reg_operand" "r"))) ! 425: (set (match_operand:SI 3 "register_operand" "=q") ! 426: (mod:SI (match_dup 1) ! 427: (match_dup 2))) ! 428: (use (match_operand:SI 4 "register_operand" "3"))] ! 429: "" ! 430: "divide %0,%1,%2") ! 431: ! 432: ;; DIVIDU ! 433: ;; ! 434: ;; Similar to DIVIDE. ! 435: (define_expand "udivmodsi4" ! 436: [(parallel [(set (match_operand:SI 0 "gen_reg_operand" "") ! 437: (udiv:SI (match_operand:SI 1 "gen_reg_operand" "") ! 438: (match_operand:SI 2 "gen_reg_operand" ""))) ! 439: (set (match_operand:SI 3 "gen_reg_operand" "") ! 440: (umod:SI (match_dup 1) ! 441: (match_dup 2))) ! 442: (use (const_int 0))])] ! 443: "" ! 444: "") ! 445: ! 446: (define_insn "" ! 447: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 448: (udiv:SI (match_operand:SI 1 "gen_reg_operand" "r") ! 449: (match_operand:SI 2 "gen_reg_operand" "r"))) ! 450: (set (match_operand:SI 3 "register_operand" "=q") ! 451: (umod:SI (match_dup 1) ! 452: (match_dup 2))) ! 453: (use (match_operand:SI 4 "const_int_operand" "3"))] ! 454: "" ! 455: "dividu %0,%1,%2") ! 456: ! 457: ;; DMAC/DMSM ! 458: (define_insn "" ! 459: [(set (match_operand:DF 0 "register_operand" "=a,*r") ! 460: (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%r,A") ! 461: (match_operand:DF 2 "register_operand" "r,r")) ! 462: (match_operand:DF 3 "register_operand" "0,*r")))] ! 463: "TARGET_29050" ! 464: "@ ! 465: dmac 0,%0,%1,%2 ! 466: dmsm %0,%2,%3" ! 467: [(set_attr "type" "dam")]) ! 468: ! 469: (define_insn "" ! 470: [(set (match_operand:DF 0 "register_operand" "=a") ! 471: (plus:DF (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "r")) ! 472: (match_operand:DF 2 "register_operand" "r")) ! 473: (match_operand:DF 3 "register_operand" "0")))] ! 474: "TARGET_29050" ! 475: "dmac 1,%0,%2,%1" ! 476: [(set_attr "type" "dam")]) ! 477: ! 478: (define_insn "" ! 479: [(set (match_operand:DF 0 "register_operand" "=a") ! 480: (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "%r") ! 481: (match_operand:DF 2 "register_operand" "r")) ! 482: (match_operand:DF 3 "register_operand" "0")))] ! 483: "TARGET_29050" ! 484: "dmac 2,%0,%1,%2" ! 485: [(set_attr "type" "dam")]) ! 486: ! 487: (define_insn "" ! 488: [(set (match_operand:DF 0 "register_operand" "=a") ! 489: (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "r") ! 490: (neg:DF (match_operand:DF 2 "register_operand" "r"))) ! 491: (match_operand:DF 3 "register_operand" "0")))] ! 492: "TARGET_29050" ! 493: "dmac 3,%0,%1,%2" ! 494: [(set_attr "type" "dam")]) ! 495: ! 496: (define_insn "" ! 497: [(set (match_operand:DF 0 "register_operand" "=a") ! 498: (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "r")) ! 499: (match_operand:DF 2 "register_operand" "r")))] ! 500: "TARGET_29050" ! 501: "dmac 5,%0,%2,%1" ! 502: [(set_attr "type" "dam")]) ! 503: ! 504: (define_insn "" ! 505: [(set (match_operand:DF 0 "register_operand" "=a") ! 506: (minus:DF (neg:DF (match_operand:DF 1 "register_operand" "r")) ! 507: (match_operand:DF 2 "register_operand" "0")))] ! 508: "TARGET_29050" ! 509: "dmac 11,%0,%1,0" ! 510: [(set_attr "type" "dam")]) ! 511: ! 512: (define_insn "" ! 513: [(set (match_operand:DF 0 "register_operand" "=a") ! 514: (neg:DF (plus:DF (match_operand:DF 1 "register_operand" "%r") ! 515: (match_operand:DF 2 "register_operand" "0"))))] ! 516: "TARGET_29050" ! 517: "dmac 11,%0,%1,0" ! 518: [(set_attr "type" "dam")]) ! 519: ! 520: (define_insn "" ! 521: [(set (match_operand:DF 0 "register_operand" "=r,r,a") ! 522: (neg:DF (match_operand:DF 1 "register_operand" "0,r,r"))) ! 523: (clobber (match_scratch:SI 2 "=&r,&r,X"))] ! 524: "TARGET_29050" ! 525: "@ ! 526: cpeq %2,gr1,gr1\;xor %0,%1,%2 ! 527: cpeq %2,gr1,gr1\;xor %0,%1,%2\;sll %L0,%L1,0 ! 528: dmac 13,%0,%1,0" ! 529: [(set_attr "type" "multi,multi,dam")]) ! 530: ! 531: ;; DMUL ! 532: (define_expand "muldf3" ! 533: [(set (match_operand:DF 0 "register_operand" "") ! 534: (mult:DF (match_operand:DF 1 "register_operand" "") ! 535: (match_operand:DF 2 "register_operand" "")))] ! 536: "" ! 537: "") ! 538: ! 539: (define_insn "" ! 540: [(set (match_operand:DF 0 "register_operand" "=r") ! 541: (mult:DF (match_operand:DF 1 "register_operand" "%r") ! 542: (match_operand:DF 2 "register_operand" "r")))] ! 543: "! TARGET_29050" ! 544: "dmul %0,%1,%2" ! 545: [(set_attr "type" "dmul")]) ! 546: ! 547: (define_insn "" ! 548: [(set (match_operand:DF 0 "register_operand" "=r,a") ! 549: (mult:DF (match_operand:DF 1 "register_operand" "%r,r") ! 550: (match_operand:DF 2 "register_operand" "r,r")))] ! 551: "TARGET_29050" ! 552: "@ ! 553: dmul %0,%1,%2 ! 554: dmac 4,%0,%1,%2" ! 555: [(set_attr "type" "dmul,dam")]) ! 556: ! 557: ;; DSUB ! 558: (define_expand "subdf3" ! 559: [(set (match_operand:DF 0 "register_operand" "=r") ! 560: (minus:DF (match_operand:DF 1 "register_operand" "r") ! 561: (match_operand:DF 2 "register_operand" "r")))] ! 562: "" ! 563: "") ! 564: ! 565: (define_insn "" ! 566: [(set (match_operand:DF 0 "register_operand" "=r") ! 567: (minus:DF (match_operand:DF 1 "register_operand" "r") ! 568: (match_operand:DF 2 "register_operand" "r")))] ! 569: "! TARGET_29050" ! 570: "dsub %0,%1,%2" ! 571: [(set_attr "type" "fadd")]) ! 572: ! 573: (define_insn "" ! 574: [(set (match_operand:DF 0 "register_operand" "=r,a,a") ! 575: (minus:DF (match_operand:DF 1 "register_operand" "r,0,r") ! 576: (match_operand:DF 2 "register_operand" "r,r,0")))] ! 577: "TARGET_29050" ! 578: "@ ! 579: dsub %0,%1,%2 ! 580: dmac 9,%0,%2,0 ! 581: dmac 10,%0,%1,0" ! 582: [(set_attr "type" "fadd,dam,dam")]) ! 583: ! 584: ;; EXBYTE ! 585: (define_insn "" ! 586: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 587: (ior:SI (and:SI (match_operand:SI 1 "srcb_operand" "rI") ! 588: (const_int -256)) ! 589: (zero_extract:SI (match_operand:SI 2 "gen_reg_operand" "r") ! 590: (const_int 8) ! 591: (ashift:SI (match_operand:SI 3 "register_operand" "b") ! 592: (const_int 3)))))] ! 593: "" ! 594: "exbyte %0,%2,%1") ! 595: ! 596: (define_insn "" ! 597: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 598: (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r") ! 599: (const_int 8) ! 600: (ashift:SI (match_operand:SI 2 "register_operand" "b") ! 601: (const_int 3))))] ! 602: "" ! 603: "exbyte %0,%1,0") ! 604: ! 605: (define_insn "" ! 606: [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r") ! 607: (const_int 8) ! 608: (match_operand:SI 1 "const_24_operand" "")) ! 609: (zero_extract:SI (match_operand:SI 2 "gen_reg_operand" "r") ! 610: (const_int 8) ! 611: (ashift:SI (match_operand:SI 3 "register_operand" "b") ! 612: (const_int 3))))] ! 613: "" ! 614: "exbyte %0,%2,%0") ! 615: ! 616: (define_expand "extzv" ! 617: [(set (match_operand:SI 0 "gen_reg_operand" "") ! 618: (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "") ! 619: (match_operand:SI 2 "general_operand" "") ! 620: (match_operand:SI 3 "general_operand" "")))] ! 621: "" ! 622: " ! 623: { ! 624: int size, pos; ! 625: ! 626: if (GET_CODE (operands[2]) != CONST_INT ! 627: || GET_CODE (operands[3]) != CONST_INT) ! 628: FAIL; ! 629: ! 630: size = INTVAL (operands[2]); ! 631: pos = INTVAL (operands[3]); ! 632: if ((size != 8 && size != 16) || pos % size != 0) ! 633: FAIL; ! 634: ! 635: operands[3] = gen_rtx (ASHIFT, SImode, ! 636: force_reg (SImode, ! 637: gen_rtx (CONST_INT, VOIDmode, pos / 8)), ! 638: gen_rtx (CONST_INT, VOIDmode, 3)); ! 639: }") ! 640: ! 641: (define_expand "extv" ! 642: [(set (match_operand:SI 0 "gen_reg_operand" "") ! 643: (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "") ! 644: (match_operand:SI 2 "general_operand" "") ! 645: (match_operand:SI 3 "general_operand" "")))] ! 646: "" ! 647: " ! 648: { ! 649: int pos; ! 650: ! 651: if (GET_CODE (operands[2]) != CONST_INT ! 652: || GET_CODE (operands[3]) != CONST_INT) ! 653: FAIL; ! 654: ! 655: pos = INTVAL (operands[3]); ! 656: if (INTVAL (operands[2]) != 16 || pos % 16 != 0) ! 657: FAIL; ! 658: ! 659: operands[3] = gen_rtx (ASHIFT, SImode, ! 660: force_reg (SImode, ! 661: gen_rtx (CONST_INT, VOIDmode, pos / 8)), ! 662: gen_rtx (CONST_INT, VOIDmode, 3)); ! 663: }") ! 664: ! 665: ;; EXHW ! 666: (define_insn "" ! 667: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 668: (ior:SI (and:SI (match_operand:SI 1 "srcb_operand" "rI") ! 669: (const_int -65536)) ! 670: (zero_extract:SI (match_operand:SI 2 "gen_reg_operand" "r") ! 671: (const_int 16) ! 672: (ashift:SI (match_operand:SI 3 "register_operand" "b") ! 673: (const_int 3)))))] ! 674: "" ! 675: "exhw %0,%2,%1") ! 676: ! 677: (define_insn "" ! 678: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 679: (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r") ! 680: (const_int 16) ! 681: (ashift:SI (match_operand:SI 2 "register_operand" "b") ! 682: (const_int 3))))] ! 683: "" ! 684: "exhw %0,%1,0") ! 685: ! 686: (define_insn "" ! 687: [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r") ! 688: (const_int 16) ! 689: (match_operand:SI 1 "const_16_operand" "")) ! 690: (zero_extract:SI (match_operand:SI 2 "gen_reg_operand" "r") ! 691: (const_int 16) ! 692: (ashift:SI (match_operand:SI 3 "register_operand" "b") ! 693: (const_int 3))))] ! 694: "" ! 695: "exhw %0,%2,%0") ! 696: ! 697: ;; EXHWS ! 698: (define_insn "" ! 699: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 700: (sign_extract:SI (match_operand:SI 1 "gen_reg_operand" "r") ! 701: (const_int 16) ! 702: (ashift:SI (match_operand:SI 2 "register_operand" "b") ! 703: (const_int 3))))] ! 704: "" ! 705: "exhws %0,%1") ! 706: ! 707: ;; EXTRACT ! 708: (define_insn "" ! 709: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 710: (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") ! 711: (reg:QI 178)))] ! 712: "" ! 713: "extract %0,%1,%1") ! 714: ! 715: (define_expand "rotlsi3" ! 716: [(set (reg:QI 178) ! 717: (match_operand: SI 2 "gen_reg_or_immediate_operand" "")) ! 718: (set (match_operand:SI 0 "gen_reg_operand" "") ! 719: (rotate:SI (match_operand:SI 1 "gen_reg_operand" "") ! 720: (reg:QI 178)))] ! 721: "" ! 722: " ! 723: { operands[2] = gen_lowpart (QImode, operands[2]); }") ! 724: ! 725: ;; FADD ! 726: (define_expand "addsf3" ! 727: [(set (match_operand:SF 0 "register_operand" "") ! 728: (plus:SF (match_operand:SF 1 "register_operand" "") ! 729: (match_operand:SF 2 "register_operand" "")))] ! 730: "" ! 731: "") ! 732: ! 733: (define_insn "" ! 734: [(set (match_operand:SF 0 "register_operand" "=r") ! 735: (plus:SF (match_operand:SF 1 "register_operand" "%r") ! 736: (match_operand:SF 2 "register_operand" "r")))] ! 737: "! TARGET_29050" ! 738: "fadd %0,%1,%2" ! 739: [(set_attr "type" "fadd")]) ! 740: ! 741: (define_insn "" ! 742: [(set (match_operand:SF 0 "register_operand" "=r,a") ! 743: (plus:SF (match_operand:SF 1 "register_operand" "%r,r") ! 744: (match_operand:SF 2 "register_operand" "r,0")))] ! 745: "TARGET_29050" ! 746: "@ ! 747: fadd %0,%1,%2 ! 748: fmac 8,%0,%1,0" ! 749: [(set_attr "type" "fadd,fam")]) ! 750: ! 751: ;; FDIV ! 752: (define_insn "divsf3" ! 753: [(set (match_operand:SF 0 "register_operand" "=r") ! 754: (div:DF (match_operand:SF 1 "register_operand" "=r") ! 755: (match_operand:SF 2 "register_operand" "r")))] ! 756: "" ! 757: "fdiv %0,%1,%2" ! 758: [(set_attr "type" "fdiv")]) ! 759: ! 760: ;; FDMUL ! 761: (define_insn "" ! 762: [(set (match_operand:DF 0 "register_operand" "=r") ! 763: (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "%r")) ! 764: (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))] ! 765: "" ! 766: "fdmul %0,%1,%2") ! 767: ! 768: ;; FMAC/FMSM ! 769: (define_insn "" ! 770: [(set (match_operand:SF 0 "register_operand" "=a,*r") ! 771: (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%r,A") ! 772: (match_operand:SF 2 "register_operand" "r,r")) ! 773: (match_operand:SF 3 "register_operand" "0,*r")))] ! 774: "TARGET_29050" ! 775: "@ ! 776: fmac 0,%0,%1,%2 ! 777: fmsm %0,%2,%3" ! 778: [(set_attr "type" "fam")]) ! 779: ! 780: (define_insn "" ! 781: [(set (match_operand:SF 0 "register_operand" "=a") ! 782: (plus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r")) ! 783: (match_operand:SF 2 "register_operand" "r")) ! 784: (match_operand:SF 3 "register_operand" "0")))] ! 785: "TARGET_29050" ! 786: "fmac 1,%0,%2,%1" ! 787: [(set_attr "type" "fam")]) ! 788: ! 789: (define_insn "" ! 790: [(set (match_operand:SF 0 "register_operand" "=a") ! 791: (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "%r") ! 792: (match_operand:SF 2 "register_operand" "r")) ! 793: (match_operand:SF 3 "register_operand" "0")))] ! 794: "TARGET_29050" ! 795: "fmac 2,%0,%1,%2" ! 796: [(set_attr "type" "fam")]) ! 797: ! 798: (define_insn "" ! 799: [(set (match_operand:SF 0 "register_operand" "=a") ! 800: (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r")) ! 801: (match_operand:SF 2 "register_operand" "r")) ! 802: (match_operand:SF 3 "register_operand" "0")))] ! 803: "TARGET_29050" ! 804: "fmac 3,%0,%2,%1" ! 805: [(set_attr "type" "fam")]) ! 806: ! 807: (define_insn "" ! 808: [(set (match_operand:SF 0 "register_operand" "=a") ! 809: (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r")) ! 810: (match_operand:SF 2 "register_operand" "r")))] ! 811: "TARGET_29050" ! 812: "fmac 5,%0,%2,%1" ! 813: [(set_attr "type" "fam")]) ! 814: ! 815: (define_insn "" ! 816: [(set (match_operand:SF 0 "register_operand" "=a") ! 817: (minus:SF (neg:SF (match_operand:SF 1 "register_operand" "%r")) ! 818: (match_operand:SF 2 "register_operand" "0")))] ! 819: "TARGET_29050" ! 820: "fmac 11,%0,%1,0" ! 821: [(set_attr "type" "fam")]) ! 822: ! 823: (define_insn "" ! 824: [(set (match_operand:SF 0 "register_operand" "=a") ! 825: (neg:SF (plus:SF (match_operand:SF 1 "register_operand" "%r") ! 826: (match_operand:SF 2 "register_operand" "0"))))] ! 827: "TARGET_29050" ! 828: "fmac 11,%0,%1,0" ! 829: [(set_attr "type" "fam")]) ! 830: ! 831: (define_insn "" ! 832: [(set (match_operand:SF 0 "register_operand" "=r,a") ! 833: (neg:SF (match_operand:SF 1 "register_operand" "r,r"))) ! 834: (clobber (match_scratch:SI 2 "=&r,X"))] ! 835: "TARGET_29050" ! 836: "@ ! 837: cpeq %2,gr1,gr1\;xor %0,%1,%2 ! 838: fmac 13,%0,%1,0" ! 839: [(set_attr "type" "multi,fam")]) ! 840: ! 841: ;; FMUL ! 842: (define_expand "mulsf3" ! 843: [(set (match_operand:SF 0 "register_operand" "") ! 844: (mult:SF (match_operand:SF 1 "register_operand" "") ! 845: (match_operand:SF 2 "register_operand" "")))] ! 846: "" ! 847: "") ! 848: ! 849: (define_insn "" ! 850: [(set (match_operand:SF 0 "register_operand" "=r") ! 851: (mult:SF (match_operand:SF 1 "register_operand" "%r") ! 852: (match_operand:SF 2 "register_operand" "r")))] ! 853: "! TARGET_29050" ! 854: "fmul %0,%1,%2" ! 855: [(set_attr "type" "fmul")]) ! 856: ! 857: (define_insn "" ! 858: [(set (match_operand:SF 0 "register_operand" "=r,a") ! 859: (mult:SF (match_operand:SF 1 "register_operand" "%r,r") ! 860: (match_operand:SF 2 "register_operand" "r,r")))] ! 861: "TARGET_29050" ! 862: "@ ! 863: fmul %0,%1,%2 ! 864: fmac 4,%0,%1,%2" ! 865: [(set_attr "type" "fmul,fam")]) ! 866: ! 867: ;; FSUB ! 868: (define_expand "subsf3" ! 869: [(set (match_operand:SF 0 "register_operand" "") ! 870: (minus:SF (match_operand:SF 1 "register_operand" "") ! 871: (match_operand:SF 2 "register_operand" "")))] ! 872: "" ! 873: "") ! 874: ! 875: (define_insn "" ! 876: [(set (match_operand:SF 0 "register_operand" "=r") ! 877: (minus:SF (match_operand:SF 1 "register_operand" "r") ! 878: (match_operand:SF 2 "register_operand" "r")))] ! 879: "! TARGET_29050" ! 880: "fsub %0,%1,%2" ! 881: [(set_attr "type" "fadd")]) ! 882: ! 883: (define_insn "" ! 884: [(set (match_operand:SF 0 "register_operand" "=r,a,a") ! 885: (minus:SF (match_operand:SF 1 "register_operand" "r,0,r") ! 886: (match_operand:SF 2 "register_operand" "r,r,0")))] ! 887: "TARGET_29050" ! 888: "@ ! 889: fsub %0,%1,%2 ! 890: fmac 9,%0,%2,0 ! 891: fmac 10,%0,%1,0" ! 892: [(set_attr "type" "fadd,fam,fam")]) ! 893: ! 894: ;; INBYTE ! 895: (define_insn "" ! 896: [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r") ! 897: (const_int 8) ! 898: (ashift:SI (match_operand:SI 2 "register_operand" "b") ! 899: (const_int 3))) ! 900: (match_operand:SI 1 "srcb_operand" "rI"))] ! 901: "" ! 902: "inbyte %0,%0,%1") ! 903: ! 904: (define_insn "" ! 905: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 906: (ior:SI (and:SI (not:SI (ashift:SI (const_int 255) ! 907: (ashift:SI (match_operand:SI 3 "register_operand" "b") ! 908: (const_int 3)))) ! 909: (match_operand:SI 1 "gen_reg_operand" "r")) ! 910: (ashift:SI (and:SI (match_operand:SI 2 "srcb_operand" "rI") ! 911: (const_int 255)) ! 912: (match_operand:SI 4 "const_24_operand" ""))))] ! 913: "" ! 914: "inbyte %0,%1,%2") ! 915: ! 916: (define_insn "" ! 917: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 918: (ior:SI (and:SI (not:SI (ashift:SI (const_int 255) ! 919: (ashift:SI (match_operand:SI 3 "register_operand" "b") ! 920: (const_int 3)))) ! 921: (match_operand:SI 1 "gen_reg_operand" "r")) ! 922: (ashift:SI (match_operand:SI 2 "srcb_operand" "rI") ! 923: (match_operand:SI 4 "const_24_operand" ""))))] ! 924: "" ! 925: "inbyte %0,%1,%2") ! 926: ! 927: ;; INHW ! 928: (define_insn "" ! 929: [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r") ! 930: (const_int 16) ! 931: (ashift:SI (match_operand:SI 2 "register_operand" "b") ! 932: (const_int 3))) ! 933: (match_operand:SI 1 "srcb_operand" "rI"))] ! 934: "" ! 935: "inhw %0,%0,%1") ! 936: ! 937: (define_insn "" ! 938: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 939: (ior:SI (and:SI (not:SI (ashift:SI (const_int 65535) ! 940: (ashift:SI (match_operand:SI 3 "register_operand" "b") ! 941: (const_int 3)))) ! 942: (match_operand:SI 1 "gen_reg_operand" "r")) ! 943: (ashift:SI (and:SI (match_operand:SI 2 "srcb_operand" "rI") ! 944: (const_int 65535)) ! 945: (match_operand:SI 4 "const_24_operand" ""))))] ! 946: "" ! 947: "inhw %0,%1,%2") ! 948: ! 949: (define_insn "" ! 950: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 951: (ior:SI (and:SI (not:SI (ashift:SI (const_int 65535) ! 952: (ashift:SI (match_operand:SI 3 "register_operand" "b") ! 953: (const_int 3)))) ! 954: (match_operand:SI 1 "gen_reg_operand" "r")) ! 955: (ashift:SI (match_operand:SI 2 "srcb_operand" "rI") ! 956: (match_operand:SI 4 "const_24_operand" ""))))] ! 957: "" ! 958: "inhw %0,%1,%2") ! 959: ! 960: (define_expand "insv" ! 961: [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "") ! 962: (match_operand:SI 1 "general_operand" "") ! 963: (match_operand:SI 2 "general_operand" "")) ! 964: (match_operand:SI 3 "srcb_operand" ""))] ! 965: "" ! 966: " ! 967: { ! 968: int size, pos; ! 969: ! 970: if (GET_CODE (operands[1]) != CONST_INT ! 971: || GET_CODE (operands[2]) != CONST_INT) ! 972: FAIL; ! 973: ! 974: size = INTVAL (operands[1]); ! 975: pos = INTVAL (operands[2]); ! 976: if ((size != 8 && size != 16) || pos % size != 0) ! 977: FAIL; ! 978: ! 979: operands[2] = gen_rtx (ASHIFT, SImode, ! 980: force_reg (SImode, ! 981: gen_rtx (CONST_INT, VOIDmode, pos / 8)), ! 982: gen_rtx (CONST_INT, VOIDmode, 3)); ! 983: }") ! 984: ! 985: ;; LOAD (also used by move insn). ! 986: (define_insn "" ! 987: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 988: (mem:SI (and:SI (match_operand:SI 1 "gen_reg_operand" "r") ! 989: (const_int -4)))) ! 990: (set (reg:SI 177) ! 991: (and:SI (match_dup 1) ! 992: (const_int 3)))] ! 993: "! TARGET_DW_ENABLE" ! 994: "load 0,17,%0,%1" ! 995: [(set_attr "type" "load")]) ! 996: ! 997: (define_insn "" ! 998: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 999: (mem:SI (and:SI (match_operand:SI 1 "gen_reg_operand" "r") ! 1000: (const_int -4)))) ! 1001: (set (reg:SI 177) ! 1002: (and:SI (match_dup 1) ! 1003: (const_int 2)))] ! 1004: "! TARGET_DW_ENABLE" ! 1005: "load 0,18,%0,%1" ! 1006: [(set_attr "type" "load")]) ! 1007: ! 1008: (define_insn "" ! 1009: [(set (match_operand 0 "gen_reg_operand" "=r") ! 1010: (match_operator 2 "extend_operator" ! 1011: [(match_operand 1 "memory_operand" "m")]))] ! 1012: "TARGET_DW_ENABLE && GET_MODE (operands[0]) == GET_MODE (operands[2])" ! 1013: "load 0,%X2,%0,%1" ! 1014: [(set_attr "type" "load")]) ! 1015: ! 1016: ;; LOADM ! 1017: (define_expand "load_multiple" ! 1018: [(set (reg:SI 179) ! 1019: (match_dup 2)) ! 1020: (match_parallel 3 "" [(set (match_operand:SI 0 "" "") ! 1021: (match_operand:SI 1 "" ""))])] ! 1022: "" ! 1023: " ! 1024: { ! 1025: int regno; ! 1026: int count; ! 1027: rtx from; ! 1028: int i; ! 1029: ! 1030: /* Support only loading a constant number of hard registers from memory. */ ! 1031: if (GET_CODE (operands[2]) != CONST_INT ! 1032: || operands[2] == const1_rtx ! 1033: || GET_CODE (operands[1]) != MEM ! 1034: || GET_CODE (operands[0]) != REG ! 1035: || REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER) ! 1036: FAIL; ! 1037: ! 1038: count = INTVAL (operands[2]); ! 1039: regno = REGNO (operands[0]); ! 1040: ! 1041: /* CR gets set to the number of registers minus one. */ ! 1042: operands[2] = gen_rtx (CONST_INT, VOIDmode, count - 1); ! 1043: ! 1044: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 2)); ! 1045: from = memory_address (SImode, XEXP (operands[1], 0)); ! 1046: XVECEXP (operands[3], 0, 0) = gen_rtx (SET, VOIDmode, ! 1047: gen_rtx (REG, SImode, regno), ! 1048: gen_rtx (MEM, SImode, from)); ! 1049: XVECEXP (operands[3], 0, 1) ! 1050: = gen_rtx (USE, VOIDmode, gen_rtx (REG, SImode, R_CR)); ! 1051: XVECEXP (operands[3], 0, 2) ! 1052: = gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, R_CR)); ! 1053: ! 1054: for (i = 1; i < count; i++) ! 1055: XVECEXP (operands[3], 0, i + 2) ! 1056: = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i), ! 1057: gen_rtx (MEM, SImode, plus_constant (from, i * 4))); ! 1058: }") ! 1059: ! 1060: ;; Indicate that CR is used and is then clobbered. ! 1061: (define_insn "" ! 1062: [(set (match_operand 0 "gen_reg_operand" "=r") ! 1063: (match_operand 1 "memory_operand" "m")) ! 1064: (use (reg:SI 179)) ! 1065: (clobber (reg:SI 179))] ! 1066: "GET_MODE (operands[0]) == GET_MODE (operands[1]) ! 1067: && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD ! 1068: && ! TARGET_29050" ! 1069: "loadm 0,0,%0,%1" ! 1070: [(set_attr "type" "load")]) ! 1071: ! 1072: (define_insn "" ! 1073: [(set (match_operand 0 "gen_reg_operand" "=&r") ! 1074: (match_operand 1 "memory_operand" "m")) ! 1075: (use (reg:SI 179)) ! 1076: (clobber (reg:SI 179))] ! 1077: "GET_MODE (operands[0]) == GET_MODE (operands[1]) ! 1078: && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD ! 1079: && TARGET_29050" ! 1080: "loadm 0,0,%0,%1" ! 1081: [(set_attr "type" "load")]) ! 1082: ! 1083: (define_insn "" ! 1084: [(match_parallel 0 "load_multiple_operation" ! 1085: [(set (match_operand:SI 1 "gen_reg_operand" "=r") ! 1086: (match_operand:SI 2 "memory_operand" "m")) ! 1087: (use (reg:SI 179)) ! 1088: (clobber (reg:SI 179))])] ! 1089: "! TARGET_29050" ! 1090: "loadm 0,0,%1,%2" ! 1091: [(set_attr "type" "load")]) ! 1092: ! 1093: (define_insn "" ! 1094: [(match_parallel 0 "load_multiple_operation" ! 1095: [(set (match_operand:SI 1 "gen_reg_operand" "=&r") ! 1096: (match_operand:SI 2 "memory_operand" "m")) ! 1097: (use (reg:SI 179)) ! 1098: (clobber (reg:SI 179))])] ! 1099: "TARGET_29050" ! 1100: "loadm 0,0,%1,%2" ! 1101: [(set_attr "type" "load")]) ! 1102: ! 1103: ;; MTSR (used also by move insn) ! 1104: (define_insn "" ! 1105: [(set (match_operand:SI 0 "spec_reg_operand" "=*h,*h") ! 1106: (and:SI (match_operand:SI 1 "gen_reg_or_immediate_operand" "r,i") ! 1107: (match_operand:SI 2 "const_int_operand" "n,n")))] ! 1108: "masks_bits_for_special (operands[0], operands[2])" ! 1109: "@ ! 1110: mtsr %0,%1 ! 1111: mtsrim %0,%1") ! 1112: ! 1113: ;; MULTIPLY, MULTM, MULTMU ! 1114: (define_insn "mulsi3" ! 1115: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 1116: (mult:SI (match_operand:SI 1 "gen_reg_operand" "%r") ! 1117: (match_operand:SI 2 "gen_reg_operand" "r")))] ! 1118: "" ! 1119: "multiply %0,%1,%2") ! 1120: ! 1121: (define_insn "" ! 1122: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 1123: (subreg:SI ! 1124: (mult:DI ! 1125: (sign_extend:DI (match_operand:SI 1 "gen_reg_operand" "%r")) ! 1126: (sign_extend:DI (match_operand:SI 2 "gen_reg_operand" "r"))) 0))] ! 1127: "" ! 1128: "multm %0,%1,%2") ! 1129: ! 1130: (define_insn "" ! 1131: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 1132: (subreg:SI ! 1133: (mult:DI ! 1134: (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "%r")) ! 1135: (zero_extend:DI (match_operand:SI 2 "gen_reg_operand" "r"))) 0))] ! 1136: "" ! 1137: "multmu %0,%1,%2") ! 1138: ! 1139: (define_insn "mulsidi3" ! 1140: [(set (match_operand:DI 0 "gen_reg_operand" "=r") ! 1141: (mult:DI (sign_extend:DI (match_operand:SI 1 "gen_reg_operand" "r")) ! 1142: (sign_extend:DI (match_operand:SI 2 "gen_reg_operand" "r"))))] ! 1143: "" ! 1144: "multiply %L0,%1,%2\;multm %0,%1,%2" ! 1145: [(set_attr "type" "multi")]) ! 1146: ! 1147: (define_split ! 1148: [(set (match_operand:DI 0 "gen_reg_operand" "") ! 1149: (mult:DI (sign_extend:DI (match_operand:SI 1 "gen_reg_operand" "")) ! 1150: (sign_extend:DI (match_operand:SI 2 "gen_reg_operand" ""))))] ! 1151: "reload_completed" ! 1152: [(set (match_dup 3) ! 1153: (mult:SI (match_dup 1) (match_dup 2))) ! 1154: (set (match_dup 4) ! 1155: (subreg:SI (mult:DI ! 1156: (sign_extend:DI (match_dup 1)) ! 1157: (sign_extend:DI (match_dup 2))) 0))] ! 1158: " ! 1159: { operands[3] = operand_subword (operands[0], 1, 1, DImode); ! 1160: operands[4] = operand_subword (operands[1], 0, 1, DImode); } ") ! 1161: ! 1162: (define_insn "umulsidi3" ! 1163: [(set (match_operand:DI 0 "gen_reg_operand" "=r") ! 1164: (mult:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "r")) ! 1165: (zero_extend:DI (match_operand:SI 2 "gen_reg_operand" "r"))))] ! 1166: "" ! 1167: "multiplu %L0,%1,%2\;multmu %0,%1,%2" ! 1168: [(set_attr "type" "multi")]) ! 1169: ! 1170: (define_split ! 1171: [(set (match_operand:DI 0 "gen_reg_operand" "") ! 1172: (mult:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "")) ! 1173: (zero_extend:DI (match_operand:SI 2 "gen_reg_operand" ""))))] ! 1174: "reload_completed" ! 1175: [(set (match_dup 3) ! 1176: (mult:SI (match_dup 1) (match_dup 2))) ! 1177: (set (match_dup 4) ! 1178: (subreg:SI (mult:DI (zero_extend:DI (match_dup 1)) ! 1179: (zero_extend:DI (match_dup 2))) 0))] ! 1180: " ! 1181: { operands[3] = operand_subword (operands[0], 1, 1, DImode); ! 1182: operands[4] = operand_subword (operands[1], 0, 1, DImode); } ") ! 1183: ! 1184: ;; NAND ! 1185: (define_insn "" ! 1186: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 1187: (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "%r")) ! 1188: (not:SI (match_operand:SI 2 "srcb_operand" "rI"))))] ! 1189: "" ! 1190: "nand %0,%1,%2") ! 1191: ! 1192: (define_insn "" ! 1193: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 1194: (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) ! 1195: (match_operand:SI 2 "const_int_operand" "K")))] ! 1196: "((unsigned) ~ INTVAL (operands[2])) < 256" ! 1197: "nand %0,%1,%C2") ! 1198: ! 1199: ;; NOR ! 1200: (define_insn "" ! 1201: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 1202: (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "%r")) ! 1203: (not:SI (match_operand:SI 2 "srcb_operand" "rI"))))] ! 1204: "" ! 1205: "nor %0,%1,%2") ! 1206: ! 1207: (define_insn "" ! 1208: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 1209: (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) ! 1210: (match_operand:SI 2 "const_int_operand" "K")))] ! 1211: "((unsigned) ~ INTVAL (operands[2])) < 256" ! 1212: "nor %0,%1,%C2") ! 1213: ! 1214: (define_insn "one_cmplsi2" ! 1215: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 1216: (not:SI (match_operand:SI 1 "gen_reg_operand" "r")))] ! 1217: "" ! 1218: "nor %0,%1,0") ! 1219: ! 1220: ;; OR/ORN ! 1221: (define_expand "iorsi3" ! 1222: [(set (match_operand:SI 0 "gen_reg_operand" "") ! 1223: (ior:SI (match_operand:SI 1 "gen_reg_operand" "") ! 1224: (match_operand:SI 2 "srcb_operand" "")))] ! 1225: "" ! 1226: "") ! 1227: ! 1228: (define_insn "" ! 1229: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 1230: (ior:SI (match_operand:SI 1 "gen_reg_operand" "%r") ! 1231: (match_operand:SI 2 "srcb_operand" "rI")))] ! 1232: "! TARGET_29050" ! 1233: "or %0,%1,%2") ! 1234: ! 1235: (define_insn "" ! 1236: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") ! 1237: (ior:SI (match_operand:SI 1 "gen_reg_operand" "%r,r") ! 1238: (match_operand:SI 2 "srcb_operand" "rI,K")))] ! 1239: "TARGET_29050" ! 1240: "@ ! 1241: or %0,%1,%2 ! 1242: orn %0,%1,%C2") ! 1243: ! 1244: ! 1245: ;; SLL (also used by move insn) ! 1246: (define_insn "nop" ! 1247: [(const_int 0)] ! 1248: "" ! 1249: "aseq 0x40,gr1,gr1") ! 1250: ! 1251: (define_insn "ashlsi3" ! 1252: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 1253: (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r") ! 1254: (match_operand:QI 2 "srcb_operand" "rn")))] ! 1255: "" ! 1256: "sll %0,%1,%Q2") ! 1257: ! 1258: ;; SRA ! 1259: (define_insn "ashrsi3" ! 1260: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 1261: (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r") ! 1262: (match_operand:QI 2 "srcb_operand" "rn")))] ! 1263: "" ! 1264: "sra %0,%1,%Q2") ! 1265: ! 1266: ;; SRL ! 1267: (define_insn "lshrsi3" ! 1268: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 1269: (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r") ! 1270: (match_operand:QI 2 "srcb_operand" "rn")))] ! 1271: "" ! 1272: "srl %0,%1,%Q2") ! 1273: ! 1274: ;; STORE ! 1275: ;; ! 1276: ;; These somewhat bogus patterns exist to set OPT = 001/010 for partial-word ! 1277: ;; stores on systems with DW not set. ! 1278: (define_insn "" ! 1279: [(set (mem:SI (and:SI (match_operand:SI 0 "gen_reg_operand" "r") ! 1280: (const_int -4))) ! 1281: (match_operand:SI 1 "gen_reg_operand" "r"))] ! 1282: "! TARGET_DW_ENABLE" ! 1283: "store 0,1,%1,%0" ! 1284: [(set_attr "type" "store")]) ! 1285: ! 1286: (define_insn "" ! 1287: [(set (mem:SI (and:SI (match_operand:SI 0 "gen_reg_operand" "r") ! 1288: (const_int -3))) ! 1289: (match_operand:SI 1 "gen_reg_operand" "r"))] ! 1290: "! TARGET_DW_ENABLE" ! 1291: "store 0,2,%1,%0" ! 1292: [(set_attr "type" "store")]) ! 1293: ! 1294: ;; STOREM ! 1295: (define_expand "store_multiple" ! 1296: [(use (match_operand 0 "" "")) ! 1297: (use (match_operand 1 "" "")) ! 1298: (use (match_operand 2 "" ""))] ! 1299: "" ! 1300: " ! 1301: { rtx pat; ! 1302: ! 1303: if (TARGET_NO_STOREM_BUG) ! 1304: pat = gen_store_multiple_no_bug (operands[0], operands[1], operands[2]); ! 1305: else ! 1306: pat = gen_store_multiple_bug (operands[0], operands[1], operands[2]); ! 1307: ! 1308: if (pat) ! 1309: emit_insn (pat); ! 1310: else ! 1311: FAIL; ! 1312: ! 1313: DONE; ! 1314: }") ! 1315: ! 1316: (define_expand "store_multiple_no_bug" ! 1317: [(set (reg:SI 179) ! 1318: (match_dup 2)) ! 1319: (match_parallel 3 "" [(set (match_operand:SI 0 "" "") ! 1320: (match_operand:SI 1 "" ""))])] ! 1321: "" ! 1322: " ! 1323: { ! 1324: int regno; ! 1325: int count; ! 1326: rtx from; ! 1327: int i; ! 1328: ! 1329: /* Support only storing a constant number of hard registers to memory. */ ! 1330: if (GET_CODE (operands[2]) != CONST_INT ! 1331: || operands[2] == const1_rtx ! 1332: || GET_CODE (operands[0]) != MEM ! 1333: || GET_CODE (operands[1]) != REG ! 1334: || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER) ! 1335: FAIL; ! 1336: ! 1337: count = INTVAL (operands[2]); ! 1338: regno = REGNO (operands[1]); ! 1339: ! 1340: /* CR gets set to the number of registers minus one. */ ! 1341: operands[2] = gen_rtx (CONST_INT, VOIDmode, count - 1); ! 1342: ! 1343: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 2)); ! 1344: from = memory_address (SImode, XEXP (operands[0], 0)); ! 1345: XVECEXP (operands[3], 0, 0) = gen_rtx (SET, VOIDmode, ! 1346: gen_rtx (MEM, SImode, from), ! 1347: gen_rtx (REG, SImode, regno)); ! 1348: XVECEXP (operands[3], 0, 1) ! 1349: = gen_rtx (USE, VOIDmode, gen_rtx (REG, SImode, R_CR)); ! 1350: XVECEXP (operands[3], 0, 2) ! 1351: = gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, R_CR)); ! 1352: ! 1353: for (i = 1; i < count; i++) ! 1354: XVECEXP (operands[3], 0, i + 2) ! 1355: = gen_rtx (SET, VOIDmode, ! 1356: gen_rtx (MEM, SImode, plus_constant (from, i * 4)), ! 1357: gen_rtx (REG, SImode, regno + i)); ! 1358: }") ! 1359: ! 1360: (define_expand "store_multiple_bug" ! 1361: [(match_parallel 3 "" [(set (match_operand:SI 0 "" "") ! 1362: (match_operand:SI 1 "" ""))])] ! 1363: "" ! 1364: " ! 1365: { ! 1366: int regno; ! 1367: int count; ! 1368: rtx from; ! 1369: int i; ! 1370: ! 1371: /* Support only storing a constant number of hard registers to memory. */ ! 1372: if (GET_CODE (operands[2]) != CONST_INT ! 1373: || operands[2] == const1_rtx ! 1374: || GET_CODE (operands[0]) != MEM ! 1375: || GET_CODE (operands[1]) != REG ! 1376: || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER) ! 1377: FAIL; ! 1378: ! 1379: count = INTVAL (operands[2]); ! 1380: regno = REGNO (operands[1]); ! 1381: ! 1382: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1)); ! 1383: from = memory_address (SImode, XEXP (operands[0], 0)); ! 1384: XVECEXP (operands[3], 0, 0) = gen_rtx (SET, VOIDmode, ! 1385: gen_rtx (MEM, SImode, from), ! 1386: gen_rtx (REG, SImode, regno)); ! 1387: XVECEXP (operands[3], 0, 1) ! 1388: = gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, R_CR)); ! 1389: ! 1390: for (i = 1; i < count; i++) ! 1391: XVECEXP (operands[3], 0, i + 1) ! 1392: = gen_rtx (SET, VOIDmode, ! 1393: gen_rtx (MEM, SImode, plus_constant (from, i * 4)), ! 1394: gen_rtx (REG, SImode, regno + i)); ! 1395: }") ! 1396: ! 1397: (define_insn "" ! 1398: [(set (match_operand 0 "memory_operand" "=m") ! 1399: (match_operand 1 "gen_reg_operand" "r")) ! 1400: (clobber (reg:SI 179))] ! 1401: "!TARGET_NO_STOREM_BUG ! 1402: && GET_MODE (operands[0]) == GET_MODE (operands[1]) ! 1403: && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD" ! 1404: "mtsrim cr,%S1\;storem 0,0,%1,%0" ! 1405: [(set_attr "type" "multi")]) ! 1406: ! 1407: (define_insn "" ! 1408: [(match_parallel 0 "store_multiple_operation" ! 1409: [(set (match_operand:SI 1 "memory_operand" "=m") ! 1410: (match_operand:SI 2 "gen_reg_operand" "r")) ! 1411: (clobber (reg:SI 179))])] ! 1412: "!TARGET_NO_STOREM_BUG" ! 1413: "mtsrim cr,%V0\;storem 0,0,%2,%1" ! 1414: [(set_attr "type" "multi")]) ! 1415: ! 1416: (define_insn "" ! 1417: [(set (match_operand 0 "memory_operand" "=m") ! 1418: (match_operand 1 "gen_reg_operand" "r")) ! 1419: (use (reg:SI 179)) ! 1420: (clobber (reg:SI 179))] ! 1421: "TARGET_NO_STOREM_BUG ! 1422: && GET_MODE (operands[0]) == GET_MODE (operands[1]) ! 1423: && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD" ! 1424: "storem 0,0,%1,%0" ! 1425: [(set_attr "type" "store")]) ! 1426: ! 1427: (define_insn "" ! 1428: [(match_parallel 0 "store_multiple_operation" ! 1429: [(set (match_operand:SI 1 "memory_operand" "=m") ! 1430: (match_operand:SI 2 "gen_reg_operand" "r")) ! 1431: (use (reg:SI 179)) ! 1432: (clobber (reg:SI 179))])] ! 1433: "TARGET_NO_STOREM_BUG" ! 1434: "storem 0,0,%2,%1" ! 1435: [(set_attr "type" "store")]) ! 1436: ! 1437: ;; SUB ! 1438: ;; ! 1439: ;; Either operand can be a register or an 8-bit constant, but both cannot be ! 1440: ;; constants (can't usually occur anyway). ! 1441: (define_expand "subsi3" ! 1442: [(set (match_operand:SI 0 "gen_reg_operand" "") ! 1443: (minus:SI (match_operand:SI 1 "srcb_operand" "") ! 1444: (match_operand:SI 2 "srcb_operand" "")))] ! 1445: "" ! 1446: " ! 1447: { ! 1448: if (GET_CODE (operands[0]) == CONST_INT ! 1449: && GET_CODE (operands[1]) == CONST_INT) ! 1450: operands[1] = force_reg (SImode, operands[1]); ! 1451: }") ! 1452: ! 1453: (define_insn "" ! 1454: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") ! 1455: (minus:SI (match_operand:SI 1 "srcb_operand" "r,I") ! 1456: (match_operand:SI 2 "srcb_operand" "rI,r")))] ! 1457: "register_operand (operands[1], SImode) ! 1458: || register_operand (operands[2], SImode)" ! 1459: "@ ! 1460: sub %0,%1,%2 ! 1461: subr %0,%2,%1") ! 1462: ! 1463: (define_insn "subdi3" ! 1464: [(set (match_operand:DI 0 "gen_reg_operand" "=r") ! 1465: (minus:DI (match_operand:DI 1 "gen_reg_operand" "r") ! 1466: (match_operand:DI 2 "gen_reg_operand" "r")))] ! 1467: "" ! 1468: "sub %L0,%L1,%L2\;subc %0,%1,%2" ! 1469: [(set_attr "type" "multi")]) ! 1470: ! 1471: ;; SUBR (also used above in SUB) ! 1472: (define_insn "negdi2" ! 1473: [(set (match_operand:DI 0 "gen_reg_operand" "=r") ! 1474: (neg:DI (match_operand:DI 1 "gen_reg_operand" "r")))] ! 1475: "" ! 1476: "subr %L0,%L1,0\;subrc %0,%1,0" ! 1477: [(set_attr "type" "multi")]) ! 1478: ! 1479: (define_insn "negsi2" ! 1480: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 1481: (neg:SI (match_operand:SI 1 "gen_reg_operand" "r")))] ! 1482: "" ! 1483: "subr %0,%1,0") ! 1484: ! 1485: ;; XNOR ! 1486: (define_insn "" ! 1487: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 1488: (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r") ! 1489: (match_operand:SI 2 "srcb_operand" "rI"))))] ! 1490: "" ! 1491: "xnor %0,%1,%2") ! 1492: ! 1493: ;; XOR ! 1494: (define_insn "xorsi3" ! 1495: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 1496: (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r") ! 1497: (match_operand:SI 2 "srcb_operand" "rI")))] ! 1498: "" ! 1499: "xor %0,%1,%2") ! 1500: ! 1501: ;; Can use XOR to negate floating-point values, but we are better off not doing ! 1502: ;; it that way on the 29050 so it can combine with the fmac insns. ! 1503: (define_expand "negsf2" ! 1504: [(parallel [(set (match_operand:SF 0 "register_operand" "") ! 1505: (neg:SF (match_operand:SF 1 "register_operand" ""))) ! 1506: (clobber (match_scratch:SI 2 ""))])] ! 1507: "" ! 1508: " ! 1509: { ! 1510: rtx result; ! 1511: rtx target; ! 1512: ! 1513: if (! TARGET_29050) ! 1514: { ! 1515: target = operand_subword_force (operands[0], 0, SFmode); ! 1516: result = expand_binop (SImode, xor_optab, ! 1517: operand_subword_force (operands[1], 0, SFmode), ! 1518: gen_rtx (CONST_INT, VOIDmode, 0x80000000), ! 1519: target, 0, OPTAB_WIDEN); ! 1520: if (result == 0) ! 1521: abort (); ! 1522: ! 1523: if (result != target) ! 1524: emit_move_insn (result, target); ! 1525: ! 1526: /* Make a place for REG_EQUAL. */ ! 1527: emit_move_insn (operands[0], operands[0]); ! 1528: DONE; ! 1529: } ! 1530: }") ! 1531: ! 1532: (define_expand "negdf2" ! 1533: [(parallel [(set (match_operand:DF 0 "register_operand" "") ! 1534: (neg:DF (match_operand:DF 1 "register_operand" ""))) ! 1535: (clobber (match_scratch:SI 2 ""))])] ! 1536: "" ! 1537: " ! 1538: { ! 1539: rtx result; ! 1540: rtx target; ! 1541: rtx insns; ! 1542: ! 1543: if (! TARGET_29050) ! 1544: { ! 1545: start_sequence (); ! 1546: target = operand_subword (operands[0], 0, 1, DFmode); ! 1547: result = expand_binop (SImode, xor_optab, ! 1548: operand_subword_force (operands[1], 0, DFmode), ! 1549: gen_rtx (CONST_INT, VOIDmode, 0x80000000), ! 1550: target, 0, OPTAB_WIDEN); ! 1551: if (result == 0) ! 1552: abort (); ! 1553: ! 1554: if (result != target) ! 1555: emit_move_insn (result, target); ! 1556: ! 1557: emit_move_insn (operand_subword (operands[0], 1, 1, DFmode), ! 1558: operand_subword_force (operands[1], 1, DFmode)); ! 1559: ! 1560: insns = get_insns (); ! 1561: end_sequence (); ! 1562: ! 1563: emit_no_conflict_block (insns, operands[0], operands[1], 0, 0); ! 1564: DONE; ! 1565: } ! 1566: }") ! 1567: ! 1568: ;; Sign extend and truncation operations. ! 1569: (define_insn "zero_extendqihi2" ! 1570: [(set (match_operand:HI 0 "gen_reg_operand" "=r") ! 1571: (zero_extend:HI (match_operand:QI 1 "gen_reg_operand" "r")))] ! 1572: "" ! 1573: "and %0,%1,255") ! 1574: ! 1575: (define_insn "zero_extendqisi2" ! 1576: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 1577: (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "r")))] ! 1578: "" ! 1579: "and %0,%1,255") ! 1580: ! 1581: (define_insn "zero_extendhisi2" ! 1582: [(set (match_operand:SI 0 "gen_reg_operand" "=r") ! 1583: (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "0")))] ! 1584: "" ! 1585: "consth %0,0") ! 1586: ! 1587: (define_expand "extendqihi2" ! 1588: [(set (match_dup 2) ! 1589: (ashift:SI (match_operand:QI 1 "gen_reg_operand" "") ! 1590: (const_int 24))) ! 1591: (set (match_operand:HI 0 "gen_reg_operand" "") ! 1592: (ashiftrt:SI (match_dup 2) ! 1593: (const_int 24)))] ! 1594: "" ! 1595: " ! 1596: { operands[0] = gen_lowpart (SImode, operands[0]); ! 1597: operands[1] = gen_lowpart (SImode, operands[1]); ! 1598: operands[2] = gen_reg_rtx (SImode); }") ! 1599: ! 1600: (define_expand "extendqisi2" ! 1601: [(set (match_dup 2) ! 1602: (ashift:SI (match_operand:QI 1 "gen_reg_operand" "") ! 1603: (const_int 24))) ! 1604: (set (match_operand:SI 0 "gen_reg_operand" "") ! 1605: (ashiftrt:SI (match_dup 2) ! 1606: (const_int 24)))] ! 1607: "" ! 1608: " ! 1609: { operands[1] = gen_lowpart (SImode, operands[1]); ! 1610: operands[2] = gen_reg_rtx (SImode); }") ! 1611: ! 1612: (define_expand "extendhisi2" ! 1613: [(set (match_dup 2) ! 1614: (ashift:SI (match_operand:HI 1 "gen_reg_operand" "") ! 1615: (const_int 16))) ! 1616: (set (match_operand:SI 0 "gen_reg_operand" "") ! 1617: (ashiftrt:SI (match_dup 2) ! 1618: (const_int 16)))] ! 1619: "" ! 1620: " ! 1621: { operands[1] = gen_lowpart (SImode, operands[1]); ! 1622: operands[2] = gen_reg_rtx (SImode); }") ! 1623: ! 1624: ;; Define the methods used to move data around. ! 1625: ;; ! 1626: ;; movsi: ! 1627: ;; ! 1628: ;; If storing into memory, force source into register. ! 1629: (define_expand "movsi" ! 1630: [(set (match_operand:SI 0 "general_operand" "") ! 1631: (match_operand:SI 1 "general_operand" ""))] ! 1632: "" ! 1633: " ! 1634: { ! 1635: if (GET_CODE (operands[0]) == MEM && ! gen_reg_operand (operands[1], SImode)) ! 1636: operands[1] = copy_to_mode_reg (SImode, operands[1]); ! 1637: else if (spec_reg_operand (operands[0], SImode) ! 1638: && ! (register_operand (operands[1], SImode) ! 1639: || cint_16_operand (operands[1], SImode))) ! 1640: operands[1] = force_reg (SImode, operands[1]); ! 1641: }") ! 1642: ! 1643: (define_split ! 1644: [(set (match_operand:SI 0 "gen_reg_operand" "") ! 1645: (match_operand:SI 1 "long_const_operand" ""))] ! 1646: "" ! 1647: [(set (match_dup 0) ! 1648: (and:SI (match_dup 1) ! 1649: (const_int 65535))) ! 1650: (set (match_dup 0) ! 1651: (ior:SI (and:SI (match_dup 0) ! 1652: (const_int 65535)) ! 1653: (and:SI (match_dup 1) ! 1654: (const_int -65536))))] ! 1655: "") ! 1656: ! 1657: ;; Subroutines to load/store halfwords. Use TAV (gr121) as scratch. We have ! 1658: ;; two versions of storehi, one when halfword writes are supported and one ! 1659: ;; where they aren't. ! 1660: (define_expand "loadhi" ! 1661: [(parallel [(set (match_dup 2) ! 1662: (mem:SI (and:SI (match_operand:SI 0 "gen_reg_operand" "") ! 1663: (const_int -4)))) ! 1664: (set (reg:SI 177) ! 1665: (and:SI (match_dup 0) ! 1666: (const_int 2)))]) ! 1667: (set (match_operand:HI 1 "gen_reg_operand" "") ! 1668: (zero_extract:SI (match_dup 2) ! 1669: (const_int 16) ! 1670: (ashift:SI (reg:SI 177) ! 1671: (const_int 3))))] ! 1672: "" ! 1673: " ! 1674: { operands[1] = gen_lowpart (SImode, operands[1]); ! 1675: ! 1676: if (reload_in_progress) ! 1677: operands[2] = gen_rtx (REG, SImode, R_TAV); ! 1678: else ! 1679: operands[2] = gen_reg_rtx (SImode); ! 1680: }") ! 1681: ! 1682: (define_expand "storehinhww" ! 1683: [(parallel [(set (match_dup 2) ! 1684: (mem:SI (and:SI (match_operand:SI 0 "gen_reg_operand" "") ! 1685: (const_int -4)))) ! 1686: (set (reg:SI 177) ! 1687: (and:SI (match_dup 0) ! 1688: (const_int 2)))]) ! 1689: (set (zero_extract:SI (match_dup 2) ! 1690: (const_int 8) ! 1691: (ashift:SI (reg:SI 177) ! 1692: (const_int 3))) ! 1693: (match_operand:HI 1 "gen_reg_operand" "")) ! 1694: (set (mem:SI (match_dup 0)) ! 1695: (match_dup 2))] ! 1696: "" ! 1697: " ! 1698: { operands[1] = gen_lowpart (SImode, operands[1]); ! 1699: ! 1700: if (reload_in_progress) ! 1701: operands[2] = gen_rtx (REG, SImode, R_TAV); ! 1702: else ! 1703: operands[2] = gen_reg_rtx (SImode); ! 1704: }") ! 1705: ! 1706: (define_expand "storehihww" ! 1707: [(set (reg:SI 177) ! 1708: (and:SI (match_operand:SI 0 "gen_reg_operand" "") ! 1709: (const_int 3))) ! 1710: (set (match_dup 2) ! 1711: (ior:SI (and:SI (not:SI (ashift:SI (const_int 65535) ! 1712: (ashift:SI (reg:SI 177) ! 1713: (const_int 3)))) ! 1714: (match_operand:HI 1 "gen_reg_operand" "")) ! 1715: (ashift:SI (and:SI (match_dup 1) ! 1716: (const_int 65535)) ! 1717: (ashift:SI (reg:SI 177) ! 1718: (const_int 3))))) ! 1719: (set (mem:SI (and:SI (match_dup 0) ! 1720: (const_int -3))) ! 1721: (match_dup 2))] ! 1722: "" ! 1723: " ! 1724: { operands[1] = gen_lowpart (SImode, operands[1]); ! 1725: ! 1726: if (reload_in_progress) ! 1727: operands[2] = gen_rtx (REG, SImode, R_TAV); ! 1728: else ! 1729: operands[2] = gen_reg_rtx (SImode); ! 1730: }") ! 1731: ! 1732: (define_expand "movhi" ! 1733: [(set (match_operand:HI 0 "general_operand" "") ! 1734: (match_operand:HI 1 "general_operand" ""))] ! 1735: "" ! 1736: " ! 1737: { if (GET_CODE (operands[0]) == MEM) ! 1738: { ! 1739: if (! gen_reg_operand (operands[1], HImode)) ! 1740: operands[1] = copy_to_mode_reg (HImode, operands[1]); ! 1741: if (! TARGET_DW_ENABLE) ! 1742: { ! 1743: if (TARGET_BYTE_WRITES) ! 1744: emit_insn (gen_storehihww (XEXP (operands[0], 0), operands[1])); ! 1745: else ! 1746: emit_insn (gen_storehinhww (XEXP (operands[0], 0), operands[1])); ! 1747: DONE; ! 1748: } ! 1749: } ! 1750: else if (GET_CODE (operands[1]) == MEM) ! 1751: { ! 1752: if (! TARGET_DW_ENABLE) ! 1753: { ! 1754: emit_insn (gen_loadhi (XEXP (operands[1], 0), operands[0])); ! 1755: DONE; ! 1756: } ! 1757: } ! 1758: }") ! 1759: ! 1760: ;; Subroutines to load/store bytes. Use TAV (gr121) as scratch. ! 1761: (define_expand "loadqi" ! 1762: [(parallel [(set (match_dup 2) ! 1763: (mem:SI (and:SI (match_operand:SI 0 "gen_reg_operand" "") ! 1764: (const_int -4)))) ! 1765: (set (reg:SI 177) ! 1766: (and:SI (match_dup 0) ! 1767: (const_int 3)))]) ! 1768: (set (match_operand:QI 1 "gen_reg_operand" "") ! 1769: (zero_extract:SI (match_dup 2) ! 1770: (const_int 8) ! 1771: (ashift:SI (reg:SI 177) ! 1772: (const_int 3))))] ! 1773: "" ! 1774: " ! 1775: { operands[1] = gen_lowpart (SImode, operands[1]); ! 1776: ! 1777: if (reload_in_progress) ! 1778: operands[2] = gen_rtx (REG, SImode, R_TAV); ! 1779: else ! 1780: operands[2] = gen_reg_rtx (SImode); ! 1781: }") ! 1782: ! 1783: (define_expand "storeqinhww" ! 1784: [(parallel [(set (match_dup 2) ! 1785: (mem:SI (and:SI (match_operand:SI 0 "gen_reg_operand" "") ! 1786: (const_int -4)))) ! 1787: (set (reg:SI 177) ! 1788: (and:SI (match_dup 0) ! 1789: (const_int 3)))]) ! 1790: (set (zero_extract:SI (match_dup 2) ! 1791: (const_int 8) ! 1792: (ashift:SI (reg:SI 177) ! 1793: (const_int 3))) ! 1794: (match_operand:QI 1 "gen_reg_operand" "")) ! 1795: (set (mem:SI (match_dup 0)) ! 1796: (match_dup 2))] ! 1797: "" ! 1798: " ! 1799: { operands[1] = gen_lowpart (SImode, operands[1]); ! 1800: ! 1801: if (reload_in_progress) ! 1802: operands[2] = gen_rtx (REG, SImode, R_TAV); ! 1803: else ! 1804: operands[2] = gen_reg_rtx (SImode); ! 1805: }") ! 1806: ! 1807: (define_expand "storeqihww" ! 1808: [(set (reg:SI 177) ! 1809: (and:SI (match_operand:SI 0 "gen_reg_operand" "") ! 1810: (const_int 3))) ! 1811: (set (match_dup 2) ! 1812: (ior:SI (and:SI (not:SI (ashift:SI (const_int 255) ! 1813: (ashift:SI (reg:SI 177) ! 1814: (const_int 3)))) ! 1815: (match_operand:HI 1 "gen_reg_operand" "")) ! 1816: (ashift:SI (and:SI (match_dup 1) ! 1817: (const_int 255)) ! 1818: (ashift:SI (reg:SI 177) ! 1819: (const_int 3))))) ! 1820: (set (mem:SI (and:SI (match_dup 0) ! 1821: (const_int -4))) ! 1822: (match_dup 2))] ! 1823: "" ! 1824: " ! 1825: { operands[1] = gen_lowpart (SImode, operands[1]); ! 1826: ! 1827: if (reload_in_progress) ! 1828: operands[2] = gen_rtx (REG, SImode, R_TAV); ! 1829: else ! 1830: operands[2] = gen_reg_rtx (SImode); ! 1831: }") ! 1832: ! 1833: (define_expand "movqi" ! 1834: [(set (match_operand:QI 0 "general_operand" "") ! 1835: (match_operand:QI 1 "general_operand" ""))] ! 1836: "" ! 1837: " ! 1838: { if (GET_CODE (operands[0]) == MEM) ! 1839: { ! 1840: if (! gen_reg_operand (operands[1], QImode)) ! 1841: operands[1] = copy_to_mode_reg (QImode, operands[1]); ! 1842: if (! TARGET_DW_ENABLE) ! 1843: { ! 1844: if (TARGET_BYTE_WRITES) ! 1845: emit_insn (gen_storeqihww (XEXP (operands[0], 0), operands[1])); ! 1846: else ! 1847: emit_insn (gen_storeqinhww (XEXP (operands[0], 0), operands[1])); ! 1848: DONE; ! 1849: } ! 1850: } ! 1851: else if (GET_CODE (operands[1]) == MEM) ! 1852: { ! 1853: if (! TARGET_DW_ENABLE) ! 1854: { ! 1855: emit_insn (gen_loadqi (XEXP (operands[1], 0), operands[0])); ! 1856: DONE; ! 1857: } ! 1858: } ! 1859: }") ! 1860: ! 1861: ;; Now the actual insns used to move data around. We include here the ! 1862: ;; DEFINE_SPLITs that may be needed. In some cases these will be ! 1863: ;; split again. For floating-point, if we can look inside the constant, ! 1864: ;; always split it. This can eliminate unnecessary insns. ! 1865: (define_insn "" ! 1866: [(set (match_operand:SF 0 "out_operand" "=r,r,r,r,m") ! 1867: (match_operand:SF 1 "in_operand" "r,E,F,m,r"))] ! 1868: "(gen_reg_operand (operands[0], SFmode) ! 1869: || gen_reg_operand (operands[1], SFmode)) ! 1870: && ! TARGET_29050" ! 1871: "@ ! 1872: sll %0,%1,0 ! 1873: # ! 1874: const %0,%1\;consth %0,%1 ! 1875: load 0,0,%0,%1 ! 1876: store 0,0,%1,%0" ! 1877: [(set_attr "type" "misc,multi,multi,load,store")]) ! 1878: ! 1879: (define_insn "" ! 1880: [(set (match_operand:SF 0 "out_operand" "=r,r,r,r,m,*a,r") ! 1881: (match_operand:SF 1 "in_operand" "r,E,F,m,r,r,*a"))] ! 1882: "(gen_reg_operand (operands[0], SFmode) ! 1883: || gen_reg_operand (operands[1], SFmode)) ! 1884: && TARGET_29050" ! 1885: "@ ! 1886: sll %0,%1,0 ! 1887: # ! 1888: const %0,%1\;consth %0,%1 ! 1889: load 0,0,%0,%1 ! 1890: store 0,0,%1,%0 ! 1891: mtacc %1,1,%0 ! 1892: mfacc %0,1,%1" ! 1893: [(set_attr "type" "misc,multi,multi,load,store,fadd,fadd")]) ! 1894: ! 1895: ;; Turn this into SImode. It will then be split up that way. ! 1896: (define_split ! 1897: [(set (match_operand:SF 0 "register_operand" "") ! 1898: (match_operand:SF 1 "float_const_operand" ""))] ! 1899: "HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT" ! 1900: [(set (match_dup 0) ! 1901: (match_dup 1))] ! 1902: " ! 1903: { operands[0] = operand_subword (operands[0], 0, 0, SFmode); ! 1904: operands[1] = operand_subword (operands[1], 0, 0, SFmode); ! 1905: ! 1906: if (operands[0] == 0 || operands[1] == 0) ! 1907: FAIL; ! 1908: }") ! 1909: ! 1910: (define_insn "" ! 1911: [(set (match_operand:DF 0 "out_operand" "=r,r,r,m") ! 1912: (match_operand:DF 1 "in_operand" "rE,F,m,r")) ! 1913: (clobber (reg:SI 179))] ! 1914: "(gen_reg_operand (operands[0], DFmode) ! 1915: || gen_reg_operand (operands[1], DFmode)) ! 1916: && ! TARGET_29050" ! 1917: "@ ! 1918: # ! 1919: const %0,%1\;consth %0,%1\;const %L0,%L1\;consth %L0,%L1 ! 1920: mtsrim cr,1\;loadm 0,0,%0,%1 ! 1921: mtsrim cr,1\;storem 0,0,%1,%0" ! 1922: [(set_attr "type" "multi")]) ! 1923: ! 1924: (define_insn "" ! 1925: [(set (match_operand:DF 0 "out_operand" "=r,r,&r,m,*a,r") ! 1926: (match_operand:DF 1 "in_operand" "rE,F,m,r,r,*a")) ! 1927: (clobber (reg:SI 179))] ! 1928: "(gen_reg_operand (operands[0], DFmode) ! 1929: || gen_reg_operand (operands[1], DFmode)) ! 1930: && TARGET_29050" ! 1931: "@ ! 1932: # ! 1933: const %0,%1\;consth %0,%1\;const %L0,%L1\;consth %L0,%L1 ! 1934: mtsrim cr,1\;loadm 0,0,%0,%1 ! 1935: mtsrim cr,1\;storem 0,0,%1,%0 ! 1936: mtacc %1,2,%0 ! 1937: mfacc %0,2,%1" ! 1938: [(set_attr "type" "multi,multi,multi,multi,fadd,fadd")]) ! 1939: ! 1940: ;; Split register-register copies and constant loads into two SImode loads, ! 1941: ;; one for each word. In the constant case, they will get further split. ! 1942: ;; Don't so this until register allocation, though, since it will ! 1943: ;; interfere with register allocation. Normally copy the lowest-addressed ! 1944: ;; word first; the exception is if we are copying register to register and ! 1945: ;; the lowest register of the first operand is the highest register of the ! 1946: ;; second operand. ! 1947: (define_split ! 1948: [(set (match_operand:DF 0 "gen_reg_operand" "") ! 1949: (match_operand:DF 1 "gen_reg_or_float_constant_operand" "")) ! 1950: (clobber (reg:SI 179))] ! 1951: "reload_completed" ! 1952: [(set (match_dup 2) (match_dup 3)) ! 1953: (set (match_dup 4) (match_dup 5))] ! 1954: " ! 1955: { if (GET_CODE (operands[1]) == REG ! 1956: && REGNO (operands[0]) == REGNO (operands[1]) + 1) ! 1957: { ! 1958: operands[2] = operand_subword (operands[0], 1, 1, DFmode); ! 1959: operands[3] = operand_subword (operands[1], 1, 1, DFmode); ! 1960: operands[4] = operand_subword (operands[0], 0, 1, DFmode); ! 1961: operands[5] = operand_subword (operands[1], 0, 1, DFmode); ! 1962: } ! 1963: else ! 1964: { ! 1965: operands[2] = operand_subword (operands[0], 0, 1, DFmode); ! 1966: operands[3] = operand_subword (operands[1], 0, 1, DFmode); ! 1967: operands[4] = operand_subword (operands[0], 1, 1, DFmode); ! 1968: operands[5] = operand_subword (operands[1], 1, 1, DFmode); ! 1969: } ! 1970: ! 1971: if (operands[2] == 0 || operands[3] == 0 ! 1972: || operands[4] == 0 || operands[5] == 0) ! 1973: FAIL; ! 1974: }") ! 1975: ! 1976: ;; Split memory loads and stores into the MTSR and LOADM/STOREM. ! 1977: (define_split ! 1978: [(set (match_operand:DF 0 "out_operand" "") ! 1979: (match_operand:DF 1 "in_operand" "")) ! 1980: (clobber (reg:SI 179))] ! 1981: "TARGET_NO_STOREM_BUG ! 1982: && (memory_operand (operands[0], DFmode) ! 1983: || memory_operand (operands[1], DFmode))" ! 1984: [(set (reg:SI 179) (const_int 1)) ! 1985: (parallel [(set (match_dup 0) (match_dup 1)) ! 1986: (use (reg:SI 179)) ! 1987: (clobber (reg:SI 179))])] ! 1988: "") ! 1989: ! 1990: ;; DI move is similar to DF move. ! 1991: (define_insn "" ! 1992: [(set (match_operand:DI 0 "out_operand" "=r,r,m") ! 1993: (match_operand:DI 1 "in_operand" "rn,m,r")) ! 1994: (clobber (reg:SI 179))] ! 1995: "(gen_reg_operand (operands[0], DImode) ! 1996: || gen_reg_operand (operands[1], DImode)) ! 1997: && ! TARGET_29050" ! 1998: "@ ! 1999: # ! 2000: mtsrim cr,1\;loadm 0,0,%0,%1 ! 2001: mtsrim cr,1\;storem 0,0,%1,%0" ! 2002: [(set_attr "type" "multi")]) ! 2003: ! 2004: (define_insn "" ! 2005: [(set (match_operand:DI 0 "out_operand" "=r,&r,m") ! 2006: (match_operand:DI 1 "in_operand" "rn,m,r")) ! 2007: (clobber (reg:SI 179))] ! 2008: "(gen_reg_operand (operands[0], DImode) ! 2009: || gen_reg_operand (operands[1], DImode)) ! 2010: && TARGET_29050" ! 2011: "@ ! 2012: # ! 2013: mtsrim cr,1\;loadm 0,0,%0,%1 ! 2014: mtsrim cr,1\;storem 0,0,%1,%0" ! 2015: [(set_attr "type" "multi")]) ! 2016: ! 2017: (define_split ! 2018: [(set (match_operand:DI 0 "gen_reg_operand" "") ! 2019: (match_operand:DI 1 "gen_reg_or_integer_constant_operand" "")) ! 2020: (clobber (reg:SI 179))] ! 2021: "reload_completed" ! 2022: [(set (match_dup 2) (match_dup 3)) ! 2023: (set (match_dup 4) (match_dup 5))] ! 2024: " ! 2025: { if (GET_CODE (operands[1]) == REG ! 2026: && REGNO (operands[0]) == REGNO (operands[1]) + 1) ! 2027: { ! 2028: operands[2] = operand_subword (operands[0], 1, 1, DImode); ! 2029: operands[3] = operand_subword (operands[1], 1, 1, DImode); ! 2030: operands[4] = operand_subword (operands[0], 0, 1, DImode); ! 2031: operands[5] = operand_subword (operands[1], 0, 1, DImode); ! 2032: } ! 2033: else ! 2034: { ! 2035: operands[2] = operand_subword (operands[0], 0, 1, DImode); ! 2036: operands[3] = operand_subword (operands[1], 0, 1, DImode); ! 2037: operands[4] = operand_subword (operands[0], 1, 1, DImode); ! 2038: operands[5] = operand_subword (operands[1], 1, 1, DImode); ! 2039: } ! 2040: }") ! 2041: ! 2042: (define_split ! 2043: [(set (match_operand:DI 0 "out_operand" "") ! 2044: (match_operand:DI 1 "in_operand" "")) ! 2045: (clobber (reg:SI 179))] ! 2046: "TARGET_NO_STOREM_BUG ! 2047: && (memory_operand (operands[0], DImode) ! 2048: || memory_operand (operands[1], DImode))" ! 2049: [(set (reg:SI 179) (const_int 1)) ! 2050: (parallel [(set (match_dup 0) (match_dup 1)) ! 2051: (use (reg:SI 179)) ! 2052: (clobber (reg:SI 179))])] ! 2053: "") ! 2054: ! 2055: ;; TImode moves are very similar to DImode moves, except that we can't ! 2056: ;; have constants. ! 2057: (define_insn "" ! 2058: [(set (match_operand:TI 0 "out_operand" "=r,r,m") ! 2059: (match_operand:TI 1 "in_operand" "r,m,r")) ! 2060: (clobber (reg:SI 179))] ! 2061: "(gen_reg_operand (operands[0], TImode) ! 2062: || gen_reg_operand (operands[1], TImode)) ! 2063: && ! TARGET_29050" ! 2064: "@ ! 2065: # ! 2066: mtsrim cr,3\;loadm 0,0,%0,%1 ! 2067: mtsrim cr,3\;storem 0,0,%1,%0" ! 2068: [(set_attr "type" "multi,multi,multi")]) ! 2069: ! 2070: (define_insn "" ! 2071: [(set (match_operand:TI 0 "out_operand" "=r,&r,m") ! 2072: (match_operand:TI 1 "in_operand" "r,m,r")) ! 2073: (clobber (reg:SI 179))] ! 2074: "(gen_reg_operand (operands[0], TImode) ! 2075: || gen_reg_operand (operands[1], TImode)) ! 2076: && TARGET_29050" ! 2077: "@ ! 2078: # ! 2079: mtsrim cr,3\;loadm 0,0,%0,%1 ! 2080: mtsrim cr,3\;storem 0,0,%1,%0" ! 2081: [(set_attr "type" "multi,multi,multi")]) ! 2082: ! 2083: (define_split ! 2084: [(set (match_operand:TI 0 "gen_reg_operand" "") ! 2085: (match_operand:TI 1 "gen_reg_operand" "")) ! 2086: (clobber (reg:SI 179))] ! 2087: "reload_completed" ! 2088: [(set (match_dup 2) (match_dup 3)) ! 2089: (set (match_dup 4) (match_dup 5)) ! 2090: (set (match_dup 6) (match_dup 7)) ! 2091: (set (match_dup 8) (match_dup 9))] ! 2092: " ! 2093: { ! 2094: if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 ! 2095: && REGNO (operands[0]) <= REGNO (operands[1]) + 3) ! 2096: { ! 2097: operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 3); ! 2098: operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 3); ! 2099: operands[4] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2); ! 2100: operands[5] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2); ! 2101: operands[6] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); ! 2102: operands[7] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); ! 2103: operands[8] = gen_rtx (REG, SImode, REGNO (operands[0])); ! 2104: operands[9] = gen_rtx (REG, SImode, REGNO (operands[1])); ! 2105: } ! 2106: else ! 2107: { ! 2108: operands[2] = gen_rtx (REG, SImode, REGNO (operands[0])); ! 2109: operands[3] = gen_rtx (REG, SImode, REGNO (operands[1])); ! 2110: operands[4] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); ! 2111: operands[5] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); ! 2112: operands[6] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2); ! 2113: operands[7] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2); ! 2114: operands[8] = gen_rtx (REG, SImode, REGNO (operands[0]) + 3); ! 2115: operands[9] = gen_rtx (REG, SImode, REGNO (operands[1]) + 3); ! 2116: } ! 2117: }") ! 2118: ! 2119: (define_split ! 2120: [(set (match_operand:TI 0 "out_operand" "") ! 2121: (match_operand:TI 1 "in_operand" "")) ! 2122: (clobber (reg:SI 179))] ! 2123: "TARGET_NO_STOREM_BUG ! 2124: && (memory_operand (operands[0], TImode) ! 2125: || memory_operand (operands[1], TImode))" ! 2126: [(set (reg:SI 179) (const_int 1)) ! 2127: (parallel [(set (match_dup 0) (match_dup 1)) ! 2128: (use (reg:SI 179)) ! 2129: (clobber (reg:SI 179))])] ! 2130: "") ! 2131: ! 2132: (define_insn "" ! 2133: [(set (match_operand:SI 0 "out_operand" "=r,r,r,r,r,r,r,m,*h,*h") ! 2134: (match_operand:SI 1 "in_operand" "r,J,M,O,i,m,*h,r,r,J"))] ! 2135: "(gen_reg_operand (operands[0], SImode) ! 2136: || gen_reg_operand (operands[1], SImode) ! 2137: || (spec_reg_operand (operands[0], SImode) ! 2138: && cint_16_operand (operands[1], SImode))) ! 2139: && ! TARGET_29050" ! 2140: "@ ! 2141: sll %0,%1,0 ! 2142: const %0,%1 ! 2143: constn %0,%M1 ! 2144: cpeq %0,gr1,gr1 ! 2145: # ! 2146: load 0,0,%0,%1 ! 2147: mfsr %0,%1 ! 2148: store 0,0,%1,%0 ! 2149: mtsr %0,%1 ! 2150: mtsrim %0,%1" ! 2151: [(set_attr "type" "misc,misc,misc,misc,multi,load,misc,store,misc,misc")]) ! 2152: ! 2153: (define_insn "" ! 2154: [(set (match_operand:SI 0 "out_operand" "=r,r,r,r,r,r,r,m,*h,*h") ! 2155: (match_operand:SI 1 "in_operand" "r,J,M,O,i,m,*h,r,r,J"))] ! 2156: "(gen_reg_operand (operands[0], SImode) ! 2157: || gen_reg_operand (operands[1], SImode) ! 2158: || (spec_reg_operand (operands[0], SImode) ! 2159: && cint_16_operand (operands[1], SImode))) ! 2160: && TARGET_29050" ! 2161: "@ ! 2162: sll %0,%1,0 ! 2163: const %0,%1 ! 2164: constn %0,%M1 ! 2165: consthz %0,%1 ! 2166: # ! 2167: load 0,0,%0,%1 ! 2168: mfsr %0,%1 ! 2169: store 0,0,%1,%0 ! 2170: mtsr %0,%1 ! 2171: mtsrim %0,%1" ! 2172: [(set_attr "type" "misc,misc,misc,misc,multi,load,misc,store,misc,misc")]) ! 2173: ! 2174: (define_insn "" ! 2175: [(set (match_operand:HI 0 "out_operand" "=r,r,r,m,r,*h,*h") ! 2176: (match_operand:HI 1 "in_operand" "r,i,m,r,*h,r,i"))] ! 2177: "gen_reg_operand (operands[0], HImode) ! 2178: || gen_reg_operand (operands[1], HImode)" ! 2179: "@ ! 2180: sll %0,%1,0 ! 2181: const %0,%1 ! 2182: load 0,2,%0,%1 ! 2183: store 0,2,%1,%0 ! 2184: mfsr %0,%1 ! 2185: mtsr %0,%1 ! 2186: mtsrim %0,%1" ! 2187: [(set_attr "type" "misc,misc,load,store,misc,misc,misc")]) ! 2188: ! 2189: (define_insn "" ! 2190: [(set (match_operand:QI 0 "out_operand" "=r,r,r,m,r,*h,*h") ! 2191: (match_operand:QI 1 "in_operand" "r,i,m,r,*h,r,i"))] ! 2192: "gen_reg_operand (operands[0], QImode) ! 2193: || gen_reg_operand (operands[1], QImode)" ! 2194: "@ ! 2195: sll %0,%1,0 ! 2196: const %0,%1 ! 2197: load 0,1,%0,%1 ! 2198: store 0,1,%1,%0 ! 2199: mfsr %0,%1 ! 2200: mtsr %0,%1 ! 2201: mtsrim %0,%1" ! 2202: [(set_attr "type" "misc,misc,load,store,misc,misc,misc")]) ! 2203: ! 2204: ;; Define move insns for DI, TI, SF, and DF. ! 2205: ;; ! 2206: ;; In no case do we support mem->mem directly. ! 2207: ;; ! 2208: ;; For DI move of constant to register, split apart at this time since these ! 2209: ;; can require anywhere from 2 to 4 insns and determining which is complex. ! 2210: ;; ! 2211: ;; In other cases, handle similarly to SImode moves. ! 2212: ;; ! 2213: ;; However, indicate that DI, TI, and DF moves (can) clobber CR (reg 179). ! 2214: (define_expand "movdi" ! 2215: [(parallel [(set (match_operand:DI 0 "general_operand" "") ! 2216: (match_operand:DI 1 "general_operand" "")) ! 2217: (clobber (reg:SI 179))])] ! 2218: "" ! 2219: " ! 2220: { ! 2221: if (GET_CODE (operands[0]) == MEM) ! 2222: operands[1] = force_reg (DImode, operands[1]); ! 2223: }") ! 2224: ! 2225: (define_expand "movsf" ! 2226: [(set (match_operand:SF 0 "general_operand" "") ! 2227: (match_operand:SF 1 "general_operand" ""))] ! 2228: "" ! 2229: " ! 2230: { if (GET_CODE (operands[0]) == MEM) ! 2231: operands[1] = force_reg (SFmode, operands[1]); ! 2232: }") ! 2233: ! 2234: (define_expand "movdf" ! 2235: [(parallel [(set (match_operand:DF 0 "general_operand" "") ! 2236: (match_operand:DF 1 "general_operand" "")) ! 2237: (clobber (reg:SI 179))])] ! 2238: "" ! 2239: " ! 2240: { if (GET_CODE (operands[0]) == MEM) ! 2241: operands[1] = force_reg (DFmode, operands[1]); ! 2242: }") ! 2243: ! 2244: (define_expand "movti" ! 2245: [(parallel [(set (match_operand:TI 0 "general_operand" "") ! 2246: (match_operand:TI 1 "general_operand" "")) ! 2247: (clobber (reg:SI 179))])] ! 2248: "" ! 2249: " ! 2250: { ! 2251: if (GET_CODE (operands[0]) == MEM) ! 2252: operands[1] = force_reg (TImode, operands[1]); ! 2253: }") ! 2254: ! 2255: ;; For compare operations, we simply store the comparison operands and ! 2256: ;; do nothing else. The following branch or scc insn will output whatever ! 2257: ;; is needed. ! 2258: (define_expand "cmpsi" ! 2259: [(set (cc0) ! 2260: (compare (match_operand:SI 0 "gen_reg_operand" "") ! 2261: (match_operand:SI 1 "srcb_operand" "")))] ! 2262: "" ! 2263: " ! 2264: { ! 2265: a29k_compare_op0 = operands[0]; ! 2266: a29k_compare_op1 = operands[1]; ! 2267: a29k_compare_fp_p = 0; ! 2268: DONE; ! 2269: }") ! 2270: ! 2271: (define_expand "cmpsf" ! 2272: [(set (cc0) ! 2273: (compare (match_operand:SF 0 "gen_reg_operand" "") ! 2274: (match_operand:SF 1 "gen_reg_operand" "")))] ! 2275: "" ! 2276: " ! 2277: { ! 2278: a29k_compare_op0 = operands[0]; ! 2279: a29k_compare_op1 = operands[1]; ! 2280: a29k_compare_fp_p = 1; ! 2281: DONE; ! 2282: }") ! 2283: ! 2284: (define_expand "cmpdf" ! 2285: [(set (cc0) ! 2286: (compare (match_operand:DF 0 "gen_reg_operand" "") ! 2287: (match_operand:DF 1 "gen_reg_operand" "")))] ! 2288: "" ! 2289: " ! 2290: { ! 2291: a29k_compare_op0 = operands[0]; ! 2292: a29k_compare_op1 = operands[1]; ! 2293: a29k_compare_fp_p = 1; ! 2294: DONE; ! 2295: }") ! 2296: ! 2297: ;; We can generate bit-tests better if we use NE instead of EQ, but we ! 2298: ;; don't have an NE for floating-point. So we have to have two patterns ! 2299: ;; for EQ and two for NE. ! 2300: ! 2301: (define_expand "beq" ! 2302: [(set (match_dup 1) (ne:SI (match_dup 2) (match_dup 3))) ! 2303: (set (pc) ! 2304: (if_then_else (ge (match_dup 1) (const_int 0)) ! 2305: (label_ref (match_operand 0 "" "")) ! 2306: (pc)))] ! 2307: "" ! 2308: " ! 2309: { ! 2310: if (GET_MODE_CLASS (GET_MODE (a29k_compare_op0)) == MODE_FLOAT) ! 2311: { ! 2312: emit_insn (gen_beq_fp (operands[0])); ! 2313: DONE; ! 2314: } ! 2315: ! 2316: operands[1] = gen_reg_rtx (SImode); ! 2317: operands[2] = a29k_compare_op0; ! 2318: operands[3] = a29k_compare_op1; ! 2319: }") ! 2320: ! 2321: (define_expand "beq_fp" ! 2322: [(set (match_dup 1) (eq:SI (match_dup 2) (match_dup 3))) ! 2323: (set (pc) ! 2324: (if_then_else (lt (match_dup 1) (const_int 0)) ! 2325: (label_ref (match_operand 0 "" "")) ! 2326: (pc)))] ! 2327: "" ! 2328: " ! 2329: { ! 2330: operands[1] = gen_reg_rtx (SImode); ! 2331: operands[2] = a29k_compare_op0; ! 2332: operands[3] = a29k_compare_op1; ! 2333: }") ! 2334: ! 2335: (define_expand "bne" ! 2336: [(set (match_dup 1) (ne:SI (match_dup 2) (match_dup 3))) ! 2337: (set (pc) ! 2338: (if_then_else (lt (match_dup 1) (const_int 0)) ! 2339: (label_ref (match_operand 0 "" "")) ! 2340: (pc)))] ! 2341: "" ! 2342: " ! 2343: { ! 2344: if (GET_MODE_CLASS (GET_MODE (a29k_compare_op0)) == MODE_FLOAT) ! 2345: { ! 2346: emit_insn (gen_bne_fp (operands[0])); ! 2347: DONE; ! 2348: } ! 2349: ! 2350: operands[1] = gen_reg_rtx (SImode); ! 2351: operands[2] = a29k_compare_op0; ! 2352: operands[3] = a29k_compare_op1; ! 2353: }") ! 2354: ! 2355: (define_expand "bne_fp" ! 2356: [(set (match_dup 1) (eq:SI (match_dup 2) (match_dup 3))) ! 2357: (set (pc) ! 2358: (if_then_else (ge (match_dup 1) (const_int 0)) ! 2359: (label_ref (match_operand 0 "" "")) ! 2360: (pc)))] ! 2361: "" ! 2362: " ! 2363: { ! 2364: operands[1] = gen_reg_rtx (SImode); ! 2365: operands[2] = a29k_compare_op0; ! 2366: operands[3] = a29k_compare_op1; ! 2367: }") ! 2368: ! 2369: ;; We don't have a floating-point "lt" insn, so we have to use "gt" in that ! 2370: ;; case with the operands swapped. The operands must both be registers in ! 2371: ;; the floating-point case, so we know that swapping them is OK. ! 2372: (define_expand "blt" ! 2373: [(set (match_dup 1) (match_dup 2)) ! 2374: (set (pc) ! 2375: (if_then_else (lt (match_dup 1) (const_int 0)) ! 2376: (label_ref (match_operand 0 "" "")) ! 2377: (pc)))] ! 2378: "" ! 2379: " ! 2380: { ! 2381: operands[1] = gen_reg_rtx (SImode); ! 2382: if (a29k_compare_fp_p) ! 2383: operands[2] = gen_rtx (GT, SImode, a29k_compare_op1, a29k_compare_op0); ! 2384: else ! 2385: operands[2] = gen_rtx (LT, SImode, a29k_compare_op0, a29k_compare_op1); ! 2386: }") ! 2387: ! 2388: ;; Similarly for "le". ! 2389: (define_expand "ble" ! 2390: [(set (match_dup 1) (match_dup 2)) ! 2391: (set (pc) ! 2392: (if_then_else (lt (match_dup 1) (const_int 0)) ! 2393: (label_ref (match_operand 0 "" "")) ! 2394: (pc)))] ! 2395: "" ! 2396: " ! 2397: { ! 2398: operands[1] = gen_reg_rtx (SImode); ! 2399: if (a29k_compare_fp_p) ! 2400: operands[2] = gen_rtx (GE, SImode, a29k_compare_op1, a29k_compare_op0); ! 2401: else ! 2402: operands[2] = gen_rtx (LE, SImode, a29k_compare_op0, a29k_compare_op1); ! 2403: }") ! 2404: ! 2405: (define_expand "bltu" ! 2406: [(set (match_dup 1) (ltu:SI (match_dup 2) (match_dup 3))) ! 2407: (set (pc) ! 2408: (if_then_else (lt (match_dup 1) (const_int 0)) ! 2409: (label_ref (match_operand 0 "" "")) ! 2410: (pc)))] ! 2411: "" ! 2412: " ! 2413: { ! 2414: operands[1] = gen_reg_rtx (SImode); ! 2415: operands[2] = a29k_compare_op0; ! 2416: operands[3] = a29k_compare_op1; ! 2417: }") ! 2418: ! 2419: (define_expand "bleu" ! 2420: [(set (match_dup 1) (leu:SI (match_dup 2) (match_dup 3))) ! 2421: (set (pc) ! 2422: (if_then_else (lt (match_dup 1) (const_int 0)) ! 2423: (label_ref (match_operand 0 "" "")) ! 2424: (pc)))] ! 2425: "" ! 2426: " ! 2427: { ! 2428: operands[1] = gen_reg_rtx (SImode); ! 2429: operands[2] = a29k_compare_op0; ! 2430: operands[3] = a29k_compare_op1; ! 2431: }") ! 2432: ! 2433: (define_expand "bgt" ! 2434: [(set (match_dup 1) (gt:SI (match_dup 2) (match_dup 3))) ! 2435: (set (pc) ! 2436: (if_then_else (lt (match_dup 1) (const_int 0)) ! 2437: (label_ref (match_operand 0 "" "")) ! 2438: (pc)))] ! 2439: "" ! 2440: " ! 2441: { ! 2442: operands[1] = gen_reg_rtx (SImode); ! 2443: operands[2] = a29k_compare_op0; ! 2444: operands[3] = a29k_compare_op1; ! 2445: }") ! 2446: ! 2447: (define_expand "bge" ! 2448: [(set (match_dup 1) (ge:SI (match_dup 2) (match_dup 3))) ! 2449: (set (pc) ! 2450: (if_then_else (lt (match_dup 1) (const_int 0)) ! 2451: (label_ref (match_operand 0 "" "")) ! 2452: (pc)))] ! 2453: "" ! 2454: " ! 2455: { ! 2456: operands[1] = gen_reg_rtx (SImode); ! 2457: operands[2] = a29k_compare_op0; ! 2458: operands[3] = a29k_compare_op1; ! 2459: }") ! 2460: ! 2461: (define_expand "bgtu" ! 2462: [(set (match_dup 1) (gtu:SI (match_dup 2) (match_dup 3))) ! 2463: (set (pc) ! 2464: (if_then_else (lt (match_dup 1) (const_int 0)) ! 2465: (label_ref (match_operand 0 "" "")) ! 2466: (pc)))] ! 2467: "" ! 2468: " ! 2469: { ! 2470: operands[1] = gen_reg_rtx (SImode); ! 2471: operands[2] = a29k_compare_op0; ! 2472: operands[3] = a29k_compare_op1; ! 2473: }") ! 2474: ! 2475: (define_expand "bgeu" ! 2476: [(set (match_dup 1) (geu:SI (match_dup 2) (match_dup 3))) ! 2477: (set (pc) ! 2478: (if_then_else (lt (match_dup 1) (const_int 0)) ! 2479: (label_ref (match_operand 0 "" "")) ! 2480: (pc)))] ! 2481: "" ! 2482: " ! 2483: { ! 2484: operands[1] = gen_reg_rtx (SImode); ! 2485: operands[2] = a29k_compare_op0; ! 2486: operands[3] = a29k_compare_op1; ! 2487: }") ! 2488: ! 2489: (define_expand "seq" ! 2490: [(set (match_operand:SI 0 "gen_reg_operand" "") ! 2491: (eq:SI (match_dup 1) (match_dup 2)))] ! 2492: "" ! 2493: " ! 2494: { ! 2495: operands[1] = a29k_compare_op0; ! 2496: operands[2] = a29k_compare_op1; ! 2497: }") ! 2498: ! 2499: ;; This is the most complicated case, because we don't have a floating-point ! 2500: ;; "ne" insn. If integer, handle normally. If floating-point, write the ! 2501: ;; compare and then write an insn to reverse the test. ! 2502: (define_expand "sne_fp" ! 2503: [(set (match_dup 3) ! 2504: (eq:SI (match_operand 1 "gen_reg_operand" "") ! 2505: (match_operand 2 "gen_reg_operand" ""))) ! 2506: (set (match_operand:SI 0 "gen_reg_operand" "") ! 2507: (ge:SI (match_dup 3) (const_int 0)))] ! 2508: "" ! 2509: " ! 2510: { operands[3] = gen_reg_rtx (SImode); ! 2511: }"); ! 2512: ! 2513: (define_expand "sne" ! 2514: [(set (match_operand:SI 0 "gen_reg_operand" "") ! 2515: (ne:SI (match_dup 1) (match_dup 2)))] ! 2516: "" ! 2517: " ! 2518: { ! 2519: operands[1] = a29k_compare_op0; ! 2520: operands[2] = a29k_compare_op1; ! 2521: ! 2522: if (a29k_compare_fp_p) ! 2523: { ! 2524: emit_insn (gen_sne_fp (operands[0], operands[1], operands[2])); ! 2525: DONE; ! 2526: } ! 2527: }") ! 2528: ! 2529: ;; We don't have a floating-point "lt" insn, so use "gt" and swap the ! 2530: ;; operands, the same as we do "blt". ! 2531: (define_expand "slt" ! 2532: [(set (match_operand:SI 0 "gen_reg_operand" "") ! 2533: (match_dup 1))] ! 2534: "" ! 2535: " ! 2536: { ! 2537: if (a29k_compare_fp_p) ! 2538: operands[1] = gen_rtx (GT, SImode, a29k_compare_op1, a29k_compare_op0); ! 2539: else ! 2540: operands[1] = gen_rtx (LT, SImode, a29k_compare_op0, a29k_compare_op1); ! 2541: }") ! 2542: ! 2543: ;; Similarly for "le" ! 2544: (define_expand "sle" ! 2545: [(set (match_operand:SI 0 "gen_reg_operand" "") ! 2546: (match_dup 1))] ! 2547: "" ! 2548: " ! 2549: { ! 2550: if (a29k_compare_fp_p) ! 2551: operands[1] = gen_rtx (GE, SImode, a29k_compare_op1, a29k_compare_op0); ! 2552: else ! 2553: operands[1] = gen_rtx (LE, SImode, a29k_compare_op0, a29k_compare_op1); ! 2554: }") ! 2555: ! 2556: (define_expand "sltu" ! 2557: [(set (match_operand:SI 0 "gen_reg_operand" "") ! 2558: (ltu:SI (match_dup 1) (match_dup 2)))] ! 2559: "" ! 2560: " ! 2561: { ! 2562: operands[1] = a29k_compare_op0; ! 2563: operands[2] = a29k_compare_op1; ! 2564: }") ! 2565: ! 2566: (define_expand "sleu" ! 2567: [(set (match_operand:SI 0 "gen_reg_operand" "") ! 2568: (leu:SI (match_dup 1) (match_dup 2)))] ! 2569: "" ! 2570: " ! 2571: { ! 2572: operands[1] = a29k_compare_op0; ! 2573: operands[2] = a29k_compare_op1; ! 2574: }") ! 2575: ! 2576: (define_expand "sgt" ! 2577: [(set (match_operand:SI 0 "gen_reg_operand" "") ! 2578: (gt:SI (match_dup 1) (match_dup 2)))] ! 2579: "" ! 2580: " ! 2581: { ! 2582: operands[1] = a29k_compare_op0; ! 2583: operands[2] = a29k_compare_op1; ! 2584: }") ! 2585: ! 2586: (define_expand "sge" ! 2587: [(set (match_operand:SI 0 "gen_reg_operand" "") ! 2588: (ge:SI (match_dup 1) (match_dup 2)))] ! 2589: "" ! 2590: " ! 2591: { ! 2592: operands[1] = a29k_compare_op0; ! 2593: operands[2] = a29k_compare_op1; ! 2594: }") ! 2595: ! 2596: (define_expand "sgtu" ! 2597: [(set (match_operand:SI 0 "gen_reg_operand" "") ! 2598: (gtu:SI (match_dup 1) (match_dup 2)))] ! 2599: "" ! 2600: " ! 2601: { ! 2602: operands[1] = a29k_compare_op0; ! 2603: operands[2] = a29k_compare_op1; ! 2604: }") ! 2605: ! 2606: (define_expand "sgeu" ! 2607: [(set (match_operand:SI 0 "gen_reg_operand" "") ! 2608: (geu:SI (match_dup 1) (match_dup 2)))] ! 2609: "" ! 2610: " ! 2611: { ! 2612: operands[1] = a29k_compare_op0; ! 2613: operands[2] = a29k_compare_op1; ! 2614: }") ! 2615: ! 2616: ;; Now define the actual jump insns. ! 2617: (define_insn "" ! 2618: [(set (pc) ! 2619: (if_then_else (match_operator 0 "branch_operator" ! 2620: [(match_operand:SI 1 "gen_reg_operand" "r") ! 2621: (const_int 0)]) ! 2622: (label_ref (match_operand 2 "" "")) ! 2623: (pc)))] ! 2624: "" ! 2625: "jmp%b0 %1,%l2%#" ! 2626: [(set_attr "type" "branch")]) ! 2627: ! 2628: (define_insn "" ! 2629: [(set (pc) ! 2630: (if_then_else (match_operator 0 "branch_operator" ! 2631: [(match_operand:SI 1 "gen_reg_operand" "r") ! 2632: (const_int 0)]) ! 2633: (return) ! 2634: (pc)))] ! 2635: "null_epilogue ()" ! 2636: "jmp%b0i %1,lr0%#" ! 2637: [(set_attr "type" "branch")]) ! 2638: ! 2639: (define_insn "" ! 2640: [(set (pc) ! 2641: (if_then_else (match_operator 0 "branch_operator" ! 2642: [(match_operand:SI 1 "gen_reg_operand" "r") ! 2643: (const_int 0)]) ! 2644: (pc) ! 2645: (label_ref (match_operand 2 "" ""))))] ! 2646: "" ! 2647: "jmp%B0 %1,%l2%#" ! 2648: [(set_attr "type" "branch")]) ! 2649: ! 2650: (define_insn "" ! 2651: [(set (pc) ! 2652: (if_then_else (match_operator 0 "branch_operator" ! 2653: [(match_operand:SI 1 "gen_reg_operand" "r") ! 2654: (const_int 0)]) ! 2655: (pc) ! 2656: (return)))] ! 2657: "null_epilogue ()" ! 2658: "jmp%B0i %1,lr0%#" ! 2659: [(set_attr "type" "branch")]) ! 2660: ! 2661: (define_insn "jump" ! 2662: [(set (pc) ! 2663: (label_ref (match_operand 0 "" "")))] ! 2664: "" ! 2665: "jmp %e0%E0" ! 2666: [(set_attr "type" "branch")]) ! 2667: ! 2668: (define_insn "return" ! 2669: [(return)] ! 2670: "null_epilogue ()" ! 2671: "jmpi lr0%#" ! 2672: [(set_attr "type" "branch")]) ! 2673: ! 2674: (define_insn "indirect_jump" ! 2675: [(set (pc) ! 2676: (match_operand:SI 0 "gen_reg_operand" "r"))] ! 2677: "" ! 2678: "jmpi %0%#" ! 2679: [(set_attr "type" "branch")]) ! 2680: ! 2681: (define_insn "tablejump" ! 2682: [(set (pc) ! 2683: (match_operand:SI 0 "gen_reg_operand" "r")) ! 2684: (use (label_ref (match_operand 1 "" "")))] ! 2685: "" ! 2686: "jmpi %0%#" ! 2687: [(set_attr "type" "branch")]) ! 2688: ! 2689: ;; JMPFDEC ! 2690: (define_insn "" ! 2691: [(set (pc) ! 2692: (if_then_else (ge (match_operand:SI 0 "gen_reg_operand" "r") ! 2693: (const_int 0)) ! 2694: (label_ref (match_operand 1 "" "")) ! 2695: (pc))) ! 2696: (set (match_dup 0) ! 2697: (plus:SI (match_dup 0) ! 2698: (const_int -1)))] ! 2699: "" ! 2700: "jmpfdec %0,%l1%#" ! 2701: [(set_attr "type" "branch")]) ! 2702: ! 2703: ;;- Local variables: ! 2704: ;;- mode:emacs-lisp ! 2705: ;;- comment-start: ";;- " ! 2706: ;;- eval: (set-syntax-table (copy-sequence (syntax-table))) ! 2707: ;;- eval: (modify-syntax-entry ?[ "(]") ! 2708: ;;- eval: (modify-syntax-entry ?] ")[") ! 2709: ;;- eval: (modify-syntax-entry ?{ "(}") ! 2710: ;;- eval: (modify-syntax-entry ?} "){") ! 2711: ;;- End:
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