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1.1 root 1: ;;- Machine description for AMD Am29000 for GNU C compiler 1.1.1.4 ! root 2: ;; Copyright (C) 1991, 1992 Free Software Foundation, Inc. 1.1 root 3: ;; Contributed by Richard Kenner ([email protected]) 4: 5: ;; This file is part of GNU CC. 6: 7: ;; GNU CC is free software; you can redistribute it and/or modify 8: ;; it under the terms of the GNU General Public License as published by 9: ;; the Free Software Foundation; either version 2, or (at your option) 10: ;; any later version. 11: 12: ;; GNU CC is distributed in the hope that it will be useful, 13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15: ;; GNU General Public License for more details. 16: 17: ;; You should have received a copy of the GNU General Public License 18: ;; along with GNU CC; see the file COPYING. If not, write to 19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 20: 21: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 22: 23: ;; The insns in this file are presented in the same order as the AMD 29000 24: ;; User's Manual (i.e., alphabetical by machine op-code). 25: ;; 1.1.1.2 root 26: ;; DEFINE_EXPAND's are located near the first occurrence of the major insn 1.1 root 27: ;; that they generate. 28: 29: ;; The only attribute we have is the type. We only care about calls, branches, 30: ;; loads, stores, floating-point operations, and multi-word insns. 31: ;; Everything else is miscellaneous. 32: 33: (define_attr "type" 1.1.1.4 ! root 34: "call,branch,load,store,fadd,fmul,fam,fdiv,fsqrt,dmul,dam,ddiv,dsqrt,multi,misc" 1.1 root 35: (const_string "misc")) 36: 37: ;; ASM insns cannot go into a delay slot, so call them "multi". 38: (define_asm_attributes [(set_attr "type" "multi")]) 39: 40: (define_attr "in_delay_slot" "yes,no" 41: (if_then_else (eq_attr "type" "call,branch,multi") (const_string "no") 42: (const_string "yes"))) 43: 44: ;; Branch and call insns require a single delay slot. Annulling is not 45: ;; supported. 46: (define_delay (eq_attr "type" "call,branch") 47: [(eq_attr "in_delay_slot" "yes") (nil) (nil)]) 48: 49: ;; Define the function unit usages. We first define memory as a unit. 1.1.1.4 ! root 50: (define_function_unit "memory" 1 0 (eq_attr "type" "load") 6 5 ! 51: [(eq_attr "type" "load")]) ! 52: (define_function_unit "memory" 1 0 (eq_attr "type" "load") 6 6 ! 53: [(eq_attr "type" "store")]) ! 54: (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0) 1.1 root 55: 56: ;; Now define the function units for the floating-point support. Most 57: ;; units are pipelined and can accept an input every cycle. 58: ;; 59: ;; Note that we have an inaccuracy here. If a fmac insn is issued, followed 60: ;; 2 cycles later by a fadd, there will be a conflict for the floating 61: ;; adder that we can't represent. Also, all insns will conflict for the 62: ;; floating-point rounder. It isn't clear how to represent this. 63: 64: (define_function_unit "multiplier" 1 0 (eq_attr "type" "fmul") 3 0) 1.1.1.4 ! root 65: (define_function_unit "multiplier" 1 0 (eq_attr "type" "dmul") 6 4) ! 66: (define_function_unit "multiplier" 1 0 (eq_attr "type" "fam") 6 0) ! 67: (define_function_unit "multiplier" 1 0 (eq_attr "type" "dam") 9 4) 1.1 root 68: 69: (define_function_unit "adder" 1 0 (eq_attr "type" "fadd,fam,dam") 3 0) 70: 1.1.1.4 ! root 71: (define_function_unit "divider" 1 0 (eq_attr "type" "fdiv") 11 10) ! 72: (define_function_unit "divider" 1 0 (eq_attr "type" "fsqrt") 28 27) ! 73: (define_function_unit "divider" 1 0 (eq_attr "type" "ddiv") 18 17) ! 74: (define_function_unit "divider" 1 0 (eq_attr "type" "dsqrt") 57 56) 1.1 root 75: 76: ;; ADD 77: (define_insn "addsi3" 1.1.1.3 root 78: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 79: (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 1.1 root 80: (match_operand:SI 2 "add_operand" "rI,N")))] 81: "" 82: "@ 83: add %0,%1,%2 84: sub %0,%1,%n2") 85: 86: (define_insn "adddi3" 1.1.1.3 root 87: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 88: (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r") 89: (match_operand:DI 2 "gpc_reg_operand" "r")))] 1.1 root 90: "" 91: "add %L0,%L1,%L2\;addc %0,%1,%2" 92: [(set_attr "type" "multi")]) 93: 94: ;; AND/ANDN 95: (define_insn "andsi3" 1.1.1.3 root 96: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 97: (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 1.1 root 98: (match_operand:SI 2 "and_operand" "rI,K")))] 99: "" 100: "@ 101: and %0,%1,%2 102: andn %0,%1,%C2") 103: 104: (define_insn "" 1.1.1.3 root 105: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1 root 106: (and:SI (not:SI (match_operand:SI 1 "srcb_operand" "rI")) 1.1.1.3 root 107: (match_operand:SI 2 "gpc_reg_operand" "r")))] 1.1 root 108: "" 109: "andn %0,%2,%1") 110: 111: 112: ;; CALLI 113: ;; 114: ;; Start with a subroutine to write out CLOBBERs starting at lr2 up to, 115: ;; but not including, the next parameter register. If operand[0] is null, 116: ;; it means that all the argument registers have been used. 117: (define_expand "clobbers_to" 118: [(clobber (match_operand:SI 0 "" ""))] 119: "" 120: " 121: { 122: int i; 123: int high_regno; 124: 125: if (operands[0] == 0) 126: high_regno = R_LR (18); 127: else if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) < R_LR (0) 128: || REGNO (operands[0]) > R_LR (18)) 129: abort (); 130: else 131: high_regno = REGNO (operands[0]); 132: 133: for (i = R_LR (2); i < high_regno; i++) 134: emit_insn (gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, i))); 135: 136: DONE; 137: }") 138: 1.1.1.4 ! root 139: ;; We indicate that LR0 is clobbered in the CALL_INSN itself. Otherwise, ! 140: ;; reorg will think it is just clobbered by the called function. ! 141: 1.1 root 142: (define_expand "call" 143: [(parallel [(call (match_operand:SI 0 "" "") 144: (match_operand 1 "" "")) 1.1.1.4 ! root 145: (clobber (scratch:SI))]) 1.1 root 146: (match_operand 2 "" "")] 147: "" 148: " 149: { 150: if (GET_CODE (operands[0]) != MEM) 151: abort (); 152: 1.1.1.4 ! root 153: /* We tell here whether this is a recursive call, since this insn may ! 154: later be inlined into another function. */ 1.1 root 155: if (! TARGET_SMALL_MEMORY 156: && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) 1.1.1.4 ! root 157: operands[0] = gen_rtx (MEM, SImode, 1.1 root 158: force_reg (Pmode, XEXP (operands[0], 0))); 159: 160: operands[2] = gen_clobbers_to (operands[2]); 161: }") 162: 163: (define_expand "call_value" 1.1.1.3 root 164: [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 1.1 root 165: (call (match_operand:SI 1 "" "") 166: (match_operand 2 "" ""))) 1.1.1.4 ! root 167: (clobber (scratch:SI))]) 1.1 root 168: (match_operand 3 "" "")] 169: "" 170: " 171: { 172: if (GET_CODE (operands[1]) != MEM) 173: abort (); 174: 1.1.1.4 ! root 175: /* We tell here whether this is a recursive call, since this insn may ! 176: later be inlined into another function. */ 1.1 root 177: if (! TARGET_SMALL_MEMORY 178: && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) 1.1.1.4 ! root 179: operands[1] = gen_rtx (MEM, SImode, 1.1 root 180: force_reg (Pmode, XEXP (operands[1], 0))); 181: 182: operands[3] = gen_clobbers_to (operands[3]); 183: }") 184: 185: (define_insn "" 1.1.1.4 ! root 186: [(call (match_operand:SI 0 "memory_operand" "m") ! 187: (match_operand 1 "" "")) ! 188: (clobber (match_scratch:SI 2 "=&l"))] ! 189: "GET_CODE (XEXP (operands[0], 0)) != CONST_INT" ! 190: "calli lr0,%0%#" 1.1 root 191: [(set_attr "type" "call")]) 192: 193: (define_insn "" 1.1.1.4 ! root 194: [(call (mem:SI (match_operand:SI 0 "call_operand" "i")) 1.1 root 195: (match_operand:SI 1 "general_operand" "g")) 1.1.1.4 ! root 196: (clobber (match_scratch:SI 2 "=&l"))] ! 197: "" 1.1 root 198: "call lr0,%F0" 199: [(set_attr "type" "call")]) 200: 201: (define_insn "" 1.1.1.3 root 202: [(set (match_operand 0 "gpc_reg_operand" "=r") 1.1.1.4 ! root 203: (call (match_operand:SI 1 "memory_operand" "m") ! 204: (match_operand 2 "" ""))) ! 205: (clobber (match_scratch:SI 3 "=&l"))] ! 206: "GET_CODE (XEXP (operands[1], 0)) != CONST_INT" ! 207: "calli lr0,%1%#" ! 208: [(set_attr "type" "call")]) ! 209: ! 210: (define_insn "" ! 211: [(set (match_operand 0 "gpc_reg_operand" "=r") ! 212: (call (mem:SI (match_operand:SI 1 "call_operand" "i")) 1.1 root 213: (match_operand:SI 2 "general_operand" "g"))) 1.1.1.4 ! root 214: (clobber (match_scratch:SI 3 "=&l"))] ! 215: "" 1.1 root 216: "call lr0,%F1" 217: [(set_attr "type" "call")]) 218: 219: (define_expand "probe" 220: [(call (mem:SI (symbol_ref:SI "_msp_check")) 221: (const_int 1))] 222: "TARGET_STACK_CHECK" 223: "") 224: 225: ;; This is used for internal routine calls via TPC. Currently used only 226: ;; in probe, above. 227: (define_insn "" 228: [(call (mem:SI (match_operand:SI 0 "immediate_operand" "s")) 229: (const_int 1))] 230: "" 231: "call %*,%0" 232: [(set_attr "type" "call")]) 233: 234: ;; CONST, CONSTH, CONSTN 235: ;; 236: ;; Many of these are generated from move insns. 237: (define_insn "" 1.1.1.3 root 238: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1 root 239: (and:SI (match_operand:SI 1 "immediate_operand" "i") 240: (const_int 65535)))] 241: "" 242: "const %0,%1") 243: 244: (define_insn "" 1.1.1.3 root 245: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 1.1 root 246: (const_int 16) 247: (match_operand:SI 1 "const_0_operand" "")) 248: (ashiftrt:SI (match_operand:SI 2 "immediate_operand" "i") 249: (const_int 16)))] 250: "" 251: "consth %0,%2") 252: 253: (define_insn "" 1.1.1.3 root 254: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 1.1 root 255: (const_int 16) 256: (match_operand:SI 1 "const_0_operand" "")) 257: (match_operand:SI 2 "cint_16_operand" "J"))] 258: "" 1.1.1.4 ! root 259: "consth %0,%m2") 1.1 root 260: 261: (define_insn "" 1.1.1.3 root 262: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1.1.4 ! root 263: (ior:SI (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "0")) 1.1 root 264: (match_operand:SI 2 "const_int_operand" "n")))] 1.1.1.4 ! root 265: "(INTVAL (operands[2]) & 0xffff) == 0" 1.1 root 266: "consth %0,%2") 267: 268: (define_insn "" 1.1.1.3 root 269: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1.1.4 ! root 270: (ior:SI (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "0")) 1.1 root 271: (and:SI (match_operand:SI 2 "immediate_operand" "i") 272: (const_int -65536))))] 273: "" 274: "consth %0,%2") 275: 276: ;; CONVERT 277: (define_insn "fix_truncsfsi2" 1.1.1.3 root 278: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1 root 279: (fix:SI (match_operand:SF 1 "register_operand" "r")))] 280: "" 281: "convert %0,%1,0,3,0,1") 282: 283: (define_insn "fix_truncdfsi2" 1.1.1.3 root 284: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1 root 285: (fix:SI (match_operand:DF 1 "register_operand" "r")))] 286: "" 287: "convert %0,%1,0,3,0,2") 288: 289: (define_insn "fixuns_truncsfsi2" 1.1.1.3 root 290: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1 root 291: (unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))] 292: "" 293: "convert %0,%1,1,3,0,1") 294: 295: (define_insn "fixuns_truncdfsi2" 1.1.1.3 root 296: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1 root 297: (unsigned_fix:SI (match_operand:DF 1 "register_operand" "r")))] 298: "" 299: "convert %0,%1,1,3,0,2") 300: 301: (define_insn "truncdfsf2" 302: [(set (match_operand:SF 0 "register_operand" "=r") 303: (float_truncate:SF (match_operand:DF 1 "register_operand" "r")))] 304: "" 305: "convert %0,%1,0,4,1,2") 306: 307: (define_insn "extendsfdf2" 308: [(set (match_operand:DF 0 "register_operand" "=r") 309: (float_extend:DF (match_operand:SF 1 "register_operand" "r")))] 310: "" 311: "convert %0,%1,0,4,2,1") 312: 313: (define_insn "floatsisf2" 314: [(set (match_operand:SF 0 "register_operand" "=r") 1.1.1.3 root 315: (float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))] 1.1 root 316: "" 317: "convert %0,%1,0,4,1,0") 318: 319: (define_insn "floatsidf2" 320: [(set (match_operand:DF 0 "register_operand" "=r") 1.1.1.3 root 321: (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))] 1.1 root 322: "" 323: "convert %0,%1,0,4,2,0") 324: 325: (define_insn "floatunssisf2" 326: [(set (match_operand:SF 0 "register_operand" "=r") 1.1.1.3 root 327: (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))] 1.1 root 328: "" 329: "convert %0,%1,1,4,1,0") 330: 331: (define_insn "floatunssidf2" 332: [(set (match_operand:DF 0 "register_operand" "=r") 1.1.1.3 root 333: (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))] 1.1 root 334: "" 335: "convert %0,%1,1,4,2,0") 336: 337: ;; CPxxx, DEQ, DGT, DGE, FEQ, FGT, FGE 338: (define_insn "" 1.1.1.3 root 339: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1 root 340: (match_operator 3 "comparison_operator" 1.1.1.3 root 341: [(match_operand:SI 1 "gpc_reg_operand" "r") 1.1 root 342: (match_operand:SI 2 "srcb_operand" "rI")]))] 343: "" 344: "cp%J3 %0,%1,%2") 345: 346: (define_insn "" 1.1.1.3 root 347: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1 root 348: (match_operator 3 "fp_comparison_operator" 349: [(match_operand:SF 1 "register_operand" "r") 350: (match_operand:SF 2 "register_operand" "r")]))] 351: "" 352: "f%J3 %0,%1,%2" 353: [(set_attr "type" "fadd")]) 354: 355: (define_insn "" 1.1.1.3 root 356: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1 root 357: (match_operator 3 "fp_comparison_operator" 358: [(match_operand:DF 1 "register_operand" "r") 359: (match_operand:DF 2 "register_operand" "r")]))] 360: "" 361: "d%J3 %0,%1,%2" 362: [(set_attr "type" "fadd")]) 363: 364: ;; DADD 365: (define_expand "adddf3" 366: [(set (match_operand:DF 0 "register_operand" "") 367: (plus:DF (match_operand:DF 1 "register_operand" "") 368: (match_operand:DF 2 "register_operand" "")))] 369: "" 370: "") 371: 372: (define_insn "" 373: [(set (match_operand:DF 0 "register_operand" "=r") 374: (plus:DF (match_operand:DF 1 "register_operand" "%r") 375: (match_operand:DF 2 "register_operand" "r")))] 376: "! TARGET_29050 " 377: "dadd %0,%1,%2" 378: [(set_attr "type" "fadd")]) 379: 380: (define_insn "" 381: [(set (match_operand:DF 0 "register_operand" "=r,a") 382: (plus:DF (match_operand:DF 1 "register_operand" "%r,r") 383: (match_operand:DF 2 "register_operand" "r,0")))] 384: "TARGET_29050" 385: "@ 386: dadd %0,%1,%2 1.1.1.4 ! root 387: dmac 8,%0,%1,%1" 1.1 root 388: [(set_attr "type" "fadd,dam")]) 389: 390: ;; DDIV 391: (define_insn "divdf3" 392: [(set (match_operand:DF 0 "register_operand" "=r") 393: (div:DF (match_operand:DF 1 "register_operand" "=r") 394: (match_operand:DF 2 "register_operand" "r")))] 395: "" 396: "ddiv %0,%1,%2" 397: [(set_attr "type" "ddiv")]) 398: 399: ;; DIVIDE 400: ;; 401: ;; We must set Q to the sign extension of the dividend first. For MOD, we 402: ;; must get the remainder from Q. 403: ;; 404: ;; For divmod: operand 1 is divided by operand 2; quotient goes to operand 405: ;; 0 and remainder to operand 3. 406: (define_expand "divmodsi4" 407: [(set (match_dup 4) 1.1.1.3 root 408: (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 1.1 root 409: (const_int 31))) 1.1.1.3 root 410: (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 1.1 root 411: (div:SI (match_dup 1) 1.1.1.3 root 412: (match_operand:SI 2 "gpc_reg_operand" ""))) 413: (set (match_operand:SI 3 "gpc_reg_operand" "") 1.1 root 414: (mod:SI (match_dup 1) 415: (match_dup 2))) 416: (use (match_dup 4))])] 417: "" 418: " 419: { 420: operands[4] = gen_reg_rtx (SImode); 421: }") 422: 423: (define_insn "" 1.1.1.3 root 424: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 425: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 426: (match_operand:SI 2 "gpc_reg_operand" "r"))) 1.1 root 427: (set (match_operand:SI 3 "register_operand" "=q") 428: (mod:SI (match_dup 1) 429: (match_dup 2))) 430: (use (match_operand:SI 4 "register_operand" "3"))] 431: "" 432: "divide %0,%1,%2") 433: 434: ;; DIVIDU 435: ;; 436: ;; Similar to DIVIDE. 437: (define_expand "udivmodsi4" 1.1.1.3 root 438: [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 439: (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") 440: (match_operand:SI 2 "gpc_reg_operand" ""))) 441: (set (match_operand:SI 3 "gpc_reg_operand" "") 1.1 root 442: (umod:SI (match_dup 1) 443: (match_dup 2))) 444: (use (const_int 0))])] 445: "" 446: "") 447: 448: (define_insn "" 1.1.1.3 root 449: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 450: (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") 451: (match_operand:SI 2 "gpc_reg_operand" "r"))) 1.1 root 452: (set (match_operand:SI 3 "register_operand" "=q") 453: (umod:SI (match_dup 1) 454: (match_dup 2))) 455: (use (match_operand:SI 4 "const_int_operand" "3"))] 456: "" 457: "dividu %0,%1,%2") 458: 459: ;; DMAC/DMSM 460: (define_insn "" 461: [(set (match_operand:DF 0 "register_operand" "=a,*r") 462: (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%r,A") 463: (match_operand:DF 2 "register_operand" "r,r")) 464: (match_operand:DF 3 "register_operand" "0,*r")))] 465: "TARGET_29050" 466: "@ 467: dmac 0,%0,%1,%2 468: dmsm %0,%2,%3" 469: [(set_attr "type" "dam")]) 470: 471: (define_insn "" 472: [(set (match_operand:DF 0 "register_operand" "=a") 473: (plus:DF (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "r")) 474: (match_operand:DF 2 "register_operand" "r")) 475: (match_operand:DF 3 "register_operand" "0")))] 476: "TARGET_29050" 477: "dmac 1,%0,%2,%1" 478: [(set_attr "type" "dam")]) 479: 480: (define_insn "" 481: [(set (match_operand:DF 0 "register_operand" "=a") 482: (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "%r") 483: (match_operand:DF 2 "register_operand" "r")) 484: (match_operand:DF 3 "register_operand" "0")))] 485: "TARGET_29050" 486: "dmac 2,%0,%1,%2" 487: [(set_attr "type" "dam")]) 488: 489: (define_insn "" 490: [(set (match_operand:DF 0 "register_operand" "=a") 491: (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "r") 492: (neg:DF (match_operand:DF 2 "register_operand" "r"))) 493: (match_operand:DF 3 "register_operand" "0")))] 494: "TARGET_29050" 495: "dmac 3,%0,%1,%2" 496: [(set_attr "type" "dam")]) 497: 498: (define_insn "" 499: [(set (match_operand:DF 0 "register_operand" "=a") 500: (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "r")) 501: (match_operand:DF 2 "register_operand" "r")))] 502: "TARGET_29050" 503: "dmac 5,%0,%2,%1" 504: [(set_attr "type" "dam")]) 505: 506: (define_insn "" 507: [(set (match_operand:DF 0 "register_operand" "=a") 508: (minus:DF (neg:DF (match_operand:DF 1 "register_operand" "r")) 509: (match_operand:DF 2 "register_operand" "0")))] 510: "TARGET_29050" 1.1.1.4 ! root 511: "dmac 11,%0,%1,%1" 1.1 root 512: [(set_attr "type" "dam")]) 513: 514: (define_insn "" 515: [(set (match_operand:DF 0 "register_operand" "=a") 516: (neg:DF (plus:DF (match_operand:DF 1 "register_operand" "%r") 517: (match_operand:DF 2 "register_operand" "0"))))] 518: "TARGET_29050" 1.1.1.4 ! root 519: "dmac 11,%0,%1,%1" 1.1 root 520: [(set_attr "type" "dam")]) 521: 522: (define_insn "" 523: [(set (match_operand:DF 0 "register_operand" "=r,r,a") 524: (neg:DF (match_operand:DF 1 "register_operand" "0,r,r"))) 525: (clobber (match_scratch:SI 2 "=&r,&r,X"))] 526: "TARGET_29050" 527: "@ 528: cpeq %2,gr1,gr1\;xor %0,%1,%2 529: cpeq %2,gr1,gr1\;xor %0,%1,%2\;sll %L0,%L1,0 1.1.1.4 ! root 530: dmac 13,%0,%1,%1" 1.1 root 531: [(set_attr "type" "multi,multi,dam")]) 532: 533: ;; DMUL 534: (define_expand "muldf3" 535: [(set (match_operand:DF 0 "register_operand" "") 536: (mult:DF (match_operand:DF 1 "register_operand" "") 537: (match_operand:DF 2 "register_operand" "")))] 538: "" 539: "") 540: 541: (define_insn "" 542: [(set (match_operand:DF 0 "register_operand" "=r") 543: (mult:DF (match_operand:DF 1 "register_operand" "%r") 544: (match_operand:DF 2 "register_operand" "r")))] 545: "! TARGET_29050" 546: "dmul %0,%1,%2" 547: [(set_attr "type" "dmul")]) 548: 549: (define_insn "" 550: [(set (match_operand:DF 0 "register_operand" "=r,a") 551: (mult:DF (match_operand:DF 1 "register_operand" "%r,r") 552: (match_operand:DF 2 "register_operand" "r,r")))] 553: "TARGET_29050" 554: "@ 555: dmul %0,%1,%2 556: dmac 4,%0,%1,%2" 557: [(set_attr "type" "dmul,dam")]) 558: 559: ;; DSUB 560: (define_expand "subdf3" 561: [(set (match_operand:DF 0 "register_operand" "=r") 562: (minus:DF (match_operand:DF 1 "register_operand" "r") 563: (match_operand:DF 2 "register_operand" "r")))] 564: "" 565: "") 566: 567: (define_insn "" 568: [(set (match_operand:DF 0 "register_operand" "=r") 569: (minus:DF (match_operand:DF 1 "register_operand" "r") 570: (match_operand:DF 2 "register_operand" "r")))] 571: "! TARGET_29050" 572: "dsub %0,%1,%2" 573: [(set_attr "type" "fadd")]) 574: 575: (define_insn "" 576: [(set (match_operand:DF 0 "register_operand" "=r,a,a") 577: (minus:DF (match_operand:DF 1 "register_operand" "r,0,r") 578: (match_operand:DF 2 "register_operand" "r,r,0")))] 579: "TARGET_29050" 580: "@ 581: dsub %0,%1,%2 1.1.1.4 ! root 582: dmac 9,%0,%2,%2 ! 583: dmac 10,%0,%1,%1" 1.1 root 584: [(set_attr "type" "fadd,dam,dam")]) 585: 586: ;; EXBYTE 587: (define_insn "" 1.1.1.3 root 588: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1 root 589: (ior:SI (and:SI (match_operand:SI 1 "srcb_operand" "rI") 590: (const_int -256)) 1.1.1.3 root 591: (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") 1.1 root 592: (const_int 8) 1.1.1.4 ! root 593: (ashift:PSI ! 594: (match_operand:PSI 3 "register_operand" "b") ! 595: (const_int 3)))))] 1.1 root 596: "" 597: "exbyte %0,%2,%1") 598: 599: (define_insn "" 1.1.1.3 root 600: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 601: (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1.1 root 602: (const_int 8) 1.1.1.4 ! root 603: (ashift:PSI ! 604: (match_operand:PSI 2 "register_operand" "b") ! 605: (const_int 3))))] 1.1 root 606: "" 607: "exbyte %0,%1,0") 608: 609: (define_insn "" 1.1.1.3 root 610: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 1.1 root 611: (const_int 8) 1.1.1.4 ! root 612: (match_operand:PSI 1 "const_24_operand" "")) 1.1.1.3 root 613: (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") 1.1 root 614: (const_int 8) 1.1.1.4 ! root 615: (ashift:PSI ! 616: (match_operand:PSI 3 "register_operand" "b") ! 617: (const_int 3))))] 1.1 root 618: "" 619: "exbyte %0,%2,%0") 620: 621: (define_expand "extzv" 1.1.1.3 root 622: [(set (match_operand:SI 0 "gpc_reg_operand" "") 623: (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") 1.1 root 624: (match_operand:SI 2 "general_operand" "") 625: (match_operand:SI 3 "general_operand" "")))] 626: "" 627: " 628: { 629: int size, pos; 630: 631: if (GET_CODE (operands[2]) != CONST_INT 632: || GET_CODE (operands[3]) != CONST_INT) 633: FAIL; 634: 635: size = INTVAL (operands[2]); 636: pos = INTVAL (operands[3]); 637: 1.1.1.4 ! root 638: /* Can't do this unless a byte extraction. If extracting the high ! 639: or low byte, don't do this because a shift or AND is shorter. ! 640: Don't do 16-bit extracts, since the only two are the high and low ! 641: ends, and it is faster to do them with CONSTH and SRL. */ 1.1 root 642: 1.1.1.4 ! root 643: if (size != 8 || (pos != 8 && pos != 16)) 1.1 root 644: FAIL; 645: 1.1.1.4 ! root 646: operands[3] = gen_rtx (ASHIFT, PSImode, ! 647: force_reg (PSImode, GEN_INT (pos / 8)), ! 648: GEN_INT (3)); 1.1 root 649: 650: }") 651: 652: ;; EXHW 653: (define_insn "" 1.1.1.3 root 654: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1 root 655: (ior:SI (and:SI (match_operand:SI 1 "srcb_operand" "rI") 656: (const_int -65536)) 1.1.1.3 root 657: (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") 1.1 root 658: (const_int 16) 1.1.1.4 ! root 659: (ashift:PSI ! 660: (match_operand:PSI 3 "register_operand" "b") ! 661: (const_int 3)))))] 1.1 root 662: "" 663: "exhw %0,%2,%1") 664: 665: (define_insn "" 1.1.1.3 root 666: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 667: (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1.1 root 668: (const_int 16) 1.1.1.4 ! root 669: (ashift:PSI ! 670: (match_operand:PSI 2 "register_operand" "b") ! 671: (const_int 3))))] 1.1 root 672: "" 673: "exhw %0,%1,0") 674: 675: (define_insn "" 1.1.1.3 root 676: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 1.1 root 677: (const_int 16) 1.1.1.4 ! root 678: (match_operand:PSI 1 "const_16_operand" "")) 1.1.1.3 root 679: (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") 1.1 root 680: (const_int 16) 1.1.1.4 ! root 681: (ashift:PSI ! 682: (match_operand:PSI 3 "register_operand" "b") ! 683: (const_int 3))))] 1.1 root 684: "" 685: "exhw %0,%2,%0") 686: 687: ;; EXHWS 1.1.1.4 ! root 688: ;; ! 689: ;; This is probably unused. The high-order 16-bits are obtained with an SRA ! 690: ;; insn. The low-order 16 bits are a sign-extend, which is a pair of ! 691: ;; shifts. Setting BP followed by the insn is equivalent, so we don't ! 692: ;; bother going to any trouble to generate this insn. ! 693: 1.1 root 694: (define_insn "" 1.1.1.3 root 695: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 696: (sign_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1.1 root 697: (const_int 16) 1.1.1.4 ! root 698: (ashift:PSI ! 699: (match_operand:PSI 2 "register_operand" "b") ! 700: (const_int 3))))] 1.1 root 701: "" 702: "exhws %0,%1") 703: 704: ;; EXTRACT 705: (define_insn "" 1.1.1.3 root 706: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 707: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1.1.1.4 ! root 708: (match_operand:PSI 2 "register_operand" "f")))] 1.1 root 709: "" 710: "extract %0,%1,%1") 711: 712: (define_expand "rotlsi3" 1.1.1.4 ! root 713: [(set (match_dup 3) ! 714: (match_operand:SI 2 "gpc_reg_or_immediate_operand" "")) 1.1.1.3 root 715: (set (match_operand:SI 0 "gpc_reg_operand" "") 716: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 1.1.1.4 ! root 717: (match_dup 3)))] 1.1 root 718: "" 719: " 1.1.1.4 ! root 720: { operands[2] = gen_lowpart (PSImode, operands[2]); ! 721: operands[3] = gen_reg_rtx (PSImode); ! 722: }") ! 723: ! 724: ;; It would be nice to be able to have a define_split corresponding to the ! 725: ;; above, but there is no way to tell combine we need a PSImode temporary. ! 726: ;; If we put a (clobber (scratch:PSI)) there, combine would merge the above ! 727: ;; two insns. This is bad because it then thinks only one insn is needed. 1.1 root 728: 729: ;; FADD 730: (define_expand "addsf3" 731: [(set (match_operand:SF 0 "register_operand" "") 732: (plus:SF (match_operand:SF 1 "register_operand" "") 733: (match_operand:SF 2 "register_operand" "")))] 734: "" 735: "") 736: 737: (define_insn "" 738: [(set (match_operand:SF 0 "register_operand" "=r") 739: (plus:SF (match_operand:SF 1 "register_operand" "%r") 740: (match_operand:SF 2 "register_operand" "r")))] 741: "! TARGET_29050" 742: "fadd %0,%1,%2" 743: [(set_attr "type" "fadd")]) 744: 745: (define_insn "" 746: [(set (match_operand:SF 0 "register_operand" "=r,a") 747: (plus:SF (match_operand:SF 1 "register_operand" "%r,r") 748: (match_operand:SF 2 "register_operand" "r,0")))] 749: "TARGET_29050" 750: "@ 751: fadd %0,%1,%2 1.1.1.4 ! root 752: fmac 8,%0,%1,%1" 1.1 root 753: [(set_attr "type" "fadd,fam")]) 754: 755: ;; FDIV 756: (define_insn "divsf3" 757: [(set (match_operand:SF 0 "register_operand" "=r") 1.1.1.4 ! root 758: (div:SF (match_operand:SF 1 "register_operand" "=r") 1.1 root 759: (match_operand:SF 2 "register_operand" "r")))] 760: "" 761: "fdiv %0,%1,%2" 762: [(set_attr "type" "fdiv")]) 763: 764: ;; FDMUL 765: (define_insn "" 766: [(set (match_operand:DF 0 "register_operand" "=r") 767: (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "%r")) 768: (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))] 769: "" 770: "fdmul %0,%1,%2") 771: 772: ;; FMAC/FMSM 773: (define_insn "" 774: [(set (match_operand:SF 0 "register_operand" "=a,*r") 775: (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%r,A") 776: (match_operand:SF 2 "register_operand" "r,r")) 777: (match_operand:SF 3 "register_operand" "0,*r")))] 778: "TARGET_29050" 779: "@ 780: fmac 0,%0,%1,%2 781: fmsm %0,%2,%3" 782: [(set_attr "type" "fam")]) 783: 784: (define_insn "" 785: [(set (match_operand:SF 0 "register_operand" "=a") 786: (plus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r")) 787: (match_operand:SF 2 "register_operand" "r")) 788: (match_operand:SF 3 "register_operand" "0")))] 789: "TARGET_29050" 790: "fmac 1,%0,%2,%1" 791: [(set_attr "type" "fam")]) 792: 793: (define_insn "" 794: [(set (match_operand:SF 0 "register_operand" "=a") 795: (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "%r") 796: (match_operand:SF 2 "register_operand" "r")) 797: (match_operand:SF 3 "register_operand" "0")))] 798: "TARGET_29050" 799: "fmac 2,%0,%1,%2" 800: [(set_attr "type" "fam")]) 801: 802: (define_insn "" 803: [(set (match_operand:SF 0 "register_operand" "=a") 804: (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r")) 805: (match_operand:SF 2 "register_operand" "r")) 806: (match_operand:SF 3 "register_operand" "0")))] 807: "TARGET_29050" 808: "fmac 3,%0,%2,%1" 809: [(set_attr "type" "fam")]) 810: 811: (define_insn "" 812: [(set (match_operand:SF 0 "register_operand" "=a") 813: (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r")) 814: (match_operand:SF 2 "register_operand" "r")))] 815: "TARGET_29050" 816: "fmac 5,%0,%2,%1" 817: [(set_attr "type" "fam")]) 818: 819: (define_insn "" 820: [(set (match_operand:SF 0 "register_operand" "=a") 821: (minus:SF (neg:SF (match_operand:SF 1 "register_operand" "%r")) 822: (match_operand:SF 2 "register_operand" "0")))] 823: "TARGET_29050" 1.1.1.4 ! root 824: "fmac 11,%0,%1,%1" 1.1 root 825: [(set_attr "type" "fam")]) 826: 827: (define_insn "" 828: [(set (match_operand:SF 0 "register_operand" "=a") 829: (neg:SF (plus:SF (match_operand:SF 1 "register_operand" "%r") 830: (match_operand:SF 2 "register_operand" "0"))))] 831: "TARGET_29050" 1.1.1.4 ! root 832: "fmac 11,%0,%1,%1" 1.1 root 833: [(set_attr "type" "fam")]) 834: 835: (define_insn "" 836: [(set (match_operand:SF 0 "register_operand" "=r,a") 837: (neg:SF (match_operand:SF 1 "register_operand" "r,r"))) 838: (clobber (match_scratch:SI 2 "=&r,X"))] 839: "TARGET_29050" 840: "@ 841: cpeq %2,gr1,gr1\;xor %0,%1,%2 1.1.1.4 ! root 842: fmac 13,%0,%1,%1" 1.1 root 843: [(set_attr "type" "multi,fam")]) 844: 845: ;; FMUL 846: (define_expand "mulsf3" 847: [(set (match_operand:SF 0 "register_operand" "") 848: (mult:SF (match_operand:SF 1 "register_operand" "") 849: (match_operand:SF 2 "register_operand" "")))] 850: "" 851: "") 852: 853: (define_insn "" 854: [(set (match_operand:SF 0 "register_operand" "=r") 855: (mult:SF (match_operand:SF 1 "register_operand" "%r") 856: (match_operand:SF 2 "register_operand" "r")))] 857: "! TARGET_29050" 858: "fmul %0,%1,%2" 859: [(set_attr "type" "fmul")]) 860: 861: (define_insn "" 862: [(set (match_operand:SF 0 "register_operand" "=r,a") 863: (mult:SF (match_operand:SF 1 "register_operand" "%r,r") 864: (match_operand:SF 2 "register_operand" "r,r")))] 865: "TARGET_29050" 866: "@ 867: fmul %0,%1,%2 868: fmac 4,%0,%1,%2" 869: [(set_attr "type" "fmul,fam")]) 870: 871: ;; FSUB 872: (define_expand "subsf3" 873: [(set (match_operand:SF 0 "register_operand" "") 874: (minus:SF (match_operand:SF 1 "register_operand" "") 875: (match_operand:SF 2 "register_operand" "")))] 876: "" 877: "") 878: 879: (define_insn "" 880: [(set (match_operand:SF 0 "register_operand" "=r") 881: (minus:SF (match_operand:SF 1 "register_operand" "r") 882: (match_operand:SF 2 "register_operand" "r")))] 883: "! TARGET_29050" 884: "fsub %0,%1,%2" 885: [(set_attr "type" "fadd")]) 886: 887: (define_insn "" 888: [(set (match_operand:SF 0 "register_operand" "=r,a,a") 889: (minus:SF (match_operand:SF 1 "register_operand" "r,0,r") 890: (match_operand:SF 2 "register_operand" "r,r,0")))] 891: "TARGET_29050" 892: "@ 893: fsub %0,%1,%2 1.1.1.4 ! root 894: fmac 9,%0,%2,%2 ! 895: fmac 10,%0,%1,%1" 1.1 root 896: [(set_attr "type" "fadd,fam,fam")]) 897: 898: ;; INBYTE 899: (define_insn "" 1.1.1.3 root 900: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 1.1 root 901: (const_int 8) 1.1.1.4 ! root 902: (ashift:PSI ! 903: (match_operand:PSI 2 "register_operand" "b") ! 904: (const_int 3))) 1.1 root 905: (match_operand:SI 1 "srcb_operand" "rI"))] 906: "" 907: "inbyte %0,%0,%1") 908: 909: (define_insn "" 1.1.1.3 root 910: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1.1.4 ! root 911: (ior:SI (and:SI ! 912: (not:SI ! 913: (ashift:SI (const_int 255) ! 914: (ashift:PSI ! 915: (match_operand:PSI 3 "register_operand" "b") ! 916: (const_int 3)))) ! 917: (match_operand:SI 1 "gpc_reg_operand" "r")) ! 918: (ashift:SI (zero_extend:SI ! 919: (match_operand:QI 2 "srcb_operand" "rI")) ! 920: (ashift:PSI (match_dup 3) (const_int 3)))))] 1.1 root 921: "" 922: "inbyte %0,%1,%2") 923: 924: ;; INHW 925: (define_insn "" 1.1.1.3 root 926: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 1.1 root 927: (const_int 16) 1.1.1.4 ! root 928: (ashift:PSI ! 929: (match_operand:PSI 2 "register_operand" "b") ! 930: (const_int 3))) 1.1 root 931: (match_operand:SI 1 "srcb_operand" "rI"))] 932: "" 933: "inhw %0,%0,%1") 934: 935: (define_insn "" 1.1.1.3 root 936: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1.1.4 ! root 937: (ior:SI (and:SI ! 938: (not:SI ! 939: (ashift:SI (const_int 65535) ! 940: (ashift:PSI ! 941: (match_operand:PSI 3 "register_operand" "b") ! 942: (const_int 3)))) ! 943: (match_operand:SI 1 "gpc_reg_operand" "r")) ! 944: (ashift:SI (zero_extend:SI ! 945: (match_operand:HI 2 "srcb_operand" "rI")) ! 946: (ashift:PSI (match_dup 3) (const_int 3)))))] 1.1 root 947: "" 948: "inhw %0,%1,%2") 949: 950: (define_expand "insv" 1.1.1.3 root 951: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "") 1.1 root 952: (match_operand:SI 1 "general_operand" "") 953: (match_operand:SI 2 "general_operand" "")) 954: (match_operand:SI 3 "srcb_operand" ""))] 955: "" 956: " 957: { 958: int size, pos; 959: 960: if (GET_CODE (operands[1]) != CONST_INT 961: || GET_CODE (operands[2]) != CONST_INT) 962: FAIL; 963: 964: size = INTVAL (operands[1]); 965: pos = INTVAL (operands[2]); 966: if ((size != 8 && size != 16) || pos % size != 0) 967: FAIL; 968: 1.1.1.4 ! root 969: operands[2] = gen_rtx (ASHIFT, PSImode, ! 970: force_reg (PSImode, GEN_INT (pos / 8)), ! 971: GEN_INT (3)); 1.1 root 972: }") 973: 974: ;; LOAD (also used by move insn). 975: (define_insn "" 1.1.1.3 root 976: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 977: (mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1.1 root 978: (const_int -4)))) 1.1.1.4 ! root 979: (set (match_operand:PSI 2 "register_operand" "=b") ! 980: (truncate:PSI (match_dup 1)))] 1.1 root 981: "! TARGET_DW_ENABLE" 1.1.1.4 ! root 982: "load 0,16,%0,%1" 1.1 root 983: [(set_attr "type" "load")]) 984: 985: (define_insn "" 1.1.1.3 root 986: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1.1.4 ! root 987: (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] ! 988: "TARGET_DW_ENABLE" ! 989: "load 0,1,%0,%1" 1.1 root 990: [(set_attr "type" "load")]) 991: 992: (define_insn "" 1.1.1.4 ! root 993: [(set (match_operand:HI 0 "gpc_reg_operand" "=r") ! 994: (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] ! 995: "TARGET_DW_ENABLE" ! 996: "load 0,1,%0,%1" ! 997: [(set_attr "type" "load")]) ! 998: ! 999: (define_insn "" ! 1000: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1001: (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] ! 1002: "TARGET_DW_ENABLE" ! 1003: "load 0,2,%0,%1" ! 1004: [(set_attr "type" "load")]) ! 1005: ! 1006: (define_insn "" ! 1007: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1008: (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))) ! 1009: (clobber (match_scratch:PSI 2 "=&b"))] ! 1010: "TARGET_DW_ENABLE" ! 1011: "load 0,17,%0,%1" ! 1012: [(set_attr "type" "load")]) ! 1013: ! 1014: (define_insn "" ! 1015: [(set (match_operand:HI 0 "gpc_reg_operand" "=r") ! 1016: (sign_extend:HI (match_operand:QI 1 "memory_operand" "m"))) ! 1017: (clobber (match_scratch:PSI 2 "=&b"))] ! 1018: "TARGET_DW_ENABLE" ! 1019: "load 0,17,%0,%1" ! 1020: [(set_attr "type" "load")]) ! 1021: ! 1022: (define_insn "" ! 1023: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1024: (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))) ! 1025: (clobber (match_scratch:PSI 2 "=&b"))] ! 1026: "TARGET_DW_ENABLE" ! 1027: "load 0,18,%0,%1" 1.1 root 1028: [(set_attr "type" "load")]) 1029: 1030: ;; LOADM 1031: (define_expand "load_multiple" 1.1.1.4 ! root 1032: [(set (match_dup 4) ! 1033: (match_operand:PSI 2 "const_int_operand" "")) ! 1034: (match_par_dup 3 [(set (match_operand:SI 0 "" "") ! 1035: (match_operand:SI 1 "" ""))])] 1.1 root 1036: "" 1037: " 1038: { 1039: int regno; 1040: int count; 1041: rtx from; 1042: int i; 1043: 1044: /* Support only loading a constant number of hard registers from memory. */ 1045: if (GET_CODE (operands[2]) != CONST_INT 1046: || operands[2] == const1_rtx 1047: || GET_CODE (operands[1]) != MEM 1048: || GET_CODE (operands[0]) != REG 1049: || REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER) 1050: FAIL; 1051: 1052: count = INTVAL (operands[2]); 1053: regno = REGNO (operands[0]); 1054: 1055: /* CR gets set to the number of registers minus one. */ 1.1.1.4 ! root 1056: operands[2] = GEN_INT(count - 1); 1.1 root 1057: 1058: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 2)); 1059: from = memory_address (SImode, XEXP (operands[1], 0)); 1060: XVECEXP (operands[3], 0, 0) = gen_rtx (SET, VOIDmode, 1061: gen_rtx (REG, SImode, regno), 1062: gen_rtx (MEM, SImode, from)); 1.1.1.4 ! root 1063: operands[4] = gen_reg_rtx (PSImode); ! 1064: ! 1065: XVECEXP (operands[3], 0, 1) = gen_rtx (USE, VOIDmode, operands[4]); ! 1066: XVECEXP (operands[3], 0, 2) = gen_rtx (CLOBBER, VOIDmode, operands[4]); 1.1 root 1067: 1068: for (i = 1; i < count; i++) 1069: XVECEXP (operands[3], 0, i + 2) 1070: = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i), 1071: gen_rtx (MEM, SImode, plus_constant (from, i * 4))); 1072: }") 1073: 1074: ;; Indicate that CR is used and is then clobbered. 1075: (define_insn "" 1.1.1.3 root 1076: [(set (match_operand 0 "gpc_reg_operand" "=r") 1.1 root 1077: (match_operand 1 "memory_operand" "m")) 1.1.1.4 ! root 1078: (use (match_operand:PSI 2 "register_operand" "+c")) ! 1079: (clobber (match_dup 2))] 1.1 root 1080: "GET_MODE (operands[0]) == GET_MODE (operands[1]) 1081: && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD 1082: && ! TARGET_29050" 1083: "loadm 0,0,%0,%1" 1084: [(set_attr "type" "load")]) 1085: 1086: (define_insn "" 1.1.1.3 root 1087: [(set (match_operand 0 "gpc_reg_operand" "=&r") 1.1 root 1088: (match_operand 1 "memory_operand" "m")) 1.1.1.4 ! root 1089: (use (match_operand:PSI 2 "register_operand" "+c")) ! 1090: (clobber (match_dup 2))] 1.1 root 1091: "GET_MODE (operands[0]) == GET_MODE (operands[1]) 1092: && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD 1093: && TARGET_29050" 1094: "loadm 0,0,%0,%1" 1095: [(set_attr "type" "load")]) 1096: 1097: (define_insn "" 1098: [(match_parallel 0 "load_multiple_operation" 1.1.1.3 root 1099: [(set (match_operand:SI 1 "gpc_reg_operand" "=r") 1.1 root 1100: (match_operand:SI 2 "memory_operand" "m")) 1.1.1.4 ! root 1101: (use (match_operand:PSI 3 "register_operand" "+c")) ! 1102: (clobber (match_dup 3))])] 1.1 root 1103: "! TARGET_29050" 1104: "loadm 0,0,%1,%2" 1105: [(set_attr "type" "load")]) 1106: 1107: (define_insn "" 1108: [(match_parallel 0 "load_multiple_operation" 1.1.1.3 root 1109: [(set (match_operand:SI 1 "gpc_reg_operand" "=&r") 1.1 root 1110: (match_operand:SI 2 "memory_operand" "m")) 1.1.1.4 ! root 1111: (use (match_operand:PSI 3 "register_operand" "+c")) ! 1112: (clobber (match_dup 3))])] 1.1 root 1113: "TARGET_29050" 1114: "loadm 0,0,%1,%2" 1115: [(set_attr "type" "load")]) 1116: 1117: ;; MTSR (used also by move insn) 1118: (define_insn "" 1119: [(set (match_operand:SI 0 "spec_reg_operand" "=*h,*h") 1.1.1.3 root 1120: (and:SI (match_operand:SI 1 "gpc_reg_or_immediate_operand" "r,i") 1.1 root 1121: (match_operand:SI 2 "const_int_operand" "n,n")))] 1122: "masks_bits_for_special (operands[0], operands[2])" 1123: "@ 1124: mtsr %0,%1 1125: mtsrim %0,%1") 1.1.1.4 ! root 1126: ! 1127: (define_insn "" ! 1128: [(set (match_operand:PSI 0 "register_operand" "=h,h") ! 1129: (truncate:PSI ! 1130: (match_operand:SI 1 "gpc_reg_or_immediate_operand" "r,i")))] ! 1131: "" ! 1132: "@ ! 1133: mtsr %0,%1 ! 1134: mtsrim %0,%1") 1.1 root 1135: 1136: ;; MULTIPLY, MULTM, MULTMU 1137: (define_insn "mulsi3" 1.1.1.3 root 1138: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1139: (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1140: (match_operand:SI 2 "gpc_reg_operand" "r")))] 1.1 root 1141: "" 1142: "multiply %0,%1,%2") 1143: 1144: (define_insn "" 1.1.1.3 root 1145: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1 root 1146: (subreg:SI 1147: (mult:DI 1.1.1.3 root 1148: (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1149: (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) 0))] 1.1 root 1150: "" 1151: "multm %0,%1,%2") 1152: 1153: (define_insn "" 1.1.1.3 root 1154: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1.1 root 1155: (subreg:SI 1156: (mult:DI 1.1.1.3 root 1157: (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1158: (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) 0))] 1.1 root 1159: "" 1160: "multmu %0,%1,%2") 1161: 1162: (define_insn "mulsidi3" 1.1.1.3 root 1163: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 1164: (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) 1165: (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] 1.1 root 1166: "" 1167: "multiply %L0,%1,%2\;multm %0,%1,%2" 1168: [(set_attr "type" "multi")]) 1169: 1170: (define_split 1.1.1.3 root 1171: [(set (match_operand:DI 0 "gpc_reg_operand" "") 1172: (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 1173: (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] 1.1 root 1174: "reload_completed" 1175: [(set (match_dup 3) 1176: (mult:SI (match_dup 1) (match_dup 2))) 1177: (set (match_dup 4) 1178: (subreg:SI (mult:DI 1179: (sign_extend:DI (match_dup 1)) 1180: (sign_extend:DI (match_dup 2))) 0))] 1181: " 1182: { operands[3] = operand_subword (operands[0], 1, 1, DImode); 1183: operands[4] = operand_subword (operands[1], 0, 1, DImode); } ") 1184: 1185: (define_insn "umulsidi3" 1.1.1.3 root 1186: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 1187: (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) 1188: (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] 1.1 root 1189: "" 1190: "multiplu %L0,%1,%2\;multmu %0,%1,%2" 1191: [(set_attr "type" "multi")]) 1192: 1193: (define_split 1.1.1.3 root 1194: [(set (match_operand:DI 0 "gpc_reg_operand" "") 1195: (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 1196: (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] 1.1 root 1197: "reload_completed" 1198: [(set (match_dup 3) 1199: (mult:SI (match_dup 1) (match_dup 2))) 1200: (set (match_dup 4) 1201: (subreg:SI (mult:DI (zero_extend:DI (match_dup 1)) 1202: (zero_extend:DI (match_dup 2))) 0))] 1203: " 1204: { operands[3] = operand_subword (operands[0], 1, 1, DImode); 1205: operands[4] = operand_subword (operands[1], 0, 1, DImode); } ") 1206: 1207: ;; NAND 1208: (define_insn "" 1.1.1.3 root 1209: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1210: (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1 root 1211: (not:SI (match_operand:SI 2 "srcb_operand" "rI"))))] 1212: "" 1213: "nand %0,%1,%2") 1214: 1215: (define_insn "" 1.1.1.3 root 1216: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1217: (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1.1 root 1218: (match_operand:SI 2 "const_int_operand" "K")))] 1219: "((unsigned) ~ INTVAL (operands[2])) < 256" 1220: "nand %0,%1,%C2") 1221: 1222: ;; NOR 1223: (define_insn "" 1.1.1.3 root 1224: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1225: (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1 root 1226: (not:SI (match_operand:SI 2 "srcb_operand" "rI"))))] 1227: "" 1228: "nor %0,%1,%2") 1229: 1230: (define_insn "" 1.1.1.3 root 1231: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1232: (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1.1 root 1233: (match_operand:SI 2 "const_int_operand" "K")))] 1234: "((unsigned) ~ INTVAL (operands[2])) < 256" 1235: "nor %0,%1,%C2") 1236: 1237: (define_insn "one_cmplsi2" 1.1.1.3 root 1238: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1239: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 1.1 root 1240: "" 1241: "nor %0,%1,0") 1242: 1243: ;; OR/ORN 1244: (define_expand "iorsi3" 1.1.1.3 root 1245: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1246: (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") 1.1 root 1247: (match_operand:SI 2 "srcb_operand" "")))] 1248: "" 1249: "") 1250: 1251: (define_insn "" 1.1.1.3 root 1252: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1253: (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1 root 1254: (match_operand:SI 2 "srcb_operand" "rI")))] 1255: "! TARGET_29050" 1256: "or %0,%1,%2") 1257: 1258: (define_insn "" 1.1.1.3 root 1259: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1260: (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 1.1 root 1261: (match_operand:SI 2 "srcb_operand" "rI,K")))] 1262: "TARGET_29050" 1263: "@ 1264: or %0,%1,%2 1265: orn %0,%1,%C2") 1266: 1267: 1268: ;; SLL (also used by move insn) 1269: (define_insn "nop" 1270: [(const_int 0)] 1271: "" 1272: "aseq 0x40,gr1,gr1") 1273: 1274: (define_insn "ashlsi3" 1.1.1.3 root 1275: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1276: (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1.1 root 1277: (match_operand:QI 2 "srcb_operand" "rn")))] 1278: "" 1279: "sll %0,%1,%Q2") 1280: 1.1.1.4 ! root 1281: ;; SQRT ! 1282: (define_insn "sqrtsf2" ! 1283: [(set (match_operand:SF 0 "gpc_reg_operand" "=r") ! 1284: (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "r")))] ! 1285: "TARGET_29050" ! 1286: "sqrt %0,%1,1" ! 1287: [(set_attr "type" "fsqrt")]) ! 1288: ! 1289: (define_insn "sqrtdf2" ! 1290: [(set (match_operand:DF 0 "gpc_reg_operand" "=r") ! 1291: (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "r")))] ! 1292: "TARGET_29050" ! 1293: "sqrt %0,%1,2" ! 1294: [(set_attr "type" "dsqrt")]) ! 1295: 1.1 root 1296: ;; SRA 1297: (define_insn "ashrsi3" 1.1.1.3 root 1298: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1299: (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1.1 root 1300: (match_operand:QI 2 "srcb_operand" "rn")))] 1301: "" 1302: "sra %0,%1,%Q2") 1303: 1304: ;; SRL 1305: (define_insn "lshrsi3" 1.1.1.3 root 1306: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1307: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1.1 root 1308: (match_operand:QI 2 "srcb_operand" "rn")))] 1309: "" 1310: "srl %0,%1,%Q2") 1311: 1312: ;; STORE 1313: ;; 1314: ;; These somewhat bogus patterns exist to set OPT = 001/010 for partial-word 1315: ;; stores on systems with DW not set. 1316: (define_insn "" 1.1.1.3 root 1317: [(set (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "r") 1.1 root 1318: (const_int -4))) 1.1.1.3 root 1319: (match_operand:SI 1 "gpc_reg_operand" "r"))] 1.1 root 1320: "! TARGET_DW_ENABLE" 1321: "store 0,1,%1,%0" 1322: [(set_attr "type" "store")]) 1323: 1324: (define_insn "" 1.1.1.3 root 1325: [(set (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "r") 1.1 root 1326: (const_int -3))) 1.1.1.3 root 1327: (match_operand:SI 1 "gpc_reg_operand" "r"))] 1.1 root 1328: "! TARGET_DW_ENABLE" 1329: "store 0,2,%1,%0" 1330: [(set_attr "type" "store")]) 1331: 1332: ;; STOREM 1333: (define_expand "store_multiple" 1334: [(use (match_operand 0 "" "")) 1335: (use (match_operand 1 "" "")) 1336: (use (match_operand 2 "" ""))] 1337: "" 1338: " 1339: { rtx pat; 1340: 1341: if (TARGET_NO_STOREM_BUG) 1342: pat = gen_store_multiple_no_bug (operands[0], operands[1], operands[2]); 1343: else 1344: pat = gen_store_multiple_bug (operands[0], operands[1], operands[2]); 1345: 1346: if (pat) 1347: emit_insn (pat); 1348: else 1349: FAIL; 1350: 1351: DONE; 1352: }") 1353: 1354: (define_expand "store_multiple_no_bug" 1.1.1.4 ! root 1355: [(set (match_dup 4) ! 1356: (match_operand:PSI 2 "const_int_operand" "")) ! 1357: (match_par_dup 3 [(set (match_operand:SI 0 "" "") ! 1358: (match_operand:SI 1 "" ""))])] 1.1 root 1359: "" 1360: " 1361: { 1362: int regno; 1363: int count; 1364: rtx from; 1365: int i; 1366: 1367: /* Support only storing a constant number of hard registers to memory. */ 1368: if (GET_CODE (operands[2]) != CONST_INT 1369: || operands[2] == const1_rtx 1370: || GET_CODE (operands[0]) != MEM 1371: || GET_CODE (operands[1]) != REG 1372: || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER) 1373: FAIL; 1374: 1375: count = INTVAL (operands[2]); 1376: regno = REGNO (operands[1]); 1377: 1378: /* CR gets set to the number of registers minus one. */ 1.1.1.4 ! root 1379: operands[2] = GEN_INT(count - 1); 1.1 root 1380: 1381: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 2)); 1382: from = memory_address (SImode, XEXP (operands[0], 0)); 1383: XVECEXP (operands[3], 0, 0) = gen_rtx (SET, VOIDmode, 1384: gen_rtx (MEM, SImode, from), 1385: gen_rtx (REG, SImode, regno)); 1.1.1.4 ! root 1386: operands[4] = gen_reg_rtx (PSImode); ! 1387: XVECEXP (operands[3], 0, 1) = gen_rtx (USE, VOIDmode, operands[4]); ! 1388: XVECEXP (operands[3], 0, 2) = gen_rtx (CLOBBER, VOIDmode, operands[4]); 1.1 root 1389: 1390: for (i = 1; i < count; i++) 1391: XVECEXP (operands[3], 0, i + 2) 1392: = gen_rtx (SET, VOIDmode, 1393: gen_rtx (MEM, SImode, plus_constant (from, i * 4)), 1394: gen_rtx (REG, SImode, regno + i)); 1395: }") 1396: 1397: (define_expand "store_multiple_bug" 1.1.1.4 ! root 1398: [(match_par_dup 3 [(set (match_operand:SI 0 "" "") ! 1399: (match_operand:SI 1 "" "")) ! 1400: (use (match_operand:SI 2 "" ""))])] 1.1 root 1401: "" 1402: " 1403: { 1404: int regno; 1405: int count; 1406: rtx from; 1407: int i; 1408: 1409: /* Support only storing a constant number of hard registers to memory. */ 1410: if (GET_CODE (operands[2]) != CONST_INT 1411: || operands[2] == const1_rtx 1412: || GET_CODE (operands[0]) != MEM 1413: || GET_CODE (operands[1]) != REG 1414: || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER) 1415: FAIL; 1416: 1417: count = INTVAL (operands[2]); 1418: regno = REGNO (operands[1]); 1419: 1420: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1)); 1421: from = memory_address (SImode, XEXP (operands[0], 0)); 1422: XVECEXP (operands[3], 0, 0) = gen_rtx (SET, VOIDmode, 1423: gen_rtx (MEM, SImode, from), 1424: gen_rtx (REG, SImode, regno)); 1425: XVECEXP (operands[3], 0, 1) 1.1.1.4 ! root 1426: = gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, PSImode)); 1.1 root 1427: 1428: for (i = 1; i < count; i++) 1429: XVECEXP (operands[3], 0, i + 1) 1430: = gen_rtx (SET, VOIDmode, 1431: gen_rtx (MEM, SImode, plus_constant (from, i * 4)), 1432: gen_rtx (REG, SImode, regno + i)); 1433: }") 1434: 1435: (define_insn "" 1436: [(set (match_operand 0 "memory_operand" "=m") 1.1.1.3 root 1437: (match_operand 1 "gpc_reg_operand" "r")) 1.1.1.4 ! root 1438: (clobber (match_scratch:PSI 2 "=&c"))] 1.1 root 1439: "!TARGET_NO_STOREM_BUG 1440: && GET_MODE (operands[0]) == GET_MODE (operands[1]) 1441: && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD" 1442: "mtsrim cr,%S1\;storem 0,0,%1,%0" 1443: [(set_attr "type" "multi")]) 1444: 1445: (define_insn "" 1446: [(match_parallel 0 "store_multiple_operation" 1447: [(set (match_operand:SI 1 "memory_operand" "=m") 1.1.1.3 root 1448: (match_operand:SI 2 "gpc_reg_operand" "r")) 1.1.1.4 ! root 1449: (clobber (match_scratch:PSI 3 "=&c"))])] 1.1 root 1450: "!TARGET_NO_STOREM_BUG" 1451: "mtsrim cr,%V0\;storem 0,0,%2,%1" 1452: [(set_attr "type" "multi")]) 1453: 1454: (define_insn "" 1455: [(set (match_operand 0 "memory_operand" "=m") 1.1.1.3 root 1456: (match_operand 1 "gpc_reg_operand" "r")) 1.1.1.4 ! root 1457: (use (match_operand:PSI 2 "register_operand" "+c")) ! 1458: (clobber (match_dup 2))] 1.1 root 1459: "TARGET_NO_STOREM_BUG 1460: && GET_MODE (operands[0]) == GET_MODE (operands[1]) 1461: && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD" 1462: "storem 0,0,%1,%0" 1463: [(set_attr "type" "store")]) 1464: 1465: (define_insn "" 1466: [(match_parallel 0 "store_multiple_operation" 1467: [(set (match_operand:SI 1 "memory_operand" "=m") 1.1.1.3 root 1468: (match_operand:SI 2 "gpc_reg_operand" "r")) 1.1.1.4 ! root 1469: (use (match_operand:PSI 3 "register_operand" "+c")) ! 1470: (clobber (match_dup 3))])] 1.1 root 1471: "TARGET_NO_STOREM_BUG" 1472: "storem 0,0,%2,%1" 1473: [(set_attr "type" "store")]) 1474: 1475: ;; SUB 1476: ;; 1477: ;; Either operand can be a register or an 8-bit constant, but both cannot be 1478: ;; constants (can't usually occur anyway). 1479: (define_expand "subsi3" 1.1.1.3 root 1480: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1.1 root 1481: (minus:SI (match_operand:SI 1 "srcb_operand" "") 1482: (match_operand:SI 2 "srcb_operand" "")))] 1483: "" 1484: " 1485: { 1486: if (GET_CODE (operands[0]) == CONST_INT 1487: && GET_CODE (operands[1]) == CONST_INT) 1488: operands[1] = force_reg (SImode, operands[1]); 1489: }") 1490: 1491: (define_insn "" 1.1.1.3 root 1492: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1.1 root 1493: (minus:SI (match_operand:SI 1 "srcb_operand" "r,I") 1494: (match_operand:SI 2 "srcb_operand" "rI,r")))] 1495: "register_operand (operands[1], SImode) 1496: || register_operand (operands[2], SImode)" 1497: "@ 1498: sub %0,%1,%2 1499: subr %0,%2,%1") 1500: 1501: (define_insn "subdi3" 1.1.1.3 root 1502: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 1503: (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r") 1504: (match_operand:DI 2 "gpc_reg_operand" "r")))] 1.1 root 1505: "" 1506: "sub %L0,%L1,%L2\;subc %0,%1,%2" 1507: [(set_attr "type" "multi")]) 1508: 1509: ;; SUBR (also used above in SUB) 1510: (define_insn "negdi2" 1.1.1.3 root 1511: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 1512: (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] 1.1 root 1513: "" 1514: "subr %L0,%L1,0\;subrc %0,%1,0" 1515: [(set_attr "type" "multi")]) 1516: 1517: (define_insn "negsi2" 1.1.1.3 root 1518: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1519: (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 1.1 root 1520: "" 1521: "subr %0,%1,0") 1522: 1523: ;; XNOR 1524: (define_insn "" 1.1.1.3 root 1525: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1526: (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1 root 1527: (match_operand:SI 2 "srcb_operand" "rI"))))] 1528: "" 1529: "xnor %0,%1,%2") 1530: 1531: ;; XOR 1532: (define_insn "xorsi3" 1.1.1.3 root 1533: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1534: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1 root 1535: (match_operand:SI 2 "srcb_operand" "rI")))] 1536: "" 1537: "xor %0,%1,%2") 1538: 1539: ;; Can use XOR to negate floating-point values, but we are better off not doing 1540: ;; it that way on the 29050 so it can combine with the fmac insns. 1541: (define_expand "negsf2" 1542: [(parallel [(set (match_operand:SF 0 "register_operand" "") 1543: (neg:SF (match_operand:SF 1 "register_operand" ""))) 1544: (clobber (match_scratch:SI 2 ""))])] 1545: "" 1546: " 1547: { 1548: rtx result; 1549: rtx target; 1550: 1551: if (! TARGET_29050) 1552: { 1553: target = operand_subword_force (operands[0], 0, SFmode); 1554: result = expand_binop (SImode, xor_optab, 1555: operand_subword_force (operands[1], 0, SFmode), 1.1.1.4 ! root 1556: GEN_INT(0x80000000), target, 0, OPTAB_WIDEN); 1.1 root 1557: if (result == 0) 1558: abort (); 1559: 1560: if (result != target) 1561: emit_move_insn (result, target); 1562: 1563: /* Make a place for REG_EQUAL. */ 1564: emit_move_insn (operands[0], operands[0]); 1565: DONE; 1566: } 1567: }") 1568: 1569: (define_expand "negdf2" 1570: [(parallel [(set (match_operand:DF 0 "register_operand" "") 1571: (neg:DF (match_operand:DF 1 "register_operand" ""))) 1572: (clobber (match_scratch:SI 2 ""))])] 1573: "" 1574: " 1575: { 1576: rtx result; 1577: rtx target; 1578: rtx insns; 1579: 1580: if (! TARGET_29050) 1581: { 1582: start_sequence (); 1583: target = operand_subword (operands[0], 0, 1, DFmode); 1584: result = expand_binop (SImode, xor_optab, 1585: operand_subword_force (operands[1], 0, DFmode), 1.1.1.4 ! root 1586: GEN_INT(0x80000000), target, 0, OPTAB_WIDEN); 1.1 root 1587: if (result == 0) 1588: abort (); 1589: 1590: if (result != target) 1591: emit_move_insn (result, target); 1592: 1593: emit_move_insn (operand_subword (operands[0], 1, 1, DFmode), 1594: operand_subword_force (operands[1], 1, DFmode)); 1595: 1596: insns = get_insns (); 1597: end_sequence (); 1598: 1599: emit_no_conflict_block (insns, operands[0], operands[1], 0, 0); 1600: DONE; 1601: } 1602: }") 1603: 1604: ;; Sign extend and truncation operations. 1605: (define_insn "zero_extendqihi2" 1.1.1.3 root 1606: [(set (match_operand:HI 0 "gpc_reg_operand" "=r") 1607: (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] 1.1 root 1608: "" 1609: "and %0,%1,255") 1610: 1611: (define_insn "zero_extendqisi2" 1.1.1.3 root 1612: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1613: (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] 1.1 root 1614: "" 1615: "and %0,%1,255") 1616: 1617: (define_insn "zero_extendhisi2" 1.1.1.3 root 1618: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1619: (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "0")))] 1.1 root 1620: "" 1621: "consth %0,0") 1622: 1623: (define_expand "extendqihi2" 1624: [(set (match_dup 2) 1.1.1.3 root 1625: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") 1.1 root 1626: (const_int 24))) 1.1.1.3 root 1627: (set (match_operand:HI 0 "gpc_reg_operand" "") 1.1 root 1628: (ashiftrt:SI (match_dup 2) 1629: (const_int 24)))] 1630: "" 1631: " 1632: { operands[0] = gen_lowpart (SImode, operands[0]); 1633: operands[1] = gen_lowpart (SImode, operands[1]); 1634: operands[2] = gen_reg_rtx (SImode); }") 1635: 1636: (define_expand "extendqisi2" 1637: [(set (match_dup 2) 1.1.1.3 root 1638: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") 1.1 root 1639: (const_int 24))) 1.1.1.3 root 1640: (set (match_operand:SI 0 "gpc_reg_operand" "") 1.1 root 1641: (ashiftrt:SI (match_dup 2) 1642: (const_int 24)))] 1643: "" 1644: " 1645: { operands[1] = gen_lowpart (SImode, operands[1]); 1646: operands[2] = gen_reg_rtx (SImode); }") 1647: 1648: (define_expand "extendhisi2" 1649: [(set (match_dup 2) 1.1.1.3 root 1650: (ashift:SI (match_operand:HI 1 "gpc_reg_operand" "") 1.1 root 1651: (const_int 16))) 1.1.1.3 root 1652: (set (match_operand:SI 0 "gpc_reg_operand" "") 1.1 root 1653: (ashiftrt:SI (match_dup 2) 1654: (const_int 16)))] 1655: "" 1656: " 1657: { operands[1] = gen_lowpart (SImode, operands[1]); 1658: operands[2] = gen_reg_rtx (SImode); }") 1659: 1660: ;; Define the methods used to move data around. 1661: ;; 1662: ;; movsi: 1663: ;; 1664: ;; If storing into memory, force source into register. 1665: (define_expand "movsi" 1666: [(set (match_operand:SI 0 "general_operand" "") 1667: (match_operand:SI 1 "general_operand" ""))] 1668: "" 1669: " 1670: { 1.1.1.3 root 1671: if (GET_CODE (operands[0]) == MEM && ! gpc_reg_operand (operands[1], SImode)) 1.1 root 1672: operands[1] = copy_to_mode_reg (SImode, operands[1]); 1673: else if (spec_reg_operand (operands[0], SImode) 1674: && ! (register_operand (operands[1], SImode) 1675: || cint_16_operand (operands[1], SImode))) 1676: operands[1] = force_reg (SImode, operands[1]); 1677: }") 1678: 1.1.1.4 ! root 1679: (define_expand "movpsi" ! 1680: [(set (match_operand:PSI 0 "general_operand" "") ! 1681: (match_operand:PSI 1 "general_operand" ""))] ! 1682: "" ! 1683: " ! 1684: { ! 1685: if (GET_CODE (operands[0]) == MEM ! 1686: && ! gpc_reg_operand (operands[1], PSImode)) ! 1687: operands[1] = copy_to_mode_reg (PSImode, operands[1]); ! 1688: else if (spec_reg_operand (operands[0], PSImode) ! 1689: && ! (register_operand (operands[1], PSImode) ! 1690: || cint_16_operand (operands[1], PSImode))) ! 1691: operands[1] = force_reg (PSImode, operands[1]); ! 1692: }") ! 1693: 1.1 root 1694: (define_split 1.1.1.3 root 1695: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1.1 root 1696: (match_operand:SI 1 "long_const_operand" ""))] 1697: "" 1698: [(set (match_dup 0) 1699: (and:SI (match_dup 1) 1700: (const_int 65535))) 1701: (set (match_dup 0) 1.1.1.4 ! root 1702: (ior:SI (zero_extend:SI (match_dup 2)) 1.1 root 1703: (and:SI (match_dup 1) 1704: (const_int -65536))))] 1.1.1.4 ! root 1705: " operands[2] = gen_lowpart (HImode, operands[0]); ") 1.1 root 1706: 1.1.1.4 ! root 1707: ;; Subroutines to load/store halfwords. Operands 0 and 1 are the output and ! 1708: ;; input, respectively, except that the address is passed for a MEM instead ! 1709: ;; of the MEM itself and the short item is passed in QImode. ! 1710: ;; ! 1711: ;; Operand 2 is a scratch general register and operand 3 is a scratch register ! 1712: ;; used for BP. When called before reload, pseudos are passed for both ! 1713: ;; operands. During reload, R_TAV is used for the general register, and ! 1714: ;; a reload register of class BR_REGS (R_VP) for BP. ! 1715: ;; ! 1716: ;; We have two versions of the store operations, for when halfword writes are ! 1717: ;; supported and when they are not. 1.1 root 1718: (define_expand "loadhi" 1.1.1.4 ! root 1719: [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "") ! 1720: (mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "") 1.1 root 1721: (const_int -4)))) 1.1.1.4 ! root 1722: (set (match_operand:PSI 3 "register_operand" "") ! 1723: (truncate:PSI (match_dup 1)))]) ! 1724: (set (match_operand:SI 0 "gpc_reg_operand" "") 1.1 root 1725: (zero_extract:SI (match_dup 2) 1726: (const_int 16) 1.1.1.4 ! root 1727: (ashift:PSI (match_dup 3) (const_int 3))))] 1.1 root 1728: "" 1.1.1.4 ! root 1729: "") 1.1 root 1730: 1731: (define_expand "storehinhww" 1.1.1.4 ! root 1732: [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "") 1.1.1.3 root 1733: (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "") 1.1 root 1734: (const_int -4)))) 1.1.1.4 ! root 1735: (set (match_operand:PSI 3 "register_operand" "") ! 1736: (truncate:PSI (match_dup 0)))]) 1.1 root 1737: (set (zero_extract:SI (match_dup 2) 1.1.1.4 ! root 1738: (const_int 16) ! 1739: (ashift:PSI (match_dup 3) (const_int 3))) ! 1740: (match_operand:SI 1 "gpc_reg_operand" "")) 1.1 root 1741: (set (mem:SI (match_dup 0)) 1742: (match_dup 2))] 1743: "" 1.1.1.4 ! root 1744: "") 1.1 root 1745: 1746: (define_expand "storehihww" 1.1.1.4 ! root 1747: [(set (match_operand:PSI 3 "register_operand" "") ! 1748: (truncate:PSI (match_operand:SI 0 "gpc_reg_operand" ""))) ! 1749: (set (match_operand:SI 2 "gpc_reg_operand" "") 1.1 root 1750: (ior:SI (and:SI (not:SI (ashift:SI (const_int 65535) 1.1.1.4 ! root 1751: (ashift:PSI (match_dup 3) ! 1752: (const_int 3)))) ! 1753: (match_operand:SI 1 "gpc_reg_operand" "")) ! 1754: (ashift:SI (zero_extend:SI (match_dup 4)) ! 1755: (ashift:PSI (match_dup 3) (const_int 3))))) 1.1 root 1756: (set (mem:SI (and:SI (match_dup 0) 1757: (const_int -3))) 1758: (match_dup 2))] 1759: "" 1760: " 1.1.1.4 ! root 1761: { operands[4] = gen_lowpart (HImode, operands[1]); }") 1.1 root 1762: 1763: (define_expand "movhi" 1764: [(set (match_operand:HI 0 "general_operand" "") 1765: (match_operand:HI 1 "general_operand" ""))] 1766: "" 1767: " 1768: { if (GET_CODE (operands[0]) == MEM) 1769: { 1.1.1.3 root 1770: if (! gpc_reg_operand (operands[1], HImode)) 1.1 root 1771: operands[1] = copy_to_mode_reg (HImode, operands[1]); 1772: if (! TARGET_DW_ENABLE) 1773: { 1.1.1.4 ! root 1774: rtx general = gen_reg_rtx (SImode); ! 1775: rtx bp = gen_reg_rtx (PSImode); ! 1776: rtx (*fcn) () ! 1777: = TARGET_BYTE_WRITES ? gen_storehihww : gen_storehinhww; ! 1778: rtx seq = (*fcn) (XEXP (operands[0], 0), ! 1779: gen_lowpart (SImode, operands[1]), ! 1780: general, bp); ! 1781: ! 1782: a29k_set_memflags (seq, operands[0]); ! 1783: emit_insn (seq); 1.1 root 1784: DONE; 1785: } 1786: } 1787: else if (GET_CODE (operands[1]) == MEM) 1788: { 1789: if (! TARGET_DW_ENABLE) 1790: { 1.1.1.4 ! root 1791: rtx general = gen_reg_rtx (SImode); ! 1792: rtx bp = gen_reg_rtx (PSImode); ! 1793: rtx seq = gen_loadqi (gen_lowpart (SImode, operands[0]), ! 1794: XEXP (operands[1], 0), general, bp); ! 1795: ! 1796: a29k_set_memflags (seq, operands[1]); ! 1797: emit_insn (seq); 1.1 root 1798: DONE; 1799: } 1800: } 1801: }") 1.1.1.4 ! root 1802: ! 1803: (define_expand "reload_inhi" ! 1804: [(parallel [(match_operand:SI 0 "register_operand" "=r") ! 1805: (match_operand:SI 1 "reload_memory_operand" "m") ! 1806: (match_operand:PSI 2 "register_operand" "=b")])] ! 1807: "! TARGET_DW_ENABLE" ! 1808: " ! 1809: { rtx seq = gen_loadhi (gen_lowpart (SImode, operands[0]), ! 1810: a29k_get_reloaded_address (operands[1]), ! 1811: gen_rtx (REG, SImode, R_TAV), ! 1812: operands[2]); ! 1813: ! 1814: a29k_set_memflags (seq, operands[1]); ! 1815: emit_insn (seq); ! 1816: DONE; ! 1817: }") ! 1818: ! 1819: (define_expand "reload_outhi" ! 1820: [(parallel [(match_operand:SI 0 "reload_memory_operand" "=m") ! 1821: (match_operand:SI 1 "register_operand" "m") ! 1822: (match_operand:PSI 2 "register_operand" "=b")])] ! 1823: "! TARGET_DW_ENABLE" ! 1824: " ! 1825: { rtx (*fcn) () = TARGET_BYTE_WRITES ? gen_storehihww : gen_storehinhww; ! 1826: rtx seq = (*fcn) (a29k_get_reloaded_address (operands[0]), ! 1827: gen_lowpart (SImode, operands[1]), ! 1828: gen_rtx (REG, SImode, R_TAV), operands[2]); ! 1829: ! 1830: a29k_set_memflags (seq, operands[0]); ! 1831: emit_insn (seq); ! 1832: DONE; ! 1833: }") 1.1 root 1834: 1.1.1.4 ! root 1835: ;; Subroutines to load/store bytes. Operands 0 and 1 are the output and ! 1836: ;; input, respectively, except that the address is passed for a MEM instead ! 1837: ;; of the MEM itself and the short item is passed in QImode. ! 1838: ;; ! 1839: ;; Operand 2 is a scratch general register and operand 3 is a scratch register ! 1840: ;; used for BP. When called before reload, pseudos are passed for both ! 1841: ;; operands. During reload, R_TAV is used for the general register, and ! 1842: ;; a reload register of class BR_REGS (R_VP) for BP. ! 1843: ;; ! 1844: ;; We have two versions of the store operations, for when byte writes are ! 1845: ;; supported and when they are not. 1.1 root 1846: (define_expand "loadqi" 1.1.1.4 ! root 1847: [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "") ! 1848: (mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "") 1.1 root 1849: (const_int -4)))) 1.1.1.4 ! root 1850: (set (match_operand:PSI 3 "register_operand" "") ! 1851: (truncate:PSI (match_dup 1)))]) ! 1852: (set (match_operand:SI 0 "gpc_reg_operand" "") 1.1 root 1853: (zero_extract:SI (match_dup 2) 1854: (const_int 8) 1.1.1.4 ! root 1855: (ashift:PSI (match_dup 3) (const_int 3))))] 1.1 root 1856: "" 1.1.1.4 ! root 1857: "") 1.1 root 1858: 1859: (define_expand "storeqinhww" 1.1.1.4 ! root 1860: [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "") 1.1.1.3 root 1861: (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "") 1.1 root 1862: (const_int -4)))) 1.1.1.4 ! root 1863: (set (match_operand:PSI 3 "register_operand" "") ! 1864: (truncate:PSI (match_dup 0)))]) 1.1 root 1865: (set (zero_extract:SI (match_dup 2) 1866: (const_int 8) 1.1.1.4 ! root 1867: (ashift:PSI (match_dup 3) ! 1868: (const_int 3))) ! 1869: (match_operand:SI 1 "gpc_reg_operand" "")) 1.1 root 1870: (set (mem:SI (match_dup 0)) 1871: (match_dup 2))] 1872: "" 1.1.1.4 ! root 1873: "") 1.1 root 1874: 1875: (define_expand "storeqihww" 1.1.1.4 ! root 1876: [(set (match_operand:PSI 3 "register_operand" "") ! 1877: (truncate:PSI (match_operand:SI 0 "gpc_reg_operand" ""))) ! 1878: (set (match_operand:SI 2 "gpc_reg_operand" "") 1.1 root 1879: (ior:SI (and:SI (not:SI (ashift:SI (const_int 255) 1.1.1.4 ! root 1880: (ashift:PSI (match_dup 3) ! 1881: (const_int 3)))) ! 1882: (match_operand:SI 1 "gpc_reg_operand" "")) ! 1883: (ashift:SI (zero_extend:SI (match_dup 4)) ! 1884: (ashift:PSI (match_dup 3) ! 1885: (const_int 3))))) 1.1 root 1886: (set (mem:SI (and:SI (match_dup 0) 1887: (const_int -4))) 1888: (match_dup 2))] 1889: "" 1890: " 1.1.1.4 ! root 1891: { operands[4] = gen_lowpart (QImode, operands[1]); }") 1.1 root 1892: 1893: (define_expand "movqi" 1894: [(set (match_operand:QI 0 "general_operand" "") 1895: (match_operand:QI 1 "general_operand" ""))] 1896: "" 1897: " 1898: { if (GET_CODE (operands[0]) == MEM) 1899: { 1.1.1.3 root 1900: if (! gpc_reg_operand (operands[1], QImode)) 1.1 root 1901: operands[1] = copy_to_mode_reg (QImode, operands[1]); 1902: if (! TARGET_DW_ENABLE) 1903: { 1.1.1.4 ! root 1904: rtx general = gen_reg_rtx (SImode); ! 1905: rtx bp = gen_reg_rtx (PSImode); ! 1906: rtx (*fcn) () ! 1907: = TARGET_BYTE_WRITES ? gen_storeqihww : gen_storeqinhww; ! 1908: rtx seq = (*fcn) (XEXP (operands[0], 0), ! 1909: gen_lowpart (SImode, operands[1]), ! 1910: general, bp); ! 1911: ! 1912: a29k_set_memflags (seq, operands[0]); ! 1913: emit_insn (seq); 1.1 root 1914: } 1915: } 1916: else if (GET_CODE (operands[1]) == MEM) 1917: { 1918: if (! TARGET_DW_ENABLE) 1919: { 1.1.1.4 ! root 1920: rtx general = gen_reg_rtx (SImode); ! 1921: rtx bp = gen_reg_rtx (PSImode); ! 1922: rtx seq = gen_loadqi (gen_lowpart (SImode, operands[0]), ! 1923: XEXP (operands[1], 0), general, bp); ! 1924: ! 1925: a29k_set_memflags (seq, operands[1]); ! 1926: emit_insn (seq); 1.1 root 1927: DONE; 1928: } 1929: } 1930: }") 1.1.1.4 ! root 1931: ! 1932: (define_expand "reload_inqi" ! 1933: [(parallel [(match_operand:SI 0 "register_operand" "=r") ! 1934: (match_operand:SI 1 "reload_memory_operand" "m") ! 1935: (match_operand:PSI 2 "register_operand" "=b")])] ! 1936: "! TARGET_DW_ENABLE" ! 1937: " ! 1938: { rtx seq = gen_loadqi (gen_lowpart (SImode, operands[0]), ! 1939: a29k_get_reloaded_address (operands[1]), ! 1940: gen_rtx (REG, SImode, R_TAV), ! 1941: operands[2]); ! 1942: ! 1943: a29k_set_memflags (seq, operands[1]); ! 1944: emit_insn (seq); ! 1945: DONE; ! 1946: }") ! 1947: ! 1948: (define_expand "reload_outqi" ! 1949: [(parallel [(match_operand:SI 0 "reload_memory_operand" "=m") ! 1950: (match_operand:SI 1 "register_operand" "m") ! 1951: (match_operand:PSI 2 "register_operand" "=b")])] ! 1952: "! TARGET_DW_ENABLE" ! 1953: " ! 1954: { rtx (*fcn) () = TARGET_BYTE_WRITES ? gen_storeqihww : gen_storeqinhww; ! 1955: rtx seq = (*fcn) (a29k_get_reloaded_address (operands[0]), ! 1956: gen_lowpart (SImode, operands[1]), ! 1957: gen_rtx (REG, SImode, R_TAV), operands[2]); ! 1958: ! 1959: a29k_set_memflags (seq, operands[0]); ! 1960: emit_insn (seq); ! 1961: DONE; ! 1962: }") 1.1 root 1963: 1964: ;; Now the actual insns used to move data around. We include here the 1965: ;; DEFINE_SPLITs that may be needed. In some cases these will be 1966: ;; split again. For floating-point, if we can look inside the constant, 1967: ;; always split it. This can eliminate unnecessary insns. 1968: (define_insn "" 1969: [(set (match_operand:SF 0 "out_operand" "=r,r,r,r,m") 1970: (match_operand:SF 1 "in_operand" "r,E,F,m,r"))] 1.1.1.3 root 1971: "(gpc_reg_operand (operands[0], SFmode) 1972: || gpc_reg_operand (operands[1], SFmode)) 1.1 root 1973: && ! TARGET_29050" 1974: "@ 1975: sll %0,%1,0 1976: # 1977: const %0,%1\;consth %0,%1 1978: load 0,0,%0,%1 1979: store 0,0,%1,%0" 1980: [(set_attr "type" "misc,multi,multi,load,store")]) 1981: 1982: (define_insn "" 1983: [(set (match_operand:SF 0 "out_operand" "=r,r,r,r,m,*a,r") 1984: (match_operand:SF 1 "in_operand" "r,E,F,m,r,r,*a"))] 1.1.1.3 root 1985: "(gpc_reg_operand (operands[0], SFmode) 1986: || gpc_reg_operand (operands[1], SFmode)) 1.1 root 1987: && TARGET_29050" 1988: "@ 1989: sll %0,%1,0 1990: # 1991: const %0,%1\;consth %0,%1 1992: load 0,0,%0,%1 1993: store 0,0,%1,%0 1994: mtacc %1,1,%0 1995: mfacc %0,1,%1" 1996: [(set_attr "type" "misc,multi,multi,load,store,fadd,fadd")]) 1997: 1998: ;; Turn this into SImode. It will then be split up that way. 1999: (define_split 2000: [(set (match_operand:SF 0 "register_operand" "") 2001: (match_operand:SF 1 "float_const_operand" ""))] 2002: "HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT" 2003: [(set (match_dup 0) 2004: (match_dup 1))] 2005: " 2006: { operands[0] = operand_subword (operands[0], 0, 0, SFmode); 2007: operands[1] = operand_subword (operands[1], 0, 0, SFmode); 2008: 2009: if (operands[0] == 0 || operands[1] == 0) 2010: FAIL; 2011: }") 2012: 2013: (define_insn "" 1.1.1.4 ! root 2014: [(set (match_operand:DF 0 "out_operand" "=?r,?r,r,m") 1.1 root 2015: (match_operand:DF 1 "in_operand" "rE,F,m,r")) 1.1.1.4 ! root 2016: (clobber (match_scratch:PSI 2 "=X,X,&c,&c"))] 1.1.1.3 root 2017: "(gpc_reg_operand (operands[0], DFmode) 2018: || gpc_reg_operand (operands[1], DFmode)) 1.1 root 2019: && ! TARGET_29050" 2020: "@ 2021: # 2022: const %0,%1\;consth %0,%1\;const %L0,%L1\;consth %L0,%L1 2023: mtsrim cr,1\;loadm 0,0,%0,%1 2024: mtsrim cr,1\;storem 0,0,%1,%0" 2025: [(set_attr "type" "multi")]) 2026: 2027: (define_insn "" 1.1.1.4 ! root 2028: [(set (match_operand:DF 0 "out_operand" "=?r,?r,&r,m,?*a,?r") 1.1 root 2029: (match_operand:DF 1 "in_operand" "rE,F,m,r,r,*a")) 1.1.1.4 ! root 2030: (clobber (match_scratch:PSI 2 "=X,X,&c,&c,X,X"))] 1.1.1.3 root 2031: "(gpc_reg_operand (operands[0], DFmode) 2032: || gpc_reg_operand (operands[1], DFmode)) 1.1 root 2033: && TARGET_29050" 2034: "@ 2035: # 2036: const %0,%1\;consth %0,%1\;const %L0,%L1\;consth %L0,%L1 2037: mtsrim cr,1\;loadm 0,0,%0,%1 2038: mtsrim cr,1\;storem 0,0,%1,%0 2039: mtacc %1,2,%0 2040: mfacc %0,2,%1" 2041: [(set_attr "type" "multi,multi,multi,multi,fadd,fadd")]) 2042: 2043: ;; Split register-register copies and constant loads into two SImode loads, 2044: ;; one for each word. In the constant case, they will get further split. 2045: ;; Don't so this until register allocation, though, since it will 2046: ;; interfere with register allocation. Normally copy the lowest-addressed 2047: ;; word first; the exception is if we are copying register to register and 2048: ;; the lowest register of the first operand is the highest register of the 2049: ;; second operand. 2050: (define_split 1.1.1.3 root 2051: [(set (match_operand:DF 0 "gpc_reg_operand" "") 2052: (match_operand:DF 1 "gpc_reg_or_float_constant_operand" "")) 1.1.1.4 ! root 2053: (clobber (match_scratch:PSI 2 ""))] 1.1 root 2054: "reload_completed" 1.1.1.4 ! root 2055: [(set (match_dup 3) (match_dup 4)) ! 2056: (set (match_dup 5) (match_dup 6))] 1.1 root 2057: " 2058: { if (GET_CODE (operands[1]) == REG 2059: && REGNO (operands[0]) == REGNO (operands[1]) + 1) 2060: { 1.1.1.4 ! root 2061: operands[3] = operand_subword (operands[0], 1, 1, DFmode); ! 2062: operands[4] = operand_subword (operands[1], 1, 1, DFmode); ! 2063: operands[5] = operand_subword (operands[0], 0, 1, DFmode); ! 2064: operands[6] = operand_subword (operands[1], 0, 1, DFmode); 1.1 root 2065: } 2066: else 2067: { 1.1.1.4 ! root 2068: operands[3] = operand_subword (operands[0], 0, 1, DFmode); ! 2069: operands[4] = operand_subword (operands[1], 0, 1, DFmode); ! 2070: operands[5] = operand_subword (operands[0], 1, 1, DFmode); ! 2071: operands[6] = operand_subword (operands[1], 1, 1, DFmode); 1.1 root 2072: } 2073: 1.1.1.4 ! root 2074: if (operands[3] == 0 || operands[4] == 0 ! 2075: || operands[5] == 0 || operands[6] == 0) 1.1 root 2076: FAIL; 2077: }") 2078: 2079: ;; Split memory loads and stores into the MTSR and LOADM/STOREM. 2080: (define_split 2081: [(set (match_operand:DF 0 "out_operand" "") 2082: (match_operand:DF 1 "in_operand" "")) 1.1.1.4 ! root 2083: (clobber (reg:PSI 179))] 1.1 root 2084: "TARGET_NO_STOREM_BUG 2085: && (memory_operand (operands[0], DFmode) 2086: || memory_operand (operands[1], DFmode))" 1.1.1.4 ! root 2087: [(set (reg:PSI 179) (const_int 1)) 1.1 root 2088: (parallel [(set (match_dup 0) (match_dup 1)) 1.1.1.4 ! root 2089: (use (reg:PSI 179)) ! 2090: (clobber (reg:PSI 179))])] 1.1 root 2091: "") 2092: 2093: ;; DI move is similar to DF move. 2094: (define_insn "" 1.1.1.4 ! root 2095: [(set (match_operand:DI 0 "out_operand" "=?r,r,m") 1.1 root 2096: (match_operand:DI 1 "in_operand" "rn,m,r")) 1.1.1.4 ! root 2097: (clobber (match_scratch:PSI 2 "=X,&c,&c"))] 1.1.1.3 root 2098: "(gpc_reg_operand (operands[0], DImode) 2099: || gpc_reg_operand (operands[1], DImode)) 1.1 root 2100: && ! TARGET_29050" 2101: "@ 2102: # 2103: mtsrim cr,1\;loadm 0,0,%0,%1 2104: mtsrim cr,1\;storem 0,0,%1,%0" 2105: [(set_attr "type" "multi")]) 2106: 2107: (define_insn "" 1.1.1.4 ! root 2108: [(set (match_operand:DI 0 "out_operand" "=?r,&r,m") 1.1 root 2109: (match_operand:DI 1 "in_operand" "rn,m,r")) 1.1.1.4 ! root 2110: (clobber (match_scratch:PSI 2 "=X,&c,&c"))] 1.1.1.3 root 2111: "(gpc_reg_operand (operands[0], DImode) 2112: || gpc_reg_operand (operands[1], DImode)) 1.1 root 2113: && TARGET_29050" 2114: "@ 2115: # 2116: mtsrim cr,1\;loadm 0,0,%0,%1 2117: mtsrim cr,1\;storem 0,0,%1,%0" 2118: [(set_attr "type" "multi")]) 2119: 2120: (define_split 1.1.1.3 root 2121: [(set (match_operand:DI 0 "gpc_reg_operand" "") 2122: (match_operand:DI 1 "gpc_reg_or_integer_constant_operand" "")) 1.1.1.4 ! root 2123: (clobber (match_scratch:PSI 2 ""))] 1.1 root 2124: "reload_completed" 1.1.1.4 ! root 2125: [(set (match_dup 3) (match_dup 4)) ! 2126: (set (match_dup 5) (match_dup 6))] 1.1 root 2127: " 2128: { if (GET_CODE (operands[1]) == REG 2129: && REGNO (operands[0]) == REGNO (operands[1]) + 1) 2130: { 1.1.1.4 ! root 2131: operands[3] = operand_subword (operands[0], 1, 1, DImode); ! 2132: operands[4] = operand_subword (operands[1], 1, 1, DImode); ! 2133: operands[5] = operand_subword (operands[0], 0, 1, DImode); ! 2134: operands[6] = operand_subword (operands[1], 0, 1, DImode); 1.1 root 2135: } 2136: else 2137: { 1.1.1.4 ! root 2138: operands[3] = operand_subword (operands[0], 0, 1, DImode); ! 2139: operands[4] = operand_subword (operands[1], 0, 1, DImode); ! 2140: operands[5] = operand_subword (operands[0], 1, 1, DImode); ! 2141: operands[6] = operand_subword (operands[1], 1, 1, DImode); 1.1 root 2142: } 2143: }") 2144: 2145: (define_split 2146: [(set (match_operand:DI 0 "out_operand" "") 2147: (match_operand:DI 1 "in_operand" "")) 1.1.1.4 ! root 2148: (clobber (reg:PSI 179))] 1.1 root 2149: "TARGET_NO_STOREM_BUG 2150: && (memory_operand (operands[0], DImode) 2151: || memory_operand (operands[1], DImode))" 1.1.1.4 ! root 2152: [(set (reg:PSI 179) (const_int 1)) 1.1 root 2153: (parallel [(set (match_dup 0) (match_dup 1)) 1.1.1.4 ! root 2154: (use (reg:PSI 179)) ! 2155: (clobber (reg:PSI 179))])] 1.1 root 2156: "") 2157: 2158: ;; TImode moves are very similar to DImode moves, except that we can't 2159: ;; have constants. 2160: (define_insn "" 1.1.1.4 ! root 2161: [(set (match_operand:TI 0 "out_operand" "=?r,r,m") 1.1 root 2162: (match_operand:TI 1 "in_operand" "r,m,r")) 1.1.1.4 ! root 2163: (clobber (match_scratch:PSI 2 "=X,&c,&c"))] 1.1.1.3 root 2164: "(gpc_reg_operand (operands[0], TImode) 2165: || gpc_reg_operand (operands[1], TImode)) 1.1 root 2166: && ! TARGET_29050" 2167: "@ 2168: # 2169: mtsrim cr,3\;loadm 0,0,%0,%1 2170: mtsrim cr,3\;storem 0,0,%1,%0" 2171: [(set_attr "type" "multi,multi,multi")]) 2172: 2173: (define_insn "" 1.1.1.4 ! root 2174: [(set (match_operand:TI 0 "out_operand" "=?r,&r,m") 1.1 root 2175: (match_operand:TI 1 "in_operand" "r,m,r")) 1.1.1.4 ! root 2176: (clobber (match_scratch:PSI 2 "=X,&c,&c"))] 1.1.1.3 root 2177: "(gpc_reg_operand (operands[0], TImode) 2178: || gpc_reg_operand (operands[1], TImode)) 1.1 root 2179: && TARGET_29050" 2180: "@ 2181: # 2182: mtsrim cr,3\;loadm 0,0,%0,%1 2183: mtsrim cr,3\;storem 0,0,%1,%0" 2184: [(set_attr "type" "multi,multi,multi")]) 2185: 2186: (define_split 1.1.1.3 root 2187: [(set (match_operand:TI 0 "gpc_reg_operand" "") 2188: (match_operand:TI 1 "gpc_reg_operand" "")) 1.1.1.4 ! root 2189: (clobber (match_scratch:PSI 2 ""))] 1.1 root 2190: "reload_completed" 1.1.1.4 ! root 2191: [(set (match_dup 3) (match_dup 4)) ! 2192: (set (match_dup 5) (match_dup 6)) ! 2193: (set (match_dup 7) (match_dup 8)) ! 2194: (set (match_dup 9) (match_dup 10))] 1.1 root 2195: " 2196: { 2197: if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 2198: && REGNO (operands[0]) <= REGNO (operands[1]) + 3) 2199: { 1.1.1.4 ! root 2200: operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 3); ! 2201: operands[4] = gen_rtx (REG, SImode, REGNO (operands[1]) + 3); ! 2202: operands[5] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2); ! 2203: operands[6] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2); ! 2204: operands[7] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); ! 2205: operands[8] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); ! 2206: operands[9] = gen_rtx (REG, SImode, REGNO (operands[0])); ! 2207: operands[10] = gen_rtx (REG, SImode, REGNO (operands[1])); 1.1 root 2208: } 2209: else 2210: { 1.1.1.4 ! root 2211: operands[3] = gen_rtx (REG, SImode, REGNO (operands[0])); ! 2212: operands[4] = gen_rtx (REG, SImode, REGNO (operands[1])); ! 2213: operands[5] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); ! 2214: operands[6] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); ! 2215: operands[7] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2); ! 2216: operands[8] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2); ! 2217: operands[9] = gen_rtx (REG, SImode, REGNO (operands[0]) + 3); ! 2218: operands[10] = gen_rtx (REG, SImode, REGNO (operands[1]) + 3); 1.1 root 2219: } 2220: }") 2221: 2222: (define_split 2223: [(set (match_operand:TI 0 "out_operand" "") 2224: (match_operand:TI 1 "in_operand" "")) 1.1.1.4 ! root 2225: (clobber (reg:PSI 179))] 1.1 root 2226: "TARGET_NO_STOREM_BUG 2227: && (memory_operand (operands[0], TImode) 2228: || memory_operand (operands[1], TImode))" 1.1.1.4 ! root 2229: [(set (reg:PSI 179) (const_int 1)) 1.1 root 2230: (parallel [(set (match_dup 0) (match_dup 1)) 1.1.1.4 ! root 2231: (use (reg:PSI 179)) ! 2232: (clobber (reg:PSI 179))])] 1.1 root 2233: "") 2234: 2235: (define_insn "" 2236: [(set (match_operand:SI 0 "out_operand" "=r,r,r,r,r,r,r,m,*h,*h") 2237: (match_operand:SI 1 "in_operand" "r,J,M,O,i,m,*h,r,r,J"))] 1.1.1.3 root 2238: "(gpc_reg_operand (operands[0], SImode) 2239: || gpc_reg_operand (operands[1], SImode) 1.1 root 2240: || (spec_reg_operand (operands[0], SImode) 2241: && cint_16_operand (operands[1], SImode))) 2242: && ! TARGET_29050" 2243: "@ 2244: sll %0,%1,0 2245: const %0,%1 2246: constn %0,%M1 2247: cpeq %0,gr1,gr1 2248: # 2249: load 0,0,%0,%1 2250: mfsr %0,%1 2251: store 0,0,%1,%0 2252: mtsr %0,%1 2253: mtsrim %0,%1" 2254: [(set_attr "type" "misc,misc,misc,misc,multi,load,misc,store,misc,misc")]) 2255: 2256: (define_insn "" 2257: [(set (match_operand:SI 0 "out_operand" "=r,r,r,r,r,r,r,m,*h,*h") 2258: (match_operand:SI 1 "in_operand" "r,J,M,O,i,m,*h,r,r,J"))] 1.1.1.3 root 2259: "(gpc_reg_operand (operands[0], SImode) 2260: || gpc_reg_operand (operands[1], SImode) 1.1 root 2261: || (spec_reg_operand (operands[0], SImode) 2262: && cint_16_operand (operands[1], SImode))) 2263: && TARGET_29050" 2264: "@ 2265: sll %0,%1,0 2266: const %0,%1 2267: constn %0,%M1 2268: consthz %0,%1 2269: # 2270: load 0,0,%0,%1 2271: mfsr %0,%1 2272: store 0,0,%1,%0 2273: mtsr %0,%1 2274: mtsrim %0,%1" 2275: [(set_attr "type" "misc,misc,misc,misc,multi,load,misc,store,misc,misc")]) 2276: 2277: (define_insn "" 1.1.1.4 ! root 2278: [(set (match_operand:PSI 0 "out_operand" "=*r,*r,*r,*r,m,h,h") ! 2279: (match_operand:PSI 1 "in_operand" "r,i,m,h,r,r,J"))] ! 2280: "(gpc_reg_operand (operands[0], PSImode) ! 2281: || gpc_reg_operand (operands[1], PSImode) ! 2282: || (spec_reg_operand (operands[0], PSImode) ! 2283: && cint_16_operand (operands[1], PSImode)))" ! 2284: "@ ! 2285: sll %0,%1,0 ! 2286: const %0,%1 ! 2287: load 0,0,%0,%1 ! 2288: mfsr %0,%1 ! 2289: store 0,0,%1,%0 ! 2290: mtsr %0,%1 ! 2291: mtsrim %0,%1" ! 2292: [(set_attr "type" "misc,multi,load,misc,store,misc,misc")]) ! 2293: ! 2294: (define_insn "" 1.1 root 2295: [(set (match_operand:HI 0 "out_operand" "=r,r,r,m,r,*h,*h") 2296: (match_operand:HI 1 "in_operand" "r,i,m,r,*h,r,i"))] 1.1.1.3 root 2297: "gpc_reg_operand (operands[0], HImode) 1.1.1.4 ! root 2298: || gpc_reg_operand (operands[1], HImode) ! 2299: || (spec_reg_operand (operands[0], HImode) ! 2300: && cint_16_operand (operands[1], HImode))" 1.1 root 2301: "@ 2302: sll %0,%1,0 2303: const %0,%1 2304: load 0,2,%0,%1 2305: store 0,2,%1,%0 2306: mfsr %0,%1 2307: mtsr %0,%1 2308: mtsrim %0,%1" 2309: [(set_attr "type" "misc,misc,load,store,misc,misc,misc")]) 2310: 2311: (define_insn "" 2312: [(set (match_operand:QI 0 "out_operand" "=r,r,r,m,r,*h,*h") 2313: (match_operand:QI 1 "in_operand" "r,i,m,r,*h,r,i"))] 1.1.1.3 root 2314: "gpc_reg_operand (operands[0], QImode) 1.1.1.4 ! root 2315: || gpc_reg_operand (operands[1], QImode) ! 2316: || (spec_reg_operand (operands[0], HImode) ! 2317: && cint_16_operand (operands[1], HImode))" 1.1 root 2318: "@ 2319: sll %0,%1,0 2320: const %0,%1 2321: load 0,1,%0,%1 2322: store 0,1,%1,%0 2323: mfsr %0,%1 2324: mtsr %0,%1 2325: mtsrim %0,%1" 2326: [(set_attr "type" "misc,misc,load,store,misc,misc,misc")]) 2327: 2328: ;; Define move insns for DI, TI, SF, and DF. 2329: ;; 2330: ;; In no case do we support mem->mem directly. 2331: ;; 2332: ;; For DI move of constant to register, split apart at this time since these 2333: ;; can require anywhere from 2 to 4 insns and determining which is complex. 2334: ;; 2335: ;; In other cases, handle similarly to SImode moves. 2336: ;; 1.1.1.4 ! root 2337: ;; However, indicate that DI, TI, and DF moves may clobber CR (reg 179). 1.1 root 2338: (define_expand "movdi" 2339: [(parallel [(set (match_operand:DI 0 "general_operand" "") 2340: (match_operand:DI 1 "general_operand" "")) 1.1.1.4 ! root 2341: (clobber (scratch:PSI))])] 1.1 root 2342: "" 2343: " 2344: { 2345: if (GET_CODE (operands[0]) == MEM) 2346: operands[1] = force_reg (DImode, operands[1]); 2347: }") 2348: 2349: (define_expand "movsf" 2350: [(set (match_operand:SF 0 "general_operand" "") 2351: (match_operand:SF 1 "general_operand" ""))] 2352: "" 2353: " 2354: { if (GET_CODE (operands[0]) == MEM) 2355: operands[1] = force_reg (SFmode, operands[1]); 2356: }") 2357: 2358: (define_expand "movdf" 2359: [(parallel [(set (match_operand:DF 0 "general_operand" "") 2360: (match_operand:DF 1 "general_operand" "")) 1.1.1.4 ! root 2361: (clobber (scratch:PSI))])] 1.1 root 2362: "" 2363: " 2364: { if (GET_CODE (operands[0]) == MEM) 2365: operands[1] = force_reg (DFmode, operands[1]); 2366: }") 2367: 2368: (define_expand "movti" 2369: [(parallel [(set (match_operand:TI 0 "general_operand" "") 2370: (match_operand:TI 1 "general_operand" "")) 1.1.1.4 ! root 2371: (clobber (scratch:PSI))])] 1.1 root 2372: "" 2373: " 2374: { 2375: if (GET_CODE (operands[0]) == MEM) 2376: operands[1] = force_reg (TImode, operands[1]); 1.1.1.4 ! root 2377: ! 2378: /* We can't handle constants in general because there is no rtl to represent ! 2379: 128 bit constants. Splitting happens to work for CONST_INTs so we split ! 2380: them for good code. Other constants will get forced to memory. */ ! 2381: ! 2382: if (GET_CODE (operands[1]) == CONST_INT) ! 2383: { ! 2384: rtx part0, part1, part2, part3; ! 2385: ! 2386: part0 = operand_subword (operands[0], 0, 1, TImode); ! 2387: part1 = operand_subword (operands[0], 1, 1, TImode); ! 2388: part2 = operand_subword (operands[0], 2, 1, TImode); ! 2389: part3 = operand_subword (operands[0], 3, 1, TImode); ! 2390: ! 2391: emit_move_insn (part0, const0_rtx); ! 2392: emit_move_insn (part1, const0_rtx); ! 2393: emit_move_insn (part2, const0_rtx); ! 2394: emit_move_insn (part3, const0_rtx); ! 2395: ! 2396: DONE; ! 2397: } ! 2398: else if (CONSTANT_P (operands[1])) ! 2399: { ! 2400: operands[1] = force_const_mem (TImode, operands[1]); ! 2401: if (! memory_address_p (TImode, XEXP (operands[1], 0)) ! 2402: && ! reload_in_progress) ! 2403: operands[1] = change_address (operands[1], TImode, ! 2404: XEXP (operands[1], 0)); ! 2405: } 1.1 root 2406: }") 2407: 1.1.1.4 ! root 2408: ;; Here are the variants of the above for use during reload. ! 2409: ! 2410: (define_expand "reload_indf" ! 2411: [(parallel [(set (match_operand:DF 0 "register_operand" "=r") ! 2412: (match_operand:DF 1 "reload_memory_operand" "m")) ! 2413: (clobber (match_operand:PSI 2 "register_operand" "=&c"))])] ! 2414: "" ! 2415: "") ! 2416: ! 2417: (define_expand "reload_outdf" ! 2418: [(parallel [(set (match_operand:DF 0 "reload_memory_operand" "=m") ! 2419: (match_operand:DF 1 "register_operand" "r")) ! 2420: (clobber (match_operand:PSI 2 "register_operand" "=&c"))])] ! 2421: "" ! 2422: "") ! 2423: ! 2424: (define_expand "reload_indi" ! 2425: [(parallel [(set (match_operand:DI 0 "register_operand" "=r") ! 2426: (match_operand:DI 1 "reload_memory_operand" "m")) ! 2427: (clobber (match_operand:PSI 2 "register_operand" "=&c"))])] ! 2428: "" ! 2429: "") ! 2430: ! 2431: (define_expand "reload_outdi" ! 2432: [(parallel [(set (match_operand:DI 0 "reload_memory_operand" "=m") ! 2433: (match_operand:DI 1 "register_operand" "r")) ! 2434: (clobber (match_operand:PSI 2 "register_operand" "=&c"))])] ! 2435: "" ! 2436: "") ! 2437: ! 2438: (define_expand "reload_inti" ! 2439: [(parallel [(set (match_operand:TI 0 "register_operand" "=r") ! 2440: (match_operand:TI 1 "reload_memory_operand" "m")) ! 2441: (clobber (match_operand:PSI 2 "register_operand" "=&c"))])] ! 2442: "" ! 2443: "") ! 2444: ! 2445: (define_expand "reload_outti" ! 2446: [(parallel [(set (match_operand:TI 0 "reload_memory_operand" "=m") ! 2447: (match_operand:TI 1 "register_operand" "r")) ! 2448: (clobber (match_operand:PSI 2 "register_operand" "=&c"))])] ! 2449: "" ! 2450: "") ! 2451: 1.1 root 2452: ;; For compare operations, we simply store the comparison operands and 2453: ;; do nothing else. The following branch or scc insn will output whatever 2454: ;; is needed. 2455: (define_expand "cmpsi" 2456: [(set (cc0) 1.1.1.3 root 2457: (compare (match_operand:SI 0 "gpc_reg_operand" "") 1.1 root 2458: (match_operand:SI 1 "srcb_operand" "")))] 2459: "" 2460: " 2461: { 2462: a29k_compare_op0 = operands[0]; 2463: a29k_compare_op1 = operands[1]; 2464: a29k_compare_fp_p = 0; 2465: DONE; 2466: }") 2467: 2468: (define_expand "cmpsf" 2469: [(set (cc0) 1.1.1.3 root 2470: (compare (match_operand:SF 0 "gpc_reg_operand" "") 2471: (match_operand:SF 1 "gpc_reg_operand" "")))] 1.1 root 2472: "" 2473: " 2474: { 2475: a29k_compare_op0 = operands[0]; 2476: a29k_compare_op1 = operands[1]; 2477: a29k_compare_fp_p = 1; 2478: DONE; 2479: }") 2480: 2481: (define_expand "cmpdf" 2482: [(set (cc0) 1.1.1.3 root 2483: (compare (match_operand:DF 0 "gpc_reg_operand" "") 2484: (match_operand:DF 1 "gpc_reg_operand" "")))] 1.1 root 2485: "" 2486: " 2487: { 2488: a29k_compare_op0 = operands[0]; 2489: a29k_compare_op1 = operands[1]; 2490: a29k_compare_fp_p = 1; 2491: DONE; 2492: }") 2493: 2494: ;; We can generate bit-tests better if we use NE instead of EQ, but we 2495: ;; don't have an NE for floating-point. So we have to have two patterns 2496: ;; for EQ and two for NE. 2497: 2498: (define_expand "beq" 2499: [(set (match_dup 1) (ne:SI (match_dup 2) (match_dup 3))) 2500: (set (pc) 2501: (if_then_else (ge (match_dup 1) (const_int 0)) 2502: (label_ref (match_operand 0 "" "")) 2503: (pc)))] 2504: "" 2505: " 2506: { 2507: if (GET_MODE_CLASS (GET_MODE (a29k_compare_op0)) == MODE_FLOAT) 2508: { 2509: emit_insn (gen_beq_fp (operands[0])); 2510: DONE; 2511: } 2512: 2513: operands[1] = gen_reg_rtx (SImode); 2514: operands[2] = a29k_compare_op0; 2515: operands[3] = a29k_compare_op1; 2516: }") 2517: 2518: (define_expand "beq_fp" 2519: [(set (match_dup 1) (eq:SI (match_dup 2) (match_dup 3))) 2520: (set (pc) 2521: (if_then_else (lt (match_dup 1) (const_int 0)) 2522: (label_ref (match_operand 0 "" "")) 2523: (pc)))] 2524: "" 2525: " 2526: { 2527: operands[1] = gen_reg_rtx (SImode); 2528: operands[2] = a29k_compare_op0; 2529: operands[3] = a29k_compare_op1; 2530: }") 2531: 2532: (define_expand "bne" 2533: [(set (match_dup 1) (ne:SI (match_dup 2) (match_dup 3))) 2534: (set (pc) 2535: (if_then_else (lt (match_dup 1) (const_int 0)) 2536: (label_ref (match_operand 0 "" "")) 2537: (pc)))] 2538: "" 2539: " 2540: { 2541: if (GET_MODE_CLASS (GET_MODE (a29k_compare_op0)) == MODE_FLOAT) 2542: { 2543: emit_insn (gen_bne_fp (operands[0])); 2544: DONE; 2545: } 2546: 2547: operands[1] = gen_reg_rtx (SImode); 2548: operands[2] = a29k_compare_op0; 2549: operands[3] = a29k_compare_op1; 2550: }") 2551: 2552: (define_expand "bne_fp" 2553: [(set (match_dup 1) (eq:SI (match_dup 2) (match_dup 3))) 2554: (set (pc) 2555: (if_then_else (ge (match_dup 1) (const_int 0)) 2556: (label_ref (match_operand 0 "" "")) 2557: (pc)))] 2558: "" 2559: " 2560: { 2561: operands[1] = gen_reg_rtx (SImode); 2562: operands[2] = a29k_compare_op0; 2563: operands[3] = a29k_compare_op1; 2564: }") 2565: 2566: ;; We don't have a floating-point "lt" insn, so we have to use "gt" in that 2567: ;; case with the operands swapped. The operands must both be registers in 2568: ;; the floating-point case, so we know that swapping them is OK. 2569: (define_expand "blt" 2570: [(set (match_dup 1) (match_dup 2)) 2571: (set (pc) 2572: (if_then_else (lt (match_dup 1) (const_int 0)) 2573: (label_ref (match_operand 0 "" "")) 2574: (pc)))] 2575: "" 2576: " 2577: { 2578: operands[1] = gen_reg_rtx (SImode); 2579: if (a29k_compare_fp_p) 2580: operands[2] = gen_rtx (GT, SImode, a29k_compare_op1, a29k_compare_op0); 2581: else 2582: operands[2] = gen_rtx (LT, SImode, a29k_compare_op0, a29k_compare_op1); 2583: }") 2584: 2585: ;; Similarly for "le". 2586: (define_expand "ble" 2587: [(set (match_dup 1) (match_dup 2)) 2588: (set (pc) 2589: (if_then_else (lt (match_dup 1) (const_int 0)) 2590: (label_ref (match_operand 0 "" "")) 2591: (pc)))] 2592: "" 2593: " 2594: { 2595: operands[1] = gen_reg_rtx (SImode); 2596: if (a29k_compare_fp_p) 2597: operands[2] = gen_rtx (GE, SImode, a29k_compare_op1, a29k_compare_op0); 2598: else 2599: operands[2] = gen_rtx (LE, SImode, a29k_compare_op0, a29k_compare_op1); 2600: }") 2601: 2602: (define_expand "bltu" 2603: [(set (match_dup 1) (ltu:SI (match_dup 2) (match_dup 3))) 2604: (set (pc) 2605: (if_then_else (lt (match_dup 1) (const_int 0)) 2606: (label_ref (match_operand 0 "" "")) 2607: (pc)))] 2608: "" 2609: " 2610: { 2611: operands[1] = gen_reg_rtx (SImode); 2612: operands[2] = a29k_compare_op0; 2613: operands[3] = a29k_compare_op1; 2614: }") 2615: 2616: (define_expand "bleu" 2617: [(set (match_dup 1) (leu:SI (match_dup 2) (match_dup 3))) 2618: (set (pc) 2619: (if_then_else (lt (match_dup 1) (const_int 0)) 2620: (label_ref (match_operand 0 "" "")) 2621: (pc)))] 2622: "" 2623: " 2624: { 2625: operands[1] = gen_reg_rtx (SImode); 2626: operands[2] = a29k_compare_op0; 2627: operands[3] = a29k_compare_op1; 2628: }") 2629: 2630: (define_expand "bgt" 2631: [(set (match_dup 1) (gt:SI (match_dup 2) (match_dup 3))) 2632: (set (pc) 2633: (if_then_else (lt (match_dup 1) (const_int 0)) 2634: (label_ref (match_operand 0 "" "")) 2635: (pc)))] 2636: "" 2637: " 2638: { 2639: operands[1] = gen_reg_rtx (SImode); 2640: operands[2] = a29k_compare_op0; 2641: operands[3] = a29k_compare_op1; 2642: }") 2643: 2644: (define_expand "bge" 2645: [(set (match_dup 1) (ge:SI (match_dup 2) (match_dup 3))) 2646: (set (pc) 2647: (if_then_else (lt (match_dup 1) (const_int 0)) 2648: (label_ref (match_operand 0 "" "")) 2649: (pc)))] 2650: "" 2651: " 2652: { 2653: operands[1] = gen_reg_rtx (SImode); 2654: operands[2] = a29k_compare_op0; 2655: operands[3] = a29k_compare_op1; 2656: }") 2657: 2658: (define_expand "bgtu" 2659: [(set (match_dup 1) (gtu:SI (match_dup 2) (match_dup 3))) 2660: (set (pc) 2661: (if_then_else (lt (match_dup 1) (const_int 0)) 2662: (label_ref (match_operand 0 "" "")) 2663: (pc)))] 2664: "" 2665: " 2666: { 2667: operands[1] = gen_reg_rtx (SImode); 2668: operands[2] = a29k_compare_op0; 2669: operands[3] = a29k_compare_op1; 2670: }") 2671: 2672: (define_expand "bgeu" 2673: [(set (match_dup 1) (geu:SI (match_dup 2) (match_dup 3))) 2674: (set (pc) 2675: (if_then_else (lt (match_dup 1) (const_int 0)) 2676: (label_ref (match_operand 0 "" "")) 2677: (pc)))] 2678: "" 2679: " 2680: { 2681: operands[1] = gen_reg_rtx (SImode); 2682: operands[2] = a29k_compare_op0; 2683: operands[3] = a29k_compare_op1; 2684: }") 2685: 2686: (define_expand "seq" 1.1.1.3 root 2687: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1.1 root 2688: (eq:SI (match_dup 1) (match_dup 2)))] 2689: "" 2690: " 2691: { 2692: operands[1] = a29k_compare_op0; 2693: operands[2] = a29k_compare_op1; 2694: }") 2695: 2696: ;; This is the most complicated case, because we don't have a floating-point 2697: ;; "ne" insn. If integer, handle normally. If floating-point, write the 2698: ;; compare and then write an insn to reverse the test. 2699: (define_expand "sne_fp" 2700: [(set (match_dup 3) 1.1.1.3 root 2701: (eq:SI (match_operand 1 "gpc_reg_operand" "") 2702: (match_operand 2 "gpc_reg_operand" ""))) 2703: (set (match_operand:SI 0 "gpc_reg_operand" "") 1.1 root 2704: (ge:SI (match_dup 3) (const_int 0)))] 2705: "" 2706: " 2707: { operands[3] = gen_reg_rtx (SImode); 2708: }"); 2709: 2710: (define_expand "sne" 1.1.1.3 root 2711: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1.1 root 2712: (ne:SI (match_dup 1) (match_dup 2)))] 2713: "" 2714: " 2715: { 2716: operands[1] = a29k_compare_op0; 2717: operands[2] = a29k_compare_op1; 2718: 2719: if (a29k_compare_fp_p) 2720: { 2721: emit_insn (gen_sne_fp (operands[0], operands[1], operands[2])); 2722: DONE; 2723: } 2724: }") 2725: 2726: ;; We don't have a floating-point "lt" insn, so use "gt" and swap the 2727: ;; operands, the same as we do "blt". 2728: (define_expand "slt" 1.1.1.3 root 2729: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1.1 root 2730: (match_dup 1))] 2731: "" 2732: " 2733: { 2734: if (a29k_compare_fp_p) 2735: operands[1] = gen_rtx (GT, SImode, a29k_compare_op1, a29k_compare_op0); 2736: else 2737: operands[1] = gen_rtx (LT, SImode, a29k_compare_op0, a29k_compare_op1); 2738: }") 2739: 2740: ;; Similarly for "le" 2741: (define_expand "sle" 1.1.1.3 root 2742: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1.1 root 2743: (match_dup 1))] 2744: "" 2745: " 2746: { 2747: if (a29k_compare_fp_p) 2748: operands[1] = gen_rtx (GE, SImode, a29k_compare_op1, a29k_compare_op0); 2749: else 2750: operands[1] = gen_rtx (LE, SImode, a29k_compare_op0, a29k_compare_op1); 2751: }") 2752: 2753: (define_expand "sltu" 1.1.1.3 root 2754: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1.1 root 2755: (ltu:SI (match_dup 1) (match_dup 2)))] 2756: "" 2757: " 2758: { 2759: operands[1] = a29k_compare_op0; 2760: operands[2] = a29k_compare_op1; 2761: }") 2762: 2763: (define_expand "sleu" 1.1.1.3 root 2764: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1.1 root 2765: (leu:SI (match_dup 1) (match_dup 2)))] 2766: "" 2767: " 2768: { 2769: operands[1] = a29k_compare_op0; 2770: operands[2] = a29k_compare_op1; 2771: }") 2772: 2773: (define_expand "sgt" 1.1.1.3 root 2774: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1.1 root 2775: (gt:SI (match_dup 1) (match_dup 2)))] 2776: "" 2777: " 2778: { 2779: operands[1] = a29k_compare_op0; 2780: operands[2] = a29k_compare_op1; 2781: }") 2782: 2783: (define_expand "sge" 1.1.1.3 root 2784: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1.1 root 2785: (ge:SI (match_dup 1) (match_dup 2)))] 2786: "" 2787: " 2788: { 2789: operands[1] = a29k_compare_op0; 2790: operands[2] = a29k_compare_op1; 2791: }") 2792: 2793: (define_expand "sgtu" 1.1.1.3 root 2794: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1.1 root 2795: (gtu:SI (match_dup 1) (match_dup 2)))] 2796: "" 2797: " 2798: { 2799: operands[1] = a29k_compare_op0; 2800: operands[2] = a29k_compare_op1; 2801: }") 2802: 2803: (define_expand "sgeu" 1.1.1.3 root 2804: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1.1 root 2805: (geu:SI (match_dup 1) (match_dup 2)))] 2806: "" 2807: " 2808: { 2809: operands[1] = a29k_compare_op0; 2810: operands[2] = a29k_compare_op1; 2811: }") 2812: 2813: ;; Now define the actual jump insns. 2814: (define_insn "" 2815: [(set (pc) 2816: (if_then_else (match_operator 0 "branch_operator" 1.1.1.3 root 2817: [(match_operand:SI 1 "gpc_reg_operand" "r") 1.1 root 2818: (const_int 0)]) 2819: (label_ref (match_operand 2 "" "")) 2820: (pc)))] 2821: "" 2822: "jmp%b0 %1,%l2%#" 2823: [(set_attr "type" "branch")]) 2824: 2825: (define_insn "" 2826: [(set (pc) 2827: (if_then_else (match_operator 0 "branch_operator" 1.1.1.3 root 2828: [(match_operand:SI 1 "gpc_reg_operand" "r") 1.1 root 2829: (const_int 0)]) 2830: (return) 2831: (pc)))] 2832: "null_epilogue ()" 2833: "jmp%b0i %1,lr0%#" 2834: [(set_attr "type" "branch")]) 2835: 2836: (define_insn "" 2837: [(set (pc) 2838: (if_then_else (match_operator 0 "branch_operator" 1.1.1.3 root 2839: [(match_operand:SI 1 "gpc_reg_operand" "r") 1.1 root 2840: (const_int 0)]) 2841: (pc) 2842: (label_ref (match_operand 2 "" ""))))] 2843: "" 2844: "jmp%B0 %1,%l2%#" 2845: [(set_attr "type" "branch")]) 2846: 2847: (define_insn "" 2848: [(set (pc) 2849: (if_then_else (match_operator 0 "branch_operator" 1.1.1.3 root 2850: [(match_operand:SI 1 "gpc_reg_operand" "r") 1.1 root 2851: (const_int 0)]) 2852: (pc) 2853: (return)))] 2854: "null_epilogue ()" 2855: "jmp%B0i %1,lr0%#" 2856: [(set_attr "type" "branch")]) 2857: 2858: (define_insn "jump" 2859: [(set (pc) 2860: (label_ref (match_operand 0 "" "")))] 2861: "" 2862: "jmp %e0%E0" 2863: [(set_attr "type" "branch")]) 2864: 2865: (define_insn "return" 2866: [(return)] 2867: "null_epilogue ()" 2868: "jmpi lr0%#" 2869: [(set_attr "type" "branch")]) 2870: 2871: (define_insn "indirect_jump" 2872: [(set (pc) 1.1.1.3 root 2873: (match_operand:SI 0 "gpc_reg_operand" "r"))] 1.1 root 2874: "" 2875: "jmpi %0%#" 2876: [(set_attr "type" "branch")]) 2877: 2878: (define_insn "tablejump" 2879: [(set (pc) 1.1.1.3 root 2880: (match_operand:SI 0 "gpc_reg_operand" "r")) 1.1 root 2881: (use (label_ref (match_operand 1 "" "")))] 2882: "" 2883: "jmpi %0%#" 2884: [(set_attr "type" "branch")]) 2885: 2886: ;; JMPFDEC 2887: (define_insn "" 2888: [(set (pc) 1.1.1.3 root 2889: (if_then_else (ge (match_operand:SI 0 "gpc_reg_operand" "r") 1.1 root 2890: (const_int 0)) 2891: (label_ref (match_operand 1 "" "")) 2892: (pc))) 2893: (set (match_dup 0) 2894: (plus:SI (match_dup 0) 2895: (const_int -1)))] 2896: "" 2897: "jmpfdec %0,%l1%#" 2898: [(set_attr "type" "branch")]) 2899: 2900: ;;- Local variables: 2901: ;;- mode:emacs-lisp 2902: ;;- comment-start: ";;- " 2903: ;;- eval: (set-syntax-table (copy-sequence (syntax-table))) 2904: ;;- eval: (modify-syntax-entry ?[ "(]") 2905: ;;- eval: (modify-syntax-entry ?] ")[") 2906: ;;- eval: (modify-syntax-entry ?{ "(}") 2907: ;;- eval: (modify-syntax-entry ?} "){") 2908: ;;- End:
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