--- gcc/config/a29k/a29k.h 2018/04/24 18:15:30 1.1.1.2 +++ gcc/config/a29k/a29k.h 2018/04/24 18:21:47 1.1.1.3 @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for AMD Am29000 CPU. - Copyright (C) 1988, 1990, 1991, 1992, 1993 Free Software Foundation, Inc. + Copyright (C) 1988, 90, 91, 92, 93, 1994 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@nyu.edu) This file is part of GNU CC. @@ -85,6 +85,11 @@ extern int target_flags; #define TARGET_NO_REUSE_ARGS (target_flags & 256) +/* This means that neither builtin nor emulated float operations are + available, and that GCC should generate libcalls instead. */ + +#define TARGET_SOFT_FLOAT (target_flags & 512) + #define TARGET_SWITCHES \ { {"dw", 1}, \ {"ndw", -1}, \ @@ -103,21 +108,13 @@ extern int target_flags; {"no-storem-bug", 128}, \ {"reuse-arg-regs", -256}, \ {"no-reuse-arg-regs", 256}, \ + {"soft-float", 512}, \ {"", TARGET_DEFAULT}} #define TARGET_DEFAULT 3 -/* Define this to change the optimizations performed by default. */ - -#define OPTIMIZATION_OPTIONS(LEVEL) \ -{ \ - if ((LEVEL) > 0) \ - { \ - flag_force_addr = 1; \ - flag_force_mem = 1; \ - flag_omit_frame_pointer = 1; \ - } \ -} +/* Show we can debug even without a frame pointer. */ +#define CAN_DEBUG_WITHOUT_FP /* target machine storage layout */ @@ -292,7 +289,7 @@ extern int target_flags; #define R_EXO 199 /* Define the number for floating-point accumulator N. */ -#define R_ACC(N) ((N) + 200) +#define R_ACU(N) ((N) + 200) /* Now define the registers used in the calling sequence. */ #define R_TAV R_GR (121) @@ -390,7 +387,7 @@ extern int target_flags; R_LR (117), R_LR (118), R_LR (119), R_LR (120), R_LR (121), \ R_LR (122), R_LR (123), R_LR (124), R_LR (124), R_LR (126), \ R_LR (127), \ - R_ACC (3), R_ACC (2), R_ACC (1), R_ACC (0), \ + R_ACU (3), R_ACU (2), R_ACU (1), R_ACU (0), \ R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (121), \ R_GR (122), R_GR (123), R_GR (124), R_GR (125), R_GR (126), \ R_GR (127), \ @@ -411,7 +408,7 @@ extern int target_flags; but can be less for certain modes in special long registers. */ #define HARD_REGNO_NREGS(REGNO, MODE) \ - ((REGNO) >= R_ACC (0) && (REGNO) <= R_ACC (3)? 1 \ + ((REGNO) >= R_ACU (0) && (REGNO) <= R_ACU (3)? 1 \ : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. @@ -428,12 +425,12 @@ extern int target_flags; (I'd like to use the "?:" syntax to make this more readable, but Sun's compiler doesn't seem to accept it.) */ #define HARD_REGNO_MODE_OK(REGNO, MODE) \ -(((REGNO) >= R_ACC (0) && (REGNO) <= R_ACC (3) \ +(((REGNO) >= R_ACU (0) && (REGNO) <= R_ACU (3) \ && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)) \ || ((REGNO) >= R_BP && (REGNO) <= R_CR \ && GET_MODE_CLASS (MODE) == MODE_PARTIAL_INT) \ - || ((REGNO) >= R_Q && (REGNO) < R_ACC (0) \ + || ((REGNO) >= R_Q && (REGNO) < R_ACU (0) \ && GET_MODE_CLASS (MODE) != MODE_FLOAT \ && GET_MODE_CLASS (MODE) != MODE_COMPLEX_FLOAT) \ || (((REGNO) < R_BP || (REGNO) >= R_KR (0)) \ @@ -534,7 +531,7 @@ enum reg_class { NO_REGS, LR0_REGS, GENE #define REG_CLASS_CONTENTS \ { {0, 0, 0, 0, 0, 0, 0, 0}, \ {0, 1, 0, 0, 0, 0, 0, 0}, \ - {~0, ~0, ~0, ~0, ~0, ~ 0xfffe0000, ~ 0xfff, 0xfffff}, \ + {~0, ~0, ~0, ~0, ~0, ~ 0xfffe0000, ~ 0xfff, 0xfff}, \ {0, 0, 0, 0, 0, 0x20000, 0, 0}, \ {0, 0, 0, 0, 0, 0x40000, 0, 0}, \ {0, 0, 0, 0, 0, 0x80000, 0, 0}, \ @@ -542,8 +539,8 @@ enum reg_class { NO_REGS, LR0_REGS, GENE {0, 0, 0, 0, 0, 0xfffe0000, 0xff, 0}, \ {0, 0, 0, 0, 0, 0, 0x100, 0}, \ {0, 0, 0, 0, 0, 0, 0xf00, 0}, \ - {~0, ~0, ~0, ~0, ~0, ~ 0xfffe0000, ~ 0xff, ~0}, \ - {~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0} } + {~0, ~0, ~0, ~0, ~0, ~ 0xfffe0000, ~ 0xff, 0xfff}, \ + {~0, ~0, ~0, ~0, ~0, ~0, ~0, 0xfff} } /* The same information, inverted: Return the class number of the smallest class containing @@ -556,9 +553,9 @@ enum reg_class { NO_REGS, LR0_REGS, GENE : (REGNO) == R_CR ? CR_REGS \ : (REGNO) == R_Q ? Q_REGS \ : (REGNO) > R_BP && (REGNO) <= R_EXO ? SPECIAL_REGS \ - : (REGNO) == R_ACC (0) ? ACCUM0_REGS \ + : (REGNO) == R_ACU (0) ? ACCUM0_REGS \ : (REGNO) >= R_KR (0) ? GENERAL_REGS \ - : (REGNO) > R_ACC (0) ? ACCUM_REGS \ + : (REGNO) > R_ACU (0) ? ACCUM_REGS \ : (REGNO) == R_LR (0) ? LR0_REGS \ : GENERAL_REGS) @@ -670,6 +667,15 @@ extern struct rtx_def *a29k_get_reloaded #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ ((CLASS1) == GENERAL_REGS || (CLASS2) == GENERAL_REGS ? 2 : 4) +/* A C expressions returning the cost of moving data of MODE from a register to + or from memory. + + It takes extra insns on the 29k to form addresses, so we want to make + this higher. In addition, we need to keep it more expensive than the + most expensive register-register copy. */ + +#define MEMORY_MOVE_COST(MODE) 6 + /* A C statement (sans semicolon) to update the integer variable COST based on the relationship between INSN that is dependent on DEP_INSN through the dependence LINK. The default is to make no @@ -1624,6 +1630,7 @@ extern int a29k_debug_reg_map[]; {"spec_reg_operand", {REG}}, \ {"accum_reg_operand", {REG}}, \ {"srcb_operand", {SUBREG, REG, CONST_INT}}, \ + {"cmplsrcb_operand", {SUBREG, REG, CONST_INT}}, \ {"reg_or_immediate_operand", {SUBREG, REG, CONST_INT, CONST, \ CONST_DOUBLE, CONST, SYMBOL_REF, LABEL_REF}}, \ {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \