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1.1 root 1: ;;- Machine description for AMD Am29000 for GNU C compiler 1.1.1.3 ! root 2: ;; Copyright (C) 1991, 1992, 1994 Free Software Foundation, Inc. ! 3: ;; Contributed by Richard Kenner ([email protected]) 1.1 root 4: 5: ;; This file is part of GNU CC. 6: 7: ;; GNU CC is free software; you can redistribute it and/or modify 8: ;; it under the terms of the GNU General Public License as published by 9: ;; the Free Software Foundation; either version 2, or (at your option) 10: ;; any later version. 11: 12: ;; GNU CC is distributed in the hope that it will be useful, 13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15: ;; GNU General Public License for more details. 16: 17: ;; You should have received a copy of the GNU General Public License 18: ;; along with GNU CC; see the file COPYING. If not, write to 19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 20: 21: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 22: 23: ;; The insns in this file are presented in the same order as the AMD 29000 24: ;; User's Manual (i.e., alphabetical by machine op-code). 25: ;; 26: ;; DEFINE_EXPAND's are located near the first occurrence of the major insn 27: ;; that they generate. 28: 29: ;; The only attribute we have is the type. We only care about calls, branches, 30: ;; loads, stores, floating-point operations, and multi-word insns. 31: ;; Everything else is miscellaneous. 32: 33: (define_attr "type" 34: "call,branch,load,store,fadd,fmul,fam,fdiv,fsqrt,dmul,dam,ddiv,dsqrt,multi,misc" 35: (const_string "misc")) 36: 37: ;; ASM insns cannot go into a delay slot, so call them "multi". 38: (define_asm_attributes [(set_attr "type" "multi")]) 39: 40: (define_attr "in_delay_slot" "yes,no" 41: (if_then_else (eq_attr "type" "call,branch,multi") (const_string "no") 42: (const_string "yes"))) 43: 44: ;; Branch and call insns require a single delay slot. Annulling is not 45: ;; supported. 46: (define_delay (eq_attr "type" "call,branch") 47: [(eq_attr "in_delay_slot" "yes") (nil) (nil)]) 48: 49: ;; Define the function unit usages. We first define memory as a unit. 50: (define_function_unit "memory" 1 0 (eq_attr "type" "load") 6 5 51: [(eq_attr "type" "load")]) 52: (define_function_unit "memory" 1 0 (eq_attr "type" "load") 6 6 53: [(eq_attr "type" "store")]) 54: (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0) 55: 56: ;; Now define the function units for the floating-point support. Most 57: ;; units are pipelined and can accept an input every cycle. 58: ;; 59: ;; Note that we have an inaccuracy here. If a fmac insn is issued, followed 60: ;; 2 cycles later by a fadd, there will be a conflict for the floating 61: ;; adder that we can't represent. Also, all insns will conflict for the 62: ;; floating-point rounder. It isn't clear how to represent this. 63: 64: (define_function_unit "multiplier" 1 0 (eq_attr "type" "fmul") 3 0) 65: (define_function_unit "multiplier" 1 0 (eq_attr "type" "dmul") 6 4) 66: (define_function_unit "multiplier" 1 0 (eq_attr "type" "fam") 6 0) 67: (define_function_unit "multiplier" 1 0 (eq_attr "type" "dam") 9 4) 68: 69: (define_function_unit "adder" 1 0 (eq_attr "type" "fadd,fam,dam") 3 0) 70: 71: (define_function_unit "divider" 1 0 (eq_attr "type" "fdiv") 11 10) 72: (define_function_unit "divider" 1 0 (eq_attr "type" "fsqrt") 28 27) 73: (define_function_unit "divider" 1 0 (eq_attr "type" "ddiv") 18 17) 74: (define_function_unit "divider" 1 0 (eq_attr "type" "dsqrt") 57 56) 75: 76: ;; ADD 77: (define_insn "addsi3" 78: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 79: (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 80: (match_operand:SI 2 "add_operand" "rI,N")))] 81: "" 82: "@ 83: add %0,%1,%2 84: sub %0,%1,%n2") 85: 86: (define_insn "adddi3" 87: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 88: (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r") 89: (match_operand:DI 2 "gpc_reg_operand" "r")))] 90: "" 91: "add %L0,%L1,%L2\;addc %0,%1,%2" 92: [(set_attr "type" "multi")]) 93: 94: ;; AND/ANDN 95: (define_insn "andsi3" 96: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 97: (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 98: (match_operand:SI 2 "and_operand" "rI,K")))] 99: "" 100: "@ 101: and %0,%1,%2 102: andn %0,%1,%C2") 103: 104: (define_insn "" 1.1.1.3 ! root 105: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 106: (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) ! 107: (match_operand:SI 2 "cmplsrcb_operand" "r,K")))] 1.1 root 108: "" 1.1.1.3 ! root 109: "@ ! 110: andn %0,%2,%1 ! 111: nor %0,%1,%C2") 1.1 root 112: 113: ;; CALLI 114: ;; 1.1.1.3 ! root 115: ;; Each call pattern is duplicated so that we can add CLOBBERs to the ! 116: ;; resulting insn. ! 117: ;; ! 118: ;; We indicate that LR0 is clobbered in the CALL_INSN itself. Otherwise, ! 119: ;; reorg will think it is just clobbered by the called function. ! 120: ! 121: (define_expand "call" ! 122: [(use (match_operand:SI 0 "" "")) ! 123: (use (match_operand 1 "" "")) ! 124: (use (match_operand 2 "" ""))] 1.1 root 125: "" 126: " 1.1.1.3 ! root 127: { rtx insn = emit_call_insn (gen_call_internal (operands[0], operands[1])); ! 128: a29k_clobbers_to (insn, operands[2]); 1.1 root 129: 130: DONE; 131: }") 1.1.1.3 ! root 132: ! 133: (define_expand "call_internal" 1.1 root 134: [(parallel [(call (match_operand:SI 0 "" "") 135: (match_operand 1 "" "")) 1.1.1.3 ! root 136: (clobber (scratch:SI))])] 1.1 root 137: "" 138: " 139: { 140: if (GET_CODE (operands[0]) != MEM) 141: abort (); 142: 143: /* We tell here whether this is a recursive call, since this insn may 144: later be inlined into another function. */ 145: if (! TARGET_SMALL_MEMORY 146: && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) 147: operands[0] = gen_rtx (MEM, SImode, 148: force_reg (Pmode, XEXP (operands[0], 0))); 149: }") 150: 151: (define_expand "call_value" 1.1.1.3 ! root 152: [(use (match_operand:SI 0 "gpc_reg_operand" "")) ! 153: (use (match_operand:SI 1 "" "")) ! 154: (use (match_operand 2 "" "")) ! 155: (use (match_operand 3 "" ""))] ! 156: "" ! 157: " ! 158: { rtx insn = emit_call_insn (gen_call_value_internal (operands[0], operands[1], ! 159: operands[2])); ! 160: ! 161: a29k_clobbers_to (insn, operands[3]); ! 162: DONE; ! 163: }") ! 164: ! 165: (define_expand "call_value_internal" 1.1 root 166: [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 167: (call (match_operand:SI 1 "" "") 168: (match_operand 2 "" ""))) 1.1.1.3 ! root 169: (clobber (scratch:SI))])] 1.1 root 170: "" 171: " 172: { 173: if (GET_CODE (operands[1]) != MEM) 174: abort (); 175: 176: /* We tell here whether this is a recursive call, since this insn may 177: later be inlined into another function. */ 178: if (! TARGET_SMALL_MEMORY 179: && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) 180: operands[1] = gen_rtx (MEM, SImode, 181: force_reg (Pmode, XEXP (operands[1], 0))); 182: 183: }") 184: 185: (define_insn "" 186: [(call (match_operand:SI 0 "memory_operand" "m") 187: (match_operand 1 "" "")) 188: (clobber (match_scratch:SI 2 "=&l"))] 189: "GET_CODE (XEXP (operands[0], 0)) != CONST_INT" 190: "calli lr0,%0%#" 191: [(set_attr "type" "call")]) 192: 193: (define_insn "" 194: [(call (mem:SI (match_operand:SI 0 "call_operand" "i")) 195: (match_operand:SI 1 "general_operand" "g")) 196: (clobber (match_scratch:SI 2 "=&l"))] 197: "" 198: "call lr0,%F0" 199: [(set_attr "type" "call")]) 200: 201: (define_insn "" 202: [(set (match_operand 0 "gpc_reg_operand" "=r") 203: (call (match_operand:SI 1 "memory_operand" "m") 204: (match_operand 2 "" ""))) 205: (clobber (match_scratch:SI 3 "=&l"))] 206: "GET_CODE (XEXP (operands[1], 0)) != CONST_INT" 207: "calli lr0,%1%#" 208: [(set_attr "type" "call")]) 209: 210: (define_insn "" 211: [(set (match_operand 0 "gpc_reg_operand" "=r") 212: (call (mem:SI (match_operand:SI 1 "call_operand" "i")) 213: (match_operand:SI 2 "general_operand" "g"))) 214: (clobber (match_scratch:SI 3 "=&l"))] 215: "" 216: "call lr0,%F1" 217: [(set_attr "type" "call")]) 218: 219: (define_expand "probe" 220: [(call (mem:SI (symbol_ref:SI "_msp_check")) 221: (const_int 1))] 222: "TARGET_STACK_CHECK" 223: "") 224: 225: ;; This is used for internal routine calls via TPC. Currently used only 226: ;; in probe, above. 227: (define_insn "" 228: [(call (mem:SI (match_operand:SI 0 "immediate_operand" "s")) 229: (const_int 1))] 230: "" 231: "call %*,%0" 232: [(set_attr "type" "call")]) 233: 234: ;; CONST, CONSTH, CONSTN 235: ;; 236: ;; Many of these are generated from move insns. 237: (define_insn "" 238: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 239: (and:SI (match_operand:SI 1 "immediate_operand" "i") 240: (const_int 65535)))] 241: "" 242: "const %0,%1") 243: 244: (define_insn "" 245: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 246: (const_int 16) 247: (match_operand:SI 1 "const_0_operand" "")) 248: (ashiftrt:SI (match_operand:SI 2 "immediate_operand" "i") 249: (const_int 16)))] 250: "" 251: "consth %0,%2") 252: 253: (define_insn "" 254: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 255: (const_int 16) 256: (match_operand:SI 1 "const_0_operand" "")) 257: (match_operand:SI 2 "cint_16_operand" "J"))] 258: "" 259: "consth %0,%m2") 260: 261: (define_insn "" 262: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 263: (ior:SI (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "0")) 264: (match_operand:SI 2 "const_int_operand" "n")))] 265: "(INTVAL (operands[2]) & 0xffff) == 0" 266: "consth %0,%2") 267: 268: (define_insn "" 269: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 270: (ior:SI (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "0")) 271: (and:SI (match_operand:SI 2 "immediate_operand" "i") 272: (const_int -65536))))] 273: "" 274: "consth %0,%2") 275: 276: ;; CONVERT 277: (define_insn "fix_truncsfsi2" 278: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 279: (fix:SI (match_operand:SF 1 "register_operand" "r")))] 1.1.1.3 ! root 280: "! TARGET_SOFT_FLOAT" 1.1 root 281: "convert %0,%1,0,3,0,1") 282: 283: (define_insn "fix_truncdfsi2" 284: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 285: (fix:SI (match_operand:DF 1 "register_operand" "r")))] 1.1.1.3 ! root 286: "! TARGET_SOFT_FLOAT" 1.1 root 287: "convert %0,%1,0,3,0,2") 288: 289: (define_insn "fixuns_truncsfsi2" 290: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 291: (unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))] 1.1.1.3 ! root 292: "! TARGET_SOFT_FLOAT" 1.1 root 293: "convert %0,%1,1,3,0,1") 294: 295: (define_insn "fixuns_truncdfsi2" 296: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 297: (unsigned_fix:SI (match_operand:DF 1 "register_operand" "r")))] 1.1.1.3 ! root 298: "! TARGET_SOFT_FLOAT" 1.1 root 299: "convert %0,%1,1,3,0,2") 300: 301: (define_insn "truncdfsf2" 302: [(set (match_operand:SF 0 "register_operand" "=r") 303: (float_truncate:SF (match_operand:DF 1 "register_operand" "r")))] 1.1.1.3 ! root 304: "! TARGET_SOFT_FLOAT" 1.1 root 305: "convert %0,%1,0,4,1,2") 306: 307: (define_insn "extendsfdf2" 308: [(set (match_operand:DF 0 "register_operand" "=r") 309: (float_extend:DF (match_operand:SF 1 "register_operand" "r")))] 1.1.1.3 ! root 310: "! TARGET_SOFT_FLOAT" 1.1 root 311: "convert %0,%1,0,4,2,1") 312: 313: (define_insn "floatsisf2" 314: [(set (match_operand:SF 0 "register_operand" "=r") 315: (float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))] 1.1.1.3 ! root 316: "! TARGET_SOFT_FLOAT" 1.1 root 317: "convert %0,%1,0,4,1,0") 318: 319: (define_insn "floatsidf2" 320: [(set (match_operand:DF 0 "register_operand" "=r") 321: (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))] 1.1.1.3 ! root 322: "! TARGET_SOFT_FLOAT" 1.1 root 323: "convert %0,%1,0,4,2,0") 324: 325: (define_insn "floatunssisf2" 326: [(set (match_operand:SF 0 "register_operand" "=r") 327: (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))] 1.1.1.3 ! root 328: "! TARGET_SOFT_FLOAT" 1.1 root 329: "convert %0,%1,1,4,1,0") 330: 331: (define_insn "floatunssidf2" 332: [(set (match_operand:DF 0 "register_operand" "=r") 333: (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))] 1.1.1.3 ! root 334: "! TARGET_SOFT_FLOAT" 1.1 root 335: "convert %0,%1,1,4,2,0") 336: 337: ;; CPxxx, DEQ, DGT, DGE, FEQ, FGT, FGE 338: (define_insn "" 339: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 340: (match_operator 3 "comparison_operator" 341: [(match_operand:SI 1 "gpc_reg_operand" "r") 342: (match_operand:SI 2 "srcb_operand" "rI")]))] 343: "" 344: "cp%J3 %0,%1,%2") 345: 346: (define_insn "" 347: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 348: (match_operator 3 "fp_comparison_operator" 349: [(match_operand:SF 1 "register_operand" "r") 350: (match_operand:SF 2 "register_operand" "r")]))] 1.1.1.3 ! root 351: "! TARGET_SOFT_FLOAT" 1.1 root 352: "f%J3 %0,%1,%2" 353: [(set_attr "type" "fadd")]) 354: 355: (define_insn "" 356: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 357: (match_operator 3 "fp_comparison_operator" 358: [(match_operand:DF 1 "register_operand" "r") 359: (match_operand:DF 2 "register_operand" "r")]))] 1.1.1.3 ! root 360: "! TARGET_SOFT_FLOAT" 1.1 root 361: "d%J3 %0,%1,%2" 362: [(set_attr "type" "fadd")]) 363: 364: ;; DADD 365: (define_expand "adddf3" 366: [(set (match_operand:DF 0 "register_operand" "") 367: (plus:DF (match_operand:DF 1 "register_operand" "") 368: (match_operand:DF 2 "register_operand" "")))] 1.1.1.3 ! root 369: "! TARGET_SOFT_FLOAT" 1.1 root 370: "") 371: 372: (define_insn "" 373: [(set (match_operand:DF 0 "register_operand" "=r") 374: (plus:DF (match_operand:DF 1 "register_operand" "%r") 375: (match_operand:DF 2 "register_operand" "r")))] 376: "! TARGET_29050 " 377: "dadd %0,%1,%2" 378: [(set_attr "type" "fadd")]) 379: 380: (define_insn "" 381: [(set (match_operand:DF 0 "register_operand" "=r,a") 382: (plus:DF (match_operand:DF 1 "register_operand" "%r,r") 383: (match_operand:DF 2 "register_operand" "r,0")))] 384: "TARGET_29050" 385: "@ 386: dadd %0,%1,%2 387: dmac 8,%0,%1,%1" 388: [(set_attr "type" "fadd,dam")]) 389: 390: ;; DDIV 391: (define_insn "divdf3" 392: [(set (match_operand:DF 0 "register_operand" "=r") 393: (div:DF (match_operand:DF 1 "register_operand" "=r") 394: (match_operand:DF 2 "register_operand" "r")))] 1.1.1.3 ! root 395: "! TARGET_SOFT_FLOAT" 1.1 root 396: "ddiv %0,%1,%2" 397: [(set_attr "type" "ddiv")]) 398: 399: ;; DIVIDE 400: ;; 401: ;; We must set Q to the sign extension of the dividend first. For MOD, we 402: ;; must get the remainder from Q. 403: ;; 404: ;; For divmod: operand 1 is divided by operand 2; quotient goes to operand 405: ;; 0 and remainder to operand 3. 406: (define_expand "divmodsi4" 407: [(set (match_dup 4) 408: (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 409: (const_int 31))) 410: (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 411: (div:SI (match_dup 1) 412: (match_operand:SI 2 "gpc_reg_operand" ""))) 413: (set (match_operand:SI 3 "gpc_reg_operand" "") 414: (mod:SI (match_dup 1) 415: (match_dup 2))) 416: (use (match_dup 4))])] 417: "" 418: " 419: { 420: operands[4] = gen_reg_rtx (SImode); 421: }") 422: 423: (define_insn "" 424: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 425: (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 426: (match_operand:SI 2 "gpc_reg_operand" "r"))) 427: (set (match_operand:SI 3 "register_operand" "=q") 428: (mod:SI (match_dup 1) 429: (match_dup 2))) 430: (use (match_operand:SI 4 "register_operand" "3"))] 431: "" 432: "divide %0,%1,%2") 433: 434: ;; DIVIDU 435: ;; 436: ;; Similar to DIVIDE. 437: (define_expand "udivmodsi4" 438: [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 439: (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") 440: (match_operand:SI 2 "gpc_reg_operand" ""))) 441: (set (match_operand:SI 3 "gpc_reg_operand" "") 442: (umod:SI (match_dup 1) 443: (match_dup 2))) 444: (use (const_int 0))])] 445: "" 446: "") 447: 448: (define_insn "" 449: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 450: (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") 451: (match_operand:SI 2 "gpc_reg_operand" "r"))) 452: (set (match_operand:SI 3 "register_operand" "=q") 453: (umod:SI (match_dup 1) 454: (match_dup 2))) 455: (use (match_operand:SI 4 "const_int_operand" "3"))] 456: "" 457: "dividu %0,%1,%2") 458: 459: ;; DMAC/DMSM 460: (define_insn "" 461: [(set (match_operand:DF 0 "register_operand" "=a,*r") 462: (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%r,A") 463: (match_operand:DF 2 "register_operand" "r,r")) 464: (match_operand:DF 3 "register_operand" "0,*r")))] 465: "TARGET_29050" 466: "@ 467: dmac 0,%0,%1,%2 468: dmsm %0,%2,%3" 469: [(set_attr "type" "dam")]) 470: 471: (define_insn "" 472: [(set (match_operand:DF 0 "register_operand" "=a") 473: (plus:DF (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "r")) 474: (match_operand:DF 2 "register_operand" "r")) 475: (match_operand:DF 3 "register_operand" "0")))] 476: "TARGET_29050" 477: "dmac 1,%0,%2,%1" 478: [(set_attr "type" "dam")]) 479: 480: (define_insn "" 481: [(set (match_operand:DF 0 "register_operand" "=a") 482: (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "%r") 483: (match_operand:DF 2 "register_operand" "r")) 484: (match_operand:DF 3 "register_operand" "0")))] 485: "TARGET_29050" 486: "dmac 2,%0,%1,%2" 487: [(set_attr "type" "dam")]) 488: 489: (define_insn "" 490: [(set (match_operand:DF 0 "register_operand" "=a") 491: (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "r") 492: (neg:DF (match_operand:DF 2 "register_operand" "r"))) 493: (match_operand:DF 3 "register_operand" "0")))] 494: "TARGET_29050" 495: "dmac 3,%0,%1,%2" 496: [(set_attr "type" "dam")]) 497: 498: (define_insn "" 499: [(set (match_operand:DF 0 "register_operand" "=a") 500: (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "r")) 501: (match_operand:DF 2 "register_operand" "r")))] 502: "TARGET_29050" 503: "dmac 5,%0,%2,%1" 504: [(set_attr "type" "dam")]) 505: 506: (define_insn "" 507: [(set (match_operand:DF 0 "register_operand" "=a") 508: (minus:DF (neg:DF (match_operand:DF 1 "register_operand" "r")) 509: (match_operand:DF 2 "register_operand" "0")))] 510: "TARGET_29050" 511: "dmac 11,%0,%1,%1" 512: [(set_attr "type" "dam")]) 513: 514: (define_insn "" 515: [(set (match_operand:DF 0 "register_operand" "=a") 516: (neg:DF (plus:DF (match_operand:DF 1 "register_operand" "%r") 517: (match_operand:DF 2 "register_operand" "0"))))] 518: "TARGET_29050" 519: "dmac 11,%0,%1,%1" 520: [(set_attr "type" "dam")]) 521: 522: (define_insn "" 523: [(set (match_operand:DF 0 "register_operand" "=r,r,a") 524: (neg:DF (match_operand:DF 1 "register_operand" "0,r,r"))) 525: (clobber (match_scratch:SI 2 "=&r,&r,X"))] 526: "TARGET_29050" 527: "@ 528: cpeq %2,gr1,gr1\;xor %0,%1,%2 529: cpeq %2,gr1,gr1\;xor %0,%1,%2\;sll %L0,%L1,0 530: dmac 13,%0,%1,%1" 531: [(set_attr "type" "multi,multi,dam")]) 532: 533: ;; DMUL 534: (define_expand "muldf3" 535: [(set (match_operand:DF 0 "register_operand" "") 536: (mult:DF (match_operand:DF 1 "register_operand" "") 537: (match_operand:DF 2 "register_operand" "")))] 1.1.1.3 ! root 538: "! TARGET_SOFT_FLOAT" 1.1 root 539: "") 540: 541: (define_insn "" 542: [(set (match_operand:DF 0 "register_operand" "=r") 543: (mult:DF (match_operand:DF 1 "register_operand" "%r") 544: (match_operand:DF 2 "register_operand" "r")))] 545: "! TARGET_29050" 546: "dmul %0,%1,%2" 547: [(set_attr "type" "dmul")]) 548: 549: (define_insn "" 550: [(set (match_operand:DF 0 "register_operand" "=r,a") 551: (mult:DF (match_operand:DF 1 "register_operand" "%r,r") 552: (match_operand:DF 2 "register_operand" "r,r")))] 553: "TARGET_29050" 554: "@ 555: dmul %0,%1,%2 556: dmac 4,%0,%1,%2" 557: [(set_attr "type" "dmul,dam")]) 558: 559: ;; DSUB 560: (define_expand "subdf3" 561: [(set (match_operand:DF 0 "register_operand" "=r") 562: (minus:DF (match_operand:DF 1 "register_operand" "r") 563: (match_operand:DF 2 "register_operand" "r")))] 1.1.1.3 ! root 564: "! TARGET_SOFT_FLOAT" 1.1 root 565: "") 566: 567: (define_insn "" 568: [(set (match_operand:DF 0 "register_operand" "=r") 569: (minus:DF (match_operand:DF 1 "register_operand" "r") 570: (match_operand:DF 2 "register_operand" "r")))] 571: "! TARGET_29050" 572: "dsub %0,%1,%2" 573: [(set_attr "type" "fadd")]) 574: 575: (define_insn "" 576: [(set (match_operand:DF 0 "register_operand" "=r,a,a") 577: (minus:DF (match_operand:DF 1 "register_operand" "r,0,r") 578: (match_operand:DF 2 "register_operand" "r,r,0")))] 579: "TARGET_29050" 580: "@ 581: dsub %0,%1,%2 582: dmac 9,%0,%2,%2 583: dmac 10,%0,%1,%1" 584: [(set_attr "type" "fadd,dam,dam")]) 585: 586: ;; EXBYTE 587: (define_insn "" 588: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 589: (ior:SI (and:SI (match_operand:SI 1 "srcb_operand" "rI") 590: (const_int -256)) 591: (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") 592: (const_int 8) 593: (ashift:PSI 594: (match_operand:PSI 3 "register_operand" "b") 595: (const_int 3)))))] 596: "" 597: "exbyte %0,%2,%1") 598: 599: (define_insn "" 600: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 601: (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") 602: (const_int 8) 603: (ashift:PSI 604: (match_operand:PSI 2 "register_operand" "b") 605: (const_int 3))))] 606: "" 607: "exbyte %0,%1,0") 608: 609: (define_insn "" 610: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 611: (const_int 8) 612: (match_operand:PSI 1 "const_24_operand" "")) 613: (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") 614: (const_int 8) 615: (ashift:PSI 616: (match_operand:PSI 3 "register_operand" "b") 617: (const_int 3))))] 618: "" 619: "exbyte %0,%2,%0") 620: 621: (define_expand "extzv" 622: [(set (match_operand:SI 0 "gpc_reg_operand" "") 623: (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") 624: (match_operand:SI 2 "general_operand" "") 625: (match_operand:SI 3 "general_operand" "")))] 626: "" 627: " 628: { 629: int size, pos; 630: 631: if (GET_CODE (operands[2]) != CONST_INT 632: || GET_CODE (operands[3]) != CONST_INT) 633: FAIL; 634: 635: size = INTVAL (operands[2]); 636: pos = INTVAL (operands[3]); 637: 638: /* Can't do this unless a byte extraction. If extracting the high 639: or low byte, don't do this because a shift or AND is shorter. 640: Don't do 16-bit extracts, since the only two are the high and low 641: ends, and it is faster to do them with CONSTH and SRL. */ 642: 643: if (size != 8 || (pos != 8 && pos != 16)) 644: FAIL; 645: 646: operands[3] = gen_rtx (ASHIFT, PSImode, 647: force_reg (PSImode, GEN_INT (pos / 8)), 648: GEN_INT (3)); 649: 650: }") 651: 652: ;; EXHW 653: (define_insn "" 654: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 655: (ior:SI (and:SI (match_operand:SI 1 "srcb_operand" "rI") 656: (const_int -65536)) 657: (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") 658: (const_int 16) 659: (ashift:PSI 660: (match_operand:PSI 3 "register_operand" "b") 661: (const_int 3)))))] 662: "" 663: "exhw %0,%2,%1") 664: 665: (define_insn "" 666: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 667: (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") 668: (const_int 16) 669: (ashift:PSI 670: (match_operand:PSI 2 "register_operand" "b") 671: (const_int 3))))] 672: "" 673: "exhw %0,%1,0") 674: 675: (define_insn "" 676: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 677: (const_int 16) 678: (match_operand:PSI 1 "const_16_operand" "")) 679: (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") 680: (const_int 16) 681: (ashift:PSI 682: (match_operand:PSI 3 "register_operand" "b") 683: (const_int 3))))] 684: "" 685: "exhw %0,%2,%0") 686: 687: ;; EXHWS 688: ;; 689: ;; This is probably unused. The high-order 16-bits are obtained with an SRA 690: ;; insn. The low-order 16 bits are a sign-extend, which is a pair of 691: ;; shifts. Setting BP followed by the insn is equivalent, so we don't 692: ;; bother going to any trouble to generate this insn. 693: 694: (define_insn "" 695: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 696: (sign_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") 697: (const_int 16) 698: (ashift:PSI 699: (match_operand:PSI 2 "register_operand" "b") 700: (const_int 3))))] 701: "" 702: "exhws %0,%1") 703: 704: ;; EXTRACT 705: (define_insn "" 706: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 707: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 708: (match_operand:PSI 2 "register_operand" "f")))] 709: "" 710: "extract %0,%1,%1") 711: 712: (define_expand "rotlsi3" 713: [(set (match_dup 3) 714: (match_operand:SI 2 "gpc_reg_or_immediate_operand" "")) 715: (set (match_operand:SI 0 "gpc_reg_operand" "") 716: (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 717: (match_dup 3)))] 718: "" 719: " 720: { operands[2] = gen_lowpart (PSImode, operands[2]); 721: operands[3] = gen_reg_rtx (PSImode); 722: }") 723: 724: ;; It would be nice to be able to have a define_split corresponding to the 725: ;; above, but there is no way to tell combine we need a PSImode temporary. 726: ;; If we put a (clobber (scratch:PSI)) there, combine would merge the above 727: ;; two insns. This is bad because it then thinks only one insn is needed. 728: 729: ;; FADD 730: (define_expand "addsf3" 731: [(set (match_operand:SF 0 "register_operand" "") 732: (plus:SF (match_operand:SF 1 "register_operand" "") 733: (match_operand:SF 2 "register_operand" "")))] 1.1.1.3 ! root 734: "! TARGET_SOFT_FLOAT" 1.1 root 735: "") 736: 737: (define_insn "" 738: [(set (match_operand:SF 0 "register_operand" "=r") 739: (plus:SF (match_operand:SF 1 "register_operand" "%r") 740: (match_operand:SF 2 "register_operand" "r")))] 741: "! TARGET_29050" 742: "fadd %0,%1,%2" 743: [(set_attr "type" "fadd")]) 744: 745: (define_insn "" 746: [(set (match_operand:SF 0 "register_operand" "=r,a") 747: (plus:SF (match_operand:SF 1 "register_operand" "%r,r") 748: (match_operand:SF 2 "register_operand" "r,0")))] 749: "TARGET_29050" 750: "@ 751: fadd %0,%1,%2 752: fmac 8,%0,%1,%1" 753: [(set_attr "type" "fadd,fam")]) 754: 755: ;; FDIV 756: (define_insn "divsf3" 757: [(set (match_operand:SF 0 "register_operand" "=r") 758: (div:SF (match_operand:SF 1 "register_operand" "=r") 759: (match_operand:SF 2 "register_operand" "r")))] 1.1.1.3 ! root 760: "! TARGET_SOFT_FLOAT" 1.1 root 761: "fdiv %0,%1,%2" 762: [(set_attr "type" "fdiv")]) 763: 764: ;; FDMUL 765: (define_insn "" 766: [(set (match_operand:DF 0 "register_operand" "=r") 767: (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "%r")) 768: (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))] 1.1.1.3 ! root 769: "! TARGET_SOFT_FLOAT" 1.1 root 770: "fdmul %0,%1,%2") 771: 772: ;; FMAC/FMSM 773: (define_insn "" 774: [(set (match_operand:SF 0 "register_operand" "=a,*r") 775: (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%r,A") 776: (match_operand:SF 2 "register_operand" "r,r")) 777: (match_operand:SF 3 "register_operand" "0,*r")))] 778: "TARGET_29050" 779: "@ 780: fmac 0,%0,%1,%2 781: fmsm %0,%2,%3" 782: [(set_attr "type" "fam")]) 783: 784: (define_insn "" 785: [(set (match_operand:SF 0 "register_operand" "=a") 786: (plus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r")) 787: (match_operand:SF 2 "register_operand" "r")) 788: (match_operand:SF 3 "register_operand" "0")))] 789: "TARGET_29050" 790: "fmac 1,%0,%2,%1" 791: [(set_attr "type" "fam")]) 792: 793: (define_insn "" 794: [(set (match_operand:SF 0 "register_operand" "=a") 795: (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "%r") 796: (match_operand:SF 2 "register_operand" "r")) 797: (match_operand:SF 3 "register_operand" "0")))] 798: "TARGET_29050" 799: "fmac 2,%0,%1,%2" 800: [(set_attr "type" "fam")]) 801: 802: (define_insn "" 803: [(set (match_operand:SF 0 "register_operand" "=a") 804: (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r")) 805: (match_operand:SF 2 "register_operand" "r")) 806: (match_operand:SF 3 "register_operand" "0")))] 807: "TARGET_29050" 808: "fmac 3,%0,%2,%1" 809: [(set_attr "type" "fam")]) 810: 811: (define_insn "" 812: [(set (match_operand:SF 0 "register_operand" "=a") 813: (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r")) 814: (match_operand:SF 2 "register_operand" "r")))] 815: "TARGET_29050" 816: "fmac 5,%0,%2,%1" 817: [(set_attr "type" "fam")]) 818: 819: (define_insn "" 820: [(set (match_operand:SF 0 "register_operand" "=a") 821: (minus:SF (neg:SF (match_operand:SF 1 "register_operand" "%r")) 822: (match_operand:SF 2 "register_operand" "0")))] 823: "TARGET_29050" 824: "fmac 11,%0,%1,%1" 825: [(set_attr "type" "fam")]) 826: 827: (define_insn "" 828: [(set (match_operand:SF 0 "register_operand" "=a") 829: (neg:SF (plus:SF (match_operand:SF 1 "register_operand" "%r") 830: (match_operand:SF 2 "register_operand" "0"))))] 831: "TARGET_29050" 832: "fmac 11,%0,%1,%1" 833: [(set_attr "type" "fam")]) 834: 835: (define_insn "" 836: [(set (match_operand:SF 0 "register_operand" "=r,a") 837: (neg:SF (match_operand:SF 1 "register_operand" "r,r"))) 838: (clobber (match_scratch:SI 2 "=&r,X"))] 839: "TARGET_29050" 840: "@ 841: cpeq %2,gr1,gr1\;xor %0,%1,%2 842: fmac 13,%0,%1,%1" 843: [(set_attr "type" "multi,fam")]) 844: 845: ;; FMUL 846: (define_expand "mulsf3" 847: [(set (match_operand:SF 0 "register_operand" "") 848: (mult:SF (match_operand:SF 1 "register_operand" "") 849: (match_operand:SF 2 "register_operand" "")))] 1.1.1.3 ! root 850: "! TARGET_SOFT_FLOAT" 1.1 root 851: "") 852: 853: (define_insn "" 854: [(set (match_operand:SF 0 "register_operand" "=r") 855: (mult:SF (match_operand:SF 1 "register_operand" "%r") 856: (match_operand:SF 2 "register_operand" "r")))] 857: "! TARGET_29050" 858: "fmul %0,%1,%2" 859: [(set_attr "type" "fmul")]) 860: 861: (define_insn "" 862: [(set (match_operand:SF 0 "register_operand" "=r,a") 863: (mult:SF (match_operand:SF 1 "register_operand" "%r,r") 864: (match_operand:SF 2 "register_operand" "r,r")))] 865: "TARGET_29050" 866: "@ 867: fmul %0,%1,%2 868: fmac 4,%0,%1,%2" 869: [(set_attr "type" "fmul,fam")]) 870: 871: ;; FSUB 872: (define_expand "subsf3" 873: [(set (match_operand:SF 0 "register_operand" "") 874: (minus:SF (match_operand:SF 1 "register_operand" "") 875: (match_operand:SF 2 "register_operand" "")))] 1.1.1.3 ! root 876: "! TARGET_SOFT_FLOAT" 1.1 root 877: "") 878: 879: (define_insn "" 880: [(set (match_operand:SF 0 "register_operand" "=r") 881: (minus:SF (match_operand:SF 1 "register_operand" "r") 882: (match_operand:SF 2 "register_operand" "r")))] 883: "! TARGET_29050" 884: "fsub %0,%1,%2" 885: [(set_attr "type" "fadd")]) 886: 887: (define_insn "" 888: [(set (match_operand:SF 0 "register_operand" "=r,a,a") 889: (minus:SF (match_operand:SF 1 "register_operand" "r,0,r") 890: (match_operand:SF 2 "register_operand" "r,r,0")))] 891: "TARGET_29050" 892: "@ 893: fsub %0,%1,%2 894: fmac 9,%0,%2,%2 895: fmac 10,%0,%1,%1" 896: [(set_attr "type" "fadd,fam,fam")]) 897: 898: ;; INBYTE 899: (define_insn "" 900: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 901: (const_int 8) 902: (ashift:PSI 903: (match_operand:PSI 2 "register_operand" "b") 904: (const_int 3))) 905: (match_operand:SI 1 "srcb_operand" "rI"))] 906: "" 907: "inbyte %0,%0,%1") 908: 909: (define_insn "" 910: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 911: (ior:SI (and:SI 912: (not:SI 913: (ashift:SI (const_int 255) 914: (ashift:PSI 915: (match_operand:PSI 3 "register_operand" "b") 916: (const_int 3)))) 917: (match_operand:SI 1 "gpc_reg_operand" "r")) 918: (ashift:SI (zero_extend:SI 919: (match_operand:QI 2 "srcb_operand" "rI")) 920: (ashift:PSI (match_dup 3) (const_int 3)))))] 921: "" 922: "inbyte %0,%1,%2") 923: 924: ;; INHW 925: (define_insn "" 926: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 927: (const_int 16) 928: (ashift:PSI 929: (match_operand:PSI 2 "register_operand" "b") 930: (const_int 3))) 931: (match_operand:SI 1 "srcb_operand" "rI"))] 932: "" 933: "inhw %0,%0,%1") 934: 935: (define_insn "" 936: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 937: (ior:SI (and:SI 938: (not:SI 939: (ashift:SI (const_int 65535) 940: (ashift:PSI 941: (match_operand:PSI 3 "register_operand" "b") 942: (const_int 3)))) 943: (match_operand:SI 1 "gpc_reg_operand" "r")) 944: (ashift:SI (zero_extend:SI 945: (match_operand:HI 2 "srcb_operand" "rI")) 946: (ashift:PSI (match_dup 3) (const_int 3)))))] 947: "" 948: "inhw %0,%1,%2") 949: 950: (define_expand "insv" 951: [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "") 952: (match_operand:SI 1 "general_operand" "") 953: (match_operand:SI 2 "general_operand" "")) 954: (match_operand:SI 3 "srcb_operand" ""))] 955: "" 956: " 957: { 958: int size, pos; 959: 960: if (GET_CODE (operands[1]) != CONST_INT 961: || GET_CODE (operands[2]) != CONST_INT) 962: FAIL; 963: 964: size = INTVAL (operands[1]); 965: pos = INTVAL (operands[2]); 966: if ((size != 8 && size != 16) || pos % size != 0) 967: FAIL; 968: 969: operands[2] = gen_rtx (ASHIFT, PSImode, 970: force_reg (PSImode, GEN_INT (pos / 8)), 971: GEN_INT (3)); 972: }") 973: 974: ;; LOAD (also used by move insn). 975: (define_insn "" 976: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 977: (mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "r") 978: (const_int -4)))) 979: (set (match_operand:PSI 2 "register_operand" "=b") 980: (truncate:PSI (match_dup 1)))] 981: "! TARGET_DW_ENABLE" 982: "load 0,16,%0,%1" 983: [(set_attr "type" "load")]) 984: 985: (define_insn "" 986: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 987: (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] 988: "TARGET_DW_ENABLE" 989: "load 0,1,%0,%1" 990: [(set_attr "type" "load")]) 991: 992: (define_insn "" 993: [(set (match_operand:HI 0 "gpc_reg_operand" "=r") 994: (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] 995: "TARGET_DW_ENABLE" 996: "load 0,1,%0,%1" 997: [(set_attr "type" "load")]) 998: 999: (define_insn "" 1000: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1001: (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] 1002: "TARGET_DW_ENABLE" 1003: "load 0,2,%0,%1" 1004: [(set_attr "type" "load")]) 1005: 1006: (define_insn "" 1007: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1008: (sign_extend:SI (match_operand:QI 1 "memory_operand" "m"))) 1009: (clobber (match_scratch:PSI 2 "=&b"))] 1010: "TARGET_DW_ENABLE" 1011: "load 0,17,%0,%1" 1012: [(set_attr "type" "load")]) 1013: 1014: (define_insn "" 1015: [(set (match_operand:HI 0 "gpc_reg_operand" "=r") 1016: (sign_extend:HI (match_operand:QI 1 "memory_operand" "m"))) 1017: (clobber (match_scratch:PSI 2 "=&b"))] 1018: "TARGET_DW_ENABLE" 1019: "load 0,17,%0,%1" 1020: [(set_attr "type" "load")]) 1021: 1022: (define_insn "" 1023: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1024: (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))) 1025: (clobber (match_scratch:PSI 2 "=&b"))] 1026: "TARGET_DW_ENABLE" 1027: "load 0,18,%0,%1" 1028: [(set_attr "type" "load")]) 1029: 1030: ;; LOADM 1031: (define_expand "load_multiple" 1032: [(set (match_dup 4) 1033: (match_operand:PSI 2 "const_int_operand" "")) 1034: (match_par_dup 3 [(set (match_operand:SI 0 "" "") 1035: (match_operand:SI 1 "" ""))])] 1036: "" 1037: " 1038: { 1039: int regno; 1040: int count; 1041: rtx from; 1042: int i; 1043: 1044: /* Support only loading a constant number of hard registers from memory. */ 1045: if (GET_CODE (operands[2]) != CONST_INT 1046: || operands[2] == const1_rtx 1047: || GET_CODE (operands[1]) != MEM 1048: || GET_CODE (operands[0]) != REG 1049: || REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER) 1050: FAIL; 1051: 1052: count = INTVAL (operands[2]); 1053: regno = REGNO (operands[0]); 1054: 1055: /* CR gets set to the number of registers minus one. */ 1056: operands[2] = GEN_INT(count - 1); 1057: 1058: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 2)); 1059: from = memory_address (SImode, XEXP (operands[1], 0)); 1060: XVECEXP (operands[3], 0, 0) = gen_rtx (SET, VOIDmode, 1061: gen_rtx (REG, SImode, regno), 1062: gen_rtx (MEM, SImode, from)); 1063: operands[4] = gen_reg_rtx (PSImode); 1064: 1065: XVECEXP (operands[3], 0, 1) = gen_rtx (USE, VOIDmode, operands[4]); 1066: XVECEXP (operands[3], 0, 2) = gen_rtx (CLOBBER, VOIDmode, operands[4]); 1067: 1068: for (i = 1; i < count; i++) 1069: XVECEXP (operands[3], 0, i + 2) 1070: = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i), 1071: gen_rtx (MEM, SImode, plus_constant (from, i * 4))); 1072: }") 1073: 1074: ;; Indicate that CR is used and is then clobbered. 1075: (define_insn "" 1076: [(set (match_operand 0 "gpc_reg_operand" "=r") 1077: (match_operand 1 "memory_operand" "m")) 1078: (use (match_operand:PSI 2 "register_operand" "+c")) 1079: (clobber (match_dup 2))] 1080: "GET_MODE (operands[0]) == GET_MODE (operands[1]) 1081: && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD" 1082: "loadm 0,0,%0,%1" 1083: [(set_attr "type" "load")]) 1084: 1085: (define_insn "" 1086: [(match_parallel 0 "load_multiple_operation" 1087: [(set (match_operand:SI 1 "gpc_reg_operand" "=r") 1088: (match_operand:SI 2 "memory_operand" "m")) 1089: (use (match_operand:PSI 3 "register_operand" "+c")) 1090: (clobber (match_dup 3))])] 1091: "" 1092: "loadm 0,0,%1,%2" 1093: [(set_attr "type" "load")]) 1094: 1095: ;; MTSR (used also by move insn) 1096: (define_insn "" 1097: [(set (match_operand:SI 0 "spec_reg_operand" "=*h,*h") 1098: (and:SI (match_operand:SI 1 "gpc_reg_or_immediate_operand" "r,i") 1099: (match_operand:SI 2 "const_int_operand" "n,n")))] 1100: "masks_bits_for_special (operands[0], operands[2])" 1101: "@ 1102: mtsr %0,%1 1103: mtsrim %0,%1") 1104: 1105: (define_insn "" 1106: [(set (match_operand:PSI 0 "register_operand" "=h,h") 1107: (truncate:PSI 1108: (match_operand:SI 1 "gpc_reg_or_immediate_operand" "r,i")))] 1109: "" 1110: "@ 1111: mtsr %0,%1 1112: mtsrim %0,%1") 1113: 1114: ;; MULTIPLY, MULTM, MULTMU 1115: (define_insn "mulsi3" 1116: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1117: (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1118: (match_operand:SI 2 "gpc_reg_operand" "r"))) 1119: (clobber (match_scratch:SI 3 "=&q"))] 1120: "" 1121: "multiply %0,%1,%2") 1122: 1123: (define_insn "" 1124: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1125: (subreg:SI 1126: (mult:DI 1127: (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1128: (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) 0)) 1129: (clobber (match_scratch:SI 3 "=&q"))] 1130: "" 1131: "multm %0,%1,%2") 1132: 1133: (define_insn "" 1134: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1135: (subreg:SI 1136: (mult:DI 1137: (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1138: (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) 0)) 1139: (clobber (match_scratch:SI 3 "=&q"))] 1140: "" 1141: "multmu %0,%1,%2") 1142: 1143: (define_insn "mulsidi3" 1144: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 1145: (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) 1146: (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) 1147: (clobber (match_scratch:SI 3 "=&q"))] 1148: "" 1149: "multiply %L0,%1,%2\;multm %0,%1,%2" 1150: [(set_attr "type" "multi")]) 1151: 1152: (define_split 1153: [(set (match_operand:DI 0 "gpc_reg_operand" "") 1154: (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 1155: (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "")))) 1156: (clobber (reg:SI 180))] 1157: "reload_completed" 1158: [(parallel [(set (match_dup 3) 1159: (mult:SI (match_dup 1) (match_dup 2))) 1160: (clobber (reg:SI 180))]) 1161: (parallel [(set (match_dup 4) 1162: (subreg:SI (mult:DI 1163: (sign_extend:DI (match_dup 1)) 1164: (sign_extend:DI (match_dup 2))) 0)) 1165: (clobber (reg:SI 180))])] 1166: " 1167: { operands[3] = operand_subword (operands[0], 1, 1, DImode); 1168: operands[4] = operand_subword (operands[1], 0, 1, DImode); } ") 1169: 1170: (define_insn "umulsidi3" 1171: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 1172: (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) 1173: (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) 1174: (clobber (match_scratch:SI 3 "=&q"))] 1175: "" 1176: "multiplu %L0,%1,%2\;multmu %0,%1,%2" 1177: [(set_attr "type" "multi")]) 1178: 1179: (define_split 1180: [(set (match_operand:DI 0 "gpc_reg_operand" "") 1181: (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 1182: (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "")))) 1183: (clobber (reg:SI 180))] 1184: "reload_completed" 1185: [(parallel [(set (match_dup 3) 1186: (mult:SI (match_dup 1) (match_dup 2))) 1187: (clobber (reg:SI 180))]) 1188: (parallel [(set (match_dup 4) 1189: (subreg:SI (mult:DI (zero_extend:DI (match_dup 1)) 1190: (zero_extend:DI (match_dup 2))) 0)) 1191: (clobber (reg:SI 180))])] 1192: " 1193: { operands[3] = operand_subword (operands[0], 1, 1, DImode); 1194: operands[4] = operand_subword (operands[1], 0, 1, DImode); } ") 1195: 1.1.1.3 ! root 1196: (define_insn "smulsi3_highpart" ! 1197: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1198: (truncate:SI ! 1199: (lshiftrt:DI ! 1200: (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) ! 1201: (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 1202: (const_int 32)))) ! 1203: (clobber (match_scratch:SI 3 "=&q"))] ! 1204: "" ! 1205: "multm %0,%1,%2") ! 1206: ! 1207: (define_insn "umulsi3_highpart" ! 1208: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ! 1209: (truncate:SI ! 1210: (lshiftrt:DI ! 1211: (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) ! 1212: (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) ! 1213: (const_int 32)))) ! 1214: (clobber (match_scratch:SI 3 "=&q"))] ! 1215: "" ! 1216: "multmu %0,%1,%2") ! 1217: 1.1 root 1218: ;; NAND 1219: (define_insn "" 1220: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1221: (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1.1.3 ! root 1222: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] 1.1 root 1223: "" 1224: "nand %0,%1,%2") 1225: 1226: (define_insn "" 1227: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1228: (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 1229: (match_operand:SI 2 "const_int_operand" "K")))] 1.1.1.3 ! root 1230: ; Match TARGET_29050 in "orn" pattern for slightly better reload. ! 1231: "! TARGET_29050 && ((unsigned) ~ INTVAL (operands[2])) < 256" 1.1 root 1232: "nand %0,%1,%C2") 1233: 1234: ;; NOR 1235: (define_insn "" 1236: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1237: (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) 1.1.1.3 ! root 1238: (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] 1.1 root 1239: "" 1240: "nor %0,%1,%2") 1241: 1242: (define_insn "one_cmplsi2" 1243: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1244: (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 1245: "" 1246: "nor %0,%1,0") 1247: 1248: ;; OR/ORN 1249: (define_expand "iorsi3" 1250: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1251: (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") 1252: (match_operand:SI 2 "srcb_operand" "")))] 1253: "" 1254: "") 1255: 1256: (define_insn "" 1257: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1258: (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1259: (match_operand:SI 2 "srcb_operand" "rI")))] 1260: "! TARGET_29050" 1261: "or %0,%1,%2") 1262: 1263: (define_insn "" 1264: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1265: (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 1.1.1.3 ! root 1266: (match_operand:SI 2 "and_operand" "rI,K")))] 1.1 root 1267: "TARGET_29050" 1268: "@ 1269: or %0,%1,%2 1270: orn %0,%1,%C2") 1271: 1.1.1.3 ! root 1272: (define_insn "" ! 1273: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 1274: (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) ! 1275: (match_operand:SI 2 "cmplsrcb_operand" "r,K")))] ! 1276: "TARGET_29050" ! 1277: "@ ! 1278: orn %0,%2,%1 ! 1279: nand %0,%1,%C2") ! 1280: 1.1 root 1281: 1282: ;; SLL (also used by move insn) 1283: (define_insn "nop" 1284: [(const_int 0)] 1285: "" 1286: "aseq 0x40,gr1,gr1") 1287: 1288: (define_insn "ashlsi3" 1289: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1290: (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1291: (match_operand:QI 2 "srcb_operand" "rn")))] 1292: "" 1293: "sll %0,%1,%Q2") 1294: 1295: ;; SQRT 1296: (define_insn "sqrtsf2" 1297: [(set (match_operand:SF 0 "gpc_reg_operand" "=r") 1298: (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "r")))] 1299: "TARGET_29050" 1300: "sqrt %0,%1,1" 1301: [(set_attr "type" "fsqrt")]) 1302: 1303: (define_insn "sqrtdf2" 1304: [(set (match_operand:DF 0 "gpc_reg_operand" "=r") 1305: (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "r")))] 1306: "TARGET_29050" 1307: "sqrt %0,%1,2" 1308: [(set_attr "type" "dsqrt")]) 1309: 1310: ;; SRA 1311: (define_insn "ashrsi3" 1312: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1313: (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1314: (match_operand:QI 2 "srcb_operand" "rn")))] 1315: "" 1316: "sra %0,%1,%Q2") 1317: 1318: ;; SRL 1319: (define_insn "lshrsi3" 1320: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1321: (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1322: (match_operand:QI 2 "srcb_operand" "rn")))] 1323: "" 1324: "srl %0,%1,%Q2") 1325: 1326: ;; STORE 1327: ;; 1328: ;; These somewhat bogus patterns exist to set OPT = 001/010 for partial-word 1329: ;; stores on systems with DW not set. 1330: (define_insn "" 1331: [(set (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "r") 1332: (const_int -4))) 1333: (match_operand:SI 1 "gpc_reg_operand" "r"))] 1334: "! TARGET_DW_ENABLE" 1335: "store 0,1,%1,%0" 1336: [(set_attr "type" "store")]) 1337: 1338: (define_insn "" 1339: [(set (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "r") 1340: (const_int -3))) 1341: (match_operand:SI 1 "gpc_reg_operand" "r"))] 1342: "! TARGET_DW_ENABLE" 1343: "store 0,2,%1,%0" 1344: [(set_attr "type" "store")]) 1345: 1346: ;; STOREM 1347: (define_expand "store_multiple" 1348: [(use (match_operand 0 "" "")) 1349: (use (match_operand 1 "" "")) 1350: (use (match_operand 2 "" ""))] 1351: "" 1352: " 1353: { rtx pat; 1354: 1355: if (TARGET_NO_STOREM_BUG) 1356: pat = gen_store_multiple_no_bug (operands[0], operands[1], operands[2]); 1357: else 1358: pat = gen_store_multiple_bug (operands[0], operands[1], operands[2]); 1359: 1360: if (pat) 1361: emit_insn (pat); 1362: else 1363: FAIL; 1364: 1365: DONE; 1366: }") 1367: 1368: (define_expand "store_multiple_no_bug" 1369: [(set (match_dup 4) 1370: (match_operand:PSI 2 "const_int_operand" "")) 1371: (match_par_dup 3 [(set (match_operand:SI 0 "" "") 1372: (match_operand:SI 1 "" ""))])] 1373: "" 1374: " 1375: { 1376: int regno; 1377: int count; 1378: rtx from; 1379: int i; 1380: 1381: /* Support only storing a constant number of hard registers to memory. */ 1382: if (GET_CODE (operands[2]) != CONST_INT 1383: || operands[2] == const1_rtx 1384: || GET_CODE (operands[0]) != MEM 1385: || GET_CODE (operands[1]) != REG 1386: || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER) 1387: FAIL; 1388: 1389: count = INTVAL (operands[2]); 1390: regno = REGNO (operands[1]); 1391: 1392: /* CR gets set to the number of registers minus one. */ 1393: operands[2] = GEN_INT(count - 1); 1394: 1395: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 2)); 1396: from = memory_address (SImode, XEXP (operands[0], 0)); 1397: XVECEXP (operands[3], 0, 0) = gen_rtx (SET, VOIDmode, 1398: gen_rtx (MEM, SImode, from), 1399: gen_rtx (REG, SImode, regno)); 1400: operands[4] = gen_reg_rtx (PSImode); 1401: XVECEXP (operands[3], 0, 1) = gen_rtx (USE, VOIDmode, operands[4]); 1402: XVECEXP (operands[3], 0, 2) = gen_rtx (CLOBBER, VOIDmode, operands[4]); 1403: 1404: for (i = 1; i < count; i++) 1405: XVECEXP (operands[3], 0, i + 2) 1406: = gen_rtx (SET, VOIDmode, 1407: gen_rtx (MEM, SImode, plus_constant (from, i * 4)), 1408: gen_rtx (REG, SImode, regno + i)); 1409: }") 1410: 1411: (define_expand "store_multiple_bug" 1412: [(match_par_dup 3 [(set (match_operand:SI 0 "" "") 1413: (match_operand:SI 1 "" "")) 1414: (use (match_operand:SI 2 "" ""))])] 1415: "" 1416: " 1417: { 1418: int regno; 1419: int count; 1420: rtx from; 1421: int i; 1422: 1423: /* Support only storing a constant number of hard registers to memory. */ 1424: if (GET_CODE (operands[2]) != CONST_INT 1425: || operands[2] == const1_rtx 1426: || GET_CODE (operands[0]) != MEM 1427: || GET_CODE (operands[1]) != REG 1428: || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER) 1429: FAIL; 1430: 1431: count = INTVAL (operands[2]); 1432: regno = REGNO (operands[1]); 1433: 1434: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1)); 1435: from = memory_address (SImode, XEXP (operands[0], 0)); 1436: XVECEXP (operands[3], 0, 0) = gen_rtx (SET, VOIDmode, 1437: gen_rtx (MEM, SImode, from), 1438: gen_rtx (REG, SImode, regno)); 1439: XVECEXP (operands[3], 0, 1) 1440: = gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, PSImode)); 1441: 1442: for (i = 1; i < count; i++) 1443: XVECEXP (operands[3], 0, i + 1) 1444: = gen_rtx (SET, VOIDmode, 1445: gen_rtx (MEM, SImode, plus_constant (from, i * 4)), 1446: gen_rtx (REG, SImode, regno + i)); 1447: }") 1448: 1449: (define_insn "" 1450: [(set (match_operand 0 "memory_operand" "=m") 1451: (match_operand 1 "gpc_reg_operand" "r")) 1452: (clobber (match_scratch:PSI 2 "=&c"))] 1453: "!TARGET_NO_STOREM_BUG 1454: && GET_MODE (operands[0]) == GET_MODE (operands[1]) 1455: && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD" 1456: "mtsrim cr,%S1\;storem 0,0,%1,%0" 1457: [(set_attr "type" "multi")]) 1458: 1459: (define_insn "" 1460: [(match_parallel 0 "store_multiple_operation" 1461: [(set (match_operand:SI 1 "memory_operand" "=m") 1462: (match_operand:SI 2 "gpc_reg_operand" "r")) 1463: (clobber (match_scratch:PSI 3 "=&c"))])] 1464: "!TARGET_NO_STOREM_BUG" 1465: "mtsrim cr,%V0\;storem 0,0,%2,%1" 1466: [(set_attr "type" "multi")]) 1467: 1468: (define_insn "" 1469: [(set (match_operand 0 "memory_operand" "=m") 1470: (match_operand 1 "gpc_reg_operand" "r")) 1471: (use (match_operand:PSI 2 "register_operand" "+c")) 1472: (clobber (match_dup 2))] 1473: "TARGET_NO_STOREM_BUG 1474: && GET_MODE (operands[0]) == GET_MODE (operands[1]) 1475: && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD" 1476: "storem 0,0,%1,%0" 1477: [(set_attr "type" "store")]) 1478: 1479: (define_insn "" 1480: [(match_parallel 0 "store_multiple_operation" 1481: [(set (match_operand:SI 1 "memory_operand" "=m") 1482: (match_operand:SI 2 "gpc_reg_operand" "r")) 1483: (use (match_operand:PSI 3 "register_operand" "+c")) 1484: (clobber (match_dup 3))])] 1485: "TARGET_NO_STOREM_BUG" 1486: "storem 0,0,%2,%1" 1487: [(set_attr "type" "store")]) 1488: 1489: ;; SUB 1490: ;; 1491: ;; Either operand can be a register or an 8-bit constant, but both cannot be 1492: ;; constants (can't usually occur anyway). 1493: (define_expand "subsi3" 1494: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1495: (minus:SI (match_operand:SI 1 "srcb_operand" "") 1496: (match_operand:SI 2 "srcb_operand" "")))] 1497: "" 1498: " 1499: { 1500: if (GET_CODE (operands[0]) == CONST_INT 1501: && GET_CODE (operands[1]) == CONST_INT) 1502: operands[1] = force_reg (SImode, operands[1]); 1503: }") 1504: 1505: (define_insn "" 1506: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1507: (minus:SI (match_operand:SI 1 "srcb_operand" "r,I") 1508: (match_operand:SI 2 "srcb_operand" "rI,r")))] 1509: "register_operand (operands[1], SImode) 1510: || register_operand (operands[2], SImode)" 1511: "@ 1512: sub %0,%1,%2 1513: subr %0,%2,%1") 1514: 1515: (define_insn "subdi3" 1516: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 1517: (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r") 1518: (match_operand:DI 2 "gpc_reg_operand" "r")))] 1519: "" 1520: "sub %L0,%L1,%L2\;subc %0,%1,%2" 1521: [(set_attr "type" "multi")]) 1522: 1523: ;; SUBR (also used above in SUB) 1524: (define_insn "negdi2" 1525: [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 1526: (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] 1527: "" 1528: "subr %L0,%L1,0\;subrc %0,%1,0" 1529: [(set_attr "type" "multi")]) 1530: 1531: (define_insn "negsi2" 1532: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1533: (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 1534: "" 1535: "subr %0,%1,0") 1536: 1537: ;; XNOR 1538: (define_insn "" 1539: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1540: (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") 1.1.1.3 ! root 1541: (match_operand:SI 2 "gpc_reg_operand" "r"))))] 1.1 root 1542: "" 1543: "xnor %0,%1,%2") 1544: 1545: ;; XOR 1.1.1.3 ! root 1546: 1.1 root 1547: (define_insn "xorsi3" 1.1.1.3 ! root 1548: [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") ! 1549: (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") ! 1550: (match_operand:SI 2 "and_operand" "rI,K")))] 1.1 root 1551: "" 1.1.1.3 ! root 1552: "@ ! 1553: xor %0,%1,%2 ! 1554: xnor %0,%1,%C2") 1.1 root 1555: 1556: ;; Can use XOR to negate floating-point values, but we are better off not doing 1557: ;; it that way on the 29050 so it can combine with the fmac insns. 1558: (define_expand "negsf2" 1559: [(parallel [(set (match_operand:SF 0 "register_operand" "") 1560: (neg:SF (match_operand:SF 1 "register_operand" ""))) 1561: (clobber (match_scratch:SI 2 ""))])] 1.1.1.3 ! root 1562: "! TARGET_SOFT_FLOAT" 1.1 root 1563: " 1564: { 1565: rtx result; 1566: rtx target; 1567: 1568: if (! TARGET_29050) 1569: { 1570: target = operand_subword_force (operands[0], 0, SFmode); 1571: result = expand_binop (SImode, xor_optab, 1572: operand_subword_force (operands[1], 0, SFmode), 1573: GEN_INT(0x80000000), target, 0, OPTAB_WIDEN); 1574: if (result == 0) 1575: abort (); 1576: 1577: if (result != target) 1578: emit_move_insn (result, target); 1579: 1580: /* Make a place for REG_EQUAL. */ 1581: emit_move_insn (operands[0], operands[0]); 1582: DONE; 1583: } 1584: }") 1585: 1586: (define_expand "negdf2" 1587: [(parallel [(set (match_operand:DF 0 "register_operand" "") 1588: (neg:DF (match_operand:DF 1 "register_operand" ""))) 1589: (clobber (match_scratch:SI 2 ""))])] 1.1.1.3 ! root 1590: "! TARGET_SOFT_FLOAT" 1.1 root 1591: " 1592: { 1593: rtx result; 1594: rtx target; 1595: rtx insns; 1596: 1597: if (! TARGET_29050) 1598: { 1599: start_sequence (); 1600: target = operand_subword (operands[0], 0, 1, DFmode); 1601: result = expand_binop (SImode, xor_optab, 1602: operand_subword_force (operands[1], 0, DFmode), 1603: GEN_INT(0x80000000), target, 0, OPTAB_WIDEN); 1604: if (result == 0) 1605: abort (); 1606: 1607: if (result != target) 1608: emit_move_insn (result, target); 1609: 1610: emit_move_insn (operand_subword (operands[0], 1, 1, DFmode), 1611: operand_subword_force (operands[1], 1, DFmode)); 1612: 1613: insns = get_insns (); 1614: end_sequence (); 1615: 1616: emit_no_conflict_block (insns, operands[0], operands[1], 0, 0); 1617: DONE; 1618: } 1619: }") 1620: 1621: ;; Sign extend and truncation operations. 1622: (define_insn "zero_extendqihi2" 1623: [(set (match_operand:HI 0 "gpc_reg_operand" "=r") 1624: (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] 1625: "" 1626: "and %0,%1,255") 1627: 1628: (define_insn "zero_extendqisi2" 1629: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1630: (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] 1631: "" 1632: "and %0,%1,255") 1633: 1634: (define_insn "zero_extendhisi2" 1635: [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1636: (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "0")))] 1637: "" 1638: "consth %0,0") 1639: 1640: (define_expand "extendqihi2" 1641: [(set (match_dup 2) 1642: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") 1643: (const_int 24))) 1644: (set (match_operand:HI 0 "gpc_reg_operand" "") 1645: (ashiftrt:SI (match_dup 2) 1646: (const_int 24)))] 1647: "" 1648: " 1649: { operands[0] = gen_lowpart (SImode, operands[0]); 1650: operands[1] = gen_lowpart (SImode, operands[1]); 1651: operands[2] = gen_reg_rtx (SImode); }") 1652: 1653: (define_expand "extendqisi2" 1654: [(set (match_dup 2) 1655: (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") 1656: (const_int 24))) 1657: (set (match_operand:SI 0 "gpc_reg_operand" "") 1658: (ashiftrt:SI (match_dup 2) 1659: (const_int 24)))] 1660: "" 1661: " 1662: { operands[1] = gen_lowpart (SImode, operands[1]); 1663: operands[2] = gen_reg_rtx (SImode); }") 1664: 1665: (define_expand "extendhisi2" 1666: [(set (match_dup 2) 1667: (ashift:SI (match_operand:HI 1 "gpc_reg_operand" "") 1668: (const_int 16))) 1669: (set (match_operand:SI 0 "gpc_reg_operand" "") 1670: (ashiftrt:SI (match_dup 2) 1671: (const_int 16)))] 1672: "" 1673: " 1674: { operands[1] = gen_lowpart (SImode, operands[1]); 1675: operands[2] = gen_reg_rtx (SImode); }") 1676: 1677: ;; Define the methods used to move data around. 1678: ;; 1679: ;; movsi: 1680: ;; 1681: ;; If storing into memory, force source into register. 1682: (define_expand "movsi" 1683: [(set (match_operand:SI 0 "general_operand" "") 1684: (match_operand:SI 1 "general_operand" ""))] 1685: "" 1686: " 1687: { 1688: if (GET_CODE (operands[0]) == MEM && ! gpc_reg_operand (operands[1], SImode)) 1689: operands[1] = copy_to_mode_reg (SImode, operands[1]); 1690: else if (spec_reg_operand (operands[0], SImode) 1691: && ! (register_operand (operands[1], SImode) 1692: || cint_16_operand (operands[1], SImode))) 1693: operands[1] = force_reg (SImode, operands[1]); 1694: }") 1695: 1696: (define_expand "movpsi" 1697: [(set (match_operand:PSI 0 "general_operand" "") 1698: (match_operand:PSI 1 "general_operand" ""))] 1699: "" 1700: " 1701: { 1702: if (GET_CODE (operands[0]) == MEM 1703: && ! gpc_reg_operand (operands[1], PSImode)) 1704: operands[1] = copy_to_mode_reg (PSImode, operands[1]); 1705: else if (spec_reg_operand (operands[0], PSImode) 1706: && ! (register_operand (operands[1], PSImode) 1707: || cint_16_operand (operands[1], PSImode))) 1708: operands[1] = force_reg (PSImode, operands[1]); 1709: }") 1710: 1711: (define_split 1712: [(set (match_operand:SI 0 "gpc_reg_operand" "") 1713: (match_operand:SI 1 "long_const_operand" ""))] 1714: "" 1715: [(set (match_dup 0) 1716: (and:SI (match_dup 1) 1717: (const_int 65535))) 1718: (set (match_dup 0) 1719: (ior:SI (zero_extend:SI (match_dup 2)) 1720: (and:SI (match_dup 1) 1721: (const_int -65536))))] 1722: " operands[2] = gen_lowpart (HImode, operands[0]); ") 1723: 1724: ;; Subroutines to load/store halfwords. Operands 0 and 1 are the output and 1725: ;; input, respectively, except that the address is passed for a MEM instead 1726: ;; of the MEM itself and the short item is passed in QImode. 1727: ;; 1728: ;; Operand 2 is a scratch general register and operand 3 is a scratch register 1729: ;; used for BP. When called before reload, pseudos are passed for both 1730: ;; operands. During reload, R_TAV is used for the general register, and 1731: ;; a reload register of class BR_REGS (R_VP) for BP. 1732: ;; 1733: ;; We have two versions of the store operations, for when halfword writes are 1734: ;; supported and when they are not. 1735: (define_expand "loadhi" 1736: [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "") 1737: (mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "") 1738: (const_int -4)))) 1739: (set (match_operand:PSI 3 "register_operand" "") 1740: (truncate:PSI (match_dup 1)))]) 1741: (set (match_operand:SI 0 "gpc_reg_operand" "") 1742: (zero_extract:SI (match_dup 2) 1743: (const_int 16) 1744: (ashift:PSI (match_dup 3) (const_int 3))))] 1745: "" 1746: "") 1747: 1748: (define_expand "storehinhww" 1749: [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "") 1750: (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "") 1751: (const_int -4)))) 1752: (set (match_operand:PSI 3 "register_operand" "") 1753: (truncate:PSI (match_dup 0)))]) 1754: (set (zero_extract:SI (match_dup 2) 1755: (const_int 16) 1756: (ashift:PSI (match_dup 3) (const_int 3))) 1757: (match_operand:SI 1 "gpc_reg_operand" "")) 1758: (set (mem:SI (match_dup 0)) 1759: (match_dup 2))] 1760: "" 1761: "") 1762: 1763: (define_expand "storehihww" 1764: [(set (match_operand:PSI 3 "register_operand" "") 1765: (truncate:PSI (match_operand:SI 0 "gpc_reg_operand" ""))) 1766: (set (match_operand:SI 2 "gpc_reg_operand" "") 1767: (ior:SI (and:SI (not:SI (ashift:SI (const_int 65535) 1768: (ashift:PSI (match_dup 3) 1769: (const_int 3)))) 1770: (match_operand:SI 1 "gpc_reg_operand" "")) 1771: (ashift:SI (zero_extend:SI (match_dup 4)) 1772: (ashift:PSI (match_dup 3) (const_int 3))))) 1773: (set (mem:SI (and:SI (match_dup 0) 1774: (const_int -3))) 1775: (match_dup 2))] 1776: "" 1777: " 1778: { operands[4] = gen_lowpart (HImode, operands[1]); }") 1779: 1780: (define_expand "movhi" 1781: [(set (match_operand:HI 0 "general_operand" "") 1782: (match_operand:HI 1 "general_operand" ""))] 1783: "" 1784: " 1785: { if (GET_CODE (operands[0]) == MEM) 1786: { 1787: if (! gpc_reg_operand (operands[1], HImode)) 1788: operands[1] = copy_to_mode_reg (HImode, operands[1]); 1789: if (! TARGET_DW_ENABLE) 1790: { 1791: rtx general = gen_reg_rtx (SImode); 1792: rtx bp = gen_reg_rtx (PSImode); 1793: rtx (*fcn) () 1794: = TARGET_BYTE_WRITES ? gen_storehihww : gen_storehinhww; 1795: rtx seq = (*fcn) (XEXP (operands[0], 0), 1796: gen_lowpart (SImode, operands[1]), 1797: general, bp); 1798: 1799: a29k_set_memflags (seq, operands[0]); 1800: emit_insn (seq); 1801: DONE; 1802: } 1803: } 1804: else if (GET_CODE (operands[1]) == MEM) 1805: { 1806: if (! TARGET_DW_ENABLE) 1807: { 1808: rtx general = gen_reg_rtx (SImode); 1809: rtx bp = gen_reg_rtx (PSImode); 1.1.1.3 ! root 1810: rtx seq = gen_loadhi (gen_lowpart (SImode, operands[0]), 1.1 root 1811: XEXP (operands[1], 0), general, bp); 1812: 1813: a29k_set_memflags (seq, operands[1]); 1814: emit_insn (seq); 1815: DONE; 1816: } 1817: } 1818: }") 1819: 1820: (define_expand "reload_inhi" 1821: [(parallel [(match_operand:SI 0 "register_operand" "=r") 1822: (match_operand:SI 1 "reload_memory_operand" "m") 1823: (match_operand:PSI 2 "register_operand" "=b")])] 1824: "! TARGET_DW_ENABLE" 1825: " 1826: { rtx seq = gen_loadhi (gen_lowpart (SImode, operands[0]), 1827: a29k_get_reloaded_address (operands[1]), 1828: gen_rtx (REG, SImode, R_TAV), 1829: operands[2]); 1830: 1831: a29k_set_memflags (seq, operands[1]); 1832: emit_insn (seq); 1833: DONE; 1834: }") 1835: 1836: (define_expand "reload_outhi" 1837: [(parallel [(match_operand:SI 0 "reload_memory_operand" "=m") 1838: (match_operand:SI 1 "register_operand" "m") 1839: (match_operand:PSI 2 "register_operand" "=b")])] 1840: "! TARGET_DW_ENABLE" 1841: " 1842: { rtx (*fcn) () = TARGET_BYTE_WRITES ? gen_storehihww : gen_storehinhww; 1843: rtx seq = (*fcn) (a29k_get_reloaded_address (operands[0]), 1844: gen_lowpart (SImode, operands[1]), 1845: gen_rtx (REG, SImode, R_TAV), operands[2]); 1846: 1847: a29k_set_memflags (seq, operands[0]); 1848: emit_insn (seq); 1849: DONE; 1850: }") 1851: 1852: ;; Subroutines to load/store bytes. Operands 0 and 1 are the output and 1853: ;; input, respectively, except that the address is passed for a MEM instead 1854: ;; of the MEM itself and the short item is passed in QImode. 1855: ;; 1856: ;; Operand 2 is a scratch general register and operand 3 is a scratch register 1857: ;; used for BP. When called before reload, pseudos are passed for both 1858: ;; operands. During reload, R_TAV is used for the general register, and 1859: ;; a reload register of class BR_REGS (R_VP) for BP. 1860: ;; 1861: ;; We have two versions of the store operations, for when byte writes are 1862: ;; supported and when they are not. 1863: (define_expand "loadqi" 1864: [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "") 1865: (mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "") 1866: (const_int -4)))) 1867: (set (match_operand:PSI 3 "register_operand" "") 1868: (truncate:PSI (match_dup 1)))]) 1869: (set (match_operand:SI 0 "gpc_reg_operand" "") 1870: (zero_extract:SI (match_dup 2) 1871: (const_int 8) 1872: (ashift:PSI (match_dup 3) (const_int 3))))] 1873: "" 1874: "") 1875: 1876: (define_expand "storeqinhww" 1877: [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "") 1878: (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "") 1879: (const_int -4)))) 1880: (set (match_operand:PSI 3 "register_operand" "") 1881: (truncate:PSI (match_dup 0)))]) 1882: (set (zero_extract:SI (match_dup 2) 1883: (const_int 8) 1884: (ashift:PSI (match_dup 3) 1885: (const_int 3))) 1886: (match_operand:SI 1 "gpc_reg_operand" "")) 1887: (set (mem:SI (match_dup 0)) 1888: (match_dup 2))] 1889: "" 1890: "") 1891: 1892: (define_expand "storeqihww" 1893: [(set (match_operand:PSI 3 "register_operand" "") 1894: (truncate:PSI (match_operand:SI 0 "gpc_reg_operand" ""))) 1895: (set (match_operand:SI 2 "gpc_reg_operand" "") 1896: (ior:SI (and:SI (not:SI (ashift:SI (const_int 255) 1897: (ashift:PSI (match_dup 3) 1898: (const_int 3)))) 1899: (match_operand:SI 1 "gpc_reg_operand" "")) 1900: (ashift:SI (zero_extend:SI (match_dup 4)) 1901: (ashift:PSI (match_dup 3) 1902: (const_int 3))))) 1903: (set (mem:SI (and:SI (match_dup 0) 1904: (const_int -4))) 1905: (match_dup 2))] 1906: "" 1907: " 1908: { operands[4] = gen_lowpart (QImode, operands[1]); }") 1909: 1910: (define_expand "movqi" 1911: [(set (match_operand:QI 0 "general_operand" "") 1912: (match_operand:QI 1 "general_operand" ""))] 1913: "" 1914: " 1915: { if (GET_CODE (operands[0]) == MEM) 1916: { 1917: if (! gpc_reg_operand (operands[1], QImode)) 1918: operands[1] = copy_to_mode_reg (QImode, operands[1]); 1919: if (! TARGET_DW_ENABLE) 1920: { 1921: rtx general = gen_reg_rtx (SImode); 1922: rtx bp = gen_reg_rtx (PSImode); 1923: rtx (*fcn) () 1924: = TARGET_BYTE_WRITES ? gen_storeqihww : gen_storeqinhww; 1925: rtx seq = (*fcn) (XEXP (operands[0], 0), 1926: gen_lowpart (SImode, operands[1]), 1927: general, bp); 1928: 1929: a29k_set_memflags (seq, operands[0]); 1930: emit_insn (seq); 1.1.1.3 ! root 1931: DONE; 1.1 root 1932: } 1933: } 1934: else if (GET_CODE (operands[1]) == MEM) 1935: { 1936: if (! TARGET_DW_ENABLE) 1937: { 1938: rtx general = gen_reg_rtx (SImode); 1939: rtx bp = gen_reg_rtx (PSImode); 1940: rtx seq = gen_loadqi (gen_lowpart (SImode, operands[0]), 1941: XEXP (operands[1], 0), general, bp); 1942: 1943: a29k_set_memflags (seq, operands[1]); 1944: emit_insn (seq); 1945: DONE; 1946: } 1947: } 1948: }") 1949: 1950: (define_expand "reload_inqi" 1951: [(parallel [(match_operand:SI 0 "register_operand" "=r") 1952: (match_operand:SI 1 "reload_memory_operand" "m") 1953: (match_operand:PSI 2 "register_operand" "=b")])] 1954: "! TARGET_DW_ENABLE" 1955: " 1956: { rtx seq = gen_loadqi (gen_lowpart (SImode, operands[0]), 1957: a29k_get_reloaded_address (operands[1]), 1958: gen_rtx (REG, SImode, R_TAV), 1959: operands[2]); 1960: 1961: a29k_set_memflags (seq, operands[1]); 1962: emit_insn (seq); 1963: DONE; 1964: }") 1965: 1966: (define_expand "reload_outqi" 1967: [(parallel [(match_operand:SI 0 "reload_memory_operand" "=m") 1968: (match_operand:SI 1 "register_operand" "m") 1969: (match_operand:PSI 2 "register_operand" "=b")])] 1970: "! TARGET_DW_ENABLE" 1971: " 1972: { rtx (*fcn) () = TARGET_BYTE_WRITES ? gen_storeqihww : gen_storeqinhww; 1973: rtx seq = (*fcn) (a29k_get_reloaded_address (operands[0]), 1974: gen_lowpart (SImode, operands[1]), 1975: gen_rtx (REG, SImode, R_TAV), operands[2]); 1976: 1977: a29k_set_memflags (seq, operands[0]); 1978: emit_insn (seq); 1979: DONE; 1980: }") 1981: 1982: ;; Now the actual insns used to move data around. We include here the 1983: ;; DEFINE_SPLITs that may be needed. In some cases these will be 1984: ;; split again. For floating-point, if we can look inside the constant, 1985: ;; always split it. This can eliminate unnecessary insns. 1986: (define_insn "" 1987: [(set (match_operand:SF 0 "out_operand" "=r,r,r,r,m") 1988: (match_operand:SF 1 "in_operand" "r,E,F,m,r"))] 1989: "(gpc_reg_operand (operands[0], SFmode) 1990: || gpc_reg_operand (operands[1], SFmode)) 1991: && ! TARGET_29050" 1992: "@ 1993: sll %0,%1,0 1994: # 1995: const %0,%1\;consth %0,%1 1996: load 0,0,%0,%1 1997: store 0,0,%1,%0" 1998: [(set_attr "type" "misc,multi,multi,load,store")]) 1999: 2000: (define_insn "" 2001: [(set (match_operand:SF 0 "out_operand" "=r,r,r,r,m,*a,r") 2002: (match_operand:SF 1 "in_operand" "r,E,F,m,r,r,*a"))] 2003: "(gpc_reg_operand (operands[0], SFmode) 2004: || gpc_reg_operand (operands[1], SFmode)) 2005: && TARGET_29050" 2006: "@ 2007: sll %0,%1,0 2008: # 2009: const %0,%1\;consth %0,%1 2010: load 0,0,%0,%1 2011: store 0,0,%1,%0 2012: mtacc %1,1,%0 2013: mfacc %0,1,%1" 2014: [(set_attr "type" "misc,multi,multi,load,store,fadd,fadd")]) 2015: 2016: ;; Turn this into SImode. It will then be split up that way. 2017: (define_split 2018: [(set (match_operand:SF 0 "register_operand" "") 2019: (match_operand:SF 1 "float_const_operand" ""))] 2020: "HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT" 2021: [(set (match_dup 0) 2022: (match_dup 1))] 2023: " 2024: { operands[0] = operand_subword (operands[0], 0, 0, SFmode); 2025: operands[1] = operand_subword (operands[1], 0, 0, SFmode); 2026: 2027: if (operands[0] == 0 || operands[1] == 0) 2028: FAIL; 2029: }") 2030: 2031: (define_insn "" 2032: [(set (match_operand:DF 0 "out_operand" "=?r,?r,r,m") 2033: (match_operand:DF 1 "in_operand" "rE,F,m,r")) 2034: (clobber (match_scratch:PSI 2 "=X,X,&c,&c"))] 2035: "(gpc_reg_operand (operands[0], DFmode) 2036: || gpc_reg_operand (operands[1], DFmode)) 2037: && ! TARGET_29050" 2038: "@ 2039: # 2040: const %0,%1\;consth %0,%1\;const %L0,%L1\;consth %L0,%L1 2041: mtsrim cr,1\;loadm 0,0,%0,%1 2042: mtsrim cr,1\;storem 0,0,%1,%0" 2043: [(set_attr "type" "multi")]) 2044: 2045: (define_insn "" 2046: [(set (match_operand:DF 0 "out_operand" "=?r,?r,r,m,?*a,?r") 2047: (match_operand:DF 1 "in_operand" "rE,F,m,r,r,*a")) 2048: (clobber (match_scratch:PSI 2 "=X,X,&c,&c,X,X"))] 2049: "(gpc_reg_operand (operands[0], DFmode) 2050: || gpc_reg_operand (operands[1], DFmode)) 2051: && TARGET_29050" 2052: "@ 2053: # 2054: const %0,%1\;consth %0,%1\;const %L0,%L1\;consth %L0,%L1 2055: mtsrim cr,1\;loadm 0,0,%0,%1 2056: mtsrim cr,1\;storem 0,0,%1,%0 2057: mtacc %1,2,%0 2058: mfacc %0,2,%1" 2059: [(set_attr "type" "multi,multi,multi,multi,fadd,fadd")]) 2060: 2061: ;; Split register-register copies and constant loads into two SImode loads, 2062: ;; one for each word. In the constant case, they will get further split. 2063: ;; Don't so this until register allocation, though, since it will 2064: ;; interfere with register allocation. Normally copy the lowest-addressed 2065: ;; word first; the exception is if we are copying register to register and 2066: ;; the lowest register of the first operand is the highest register of the 2067: ;; second operand. 2068: (define_split 2069: [(set (match_operand:DF 0 "gpc_reg_operand" "") 2070: (match_operand:DF 1 "gpc_reg_or_float_constant_operand" "")) 2071: (clobber (match_scratch:PSI 2 ""))] 2072: "reload_completed" 2073: [(set (match_dup 3) (match_dup 4)) 2074: (set (match_dup 5) (match_dup 6))] 2075: " 2076: { if (GET_CODE (operands[1]) == REG 2077: && REGNO (operands[0]) == REGNO (operands[1]) + 1) 2078: { 2079: operands[3] = operand_subword (operands[0], 1, 1, DFmode); 2080: operands[4] = operand_subword (operands[1], 1, 1, DFmode); 2081: operands[5] = operand_subword (operands[0], 0, 1, DFmode); 2082: operands[6] = operand_subword (operands[1], 0, 1, DFmode); 2083: } 2084: else 2085: { 2086: operands[3] = operand_subword (operands[0], 0, 1, DFmode); 2087: operands[4] = operand_subword (operands[1], 0, 1, DFmode); 2088: operands[5] = operand_subword (operands[0], 1, 1, DFmode); 2089: operands[6] = operand_subword (operands[1], 1, 1, DFmode); 2090: } 2091: 2092: if (operands[3] == 0 || operands[4] == 0 2093: || operands[5] == 0 || operands[6] == 0) 2094: FAIL; 2095: }") 2096: 2097: ;; Split memory loads and stores into the MTSR and LOADM/STOREM. 2098: (define_split 2099: [(set (match_operand:DF 0 "out_operand" "") 2100: (match_operand:DF 1 "in_operand" "")) 2101: (clobber (reg:PSI 179))] 2102: "TARGET_NO_STOREM_BUG 2103: && (memory_operand (operands[0], DFmode) 2104: || memory_operand (operands[1], DFmode))" 2105: [(set (reg:PSI 179) (const_int 1)) 2106: (parallel [(set (match_dup 0) (match_dup 1)) 2107: (use (reg:PSI 179)) 2108: (clobber (reg:PSI 179))])] 2109: "") 2110: 2111: ;; DI move is similar to DF move. 2112: (define_insn "" 2113: [(set (match_operand:DI 0 "out_operand" "=?r,r,m") 2114: (match_operand:DI 1 "in_operand" "rn,m,r")) 2115: (clobber (match_scratch:PSI 2 "=X,&c,&c"))] 2116: "(gpc_reg_operand (operands[0], DImode) 2117: || gpc_reg_operand (operands[1], DImode))" 2118: "@ 2119: # 2120: mtsrim cr,1\;loadm 0,0,%0,%1 2121: mtsrim cr,1\;storem 0,0,%1,%0" 2122: [(set_attr "type" "multi")]) 2123: 2124: (define_split 2125: [(set (match_operand:DI 0 "gpc_reg_operand" "") 2126: (match_operand:DI 1 "gpc_reg_or_integer_constant_operand" "")) 2127: (clobber (match_scratch:PSI 2 ""))] 2128: "reload_completed" 2129: [(set (match_dup 3) (match_dup 4)) 2130: (set (match_dup 5) (match_dup 6))] 2131: " 2132: { if (GET_CODE (operands[1]) == REG 2133: && REGNO (operands[0]) == REGNO (operands[1]) + 1) 2134: { 2135: operands[3] = operand_subword (operands[0], 1, 1, DImode); 2136: operands[4] = operand_subword (operands[1], 1, 1, DImode); 2137: operands[5] = operand_subword (operands[0], 0, 1, DImode); 2138: operands[6] = operand_subword (operands[1], 0, 1, DImode); 2139: } 2140: else 2141: { 2142: operands[3] = operand_subword (operands[0], 0, 1, DImode); 2143: operands[4] = operand_subword (operands[1], 0, 1, DImode); 2144: operands[5] = operand_subword (operands[0], 1, 1, DImode); 2145: operands[6] = operand_subword (operands[1], 1, 1, DImode); 2146: } 2147: }") 2148: 2149: (define_split 2150: [(set (match_operand:DI 0 "out_operand" "") 2151: (match_operand:DI 1 "in_operand" "")) 2152: (clobber (reg:PSI 179))] 2153: "TARGET_NO_STOREM_BUG 2154: && (memory_operand (operands[0], DImode) 2155: || memory_operand (operands[1], DImode))" 2156: [(set (reg:PSI 179) (const_int 1)) 2157: (parallel [(set (match_dup 0) (match_dup 1)) 2158: (use (reg:PSI 179)) 2159: (clobber (reg:PSI 179))])] 2160: "") 2161: 2162: ;; TImode moves are very similar to DImode moves, except that we can't 2163: ;; have constants. 2164: (define_insn "" 2165: [(set (match_operand:TI 0 "out_operand" "=?r,r,m") 2166: (match_operand:TI 1 "in_operand" "r,m,r")) 2167: (clobber (match_scratch:PSI 2 "=X,&c,&c"))] 2168: "(gpc_reg_operand (operands[0], TImode) 2169: || gpc_reg_operand (operands[1], TImode))" 2170: "@ 2171: # 2172: mtsrim cr,3\;loadm 0,0,%0,%1 2173: mtsrim cr,3\;storem 0,0,%1,%0" 2174: [(set_attr "type" "multi,multi,multi")]) 2175: 2176: (define_split 2177: [(set (match_operand:TI 0 "gpc_reg_operand" "") 2178: (match_operand:TI 1 "gpc_reg_operand" "")) 2179: (clobber (match_scratch:PSI 2 ""))] 2180: "reload_completed" 2181: [(set (match_dup 3) (match_dup 4)) 2182: (set (match_dup 5) (match_dup 6)) 2183: (set (match_dup 7) (match_dup 8)) 2184: (set (match_dup 9) (match_dup 10))] 2185: " 2186: { 2187: if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 2188: && REGNO (operands[0]) <= REGNO (operands[1]) + 3) 2189: { 2190: operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 3); 2191: operands[4] = gen_rtx (REG, SImode, REGNO (operands[1]) + 3); 2192: operands[5] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2); 2193: operands[6] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2); 2194: operands[7] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 2195: operands[8] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 2196: operands[9] = gen_rtx (REG, SImode, REGNO (operands[0])); 2197: operands[10] = gen_rtx (REG, SImode, REGNO (operands[1])); 2198: } 2199: else 2200: { 2201: operands[3] = gen_rtx (REG, SImode, REGNO (operands[0])); 2202: operands[4] = gen_rtx (REG, SImode, REGNO (operands[1])); 2203: operands[5] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 2204: operands[6] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 2205: operands[7] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2); 2206: operands[8] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2); 2207: operands[9] = gen_rtx (REG, SImode, REGNO (operands[0]) + 3); 2208: operands[10] = gen_rtx (REG, SImode, REGNO (operands[1]) + 3); 2209: } 2210: }") 2211: 2212: (define_split 2213: [(set (match_operand:TI 0 "out_operand" "") 2214: (match_operand:TI 1 "in_operand" "")) 2215: (clobber (reg:PSI 179))] 2216: "TARGET_NO_STOREM_BUG 2217: && (memory_operand (operands[0], TImode) 2218: || memory_operand (operands[1], TImode))" 1.1.1.2 root 2219: [(set (reg:PSI 179) (const_int 3)) 1.1 root 2220: (parallel [(set (match_dup 0) (match_dup 1)) 2221: (use (reg:PSI 179)) 2222: (clobber (reg:PSI 179))])] 2223: "") 2224: 2225: (define_insn "" 2226: [(set (match_operand:SI 0 "out_operand" "=r,r,r,r,r,r,r,m,*h,*h") 2227: (match_operand:SI 1 "in_operand" "r,J,M,O,i,m,*h,r,r,J"))] 2228: "(gpc_reg_operand (operands[0], SImode) 2229: || gpc_reg_operand (operands[1], SImode) 2230: || (spec_reg_operand (operands[0], SImode) 2231: && cint_16_operand (operands[1], SImode))) 2232: && ! TARGET_29050" 2233: "@ 2234: sll %0,%1,0 2235: const %0,%1 2236: constn %0,%M1 2237: cpeq %0,gr1,gr1 2238: # 2239: load 0,0,%0,%1 2240: mfsr %0,%1 2241: store 0,0,%1,%0 2242: mtsr %0,%1 2243: mtsrim %0,%1" 2244: [(set_attr "type" "misc,misc,misc,misc,multi,load,misc,store,misc,misc")]) 2245: 2246: (define_insn "" 2247: [(set (match_operand:SI 0 "out_operand" "=r,r,r,r,r,r,r,m,*h,*h") 2248: (match_operand:SI 1 "in_operand" "r,J,M,O,i,m,*h,r,r,J"))] 2249: "(gpc_reg_operand (operands[0], SImode) 2250: || gpc_reg_operand (operands[1], SImode) 2251: || (spec_reg_operand (operands[0], SImode) 2252: && cint_16_operand (operands[1], SImode))) 2253: && TARGET_29050" 2254: "@ 2255: sll %0,%1,0 2256: const %0,%1 2257: constn %0,%M1 2258: consthz %0,%1 2259: # 2260: load 0,0,%0,%1 2261: mfsr %0,%1 2262: store 0,0,%1,%0 2263: mtsr %0,%1 2264: mtsrim %0,%1" 2265: [(set_attr "type" "misc,misc,misc,misc,multi,load,misc,store,misc,misc")]) 2266: 2267: (define_insn "" 2268: [(set (match_operand:PSI 0 "out_operand" "=*r,*r,*r,*r,m,h,h") 2269: (match_operand:PSI 1 "in_operand" "r,i,m,h,r,r,J"))] 2270: "(gpc_reg_operand (operands[0], PSImode) 2271: || gpc_reg_operand (operands[1], PSImode) 2272: || (spec_reg_operand (operands[0], PSImode) 2273: && cint_16_operand (operands[1], PSImode)))" 2274: "@ 2275: sll %0,%1,0 2276: const %0,%1 2277: load 0,0,%0,%1 2278: mfsr %0,%1 2279: store 0,0,%1,%0 2280: mtsr %0,%1 2281: mtsrim %0,%1" 2282: [(set_attr "type" "misc,multi,load,misc,store,misc,misc")]) 2283: 2284: (define_insn "" 2285: [(set (match_operand:HI 0 "out_operand" "=r,r,r,m,r,*h,*h") 2286: (match_operand:HI 1 "in_operand" "r,i,m,r,*h,r,i"))] 2287: "gpc_reg_operand (operands[0], HImode) 2288: || gpc_reg_operand (operands[1], HImode) 2289: || (spec_reg_operand (operands[0], HImode) 2290: && cint_16_operand (operands[1], HImode))" 2291: "@ 2292: sll %0,%1,0 2293: const %0,%1 2294: load 0,2,%0,%1 2295: store 0,2,%1,%0 2296: mfsr %0,%1 2297: mtsr %0,%1 2298: mtsrim %0,%1" 2299: [(set_attr "type" "misc,misc,load,store,misc,misc,misc")]) 2300: 2301: (define_insn "" 2302: [(set (match_operand:QI 0 "out_operand" "=r,r,r,m,r,*h,*h") 2303: (match_operand:QI 1 "in_operand" "r,i,m,r,*h,r,i"))] 2304: "gpc_reg_operand (operands[0], QImode) 2305: || gpc_reg_operand (operands[1], QImode) 2306: || (spec_reg_operand (operands[0], HImode) 2307: && cint_16_operand (operands[1], HImode))" 2308: "@ 2309: sll %0,%1,0 2310: const %0,%1 2311: load 0,1,%0,%1 2312: store 0,1,%1,%0 2313: mfsr %0,%1 2314: mtsr %0,%1 2315: mtsrim %0,%1" 2316: [(set_attr "type" "misc,misc,load,store,misc,misc,misc")]) 2317: 2318: ;; Define move insns for DI, TI, SF, and DF. 2319: ;; 2320: ;; In no case do we support mem->mem directly. 2321: ;; 2322: ;; For DI move of constant to register, split apart at this time since these 2323: ;; can require anywhere from 2 to 4 insns and determining which is complex. 2324: ;; 2325: ;; In other cases, handle similarly to SImode moves. 2326: ;; 2327: ;; However, indicate that DI, TI, and DF moves may clobber CR (reg 179). 2328: (define_expand "movdi" 2329: [(parallel [(set (match_operand:DI 0 "general_operand" "") 2330: (match_operand:DI 1 "general_operand" "")) 2331: (clobber (scratch:PSI))])] 2332: "" 2333: " 2334: { 2335: if (GET_CODE (operands[0]) == MEM) 2336: operands[1] = force_reg (DImode, operands[1]); 2337: }") 2338: 2339: (define_expand "movsf" 2340: [(set (match_operand:SF 0 "general_operand" "") 2341: (match_operand:SF 1 "general_operand" ""))] 2342: "" 2343: " 2344: { if (GET_CODE (operands[0]) == MEM) 2345: operands[1] = force_reg (SFmode, operands[1]); 2346: }") 2347: 2348: (define_expand "movdf" 2349: [(parallel [(set (match_operand:DF 0 "general_operand" "") 2350: (match_operand:DF 1 "general_operand" "")) 2351: (clobber (scratch:PSI))])] 2352: "" 2353: " 2354: { if (GET_CODE (operands[0]) == MEM) 2355: operands[1] = force_reg (DFmode, operands[1]); 2356: }") 2357: 2358: (define_expand "movti" 2359: [(parallel [(set (match_operand:TI 0 "general_operand" "") 2360: (match_operand:TI 1 "general_operand" "")) 2361: (clobber (scratch:PSI))])] 2362: "" 2363: " 2364: { 2365: if (GET_CODE (operands[0]) == MEM) 2366: operands[1] = force_reg (TImode, operands[1]); 2367: 2368: /* We can't handle constants in general because there is no rtl to represent 2369: 128 bit constants. Splitting happens to work for CONST_INTs so we split 2370: them for good code. Other constants will get forced to memory. */ 2371: 2372: if (GET_CODE (operands[1]) == CONST_INT) 2373: { 2374: rtx part0, part1, part2, part3; 2375: 2376: part0 = operand_subword (operands[0], 0, 1, TImode); 2377: part1 = operand_subword (operands[0], 1, 1, TImode); 2378: part2 = operand_subword (operands[0], 2, 1, TImode); 2379: part3 = operand_subword (operands[0], 3, 1, TImode); 2380: 2381: emit_move_insn (part0, const0_rtx); 2382: emit_move_insn (part1, const0_rtx); 2383: emit_move_insn (part2, const0_rtx); 2384: emit_move_insn (part3, const0_rtx); 2385: 2386: DONE; 2387: } 2388: else if (CONSTANT_P (operands[1])) 2389: { 2390: operands[1] = force_const_mem (TImode, operands[1]); 2391: if (! memory_address_p (TImode, XEXP (operands[1], 0)) 2392: && ! reload_in_progress) 2393: operands[1] = change_address (operands[1], TImode, 2394: XEXP (operands[1], 0)); 2395: } 2396: }") 2397: 2398: ;; Here are the variants of the above for use during reload. 2399: 2400: (define_expand "reload_indf" 2401: [(parallel [(set (match_operand:DF 0 "register_operand" "=r") 2402: (match_operand:DF 1 "reload_memory_operand" "m")) 2403: (clobber (match_operand:PSI 2 "register_operand" "=&c"))])] 2404: "" 2405: "") 2406: 2407: (define_expand "reload_outdf" 2408: [(parallel [(set (match_operand:DF 0 "reload_memory_operand" "=m") 2409: (match_operand:DF 1 "register_operand" "r")) 2410: (clobber (match_operand:PSI 2 "register_operand" "=&c"))])] 2411: "" 2412: "") 2413: 2414: (define_expand "reload_indi" 2415: [(parallel [(set (match_operand:DI 0 "register_operand" "=r") 2416: (match_operand:DI 1 "reload_memory_operand" "m")) 2417: (clobber (match_operand:PSI 2 "register_operand" "=&c"))])] 2418: "" 2419: "") 2420: 2421: (define_expand "reload_outdi" 2422: [(parallel [(set (match_operand:DI 0 "reload_memory_operand" "=m") 2423: (match_operand:DI 1 "register_operand" "r")) 2424: (clobber (match_operand:PSI 2 "register_operand" "=&c"))])] 2425: "" 2426: "") 2427: 2428: (define_expand "reload_inti" 2429: [(parallel [(set (match_operand:TI 0 "register_operand" "=r") 2430: (match_operand:TI 1 "reload_memory_operand" "m")) 2431: (clobber (match_operand:PSI 2 "register_operand" "=&c"))])] 2432: "" 2433: "") 2434: 2435: (define_expand "reload_outti" 2436: [(parallel [(set (match_operand:TI 0 "reload_memory_operand" "=m") 2437: (match_operand:TI 1 "register_operand" "r")) 2438: (clobber (match_operand:PSI 2 "register_operand" "=&c"))])] 2439: "" 2440: "") 2441: 2442: ;; For compare operations, we simply store the comparison operands and 2443: ;; do nothing else. The following branch or scc insn will output whatever 2444: ;; is needed. 2445: (define_expand "cmpsi" 2446: [(set (cc0) 2447: (compare (match_operand:SI 0 "gpc_reg_operand" "") 2448: (match_operand:SI 1 "srcb_operand" "")))] 2449: "" 2450: " 2451: { 2452: a29k_compare_op0 = operands[0]; 2453: a29k_compare_op1 = operands[1]; 2454: a29k_compare_fp_p = 0; 2455: DONE; 2456: }") 2457: 2458: (define_expand "cmpsf" 2459: [(set (cc0) 2460: (compare (match_operand:SF 0 "gpc_reg_operand" "") 2461: (match_operand:SF 1 "gpc_reg_operand" "")))] 1.1.1.3 ! root 2462: "! TARGET_SOFT_FLOAT" 1.1 root 2463: " 2464: { 2465: a29k_compare_op0 = operands[0]; 2466: a29k_compare_op1 = operands[1]; 2467: a29k_compare_fp_p = 1; 2468: DONE; 2469: }") 2470: 2471: (define_expand "cmpdf" 2472: [(set (cc0) 2473: (compare (match_operand:DF 0 "gpc_reg_operand" "") 2474: (match_operand:DF 1 "gpc_reg_operand" "")))] 1.1.1.3 ! root 2475: "! TARGET_SOFT_FLOAT" 1.1 root 2476: " 2477: { 2478: a29k_compare_op0 = operands[0]; 2479: a29k_compare_op1 = operands[1]; 2480: a29k_compare_fp_p = 1; 2481: DONE; 2482: }") 2483: 2484: ;; We can generate bit-tests better if we use NE instead of EQ, but we 2485: ;; don't have an NE for floating-point. So we have to have two patterns 2486: ;; for EQ and two for NE. 2487: 2488: (define_expand "beq" 2489: [(set (match_dup 1) (ne:SI (match_dup 2) (match_dup 3))) 2490: (set (pc) 2491: (if_then_else (ge (match_dup 1) (const_int 0)) 2492: (label_ref (match_operand 0 "" "")) 2493: (pc)))] 2494: "" 2495: " 2496: { 2497: if (GET_MODE_CLASS (GET_MODE (a29k_compare_op0)) == MODE_FLOAT) 2498: { 2499: emit_insn (gen_beq_fp (operands[0])); 2500: DONE; 2501: } 2502: 2503: operands[1] = gen_reg_rtx (SImode); 2504: operands[2] = a29k_compare_op0; 2505: operands[3] = a29k_compare_op1; 2506: }") 2507: 2508: (define_expand "beq_fp" 2509: [(set (match_dup 1) (eq:SI (match_dup 2) (match_dup 3))) 2510: (set (pc) 2511: (if_then_else (lt (match_dup 1) (const_int 0)) 2512: (label_ref (match_operand 0 "" "")) 2513: (pc)))] 2514: "" 2515: " 2516: { 2517: operands[1] = gen_reg_rtx (SImode); 2518: operands[2] = a29k_compare_op0; 2519: operands[3] = a29k_compare_op1; 2520: }") 2521: 2522: (define_expand "bne" 2523: [(set (match_dup 1) (ne:SI (match_dup 2) (match_dup 3))) 2524: (set (pc) 2525: (if_then_else (lt (match_dup 1) (const_int 0)) 2526: (label_ref (match_operand 0 "" "")) 2527: (pc)))] 2528: "" 2529: " 2530: { 2531: if (GET_MODE_CLASS (GET_MODE (a29k_compare_op0)) == MODE_FLOAT) 2532: { 2533: emit_insn (gen_bne_fp (operands[0])); 2534: DONE; 2535: } 2536: 2537: operands[1] = gen_reg_rtx (SImode); 2538: operands[2] = a29k_compare_op0; 2539: operands[3] = a29k_compare_op1; 2540: }") 2541: 2542: (define_expand "bne_fp" 2543: [(set (match_dup 1) (eq:SI (match_dup 2) (match_dup 3))) 2544: (set (pc) 2545: (if_then_else (ge (match_dup 1) (const_int 0)) 2546: (label_ref (match_operand 0 "" "")) 2547: (pc)))] 2548: "" 2549: " 2550: { 2551: operands[1] = gen_reg_rtx (SImode); 2552: operands[2] = a29k_compare_op0; 2553: operands[3] = a29k_compare_op1; 2554: }") 2555: 2556: ;; We don't have a floating-point "lt" insn, so we have to use "gt" in that 2557: ;; case with the operands swapped. The operands must both be registers in 2558: ;; the floating-point case, so we know that swapping them is OK. 2559: (define_expand "blt" 2560: [(set (match_dup 1) (match_dup 2)) 2561: (set (pc) 2562: (if_then_else (lt (match_dup 1) (const_int 0)) 2563: (label_ref (match_operand 0 "" "")) 2564: (pc)))] 2565: "" 2566: " 2567: { 2568: operands[1] = gen_reg_rtx (SImode); 2569: if (a29k_compare_fp_p) 2570: operands[2] = gen_rtx (GT, SImode, a29k_compare_op1, a29k_compare_op0); 2571: else 2572: operands[2] = gen_rtx (LT, SImode, a29k_compare_op0, a29k_compare_op1); 2573: }") 2574: 2575: ;; Similarly for "le". 2576: (define_expand "ble" 2577: [(set (match_dup 1) (match_dup 2)) 2578: (set (pc) 2579: (if_then_else (lt (match_dup 1) (const_int 0)) 2580: (label_ref (match_operand 0 "" "")) 2581: (pc)))] 2582: "" 2583: " 2584: { 2585: operands[1] = gen_reg_rtx (SImode); 2586: if (a29k_compare_fp_p) 2587: operands[2] = gen_rtx (GE, SImode, a29k_compare_op1, a29k_compare_op0); 2588: else 2589: operands[2] = gen_rtx (LE, SImode, a29k_compare_op0, a29k_compare_op1); 2590: }") 2591: 2592: (define_expand "bltu" 2593: [(set (match_dup 1) (ltu:SI (match_dup 2) (match_dup 3))) 2594: (set (pc) 2595: (if_then_else (lt (match_dup 1) (const_int 0)) 2596: (label_ref (match_operand 0 "" "")) 2597: (pc)))] 2598: "" 2599: " 2600: { 2601: operands[1] = gen_reg_rtx (SImode); 2602: operands[2] = a29k_compare_op0; 2603: operands[3] = a29k_compare_op1; 2604: }") 2605: 2606: (define_expand "bleu" 2607: [(set (match_dup 1) (leu:SI (match_dup 2) (match_dup 3))) 2608: (set (pc) 2609: (if_then_else (lt (match_dup 1) (const_int 0)) 2610: (label_ref (match_operand 0 "" "")) 2611: (pc)))] 2612: "" 2613: " 2614: { 2615: operands[1] = gen_reg_rtx (SImode); 2616: operands[2] = a29k_compare_op0; 2617: operands[3] = a29k_compare_op1; 2618: }") 2619: 2620: (define_expand "bgt" 2621: [(set (match_dup 1) (gt:SI (match_dup 2) (match_dup 3))) 2622: (set (pc) 2623: (if_then_else (lt (match_dup 1) (const_int 0)) 2624: (label_ref (match_operand 0 "" "")) 2625: (pc)))] 2626: "" 2627: " 2628: { 2629: operands[1] = gen_reg_rtx (SImode); 2630: operands[2] = a29k_compare_op0; 2631: operands[3] = a29k_compare_op1; 2632: }") 2633: 2634: (define_expand "bge" 2635: [(set (match_dup 1) (ge:SI (match_dup 2) (match_dup 3))) 2636: (set (pc) 2637: (if_then_else (lt (match_dup 1) (const_int 0)) 2638: (label_ref (match_operand 0 "" "")) 2639: (pc)))] 2640: "" 2641: " 2642: { 2643: operands[1] = gen_reg_rtx (SImode); 2644: operands[2] = a29k_compare_op0; 2645: operands[3] = a29k_compare_op1; 2646: }") 2647: 2648: (define_expand "bgtu" 2649: [(set (match_dup 1) (gtu:SI (match_dup 2) (match_dup 3))) 2650: (set (pc) 2651: (if_then_else (lt (match_dup 1) (const_int 0)) 2652: (label_ref (match_operand 0 "" "")) 2653: (pc)))] 2654: "" 2655: " 2656: { 2657: operands[1] = gen_reg_rtx (SImode); 2658: operands[2] = a29k_compare_op0; 2659: operands[3] = a29k_compare_op1; 2660: }") 2661: 2662: (define_expand "bgeu" 2663: [(set (match_dup 1) (geu:SI (match_dup 2) (match_dup 3))) 2664: (set (pc) 2665: (if_then_else (lt (match_dup 1) (const_int 0)) 2666: (label_ref (match_operand 0 "" "")) 2667: (pc)))] 2668: "" 2669: " 2670: { 2671: operands[1] = gen_reg_rtx (SImode); 2672: operands[2] = a29k_compare_op0; 2673: operands[3] = a29k_compare_op1; 2674: }") 2675: 2676: (define_expand "seq" 2677: [(set (match_operand:SI 0 "gpc_reg_operand" "") 2678: (eq:SI (match_dup 1) (match_dup 2)))] 2679: "" 2680: " 2681: { 2682: operands[1] = a29k_compare_op0; 2683: operands[2] = a29k_compare_op1; 2684: }") 2685: 2686: ;; This is the most complicated case, because we don't have a floating-point 2687: ;; "ne" insn. If integer, handle normally. If floating-point, write the 2688: ;; compare and then write an insn to reverse the test. 2689: (define_expand "sne_fp" 2690: [(set (match_dup 3) 2691: (eq:SI (match_operand 1 "gpc_reg_operand" "") 2692: (match_operand 2 "gpc_reg_operand" ""))) 2693: (set (match_operand:SI 0 "gpc_reg_operand" "") 2694: (ge:SI (match_dup 3) (const_int 0)))] 1.1.1.3 ! root 2695: "! TARGET_SOFT_FLOAT" 1.1 root 2696: " 2697: { operands[3] = gen_reg_rtx (SImode); 2698: }"); 2699: 2700: (define_expand "sne" 2701: [(set (match_operand:SI 0 "gpc_reg_operand" "") 2702: (ne:SI (match_dup 1) (match_dup 2)))] 2703: "" 2704: " 2705: { 2706: operands[1] = a29k_compare_op0; 2707: operands[2] = a29k_compare_op1; 2708: 2709: if (a29k_compare_fp_p) 2710: { 2711: emit_insn (gen_sne_fp (operands[0], operands[1], operands[2])); 2712: DONE; 2713: } 2714: }") 2715: 2716: ;; We don't have a floating-point "lt" insn, so use "gt" and swap the 2717: ;; operands, the same as we do "blt". 2718: (define_expand "slt" 2719: [(set (match_operand:SI 0 "gpc_reg_operand" "") 2720: (match_dup 1))] 2721: "" 2722: " 2723: { 2724: if (a29k_compare_fp_p) 2725: operands[1] = gen_rtx (GT, SImode, a29k_compare_op1, a29k_compare_op0); 2726: else 2727: operands[1] = gen_rtx (LT, SImode, a29k_compare_op0, a29k_compare_op1); 2728: }") 2729: 2730: ;; Similarly for "le" 2731: (define_expand "sle" 2732: [(set (match_operand:SI 0 "gpc_reg_operand" "") 2733: (match_dup 1))] 2734: "" 2735: " 2736: { 2737: if (a29k_compare_fp_p) 2738: operands[1] = gen_rtx (GE, SImode, a29k_compare_op1, a29k_compare_op0); 2739: else 2740: operands[1] = gen_rtx (LE, SImode, a29k_compare_op0, a29k_compare_op1); 2741: }") 2742: 2743: (define_expand "sltu" 2744: [(set (match_operand:SI 0 "gpc_reg_operand" "") 2745: (ltu:SI (match_dup 1) (match_dup 2)))] 2746: "" 2747: " 2748: { 2749: operands[1] = a29k_compare_op0; 2750: operands[2] = a29k_compare_op1; 2751: }") 2752: 2753: (define_expand "sleu" 2754: [(set (match_operand:SI 0 "gpc_reg_operand" "") 2755: (leu:SI (match_dup 1) (match_dup 2)))] 2756: "" 2757: " 2758: { 2759: operands[1] = a29k_compare_op0; 2760: operands[2] = a29k_compare_op1; 2761: }") 2762: 2763: (define_expand "sgt" 2764: [(set (match_operand:SI 0 "gpc_reg_operand" "") 2765: (gt:SI (match_dup 1) (match_dup 2)))] 2766: "" 2767: " 2768: { 2769: operands[1] = a29k_compare_op0; 2770: operands[2] = a29k_compare_op1; 2771: }") 2772: 2773: (define_expand "sge" 2774: [(set (match_operand:SI 0 "gpc_reg_operand" "") 2775: (ge:SI (match_dup 1) (match_dup 2)))] 2776: "" 2777: " 2778: { 2779: operands[1] = a29k_compare_op0; 2780: operands[2] = a29k_compare_op1; 2781: }") 2782: 2783: (define_expand "sgtu" 2784: [(set (match_operand:SI 0 "gpc_reg_operand" "") 2785: (gtu:SI (match_dup 1) (match_dup 2)))] 2786: "" 2787: " 2788: { 2789: operands[1] = a29k_compare_op0; 2790: operands[2] = a29k_compare_op1; 2791: }") 2792: 2793: (define_expand "sgeu" 2794: [(set (match_operand:SI 0 "gpc_reg_operand" "") 2795: (geu:SI (match_dup 1) (match_dup 2)))] 2796: "" 2797: " 2798: { 2799: operands[1] = a29k_compare_op0; 2800: operands[2] = a29k_compare_op1; 2801: }") 2802: 2803: ;; Now define the actual jump insns. 2804: (define_insn "" 2805: [(set (pc) 2806: (if_then_else (match_operator 0 "branch_operator" 2807: [(match_operand:SI 1 "gpc_reg_operand" "r") 2808: (const_int 0)]) 2809: (label_ref (match_operand 2 "" "")) 2810: (pc)))] 2811: "" 2812: "jmp%b0 %1,%l2%#" 2813: [(set_attr "type" "branch")]) 2814: 2815: (define_insn "" 2816: [(set (pc) 2817: (if_then_else (match_operator 0 "branch_operator" 2818: [(match_operand:SI 1 "gpc_reg_operand" "r") 2819: (const_int 0)]) 2820: (return) 2821: (pc)))] 2822: "null_epilogue ()" 2823: "jmp%b0i %1,lr0%#" 2824: [(set_attr "type" "branch")]) 2825: 2826: (define_insn "" 2827: [(set (pc) 2828: (if_then_else (match_operator 0 "branch_operator" 2829: [(match_operand:SI 1 "gpc_reg_operand" "r") 2830: (const_int 0)]) 2831: (pc) 2832: (label_ref (match_operand 2 "" ""))))] 2833: "" 2834: "jmp%B0 %1,%l2%#" 2835: [(set_attr "type" "branch")]) 2836: 2837: (define_insn "" 2838: [(set (pc) 2839: (if_then_else (match_operator 0 "branch_operator" 2840: [(match_operand:SI 1 "gpc_reg_operand" "r") 2841: (const_int 0)]) 2842: (pc) 2843: (return)))] 2844: "null_epilogue ()" 2845: "jmp%B0i %1,lr0%#" 2846: [(set_attr "type" "branch")]) 2847: 2848: (define_insn "jump" 2849: [(set (pc) 2850: (label_ref (match_operand 0 "" "")))] 2851: "" 2852: "jmp %e0%E0" 2853: [(set_attr "type" "branch")]) 2854: 2855: (define_insn "return" 2856: [(return)] 2857: "null_epilogue ()" 2858: "jmpi lr0%#" 2859: [(set_attr "type" "branch")]) 2860: 2861: (define_insn "indirect_jump" 2862: [(set (pc) 2863: (match_operand:SI 0 "gpc_reg_operand" "r"))] 2864: "" 2865: "jmpi %0%#" 2866: [(set_attr "type" "branch")]) 2867: 2868: (define_insn "tablejump" 2869: [(set (pc) 2870: (match_operand:SI 0 "gpc_reg_operand" "r")) 2871: (use (label_ref (match_operand 1 "" "")))] 2872: "" 2873: "jmpi %0%#" 2874: [(set_attr "type" "branch")]) 2875: 2876: ;; JMPFDEC 2877: (define_insn "" 2878: [(set (pc) 2879: (if_then_else (ge (match_operand:SI 0 "gpc_reg_operand" "r") 2880: (const_int 0)) 2881: (label_ref (match_operand 1 "" "")) 2882: (pc))) 2883: (set (match_dup 0) 2884: (plus:SI (match_dup 0) 2885: (const_int -1)))] 2886: "" 2887: "jmpfdec %0,%l1%#" 2888: [(set_attr "type" "branch")])
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