--- gcc/config/alpha/alpha.md	2018/04/24 18:10:26	1.1
+++ gcc/config/alpha/alpha.md	2018/04/24 18:16:17	1.1.1.2
@@ -26,7 +26,7 @@
 ;; separately.
 
 (define_attr "type"
-  "ld,st,ibr,fbr,jsr,iaddlog,shiftcm,icmp,imull,imulq,fpop,fdivs,fdivt,ldsym"
+  "ld,st,ibr,fbr,jsr,iaddlog,shiftcm,icmp,imull,imulq,fpop,fdivs,fdivt,ldsym,isubr"
   (const_string "shiftcm"))
 
 ;; We include four function units: ABOX, which computes the address,
@@ -87,7 +87,7 @@
 
 (define_insn "addsi3"
   [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
-	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,%rJ,%rJ,%rJ")
+	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
 		 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
   ""
   "@
@@ -151,7 +151,7 @@
 
 (define_insn "adddi3"
   [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
-	(plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,%rJ,%rJ,%rJ")
+	(plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
 		 (match_operand:DI 2 "add_operand" "rI,O,K,L")))]
   ""
   "@
@@ -503,7 +503,8 @@
    (clobber (reg:DI 23))
    (clobber (reg:DI 28))]
   ""
-  "%E1 $24,$25,$27")
+  "%E1 $24,$25,$27"
+  [(set_attr "type" "isubr")])
 
 (define_insn ""
   [(set (reg:DI 27)
@@ -512,7 +513,8 @@
    (clobber (reg:DI 23))
    (clobber (reg:DI 28))]
   ""
-  "%E1 $24,$25,$27")
+  "%E1 $24,$25,$27"
+  [(set_attr "type" "isubr")])
 
 ;; Next are the basic logical operations.  These only exist in DImode.
 
@@ -633,7 +635,7 @@
 
 (define_insn "xordi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
-	(xor:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
+	(xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
 		(match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
   ""
   "xor %r1,%2,%0"
@@ -641,7 +643,7 @@
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")
-	(not:DI (xor:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
+	(not:DI (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
 			(match_operand:DI 2 "reg_or_8bit_operand" "rI"))))]
   ""
   "eqv %r1,%2,%0"
@@ -652,7 +654,7 @@
 (define_insn "ashldi3"
   [(set (match_operand:DI 0 "register_operand" "=r,r")
 	(ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
-		   (match_operand:DI 2 "reg_or_8bit_operand" "P,rI")))]
+		   (match_operand:DI 2 "reg_or_6bit_operand" "P,rI")))]
   ""
   "*
 {
@@ -695,14 +697,14 @@
 (define_insn "lshrdi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-		     (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
+		     (match_operand:DI 2 "reg_or_6bit_operand" "rI")))]
   ""
   "srl %r1,%2,%0")
 
 (define_insn "ashrdi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-		     (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
+		     (match_operand:DI 2 "reg_or_6bit_operand" "rI")))]
   ""
   "sra %r1,%2,%0")
 
@@ -971,7 +973,7 @@
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(plus:DF (float_extend:DF
-		  (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
+		  (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
 		 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
   "addt %R1,%R2,%0"
@@ -1075,7 +1077,7 @@
 
 (define_insn "mulsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
-	(mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
+	(mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
 		 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
   "muls %R1,%R2,%0"
@@ -1083,7 +1085,7 @@
 
 (define_insn "muldf3"
   [(set (match_operand:DF 0 "register_operand" "=f")
-	(mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
+	(mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
 		 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
   "mult %R1,%R2,%0"
@@ -1101,7 +1103,7 @@
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(mult:DF (float_extend:DF
-		  (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
+		  (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
 		 (float_extend:DF
 		  (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
   "TARGET_FP"
@@ -1110,7 +1112,7 @@
 
 (define_insn "subsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
-	(minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
+	(minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
 		  (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
   "subs %R1,%R2,%0"
@@ -1118,7 +1120,7 @@
 
 (define_insn "subdf3"
   [(set (match_operand:DF 0 "register_operand" "=f")
-	(minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
+	(minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
 		  (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
   "subt %R1,%R2,%0"
@@ -1127,7 +1129,7 @@
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(minus:DF (float_extend:DF
-		   (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
+		   (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
 		  (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
   "subt %R1,%R2,%0"
@@ -1135,7 +1137,7 @@
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
-	(minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
+	(minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
 		  (float_extend:DF
 		   (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
   "TARGET_FP"
@@ -1145,7 +1147,7 @@
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(minus:DF (float_extend:DF
-		   (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
+		   (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
 		  (float_extend:DF
 		   (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
   "TARGET_FP"
@@ -1366,7 +1368,7 @@
 				       (match_dup 0) (match_dup 1)))]
   "")
 
-(define_expand "maxdi3"
+(define_expand "smaxdi3"
   [(set (match_dup 3)
 	(le:DI (match_operand:DI 1 "reg_or_0_operand" "")
 	       (match_operand:DI 2 "reg_or_8bit_operand" "")))
@@ -2470,11 +2472,11 @@
 
 (define_insn ""
   [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m")
-	(match_operand:SF 1 "input_operand" "r,m,rG,f,G,m,fG"))]
+	(match_operand:SF 1 "input_operand" "rG,m,rG,f,G,m,fG"))]
   "register_operand (operands[0], SFmode)
    || reg_or_fp0_operand (operands[1], SFmode)"
   "@
-   bis %1,%1,%0
+   bis %r1,%r1,%0
    ldl %0,%1
    stl %r1,%0
    cpys %1,%1,%0
@@ -2485,11 +2487,11 @@
 
 (define_insn ""
   [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m")
-	(match_operand:DF 1 "input_operand" "r,m,rG,f,G,m,fG"))]
+	(match_operand:DF 1 "input_operand" "rG,m,rG,f,G,m,fG"))]
   "register_operand (operands[0], DFmode)
    || reg_or_fp0_operand (operands[1], DFmode)"
   "@
-   bis %1,%1,%0
+   bis %r1,%r1,%0
    ldq %0,%1
    stq %r1,%0
    cpys %1,%1,%0
@@ -2614,8 +2616,8 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,r,r,m,f,f,f,m")
-	(match_operand:DI 1 "input_operand" "r,J,I,K,L,s,m,rJ,f,J,m,fG"))]
+  [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,r,r,m,f,f,f,Q")
+	(match_operand:DI 1 "input_operand" "r,J,I,K,L,s,m,rJ,f,J,Q,fG"))]
   "register_operand (operands[0], DImode)
    || reg_or_0_operand (operands[1], DImode)"
   "@