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1.1.1.3 root 1: ;; Machine description for DEC Alpha for GNU C compiler 1.1.1.4 ! root 2: ;; Copyright (C) 1992, 1993, 1994, 1995 Free Software Foundation, Inc. 1.1.1.3 root 3: ;; Contributed by Richard Kenner ([email protected]) 1.1 root 4: 5: ;; This file is part of GNU CC. 6: 7: ;; GNU CC is free software; you can redistribute it and/or modify 8: ;; it under the terms of the GNU General Public License as published by 9: ;; the Free Software Foundation; either version 2, or (at your option) 10: ;; any later version. 11: 12: ;; GNU CC is distributed in the hope that it will be useful, 13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15: ;; GNU General Public License for more details. 16: 17: ;; You should have received a copy of the GNU General Public License 18: ;; along with GNU CC; see the file COPYING. If not, write to 1.1.1.4 ! root 19: ;; the Free Software Foundation, 59 Temple Place - Suite 330, ! 20: ;; Boston, MA 02111-1307, USA. 1.1 root 21: 22: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 23: 24: ;; Define an insn type attribute. This is used in function unit delay 25: ;; computations, among other purposes. For the most part, we use the names 26: ;; defined in the EV4 documentation, but add a few that we have to know about 27: ;; separately. 28: 29: (define_attr "type" 1.1.1.2 root 30: "ld,st,ibr,fbr,jsr,iaddlog,shiftcm,icmp,imull,imulq,fpop,fdivs,fdivt,ldsym,isubr" 1.1 root 31: (const_string "shiftcm")) 32: 33: ;; We include four function units: ABOX, which computes the address, 34: ;; BBOX, used for branches, EBOX, used for integer operations, and FBOX, 35: ;; used for FP operations. 36: ;; 37: ;; We assume that we have been successful in getting double issues and 38: ;; hence multiply all costs by two insns per cycle. The minimum time in 39: ;; a function unit is 2 cycle, which will tend to produce the double 40: ;; issues. 41: 42: ;; Memory delivers its result in three cycles. 43: (define_function_unit "abox" 1 0 (eq_attr "type" "ld,ldsym,st") 6 2) 44: 45: ;; Branches have no delay cost, but do tie up the unit for two cycles. 46: (define_function_unit "bbox" 1 1 (eq_attr "type" "ibr,fbr,jsr") 4 4) 47: 48: ;; Arithmetic insns are normally have their results available after two 49: ;; cycles. There are a number of exceptions. They are encoded in 50: ;; ADJUST_COST. Some of the other insns have similar exceptions. 51: 52: (define_function_unit "ebox" 1 0 (eq_attr "type" "iaddlog,shiftcm,icmp") 4 2) 53: 54: ;; These really don't take up the integer pipeline, but they do occupy 55: ;; IBOX1; we approximate here. 56: 57: (define_function_unit "ebox" 1 0 (eq_attr "type" "imull") 42 2) 58: (define_function_unit "ebox" 1 0 (eq_attr "type" "imulq") 46 2) 59: 60: (define_function_unit "imult" 1 0 (eq_attr "type" "imull") 42 38) 61: (define_function_unit "imult" 1 0 (eq_attr "type" "imulq") 46 42) 62: 63: (define_function_unit "fbox" 1 0 (eq_attr "type" "fpop") 12 2) 64: 65: (define_function_unit "fbox" 1 0 (eq_attr "type" "fdivs") 68 0) 66: (define_function_unit "fbox" 1 0 (eq_attr "type" "fdivt") 126 0) 67: 68: (define_function_unit "divider" 1 0 (eq_attr "type" "fdivs") 68 60) 69: (define_function_unit "divider" 1 0 (eq_attr "type" "fdivt") 126 118) 70: 71: ;; First define the arithmetic insns. Note that the 32-bit forms also 72: ;; sign-extend. 73: 74: ;; Note that we can do sign extensions in both FP and integer registers. 75: ;; However, the result must be in the same type of register as the input. 76: ;; The register preferencing code can't handle this case very well, so, for 77: ;; now, don't let the FP case show up here for preferencing. Also, 78: ;; sign-extends in FP registers take two instructions. 79: (define_insn "extendsidi2" 80: [(set (match_operand:DI 0 "register_operand" "=r,r,*f") 81: (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,*f")))] 82: "" 83: "@ 84: addl %1,$31,%0 85: ldl %0,%1 86: cvtql %1,%0\;cvtlq %0,%0" 87: [(set_attr "type" "iaddlog,ld,fpop")]) 88: 1.1.1.3 root 89: ;; Do addsi3 the way expand_binop would do if we didn't have one. This 90: ;; generates better code. We have the anonymous addsi3 pattern below in 91: ;; case combine wants to make it. 92: (define_expand "addsi3" 93: [(set (match_operand:SI 0 "register_operand" "") 94: (plus:SI (match_operand:SI 1 "reg_or_0_operand" "") 95: (match_operand:SI 2 "add_operand" "")))] 96: "" 97: " 98: { emit_insn (gen_rtx (SET, VOIDmode, gen_lowpart (DImode, operands[0]), 99: gen_rtx (PLUS, DImode, 100: gen_lowpart (DImode, operands[1]), 101: gen_lowpart (DImode, operands[2])))); 102: DONE; 103: } ") 104: 105: (define_insn "" 1.1 root 106: [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 1.1.1.2 root 107: (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ") 1.1 root 108: (match_operand:SI 2 "add_operand" "rI,O,K,L")))] 109: "" 110: "@ 111: addl %r1,%2,%0 112: subl %r1,%n2,%0 113: lda %0,%2(%r1) 114: ldah %0,%h2(%r1)" 115: [(set_attr "type" "iaddlog")]) 116: 117: (define_split 118: [(set (match_operand:SI 0 "register_operand" "") 119: (plus:SI (match_operand:SI 1 "register_operand" "") 120: (match_operand:SI 2 "const_int_operand" "")))] 121: "! add_operand (operands[2], SImode)" 122: [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) 123: (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] 124: " 125: { 126: HOST_WIDE_INT val = INTVAL (operands[2]); 127: HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); 128: HOST_WIDE_INT rest = val - low; 129: 130: operands[3] = GEN_INT (rest); 131: operands[4] = GEN_INT (low); 132: }") 133: 134: (define_insn "" 135: [(set (match_operand:DI 0 "register_operand" "=r,r") 136: (sign_extend:DI 137: (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") 138: (match_operand:SI 2 "sext_add_operand" "rI,O"))))] 139: "" 140: "@ 141: addl %r1,%2,%0 142: subl %r1,%n2,%0" 143: [(set_attr "type" "iaddlog")]) 144: 145: (define_split 146: [(set (match_operand:DI 0 "register_operand" "") 147: (sign_extend:DI 148: (plus:SI (match_operand:SI 1 "register_operand" "") 149: (match_operand:SI 2 "const_int_operand" "")))) 150: (clobber (match_operand:SI 3 "register_operand" ""))] 151: "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0 152: && INTVAL (operands[2]) % 4 == 0" 153: [(set (match_dup 3) (match_dup 4)) 154: (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3) 155: (match_dup 5)) 156: (match_dup 1))))] 157: " 158: { 159: HOST_WIDE_INT val = INTVAL (operands[2]) / 4; 160: int mult = 4; 161: 162: if (val % 2 == 0) 163: val /= 2, mult = 8; 164: 165: operands[4] = GEN_INT (val); 166: operands[5] = GEN_INT (mult); 167: }") 168: 1.1.1.3 root 169: (define_split 170: [(set (match_operand:DI 0 "register_operand" "") 171: (sign_extend:DI 172: (plus:SI (match_operator:SI 1 "comparison_operator" 173: [(match_operand 2 "" "") 174: (match_operand 3 "" "")]) 175: (match_operand:SI 4 "add_operand" "")))) 176: (clobber (match_operand:DI 5 "register_operand" ""))] 177: "" 178: [(set (match_dup 5) (match_dup 6)) 179: (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))] 180: " 181: { 182: operands[6] = gen_rtx (GET_CODE (operands[1]), DImode, 183: operands[2], operands[3]); 184: operands[7] = gen_lowpart (SImode, operands[5]); 185: }") 186: 1.1 root 187: (define_insn "adddi3" 188: [(set (match_operand:DI 0 "register_operand" "=r,r,r,r") 1.1.1.2 root 189: (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ") 1.1 root 190: (match_operand:DI 2 "add_operand" "rI,O,K,L")))] 191: "" 192: "@ 193: addq %r1,%2,%0 194: subq %r1,%n2,%0 195: lda %0,%2(%r1) 196: ldah %0,%h2(%r1)" 197: [(set_attr "type" "iaddlog")]) 198: 199: ;; Don't do this if we are adjusting SP since we don't want to do 200: ;; it in two steps. 201: (define_split 202: [(set (match_operand:DI 0 "register_operand" "") 203: (plus:DI (match_operand:DI 1 "register_operand" "") 204: (match_operand:DI 2 "const_int_operand" "")))] 205: "! add_operand (operands[2], DImode) 206: && REGNO (operands[0]) != STACK_POINTER_REGNUM" 207: [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) 208: (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] 209: " 210: { 211: HOST_WIDE_INT val = INTVAL (operands[2]); 212: HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); 213: HOST_WIDE_INT rest = val - low; 214: 215: operands[3] = GEN_INT (rest); 216: operands[4] = GEN_INT (low); 217: }") 218: 219: (define_insn "" 220: [(set (match_operand:SI 0 "register_operand" "=r,r") 221: (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ,rJ") 222: (match_operand:SI 2 "const48_operand" "I,I")) 223: (match_operand:SI 3 "sext_add_operand" "rI,O")))] 224: "" 225: "@ 226: s%2addl %r1,%3,%0 227: s%2subl %r1,%n3,%0" 228: [(set_attr "type" "iaddlog")]) 229: 230: (define_insn "" 231: [(set (match_operand:DI 0 "register_operand" "=r,r") 232: (sign_extend:DI 233: (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ,rJ") 234: (match_operand:SI 2 "const48_operand" "I,I")) 235: (match_operand:SI 3 "sext_add_operand" "rI,O"))))] 236: "" 237: "@ 238: s%2addl %r1,%3,%0 239: s%2subl %r1,%n3,%0" 240: [(set_attr "type" "iaddlog")]) 241: 1.1.1.3 root 242: (define_split 243: [(set (match_operand:DI 0 "register_operand" "") 244: (sign_extend:DI 245: (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator" 246: [(match_operand 2 "" "") 247: (match_operand 3 "" "")]) 248: (match_operand:SI 4 "const48_operand" "")) 249: (match_operand:SI 5 "add_operand" "")))) 250: (clobber (match_operand:DI 6 "register_operand" ""))] 251: "" 252: [(set (match_dup 6) (match_dup 7)) 253: (set (match_dup 0) 254: (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4)) 255: (match_dup 5))))] 256: " 257: { 258: operands[7] = gen_rtx (GET_CODE (operands[1]), DImode, 259: operands[2], operands[3]); 260: operands[8] = gen_lowpart (SImode, operands[6]); 261: }") 262: 1.1 root 263: (define_insn "" 264: [(set (match_operand:DI 0 "register_operand" "=r,r") 265: (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ") 266: (match_operand:DI 2 "const48_operand" "I,I")) 267: (match_operand:DI 3 "reg_or_8bit_operand" "rI,O")))] 268: "" 269: "@ 270: s%2addq %r1,%3,%0 271: s%2subq %1,%n3,%0" 272: [(set_attr "type" "iaddlog")]) 273: 274: ;; These variants of the above insns can occur if the third operand 275: ;; is the frame pointer. This is a kludge, but there doesn't 276: ;; seem to be a way around it. Only recognize them while reloading. 277: 278: (define_insn "" 1.1.1.4 ! root 279: [(set (match_operand:DI 0 "some_operand" "=&r") ! 280: (plus:DI (plus:DI (match_operand:DI 1 "some_operand" "r") ! 281: (match_operand:DI 2 "some_operand" "r")) ! 282: (match_operand:DI 3 "some_operand" "rIOKL")))] 1.1.1.3 root 283: "reload_in_progress" 284: "#" 285: [(set_attr "type" "iaddlog")]) 286: 287: (define_split 288: [(set (match_operand:DI 0 "register_operand" "") 289: (plus:DI (plus:DI (match_operand:DI 1 "register_operand" "") 290: (match_operand:DI 2 "register_operand" "")) 291: (match_operand:DI 3 "add_operand" "")))] 292: "reload_completed" 293: [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2))) 294: (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] 295: "") 296: 297: (define_insn "" 1.1.1.4 ! root 298: [(set (match_operand:SI 0 "some_operand" "=&r") 1.1.1.3 root 299: (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "some_operand" "rJ") 1.1 root 300: (match_operand:SI 2 "const48_operand" "I")) 1.1.1.4 ! root 301: (match_operand:SI 3 "some_operand" "r")) ! 302: (match_operand:SI 4 "some_operand" "rIOKL")))] 1.1 root 303: "reload_in_progress" 1.1.1.3 root 304: "#" 1.1 root 305: [(set_attr "type" "iaddlog")]) 306: 1.1.1.3 root 307: (define_split 308: [(set (match_operand:SI 0 "register_operand" "r") 309: (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "") 310: (match_operand:SI 2 "const48_operand" "")) 311: (match_operand:SI 3 "register_operand" "")) 312: (match_operand:SI 4 "add_operand" "rIOKL")))] 313: "reload_completed" 314: [(set (match_dup 0) 315: (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 316: (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] 317: "") 318: 1.1 root 319: (define_insn "" 1.1.1.4 ! root 320: [(set (match_operand:DI 0 "some_operand" "=&r") 1.1 root 321: (sign_extend:DI 322: (plus:SI (plus:SI 1.1.1.3 root 323: (mult:SI (match_operand:SI 1 "some_operand" "rJ") 1.1 root 324: (match_operand:SI 2 "const48_operand" "I")) 1.1.1.4 ! root 325: (match_operand:SI 3 "some_operand" "r")) ! 326: (match_operand:SI 4 "some_operand" "rIOKL"))))] 1.1 root 327: "reload_in_progress" 1.1.1.3 root 328: "#" 1.1 root 329: [(set_attr "type" "iaddlog")]) 330: 1.1.1.3 root 331: (define_split 332: [(set (match_operand:DI 0 "register_operand" "") 333: (sign_extend:DI 334: (plus:SI (plus:SI 335: (mult:SI (match_operand:SI 1 "reg_or_0_operand" "") 336: (match_operand:SI 2 "const48_operand" "")) 337: (match_operand:SI 3 "register_operand" "")) 338: (match_operand:SI 4 "add_operand" ""))))] 339: "reload_completed" 340: [(set (match_dup 5) 341: (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 342: (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 5) (match_dup 4))))] 343: " 344: { operands[5] = gen_lowpart (SImode, operands[0]); 345: }") 346: 1.1 root 347: (define_insn "" 1.1.1.4 ! root 348: [(set (match_operand:DI 0 "some_operand" "=&r") 1.1.1.3 root 349: (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "some_operand" "rJ") 1.1 root 350: (match_operand:DI 2 "const48_operand" "I")) 1.1.1.4 ! root 351: (match_operand:DI 3 "some_operand" "r")) ! 352: (match_operand:DI 4 "some_operand" "rIOKL")))] 1.1 root 353: "reload_in_progress" 1.1.1.4 ! root 354: "#" 1.1 root 355: [(set_attr "type" "iaddlog")]) 356: 1.1.1.3 root 357: (define_split 358: [(set (match_operand:DI 0 "register_operand" "=") 359: (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "") 360: (match_operand:DI 2 "const48_operand" "")) 361: (match_operand:DI 3 "register_operand" "")) 362: (match_operand:DI 4 "add_operand" "")))] 363: "reload_completed" 364: [(set (match_dup 0) 365: (plus:DI (mult:DI (match_dup 1) (match_dup 2)) (match_dup 3))) 366: (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] 367: "") 368: 1.1 root 369: (define_insn "negsi2" 370: [(set (match_operand:SI 0 "register_operand" "=r") 371: (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))] 372: "" 373: "subl $31,%1,%0" 374: [(set_attr "type" "iaddlog")]) 375: 376: (define_insn "" 377: [(set (match_operand:DI 0 "register_operand" "=r") 378: (sign_extend:DI (neg:SI 379: (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))] 380: "" 381: "subl $31,%1,%0" 382: [(set_attr "type" "iaddlog")]) 383: 384: (define_insn "negdi2" 385: [(set (match_operand:DI 0 "register_operand" "=r") 386: (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))] 387: "" 388: "subq $31,%1,%0" 389: [(set_attr "type" "iaddlog")]) 390: 1.1.1.3 root 391: (define_expand "subsi3" 392: [(set (match_operand:SI 0 "register_operand" "") 393: (minus:SI (match_operand:SI 1 "reg_or_0_operand" "") 394: (match_operand:SI 2 "reg_or_8bit_operand" "")))] 395: "" 396: " 397: { emit_insn (gen_rtx (SET, VOIDmode, gen_lowpart (DImode, operands[0]), 398: gen_rtx (MINUS, DImode, 399: gen_lowpart (DImode, operands[1]), 400: gen_lowpart (DImode, operands[2])))); 401: DONE; 402: 403: } ") 404: 405: (define_insn "" 1.1 root 406: [(set (match_operand:SI 0 "register_operand" "=r") 407: (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") 408: (match_operand:SI 2 "reg_or_8bit_operand" "rI")))] 409: "" 410: "subl %r1,%2,%0" 411: [(set_attr "type" "iaddlog")]) 412: 413: (define_insn "" 414: [(set (match_operand:DI 0 "register_operand" "=r") 415: (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") 416: (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))] 417: "" 418: "subl %r1,%2,%0" 419: [(set_attr "type" "iaddlog")]) 420: 421: (define_insn "subdi3" 422: [(set (match_operand:DI 0 "register_operand" "=r") 423: (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 424: (match_operand:DI 2 "reg_or_8bit_operand" "rI")))] 425: "" 426: "subq %r1,%2,%0" 427: [(set_attr "type" "iaddlog")]) 428: 429: (define_insn "" 430: [(set (match_operand:SI 0 "register_operand" "=r") 431: (minus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") 432: (match_operand:SI 2 "const48_operand" "I")) 433: (match_operand:SI 3 "reg_or_8bit_operand" "rI")))] 434: "" 435: "s%2subl %r1,%3,%0" 436: [(set_attr "type" "iaddlog")]) 437: 438: (define_insn "" 439: [(set (match_operand:DI 0 "register_operand" "=r") 440: (sign_extend:DI 441: (minus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") 442: (match_operand:SI 2 "const48_operand" "I")) 443: (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))] 444: "" 445: "s%2subl %r1,%3,%0" 446: [(set_attr "type" "iaddlog")]) 447: 448: (define_insn "" 449: [(set (match_operand:DI 0 "register_operand" "=r") 450: (minus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 451: (match_operand:DI 2 "const48_operand" "I")) 452: (match_operand:DI 3 "reg_or_8bit_operand" "rI")))] 453: "" 454: "s%2subq %r1,%3,%0" 455: [(set_attr "type" "iaddlog")]) 456: 457: (define_insn "mulsi3" 458: [(set (match_operand:SI 0 "register_operand" "=r") 459: (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") 1.1.1.3 root 460: (match_operand:SI 2 "reg_or_0_operand" "rJ")))] 1.1 root 461: "" 1.1.1.3 root 462: "mull %r1,%r2,%0" 1.1 root 463: [(set_attr "type" "imull")]) 464: 465: (define_insn "" 466: [(set (match_operand:DI 0 "register_operand" "=r") 467: (sign_extend:DI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") 1.1.1.3 root 468: (match_operand:SI 2 "reg_or_0_operand" "rJ"))))] 1.1 root 469: "" 1.1.1.3 root 470: "mull %r1,%r2,%0" 1.1 root 471: [(set_attr "type" "imull")]) 472: 473: (define_insn "muldi3" 474: [(set (match_operand:DI 0 "register_operand" "=r") 475: (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ") 1.1.1.3 root 476: (match_operand:DI 2 "reg_or_0_operand" "rJ")))] 477: "" 478: "mulq %r1,%r2,%0" 479: [(set_attr "type" "imulq")]) 480: 481: (define_insn "umuldi3_highpart" 482: [(set (match_operand:DI 0 "register_operand" "=r") 483: (truncate:DI 484: (lshiftrt:TI 485: (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r")) 486: (zero_extend:TI (match_operand:DI 2 "register_operand" "r"))) 487: (const_int 64))))] 488: "" 489: "umulh %1,%2,%0" 490: [(set_attr "type" "imulq")]) 491: 492: (define_insn "" 493: [(set (match_operand:DI 0 "register_operand" "=r") 494: (truncate:DI 495: (lshiftrt:TI 496: (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r")) 497: (match_operand:TI 2 "cint8_operand" "I")) 498: (const_int 64))))] 1.1 root 499: "" 1.1.1.3 root 500: "umulh %1,%2,%0" 1.1 root 501: [(set_attr "type" "imulq")]) 502: 503: ;; The divide and remainder operations always take their inputs from 504: ;; r24 and r25, put their output in r27, and clobber r23 and r28. 505: 506: (define_expand "divsi3" 1.1.1.3 root 507: [(set (reg:SI 24) (match_operand:SI 1 "input_operand" "")) 508: (set (reg:SI 25) (match_operand:SI 2 "input_operand" "")) 509: (parallel [(set (reg:SI 27) 510: (div:SI (reg:SI 24) 511: (reg:SI 25))) 1.1 root 512: (clobber (reg:DI 23)) 513: (clobber (reg:DI 28))]) 514: (set (match_operand:SI 0 "general_operand" "") 515: (reg:SI 27))] 516: "" 1.1.1.3 root 517: "") 1.1 root 518: 519: (define_expand "udivsi3" 1.1.1.3 root 520: [(set (reg:SI 24) (match_operand:SI 1 "input_operand" "")) 521: (set (reg:SI 25) (match_operand:SI 2 "input_operand" "")) 522: (parallel [(set (reg:SI 27) 523: (udiv:SI (reg:SI 24) 524: (reg:SI 25))) 1.1 root 525: (clobber (reg:DI 23)) 526: (clobber (reg:DI 28))]) 527: (set (match_operand:SI 0 "general_operand" "") 528: (reg:SI 27))] 529: "" 1.1.1.3 root 530: "") 1.1 root 531: 532: (define_expand "modsi3" 1.1.1.3 root 533: [(set (reg:SI 24) (match_operand:SI 1 "input_operand" "")) 534: (set (reg:SI 25) (match_operand:SI 2 "input_operand" "")) 535: (parallel [(set (reg:SI 27) 536: (mod:SI (reg:SI 24) 537: (reg:SI 25))) 1.1 root 538: (clobber (reg:DI 23)) 539: (clobber (reg:DI 28))]) 540: (set (match_operand:SI 0 "general_operand" "") 541: (reg:SI 27))] 542: "" 1.1.1.3 root 543: "") 1.1 root 544: 545: (define_expand "umodsi3" 1.1.1.3 root 546: [(set (reg:SI 24) (match_operand:SI 1 "input_operand" "")) 547: (set (reg:SI 25) (match_operand:SI 2 "input_operand" "")) 548: (parallel [(set (reg:SI 27) 549: (umod:SI (reg:SI 24) 550: (reg:SI 25))) 1.1 root 551: (clobber (reg:DI 23)) 552: (clobber (reg:DI 28))]) 553: (set (match_operand:SI 0 "general_operand" "") 554: (reg:SI 27))] 555: "" 1.1.1.3 root 556: "") 1.1 root 557: 558: (define_expand "divdi3" 1.1.1.3 root 559: [(set (reg:DI 24) (match_operand:DI 1 "input_operand" "")) 560: (set (reg:DI 25) (match_operand:DI 2 "input_operand" "")) 561: (parallel [(set (reg:DI 27) 562: (div:DI (reg:DI 24) 563: (reg:DI 25))) 1.1 root 564: (clobber (reg:DI 23)) 565: (clobber (reg:DI 28))]) 566: (set (match_operand:DI 0 "general_operand" "") 567: (reg:DI 27))] 568: "" 1.1.1.3 root 569: "") 1.1 root 570: 571: (define_expand "udivdi3" 1.1.1.3 root 572: [(set (reg:DI 24) (match_operand:DI 1 "input_operand" "")) 573: (set (reg:DI 25) (match_operand:DI 2 "input_operand" "")) 574: (parallel [(set (reg:DI 27) 575: (udiv:DI (reg:DI 24) 576: (reg:DI 25))) 1.1 root 577: (clobber (reg:DI 23)) 578: (clobber (reg:DI 28))]) 579: (set (match_operand:DI 0 "general_operand" "") 580: (reg:DI 27))] 581: "" 1.1.1.3 root 582: "") 1.1 root 583: 584: (define_expand "moddi3" 1.1.1.3 root 585: [(set (reg:DI 24) (match_operand:DI 1 "input_operand" "")) 586: (set (reg:DI 25) (match_operand:DI 2 "input_operand" "")) 587: (parallel [(set (reg:DI 27) 588: (mod:DI (reg:DI 24) 589: (reg:DI 25))) 1.1 root 590: (clobber (reg:DI 23)) 591: (clobber (reg:DI 28))]) 592: (set (match_operand:DI 0 "general_operand" "") 593: (reg:DI 27))] 594: "" 1.1.1.3 root 595: "") 1.1 root 596: 597: (define_expand "umoddi3" 1.1.1.3 root 598: [(set (reg:DI 24) (match_operand:DI 1 "input_operand" "")) 599: (set (reg:DI 25) (match_operand:DI 2 "input_operand" "")) 600: (parallel [(set (reg:DI 27) 601: (umod:DI (reg:DI 24) 602: (reg:DI 25))) 1.1 root 603: (clobber (reg:DI 23)) 604: (clobber (reg:DI 28))]) 605: (set (match_operand:DI 0 "general_operand" "") 606: (reg:DI 27))] 607: "" 1.1.1.3 root 608: "") 1.1 root 609: 610: (define_insn "" 611: [(set (reg:SI 27) 612: (match_operator:SI 1 "divmod_operator" 613: [(reg:SI 24) (reg:SI 25)])) 614: (clobber (reg:DI 23)) 615: (clobber (reg:DI 28))] 616: "" 1.1.1.2 root 617: "%E1 $24,$25,$27" 618: [(set_attr "type" "isubr")]) 1.1 root 619: 620: (define_insn "" 621: [(set (reg:DI 27) 622: (match_operator:DI 1 "divmod_operator" 623: [(reg:DI 24) (reg:DI 25)])) 624: (clobber (reg:DI 23)) 625: (clobber (reg:DI 28))] 626: "" 1.1.1.2 root 627: "%E1 $24,$25,$27" 628: [(set_attr "type" "isubr")]) 1.1 root 629: 630: ;; Next are the basic logical operations. These only exist in DImode. 631: 632: (define_insn "anddi3" 633: [(set (match_operand:DI 0 "register_operand" "=r,r,r") 634: (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ") 635: (match_operand:DI 2 "and_operand" "rI,N,MH")))] 636: "" 637: "@ 638: and %r1,%2,%0 639: bic %r1,%N2,%0 640: zapnot %r1,%m2,%0" 641: [(set_attr "type" "iaddlog,iaddlog,shiftcm")]) 642: 643: ;; There are times when we can split and AND into two AND insns. This occurs 644: ;; when we can first clear any bytes and then clear anything else. For 645: ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07". 646: ;; Only to this when running on 64-bit host since the computations are 647: ;; too messy otherwise. 648: 649: (define_split 650: [(set (match_operand:DI 0 "register_operand" "") 651: (and:DI (match_operand:DI 1 "register_operand" "") 652: (match_operand:DI 2 "const_int_operand" "")))] 653: "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)" 654: [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3))) 655: (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))] 656: " 657: { 658: unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]); 659: unsigned HOST_WIDE_INT mask2 = mask1; 660: int i; 661: 662: /* For each byte that isn't all zeros, make it all ones. */ 663: for (i = 0; i < 64; i += 8) 664: if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0) 665: mask1 |= (HOST_WIDE_INT) 0xff << i; 666: 667: /* Now turn on any bits we've just turned off. */ 668: mask2 |= ~ mask1; 669: 670: operands[3] = GEN_INT (mask1); 671: operands[4] = GEN_INT (mask2); 672: }") 673: 674: (define_insn "zero_extendqihi2" 675: [(set (match_operand:HI 0 "register_operand" "=r") 676: (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))] 677: "" 678: "zapnot %1,1,%0" 679: [(set_attr "type" "iaddlog")]) 680: 681: (define_insn "zero_extendqisi2" 682: [(set (match_operand:SI 0 "register_operand" "=r") 683: (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))] 684: "" 685: "zapnot %1,1,%0" 686: [(set_attr "type" "iaddlog")]) 687: 688: (define_insn "zero_extendqidi2" 689: [(set (match_operand:DI 0 "register_operand" "=r") 690: (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))] 691: "" 692: "zapnot %1,1,%0" 693: [(set_attr "type" "iaddlog")]) 694: 695: (define_insn "zero_extendhisi2" 696: [(set (match_operand:SI 0 "register_operand" "=r") 697: (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))] 698: "" 699: "zapnot %1,3,%0" 700: [(set_attr "type" "iaddlog")]) 701: 702: (define_insn "zero_extendhidi2" 703: [(set (match_operand:DI 0 "register_operand" "=r") 704: (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))] 705: "" 706: "zapnot %1,3,%0" 707: [(set_attr "type" "iaddlog")]) 708: 709: (define_insn "zero_extendsidi2" 710: [(set (match_operand:DI 0 "register_operand" "=r") 711: (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))] 712: "" 713: "zapnot %1,15,%0" 714: [(set_attr "type" "iaddlog")]) 715: 716: (define_insn "" 717: [(set (match_operand:DI 0 "register_operand" "=r") 718: (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")) 719: (match_operand:DI 2 "reg_or_0_operand" "rJ")))] 720: "" 721: "bic %r2,%1,%0" 722: [(set_attr "type" "iaddlog")]) 723: 724: (define_insn "iordi3" 1.1.1.3 root 725: [(set (match_operand:DI 0 "register_operand" "=r,r") 726: (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 727: (match_operand:DI 2 "or_operand" "rI,N")))] 1.1 root 728: "" 1.1.1.3 root 729: "@ 730: bis %r1,%2,%0 731: ornot %r1,%N2,%0" 1.1 root 732: [(set_attr "type" "iaddlog")]) 733: 734: (define_insn "one_cmpldi2" 735: [(set (match_operand:DI 0 "register_operand" "=r") 736: (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))] 737: "" 738: "ornot $31,%1,%0" 739: [(set_attr "type" "iaddlog")]) 740: 741: (define_insn "" 742: [(set (match_operand:DI 0 "register_operand" "=r") 743: (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")) 744: (match_operand:DI 2 "reg_or_0_operand" "rJ")))] 745: "" 746: "ornot %r2,%1,%0" 747: [(set_attr "type" "iaddlog")]) 748: 749: (define_insn "xordi3" 1.1.1.3 root 750: [(set (match_operand:DI 0 "register_operand" "=r,r") 751: (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 752: (match_operand:DI 2 "or_operand" "rI,N")))] 1.1 root 753: "" 1.1.1.3 root 754: "@ 755: xor %r1,%2,%0 756: eqv %r1,%N2,%0" 1.1 root 757: [(set_attr "type" "iaddlog")]) 758: 759: (define_insn "" 760: [(set (match_operand:DI 0 "register_operand" "=r") 1.1.1.3 root 761: (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ") 762: (match_operand:DI 2 "register_operand" "rI"))))] 1.1 root 763: "" 764: "eqv %r1,%2,%0" 765: [(set_attr "type" "iaddlog")]) 766: 767: ;; Next come the shifts and the various extract and insert operations. 768: 769: (define_insn "ashldi3" 770: [(set (match_operand:DI 0 "register_operand" "=r,r") 771: (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ") 1.1.1.2 root 772: (match_operand:DI 2 "reg_or_6bit_operand" "P,rI")))] 1.1 root 773: "" 774: "* 775: { 776: switch (which_alternative) 777: { 778: case 0: 779: if (operands[2] == const1_rtx) 780: return \"addq %r1,%r1,%0\"; 781: else 782: return \"s%P2addq %r1,0,%0\"; 783: case 1: 784: return \"sll %r1,%2,%0\"; 785: } 786: }" 787: [(set_attr "type" "iaddlog,shiftcm")]) 788: 1.1.1.4 ! root 789: ;; ??? The following pattern is made by combine, but earlier phases ! 790: ;; (specifically flow) can't handle it. This occurs in jump.c. Deal ! 791: ;; with this in a better way at some point. ! 792: ;;(define_insn "" ! 793: ;; [(set (match_operand:DI 0 "register_operand" "=r") ! 794: ;; (sign_extend:DI ! 795: ;; (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") ! 796: ;; (match_operand:DI 2 "const_int_operand" "P")) ! 797: ;; 0)))] ! 798: ;; "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3" ! 799: ;; "* ! 800: ;;{ ! 801: ;; if (operands[2] == const1_rtx) ! 802: ;; return \"addl %r1,%r1,%0\"; ! 803: ;; else ! 804: ;; return \"s%P2addl %r1,0,%0\"; ! 805: ;; }" ! 806: ;; [(set_attr "type" "iaddlog")]) 1.1 root 807: 808: (define_insn "lshrdi3" 809: [(set (match_operand:DI 0 "register_operand" "=r") 810: (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1.1.1.2 root 811: (match_operand:DI 2 "reg_or_6bit_operand" "rI")))] 1.1 root 812: "" 813: "srl %r1,%2,%0") 814: 815: (define_insn "ashrdi3" 816: [(set (match_operand:DI 0 "register_operand" "=r") 817: (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1.1.1.2 root 818: (match_operand:DI 2 "reg_or_6bit_operand" "rI")))] 1.1 root 819: "" 820: "sra %r1,%2,%0") 821: 822: (define_expand "extendqihi2" 823: [(set (match_dup 2) 824: (ashift:DI (match_operand:QI 1 "register_operand" "") 825: (const_int 56))) 826: (set (match_operand:HI 0 "register_operand" "") 827: (ashiftrt:DI (match_dup 2) 828: (const_int 56)))] 829: "" 830: " 831: { operands[0] = gen_lowpart (DImode, operands[0]); 832: operands[1] = gen_lowpart (DImode, operands[1]); 833: operands[2] = gen_reg_rtx (DImode); 834: }") 835: 836: (define_expand "extendqisi2" 837: [(set (match_dup 2) 838: (ashift:DI (match_operand:QI 1 "register_operand" "") 839: (const_int 56))) 840: (set (match_operand:SI 0 "register_operand" "") 841: (ashiftrt:DI (match_dup 2) 842: (const_int 56)))] 843: "" 844: " 845: { operands[0] = gen_lowpart (DImode, operands[0]); 846: operands[1] = gen_lowpart (DImode, operands[1]); 847: operands[2] = gen_reg_rtx (DImode); 848: }") 849: 850: (define_expand "extendqidi2" 851: [(set (match_dup 2) 852: (ashift:DI (match_operand:QI 1 "register_operand" "") 853: (const_int 56))) 854: (set (match_operand:DI 0 "register_operand" "") 855: (ashiftrt:DI (match_dup 2) 856: (const_int 56)))] 857: "" 858: " 859: { operands[1] = gen_lowpart (DImode, operands[1]); 860: operands[2] = gen_reg_rtx (DImode); 861: }") 862: 863: (define_expand "extendhisi2" 864: [(set (match_dup 2) 865: (ashift:DI (match_operand:HI 1 "register_operand" "") 866: (const_int 48))) 867: (set (match_operand:SI 0 "register_operand" "") 868: (ashiftrt:DI (match_dup 2) 869: (const_int 48)))] 870: "" 871: " 872: { operands[0] = gen_lowpart (DImode, operands[0]); 873: operands[1] = gen_lowpart (DImode, operands[1]); 874: operands[2] = gen_reg_rtx (DImode); 875: }") 876: 877: (define_expand "extendhidi2" 878: [(set (match_dup 2) 879: (ashift:DI (match_operand:HI 1 "register_operand" "") 880: (const_int 48))) 881: (set (match_operand:DI 0 "register_operand" "") 882: (ashiftrt:DI (match_dup 2) 883: (const_int 48)))] 884: "" 885: " 886: { operands[1] = gen_lowpart (DImode, operands[1]); 887: operands[2] = gen_reg_rtx (DImode); 888: }") 889: 890: (define_insn "" 891: [(set (match_operand:DI 0 "register_operand" "=r") 892: (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 893: (match_operand:DI 2 "mode_width_operand" "n") 894: (match_operand:DI 3 "mul8_operand" "I")))] 895: "" 896: "ext%M2l %r1,%s3,%0") 897: 898: (define_insn "" 899: [(set (match_operand:DI 0 "register_operand" "=r") 900: (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 901: (match_operand:DI 2 "mode_width_operand" "n") 902: (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI") 903: (const_int 3))))] 904: "" 905: "ext%M2l %r1,%3,%0") 906: 907: (define_insn "" 908: [(set (match_operand:DI 0 "register_operand" "=r") 909: (ashift:DI 910: (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 911: (const_int 8) 912: (ashift:DI 913: (plus:DI 914: (match_operand:DI 2 "reg_or_8bit_operand" "rI") 915: (const_int -1)) 916: (const_int 3))) 917: (const_int 56)))] 918: "" 919: "extqh %r1,%2,%0") 920: 921: (define_insn "" 922: [(set (match_operand:DI 0 "register_operand" "=r") 923: (ashift:DI 924: (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 925: (const_int 16) 926: (ashift:DI 927: (plus:DI 928: (match_operand:DI 2 "reg_or_8bit_operand" "rI") 929: (const_int -2)) 930: (const_int 3))) 931: (const_int 48)))] 932: "" 933: "extwh %r1,%2,%0") 934: 935: (define_insn "" 936: [(set (match_operand:DI 0 "register_operand" "=r") 937: (ashift:DI 938: (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 939: (const_int 32) 940: (ashift:DI 941: (plus:DI 942: (match_operand:DI 2 "reg_or_8bit_operand" "rI") 943: (const_int -4)) 944: (const_int 3))) 945: (const_int 32)))] 946: "" 947: "extlh %r1,%2,%0") 948: 949: ;; This converts an extXl into an extXh with an appropriate adjustment 950: ;; to the address calculation. 951: 952: (define_split 953: [(set (match_operand:DI 0 "register_operand" "") 954: (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "") 955: (match_operand:DI 2 "mode_width_operand" "") 956: (ashift:DI (match_operand:DI 3 "" "") 957: (const_int 3))) 958: (match_operand:DI 4 "const_int_operand" ""))) 959: (clobber (match_operand:DI 5 "register_operand" ""))] 960: "INTVAL (operands[4]) == 64 - INTVAL (operands[2])" 961: [(set (match_dup 5) (match_dup 6)) 962: (set (match_dup 0) 963: (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2) 964: (ashift:DI (plus:DI (match_dup 5) 965: (match_dup 7)) 966: (const_int 3))) 967: (match_dup 4)))] 968: " 969: { 970: operands[6] = plus_constant (operands[3], 971: INTVAL (operands[2]) / BITS_PER_UNIT); 972: operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT); 973: }") 974: 975: (define_insn "" 976: [(set (match_operand:DI 0 "register_operand" "=r") 977: (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r")) 978: (match_operand:DI 2 "mul8_operand" "I")))] 979: "" 980: "insbl %1,%s2,%0") 981: 982: (define_insn "" 983: [(set (match_operand:DI 0 "register_operand" "=r") 984: (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r")) 985: (match_operand:DI 2 "mul8_operand" "I")))] 986: "" 987: "inswl %1,%s2,%0") 988: 989: (define_insn "" 990: [(set (match_operand:DI 0 "register_operand" "=r") 991: (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) 992: (match_operand:DI 2 "mul8_operand" "I")))] 993: "" 994: "insll %1,%s2,%0") 995: 996: (define_insn "" 997: [(set (match_operand:DI 0 "register_operand" "=r") 998: (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r")) 999: (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1000: (const_int 3))))] 1001: "" 1002: "insbl %1,%2,%0") 1003: 1004: (define_insn "" 1005: [(set (match_operand:DI 0 "register_operand" "=r") 1006: (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r")) 1007: (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1008: (const_int 3))))] 1009: "" 1010: "inswl %1,%2,%0") 1011: 1012: (define_insn "" 1013: [(set (match_operand:DI 0 "register_operand" "=r") 1014: (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) 1015: (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1016: (const_int 3))))] 1017: "" 1018: "insll %1,%2,%0") 1019: 1020: ;; We do not include the insXh insns because they are complex to express 1021: ;; and it does not appear that we would ever want to generate them. 1022: 1023: (define_insn "" 1024: [(set (match_operand:DI 0 "register_operand" "=r") 1.1.1.3 root 1025: (and:DI (not:DI (ashift:DI 1026: (match_operand:DI 2 "mode_mask_operand" "n") 1027: (ashift:DI 1028: (match_operand:DI 3 "reg_or_8bit_operand" "rI") 1029: (const_int 3)))) 1.1 root 1030: (match_operand:DI 1 "reg_or_0_operand" "rJ")))] 1031: "" 1032: "msk%U2l %r1,%3,%0") 1033: 1034: ;; We do not include the mskXh insns because it does not appear we would ever 1035: ;; generate one. 1036: 1037: ;; Floating-point operations. All the double-precision insns can extend 1038: ;; from single, so indicate that. The exception are the ones that simply 1039: ;; play with the sign bits; it's not clear what to do there. 1040: 1041: (define_insn "abssf2" 1042: [(set (match_operand:SF 0 "register_operand" "=f") 1043: (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))] 1044: "TARGET_FP" 1045: "cpys $f31,%R1,%0" 1046: [(set_attr "type" "fpop")]) 1047: 1048: (define_insn "absdf2" 1049: [(set (match_operand:DF 0 "register_operand" "=f") 1050: (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))] 1051: "TARGET_FP" 1052: "cpys $f31,%R1,%0" 1053: [(set_attr "type" "fpop")]) 1054: 1055: (define_insn "negsf2" 1056: [(set (match_operand:SF 0 "register_operand" "=f") 1057: (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))] 1058: "TARGET_FP" 1.1.1.3 root 1059: "cpysn %R1,%R1,%0" 1.1 root 1060: [(set_attr "type" "fpop")]) 1061: 1062: (define_insn "negdf2" 1063: [(set (match_operand:DF 0 "register_operand" "=f") 1064: (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))] 1065: "TARGET_FP" 1.1.1.3 root 1066: "cpysn %R1,%R1,%0" 1.1 root 1067: [(set_attr "type" "fpop")]) 1068: 1069: (define_insn "addsf3" 1070: [(set (match_operand:SF 0 "register_operand" "=f") 1071: (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG") 1072: (match_operand:SF 2 "reg_or_fp0_operand" "fG")))] 1073: "TARGET_FP" 1074: "adds %R1,%R2,%0" 1075: [(set_attr "type" "fpop")]) 1076: 1077: (define_insn "adddf3" 1078: [(set (match_operand:DF 0 "register_operand" "=f") 1079: (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG") 1080: (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] 1081: "TARGET_FP" 1082: "addt %R1,%R2,%0" 1083: [(set_attr "type" "fpop")]) 1084: 1085: (define_insn "" 1086: [(set (match_operand:DF 0 "register_operand" "=f") 1087: (plus:DF (float_extend:DF 1.1.1.2 root 1088: (match_operand:SF 1 "reg_or_fp0_operand" "fG")) 1.1 root 1089: (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] 1090: "TARGET_FP" 1091: "addt %R1,%R2,%0" 1092: [(set_attr "type" "fpop")]) 1093: 1094: (define_insn "" 1095: [(set (match_operand:DF 0 "register_operand" "=f") 1096: (plus:DF (float_extend:DF 1097: (match_operand:SF 1 "reg_or_fp0_operand" "%fG")) 1098: (float_extend:DF 1099: (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))] 1100: "TARGET_FP" 1101: "addt %R1,%R2,%0" 1102: [(set_attr "type" "fpop")]) 1103: 1104: (define_insn "fix_truncdfdi2" 1105: [(set (match_operand:DI 0 "register_operand" "=f") 1106: (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))] 1107: "TARGET_FP" 1108: "cvttqc %R1,%0" 1109: [(set_attr "type" "fpop")]) 1110: 1111: (define_insn "fix_truncsfdi2" 1112: [(set (match_operand:DI 0 "register_operand" "=f") 1113: (fix:DI (float_extend:DF 1114: (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))] 1115: "TARGET_FP" 1116: "cvttqc %R1,%0" 1117: [(set_attr "type" "fpop")]) 1118: 1119: (define_insn "floatdisf2" 1120: [(set (match_operand:SF 0 "register_operand" "=f") 1121: (float:SF (match_operand:DI 1 "register_operand" "f")))] 1122: "TARGET_FP" 1123: "cvtqs %1,%0" 1124: [(set_attr "type" "fpop")]) 1125: 1126: (define_insn "floatdidf2" 1127: [(set (match_operand:DF 0 "register_operand" "=f") 1128: (float:DF (match_operand:DI 1 "register_operand" "f")))] 1129: "TARGET_FP" 1130: "cvtqt %1,%0" 1131: [(set_attr "type" "fpop")]) 1132: 1133: (define_insn "extendsfdf2" 1134: [(set (match_operand:DF 0 "register_operand" "=f,f") 1135: (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))] 1136: "TARGET_FP" 1137: "@ 1138: addt $f31,%1,%0 1139: lds %0,%1" 1140: [(set_attr "type" "fpop,ld")]) 1141: 1142: (define_insn "truncdfsf2" 1143: [(set (match_operand:SF 0 "register_operand" "=f") 1144: (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))] 1145: "TARGET_FP" 1146: "cvtts %R1,%0" 1147: [(set_attr "type" "fpop")]) 1148: 1149: (define_insn "divsf3" 1150: [(set (match_operand:SF 0 "register_operand" "=f") 1151: (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG") 1152: (match_operand:SF 2 "reg_or_fp0_operand" "fG")))] 1153: "TARGET_FP" 1154: "divs %R1,%R2,%0" 1155: [(set_attr "type" "fdivs")]) 1156: 1157: (define_insn "divdf3" 1158: [(set (match_operand:DF 0 "register_operand" "=f") 1159: (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG") 1160: (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] 1161: "TARGET_FP" 1162: "divt %R1,%R2,%0" 1163: [(set_attr "type" "fdivt")]) 1164: 1165: (define_insn "" 1166: [(set (match_operand:DF 0 "register_operand" "=f") 1167: (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG")) 1168: (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] 1169: "TARGET_FP" 1170: "divt %R1,%R2,%0" 1171: [(set_attr "type" "fdivt")]) 1172: 1173: (define_insn "" 1174: [(set (match_operand:DF 0 "register_operand" "=f") 1175: (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG") 1176: (float_extend:DF 1177: (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))] 1178: "TARGET_FP" 1179: "divt %R1,%R2,%0" 1180: [(set_attr "type" "fdivt")]) 1181: 1182: (define_insn "" 1183: [(set (match_operand:DF 0 "register_operand" "=f") 1184: (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG")) 1185: (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))] 1186: "TARGET_FP" 1187: "divt %R1,%R2,%0" 1188: [(set_attr "type" "fdivt")]) 1189: 1190: (define_insn "mulsf3" 1191: [(set (match_operand:SF 0 "register_operand" "=f") 1.1.1.2 root 1192: (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG") 1.1 root 1193: (match_operand:SF 2 "reg_or_fp0_operand" "fG")))] 1194: "TARGET_FP" 1195: "muls %R1,%R2,%0" 1196: [(set_attr "type" "fpop")]) 1197: 1198: (define_insn "muldf3" 1199: [(set (match_operand:DF 0 "register_operand" "=f") 1.1.1.2 root 1200: (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG") 1.1 root 1201: (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] 1202: "TARGET_FP" 1203: "mult %R1,%R2,%0" 1204: [(set_attr "type" "fpop")]) 1205: 1206: (define_insn "" 1207: [(set (match_operand:DF 0 "register_operand" "=f") 1208: (mult:DF (float_extend:DF 1209: (match_operand:SF 1 "reg_or_fp0_operand" "fG")) 1210: (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] 1211: "TARGET_FP" 1212: "mult %R1,%R2,%0" 1213: [(set_attr "type" "fpop")]) 1214: 1215: (define_insn "" 1216: [(set (match_operand:DF 0 "register_operand" "=f") 1217: (mult:DF (float_extend:DF 1.1.1.2 root 1218: (match_operand:SF 1 "reg_or_fp0_operand" "%fG")) 1.1 root 1219: (float_extend:DF 1220: (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))] 1221: "TARGET_FP" 1222: "mult %R1,%R2,%0" 1223: [(set_attr "type" "fpop")]) 1224: 1225: (define_insn "subsf3" 1226: [(set (match_operand:SF 0 "register_operand" "=f") 1.1.1.2 root 1227: (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG") 1.1 root 1228: (match_operand:SF 2 "reg_or_fp0_operand" "fG")))] 1229: "TARGET_FP" 1230: "subs %R1,%R2,%0" 1231: [(set_attr "type" "fpop")]) 1232: 1233: (define_insn "subdf3" 1234: [(set (match_operand:DF 0 "register_operand" "=f") 1.1.1.2 root 1235: (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG") 1.1 root 1236: (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] 1237: "TARGET_FP" 1238: "subt %R1,%R2,%0" 1239: [(set_attr "type" "fpop")]) 1240: 1241: (define_insn "" 1242: [(set (match_operand:DF 0 "register_operand" "=f") 1243: (minus:DF (float_extend:DF 1.1.1.2 root 1244: (match_operand:SF 1 "reg_or_fp0_operand" "fG")) 1.1 root 1245: (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] 1246: "TARGET_FP" 1247: "subt %R1,%R2,%0" 1248: [(set_attr "type" "fpop")]) 1249: 1250: (define_insn "" 1251: [(set (match_operand:DF 0 "register_operand" "=f") 1.1.1.2 root 1252: (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG") 1.1 root 1253: (float_extend:DF 1254: (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))] 1255: "TARGET_FP" 1256: "subt %R1,%R2,%0" 1257: [(set_attr "type" "fpop")]) 1258: 1259: (define_insn "" 1260: [(set (match_operand:DF 0 "register_operand" "=f") 1261: (minus:DF (float_extend:DF 1.1.1.2 root 1262: (match_operand:SF 1 "reg_or_fp0_operand" "fG")) 1.1 root 1263: (float_extend:DF 1264: (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))] 1265: "TARGET_FP" 1266: "subt %R1,%R2,%0" 1267: [(set_attr "type" "fpop")]) 1268: 1269: ;; Next are all the integer comparisons, and conditional moves and branches 1270: ;; and some of the related define_expand's and define_split's. 1271: 1272: (define_insn "" 1273: [(set (match_operand:DI 0 "register_operand" "=r") 1274: (match_operator:DI 1 "alpha_comparison_operator" 1275: [(match_operand:DI 2 "reg_or_0_operand" "rJ") 1276: (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))] 1277: "" 1278: "cmp%C1 %r2,%3,%0" 1279: [(set_attr "type" "icmp")]) 1280: 1281: ;; There are three important special-case that don't fit the above pattern 1282: ;; but which we want to handle here. 1283: 1284: (define_insn "" 1285: [(set (match_operand:DI 0 "register_operand" "=r") 1286: (ne:DI (match_operand:DI 1 "register_operand" "r") 1287: (const_int 0)))] 1288: "" 1289: "cmpult $31,%1,%0" 1290: [(set_attr "type" "icmp")]) 1291: 1292: (define_insn "" 1293: [(set (match_operand:DI 0 "register_operand" "=r") 1294: (gt:DI (match_operand:DI 1 "register_operand" "r") 1295: (const_int 0)))] 1296: "" 1297: "cmplt $31,%1,%0" 1298: [(set_attr "type" "icmp")]) 1299: 1300: (define_insn "" 1301: [(set (match_operand:DI 0 "register_operand" "=r") 1302: (ge:DI (match_operand:DI 1 "register_operand" "r") 1303: (const_int 0)))] 1304: "" 1305: "cmple $31,%1,%0" 1306: [(set_attr "type" "icmp")]) 1307: 1.1.1.4 ! root 1308: ;; This pattern exists so conditional moves of SImode values are handled. ! 1309: ;; Comparisons are still done in DImode though. ! 1310: 1.1 root 1311: (define_insn "" 1.1.1.4 ! root 1312: [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 1.1 root 1313: (if_then_else:DI 1314: (match_operator 2 "signed_comparison_operator" 1.1.1.4 ! root 1315: [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J") ! 1316: (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")]) ! 1317: (match_operand:SI 1 "reg_or_8bit_operand" "rI,0,rI,0") ! 1318: (match_operand:SI 5 "reg_or_8bit_operand" "0,rI,0,rI")))] ! 1319: "operands[3] == const0_rtx || operands[4] == const0_rtx" 1.1 root 1320: "@ 1321: cmov%C2 %r3,%1,%0 1.1.1.4 ! root 1322: cmov%D2 %r3,%5,%0 ! 1323: cmov%c2 %r4,%1,%0 ! 1324: cmov%d2 %r4,%5,%0") ! 1325: ! 1326: (define_insn "" ! 1327: [(set (match_operand:DI 0 "register_operand" "=r,r,r,r") ! 1328: (if_then_else:DI ! 1329: (match_operator 2 "signed_comparison_operator" ! 1330: [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J") ! 1331: (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")]) ! 1332: (match_operand:DI 1 "reg_or_8bit_operand" "rI,0,rI,0") ! 1333: (match_operand:DI 5 "reg_or_8bit_operand" "0,rI,0,rI")))] ! 1334: "operands[3] == const0_rtx || operands[4] == const0_rtx" ! 1335: "@ ! 1336: cmov%C2 %r3,%1,%0 ! 1337: cmov%D2 %r3,%5,%0 ! 1338: cmov%c2 %r4,%1,%0 ! 1339: cmov%d2 %r4,%5,%0") 1.1 root 1340: 1341: (define_insn "" 1342: [(set (match_operand:DI 0 "register_operand" "=r,r") 1343: (if_then_else:DI 1344: (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") 1345: (const_int 1) 1346: (const_int 0)) 1347: (const_int 0)) 1348: (match_operand:DI 1 "reg_or_8bit_operand" "rI,0") 1349: (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))] 1350: "" 1351: "@ 1352: cmovlbc %r2,%1,%0 1353: cmovlbs %r2,%3,%0") 1354: 1355: (define_insn "" 1356: [(set (match_operand:DI 0 "register_operand" "=r,r") 1357: (if_then_else:DI 1358: (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") 1359: (const_int 1) 1360: (const_int 0)) 1361: (const_int 0)) 1362: (match_operand:DI 1 "reg_or_8bit_operand" "rI,0") 1363: (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))] 1364: "" 1365: "@ 1366: cmovlbs %r2,%1,%0 1367: cmovlbc %r2,%3,%0") 1368: 1369: ;; This form is added since combine thinks that an IF_THEN_ELSE with both 1370: ;; arms constant is a single insn, so it won't try to form it if combine 1371: ;; knows they are really two insns. This occurs in divides by powers 1372: ;; of two. 1373: 1374: (define_insn "" 1375: [(set (match_operand:DI 0 "register_operand" "=r") 1376: (if_then_else:DI 1377: (match_operator 2 "signed_comparison_operator" 1378: [(match_operand:DI 3 "reg_or_0_operand" "rJ") 1379: (const_int 0)]) 1380: (plus:DI (match_dup 0) 1381: (match_operand:DI 1 "reg_or_8bit_operand" "rI")) 1382: (match_dup 0))) 1383: (clobber (match_scratch:DI 4 "=&r"))] 1384: "" 1385: "addq %0,%1,%4\;cmov%C2 %r3,%4,%0") 1386: 1387: (define_split 1388: [(set (match_operand:DI 0 "register_operand" "") 1389: (if_then_else:DI 1390: (match_operator 2 "signed_comparison_operator" 1391: [(match_operand:DI 3 "reg_or_0_operand" "") 1392: (const_int 0)]) 1393: (plus:DI (match_dup 0) 1394: (match_operand:DI 1 "reg_or_8bit_operand" "")) 1395: (match_dup 0))) 1396: (clobber (match_operand:DI 4 "register_operand" ""))] 1397: "" 1398: [(set (match_dup 4) (plus:DI (match_dup 0) (match_dup 1))) 1399: (set (match_dup 0) (if_then_else:DI (match_op_dup 2 1400: [(match_dup 3) 1401: (const_int 0)]) 1402: (match_dup 4) (match_dup 0)))] 1403: "") 1404: 1405: (define_split 1406: [(parallel 1407: [(set (match_operand:DI 0 "register_operand" "") 1408: (if_then_else:DI 1409: (match_operator 1 "comparison_operator" 1410: [(zero_extract:DI (match_operand:DI 2 "register_operand" "") 1411: (const_int 1) 1412: (match_operand:DI 3 "const_int_operand" "")) 1413: (const_int 0)]) 1414: (match_operand:DI 4 "reg_or_8bit_operand" "") 1415: (match_operand:DI 5 "reg_or_8bit_operand" ""))) 1416: (clobber (match_operand:DI 6 "register_operand" ""))])] 1417: "INTVAL (operands[3]) != 0" 1418: [(set (match_dup 6) 1419: (lshiftrt:DI (match_dup 2) (match_dup 3))) 1420: (set (match_dup 0) 1421: (if_then_else:DI (match_op_dup 1 1422: [(zero_extract:DI (match_dup 6) 1423: (const_int 1) 1424: (const_int 0)) 1425: (const_int 0)]) 1426: (match_dup 4) 1427: (match_dup 5)))] 1428: "") 1429: 1430: ;; For ABS, we have two choices, depending on whether the input and output 1431: ;; registers are the same or not. 1432: (define_expand "absdi2" 1433: [(set (match_operand:DI 0 "register_operand" "") 1434: (abs:DI (match_operand:DI 1 "register_operand" "")))] 1435: "" 1436: " 1437: { if (rtx_equal_p (operands[0], operands[1])) 1438: emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode))); 1439: else 1440: emit_insn (gen_absdi2_diff (operands[0], operands[1])); 1441: 1442: DONE; 1443: }") 1444: 1445: (define_expand "absdi2_same" 1446: [(set (match_operand:DI 1 "register_operand" "") 1447: (neg:DI (match_operand:DI 0 "register_operand" ""))) 1448: (set (match_dup 0) 1449: (if_then_else:DI (ge (match_dup 0) (const_int 0)) 1450: (match_dup 0) 1451: (match_dup 1)))] 1452: "" 1453: "") 1454: 1455: (define_expand "absdi2_diff" 1456: [(set (match_operand:DI 0 "register_operand" "") 1457: (neg:DI (match_operand:DI 1 "register_operand" ""))) 1458: (set (match_dup 0) 1459: (if_then_else:DI (lt (match_dup 1) (const_int 0)) 1460: (match_dup 0) 1461: (match_dup 1)))] 1462: "" 1463: "") 1464: 1465: (define_split 1466: [(set (match_operand:DI 0 "register_operand" "") 1467: (abs:DI (match_dup 0))) 1468: (clobber (match_operand:DI 2 "register_operand" ""))] 1469: "" 1470: [(set (match_dup 1) (neg:DI (match_dup 0))) 1471: (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0)) 1472: (match_dup 0) (match_dup 1)))] 1473: "") 1474: 1475: (define_split 1476: [(set (match_operand:DI 0 "register_operand" "") 1477: (abs:DI (match_operand:DI 1 "register_operand" "")))] 1478: "! rtx_equal_p (operands[0], operands[1])" 1479: [(set (match_dup 0) (neg:DI (match_dup 1))) 1480: (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0)) 1481: (match_dup 0) (match_dup 1)))] 1482: "") 1483: 1484: (define_split 1485: [(set (match_operand:DI 0 "register_operand" "") 1486: (neg:DI (abs:DI (match_dup 0)))) 1487: (clobber (match_operand:DI 2 "register_operand" ""))] 1488: "" 1489: [(set (match_dup 1) (neg:DI (match_dup 0))) 1490: (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0)) 1491: (match_dup 0) (match_dup 1)))] 1492: "") 1493: 1494: (define_split 1495: [(set (match_operand:DI 0 "register_operand" "") 1496: (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))] 1497: "! rtx_equal_p (operands[0], operands[1])" 1498: [(set (match_dup 0) (neg:DI (match_dup 1))) 1499: (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0)) 1500: (match_dup 0) (match_dup 1)))] 1501: "") 1502: 1.1.1.2 root 1503: (define_expand "smaxdi3" 1.1 root 1504: [(set (match_dup 3) 1505: (le:DI (match_operand:DI 1 "reg_or_0_operand" "") 1506: (match_operand:DI 2 "reg_or_8bit_operand" ""))) 1507: (set (match_operand:DI 0 "register_operand" "") 1508: (if_then_else:DI (eq (match_dup 3) (const_int 0)) 1509: (match_dup 1) (match_dup 2)))] 1510: "" 1511: " 1512: { operands[3] = gen_reg_rtx (DImode); 1513: }") 1514: 1515: (define_split 1516: [(set (match_operand:DI 0 "register_operand" "") 1517: (smax:DI (match_operand:DI 1 "reg_or_0_operand" "") 1518: (match_operand:DI 2 "reg_or_8bit_operand" ""))) 1519: (clobber (match_operand:DI 3 "register_operand" ""))] 1520: "operands[2] != const0_rtx" 1521: [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2))) 1522: (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0)) 1523: (match_dup 1) (match_dup 2)))] 1524: "") 1525: 1526: (define_insn "" 1527: [(set (match_operand:DI 0 "register_operand" "=r") 1528: (smax:DI (match_operand:DI 1 "register_operand" "0") 1529: (const_int 0)))] 1530: "" 1531: "cmovlt %0,0,%0") 1532: 1533: (define_expand "smindi3" 1534: [(set (match_dup 3) 1535: (lt:DI (match_operand:DI 1 "reg_or_0_operand" "") 1536: (match_operand:DI 2 "reg_or_8bit_operand" ""))) 1537: (set (match_operand:DI 0 "register_operand" "") 1538: (if_then_else:DI (ne (match_dup 3) (const_int 0)) 1539: (match_dup 1) (match_dup 2)))] 1540: "" 1541: " 1542: { operands[3] = gen_reg_rtx (DImode); 1543: }") 1544: 1545: (define_split 1546: [(set (match_operand:DI 0 "register_operand" "") 1547: (smin:DI (match_operand:DI 1 "reg_or_0_operand" "") 1548: (match_operand:DI 2 "reg_or_8bit_operand" ""))) 1549: (clobber (match_operand:DI 3 "register_operand" ""))] 1550: "operands[2] != const0_rtx" 1551: [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2))) 1552: (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0)) 1553: (match_dup 1) (match_dup 2)))] 1554: "") 1555: 1556: (define_insn "" 1557: [(set (match_operand:DI 0 "register_operand" "=r") 1558: (smin:DI (match_operand:DI 1 "register_operand" "0") 1559: (const_int 0)))] 1560: "" 1561: "cmovgt %0,0,%0") 1562: 1563: (define_expand "umaxdi3" 1564: [(set (match_dup 3) 1565: (leu:DI (match_operand:DI 1 "reg_or_0_operand" "") 1566: (match_operand:DI 2 "reg_or_8bit_operand" ""))) 1567: (set (match_operand:DI 0 "register_operand" "") 1568: (if_then_else:DI (eq (match_dup 3) (const_int 0)) 1569: (match_dup 1) (match_dup 2)))] 1570: "" 1571: " 1572: { operands[3] = gen_reg_rtx (DImode); 1573: }") 1574: 1575: (define_split 1576: [(set (match_operand:DI 0 "register_operand" "") 1577: (umax:DI (match_operand:DI 1 "reg_or_0_operand" "") 1578: (match_operand:DI 2 "reg_or_8bit_operand" ""))) 1579: (clobber (match_operand:DI 3 "register_operand" ""))] 1580: "operands[2] != const0_rtx" 1581: [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2))) 1582: (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0)) 1583: (match_dup 1) (match_dup 2)))] 1584: "") 1585: 1586: (define_expand "umindi3" 1587: [(set (match_dup 3) 1588: (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "") 1589: (match_operand:DI 2 "reg_or_8bit_operand" ""))) 1590: (set (match_operand:DI 0 "register_operand" "") 1591: (if_then_else:DI (ne (match_dup 3) (const_int 0)) 1592: (match_dup 1) (match_dup 2)))] 1593: "" 1594: " 1595: { operands[3] = gen_reg_rtx (DImode); 1596: }") 1597: 1598: (define_split 1599: [(set (match_operand:DI 0 "register_operand" "") 1600: (umin:DI (match_operand:DI 1 "reg_or_0_operand" "") 1601: (match_operand:DI 2 "reg_or_8bit_operand" ""))) 1602: (clobber (match_operand:DI 3 "register_operand" ""))] 1603: "operands[2] != const0_rtx" 1604: [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2))) 1605: (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0)) 1606: (match_dup 1) (match_dup 2)))] 1607: "") 1608: 1609: (define_insn "" 1610: [(set (pc) 1611: (if_then_else 1612: (match_operator 1 "signed_comparison_operator" 1613: [(match_operand:DI 2 "reg_or_0_operand" "rJ") 1614: (const_int 0)]) 1615: (label_ref (match_operand 0 "" "")) 1616: (pc)))] 1617: "" 1618: "b%C1 %r2,%0" 1619: [(set_attr "type" "ibr")]) 1620: 1621: (define_insn "" 1622: [(set (pc) 1623: (if_then_else 1624: (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1625: (const_int 1) 1626: (const_int 0)) 1627: (const_int 0)) 1628: (label_ref (match_operand 0 "" "")) 1629: (pc)))] 1630: "" 1631: "blbs %r1,%0" 1632: [(set_attr "type" "ibr")]) 1633: 1634: (define_insn "" 1635: [(set (pc) 1636: (if_then_else 1637: (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1638: (const_int 1) 1639: (const_int 0)) 1640: (const_int 0)) 1641: (label_ref (match_operand 0 "" "")) 1642: (pc)))] 1643: "" 1644: "blbc %r1,%0" 1645: [(set_attr "type" "ibr")]) 1646: 1647: (define_split 1648: [(parallel 1649: [(set (pc) 1650: (if_then_else 1651: (match_operator 1 "comparison_operator" 1652: [(zero_extract:DI (match_operand:DI 2 "register_operand" "") 1653: (const_int 1) 1654: (match_operand:DI 3 "const_int_operand" "")) 1655: (const_int 0)]) 1656: (label_ref (match_operand 0 "" "")) 1657: (pc))) 1658: (clobber (match_operand:DI 4 "register_operand" ""))])] 1659: "INTVAL (operands[3]) != 0" 1660: [(set (match_dup 4) 1661: (lshiftrt:DI (match_dup 2) (match_dup 3))) 1662: (set (pc) 1663: (if_then_else (match_op_dup 1 1664: [(zero_extract:DI (match_dup 4) 1665: (const_int 1) 1666: (const_int 0)) 1667: (const_int 0)]) 1668: (label_ref (match_dup 0)) 1669: (pc)))] 1670: "") 1671: 1672: ;; The following are the corresponding floating-point insns. Recall 1673: ;; we need to have variants that expand the arguments from SF mode 1674: ;; to DFmode. 1675: 1676: (define_insn "" 1677: [(set (match_operand:DF 0 "register_operand" "=f") 1678: (match_operator:DF 1 "alpha_comparison_operator" 1679: [(match_operand:DF 2 "reg_or_fp0_operand" "fG") 1680: (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))] 1681: "TARGET_FP" 1682: "cmpt%C1 %R2,%R3,%0" 1683: [(set_attr "type" "fpop")]) 1684: 1685: (define_insn "" 1686: [(set (match_operand:DF 0 "register_operand" "=f") 1687: (match_operator:DF 1 "alpha_comparison_operator" 1688: [(float_extend:DF 1689: (match_operand:SF 2 "reg_or_fp0_operand" "fG")) 1690: (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))] 1691: "TARGET_FP" 1692: "cmpt%C1 %R2,%R3,%0" 1693: [(set_attr "type" "fpop")]) 1694: 1695: (define_insn "" 1696: [(set (match_operand:DF 0 "register_operand" "=f") 1697: (match_operator:DF 1 "alpha_comparison_operator" 1698: [(match_operand:DF 2 "reg_or_fp0_operand" "fG") 1699: (float_extend:DF 1700: (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))] 1701: "TARGET_FP" 1702: "cmpt%C1 %R2,%R3,%0" 1703: [(set_attr "type" "fpop")]) 1704: 1705: (define_insn "" 1706: [(set (match_operand:DF 0 "register_operand" "=f") 1707: (match_operator:DF 1 "alpha_comparison_operator" 1708: [(float_extend:DF 1709: (match_operand:SF 2 "reg_or_fp0_operand" "fG")) 1710: (float_extend:DF 1711: (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))] 1712: "TARGET_FP" 1713: "cmpt%C1 %R2,%R3,%0" 1714: [(set_attr "type" "fpop")]) 1715: 1716: (define_insn "" 1717: [(set (match_operand:DF 0 "register_operand" "=f,f") 1718: (if_then_else:DF 1719: (match_operator 3 "signed_comparison_operator" 1720: [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG") 1721: (match_operand:DF 2 "fp0_operand" "G,G")]) 1722: (match_operand:DF 1 "reg_or_fp0_operand" "fG,0") 1723: (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))] 1724: "TARGET_FP" 1725: "@ 1726: fcmov%C3 %R4,%R1,%0 1727: fcmov%D3 %R4,%R5,%0" 1728: [(set_attr "type" "fpop")]) 1729: 1730: (define_insn "" 1731: [(set (match_operand:SF 0 "register_operand" "=f,f") 1732: (if_then_else:SF 1733: (match_operator 3 "signed_comparison_operator" 1734: [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG") 1735: (match_operand:DF 2 "fp0_operand" "G,G")]) 1736: (match_operand:SF 1 "reg_or_fp0_operand" "fG,0") 1737: (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))] 1738: "TARGET_FP" 1739: "@ 1740: fcmov%C3 %R4,%R1,%0 1741: fcmov%D3 %R4,%R5,%0" 1742: [(set_attr "type" "fpop")]) 1743: 1744: (define_insn "" 1745: [(set (match_operand:DF 0 "register_operand" "=f,f") 1746: (if_then_else:DF 1747: (match_operator 3 "signed_comparison_operator" 1748: [(match_operand:DF 1 "reg_or_fp0_operand" "fG,fG") 1749: (match_operand:DF 2 "fp0_operand" "G,G")]) 1750: (float_extend:DF (match_operand:SF 4 "reg_or_fp0_operand" "fG,0")) 1751: (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))] 1752: "TARGET_FP" 1753: "@ 1754: fcmov%C3 %R4,%R1,%0 1755: fcmov%D3 %R4,%R5,%0" 1756: [(set_attr "type" "fpop")]) 1757: 1758: (define_insn "" 1759: [(set (match_operand:DF 0 "register_operand" "=f,f") 1760: (if_then_else:DF 1761: (match_operator 3 "signed_comparison_operator" 1762: [(float_extend:DF 1763: (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG")) 1764: (match_operand:DF 2 "fp0_operand" "G,G")]) 1765: (match_operand:DF 1 "reg_or_fp0_operand" "fG,0") 1766: (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))] 1767: "TARGET_FP" 1768: "@ 1769: fcmov%C3 %R4,%R1,%0 1770: fcmov%D3 %R4,%R5,%0" 1771: [(set_attr "type" "fpop")]) 1772: 1773: (define_insn "" 1774: [(set (match_operand:SF 0 "register_operand" "=f,f") 1775: (if_then_else:SF 1776: (match_operator 3 "signed_comparison_operator" 1777: [(float_extend:DF 1778: (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG")) 1779: (match_operand:DF 2 "fp0_operand" "G,G")]) 1780: (match_operand:SF 1 "reg_or_fp0_operand" "fG,0") 1781: (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))] 1782: "TARGET_FP" 1783: "@ 1784: fcmov%C3 %R4,%R1,%0 1785: fcmov%D3 %R4,%R5,%0" 1786: [(set_attr "type" "fpop")]) 1787: 1788: (define_insn "" 1789: [(set (match_operand:DF 0 "register_operand" "=f,f") 1790: (if_then_else:DF 1791: (match_operator 3 "signed_comparison_operator" 1792: [(float_extend:DF 1793: (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG")) 1794: (match_operand:DF 2 "fp0_operand" "G,G")]) 1795: (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")) 1796: (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))] 1797: "TARGET_FP" 1798: "@ 1799: fcmov%C3 %R4,%R1,%0 1800: fcmov%D3 %R4,%R5,%0" 1801: [(set_attr "type" "fpop")]) 1802: 1803: (define_expand "maxdf3" 1804: [(set (match_dup 3) 1805: (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "") 1806: (match_operand:DF 2 "reg_or_fp0_operand" ""))) 1807: (set (match_operand:DF 0 "register_operand" "") 1.1.1.3 root 1808: (if_then_else:DF (eq (match_dup 3) (match_dup 4)) 1.1 root 1809: (match_dup 1) (match_dup 2)))] 1810: "TARGET_FP" 1811: " 1812: { operands[3] = gen_reg_rtx (DFmode); 1.1.1.3 root 1813: operands[4] = CONST0_RTX (DFmode); 1.1 root 1814: }") 1815: 1816: (define_expand "mindf3" 1817: [(set (match_dup 3) 1818: (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "") 1819: (match_operand:DF 2 "reg_or_fp0_operand" ""))) 1820: (set (match_operand:DF 0 "register_operand" "") 1.1.1.3 root 1821: (if_then_else:DF (ne (match_dup 3) (match_dup 4)) 1.1 root 1822: (match_dup 1) (match_dup 2)))] 1823: "TARGET_FP" 1824: " 1825: { operands[3] = gen_reg_rtx (DFmode); 1.1.1.3 root 1826: operands[4] = CONST0_RTX (DFmode); 1.1 root 1827: }") 1828: 1829: (define_expand "maxsf3" 1830: [(set (match_dup 3) 1.1.1.3 root 1831: (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "")) 1.1 root 1832: (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "")))) 1833: (set (match_operand:SF 0 "register_operand" "") 1.1.1.3 root 1834: (if_then_else:SF (eq (match_dup 3) (match_dup 4)) 1.1 root 1835: (match_dup 1) (match_dup 2)))] 1836: "TARGET_FP" 1837: " 1.1.1.3 root 1838: { operands[3] = gen_reg_rtx (DFmode); 1839: operands[4] = CONST0_RTX (DFmode); 1.1 root 1840: }") 1841: 1842: (define_expand "minsf3" 1843: [(set (match_dup 3) 1.1.1.3 root 1844: (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "")) 1.1 root 1845: (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "")))) 1846: (set (match_operand:SF 0 "register_operand" "") 1.1.1.3 root 1847: (if_then_else:SF (ne (match_dup 3) (match_dup 4)) 1.1 root 1848: (match_dup 1) (match_dup 2)))] 1849: "TARGET_FP" 1850: " 1.1.1.3 root 1851: { operands[3] = gen_reg_rtx (DFmode); 1852: operands[4] = CONST0_RTX (DFmode); 1.1 root 1853: }") 1854: 1855: (define_insn "" 1856: [(set (pc) 1857: (if_then_else 1858: (match_operator 1 "signed_comparison_operator" 1859: [(match_operand:DF 2 "reg_or_fp0_operand" "fG") 1860: (match_operand:DF 3 "fp0_operand" "G")]) 1861: (label_ref (match_operand 0 "" "")) 1862: (pc)))] 1863: "TARGET_FP" 1864: "fb%C1 %R2,%0" 1865: [(set_attr "type" "fbr")]) 1866: 1867: (define_insn "" 1868: [(set (pc) 1869: (if_then_else 1870: (match_operator 1 "signed_comparison_operator" 1871: [(float_extend:DF 1872: (match_operand:SF 2 "reg_or_fp0_operand" "fG")) 1873: (match_operand:DF 3 "fp0_operand" "G")]) 1874: (label_ref (match_operand 0 "" "")) 1875: (pc)))] 1876: "TARGET_FP" 1877: "fb%C1 %R2,%0" 1878: [(set_attr "type" "fbr")]) 1879: 1880: ;; These are the main define_expand's used to make conditional branches 1881: ;; and compares. 1882: 1883: (define_expand "cmpdf" 1884: [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "") 1885: (match_operand:DF 1 "reg_or_fp0_operand" "")))] 1.1.1.4 ! root 1886: "TARGET_FP" 1.1 root 1887: " 1888: { 1889: alpha_compare_op0 = operands[0]; 1890: alpha_compare_op1 = operands[1]; 1891: alpha_compare_fp_p = 1; 1892: DONE; 1893: }") 1894: 1895: (define_expand "cmpdi" 1896: [(set (cc0) (compare (match_operand:DI 0 "reg_or_0_operand" "") 1897: (match_operand:DI 1 "reg_or_8bit_operand" "")))] 1898: "" 1899: " 1900: { 1901: alpha_compare_op0 = operands[0]; 1902: alpha_compare_op1 = operands[1]; 1903: alpha_compare_fp_p = 0; 1904: DONE; 1905: }") 1906: 1907: (define_expand "beq" 1908: [(set (match_dup 1) (match_dup 2)) 1909: (set (pc) 1910: (if_then_else (match_dup 3) 1911: (label_ref (match_operand 0 "" "")) 1912: (pc)))] 1913: "" 1914: " 1915: { 1916: enum machine_mode mode; 1917: enum rtx_code compare_code, branch_code; 1918: 1919: if (alpha_compare_fp_p) 1920: mode = DFmode, compare_code = EQ, branch_code = NE; 1921: else 1922: { 1923: mode = DImode, compare_code = MINUS, branch_code = EQ; 1924: if (GET_CODE (alpha_compare_op1) == CONST_INT) 1925: { 1926: compare_code = PLUS; 1927: alpha_compare_op1 = GEN_INT (- INTVAL (alpha_compare_op1)); 1928: } 1929: } 1930: 1931: operands[1] = gen_reg_rtx (mode); 1932: operands[2] = gen_rtx (compare_code, mode, 1933: alpha_compare_op0, alpha_compare_op1); 1934: operands[3] = gen_rtx (branch_code, VOIDmode, 1935: operands[1], CONST0_RTX (mode)); 1936: }") 1937: 1938: (define_expand "bne" 1939: [(set (match_dup 1) (match_dup 2)) 1940: (set (pc) 1941: (if_then_else (match_dup 3) 1942: (label_ref (match_operand 0 "" "")) 1943: (pc)))] 1944: "" 1945: " 1946: { 1947: enum machine_mode mode; 1948: enum rtx_code compare_code, branch_code; 1949: 1950: if (alpha_compare_fp_p) 1951: mode = DFmode, compare_code = EQ, branch_code = EQ; 1952: else 1953: { 1954: mode = DImode, compare_code = MINUS, branch_code = NE; 1955: if (GET_CODE (alpha_compare_op1) == CONST_INT) 1956: { 1957: compare_code = PLUS; 1958: alpha_compare_op1 = GEN_INT (- INTVAL (alpha_compare_op1)); 1959: } 1960: } 1961: 1962: operands[1] = gen_reg_rtx (mode); 1963: operands[2] = gen_rtx (compare_code, mode, 1964: alpha_compare_op0, alpha_compare_op1); 1965: operands[3] = gen_rtx (branch_code, VOIDmode, 1966: operands[1], CONST0_RTX (mode)); 1967: }") 1968: 1969: (define_expand "blt" 1970: [(set (match_dup 1) (match_dup 2)) 1971: (set (pc) 1972: (if_then_else (match_dup 3) 1973: (label_ref (match_operand 0 "" "")) 1974: (pc)))] 1975: "" 1976: " 1977: { 1978: enum machine_mode mode = alpha_compare_fp_p ? DFmode : DImode; 1979: operands[1] = gen_reg_rtx (mode); 1980: operands[2] = gen_rtx (LT, mode, alpha_compare_op0, alpha_compare_op1); 1981: operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (mode)); 1982: }") 1983: 1984: (define_expand "ble" 1985: [(set (match_dup 1) (match_dup 2)) 1986: (set (pc) 1987: (if_then_else (match_dup 3) 1988: (label_ref (match_operand 0 "" "")) 1989: (pc)))] 1990: "" 1991: " 1992: { 1993: enum machine_mode mode = alpha_compare_fp_p ? DFmode : DImode; 1994: operands[1] = gen_reg_rtx (mode); 1995: operands[2] = gen_rtx (LE, mode, alpha_compare_op0, alpha_compare_op1); 1996: operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (mode)); 1997: }") 1998: 1999: (define_expand "bgt" 2000: [(set (match_dup 1) (match_dup 2)) 2001: (set (pc) 2002: (if_then_else (match_dup 3) 2003: (label_ref (match_operand 0 "" "")) 2004: (pc)))] 2005: "" 2006: " 2007: { 2008: if (alpha_compare_fp_p) 2009: { 2010: operands[1] = gen_reg_rtx (DFmode); 2011: operands[2] = gen_rtx (LT, DFmode, alpha_compare_op1, alpha_compare_op0); 2012: operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (DFmode)); 2013: } 2014: else 2015: { 2016: operands[1] = gen_reg_rtx (DImode); 2017: operands[2] = gen_rtx (LE, DImode, alpha_compare_op0, alpha_compare_op1); 2018: operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx); 2019: } 2020: }") 2021: 2022: (define_expand "bge" 2023: [(set (match_dup 1) (match_dup 2)) 2024: (set (pc) 2025: (if_then_else (match_dup 3) 2026: (label_ref (match_operand 0 "" "")) 2027: (pc)))] 2028: "" 2029: " 2030: { 2031: if (alpha_compare_fp_p) 2032: { 2033: operands[1] = gen_reg_rtx (DFmode); 2034: operands[2] = gen_rtx (LE, DFmode, alpha_compare_op1, alpha_compare_op0); 2035: operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (DFmode)); 2036: } 2037: else 2038: { 2039: operands[1] = gen_reg_rtx (DImode); 2040: operands[2] = gen_rtx (LT, DImode, alpha_compare_op0, alpha_compare_op1); 2041: operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx); 2042: } 2043: }") 2044: 2045: (define_expand "bltu" 2046: [(set (match_dup 1) (match_dup 2)) 2047: (set (pc) 2048: (if_then_else (match_dup 3) 2049: (label_ref (match_operand 0 "" "")) 2050: (pc)))] 2051: "" 2052: " 2053: { 2054: operands[1] = gen_reg_rtx (DImode); 2055: operands[2] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1); 2056: operands[3] = gen_rtx (NE, VOIDmode, operands[1], const0_rtx); 2057: }") 2058: 2059: (define_expand "bleu" 2060: [(set (match_dup 1) (match_dup 2)) 2061: (set (pc) 2062: (if_then_else (match_dup 3) 2063: (label_ref (match_operand 0 "" "")) 2064: (pc)))] 2065: "" 2066: " 2067: { 2068: operands[1] = gen_reg_rtx (DImode); 2069: operands[2] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1); 2070: operands[3] = gen_rtx (NE, VOIDmode, operands[1], const0_rtx); 2071: }") 2072: 2073: (define_expand "bgtu" 2074: [(set (match_dup 1) (match_dup 2)) 2075: (set (pc) 2076: (if_then_else (match_dup 3) 2077: (label_ref (match_operand 0 "" "")) 2078: (pc)))] 2079: "" 2080: " 2081: { 2082: operands[1] = gen_reg_rtx (DImode); 2083: operands[2] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1); 2084: operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx); 2085: }") 2086: 2087: (define_expand "bgeu" 2088: [(set (match_dup 1) (match_dup 2)) 2089: (set (pc) 2090: (if_then_else (match_dup 3) 2091: (label_ref (match_operand 0 "" "")) 2092: (pc)))] 2093: "" 2094: " 2095: { 2096: operands[1] = gen_reg_rtx (DImode); 2097: operands[2] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1); 2098: operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx); 2099: }") 2100: 2101: (define_expand "seq" 2102: [(set (match_operand:DI 0 "register_operand" "") 2103: (match_dup 1))] 2104: "" 2105: " 2106: { 2107: if (alpha_compare_fp_p) 2108: FAIL; 2109: 2110: operands[1] = gen_rtx (EQ, DImode, alpha_compare_op0, alpha_compare_op1); 2111: }") 2112: 2113: (define_expand "sne" 2114: [(set (match_operand:DI 0 "register_operand" "") 2115: (match_dup 1)) 2116: (set (match_dup 0) (xor:DI (match_dup 0) (const_int 1)))] 2117: "" 2118: " 2119: { 2120: if (alpha_compare_fp_p) 2121: FAIL; 2122: 2123: operands[1] = gen_rtx (EQ, DImode, alpha_compare_op0, alpha_compare_op1); 2124: }") 2125: 2126: (define_expand "slt" 2127: [(set (match_operand:DI 0 "register_operand" "") 2128: (match_dup 1))] 2129: "" 2130: " 2131: { 2132: if (alpha_compare_fp_p) 2133: FAIL; 2134: 2135: operands[1] = gen_rtx (LT, DImode, alpha_compare_op0, alpha_compare_op1); 2136: }") 2137: 2138: (define_expand "sle" 2139: [(set (match_operand:DI 0 "register_operand" "") 2140: (match_dup 1))] 2141: "" 2142: " 2143: { 2144: if (alpha_compare_fp_p) 2145: FAIL; 2146: 2147: operands[1] = gen_rtx (LE, DImode, alpha_compare_op0, alpha_compare_op1); 2148: }") 2149: 2150: (define_expand "sgt" 2151: [(set (match_operand:DI 0 "register_operand" "") 2152: (match_dup 1))] 2153: "" 2154: " 2155: { 2156: if (alpha_compare_fp_p) 2157: FAIL; 2158: 2159: operands[1] = gen_rtx (LT, DImode, force_reg (DImode, alpha_compare_op1), 2160: alpha_compare_op0); 2161: }") 2162: 2163: (define_expand "sge" 2164: [(set (match_operand:DI 0 "register_operand" "") 2165: (match_dup 1))] 2166: "" 2167: " 2168: { 2169: if (alpha_compare_fp_p) 2170: FAIL; 2171: 2172: operands[1] = gen_rtx (LE, DImode, force_reg (DImode, alpha_compare_op1), 2173: alpha_compare_op0); 2174: }") 2175: 2176: (define_expand "sltu" 2177: [(set (match_operand:DI 0 "register_operand" "") 2178: (match_dup 1))] 2179: "" 2180: " 2181: { 2182: if (alpha_compare_fp_p) 2183: FAIL; 2184: 2185: operands[1] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1); 2186: }") 2187: 2188: (define_expand "sleu" 2189: [(set (match_operand:DI 0 "register_operand" "") 2190: (match_dup 1))] 2191: "" 2192: " 2193: { 2194: if (alpha_compare_fp_p) 2195: FAIL; 2196: 2197: operands[1] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1); 2198: }") 2199: 2200: (define_expand "sgtu" 2201: [(set (match_operand:DI 0 "register_operand" "") 2202: (match_dup 1))] 2203: "" 2204: " 2205: { 2206: if (alpha_compare_fp_p) 2207: FAIL; 2208: 2209: operands[1] = gen_rtx (LTU, DImode, force_reg (DImode, alpha_compare_op1), 2210: alpha_compare_op0); 2211: }") 2212: 2213: (define_expand "sgeu" 2214: [(set (match_operand:DI 0 "register_operand" "") 2215: (match_dup 1))] 2216: "" 2217: " 2218: { 2219: if (alpha_compare_fp_p) 2220: FAIL; 2221: 2222: operands[1] = gen_rtx (LEU, DImode, force_reg (DImode, alpha_compare_op1), 2223: alpha_compare_op0); 2224: }") 2225: 1.1.1.4 ! root 2226: ;; These are the main define_expand's used to make conditional moves. ! 2227: ! 2228: (define_expand "movsicc" ! 2229: [(set (match_dup 4) (match_operand 1 "comparison_operator" "")) ! 2230: (set (match_operand:SI 0 "register_operand" "") ! 2231: (if_then_else:DI (match_dup 5) ! 2232: (match_operand:SI 2 "reg_or_8bit_operand" "") ! 2233: (match_operand:SI 3 "reg_or_8bit_operand" "")))] ! 2234: "" ! 2235: " ! 2236: { ! 2237: rtx op0,op1; ! 2238: enum rtx_code code = GET_CODE (operands[1]), code2 = NE; ! 2239: ! 2240: if (alpha_compare_fp_p) ! 2241: FAIL; ! 2242: switch (code) ! 2243: { ! 2244: case EQ: case LE: case LT: ! 2245: op0 = alpha_compare_op0; ! 2246: op1 = alpha_compare_op1; ! 2247: break; ! 2248: case NE: ! 2249: code = code2 = EQ; ! 2250: op0 = alpha_compare_op0; ! 2251: op1 = alpha_compare_op1; ! 2252: break; ! 2253: case GE: ! 2254: code = LE; ! 2255: op0 = force_reg (DImode, alpha_compare_op1); ! 2256: op1 = alpha_compare_op0; ! 2257: break; ! 2258: case GT: ! 2259: code = LT; ! 2260: op0 = force_reg (DImode, alpha_compare_op1); ! 2261: op1 = alpha_compare_op0; ! 2262: break; ! 2263: default: ! 2264: FAIL; ! 2265: } ! 2266: operands[1] = gen_rtx (code, DImode, op0, op1); ! 2267: operands[4] = gen_reg_rtx (DImode); ! 2268: operands[5] = gen_rtx (code2, VOIDmode, operands[4], CONST0_RTX (DImode)); ! 2269: }") ! 2270: ! 2271: (define_expand "movdicc" ! 2272: [(set (match_dup 4) (match_operand 1 "comparison_operator" "")) ! 2273: (set (match_operand:DI 0 "register_operand" "") ! 2274: (if_then_else:DI (match_dup 5) ! 2275: (match_operand:DI 2 "reg_or_8bit_operand" "") ! 2276: (match_operand:DI 3 "reg_or_8bit_operand" "")))] ! 2277: "" ! 2278: " ! 2279: { ! 2280: rtx op0,op1; ! 2281: enum rtx_code code = GET_CODE (operands[1]), code2 = NE; ! 2282: ! 2283: if (alpha_compare_fp_p) ! 2284: FAIL; ! 2285: switch (code) ! 2286: { ! 2287: case EQ: case LE: case LT: ! 2288: op0 = alpha_compare_op0; ! 2289: op1 = alpha_compare_op1; ! 2290: break; ! 2291: case NE: ! 2292: code = code2 = EQ; ! 2293: op0 = alpha_compare_op0; ! 2294: op1 = alpha_compare_op1; ! 2295: break; ! 2296: case GE: ! 2297: code = LE; ! 2298: op0 = force_reg (DImode, alpha_compare_op1); ! 2299: op1 = alpha_compare_op0; ! 2300: break; ! 2301: case GT: ! 2302: code = LT; ! 2303: op0 = force_reg (DImode, alpha_compare_op1); ! 2304: op1 = alpha_compare_op0; ! 2305: break; ! 2306: default: ! 2307: FAIL; ! 2308: } ! 2309: operands[1] = gen_rtx (code, DImode, op0, op1); ! 2310: operands[4] = gen_reg_rtx (DImode); ! 2311: operands[5] = gen_rtx (code2, VOIDmode, operands[4], CONST0_RTX (DImode)); ! 2312: }") ! 2313: ! 2314: (define_expand "movsfcc" ! 2315: [(set (match_dup 4) (match_operand 1 "comparison_operator" "")) ! 2316: (set (match_operand:SF 0 "register_operand" "") ! 2317: (if_then_else:SF (match_dup 5) ! 2318: (match_operand:SF 2 "reg_or_fp0_operand" "") ! 2319: (match_operand:SF 3 "reg_or_fp0_operand" "")))] ! 2320: "" ! 2321: " ! 2322: { ! 2323: rtx op0,op1; ! 2324: enum rtx_code code = GET_CODE (operands[1]), code2 = NE; ! 2325: ! 2326: if (!alpha_compare_fp_p) ! 2327: FAIL; ! 2328: switch (code) ! 2329: { ! 2330: case EQ: case LE: case LT: ! 2331: op0 = alpha_compare_op0; ! 2332: op1 = alpha_compare_op1; ! 2333: break; ! 2334: case NE: ! 2335: /* There isn't a cmptne insn. */ ! 2336: code = code2 = EQ; ! 2337: op0 = alpha_compare_op0; ! 2338: op1 = alpha_compare_op1; ! 2339: break; ! 2340: case GE: ! 2341: code = LE; ! 2342: op0 = force_reg (DFmode, alpha_compare_op1); ! 2343: op1 = alpha_compare_op0; ! 2344: break; ! 2345: case GT: ! 2346: code = LT; ! 2347: op0 = force_reg (DFmode, alpha_compare_op1); ! 2348: op1 = alpha_compare_op0; ! 2349: break; ! 2350: default: ! 2351: FAIL; ! 2352: } ! 2353: operands[1] = gen_rtx (code, DFmode, op0, op1); ! 2354: operands[4] = gen_reg_rtx (DFmode); ! 2355: operands[5] = gen_rtx (code2, VOIDmode, operands[4], CONST0_RTX (DFmode)); ! 2356: }") ! 2357: ! 2358: (define_expand "movdfcc" ! 2359: [(set (match_dup 4) (match_operand 1 "comparison_operator" "")) ! 2360: (set (match_operand:DF 0 "register_operand" "") ! 2361: (if_then_else:DF (match_dup 5) ! 2362: (match_operand:DF 2 "reg_or_fp0_operand" "") ! 2363: (match_operand:DF 3 "reg_or_fp0_operand" "")))] ! 2364: "" ! 2365: " ! 2366: { ! 2367: rtx op0,op1; ! 2368: enum rtx_code code = GET_CODE (operands[1]), code2 = NE; ! 2369: ! 2370: if (!alpha_compare_fp_p) ! 2371: FAIL; ! 2372: switch (code) ! 2373: { ! 2374: case EQ: case LE: case LT: ! 2375: op0 = alpha_compare_op0; ! 2376: op1 = alpha_compare_op1; ! 2377: break; ! 2378: case NE: ! 2379: /* There isn't a cmptne insn. */ ! 2380: code = code2 = EQ; ! 2381: op0 = alpha_compare_op0; ! 2382: op1 = alpha_compare_op1; ! 2383: break; ! 2384: case GE: ! 2385: code = LE; ! 2386: op0 = force_reg (DFmode, alpha_compare_op1); ! 2387: op1 = alpha_compare_op0; ! 2388: break; ! 2389: case GT: ! 2390: code = LT; ! 2391: op0 = force_reg (DFmode, alpha_compare_op1); ! 2392: op1 = alpha_compare_op0; ! 2393: break; ! 2394: default: ! 2395: FAIL; ! 2396: } ! 2397: operands[1] = gen_rtx (code, DFmode, op0, op1); ! 2398: operands[4] = gen_reg_rtx (DFmode); ! 2399: operands[5] = gen_rtx (code2, VOIDmode, operands[4], CONST0_RTX (DFmode)); ! 2400: }") ! 2401: 1.1 root 2402: ;; These define_split definitions are used in cases when comparisons have 2403: ;; not be stated in the correct way and we need to reverse the second 2404: ;; comparison. For example, x >= 7 has to be done as x < 6 with the 2405: ;; comparison that tests the result being reversed. We have one define_split 2406: ;; for each use of a comparison. They do not match valid insns and need 2407: ;; not generate valid insns. 2408: ;; 2409: ;; We can also handle equality comparisons (and inequality comparisons in 2410: ;; cases where the resulting add cannot overflow) by doing an add followed by 2411: ;; a comparison with zero. This is faster since the addition takes one 2412: ;; less cycle than a compare when feeding into a conditional move. 2413: ;; For this case, we also have an SImode pattern since we can merge the add 2414: ;; and sign extend and the order doesn't matter. 2415: ;; 2416: ;; We do not do this for floating-point, since it isn't clear how the "wrong" 2417: ;; operation could have been generated. 2418: 2419: (define_split 2420: [(set (match_operand:DI 0 "register_operand" "") 2421: (if_then_else:DI 2422: (match_operator 1 "comparison_operator" 2423: [(match_operand:DI 2 "reg_or_0_operand" "") 2424: (match_operand:DI 3 "reg_or_cint_operand" "")]) 2425: (match_operand:DI 4 "reg_or_cint_operand" "") 2426: (match_operand:DI 5 "reg_or_cint_operand" ""))) 2427: (clobber (match_operand:DI 6 "register_operand" ""))] 2428: "operands[3] != const0_rtx" 2429: [(set (match_dup 6) (match_dup 7)) 2430: (set (match_dup 0) 2431: (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))] 2432: " 2433: { enum rtx_code code = GET_CODE (operands[1]); 2434: int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU); 2435: 2436: /* If we are comparing for equality with a constant and that constant 2437: appears in the arm when the register equals the constant, use the 2438: register since that is more likely to match (and to produce better code 2439: if both would). */ 2440: 2441: if (code == EQ && GET_CODE (operands[3]) == CONST_INT 2442: && rtx_equal_p (operands[4], operands[3])) 2443: operands[4] = operands[2]; 2444: 2445: else if (code == NE && GET_CODE (operands[3]) == CONST_INT 2446: && rtx_equal_p (operands[5], operands[3])) 2447: operands[5] = operands[2]; 2448: 2449: if (code == NE || code == EQ 2450: || (extended_count (operands[2], DImode, unsignedp) >= 1 2451: && extended_count (operands[3], DImode, unsignedp) >= 1)) 2452: { 2453: if (GET_CODE (operands[3]) == CONST_INT) 2454: operands[7] = gen_rtx (PLUS, DImode, operands[2], 2455: GEN_INT (- INTVAL (operands[3]))); 2456: else 2457: operands[7] = gen_rtx (MINUS, DImode, operands[2], operands[3]); 2458: 2459: operands[8] = gen_rtx (code, VOIDmode, operands[6], const0_rtx); 2460: } 2461: 2462: else if (code == EQ || code == LE || code == LT 2463: || code == LEU || code == LTU) 2464: { 2465: operands[7] = gen_rtx (code, DImode, operands[2], operands[3]); 2466: operands[8] = gen_rtx (NE, VOIDmode, operands[6], const0_rtx); 2467: } 2468: else 2469: { 2470: operands[7] = gen_rtx (reverse_condition (code), DImode, operands[2], 2471: operands[3]); 2472: operands[8] = gen_rtx (EQ, VOIDmode, operands[6], const0_rtx); 2473: } 2474: }") 2475: 2476: (define_split 2477: [(set (match_operand:DI 0 "register_operand" "") 2478: (if_then_else:DI 2479: (match_operator 1 "comparison_operator" 2480: [(match_operand:SI 2 "reg_or_0_operand" "") 2481: (match_operand:SI 3 "reg_or_cint_operand" "")]) 2482: (match_operand:DI 4 "reg_or_8bit_operand" "") 2483: (match_operand:DI 5 "reg_or_8bit_operand" ""))) 2484: (clobber (match_operand:DI 6 "register_operand" ""))] 2485: "operands[3] != const0_rtx 2486: && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)" 2487: [(set (match_dup 6) (match_dup 7)) 2488: (set (match_dup 0) 2489: (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))] 2490: " 2491: { enum rtx_code code = GET_CODE (operands[1]); 2492: int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU); 2493: rtx tem; 2494: 2495: if ((code != NE && code != EQ 2496: && ! (extended_count (operands[2], DImode, unsignedp) >= 1 2497: && extended_count (operands[3], DImode, unsignedp) >= 1))) 2498: FAIL; 2499: 2500: if (GET_CODE (operands[3]) == CONST_INT) 2501: tem = gen_rtx (PLUS, SImode, operands[2], 2502: GEN_INT (- INTVAL (operands[3]))); 2503: else 2504: tem = gen_rtx (MINUS, SImode, operands[2], operands[3]); 2505: 2506: operands[7] = gen_rtx (SIGN_EXTEND, DImode, tem); 2507: operands[8] = gen_rtx (GET_CODE (operands[1]), VOIDmode, operands[6], 2508: const0_rtx); 2509: }") 2510: 2511: (define_split 2512: [(set (pc) 2513: (if_then_else 2514: (match_operator 1 "comparison_operator" 2515: [(match_operand:DI 2 "reg_or_0_operand" "") 2516: (match_operand:DI 3 "reg_or_cint_operand" "")]) 2517: (label_ref (match_operand 0 "" "")) 2518: (pc))) 2519: (clobber (match_operand:DI 4 "register_operand" ""))] 2520: "operands[3] != const0_rtx" 2521: [(set (match_dup 4) (match_dup 5)) 2522: (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))] 2523: " 2524: { enum rtx_code code = GET_CODE (operands[1]); 2525: int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU); 2526: 2527: if (code == NE || code == EQ 2528: || (extended_count (operands[2], DImode, unsignedp) >= 1 2529: && extended_count (operands[3], DImode, unsignedp) >= 1)) 2530: { 2531: if (GET_CODE (operands[3]) == CONST_INT) 2532: operands[5] = gen_rtx (PLUS, DImode, operands[2], 2533: GEN_INT (- INTVAL (operands[3]))); 2534: else 2535: operands[5] = gen_rtx (MINUS, DImode, operands[2], operands[3]); 2536: 2537: operands[6] = gen_rtx (code, VOIDmode, operands[4], const0_rtx); 2538: } 2539: 2540: else if (code == EQ || code == LE || code == LT 2541: || code == LEU || code == LTU) 2542: { 2543: operands[5] = gen_rtx (code, DImode, operands[2], operands[3]); 2544: operands[6] = gen_rtx (NE, VOIDmode, operands[4], const0_rtx); 2545: } 2546: else 2547: { 2548: operands[5] = gen_rtx (reverse_condition (code), DImode, operands[2], 2549: operands[3]); 2550: operands[6] = gen_rtx (EQ, VOIDmode, operands[4], const0_rtx); 2551: } 2552: }") 2553: 2554: (define_split 2555: [(set (pc) 2556: (if_then_else 2557: (match_operator 1 "comparison_operator" 2558: [(match_operand:SI 2 "reg_or_0_operand" "") 2559: (match_operand:SI 3 "const_int_operand" "")]) 2560: (label_ref (match_operand 0 "" "")) 2561: (pc))) 2562: (clobber (match_operand:DI 4 "register_operand" ""))] 2563: "operands[3] != const0_rtx 2564: && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)" 2565: [(set (match_dup 4) (match_dup 5)) 2566: (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))] 2567: " 2568: { rtx tem; 2569: 2570: if (GET_CODE (operands[3]) == CONST_INT) 2571: tem = gen_rtx (PLUS, SImode, operands[2], 2572: GEN_INT (- INTVAL (operands[3]))); 2573: else 2574: tem = gen_rtx (MINUS, SImode, operands[2], operands[3]); 2575: 2576: operands[5] = gen_rtx (SIGN_EXTEND, DImode, tem); 2577: operands[6] = gen_rtx (GET_CODE (operands[1]), VOIDmode, 2578: operands[4], const0_rtx); 2579: }") 1.1.1.3 root 2580: 2581: ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0". 2582: ;; This eliminates one, and sometimes two, insns when the AND can be done 2583: ;; with a ZAP. 2584: (define_split 2585: [(set (match_operand:DI 0 "register_operand" "") 2586: (match_operator 1 "comparison_operator" 2587: [(match_operand:DI 2 "register_operand" "") 2588: (match_operand:DI 3 "const_int_operand" "")])) 2589: (clobber (match_operand:DI 4 "register_operand" ""))] 2590: "exact_log2 (INTVAL (operands[3]) + 1) >= 0 2591: && (GET_CODE (operands[1]) == GTU 2592: || GET_CODE (operands[1]) == LEU 2593: || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE) 2594: && extended_count (operands[2], DImode, 1) > 0))" 2595: [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5))) 2596: (set (match_dup 0) (match_dup 6))] 2597: " 2598: { 2599: operands[5] = GEN_INT (~ INTVAL (operands[3])); 2600: operands[6] = gen_rtx (((GET_CODE (operands[1]) == GTU 2601: || GET_CODE (operands[1]) == GT) 2602: ? NE : EQ), 2603: DImode, operands[4], const0_rtx); 2604: }") 1.1 root 2605: 1.1.1.4 ! root 2606: ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF ! 2607: ;; work differently, so we have different patterns for each. 1.1 root 2608: 2609: (define_expand "call" 1.1.1.4 ! root 2610: [(use (match_operand:DI 0 "" "")) ! 2611: (use (match_operand 1 "" ""))] ! 2612: "" ! 2613: " ! 2614: { if (WINDOWS_NT) ! 2615: emit_call_insn (gen_call_nt (operands[0], operands[1])); ! 2616: else ! 2617: emit_call_insn (gen_call_osf (operands[0], operands[1])); ! 2618: ! 2619: DONE; ! 2620: }") ! 2621: ! 2622: (define_expand "call_osf" 1.1.1.3 root 2623: [(parallel [(call (mem:DI (match_operand 0 "" "")) 1.1 root 2624: (match_operand 1 "" "")) 1.1.1.3 root 2625: (clobber (reg:DI 27)) 1.1 root 2626: (clobber (reg:DI 26))])] 2627: "" 2628: " 2629: { if (GET_CODE (operands[0]) != MEM) 2630: abort (); 2631: 1.1.1.3 root 2632: operands[0] = XEXP (operands[0], 0); 1.1 root 2633: 1.1.1.3 root 2634: if (GET_CODE (operands[0]) != SYMBOL_REF 2635: && ! (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 27)) 2636: { 2637: rtx tem = gen_rtx (REG, DImode, 27); 2638: emit_move_insn (tem, operands[0]); 2639: operands[0] = tem; 2640: } 1.1 root 2641: }") 2642: 1.1.1.4 ! root 2643: (define_expand "call_nt" ! 2644: [(parallel [(call (mem:DI (match_operand:DI 0 "" "")) ! 2645: (match_operand 1 "" "")) ! 2646: (clobber (reg:DI 26))])] ! 2647: "" ! 2648: " ! 2649: { if (GET_CODE (operands[0]) != MEM) ! 2650: abort (); ! 2651: operands[0] = XEXP (operands[0], 0); ! 2652: ! 2653: if (GET_CODE (operands[1]) != SYMBOL_REF ! 2654: && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27)) ! 2655: { ! 2656: rtx tem = gen_rtx (REG, DImode, 27); ! 2657: emit_move_insn (tem, operands[1]); ! 2658: operands[1] = tem; ! 2659: } ! 2660: }") ! 2661: 1.1 root 2662: (define_expand "call_value" 1.1.1.4 ! root 2663: [(use (match_operand 0 "" "")) ! 2664: (use (match_operand:DI 1 "" "")) ! 2665: (use (match_operand 2 "" ""))] ! 2666: "" ! 2667: " ! 2668: { if (WINDOWS_NT) ! 2669: emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2])); ! 2670: else ! 2671: emit_call_insn (gen_call_value_osf (operands[0], operands[1], ! 2672: operands[2])); ! 2673: DONE; ! 2674: }") ! 2675: ! 2676: (define_expand "call_value_osf" 1.1 root 2677: [(parallel [(set (match_operand 0 "" "") 1.1.1.3 root 2678: (call (mem:DI (match_operand 1 "" "")) 1.1 root 2679: (match_operand 2 "" ""))) 1.1.1.3 root 2680: (clobber (reg:DI 27)) 1.1 root 2681: (clobber (reg:DI 26))])] 2682: "" 2683: " 2684: { if (GET_CODE (operands[1]) != MEM) 2685: abort (); 2686: 2687: operands[1] = XEXP (operands[1], 0); 2688: 1.1.1.3 root 2689: if (GET_CODE (operands[1]) != SYMBOL_REF 2690: && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27)) 2691: { 2692: rtx tem = gen_rtx (REG, DImode, 27); 2693: emit_move_insn (tem, operands[1]); 2694: operands[1] = tem; 2695: } 1.1 root 2696: }") 2697: 1.1.1.4 ! root 2698: (define_expand "call_value_nt" ! 2699: [(parallel [(set (match_operand 0 "" "") ! 2700: (call (mem:DI (match_operand:DI 1 "" "")) ! 2701: (match_operand 2 "" ""))) ! 2702: (clobber (reg:DI 26))])] ! 2703: "" ! 2704: " ! 2705: { if (GET_CODE (operands[1]) != MEM) ! 2706: abort (); ! 2707: ! 2708: operands[1] = XEXP (operands[1], 0); ! 2709: if (GET_CODE (operands[1]) != SYMBOL_REF ! 2710: && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27)) ! 2711: { ! 2712: rtx tem = gen_rtx (REG, DImode, 27); ! 2713: emit_move_insn (tem, operands[1]); ! 2714: operands[1] = tem; ! 2715: } ! 2716: }") ! 2717: 1.1 root 2718: (define_insn "" 1.1.1.3 root 2719: [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i")) 2720: (match_operand 1 "" "")) 2721: (clobber (reg:DI 27)) 1.1 root 2722: (clobber (reg:DI 26))] 1.1.1.4 ! root 2723: "! WINDOWS_NT" 1.1.1.3 root 2724: "@ 2725: jsr $26,($27),0\;ldgp $29,0($26) 2726: bsr $26,%0..ng 2727: jsr $26,%0\;ldgp $29,0($26)" 2728: [(set_attr "type" "jsr,jsr,ibr")]) 1.1 root 2729: 2730: (define_insn "" 1.1.1.4 ! root 2731: [(call (mem:DI (match_operand:DI 0 "call_operand" "r,i")) ! 2732: (match_operand 1 "" "")) ! 2733: (clobber (reg:DI 26))] ! 2734: "WINDOWS_NT" ! 2735: "@ ! 2736: jsr $26,(%0) ! 2737: bsr $26,%0" ! 2738: [(set_attr "type" "jsr")]) ! 2739: ! 2740: (define_insn "" 1.1.1.3 root 2741: [(set (match_operand 0 "register_operand" "=rf,rf,rf") 2742: (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i")) 1.1 root 2743: (match_operand 2 "" ""))) 1.1.1.3 root 2744: (clobber (reg:DI 27)) 1.1 root 2745: (clobber (reg:DI 26))] 1.1.1.4 ! root 2746: "! WINDOWS_NT" 1.1.1.3 root 2747: "@ 2748: jsr $26,($27),0\;ldgp $29,0($26) 2749: bsr $26,%1..ng 2750: jsr $26,%1\;ldgp $29,0($26)" 2751: [(set_attr "type" "jsr,jsr,ibr")]) 1.1 root 2752: 1.1.1.4 ! root 2753: (define_insn "" ! 2754: [(set (match_operand 0 "register_operand" "=rf,rf") ! 2755: (call (mem:DI (match_operand:DI 1 "call_operand" "r,i")) ! 2756: (match_operand 2 "" ""))) ! 2757: (clobber (reg:DI 26))] ! 2758: "WINDOWS_NT" ! 2759: "@ ! 2760: jsr $26,(%1) ! 2761: bsr $26,%1" ! 2762: [(set_attr "type" "jsr")]) ! 2763: 1.1 root 2764: ;; Call subroutine returning any type. 2765: 2766: (define_expand "untyped_call" 2767: [(parallel [(call (match_operand 0 "" "") 2768: (const_int 0)) 2769: (match_operand 1 "" "") 2770: (match_operand 2 "" "")])] 2771: "" 2772: " 2773: { 2774: int i; 2775: 2776: emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); 2777: 2778: for (i = 0; i < XVECLEN (operands[2], 0); i++) 2779: { 2780: rtx set = XVECEXP (operands[2], 0, i); 2781: emit_move_insn (SET_DEST (set), SET_SRC (set)); 2782: } 2783: 2784: /* The optimizer does not know that the call sets the function value 2785: registers we stored in the result block. We avoid problems by 2786: claiming that all hard registers are used and clobbered at this 2787: point. */ 2788: emit_insn (gen_blockage ()); 2789: 2790: DONE; 2791: }") 2792: 2793: ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 2794: ;; all of memory. This blocks insns from being moved across this point. 2795: 2796: (define_insn "blockage" 2797: [(unspec_volatile [(const_int 0)] 1)] 2798: "" 2799: "") 2800: 2801: (define_insn "jump" 2802: [(set (pc) 2803: (label_ref (match_operand 0 "" "")))] 2804: "" 2805: "br $31,%l0" 2806: [(set_attr "type" "ibr")]) 2807: 2808: (define_insn "return" 2809: [(return)] 2810: "direct_return ()" 2811: "ret $31,($26),1" 2812: [(set_attr "type" "ibr")]) 2813: 2814: (define_insn "indirect_jump" 2815: [(set (pc) (match_operand:DI 0 "register_operand" "r"))] 2816: "" 2817: "jmp $31,(%0),0" 2818: [(set_attr "type" "ibr")]) 2819: 2820: (define_insn "nop" 2821: [(const_int 0)] 2822: "" 2823: "bis $31,$31,$31" 2824: [(set_attr "type" "iaddlog")]) 2825: 2826: (define_expand "tablejump" 1.1.1.4 ! root 2827: [(use (match_operand:SI 0 "register_operand" "")) ! 2828: (use (match_operand:SI 1 "" ""))] ! 2829: "" ! 2830: " ! 2831: { ! 2832: if (WINDOWS_NT) ! 2833: emit_jump_insn (gen_tablejump_nt (operands[0], operands[1])); ! 2834: else ! 2835: emit_jump_insn (gen_tablejump_osf (operands[0], operands[1])); ! 2836: ! 2837: DONE; ! 2838: }") ! 2839: ! 2840: (define_expand "tablejump_osf" 1.1 root 2841: [(set (match_dup 3) 2842: (sign_extend:DI (match_operand:SI 0 "register_operand" ""))) 1.1.1.3 root 2843: (parallel [(set (pc) 2844: (plus:DI (match_dup 3) 2845: (label_ref:DI (match_operand 1 "" "")))) 1.1 root 2846: (clobber (match_scratch:DI 2 "=r"))])] 2847: "" 2848: " 2849: { operands[3] = gen_reg_rtx (DImode); }") 2850: 1.1.1.4 ! root 2851: (define_expand "tablejump_nt" ! 2852: [(set (match_dup 3) ! 2853: (sign_extend:DI (match_operand:SI 0 "register_operand" ""))) ! 2854: (parallel [(set (pc) ! 2855: (match_dup 3)) ! 2856: (use (label_ref (match_operand 1 "" "")))])] ! 2857: "" ! 2858: " ! 2859: { operands[3] = gen_reg_rtx (DImode); }") ! 2860: 1.1 root 2861: (define_insn "" 2862: [(set (pc) 2863: (plus:DI (match_operand:DI 0 "register_operand" "r") 1.1.1.3 root 2864: (label_ref:DI (match_operand 1 "" "")))) 1.1 root 2865: (clobber (match_scratch:DI 2 "=r"))] 1.1.1.4 ! root 2866: "! WINDOWS_NT && next_active_insn (insn) != 0 1.1.1.3 root 2867: && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC 2868: && PREV_INSN (next_active_insn (insn)) == operands[1]" 1.1 root 2869: "* 2870: { rtx best_label = 0; 2871: rtx jump_table_insn = next_active_insn (operands[1]); 2872: 2873: if (GET_CODE (jump_table_insn) == JUMP_INSN 1.1.1.3 root 2874: && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC) 1.1 root 2875: { 2876: rtx jump_table = PATTERN (jump_table_insn); 1.1.1.3 root 2877: int n_labels = XVECLEN (jump_table, 1); 1.1 root 2878: int best_count = -1; 2879: int i, j; 2880: 2881: for (i = 0; i < n_labels; i++) 2882: { 2883: int count = 1; 2884: 2885: for (j = i + 1; j < n_labels; j++) 1.1.1.3 root 2886: if (XEXP (XVECEXP (jump_table, 1, i), 0) 2887: == XEXP (XVECEXP (jump_table, 1, j), 0)) 1.1 root 2888: count++; 2889: 2890: if (count > best_count) 1.1.1.3 root 2891: best_count = count, best_label = XVECEXP (jump_table, 1, i); 1.1 root 2892: } 2893: } 2894: 2895: if (best_label) 2896: { 2897: operands[3] = best_label; 2898: return \"addq %0,$29,%2\;jmp $31,(%2),%3\"; 2899: } 2900: else 2901: return \"addq %0,$29,%2\;jmp $31,(%2),0\"; 2902: }" 2903: [(set_attr "type" "ibr")]) 2904: 1.1.1.4 ! root 2905: (define_insn "" ! 2906: [(set (pc) ! 2907: (match_operand:DI 0 "register_operand" "r")) ! 2908: (use (label_ref (match_operand 1 "" "")))] ! 2909: "WINDOWS_NT && next_active_insn (insn) != 0 ! 2910: && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC ! 2911: && PREV_INSN (next_active_insn (insn)) == operands[1]" ! 2912: "* ! 2913: { rtx best_label = 0; ! 2914: rtx jump_table_insn = next_active_insn (operands[1]); ! 2915: ! 2916: if (GET_CODE (jump_table_insn) == JUMP_INSN ! 2917: && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC) ! 2918: { ! 2919: rtx jump_table = PATTERN (jump_table_insn); ! 2920: int n_labels = XVECLEN (jump_table, 1); ! 2921: int best_count = -1; ! 2922: int i, j; ! 2923: ! 2924: for (i = 0; i < n_labels; i++) ! 2925: { ! 2926: int count = 1; ! 2927: ! 2928: for (j = i + 1; j < n_labels; j++) ! 2929: if (XEXP (XVECEXP (jump_table, 1, i), 0) ! 2930: == XEXP (XVECEXP (jump_table, 1, j), 0)) ! 2931: count++; ! 2932: ! 2933: if (count > best_count) ! 2934: best_count = count, best_label = XVECEXP (jump_table, 1, i); ! 2935: } ! 2936: } ! 2937: ! 2938: if (best_label) ! 2939: { ! 2940: operands[2] = best_label; ! 2941: return \"jmp $31,(%0),%2\"; ! 2942: } ! 2943: else ! 2944: return \"jmp $31,(%0),0\"; ! 2945: }" ! 2946: [(set_attr "type" "ibr")]) ! 2947: 1.1 root 2948: ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't 2949: ;; want to have to include pal.h in our .s file. 2950: (define_insn "" 2951: [(unspec_volatile [(const_int 0)] 0)] 2952: "" 2953: "call_pal 0x86") 2954: 2955: ;; Finally, we have the basic data motion insns. The byte and word insns 2956: ;; are done via define_expand. Start with the floating-point insns, since 2957: ;; they are simpler. 2958: 2959: (define_insn "" 2960: [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m") 1.1.1.2 root 2961: (match_operand:SF 1 "input_operand" "rG,m,rG,f,G,m,fG"))] 1.1 root 2962: "register_operand (operands[0], SFmode) 2963: || reg_or_fp0_operand (operands[1], SFmode)" 2964: "@ 1.1.1.2 root 2965: bis %r1,%r1,%0 1.1 root 2966: ldl %0,%1 2967: stl %r1,%0 2968: cpys %1,%1,%0 2969: cpys $f31,$f31,%0 2970: lds %0,%1 2971: sts %R1,%0" 2972: [(set_attr "type" "iaddlog,ld,st,fpop,fpop,ld,st")]) 2973: 2974: (define_insn "" 2975: [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m") 1.1.1.2 root 2976: (match_operand:DF 1 "input_operand" "rG,m,rG,f,G,m,fG"))] 1.1 root 2977: "register_operand (operands[0], DFmode) 2978: || reg_or_fp0_operand (operands[1], DFmode)" 2979: "@ 1.1.1.2 root 2980: bis %r1,%r1,%0 1.1 root 2981: ldq %0,%1 2982: stq %r1,%0 2983: cpys %1,%1,%0 2984: cpys $f31,$f31,%0 2985: ldt %0,%1 2986: stt %R1,%0" 2987: [(set_attr "type" "iaddlog,ld,st,fpop,fpop,ld,st")]) 2988: 2989: (define_expand "movsf" 2990: [(set (match_operand:SF 0 "nonimmediate_operand" "") 2991: (match_operand:SF 1 "general_operand" ""))] 2992: "" 2993: " 2994: { 2995: if (GET_CODE (operands[0]) == MEM 2996: && ! reg_or_fp0_operand (operands[1], SFmode)) 2997: operands[1] = force_reg (SFmode, operands[1]); 2998: }") 2999: 3000: (define_expand "movdf" 3001: [(set (match_operand:DF 0 "nonimmediate_operand" "") 3002: (match_operand:DF 1 "general_operand" ""))] 3003: "" 3004: " 3005: { 3006: if (GET_CODE (operands[0]) == MEM 3007: && ! reg_or_fp0_operand (operands[1], DFmode)) 3008: operands[1] = force_reg (DFmode, operands[1]); 3009: }") 3010: 1.1.1.4 ! root 3011: (define_insn "" ! 3012: [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,f,f,f,m") ! 3013: (match_operand:SI 1 "input_operand" "r,J,I,K,L,m,rJ,f,J,m,fG"))] ! 3014: "! WINDOWS_NT && (register_operand (operands[0], SImode) ! 3015: || reg_or_0_operand (operands[1], SImode))" ! 3016: "@ ! 3017: bis %1,%1,%0 ! 3018: bis $31,$31,%0 ! 3019: bis $31,%1,%0 ! 3020: lda %0,%1 ! 3021: ldah %0,%h1 ! 3022: ldl %0,%1 ! 3023: stl %r1,%0 ! 3024: cpys %1,%1,%0 ! 3025: cpys $f31,$f31,%0 ! 3026: lds %0,%1 ! 3027: sts %R1,%0" ! 3028: [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,iaddlog,ld,st,fpop,fpop,ld,st")]) 1.1 root 3029: 3030: (define_insn "" 1.1.1.4 ! root 3031: [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,f,f,f,m") ! 3032: (match_operand:SI 1 "input_operand" "r,J,I,K,L,s,m,rJ,f,J,m,fG"))] ! 3033: "WINDOWS_NT && (register_operand (operands[0], SImode) ! 3034: || reg_or_0_operand (operands[1], SImode))" 1.1 root 3035: "@ 3036: bis %1,%1,%0 3037: bis $31,$31,%0 3038: bis $31,%1,%0 3039: lda %0,%1 3040: ldah %0,%h1 1.1.1.4 ! root 3041: lda %0,%1 1.1 root 3042: ldl %0,%1 3043: stl %r1,%0 3044: cpys %1,%1,%0 3045: cpys $f31,$f31,%0 1.1.1.4 ! root 3046: lds %0,%1 ! 3047: sts %R1,%0" ! 3048: [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,iaddlog,ldsym,ld,st,fpop,fpop,ld,st")]) 1.1 root 3049: 3050: (define_insn "" 3051: [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,r,f,f") 3052: (match_operand:HI 1 "input_operand" "r,J,I,n,f,J"))] 3053: "register_operand (operands[0], HImode) 3054: || register_operand (operands[1], HImode)" 3055: "@ 3056: bis %1,%1,%0 3057: bis $31,$31,%0 3058: bis $31,%1,%0 3059: lda %0,%L1 3060: cpys %1,%1,%0 3061: cpys $f31,$f31,%0" 3062: [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,fpop,fpop")]) 3063: 3064: (define_insn "" 3065: [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,r,f,f") 3066: (match_operand:QI 1 "input_operand" "r,J,I,n,f,J"))] 3067: "register_operand (operands[0], QImode) 3068: || register_operand (operands[1], QImode)" 3069: "@ 3070: bis %1,%1,%0 3071: bis $31,$31,%0 3072: bis $31,%1,%0 3073: lda %0,%L1 3074: cpys %1,%1,%0 3075: cpys $f31,$f31,%0" 3076: [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,fpop,fpop")]) 3077: 3078: ;; We do two major things here: handle mem->mem and construct long 3079: ;; constants. 3080: 3081: (define_expand "movsi" 3082: [(set (match_operand:SI 0 "general_operand" "") 3083: (match_operand:SI 1 "general_operand" ""))] 3084: "" 3085: " 3086: { 3087: if (GET_CODE (operands[0]) == MEM 3088: && ! reg_or_0_operand (operands[1], SImode)) 3089: operands[1] = force_reg (SImode, operands[1]); 3090: 3091: if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode)) 3092: ; 3093: else if (GET_CODE (operands[1]) == CONST_INT) 3094: { 1.1.1.4 ! root 3095: operands[1] ! 3096: = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 3); ! 3097: if (rtx_equal_p (operands[0], operands[1])) 1.1 root 3098: DONE; 3099: } 3100: }") 3101: 3102: ;; Split a load of a large constant into the appropriate two-insn 3103: ;; sequence. 3104: 3105: (define_split 3106: [(set (match_operand:SI 0 "register_operand" "") 3107: (match_operand:SI 1 "const_int_operand" ""))] 3108: "! add_operand (operands[1], SImode)" 3109: [(set (match_dup 0) (match_dup 2)) 3110: (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))] 3111: " 1.1.1.4 ! root 3112: { rtx tem ! 3113: = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2); ! 3114: ! 3115: if (tem == operands[0]) 1.1 root 3116: DONE; 3117: else 3118: FAIL; 3119: }") 3120: 3121: (define_insn "" 1.1.1.2 root 3122: [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,r,r,m,f,f,f,Q") 3123: (match_operand:DI 1 "input_operand" "r,J,I,K,L,s,m,rJ,f,J,Q,fG"))] 1.1 root 3124: "register_operand (operands[0], DImode) 3125: || reg_or_0_operand (operands[1], DImode)" 3126: "@ 3127: bis %1,%1,%0 3128: bis $31,$31,%0 3129: bis $31,%1,%0 3130: lda %0,%1 3131: ldah %0,%h1 3132: lda %0,%1 3133: ldq%A1 %0,%1 3134: stq%A0 %r1,%0 3135: cpys %1,%1,%0 3136: cpys $f31,$f31,%0 3137: ldt %0,%1 3138: stt %R1,%0" 3139: [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,iaddlog,ldsym,ld,st,fpop,fpop,ld,st")]) 3140: 3141: ;; We do three major things here: handle mem->mem, put 64-bit constants in 3142: ;; memory, and construct long 32-bit constants. 3143: 3144: (define_expand "movdi" 3145: [(set (match_operand:DI 0 "general_operand" "") 3146: (match_operand:DI 1 "general_operand" ""))] 3147: "" 3148: " 3149: { 1.1.1.4 ! root 3150: rtx tem; ! 3151: 1.1 root 3152: if (GET_CODE (operands[0]) == MEM 3153: && ! reg_or_0_operand (operands[1], DImode)) 3154: operands[1] = force_reg (DImode, operands[1]); 3155: 3156: if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode)) 3157: ; 3158: else if (GET_CODE (operands[1]) == CONST_INT 1.1.1.4 ! root 3159: && (tem = alpha_emit_set_const (operands[0], DImode, ! 3160: INTVAL (operands[1]), 3)) != 0) ! 3161: { ! 3162: if (rtx_equal_p (tem, operands[0])) ! 3163: DONE; ! 3164: else ! 3165: operands[1] = tem; ! 3166: } 1.1 root 3167: else if (CONSTANT_P (operands[1])) 3168: { 3169: operands[1] = force_const_mem (DImode, operands[1]); 3170: if (reload_in_progress) 3171: { 3172: emit_move_insn (operands[0], XEXP (operands[1], 0)); 1.1.1.4 ! root 3173: operands[1] = copy_rtx (operands[1]); 1.1 root 3174: XEXP (operands[1], 0) = operands[0]; 3175: } 3176: else 3177: operands[1] = validize_mem (operands[1]); 3178: } 3179: else 3180: abort (); 3181: }") 3182: 3183: ;; Split a load of a large constant into the appropriate two-insn 3184: ;; sequence. 3185: 3186: (define_split 3187: [(set (match_operand:DI 0 "register_operand" "") 3188: (match_operand:DI 1 "const_int_operand" ""))] 3189: "! add_operand (operands[1], DImode)" 3190: [(set (match_dup 0) (match_dup 2)) 3191: (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] 3192: " 1.1.1.4 ! root 3193: { rtx tem ! 3194: = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2); ! 3195: ! 3196: if (tem == operands[0]) 1.1 root 3197: DONE; 3198: else 3199: FAIL; 3200: }") 3201: 3202: ;; These are the partial-word cases. 3203: ;; 3204: ;; First we have the code to load an aligned word. Operand 0 is the register 3205: ;; in which to place the result. It's mode is QImode or HImode. Operand 1 3206: ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the 3207: ;; number of bits within the word that the value is. Operand 3 is an SImode 3208: ;; scratch register. If operand 0 is a hard register, operand 3 may be the 3209: ;; same register. It is allowed to conflict with operand 1 as well. 3210: 3211: (define_expand "aligned_loadqi" 3212: [(set (match_operand:SI 3 "register_operand" "") 3213: (match_operand:SI 1 "memory_operand" "")) 3214: (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0) 3215: (zero_extract:DI (subreg:DI (match_dup 3) 0) 3216: (const_int 8) 3217: (match_operand:DI 2 "const_int_operand" "")))] 3218: 3219: "" 3220: "") 3221: 3222: (define_expand "aligned_loadhi" 3223: [(set (match_operand:SI 3 "register_operand" "") 3224: (match_operand:SI 1 "memory_operand" "")) 3225: (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0) 3226: (zero_extract:DI (subreg:DI (match_dup 3) 0) 3227: (const_int 16) 3228: (match_operand:DI 2 "const_int_operand" "")))] 3229: 3230: "" 3231: "") 3232: 3233: ;; Similar for unaligned loads. For QImode, we use the sequence from the 3234: ;; Alpha Architecture manual. However, for HImode, we do not. HImode pointers 3235: ;; are normally aligned to the byte boundary, so an HImode object cannot 3236: ;; cross a longword boundary. We could use a sequence similar to that for 3237: ;; QImode, but that would fail if the pointer, was, in fact, not aligned. 3238: ;; Instead, we clear bit 1 in the address and do an ldl. If the low-order 3239: ;; bit was not aligned, this will trap and the trap handler will do what is 3240: ;; needed. 3241: ;; 3242: ;; Here operand 1 is the address. Operands 2 and 3 are temporaries, where 3243: ;; operand 3 can overlap the input and output registers. 3244: 3245: (define_expand "unaligned_loadqi" 3246: [(set (match_operand:DI 2 "register_operand" "") 3247: (mem:DI (and:DI (match_operand:DI 1 "address_operand" "") 3248: (const_int -8)))) 3249: (set (match_operand:DI 3 "register_operand" "") 3250: (match_dup 1)) 3251: (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0) 3252: (zero_extract:DI (match_dup 2) 3253: (const_int 8) 3254: (ashift:DI (match_dup 3) (const_int 3))))] 3255: "" 3256: "") 3257: 3258: ;; For this, the address must already be in a register. We also need two 3259: ;; DImode temporaries, neither of which may overlap the input (and hence the 3260: ;; output, since they might be the same register), but both of which may 3261: ;; be the same. 3262: 3263: (define_expand "unaligned_loadhi" 3264: [(set (match_operand:DI 2 "register_operand" "") 3265: (and:DI (match_operand:DI 1 "register_operand" "") 3266: (const_int -7))) 3267: (set (match_operand:DI 3 "register_operand" "") 3268: (mem:DI (match_dup 2))) 1.1.1.3 root 3269: (set (match_operand:DI 4 "register_operand" "") 3270: (and:DI (match_dup 1) (const_int -2))) 1.1 root 3271: (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0) 3272: (zero_extract:DI (match_dup 3) 3273: (const_int 16) 1.1.1.3 root 3274: (ashift:DI (match_dup 4) (const_int 3))))] 1.1 root 3275: "" 3276: "") 3277: 3278: ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the 3279: ;; aligned SImode MEM. Operand 1 is the register containing the 3280: ;; byte or word to store. Operand 2 is the number of bits within the word that 3281: ;; the value should be placed. Operands 3 and 4 are SImode temporaries. 3282: 3283: (define_expand "aligned_store" 3284: [(set (match_operand:SI 3 "register_operand" "") 3285: (match_operand:SI 0 "memory_operand" "")) 3286: (set (subreg:DI (match_dup 3) 0) 3287: (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5))) 3288: (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0) 3289: (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" "")) 3290: (match_operand:DI 2 "const_int_operand" ""))) 3291: (set (subreg:DI (match_dup 4) 0) 3292: (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0))) 3293: (set (match_dup 0) (match_dup 4))] 3294: "" 3295: " 3296: { operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1])) 3297: << INTVAL (operands[2]))); 3298: }") 3299: 3300: ;; For the unaligned byte case, we use code similar to that in the 3301: ;; Architecture book, but reordered to lower the number of registers 3302: ;; required. Operand 0 is the address. Operand 1 is the data to store. 1.1.1.3 root 3303: ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may 1.1 root 3304: ;; be the same temporary, if desired. If the address is in a register, 3305: ;; operand 2 can be that register. 3306: 3307: (define_expand "unaligned_storeqi" 3308: [(set (match_operand:DI 3 "register_operand" "") 3309: (mem:DI (and:DI (match_operand:DI 0 "address_operand" "") 3310: (const_int -8)))) 3311: (set (match_operand:DI 2 "register_operand" "") 3312: (match_dup 0)) 3313: (set (match_dup 3) 1.1.1.3 root 3314: (and:DI (not:DI (ashift:DI (const_int 255) 3315: (ashift:DI (match_dup 2) (const_int 3)))) 1.1 root 3316: (match_dup 3))) 3317: (set (match_operand:DI 4 "register_operand" "") 3318: (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "")) 3319: (ashift:DI (match_dup 2) (const_int 3)))) 3320: (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3))) 3321: (set (mem:DI (and:DI (match_dup 0) (const_int -8))) 3322: (match_dup 4))] 3323: "" 3324: "") 3325: 3326: ;; This is the code for storing into an unaligned short. It uses the same 3327: ;; trick as loading from an unaligned short. It needs lots of temporaries. 3328: ;; However, during reload, we only have two registers available. So we 3329: ;; repeat code so that only two temporaries are available. During RTL 3330: ;; generation, we can use different pseudos for each temporary and CSE 3331: ;; will remove the redundancies. During reload, we have to settle with 3332: ;; what we get. Luckily, unaligned accesses of this kind produced during 3333: ;; reload are quite rare. 3334: ;; 3335: ;; Operand 0 is the address of the memory location. Operand 1 contains the 3336: ;; data to store. The rest of the operands are all temporaries, with 3337: ;; various overlap possibilities during reload. See reload_outhi for 3338: ;; details of this use. 3339: 3340: (define_expand "unaligned_storehi" 3341: [(set (match_operand:DI 2 "register_operand" "") 3342: (match_operand:DI 0 "address_operand" "")) 3343: (set (match_operand:DI 3 "register_operand" "") 3344: (and:DI (match_dup 2) (const_int -7))) 3345: (set (match_operand:DI 4 "register_operand" "") 3346: (mem:DI (match_dup 3))) 1.1.1.3 root 3347: (set (match_operand:DI 10 "register_operand" "") 3348: (and:DI (match_dup 2) (const_int -2))) 1.1 root 3349: (set (match_operand:DI 5 "register_operand" "") 1.1.1.3 root 3350: (and:DI (not:DI (ashift:DI (const_int 65535) 3351: (ashift:DI (match_dup 10) (const_int 3)))) 1.1 root 3352: (match_dup 4))) 3353: (set (match_operand:DI 6 "register_operand" "") 3354: (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "")) 1.1.1.3 root 3355: (ashift:DI (match_dup 10) (const_int 3)))) 1.1 root 3356: (set (match_operand:DI 7 "register_operand" "") 3357: (ior:DI (match_dup 5) (match_dup 6))) 3358: (set (match_operand:DI 8 "register_operand" "") (match_dup 0)) 3359: (set (match_operand:DI 9 "register_operand" "") 3360: (and:DI (match_dup 8) (const_int -7))) 3361: (set (mem:DI (match_dup 9)) (match_dup 7))] 3362: "" 3363: "") 3364: 3365: ;; Here are the define_expand's for QI and HI moves that use the above 3366: ;; patterns. We have the normal sets, plus the ones that need scratch 3367: ;; registers for reload. 3368: 3369: (define_expand "movqi" 3370: [(set (match_operand:QI 0 "general_operand" "") 3371: (match_operand:QI 1 "general_operand" ""))] 3372: "" 3373: " 3374: { extern rtx get_unaligned_address (); 3375: 3376: /* If the output is not a register, the input must be. */ 3377: if (GET_CODE (operands[0]) == MEM) 3378: operands[1] = force_reg (QImode, operands[1]); 3379: 3380: /* Handle four memory cases, unaligned and aligned for either the input 3381: or the output. The only case where we can be called during reload is 3382: for aligned loads; all other cases require temporaries. */ 3383: 3384: if (GET_CODE (operands[1]) == MEM 3385: || (GET_CODE (operands[1]) == SUBREG 3386: && GET_CODE (SUBREG_REG (operands[1])) == MEM) 3387: || (reload_in_progress && GET_CODE (operands[1]) == REG 3388: && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER) 3389: || (reload_in_progress && GET_CODE (operands[1]) == SUBREG 3390: && GET_CODE (SUBREG_REG (operands[1])) == REG 3391: && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER)) 3392: { 3393: if (aligned_memory_operand (operands[1], QImode)) 3394: { 3395: rtx aligned_mem, bitnum; 3396: rtx scratch = (reload_in_progress 3397: ? gen_rtx (REG, SImode, REGNO (operands[0])) 3398: : gen_reg_rtx (SImode)); 3399: 3400: get_aligned_mem (operands[1], &aligned_mem, &bitnum); 3401: 3402: emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum, 3403: scratch)); 3404: } 3405: else 3406: { 3407: /* Don't pass these as parameters since that makes the generated 3408: code depend on parameter evaluation order which will cause 3409: bootstrap failures. */ 3410: 3411: rtx temp1 = gen_reg_rtx (DImode); 3412: rtx temp2 = gen_reg_rtx (DImode); 3413: rtx seq = gen_unaligned_loadqi (operands[0], 3414: get_unaligned_address (operands[1]), 3415: temp1, temp2); 3416: 3417: alpha_set_memflags (seq, operands[1]); 3418: emit_insn (seq); 3419: } 3420: 3421: DONE; 3422: } 3423: 3424: else if (GET_CODE (operands[0]) == MEM 3425: || (GET_CODE (operands[0]) == SUBREG 3426: && GET_CODE (SUBREG_REG (operands[0])) == MEM) 3427: || (reload_in_progress && GET_CODE (operands[0]) == REG 3428: && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER) 3429: || (reload_in_progress && GET_CODE (operands[0]) == SUBREG 3430: && GET_CODE (SUBREG_REG (operands[0])) == REG 3431: && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)) 3432: { 3433: if (aligned_memory_operand (operands[0], QImode)) 3434: { 3435: rtx aligned_mem, bitnum; 3436: rtx temp1 = gen_reg_rtx (SImode); 3437: rtx temp2 = gen_reg_rtx (SImode); 3438: 3439: get_aligned_mem (operands[0], &aligned_mem, &bitnum); 3440: 3441: emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum, 3442: temp1, temp2)); 3443: } 3444: else 3445: { 3446: rtx temp1 = gen_reg_rtx (DImode); 3447: rtx temp2 = gen_reg_rtx (DImode); 3448: rtx temp3 = gen_reg_rtx (DImode); 3449: rtx seq = gen_unaligned_storeqi (get_unaligned_address (operands[0]), 3450: operands[1], temp1, temp2, temp3); 3451: 3452: alpha_set_memflags (seq, operands[0]); 3453: emit_insn (seq); 3454: } 3455: DONE; 3456: } 3457: }") 3458: 3459: (define_expand "movhi" 3460: [(set (match_operand:HI 0 "general_operand" "") 3461: (match_operand:HI 1 "general_operand" ""))] 3462: "" 3463: " 3464: { extern rtx get_unaligned_address (); 3465: 3466: /* If the output is not a register, the input must be. */ 3467: if (GET_CODE (operands[0]) == MEM) 3468: operands[1] = force_reg (HImode, operands[1]); 3469: 3470: /* Handle four memory cases, unaligned and aligned for either the input 3471: or the output. The only case where we can be called during reload is 3472: for aligned loads; all other cases require temporaries. */ 3473: 3474: if (GET_CODE (operands[1]) == MEM 3475: || (GET_CODE (operands[1]) == SUBREG 3476: && GET_CODE (SUBREG_REG (operands[1])) == MEM) 3477: || (reload_in_progress && GET_CODE (operands[1]) == REG 3478: && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER) 3479: || (reload_in_progress && GET_CODE (operands[1]) == SUBREG 3480: && GET_CODE (SUBREG_REG (operands[1])) == REG 3481: && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER)) 3482: { 3483: if (aligned_memory_operand (operands[1], HImode)) 3484: { 3485: rtx aligned_mem, bitnum; 3486: rtx scratch = (reload_in_progress 3487: ? gen_rtx (REG, SImode, REGNO (operands[0])) 3488: : gen_reg_rtx (SImode)); 3489: 3490: get_aligned_mem (operands[1], &aligned_mem, &bitnum); 3491: 3492: emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum, 3493: scratch)); 3494: } 3495: else 3496: { 3497: rtx addr 3498: = force_reg (DImode, 3499: force_operand (get_unaligned_address (operands[1]), 3500: NULL_RTX)); 3501: rtx scratch1 = gen_reg_rtx (DImode); 3502: rtx scratch2 = gen_reg_rtx (DImode); 1.1.1.3 root 3503: rtx scratch3 = gen_reg_rtx (DImode); 3504: 1.1 root 3505: rtx seq = gen_unaligned_loadhi (operands[0], addr, scratch1, 1.1.1.3 root 3506: scratch2, scratch3); 1.1 root 3507: 3508: alpha_set_memflags (seq, operands[1]); 3509: emit_insn (seq); 3510: } 3511: 3512: DONE; 3513: } 3514: 3515: else if (GET_CODE (operands[0]) == MEM 3516: || (GET_CODE (operands[0]) == SUBREG 3517: && GET_CODE (SUBREG_REG (operands[0])) == MEM) 3518: || (reload_in_progress && GET_CODE (operands[0]) == REG 3519: && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER) 3520: || (reload_in_progress && GET_CODE (operands[0]) == SUBREG 3521: && GET_CODE (SUBREG_REG (operands[0])) == REG 3522: && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)) 3523: { 3524: if (aligned_memory_operand (operands[0], HImode)) 3525: { 3526: rtx aligned_mem, bitnum; 3527: rtx temp1 = gen_reg_rtx (SImode); 3528: rtx temp2 = gen_reg_rtx (SImode); 3529: 3530: get_aligned_mem (operands[0], &aligned_mem, &bitnum); 3531: 3532: emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum, 3533: temp1, temp2)); 3534: } 3535: else 3536: { 3537: rtx temp1 = gen_reg_rtx (DImode); 3538: rtx temp2 = gen_reg_rtx (DImode); 3539: rtx temp3 = gen_reg_rtx (DImode); 3540: rtx temp4 = gen_reg_rtx (DImode); 3541: rtx temp5 = gen_reg_rtx (DImode); 3542: rtx temp6 = gen_reg_rtx (DImode); 3543: rtx temp7 = gen_reg_rtx (DImode); 3544: rtx temp8 = gen_reg_rtx (DImode); 1.1.1.3 root 3545: rtx temp9 = gen_reg_rtx (DImode); 3546: 1.1 root 3547: rtx seq = gen_unaligned_storehi (get_unaligned_address (operands[0]), 3548: operands[1], temp1, temp2,temp3, 1.1.1.3 root 3549: temp4, temp5, temp6,temp7, 3550: temp8, temp9); 1.1 root 3551: 3552: alpha_set_memflags (seq, operands[0]); 3553: emit_insn (seq); 3554: } 3555: 3556: DONE; 3557: } 3558: }") 3559: 3560: ;; Here are the versions for reload. Note that in the unaligned cases 3561: ;; we know that the operand must not be a pseudo-register because stack 3562: ;; slots are always aligned references. 3563: 3564: (define_expand "reload_inqi" 3565: [(parallel [(match_operand:QI 0 "register_operand" "=r") 3566: (match_operand:QI 1 "unaligned_memory_operand" "m") 1.1.1.3 root 3567: (match_operand:TI 2 "register_operand" "=&r")])] 1.1 root 3568: "" 3569: " 3570: { extern rtx get_unaligned_address (); 3571: rtx addr = get_unaligned_address (operands[1]); 1.1.1.3 root 3572: /* It is possible that one of the registers we got for operands[2] 1.1.1.4 ! root 3573: might coincide with that of operands[0] (which is why we made 1.1.1.3 root 3574: it TImode). Pick the other one to use as our scratch. */ 3575: rtx scratch = gen_rtx (REG, DImode, 3576: REGNO (operands[0]) == REGNO (operands[2]) 3577: ? REGNO (operands[2]) + 1 : REGNO (operands[2])); 3578: rtx seq = gen_unaligned_loadqi (operands[0], addr, scratch, 1.1 root 3579: gen_rtx (REG, DImode, REGNO (operands[0]))); 3580: 3581: alpha_set_memflags (seq, operands[1]); 3582: emit_insn (seq); 3583: DONE; 3584: }") 3585: 3586: (define_expand "reload_inhi" 3587: [(parallel [(match_operand:HI 0 "register_operand" "=r") 3588: (match_operand:HI 1 "unaligned_memory_operand" "m") 3589: (match_operand:TI 2 "register_operand" "=&r")])] 3590: "" 3591: " 3592: { extern rtx get_unaligned_address (); 3593: rtx addr = get_unaligned_address (operands[1]); 3594: rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2])); 3595: rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1); 3596: rtx seq; 3597: 3598: if (GET_CODE (addr) != REG) 3599: { 3600: emit_insn (gen_rtx (SET, VOIDmode, scratch2, addr)); 3601: addr = scratch2; 3602: } 3603: 1.1.1.3 root 3604: seq = gen_unaligned_loadhi (operands[0], addr, scratch1, scratch1, scratch2); 1.1 root 3605: alpha_set_memflags (seq, operands[1]); 3606: emit_insn (seq); 3607: DONE; 3608: }") 3609: 3610: (define_expand "reload_outqi" 3611: [(parallel [(match_operand:QI 0 "any_memory_operand" "=m") 3612: (match_operand:QI 1 "register_operand" "r") 3613: (match_operand:TI 2 "register_operand" "=&r")])] 3614: "" 3615: " 3616: { extern rtx get_unaligned_address (); 3617: 3618: if (aligned_memory_operand (operands[0], QImode)) 3619: { 3620: rtx aligned_mem, bitnum; 3621: 3622: get_aligned_mem (operands[0], &aligned_mem, &bitnum); 3623: 3624: emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum, 3625: gen_rtx (REG, SImode, REGNO (operands[2])), 3626: gen_rtx (REG, SImode, 3627: REGNO (operands[2]) + 1))); 3628: } 3629: else 3630: { 3631: rtx addr = get_unaligned_address (operands[0]); 3632: rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2])); 3633: rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1); 1.1.1.3 root 3634: rtx scratch3 = scratch1; 1.1 root 3635: rtx seq; 3636: 3637: if (GET_CODE (addr) == REG) 3638: scratch1 = addr; 3639: 3640: seq = gen_unaligned_storeqi (addr, operands[1], scratch1, 1.1.1.3 root 3641: scratch2, scratch3); 1.1 root 3642: alpha_set_memflags (seq, operands[0]); 3643: emit_insn (seq); 3644: } 3645: 3646: DONE; 3647: }") 3648: 3649: (define_expand "reload_outhi" 3650: [(parallel [(match_operand:HI 0 "any_memory_operand" "=m") 3651: (match_operand:HI 1 "register_operand" "r") 3652: (match_operand:TI 2 "register_operand" "=&r")])] 3653: "" 3654: " 3655: { extern rtx get_unaligned_address (); 3656: 3657: if (aligned_memory_operand (operands[0], HImode)) 3658: { 3659: rtx aligned_mem, bitnum; 3660: 3661: get_aligned_mem (operands[0], &aligned_mem, &bitnum); 3662: 3663: emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum, 3664: gen_rtx (REG, SImode, REGNO (operands[2])), 3665: gen_rtx (REG, SImode, 3666: REGNO (operands[2]) + 1))); 3667: } 3668: else 3669: { 3670: rtx addr = get_unaligned_address (operands[0]); 3671: rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2])); 3672: rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1); 3673: rtx scratch_a = GET_CODE (addr) == REG ? addr : scratch1; 3674: rtx seq; 3675: 3676: seq = gen_unaligned_storehi (addr, operands[1], scratch_a, 3677: scratch2, scratch2, scratch2, 3678: scratch1, scratch2, scratch_a, 1.1.1.3 root 3679: scratch1, scratch_a); 1.1 root 3680: alpha_set_memflags (seq, operands[0]); 3681: emit_insn (seq); 3682: } 3683: 3684: DONE; 3685: }") 3686: 3687: ;; Subroutine of stack space allocation. Perform a stack probe. 3688: (define_expand "probe_stack" 3689: [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))] 3690: "" 3691: " 3692: { 1.1.1.4 ! root 3693: operands[1] = gen_rtx (MEM, DImode, plus_constant (stack_pointer_rtx, 1.1 root 3694: INTVAL (operands[0]))); 1.1.1.4 ! root 3695: MEM_VOLATILE_P (operands[1]) = 1; 1.1 root 3696: 1.1.1.4 ! root 3697: operands[0] = const0_rtx; 1.1 root 3698: }") 3699: 3700: ;; This is how we allocate stack space. If we are allocating a 3701: ;; constant amount of space and we know it is less than 4096 3702: ;; bytes, we need do nothing. 3703: ;; 3704: ;; If it is more than 4096 bytes, we need to probe the stack 3705: ;; periodically. 3706: (define_expand "allocate_stack" 3707: [(set (reg:DI 30) 3708: (plus:DI (reg:DI 30) 3709: (match_operand:DI 0 "reg_or_cint_operand" "")))] 3710: "" 3711: " 3712: { 3713: if (GET_CODE (operands[0]) == CONST_INT 3714: && INTVAL (operands[0]) < 32768) 3715: { 3716: if (INTVAL (operands[0]) >= 4096) 3717: { 3718: /* We do this the same way as in the prologue and generate explicit 3719: probes. Then we update the stack by the constant. */ 3720: 3721: int probed = 4096; 3722: 3723: emit_insn (gen_probe_stack (GEN_INT (- probed))); 3724: while (probed + 8192 < INTVAL (operands[0])) 3725: emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192)))); 3726: 3727: if (probed + 4096 < INTVAL (operands[0])) 1.1.1.4 ! root 3728: emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[0])))); 1.1 root 3729: } 3730: 3731: operands[0] = GEN_INT (- INTVAL (operands[0])); 3732: } 3733: else 3734: { 3735: rtx out_label = 0; 3736: rtx loop_label = gen_label_rtx (); 1.1.1.4 ! root 3737: rtx want = gen_reg_rtx (Pmode); ! 3738: rtx tmp = gen_reg_rtx (Pmode); ! 3739: rtx memref; 1.1 root 3740: 1.1.1.4 ! root 3741: emit_insn (gen_subdi3 (want, stack_pointer_rtx, ! 3742: force_reg (Pmode, operands[0]))); ! 3743: emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096))); 1.1 root 3744: 3745: if (GET_CODE (operands[0]) != CONST_INT) 3746: { 3747: out_label = gen_label_rtx (); 1.1.1.4 ! root 3748: emit_insn (gen_cmpdi (want, tmp)); ! 3749: emit_jump_insn (gen_bgeu (out_label)); 1.1 root 3750: } 3751: 3752: emit_label (loop_label); 1.1.1.4 ! root 3753: memref = gen_rtx (MEM, DImode, tmp); ! 3754: MEM_VOLATILE_P (memref) = 1; ! 3755: emit_move_insn (memref, const0_rtx); ! 3756: emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192))); ! 3757: emit_insn (gen_cmpdi (tmp, want)); ! 3758: emit_jump_insn (gen_bgtu (loop_label)); ! 3759: memref = gen_rtx (MEM, DImode, want); ! 3760: MEM_VOLATILE_P (memref) = 1; ! 3761: emit_move_insn (memref, const0_rtx); 1.1 root 3762: 3763: if (out_label) 3764: emit_label (out_label); 3765: 1.1.1.4 ! root 3766: emit_move_insn (stack_pointer_rtx, want); 1.1 root 3767: 3768: DONE; 3769: } 3770: }")
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