|
|
1.1 ! root 1: /* Definitions of target machine for GNU compiler, for Acorn RISC Machine. ! 2: Copyright (C) 1991 Free Software Foundation, Inc. ! 3: Contributed by Pieter `Tiggr' Schoenmakers ([email protected]) ! 4: and Martin Simmons (@harleqn.co.uk). ! 5: ! 6: This file is part of GNU CC. ! 7: ! 8: GNU CC is free software; you can redistribute it and/or modify ! 9: it under the terms of the GNU General Public License as published by ! 10: the Free Software Foundation; either version 2, or (at your option) ! 11: any later version. ! 12: ! 13: GNU CC is distributed in the hope that it will be useful, ! 14: but WITHOUT ANY WARRANTY; without even the implied warranty of ! 15: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! 16: GNU General Public License for more details. ! 17: ! 18: You should have received a copy of the GNU General Public License ! 19: along with GNU CC; see the file COPYING. If not, write to ! 20: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ ! 21: ! 22: /* Sometimes the directive `riscos' is check. This does not imply that this ! 23: tm file can be used unchanged to build a GCC for RISC OS. ! 24: (Since in fact, it can't.) */ ! 25: ! 26: extern void output_prologue (); ! 27: extern void output_epilogue (); ! 28: extern char *arm_output_asm_insn (); ! 29: extern char *arm_output_llc (); ! 30: extern char *output_add_immediate (); ! 31: extern char *output_call (); ! 32: extern char *output_move_double (); ! 33: extern char *output_mov_double_fpu_from_arm (); ! 34: extern char *output_mov_double_arm_from_fpu (); ! 35: extern char *output_mov_immediate (); ! 36: extern char *output_multi_immediate (); ! 37: extern char *output_shifted_move (); ! 38: ! 39: /* Translation to find startup files. On RISCiX boxes, gcrt0.o is in ! 40: /usr/lib. */ ! 41: #define STARTFILE_SPEC \ ! 42: "%{pg:/usr/lib/gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}" ! 43: ! 44: #ifdef riscos ! 45: #define CPP_PREDEFINES "-Darm -Driscos" ! 46: #else ! 47: #define CPP_PREDEFINES "-Darm -Driscix -Dunix" ! 48: #endif ! 49: ! 50: /* Run-time Target Specification. */ ! 51: #define TARGET_VERSION \ ! 52: fputs (" (ARM/RISCiX)", stderr); ! 53: ! 54: /* Run-time compilation parameters selecting different hardware subsets. ! 55: On the ARM, misuse it in a different way. */ ! 56: extern int target_flags; ! 57: ! 58: /* Nonzero if the function prologue (and epilogue) should obey ! 59: the ARM Procedure Call Standard. */ ! 60: #define TARGET_APCS (target_flags & 1) ! 61: ! 62: /* Nonzero if the function prologue should output the function name to enable ! 63: the post mortem debugger to print a backtrace (very useful on RISCOS, ! 64: unused on RISCiX). Specifying this flag also enables -mapcs. ! 65: XXX Must still be implemented in the prologue. */ ! 66: #define TARGET_POKE_FUNCTION_NAME (target_flags & 2) ! 67: ! 68: /* Nonzero if floating point instructions are emulated by the FPE, in which ! 69: case instruction scheduling becomes very uninteresting. */ ! 70: #define TARGET_FPE (target_flags & 4) ! 71: ! 72: #define TARGET_SWITCHES \ ! 73: { \ ! 74: {"apcs", 1}, \ ! 75: {"poke-function-name", 2}, \ ! 76: {"fpe", 4}, \ ! 77: {"", TARGET_DEFAULT } \ ! 78: } ! 79: ! 80: #define TARGET_DEFAULT 0 ! 81: ! 82: #define TARGET_MEM_FUNCTIONS 1 ! 83: ! 84: /* OVERRIDE_OPTIONS takes care of the following: ! 85: - if -mpoke-function-name, then -mapcs. ! 86: - if doing debugging, then -mapcs; if RISCOS, then -mpoke-function-name. ! 87: - if floating point is done by emulation, forget about instruction ! 88: scheduling. Note that this only saves compilation time; it doesn't ! 89: matter for the final code. */ ! 90: #ifdef riscos ! 91: #define TARGET_WHEN_DEBUGING 3 ! 92: #else ! 93: #define TARGET_WHEN_DEBUGING 1 ! 94: #endif ! 95: ! 96: #define OVERRIDE_OPTIONS \ ! 97: { \ ! 98: if (write_symbols != NO_DEBUG) \ ! 99: target_flags |= TARGET_WHEN_DEBUGING; \ ! 100: else if (TARGET_POKE_FUNCTION_NAME) \ ! 101: target_flags |= 1; \ ! 102: if (TARGET_FPE) \ ! 103: flag_schedule_insns = flag_schedule_insns_after_reload = 0; \ ! 104: } ! 105: ! 106: /* Omitting the frame pointer is a very good idea on the ARM, especially if ! 107: not TARGET_APCS, in which case all that pushing on function entry isn't ! 108: mandatory anymore. */ ! 109: #define OPTIMIZATION_OPTIONS(OPTIMIZE) \ ! 110: { \ ! 111: if (OPTIMIZE) \ ! 112: flag_omit_frame_pointer = 1; \ ! 113: } ! 114: ! 115: /* Target machine storage Layout. */ ! 116: ! 117: /* Define this if most significant bit is lowest numbered ! 118: in instructions that operate on numbered bit-fields. */ ! 119: #define BITS_BIG_ENDIAN 0 ! 120: ! 121: /* Define this if most significant byte of a word is the lowest numbered. */ ! 122: #define BYTES_BIG_ENDIAN 0 ! 123: ! 124: /* Define this if most significant word of a multiword number is the lowest ! 125: numbered. */ ! 126: #define WORDS_BIG_ENDIAN 0 ! 127: ! 128: /* Number of bits in an addressible storage unit */ ! 129: #define BITS_PER_UNIT 8 ! 130: ! 131: #define BITS_PER_WORD 32 ! 132: ! 133: #define UNITS_PER_WORD 4 ! 134: ! 135: #define POINTER_SIZE 32 ! 136: ! 137: #define PARM_BOUNDARY 32 ! 138: ! 139: #define STACK_BOUNDARY 32 ! 140: ! 141: #define FUNCTION_BOUNDARY 32 ! 142: ! 143: #define EMPTY_FIELD_BOUNDARY 32 ! 144: ! 145: #define BIGGEST_ALIGNMENT 32 ! 146: ! 147: /* Every structures size must be a multiple of 32 bits. */ ! 148: #define STRUCTURE_SIZE_BOUNDARY 32 ! 149: ! 150: #define STRICT_ALIGNMENT 1 ! 151: ! 152: /* Define number of bits in most basic integer type. ! 153: (If undefined, default is BITS_PER_WORD). */ ! 154: /* #define INT_TYPE_SIZE */ ! 155: ! 156: /* Standard register usage. */ ! 157: ! 158: /* Register allocation in ARM Procedure Call Standard (as used on RISCiX): ! 159: (S - saved over call). ! 160: ! 161: r0 * argument word/integer result ! 162: r1-r3 argument word ! 163: ! 164: r4-r8 S register variable ! 165: r9 S (rfp) register variable (real frame pointer) ! 166: ! 167: r10 F S (sl) stack limit (not currently used) ! 168: r11 F S (fp) argument pointer ! 169: r12 (ip) temp workspace ! 170: r13 F S (sp) lower end of current stack frame ! 171: r14 (lr) link address/workspace ! 172: r15 F (pc) program counter ! 173: ! 174: f0 floating point result ! 175: f1-f3 floating point scratch ! 176: ! 177: f4-f7 S floating point variable ! 178: ! 179: *: See CONDITIONAL_REGISTER_USAGE */ ! 180: ! 181: /* The number of hard registers is 16 ARM + 8 FPU. */ ! 182: #define FIRST_PSEUDO_REGISTER 24 ! 183: ! 184: /* 1 for registers that have pervasive standard uses ! 185: and are not available for the register allocator. */ ! 186: #define FIXED_REGISTERS \ ! 187: { \ ! 188: 0,0,0,0,0,0,0,0, \ ! 189: 0,0,1,1,0,1,0,1, \ ! 190: 0,0,0,0,0,0,0,0 \ ! 191: } ! 192: ! 193: /* 1 for registers not available across function calls. ! 194: These must include the FIXED_REGISTERS and also any ! 195: registers that can be used without being saved. ! 196: The latter must include the registers where values are returned ! 197: and the register where structure-value addresses are passed. ! 198: Aside from that, you can include as many other registers as you like. */ ! 199: #define CALL_USED_REGISTERS \ ! 200: { \ ! 201: 1,1,1,1,0,0,0,0, \ ! 202: 0,0,1,1,1,1,1,1, \ ! 203: 1,1,1,1,0,0,0,0 \ ! 204: } ! 205: ! 206: /* If doing stupid life analysis, avoid a bug causing a return value r0 to be ! 207: trampled. This effectively reduces the number of available registers by 1. ! 208: XXX It is a hack, I know. ! 209: XXX Is this still needed? */ ! 210: #define CONDITIONAL_REGISTER_USAGE \ ! 211: { \ ! 212: if (obey_regdecls) \ ! 213: fixed_regs[0] = 1; \ ! 214: } ! 215: ! 216: /* Return number of consecutive hard regs needed starting at reg REGNO ! 217: to hold something of mode MODE. ! 218: This is ordinarily the length in words of a value of mode MODE ! 219: but can be less for certain modes in special long registers. ! 220: ! 221: On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP ! 222: mode. */ ! 223: #define HARD_REGNO_NREGS(REGNO, MODE) \ ! 224: ((REGNO) >= 16 ? 1 \ ! 225: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) ! 226: ! 227: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. ! 228: This is TRUE for ARM regs since they can hold anything, and TRUE for FPU ! 229: regs holding FP. */ ! 230: #define HARD_REGNO_MODE_OK(REGNO, MODE) \ ! 231: ((REGNO) < 16 || GET_MODE_CLASS (MODE) == MODE_FLOAT) ! 232: ! 233: /* Value is 1 if it is a good idea to tie two pseudo registers ! 234: when one has mode MODE1 and one has mode MODE2. ! 235: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, ! 236: for any hard reg, then this must be 0 for correct output. */ ! 237: #define MODES_TIEABLE_P(MODE1, MODE2) \ ! 238: (((MODE1) == SFmode || (MODE1) == DFmode) \ ! 239: == ((MODE2) == SFmode || (MODE2) == DFmode)) ! 240: ! 241: /* Specify the registers used for certain standard purposes. ! 242: The values of these macros are register numbers. */ ! 243: ! 244: /* Define this if the program counter is overloaded on a register. */ ! 245: #define PC_REGNUM 15 ! 246: ! 247: /* Register to use for pushing function arguments. */ ! 248: #define STACK_POINTER_REGNUM 13 ! 249: ! 250: /* Base register for access to local variables of the function. */ ! 251: #define FRAME_POINTER_REGNUM 9 ! 252: ! 253: /* Value should be nonzero if functions must have frame pointers. ! 254: Zero means the frame pointer need not be set up (and parms may be accessed ! 255: via the stack pointer) in functions that seem suitable. */ ! 256: #define FRAME_POINTER_REQUIRED 0 ! 257: ! 258: /* Base register for access to arguments of the function. */ ! 259: #define ARG_POINTER_REGNUM 11 ! 260: ! 261: /* The native (Norcroft) Pascal compiler for the ARM passes the static chain ! 262: as an invisible last argument (possible since varargs don't exist in ! 263: Pascal), so the following is not true. */ ! 264: #define STATIC_CHAIN_REGNUM 8 ! 265: ! 266: /* Register in which address to store a structure value ! 267: is passed to a function. */ ! 268: #define STRUCT_VALUE_REGNUM 0 ! 269: ! 270: /* The order in which register should be allocated. It is good to use ip ! 271: since no saving is required (though calls clobber it). It is quite good to ! 272: use lr since other calls may clobber it anyway. */ ! 273: #define REG_ALLOC_ORDER \ ! 274: { \ ! 275: 0, 1, 2, 3, 12, 14, 4, 5, \ ! 276: 6, 7, 8, 10, 9, 11, 13, 15, \ ! 277: 16, 17, 18, 19, 20, 21, 22, 23 \ ! 278: } ! 279: ! 280: /* Register and constant classes. */ ! 281: ! 282: /* Register classes: all ARM regs or all FPU regs---simple! */ ! 283: enum reg_class ! 284: { ! 285: NO_REGS, ! 286: FPU_REGS, ! 287: GENERAL_REGS, ! 288: ALL_REGS, ! 289: LIM_REG_CLASSES ! 290: }; ! 291: ! 292: #define N_REG_CLASSES (int) LIM_REG_CLASSES ! 293: ! 294: /* Give names of register classes as strings for dump file. */ ! 295: #define REG_CLASS_NAMES \ ! 296: { \ ! 297: "NO_REGS", \ ! 298: "FPU_REGS", \ ! 299: "GENERAL_REGS", \ ! 300: "ALL_REGS", \ ! 301: } ! 302: ! 303: /* Define which registers fit in which classes. ! 304: This is an initializer for a vector of HARD_REG_SET ! 305: of length N_REG_CLASSES. */ ! 306: #define REG_CLASS_CONTENTS \ ! 307: { \ ! 308: 0x000000, /* NO_REGS */ \ ! 309: 0xFF0000, /* FPU_REGS */ \ ! 310: 0x00FFFF, /* GENERAL_REGS */ \ ! 311: 0xFFFFFF /* ALL_REGS */ \ ! 312: } ! 313: ! 314: /* The same information, inverted: ! 315: Return the class number of the smallest class containing ! 316: reg number REGNO. This could be a conditional expression ! 317: or could index an array. */ ! 318: #define REGNO_REG_CLASS(REGNO) \ ! 319: ((REGNO) < 16 ? GENERAL_REGS : FPU_REGS) ! 320: ! 321: /* The class value for index registers, and the one for base regs. */ ! 322: #define INDEX_REG_CLASS GENERAL_REGS ! 323: #define BASE_REG_CLASS GENERAL_REGS ! 324: ! 325: /* Get reg_class from a letter such as appears in the machine description. ! 326: We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */ ! 327: #define REG_CLASS_FROM_LETTER(C) \ ! 328: ((C)=='f' ? FPU_REGS : NO_REGS) ! 329: ! 330: /* The letters I, J, K, L and M in a register constraint string ! 331: can be used to stand for particular ranges of immediate operands. ! 332: This macro defines what the ranges are. ! 333: C is the letter, and VALUE is a constant value. ! 334: Return 1 if VALUE is in the range specified by C. ! 335: I: immediate arithmetic operand (i.e. 8 bits shifted as requried). ! 336: J: valid indexing constants. */ ! 337: #define CONST_OK_FOR_LETTER_P(VALUE, C) \ ! 338: ((C) == 'I' ? const_ok_for_arm (VALUE) : \ ! 339: (C) == 'J' ? (abs (VALUE) < 4096) : 0) ! 340: ! 341: /* Constaint letter 'G' for the FPU immediate constants. */ ! 342: #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \ ! 343: ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) : 0) ! 344: ! 345: /* Given an rtx X being reloaded into a reg required to be ! 346: in class CLASS, return the class of reg to actually use. ! 347: In general this is just CLASS; but on some machines ! 348: in some cases it is preferable to use a more restrictive class. */ ! 349: #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS) ! 350: ! 351: /* Return the maximum number of consecutive registers ! 352: needed to represent mode MODE in a register of class CLASS. ! 353: ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */ ! 354: #define CLASS_MAX_NREGS(CLASS, MODE) \ ! 355: ((CLASS) == FPU_REGS ? 1 \ ! 356: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) ! 357: ! 358: /* Moves between FPU_REGS and GENERAL_REGS are two insns. */ ! 359: #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ ! 360: ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \ ! 361: || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \ ! 362: ? 4 : 2) ! 363: ! 364: /* Stack layout; function entry, exit and calling. */ ! 365: ! 366: /* Define this if pushing a word on the stack ! 367: makes the stack pointer a smaller address. */ ! 368: #define STACK_GROWS_DOWNWARD 1 ! 369: ! 370: /* Define this if the nominal address of the stack frame ! 371: is at the high-address end of the local variables; ! 372: that is, each additional local variable allocated ! 373: goes at a more negative offset in the frame. */ ! 374: #define FRAME_GROWS_DOWNWARD 1 ! 375: ! 376: /* Offset within stack frame to start allocating local variables at. ! 377: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the ! 378: first local allocated. Otherwise, it is the offset to the BEGINNING ! 379: of the first local allocated. */ ! 380: #define STARTING_FRAME_OFFSET 0 ! 381: ! 382: /* If we generate an insn to push BYTES bytes, ! 383: this says how many the stack pointer really advances by. */ ! 384: #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) ! 385: ! 386: /* Offset of first parameter from the argument pointer register value. */ ! 387: #define FIRST_PARM_OFFSET(FNDECL) 4 ! 388: ! 389: /* Value is the number of byte of arguments automatically ! 390: popped when returning from a subroutine call. ! 391: FUNTYPE is the data type of the function (as a tree), ! 392: or for a library call it is an identifier node for the subroutine name. ! 393: SIZE is the number of bytes of arguments passed on the stack. ! 394: ! 395: On the ARM, the caller does not pop any of its arguments that were passed ! 396: on the stack. */ ! 397: #define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0 ! 398: ! 399: /* Define how to find the value returned by a function. ! 400: VALTYPE is the data type of the value (as a tree). ! 401: If the precise function being called is known, FUNC is its FUNCTION_DECL; ! 402: otherwise, FUNC is 0. */ ! 403: #define FUNCTION_VALUE(VALTYPE, FUNC) \ ! 404: (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT \ ! 405: ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \ ! 406: : gen_rtx (REG, TYPE_MODE (VALTYPE), 0)) ! 407: ! 408: /* Define how to find the value returned by a library function ! 409: assuming the value has mode MODE. */ ! 410: #define LIBCALL_VALUE(MODE) \ ! 411: (GET_MODE_CLASS (MODE) == MODE_FLOAT \ ! 412: ? gen_rtx (REG, MODE, 16) \ ! 413: : gen_rtx (REG, MODE, 0)) ! 414: ! 415: /* 1 if N is a possible register number for a function value. ! 416: On the ARM, only r0 and f0 can return results. */ ! 417: #define FUNCTION_VALUE_REGNO_P(REGNO) \ ! 418: ((REGNO) == 0 || (REGNO) == 16) ! 419: ! 420: /* Define where to put the arguments to a function. ! 421: Value is zero to push the argument on the stack, ! 422: or a hard register in which to store the argument. ! 423: ! 424: MODE is the argument's machine mode. ! 425: TYPE is the data type of the argument (as a tree). ! 426: This is null for libcalls where that information may ! 427: not be available. ! 428: CUM is a variable of type CUMULATIVE_ARGS which gives info about ! 429: the preceding args and about the function being called. ! 430: NAMED is nonzero if this argument is a named parameter ! 431: (otherwise it is an extra parameter matching an ellipsis). ! 432: ! 433: On the ARM, normally the first 16 bytes are passed in registers r0-r3; all ! 434: other arguments are passed on the stack. If (NAMED == 0) (which happens ! 435: only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is ! 436: passed in the stack (function_prologue will indeed make it pass in the ! 437: stack if necessary). */ ! 438: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ ! 439: ((NAMED) \ ! 440: ? ((CUM) >= 16 ? 0 : gen_rtx (REG, MODE, (CUM) / 4)) \ ! 441: : 0) ! 442: ! 443: /* For an arg passed partly in registers and partly in memory, ! 444: this is the number of registers used. ! 445: For args passed entirely in registers or entirely in memory, zero. */ ! 446: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ ! 447: ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \ ! 448: ? GET_MODE_SIZE (MODE) \ ! 449: : int_size_in_bytes (TYPE)) \ ! 450: ? 4 - (CUM) / 4 : 0) ! 451: ! 452: /* A C type for declaring a variable that is used as the first argument of ! 453: `FUNCTION_ARG' and other related values. For some target machines, the ! 454: type `int' suffices and can hold the number of bytes of argument so far. ! 455: ! 456: On the ARM, this is the number of bytes of arguments scanned so far. */ ! 457: #define CUMULATIVE_ARGS int ! 458: ! 459: /* Initialize a variable CUM of type CUMULATIVE_ARGS ! 460: for a call to a function whose data type is FNTYPE. ! 461: For a library call, FNTYPE is 0. ! 462: On the ARM, the offset starts at 0. */ ! 463: #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \ ! 464: ((CUM) = (((FNTYPE) && aggregate_value_p (FNTYPE)) ? 4 : 0)) ! 465: ! 466: /* Update the data in CUM to advance over an argument ! 467: of mode MODE and data type TYPE. ! 468: (TYPE is null for libcalls where that information may not be available.) */ ! 469: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ ! 470: (CUM) += ((MODE) != BLKmode \ ! 471: ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ ! 472: : (int_size_in_bytes (TYPE) + 3) & ~3) \ ! 473: ! 474: /* 1 if N is a possible register number for function argument passing. ! 475: On the ARM, r0-r3 are used to pass args. */ ! 476: #define FUNCTION_ARG_REGNO_P(REGNO) \ ! 477: ((REGNO) >= 0 && (REGNO) <= 3) ! 478: ! 479: /* Perform any actions needed for a function that is receiving a variable ! 480: number of arguments. CUM is as above. MODE and TYPE are the mode and type ! 481: of the current parameter. PRETEND_SIZE is a variable that should be set to ! 482: the amount of stack that must be pushed by the prolog to pretend that our ! 483: caller pushed it. ! 484: ! 485: Normally, this macro will push all remaining incoming registers on the ! 486: stack and set PRETEND_SIZE to the length of the registers pushed. ! 487: ! 488: On the ARM, PRETEND_SIZE is set in order to have the prologue push the last ! 489: named arg and all anonymous args onto the stack. ! 490: XXX I know the prologue shouldn't be pushing registers, but it is faster ! 491: that way. */ ! 492: #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ ! 493: { \ ! 494: extern int current_function_anonymous_args; \ ! 495: current_function_anonymous_args = 1; \ ! 496: if ((CUM) < 16) \ ! 497: (PRETEND_SIZE) = 16 - (CUM); \ ! 498: } ! 499: ! 500: /* Generate assembly output for the start of a function. */ ! 501: #define FUNCTION_PROLOGUE(STREAM, SIZE) \ ! 502: output_prologue ((STREAM), (SIZE)) ! 503: ! 504: /* Call the function profiler with a given profile label. The Acorn compiler ! 505: puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr'' ! 506: seems like a good idea to stick with cc convention. ``prof'' doesn't seem ! 507: to mind about this! */ ! 508: #define FUNCTION_PROFILER(STREAM,LABELNO) \ ! 509: { \ ! 510: fprintf(STREAM, "\tmov\tip, lr\n"); \ ! 511: fprintf(STREAM, "\tbl\tmcount\n"); \ ! 512: fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \ ! 513: arm_increase_location (12); \ ! 514: } ! 515: ! 516: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, ! 517: the stack pointer does not matter. The value is tested only in ! 518: functions that have frame pointers. ! 519: No definition is equivalent to always zero. ! 520: ! 521: On the ARM, the function epilogue recovers the stack pointer from the ! 522: frame. */ ! 523: #define EXIT_IGNORE_STACK 1 ! 524: ! 525: /* Generate the assembly code for function exit. */ ! 526: #define FUNCTION_EPILOGUE(STREAM, SIZE) \ ! 527: output_epilogue ((STREAM), (SIZE)) ! 528: ! 529: /* Determine if the epilogue should be output as RTL. ! 530: You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ ! 531: /* #define USE_RETURN_INSN use_return_insn () */ ! 532: ! 533: /* Store in the variable DEPTH the initial difference between the frame ! 534: pointer reg contents and the stack pointer reg contents, as of the start of ! 535: the function body. This depends on the layout of the fixed parts of the ! 536: stack frame and on how registers are saved. */ ! 537: #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \ ! 538: (DEPTH) = (get_frame_size () + 3) & ~3; ! 539: ! 540: /* Output assembler code for a block containing the constant parts ! 541: of a trampoline, leaving space for the variable parts. ! 542: ! 543: On the ARM, (if r8 is the static chain regnum, and remembering that ! 544: referencing pc adds an offset of 8) the trampoline looks like: ! 545: ldr r8, [pc, #0] ! 546: ldr pc, [pc] ! 547: .word static chain value ! 548: .word function's address */ ! 549: #define TRAMPOLINE_TEMPLATE(FILE) \ ! 550: { \ ! 551: fprintf ((FILE), "\tldr\tr8, [pc, #0]\n"); \ ! 552: fprintf ((FILE), "\tldr\tpc, [pc, #0]\n"); \ ! 553: fprintf ((FILE), "\t.word\t0\n"); \ ! 554: fprintf ((FILE), "\t.word\t0\n"); \ ! 555: } ! 556: ! 557: /* Length in units of the trampoline for entering a nested function. */ ! 558: #define TRAMPOLINE_SIZE 16 ! 559: ! 560: /* Alignment required for a trampoline in units. */ ! 561: #define TRAMPOLINE_ALIGN 4 ! 562: ! 563: /* Emit RTL insns to initialize the variable parts of a trampoline. ! 564: FNADDR is an RTX for the address of the function's pure code. ! 565: CXT is an RTX for the static chain value for the function. */ ! 566: #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ ! 567: { \ ! 568: emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \ ! 569: (CXT)); \ ! 570: emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \ ! 571: (FNADDR)); \ ! 572: } ! 573: ! 574: /* Call the function profiler with a given profile label. The Acorn compiler ! 575: puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr'' ! 576: seems like a good idea to stick with cc convention. ``prof'' doesn't seem ! 577: to mind about this! */ ! 578: #define FUNCTION_PROFILER(STREAM,LABELNO) \ ! 579: { \ ! 580: fprintf(STREAM, "\tmov\tip, lr\n"); \ ! 581: fprintf(STREAM, "\tbl\tmcount\n"); \ ! 582: fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \ ! 583: arm_increase_location (12); \ ! 584: } ! 585: ! 586: /* Addressing modes, and classification of registers for them. */ ! 587: ! 588: #define HAVE_POST_INCREMENT 1 ! 589: #define HAVE_PRE_INCREMENT 1 ! 590: #define HAVE_POST_DECREMENT 1 ! 591: #define HAVE_PRE_DECREMENT 1 ! 592: ! 593: /* Macros to check register numbers against specific register classes. */ ! 594: ! 595: /* These assume that REGNO is a hard or pseudo reg number. ! 596: They give nonzero only if REGNO is a hard reg of the suitable class ! 597: or a pseudo reg currently allocated to a suitable hard reg. ! 598: Since they use reg_renumber, they are safe only once reg_renumber ! 599: has been allocated, which happens in local-alloc.c. ! 600: ! 601: On the ARM, don't allow the pc to be used. */ ! 602: #define REGNO_OK_FOR_BASE_P(REGNO) \ ! 603: ((REGNO) < 15 || (unsigned) reg_renumber[(REGNO)] < 15) ! 604: #define REGNO_OK_FOR_INDEX_P(REGNO) \ ! 605: REGNO_OK_FOR_BASE_P(REGNO) ! 606: ! 607: /* Maximum number of registers that can appear in a valid memory address. ! 608: The addressing mode [ra,rb, <shift> rc] uses the greatest number of ! 609: registers. */ ! 610: #define MAX_REGS_PER_ADDRESS 3 ! 611: ! 612: /* Recognize any constant value that is a valid address. */ ! 613: /* XXX We can address any constant, eventually... */ ! 614: #if 0 ! 615: #define CONSTANT_ADDRESS_P(X) \ ! 616: ( GET_CODE(X) == LABEL_REF \ ! 617: || GET_CODE(X) == SYMBOL_REF \ ! 618: || GET_CODE(X) == CONST_INT \ ! 619: || GET_CODE(X) == CONST ) ! 620: #endif ! 621: ! 622: #define CONSTANT_ADDRESS_P(X) \ ! 623: (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) ! 624: ! 625: /* Nonzero if the constant value X is a legitimate general operand. ! 626: It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. ! 627: ! 628: On the ARM, allow any integer (invalid ones are removed later by insn ! 629: patterns), nice doubles and symbol_refs which refer to the function's ! 630: constant pool XXX. */ ! 631: #define LEGITIMATE_CONSTANT_P(X) \ ! 632: (GET_CODE (X) == CONST_INT \ ! 633: || (GET_CODE (X) == CONST_DOUBLE \ ! 634: && const_double_rtx_ok_for_fpu (X))) ! 635: #if 0 ! 636: || GET_CODE(X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P(X)) ! 637: #endif ! 638: ! 639: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx ! 640: and check its validity for a certain class. ! 641: We have two alternate definitions for each of them. ! 642: The usual definition accepts all pseudo regs; the other rejects ! 643: them unless they have been allocated suitable hard regs. ! 644: The symbol REG_OK_STRICT causes the latter definition to be used. */ ! 645: #ifndef REG_OK_STRICT ! 646: /* Nonzero if X is a hard reg that can be used as a base reg ! 647: or if it is a pseudo reg. */ ! 648: #define REG_OK_FOR_BASE_P(X) \ ! 649: (REGNO (X) < 16 || REGNO (X) >= 24) ! 650: /* Nonzero if X is a hard reg that can be used as an index ! 651: or if it is a pseudo reg. */ ! 652: #define REG_OK_FOR_INDEX_P(X) \ ! 653: REG_OK_FOR_BASE_P(X) ! 654: #define REG_OK_FOR_PRE_POST_P(X) \ ! 655: (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER) ! 656: #else ! 657: /* Nonzero if X is a hard reg that can be used as a base reg. */ ! 658: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) ! 659: /* Nonzero if X is a hard reg that can be used as an index. */ ! 660: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) ! 661: #define REG_OK_FOR_PRE_POST_P(X) \ ! 662: (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16) ! 663: #endif ! 664: ! 665: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression ! 666: that is a valid memory address for an instruction. ! 667: The MODE argument is the machine mode for the MEM expression ! 668: that wants to use this address. ! 669: ! 670: The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ ! 671: #define BASE_REGISTER_RTX_P(X) \ ! 672: (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) ! 673: ! 674: #define INDEX_REGISTER_RTX_P(X) \ ! 675: (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) ! 676: ! 677: /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs ! 678: used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can ! 679: only be small constants. */ ! 680: #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \ ! 681: do \ ! 682: { \ ! 683: int range; \ ! 684: \ ! 685: if (GET_MODE_CLASS (MODE) == MODE_FLOAT) \ ! 686: range = 1024; \ ! 687: else \ ! 688: { \ ! 689: if (INDEX_REGISTER_RTX_P (INDEX)) \ ! 690: goto LABEL; \ ! 691: if (GET_MODE_SIZE (MODE) <= 4 && GET_CODE (INDEX) == MULT) \ ! 692: { \ ! 693: rtx xiop0 = XEXP (INDEX, 0); \ ! 694: rtx xiop1 = XEXP (INDEX, 1); \ ! 695: if (INDEX_REGISTER_RTX_P (xiop0) && power_of_two_operand (xiop1, SImode)) \ ! 696: goto LABEL; \ ! 697: if (INDEX_REGISTER_RTX_P (xiop1) && power_of_two_operand (xiop0, SImode)) \ ! 698: goto LABEL; \ ! 699: } \ ! 700: range = 4096; \ ! 701: } \ ! 702: \ ! 703: if (GET_CODE (INDEX) == CONST_INT && abs (INTVAL (INDEX)) < range) \ ! 704: goto LABEL; \ ! 705: } while (0) ! 706: ! 707: /* Jump to LABEL if X is a valid address RTX. This must also take ! 708: REG_OK_STRICT into account when deciding about valid registers, but it uses ! 709: the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX, ! 710: INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool. ! 711: Allow REG-only and AUTINC-REG if handling TImode. Other symbol refs must ! 712: be forced though a static cell to ensure addressability. */ ! 713: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ ! 714: { \ ! 715: if (BASE_REGISTER_RTX_P (X)) \ ! 716: goto LABEL; \ ! 717: else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \ ! 718: && GET_CODE (XEXP (X, 0)) == REG \ ! 719: && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \ ! 720: goto LABEL; \ ! 721: else if ((MODE) == TImode) \ ! 722: ; \ ! 723: else if (GET_CODE (X) == PLUS) \ ! 724: { \ ! 725: rtx xop0 = XEXP(X,0); \ ! 726: rtx xop1 = XEXP(X,1); \ ! 727: \ ! 728: if (BASE_REGISTER_RTX_P (xop0)) \ ! 729: GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \ ! 730: else if (BASE_REGISTER_RTX_P (xop1)) \ ! 731: GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \ ! 732: } \ ! 733: else if (GET_CODE (X) == MINUS) \ ! 734: { \ ! 735: rtx xop0 = XEXP (X,0); \ ! 736: rtx xop1 = XEXP (X,1); \ ! 737: \ ! 738: if (BASE_REGISTER_RTX_P (xop0)) \ ! 739: GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \ ! 740: } \ ! 741: else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \ ! 742: && GET_CODE (X) == SYMBOL_REF \ ! 743: && CONSTANT_POOL_ADDRESS_P (X)) \ ! 744: goto LABEL; \ ! 745: else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \ ! 746: && GET_CODE (XEXP (X, 0)) == REG \ ! 747: && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \ ! 748: goto LABEL; \ ! 749: } ! 750: ! 751: /* Try machine-dependent ways of modifying an illegitimate address ! 752: to be legitimate. If we find one, return the new, valid address. ! 753: This macro is used in only one place: `memory_address' in explow.c. ! 754: ! 755: OLDX is the address as it was before break_out_memory_refs was called. ! 756: In some cases it is useful to look at this to decide what needs to be done. ! 757: ! 758: MODE and WIN are passed so that this macro can use ! 759: GO_IF_LEGITIMATE_ADDRESS. ! 760: ! 761: It is always safe for this macro to do nothing. It exists to recognize ! 762: opportunities to optimize the output. ! 763: ! 764: On the ARM, try to convert [REG, #BIGCONST] ! 765: into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST], ! 766: where VALIDCONST == 0 in case of TImode. */ ! 767: #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ ! 768: { \ ! 769: if (GET_CODE (X) == PLUS) \ ! 770: { \ ! 771: rtx xop0 = XEXP (X, 0); \ ! 772: rtx xop1 = XEXP (X, 1); \ ! 773: \ ! 774: if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \ ! 775: { \ ! 776: int n = INTVAL (xop1); \ ! 777: int low_n = ((MODE) == TImode ? 0 \ ! 778: : n >= 0 ? (n & 0xFFF) : -((-n) & 0xFFF)); \ ! 779: rtx base_reg = gen_reg_rtx (SImode); \ ! 780: rtx val = force_operand (gen_rtx (PLUS, SImode, xop0, \ ! 781: gen_rtx (CONST_INT, \ ! 782: VOIDmode, n - low_n)), \ ! 783: 0); \ ! 784: emit_move_insn (base_reg, val); \ ! 785: (X) = (low_n == 0 ? base_reg \ ! 786: : gen_rtx (PLUS, SImode, base_reg, \ ! 787: gen_rtx (CONST_INT, VOIDmode, low_n))); \ ! 788: } \ ! 789: else if (BASE_REGISTER_RTX_P (xop1) && GET_CODE (xop0) == CONST_INT) \ ! 790: { \ ! 791: int n = INTVAL (xop0); \ ! 792: int low_n = ((MODE) == TImode ? 0 \ ! 793: : n >= 0 ? (n & 0xFFF) : -((-n) & 0xFFF)); \ ! 794: rtx base_reg = gen_reg_rtx (SImode); \ ! 795: rtx val = force_operand (gen_rtx (PLUS, SImode, xop1, \ ! 796: gen_rtx (CONST_INT, \ ! 797: VOIDmode, n - low_n)), \ ! 798: 0); \ ! 799: emit_move_insn (base_reg, val); \ ! 800: (X) = (low_n == 0 ? base_reg \ ! 801: : gen_rtx (PLUS, SImode, base_reg, \ ! 802: gen_rtx (CONST_INT, VOIDmode, low_n))); \ ! 803: } \ ! 804: } \ ! 805: if (memory_address_p (MODE, X)) \ ! 806: goto win; \ ! 807: } ! 808: ! 809: /* Go to LABEL if ADDR (a legitimate address expression) ! 810: has an effect that depends on the machine mode it is used for. */ ! 811: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ ! 812: { \ ! 813: if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \ ! 814: || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \ ! 815: goto LABEL; \ ! 816: } ! 817: ! 818: /* Specify the machine mode that this machine uses ! 819: for the index in the tablejump instruction. */ ! 820: #define CASE_VECTOR_MODE SImode ! 821: ! 822: /* Define this if the tablejump instruction expects the table ! 823: to contain offsets from the address of the table. ! 824: Do not define this if the table should contain absolute addresses. */ ! 825: /* #define CASE_VECTOR_PC_RELATIVE */ ! 826: ! 827: /* Specify the tree operation to be used to convert reals to integers. */ ! 828: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR ! 829: ! 830: /* This is the kind of divide that is easiest to do in the general case. */ ! 831: #define EASY_DIV_EXPR TRUNC_DIV_EXPR ! 832: ! 833: /* 'char' is signed by default on RISCiX, unsigned on RISCOS. */ ! 834: #ifdef riscos ! 835: #define DEFAULT_SIGNED_CHAR 0 ! 836: #else ! 837: #define DEFAULT_SIGNED_CHAR 1 ! 838: #endif ! 839: ! 840: /* Don't cse the address of the function being compiled. */ ! 841: #define NO_RECURSIVE_FUNCTION_CSE 1 ! 842: ! 843: /* Max number of bytes we can move from memory to memory ! 844: in one reasonably fast instruction. ! 845: On the ARM, there are no instructions which move memory to memory! */ ! 846: #define MOVE_MAX 0 ! 847: ! 848: /* Define if normal loads of shorter-than-word items from memory clears ! 849: the rest of the bigs in the register. ! 850: On the ARM, movhi does a garbage extend. */ ! 851: /* #define BYTE_LOADS_ZERO_EXTEND */ ! 852: ! 853: /* Define this if zero-extension is slow (more than one real instruction). ! 854: On the ARM, it is more than one instruction only if not fetching from ! 855: memory. */ ! 856: /* #define SLOW_ZERO_EXTEND */ ! 857: ! 858: /* Nonzero if access to memory by bytes is slow and undesirable. */ ! 859: #define SLOW_BYTE_ACCESS 0 ! 860: ! 861: /* Immediate shift counts are truncated by the output routines (or was it ! 862: the assembler?). Shift counts in a register are truncated by ARM. Note ! 863: that the native compiler puts too large (> 32) immediate shift counts ! 864: into a register and shifts by the register, letting the ARM decide what ! 865: to do instead of doing that itself. */ ! 866: #define SHIFT_COUNT_TRUNCATED 1 ! 867: ! 868: /* We have the vprintf function. */ ! 869: #define HAVE_VPRINTF 1 ! 870: ! 871: /* XX This is not true, is it? */ ! 872: /* All integers have the same format so truncation is easy. */ ! 873: #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1 ! 874: ! 875: /* Calling from registers is a massive pain. */ ! 876: #define NO_FUNCTION_CSE 1 ! 877: ! 878: /* Chars and shorts should be passed as ints. */ ! 879: #define PROMOTE_PROTOTYPES 1 ! 880: ! 881: /* There is no support for s<cond> insns at present */ ! 882: #define STORE_FLAG_VALUE 0 ! 883: ! 884: /* The machine modes of pointers and functions */ ! 885: #define Pmode SImode ! 886: #define FUNCTION_MODE Pmode ! 887: ! 888: /* The structure type of the machine dependent info field of insns ! 889: No uses for this yet. */ ! 890: /* #define INSN_MACHINE_INFO struct machine_info */ ! 891: ! 892: /* The relative costs of various types of constants. Note that cse.c defines ! 893: REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */ ! 894: #define CONST_COSTS(RTX, CODE) \ ! 895: case CONST_INT: \ ! 896: if (const_ok_for_arm (INTVAL (RTX))) \ ! 897: return (2); \ ! 898: else \ ! 899: return (5); \ ! 900: \ ! 901: case CONST: \ ! 902: case LABEL_REF: \ ! 903: case SYMBOL_REF: \ ! 904: return (6); \ ! 905: \ ! 906: case CONST_DOUBLE: \ ! 907: if (const_double_rtx_ok_for_fpu (RTX)) \ ! 908: return(2); \ ! 909: else \ ! 910: return(7); ! 911: ! 912: /* Condition code information. */ ! 913: ! 914: /* Store in cc_status the expressions ! 915: that the condition codes will describe ! 916: after execution of an instruction whose pattern is EXP. ! 917: Do not alter them if the instruction would not alter the cc's. */ ! 918: ! 919: /* On the ARM nothing sets the condition code implicitly---apart from DImode ! 920: operations excluding moves---but we have to watch for registers in the ! 921: condition code value being clobbered. This clobbering includes (alas) ! 922: function calls. XXX They could just be considered to clobber regs 0-3 and ! 923: 10-15 with extra work. */ ! 924: #define NOTICE_UPDATE_CC(EXP, INSN) \ ! 925: { \ ! 926: if (GET_MODE (EXP) == DImode \ ! 927: && GET_CODE (EXP) == SET \ ! 928: && GET_CODE (SET_SRC (EXP)) != REG \ ! 929: && GET_CODE (SET_SRC (EXP)) != MEM \ ! 930: && GET_CODE (SET_SRC (EXP)) != CONST_INT) \ ! 931: CC_STATUS_INIT; \ ! 932: else if (GET_CODE (EXP) == SET) \ ! 933: { \ ! 934: rtx dest = SET_DEST (EXP); \ ! 935: if (dest == cc0_rtx) \ ! 936: { \ ! 937: cc_status.flags = 0; \ ! 938: cc_status.value1 = SET_DEST (EXP); \ ! 939: cc_status.value2 = SET_SRC (EXP); \ ! 940: } \ ! 941: if (BASE_REGISTER_RTX_P (dest)) \ ! 942: { \ ! 943: if (cc_status.value1 \ ! 944: && reg_overlap_mentioned_p (dest, cc_status.value1)) \ ! 945: cc_status.value1 = 0; \ ! 946: if (cc_status.value2 \ ! 947: && reg_overlap_mentioned_p (dest, cc_status.value2)) \ ! 948: cc_status.value2 = 0; \ ! 949: } \ ! 950: } \ ! 951: else if (GET_CODE (INSN) != JUMP_INSN && GET_CODE (EXP) == PARALLEL) \ ! 952: { \ ! 953: CC_STATUS_INIT; \ ! 954: } \ ! 955: } ! 956: ! 957: /* Assembler output control */ ! 958: ! 959: /* The text to go at the start of the assembler file */ ! 960: #define ASM_FILE_START(STREAM) \ ! 961: { \ ! 962: extern char *version_string; \ ! 963: \ ! 964: fprintf (STREAM,"@ Generated by gcc %s for ARM/RISCiX\n", version_string); \ ! 965: fprintf (STREAM,"rfp\t.req\tr9\n"); \ ! 966: fprintf (STREAM,"fp\t.req\tr11\n"); \ ! 967: fprintf (STREAM,"ip\t.req\tr12\n"); \ ! 968: fprintf (STREAM,"sp\t.req\tr13\n"); \ ! 969: fprintf (STREAM,"lr\t.req\tr14\n"); \ ! 970: fprintf (STREAM,"pc\t.req\tr15\n"); \ ! 971: } ! 972: ! 973: #define ASM_APP_ON "" ! 974: #define ASM_APP_OFF "" ! 975: ! 976: /* Switch to the text or data segment. */ ! 977: #define TEXT_SECTION_ASM_OP "\n\t.text\n" ! 978: #define DATA_SECTION_ASM_OP "\n\t.data\n" ! 979: ! 980: /* The assembler's names for the registers. RFP need not always be used as ! 981: the Real framepointer; it can also be used as a normal general register. ! 982: Note that the name `fp' is horribly misleading since `fp' is in fact only ! 983: the argument-and-return-context pointer. */ ! 984: #define REGISTER_NAMES \ ! 985: { \ ! 986: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ ! 987: "r8","rfp", "sl", "fp", "ip", "sp", "lr", "pc", \ ! 988: "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7" \ ! 989: } ! 990: ! 991: /* DBX register number for a given compiler register number */ ! 992: #define DBX_REGISTER_NUMBER(REGNO) (REGNO) ! 993: ! 994: /* Generate DBX debugging information. */ ! 995: #define DBX_DEBUGGING_INFO 1 ! 996: ! 997: /* Acorn dbx moans about continuation chars, so don't use any. */ ! 998: #define DBX_CONTIN_LENGTH 0 ! 999: ! 1000: /* Output a label definition. */ ! 1001: #define ASM_OUTPUT_LABEL(STREAM,NAME) \ ! 1002: arm_asm_output_label ((STREAM), (NAME)) ! 1003: ! 1004: /* Output a function label definition. */ ! 1005: #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \ ! 1006: ASM_OUTPUT_LABEL(STREAM, NAME) ! 1007: ! 1008: /* Output a globalising directive for a label. */ ! 1009: #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \ ! 1010: (fprintf (STREAM, "\t.global\t"), \ ! 1011: assemble_name (STREAM, NAME), \ ! 1012: fputc ('\n',STREAM)) \ ! 1013: ! 1014: /* Output a reference to a label. */ ! 1015: #define ASM_OUTPUT_LABELREF(STREAM,NAME) \ ! 1016: fprintf (STREAM, "_%s", NAME) ! 1017: ! 1018: /* Make an internal label into a string. */ ! 1019: #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \ ! 1020: sprintf (STRING, "*%s%d", PREFIX, NUM) ! 1021: ! 1022: /* Output an internal label definition. */ ! 1023: #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \ ! 1024: do \ ! 1025: { \ ! 1026: char *s = (char *) alloca (11 + strlen (PREFIX)); \ ! 1027: extern int arm_target_label, arm_ccfsm_state; \ ! 1028: \ ! 1029: if (arm_ccfsm_state == 3 && arm_target_label == (NUM)) \ ! 1030: arm_ccfsm_state = 0; \ ! 1031: strcpy (s, "*"); \ ! 1032: sprintf (&s[strlen (s)], "%s%d", (PREFIX), (NUM)); \ ! 1033: arm_asm_output_label (STREAM, s); \ ! 1034: } while (0) ! 1035: ! 1036: /* Nothing special is done about jump tables */ ! 1037: /* #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) */ ! 1038: /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */ ! 1039: ! 1040: /* Construct a private name. */ ! 1041: #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \ ! 1042: ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \ ! 1043: sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER))) ! 1044: ! 1045: /* Output a push or a pop instruction (only used when profiling). */ ! 1046: #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ ! 1047: (arm_increase_location (4) \ ! 1048: , fprintf(STREAM,"\tstmfd\tsp!,{%s}\n", reg_names[REGNO])) ! 1049: ! 1050: #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ ! 1051: (arm_increase_location (4) \ ! 1052: , fprintf(STREAM,"\tldmfd\tsp!,{%s}\n", reg_names[REGNO])) ! 1053: ! 1054: /* Output a relative address. Not needed since jump tables are absolute ! 1055: but we must define it anyway. */ ! 1056: #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \ ! 1057: fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM) ! 1058: ! 1059: /* Output an element of a dispatch table. */ ! 1060: #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ ! 1061: (arm_increase_location (4) \ ! 1062: , fprintf (STREAM, "\t.word\tL%d\n", VALUE)) ! 1063: ! 1064: /* Output various types of constants. */ ! 1065: #define ASM_OUTPUT_DOUBLE(STREAM, VALUE) \ ! 1066: (arm_increase_location (sizeof (double)) \ ! 1067: , fprintf (STREAM, "\t.double\t%20.20f\n", VALUE)) ! 1068: ! 1069: #define ASM_OUTPUT_FLOAT(STREAM, VALUE) \ ! 1070: (arm_increase_location (sizeof (float)) \ ! 1071: , fprintf (STREAM, "\t.float\t%20.20f\n", VALUE)) ! 1072: ! 1073: #define ASM_OUTPUT_INT(STREAM, EXP) \ ! 1074: (fprintf (STREAM, "\t.word\t"), \ ! 1075: output_addr_const (STREAM, (EXP)), \ ! 1076: arm_increase_location (4), \ ! 1077: fputc ('\n', STREAM)) ! 1078: ! 1079: #define ASM_OUTPUT_SHORT(STREAM, EXP) \ ! 1080: (fprintf (STREAM, "\t.short\t"), \ ! 1081: output_addr_const (STREAM, (EXP)), \ ! 1082: arm_increase_location (2), \ ! 1083: fputc ('\n', STREAM)) ! 1084: ! 1085: #define ASM_OUTPUT_CHAR(STREAM, EXP) \ ! 1086: (fprintf (STREAM, "\t.byte\t"), \ ! 1087: output_addr_const (STREAM, (EXP)), \ ! 1088: arm_increase_location (1), \ ! 1089: fputc ('\n', STREAM)) ! 1090: ! 1091: #define ASM_OUTPUT_BYTE(STREAM, VALUE) \ ! 1092: (fprintf (STREAM, "\t.byte\t%d\n", VALUE), \ ! 1093: arm_increase_location (1)) ! 1094: ! 1095: #define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) \ ! 1096: output_ascii_pseudo_op ((STREAM), (PTR), (LEN)) ! 1097: ! 1098: /* Output a gap. In fact we fill it with nulls. */ ! 1099: #define ASM_OUTPUT_SKIP(STREAM, NBYTES) \ ! 1100: (arm_increase_location (NBYTES), \ ! 1101: fprintf (STREAM, "\t.space\t%d\n", NBYTES)) ! 1102: ! 1103: /* Align output to a power of two. Horrible /bin/as. */ ! 1104: #define ASM_OUTPUT_ALIGN(STREAM, POWER) \ ! 1105: do \ ! 1106: { \ ! 1107: register int amount = 1 << (POWER); \ ! 1108: extern int arm_text_location; \ ! 1109: \ ! 1110: if (amount == 2) \ ! 1111: fprintf (STREAM, "\t.even\n"); \ ! 1112: else \ ! 1113: fprintf (STREAM, "\t.align\t%d\n", amount - 4); \ ! 1114: \ ! 1115: if (in_text_section ()) \ ! 1116: arm_text_location = ((arm_text_location + amount - 1) \ ! 1117: & ~(amount - 1)); \ ! 1118: } while (0) ! 1119: ! 1120: /* Output a common block */ ! 1121: #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \ ! 1122: (fprintf (STREAM, "\t.comm\t"), \ ! 1123: assemble_name ((STREAM), (NAME)), \ ! 1124: fprintf(STREAM, ", %d\t@%d\n", ROUNDED, SIZE)) ! 1125: ! 1126: /* Output a local common block. /bin/as can't do this, so hack a `.space' into ! 1127: the bss segment. Note that this is *bad* practice. */ ! 1128: #define ASM_OUTPUT_LOCAL(STREAM,NAME,SIZE,ROUNDED) \ ! 1129: output_lcomm_directive (STREAM, NAME, SIZE, ROUNDED) ! 1130: ! 1131: /* Output a source filename for the debugger. RISCiX dbx insists that the ! 1132: ``desc'' field is set to compiler version number >= 315 (sic). */ ! 1133: #if 0 ! 1134: #define ASM_OUTPUT_SOURCE_FILENAME(STREAM,NAME) \ ! 1135: fprintf (STREAM, "\t.stabs\t\"%s\", %d, 0, 315, Ltext\n", (NAME), N_SOL) ! 1136: #endif ! 1137: ! 1138: /* Output a source line for the debugger. */ ! 1139: /* #define ASM_OUTPUT_SOURCE_LINE(STREAM,LINE) */ ! 1140: ! 1141: /* Output a #ident directive. */ ! 1142: #define ASM_OUTPUT_IDENT(STREAM,STRING) \ ! 1143: fprintf (STREAM,"- - - ident %s\n",STRING) ! 1144: ! 1145: /* The assembler's parentheses characters. */ ! 1146: #define ASM_OPEN_PAREN "(" ! 1147: #define ASM_CLOSE_PAREN ")" ! 1148: ! 1149: /* Target characters. */ ! 1150: #define TARGET_BELL 007 ! 1151: #define TARGET_BS 010 ! 1152: #define TARGET_TAB 011 ! 1153: #define TARGET_NEWLINE 012 ! 1154: #define TARGET_VT 013 ! 1155: #define TARGET_FF 014 ! 1156: #define TARGET_CR 015 ! 1157: ! 1158: /* FINAL_PRESCAN_INSN is used to take a look at the insns, in order to delete ! 1159: small-distance conditional branches and have ASM_OUTPUT_OPCODE make the ! 1160: instructions conditional. Suffixes like s (affect flags) and b (bytewise ! 1161: load/store) need to stay suffixes, so the possible condition code comes ! 1162: before these suffixes. */ ! 1163: #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ ! 1164: { \ ! 1165: extern int arm_ccfsm_state, arm_current_cc; \ ! 1166: extern char *arm_condition_codes[]; \ ! 1167: int i; \ ! 1168: \ ! 1169: fflush (STREAM); /* XXX for dubugging only. */ \ ! 1170: if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2) \ ! 1171: { \ ! 1172: fprintf (STREAM, "@ \t"); \ ! 1173: arm_ccfsm_state += 2; \ ! 1174: } \ ! 1175: else if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4) \ ! 1176: { \ ! 1177: for (i = 0; *(PTR) != ' ' && *(PTR) != '\t' && i < 3; i++, (PTR)++) \ ! 1178: putc (*(PTR), STREAM); \ ! 1179: fprintf (STREAM, "%s", arm_condition_codes[arm_current_cc]); \ ! 1180: for (; *(PTR) != ' ' && *(PTR) != '\t'; (PTR)++) \ ! 1181: putc (*(PTR), STREAM); \ ! 1182: } \ ! 1183: } ! 1184: ! 1185: /* Only perform branch elimination (by making instructions conditional) if ! 1186: we're optimising. Otherwise it's of no use anyway. */ ! 1187: #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ ! 1188: if (optimize) \ ! 1189: final_prescan_insn (INSN, OPVEC, NOPERANDS) ! 1190: ! 1191: /* Output an operand of an instruction. If X is a REG and CODE is `M', output ! 1192: a ldm/stm style multi-reg. */ ! 1193: #define PRINT_OPERAND(STREAM, X, CODE) \ ! 1194: { \ ! 1195: if ((CODE) == 'R') \ ! 1196: fputs (reg_names[REGNO (X) + 1], (STREAM)); \ ! 1197: else if (GET_CODE (X) == REG) \ ! 1198: { \ ! 1199: if ((CODE) != 'M') \ ! 1200: fputs (reg_names[REGNO (X)], (STREAM)); \ ! 1201: else \ ! 1202: fprintf ((STREAM), "{%s-%s}", \ ! 1203: reg_names[REGNO (X)], \ ! 1204: reg_names[REGNO (X) - 1 \ ! 1205: + ((GET_MODE_SIZE (GET_MODE (X)) \ ! 1206: + GET_MODE_SIZE (SImode) - 1) \ ! 1207: / GET_MODE_SIZE (SImode))]); \ ! 1208: } \ ! 1209: else if (GET_CODE (X) == MEM) \ ! 1210: { \ ! 1211: extern int output_memory_reference_mode; \ ! 1212: output_memory_reference_mode = GET_MODE (X); \ ! 1213: output_address (XEXP (X, 0)); \ ! 1214: } \ ! 1215: else if (GET_CODE(X) == CONST_DOUBLE) \ ! 1216: { \ ! 1217: union real_extract u; \ ! 1218: u.i[0] = CONST_DOUBLE_LOW (X); \ ! 1219: u.i[1] = CONST_DOUBLE_HIGH (X); \ ! 1220: fprintf(STREAM,"#%20.20f",u.d); \ ! 1221: } \ ! 1222: else if (GET_CODE (X) == NEG) \ ! 1223: { \ ! 1224: fputc ('-', (STREAM)); \ ! 1225: output_operand ((X), 0); \ ! 1226: } \ ! 1227: else \ ! 1228: { \ ! 1229: fputc('#', STREAM); \ ! 1230: output_addr_const(STREAM, X); \ ! 1231: } \ ! 1232: } ! 1233: ! 1234: /* Output the address of an operand. */ ! 1235: #define PRINT_OPERAND_ADDRESS(STREAM,X) \ ! 1236: { \ ! 1237: int is_minus = GET_CODE (X) == MINUS; \ ! 1238: \ ! 1239: if (GET_CODE (X) == REG) \ ! 1240: fprintf (STREAM, "[%s, #0]", reg_names[REGNO (X)]); \ ! 1241: else if (GET_CODE (X) == PLUS || is_minus) \ ! 1242: { \ ! 1243: rtx base = XEXP (X, 0); \ ! 1244: rtx index = XEXP (X, 1); \ ! 1245: char *base_reg_name; \ ! 1246: int offset = 0; \ ! 1247: int shift; \ ! 1248: if (GET_CODE (base) != REG) \ ! 1249: { \ ! 1250: /* Ensure that BASE is a register (one of them must be). */ \ ! 1251: rtx temp = base; \ ! 1252: base = index; \ ! 1253: index = temp; \ ! 1254: } \ ! 1255: base_reg_name = reg_names[REGNO (base)]; \ ! 1256: switch (GET_CODE (index)) \ ! 1257: { \ ! 1258: case CONST_INT: \ ! 1259: offset = INTVAL (index); \ ! 1260: if (is_minus) \ ! 1261: offset = -offset; \ ! 1262: fprintf (STREAM, "[%s, #%d]", base_reg_name, offset); \ ! 1263: break; \ ! 1264: \ ! 1265: case REG: \ ! 1266: fprintf (STREAM, "[%s, %s%s]", base_reg_name, \ ! 1267: is_minus ? "-" : "", reg_names[REGNO (index)] ); \ ! 1268: break; \ ! 1269: \ ! 1270: case MULT: \ ! 1271: if (GET_CODE (XEXP (index,0)) == CONST_INT) \ ! 1272: { \ ! 1273: shift = int_log2 (INTVAL (XEXP (index, 0))); \ ! 1274: index = XEXP (index, 1); \ ! 1275: } \ ! 1276: else if (GET_CODE(XEXP(index,1)) == CONST_INT) \ ! 1277: { \ ! 1278: shift = int_log2 (INTVAL (XEXP (index, 1))); \ ! 1279: index = XEXP (index, 0); \ ! 1280: } \ ! 1281: else \ ! 1282: abort(); \ ! 1283: fprintf (STREAM, "[%s, %s%s, asl#%d]", base_reg_name, \ ! 1284: is_minus ? "-" : "", reg_names[REGNO (index)], \ ! 1285: shift); \ ! 1286: break; \ ! 1287: \ ! 1288: default: \ ! 1289: abort(); \ ! 1290: } \ ! 1291: } \ ! 1292: else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \ ! 1293: || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \ ! 1294: { \ ! 1295: extern int output_memory_reference_mode; \ ! 1296: \ ! 1297: if (GET_CODE (XEXP (X, 0)) != REG) \ ! 1298: abort (); \ ! 1299: \ ! 1300: if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ ! 1301: fprintf (STREAM, "[%s, #%s%d]!", reg_names[REGNO (XEXP (X, 0))],\ ! 1302: GET_CODE (X) == PRE_DEC ? "-" : "", \ ! 1303: GET_MODE_SIZE (output_memory_reference_mode)); \ ! 1304: else \ ! 1305: fprintf (STREAM, "[%s], #%s%d", reg_names[REGNO (XEXP (X, 0))], \ ! 1306: GET_CODE (X) == POST_DEC ? "-" : "", \ ! 1307: GET_MODE_SIZE (output_memory_reference_mode)); \ ! 1308: } \ ! 1309: else output_addr_const(STREAM, X); \ ! 1310: } ! 1311: ! 1312: /* EOF arm.h */
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.