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1.1 root 1: /* Definitions of target machine for GNU compiler, for Acorn RISC Machine.
2: Copyright (C) 1991 Free Software Foundation, Inc.
3: Contributed by Pieter `Tiggr' Schoenmakers ([email protected])
4: and Martin Simmons (@harleqn.co.uk).
5:
6: This file is part of GNU CC.
7:
8: GNU CC is free software; you can redistribute it and/or modify
9: it under the terms of the GNU General Public License as published by
10: the Free Software Foundation; either version 2, or (at your option)
11: any later version.
12:
13: GNU CC is distributed in the hope that it will be useful,
14: but WITHOUT ANY WARRANTY; without even the implied warranty of
15: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16: GNU General Public License for more details.
17:
18: You should have received a copy of the GNU General Public License
19: along with GNU CC; see the file COPYING. If not, write to
20: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21:
22: /* Sometimes the directive `riscos' is checked. This does not imply that this
23: tm file can be used unchanged to build a GCC for RISC OS.
24: (Since in fact, it can't.) */
25:
26: extern void output_prologue ();
27: extern void output_epilogue ();
28: extern char *arm_output_asm_insn ();
29: extern char *arm_output_llc ();
30: extern char *output_add_immediate ();
31: extern char *output_call ();
32: extern char *output_move_double ();
33: extern char *output_mov_double_fpu_from_arm ();
34: extern char *output_mov_double_arm_from_fpu ();
35: extern char *output_mov_immediate ();
36: extern char *output_multi_immediate ();
37: extern char *output_shifted_move ();
38: extern char *output_arithmetic_with_immediate_multiply ();
39:
40: /* Translation to find startup files. On RISCiX boxes, gcrt0.o is in
41: /usr/lib. */
42: #define STARTFILE_SPEC \
43: "%{pg:/usr/lib/gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}"
44:
45: #ifdef riscos
46: #define CPP_PREDEFINES "-Darm -Driscos"
47: #else
48: #define CPP_PREDEFINES "-Darm -Driscix -Dunix"
49: #endif
50:
51: /* Run-time Target Specification. */
52: #define TARGET_VERSION \
53: fputs (" (ARM/RISCiX)", stderr);
54:
55: /* Run-time compilation parameters selecting different hardware subsets.
56: On the ARM, misuse it in a different way. */
57: extern int target_flags;
58:
59: /* Nonzero if the function prologue (and epilogue) should obey
60: the ARM Procedure Call Standard. */
61: #define TARGET_APCS (target_flags & 1)
62:
63: /* Nonzero if the function prologue should output the function name to enable
64: the post mortem debugger to print a backtrace (very useful on RISCOS,
65: unused on RISCiX). Specifying this flag also enables -mapcs.
66: XXX Must still be implemented in the prologue. */
67: #define TARGET_POKE_FUNCTION_NAME (target_flags & 2)
68:
69: /* Nonzero if floating point instructions are emulated by the FPE, in which
70: case instruction scheduling becomes very uninteresting. */
71: #define TARGET_FPE (target_flags & 4)
72:
73: #define TARGET_SWITCHES \
74: { \
75: {"apcs", 1}, \
76: {"poke-function-name", 2}, \
77: {"fpe", 4}, \
78: {"", TARGET_DEFAULT } \
79: }
80:
81: #define TARGET_DEFAULT 0
82:
83: #define TARGET_MEM_FUNCTIONS 1
84:
85: /* OVERRIDE_OPTIONS takes care of the following:
86: - if -mpoke-function-name, then -mapcs.
87: - if doing debugging, then -mapcs; if RISCOS, then -mpoke-function-name.
88: - if floating point is done by emulation, forget about instruction
89: scheduling. Note that this only saves compilation time; it doesn't
90: matter for the final code. */
91: #ifdef riscos
92: #define TARGET_WHEN_DEBUGGING 3
93: #else
94: #define TARGET_WHEN_DEBUGGING 1
95: #endif
96:
97: #define OVERRIDE_OPTIONS \
98: { \
99: if (write_symbols != NO_DEBUG) \
100: target_flags |= TARGET_WHEN_DEBUGGING; \
101: else if (TARGET_POKE_FUNCTION_NAME) \
102: target_flags |= 1; \
103: if (TARGET_FPE) \
104: flag_schedule_insns = flag_schedule_insns_after_reload = 0; \
105: }
106:
107: /* Omitting the frame pointer is a very good idea on the ARM, especially if
108: not TARGET_APCS, in which case all that pushing on function entry isn't
109: mandatory anymore. */
110: #define OPTIMIZATION_OPTIONS(OPTIMIZE) \
111: { \
112: if (OPTIMIZE) \
113: flag_omit_frame_pointer = 1; \
114: }
115:
116: /* Target machine storage Layout. */
117:
118: /* Define this if most significant bit is lowest numbered
119: in instructions that operate on numbered bit-fields. */
120: #define BITS_BIG_ENDIAN 0
121:
122: /* Define this if most significant byte of a word is the lowest numbered. */
123: #define BYTES_BIG_ENDIAN 0
124:
125: /* Define this if most significant word of a multiword number is the lowest
126: numbered. */
127: #define WORDS_BIG_ENDIAN 0
128:
129: /* Number of bits in an addressable storage unit */
130: #define BITS_PER_UNIT 8
131:
132: #define BITS_PER_WORD 32
133:
134: #define UNITS_PER_WORD 4
135:
136: #define POINTER_SIZE 32
137:
138: #define PARM_BOUNDARY 32
139:
140: #define STACK_BOUNDARY 32
141:
142: #define FUNCTION_BOUNDARY 32
143:
144: #define EMPTY_FIELD_BOUNDARY 32
145:
146: #define BIGGEST_ALIGNMENT 32
147:
148: /* Every structures size must be a multiple of 32 bits. */
149: #define STRUCTURE_SIZE_BOUNDARY 32
150:
151: #define STRICT_ALIGNMENT 1
152:
153: /* Define number of bits in most basic integer type.
154: (If undefined, default is BITS_PER_WORD). */
155: /* #define INT_TYPE_SIZE */
156:
157: /* Standard register usage. */
158:
159: /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
160: (S - saved over call).
161:
162: r0 * argument word/integer result
163: r1-r3 argument word
164:
165: r4-r8 S register variable
166: r9 S (rfp) register variable (real frame pointer)
167:
168: r10 F S (sl) stack limit (not currently used)
169: r11 F S (fp) argument pointer
170: r12 (ip) temp workspace
171: r13 F S (sp) lower end of current stack frame
172: r14 (lr) link address/workspace
173: r15 F (pc) program counter
174:
175: f0 floating point result
176: f1-f3 floating point scratch
177:
178: f4-f7 S floating point variable
179:
180: *: See CONDITIONAL_REGISTER_USAGE */
181:
182: /* The number of hard registers is 16 ARM + 8 FPU. */
183: #define FIRST_PSEUDO_REGISTER 24
184:
185: /* 1 for registers that have pervasive standard uses
186: and are not available for the register allocator. */
187: #define FIXED_REGISTERS \
188: { \
189: 0,0,0,0,0,0,0,0, \
190: 0,0,1,1,0,1,0,1, \
191: 0,0,0,0,0,0,0,0 \
192: }
193:
194: /* 1 for registers not available across function calls.
195: These must include the FIXED_REGISTERS and also any
196: registers that can be used without being saved.
197: The latter must include the registers where values are returned
198: and the register where structure-value addresses are passed.
199: Aside from that, you can include as many other registers as you like. */
200: #define CALL_USED_REGISTERS \
201: { \
202: 1,1,1,1,0,0,0,0, \
203: 0,0,1,1,1,1,1,1, \
204: 1,1,1,1,0,0,0,0 \
205: }
206:
207: /* If doing stupid life analysis, avoid a bug causing a return value r0 to be
208: trampled. This effectively reduces the number of available registers by 1.
209: XXX It is a hack, I know.
210: XXX Is this still needed? */
211: #define CONDITIONAL_REGISTER_USAGE \
212: { \
213: if (obey_regdecls) \
214: fixed_regs[0] = 1; \
215: }
216:
217: /* Return number of consecutive hard regs needed starting at reg REGNO
218: to hold something of mode MODE.
219: This is ordinarily the length in words of a value of mode MODE
220: but can be less for certain modes in special long registers.
221:
222: On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
223: mode. */
224: #define HARD_REGNO_NREGS(REGNO, MODE) \
225: ((REGNO) >= 16 ? 1 \
226: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
227:
228: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
229: This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
230: regs holding FP. */
231: #define HARD_REGNO_MODE_OK(REGNO, MODE) \
232: ((REGNO) < 16 || GET_MODE_CLASS (MODE) == MODE_FLOAT)
233:
234: /* Value is 1 if it is a good idea to tie two pseudo registers
235: when one has mode MODE1 and one has mode MODE2.
236: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
237: for any hard reg, then this must be 0 for correct output. */
238: #define MODES_TIEABLE_P(MODE1, MODE2) \
239: (((MODE1) == SFmode || (MODE1) == DFmode) \
240: == ((MODE2) == SFmode || (MODE2) == DFmode))
241:
242: /* Specify the registers used for certain standard purposes.
243: The values of these macros are register numbers. */
244:
245: /* Define this if the program counter is overloaded on a register. */
246: #define PC_REGNUM 15
247:
248: /* Register to use for pushing function arguments. */
249: #define STACK_POINTER_REGNUM 13
250:
251: /* Base register for access to local variables of the function. */
252: #define FRAME_POINTER_REGNUM 9
253:
254: /* Value should be nonzero if functions must have frame pointers.
255: Zero means the frame pointer need not be set up (and parms may be accessed
256: via the stack pointer) in functions that seem suitable. */
257: #define FRAME_POINTER_REQUIRED 0
258:
259: /* Base register for access to arguments of the function. */
260: #define ARG_POINTER_REGNUM 11
261:
262: /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
263: as an invisible last argument (possible since varargs don't exist in
264: Pascal), so the following is not true. */
265: #define STATIC_CHAIN_REGNUM 8
266:
267: /* Register in which address to store a structure value
268: is passed to a function. */
269: #define STRUCT_VALUE_REGNUM 0
270:
271: /* The order in which register should be allocated. It is good to use ip
272: since no saving is required (though calls clobber it). It is quite good to
273: use lr since other calls may clobber it anyway. */
274: #define REG_ALLOC_ORDER \
275: { \
276: 0, 1, 2, 3, 12, 14, 4, 5, \
277: 6, 7, 8, 10, 9, 11, 13, 15, \
278: 16, 17, 18, 19, 20, 21, 22, 23 \
279: }
280:
281: /* Register and constant classes. */
282:
283: /* Register classes: all ARM regs or all FPU regs---simple! */
284: enum reg_class
285: {
286: NO_REGS,
287: FPU_REGS,
288: GENERAL_REGS,
289: ALL_REGS,
290: LIM_REG_CLASSES
291: };
292:
293: #define N_REG_CLASSES (int) LIM_REG_CLASSES
294:
295: /* Give names of register classes as strings for dump file. */
296: #define REG_CLASS_NAMES \
297: { \
298: "NO_REGS", \
299: "FPU_REGS", \
300: "GENERAL_REGS", \
301: "ALL_REGS", \
302: }
303:
304: /* Define which registers fit in which classes.
305: This is an initializer for a vector of HARD_REG_SET
306: of length N_REG_CLASSES. */
307: #define REG_CLASS_CONTENTS \
308: { \
309: 0x000000, /* NO_REGS */ \
310: 0xFF0000, /* FPU_REGS */ \
311: 0x00FFFF, /* GENERAL_REGS */ \
312: 0xFFFFFF /* ALL_REGS */ \
313: }
314:
315: /* The same information, inverted:
316: Return the class number of the smallest class containing
317: reg number REGNO. This could be a conditional expression
318: or could index an array. */
319: #define REGNO_REG_CLASS(REGNO) \
320: ((REGNO) < 16 ? GENERAL_REGS : FPU_REGS)
321:
322: /* The class value for index registers, and the one for base regs. */
323: #define INDEX_REG_CLASS GENERAL_REGS
324: #define BASE_REG_CLASS GENERAL_REGS
325:
326: /* Get reg_class from a letter such as appears in the machine description.
327: We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
328: #define REG_CLASS_FROM_LETTER(C) \
329: ((C)=='f' ? FPU_REGS : NO_REGS)
330:
331: /* The letters I, J, K, L and M in a register constraint string
332: can be used to stand for particular ranges of immediate operands.
333: This macro defines what the ranges are.
334: C is the letter, and VALUE is a constant value.
335: Return 1 if VALUE is in the range specified by C.
336: I: immediate arithmetic operand (i.e. 8 bits shifted as required).
337: J: valid indexing constants. */
338: #define CONST_OK_FOR_LETTER_P(VALUE, C) \
339: ((C) == 'I' ? const_ok_for_arm (VALUE) : \
340: (C) == 'J' ? (abs (VALUE) < 4096) : 0)
341:
342: /* Constant letter 'G' for the FPU immediate constants. */
343: #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
344: ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) : 0)
345:
346: /* Given an rtx X being reloaded into a reg required to be
347: in class CLASS, return the class of reg to actually use.
348: In general this is just CLASS; but on some machines
349: in some cases it is preferable to use a more restrictive class. */
350: #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
351:
352: /* Return the maximum number of consecutive registers
353: needed to represent mode MODE in a register of class CLASS.
354: ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
355: #define CLASS_MAX_NREGS(CLASS, MODE) \
356: ((CLASS) == FPU_REGS ? 1 \
357: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
358:
359: /* Moves between FPU_REGS and GENERAL_REGS are two insns. */
360: #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
361: ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
362: || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
363: ? 4 : 2)
364:
365: /* Stack layout; function entry, exit and calling. */
366:
367: /* Define this if pushing a word on the stack
368: makes the stack pointer a smaller address. */
369: #define STACK_GROWS_DOWNWARD 1
370:
371: /* Define this if the nominal address of the stack frame
372: is at the high-address end of the local variables;
373: that is, each additional local variable allocated
374: goes at a more negative offset in the frame. */
375: #define FRAME_GROWS_DOWNWARD 1
376:
377: /* Offset within stack frame to start allocating local variables at.
378: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
379: first local allocated. Otherwise, it is the offset to the BEGINNING
380: of the first local allocated. */
381: #define STARTING_FRAME_OFFSET 0
382:
383: /* If we generate an insn to push BYTES bytes,
384: this says how many the stack pointer really advances by. */
385: #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
386:
387: /* Offset of first parameter from the argument pointer register value. */
388: #define FIRST_PARM_OFFSET(FNDECL) 4
389:
390: /* Value is the number of byte of arguments automatically
391: popped when returning from a subroutine call.
392: FUNTYPE is the data type of the function (as a tree),
393: or for a library call it is an identifier node for the subroutine name.
394: SIZE is the number of bytes of arguments passed on the stack.
395:
396: On the ARM, the caller does not pop any of its arguments that were passed
397: on the stack. */
398: #define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0
399:
400: /* Define how to find the value returned by a function.
401: VALTYPE is the data type of the value (as a tree).
402: If the precise function being called is known, FUNC is its FUNCTION_DECL;
403: otherwise, FUNC is 0. */
404: #define FUNCTION_VALUE(VALTYPE, FUNC) \
405: (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT \
406: ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \
407: : gen_rtx (REG, TYPE_MODE (VALTYPE), 0))
408:
409: /* Define how to find the value returned by a library function
410: assuming the value has mode MODE. */
411: #define LIBCALL_VALUE(MODE) \
412: (GET_MODE_CLASS (MODE) == MODE_FLOAT \
413: ? gen_rtx (REG, MODE, 16) \
414: : gen_rtx (REG, MODE, 0))
415:
416: /* 1 if N is a possible register number for a function value.
417: On the ARM, only r0 and f0 can return results. */
418: #define FUNCTION_VALUE_REGNO_P(REGNO) \
419: ((REGNO) == 0 || (REGNO) == 16)
420:
421: /* Define where to put the arguments to a function.
422: Value is zero to push the argument on the stack,
423: or a hard register in which to store the argument.
424:
425: MODE is the argument's machine mode.
426: TYPE is the data type of the argument (as a tree).
427: This is null for libcalls where that information may
428: not be available.
429: CUM is a variable of type CUMULATIVE_ARGS which gives info about
430: the preceding args and about the function being called.
431: NAMED is nonzero if this argument is a named parameter
432: (otherwise it is an extra parameter matching an ellipsis).
433:
434: On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
435: other arguments are passed on the stack. If (NAMED == 0) (which happens
436: only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
437: passed in the stack (function_prologue will indeed make it pass in the
438: stack if necessary). */
439: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
440: ((NAMED) \
441: ? ((CUM) >= 16 ? 0 : gen_rtx (REG, MODE, (CUM) / 4)) \
442: : 0)
443:
444: /* For an arg passed partly in registers and partly in memory,
445: this is the number of registers used.
446: For args passed entirely in registers or entirely in memory, zero. */
447: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
448: ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \
449: ? GET_MODE_SIZE (MODE) \
450: : int_size_in_bytes (TYPE)) \
451: ? 4 - (CUM) / 4 : 0)
452:
453: /* A C type for declaring a variable that is used as the first argument of
454: `FUNCTION_ARG' and other related values. For some target machines, the
455: type `int' suffices and can hold the number of bytes of argument so far.
456:
457: On the ARM, this is the number of bytes of arguments scanned so far. */
458: #define CUMULATIVE_ARGS int
459:
460: /* Initialize a variable CUM of type CUMULATIVE_ARGS
461: for a call to a function whose data type is FNTYPE.
462: For a library call, FNTYPE is 0.
463: On the ARM, the offset starts at 0. */
464: #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \
465: ((CUM) = (((FNTYPE) && aggregate_value_p (FNTYPE)) ? 4 : 0))
466:
467: /* Update the data in CUM to advance over an argument
468: of mode MODE and data type TYPE.
469: (TYPE is null for libcalls where that information may not be available.) */
470: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
471: (CUM) += ((MODE) != BLKmode \
472: ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
473: : (int_size_in_bytes (TYPE) + 3) & ~3) \
474:
475: /* 1 if N is a possible register number for function argument passing.
476: On the ARM, r0-r3 are used to pass args. */
477: #define FUNCTION_ARG_REGNO_P(REGNO) \
478: ((REGNO) >= 0 && (REGNO) <= 3)
479:
480: /* Perform any actions needed for a function that is receiving a variable
481: number of arguments. CUM is as above. MODE and TYPE are the mode and type
482: of the current parameter. PRETEND_SIZE is a variable that should be set to
483: the amount of stack that must be pushed by the prolog to pretend that our
484: caller pushed it.
485:
486: Normally, this macro will push all remaining incoming registers on the
487: stack and set PRETEND_SIZE to the length of the registers pushed.
488:
489: On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
490: named arg and all anonymous args onto the stack.
491: XXX I know the prologue shouldn't be pushing registers, but it is faster
492: that way. */
493: #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
494: { \
495: extern int current_function_anonymous_args; \
496: current_function_anonymous_args = 1; \
497: if ((CUM) < 16) \
498: (PRETEND_SIZE) = 16 - (CUM); \
499: }
500:
501: /* Generate assembly output for the start of a function. */
502: #define FUNCTION_PROLOGUE(STREAM, SIZE) \
503: output_prologue ((STREAM), (SIZE))
504:
505: /* Call the function profiler with a given profile label. The Acorn compiler
506: puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr''
507: seems like a good idea to stick with cc convention. ``prof'' doesn't seem
508: to mind about this! */
509: #define FUNCTION_PROFILER(STREAM,LABELNO) \
510: { \
511: fprintf(STREAM, "\tmov\tip, lr\n"); \
512: fprintf(STREAM, "\tbl\tmcount\n"); \
513: fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \
514: arm_increase_location (12); \
515: }
516:
517: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
518: the stack pointer does not matter. The value is tested only in
519: functions that have frame pointers.
520: No definition is equivalent to always zero.
521:
522: On the ARM, the function epilogue recovers the stack pointer from the
523: frame. */
524: #define EXIT_IGNORE_STACK 1
525:
526: /* Generate the assembly code for function exit. */
527: #define FUNCTION_EPILOGUE(STREAM, SIZE) \
528: output_epilogue ((STREAM), (SIZE))
529:
530: /* Determine if the epilogue should be output as RTL.
531: You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
532: /* #define USE_RETURN_INSN use_return_insn () */
533:
534: /* Store in the variable DEPTH the initial difference between the frame
535: pointer reg contents and the stack pointer reg contents, as of the start of
536: the function body. This depends on the layout of the fixed parts of the
537: stack frame and on how registers are saved. */
538: #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
539: (DEPTH) = (get_frame_size () + 3) & ~3;
540:
541: /* Output assembler code for a block containing the constant parts
542: of a trampoline, leaving space for the variable parts.
543:
544: On the ARM, (if r8 is the static chain regnum, and remembering that
545: referencing pc adds an offset of 8) the trampoline looks like:
546: ldr r8, [pc, #0]
547: ldr pc, [pc]
548: .word static chain value
549: .word function's address */
550: #define TRAMPOLINE_TEMPLATE(FILE) \
551: { \
552: fprintf ((FILE), "\tldr\tr8, [pc, #0]\n"); \
553: fprintf ((FILE), "\tldr\tpc, [pc, #0]\n"); \
554: fprintf ((FILE), "\t.word\t0\n"); \
555: fprintf ((FILE), "\t.word\t0\n"); \
556: }
557:
558: /* Length in units of the trampoline for entering a nested function. */
559: #define TRAMPOLINE_SIZE 16
560:
561: /* Alignment required for a trampoline in units. */
562: #define TRAMPOLINE_ALIGN 4
563:
564: /* Emit RTL insns to initialize the variable parts of a trampoline.
565: FNADDR is an RTX for the address of the function's pure code.
566: CXT is an RTX for the static chain value for the function. */
567: #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
568: { \
569: emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
570: (CXT)); \
571: emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
572: (FNADDR)); \
573: }
574:
575: /* Call the function profiler with a given profile label. The Acorn compiler
576: puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr''
577: seems like a good idea to stick with cc convention. ``prof'' doesn't seem
578: to mind about this! */
579: #define FUNCTION_PROFILER(STREAM,LABELNO) \
580: { \
581: fprintf(STREAM, "\tmov\tip, lr\n"); \
582: fprintf(STREAM, "\tbl\tmcount\n"); \
583: fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \
584: arm_increase_location (12); \
585: }
586:
587: /* Addressing modes, and classification of registers for them. */
588:
589: #define HAVE_POST_INCREMENT 1
590: #define HAVE_PRE_INCREMENT 1
591: #define HAVE_POST_DECREMENT 1
592: #define HAVE_PRE_DECREMENT 1
593:
594: /* Macros to check register numbers against specific register classes. */
595:
596: /* These assume that REGNO is a hard or pseudo reg number.
597: They give nonzero only if REGNO is a hard reg of the suitable class
598: or a pseudo reg currently allocated to a suitable hard reg.
599: Since they use reg_renumber, they are safe only once reg_renumber
600: has been allocated, which happens in local-alloc.c.
601:
602: On the ARM, don't allow the pc to be used. */
603: #define REGNO_OK_FOR_BASE_P(REGNO) \
604: ((REGNO) < 15 || (unsigned) reg_renumber[(REGNO)] < 15)
605: #define REGNO_OK_FOR_INDEX_P(REGNO) \
606: REGNO_OK_FOR_BASE_P(REGNO)
607:
608: /* Maximum number of registers that can appear in a valid memory address.
609: The addressing mode [ra,rb, <shift> rc] uses the greatest number of
610: registers. */
611: #define MAX_REGS_PER_ADDRESS 3
612:
613: /* Recognize any constant value that is a valid address. */
614: /* XXX We can address any constant, eventually... */
615: #if 0
616: #define CONSTANT_ADDRESS_P(X) \
617: ( GET_CODE(X) == LABEL_REF \
618: || GET_CODE(X) == SYMBOL_REF \
619: || GET_CODE(X) == CONST_INT \
620: || GET_CODE(X) == CONST )
621: #endif
622:
623: #define CONSTANT_ADDRESS_P(X) \
624: (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
625:
626: /* Nonzero if the constant value X is a legitimate general operand.
627: It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
628:
629: On the ARM, allow any integer (invalid ones are removed later by insn
630: patterns), nice doubles and symbol_refs which refer to the function's
631: constant pool XXX. */
632: #define LEGITIMATE_CONSTANT_P(X) \
633: (GET_CODE (X) == CONST_INT \
634: || (GET_CODE (X) == CONST_DOUBLE \
635: && const_double_rtx_ok_for_fpu (X)))
636: #if 0
637: || GET_CODE(X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P(X))
638: #endif
639:
640: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
641: and check its validity for a certain class.
642: We have two alternate definitions for each of them.
643: The usual definition accepts all pseudo regs; the other rejects
644: them unless they have been allocated suitable hard regs.
645: The symbol REG_OK_STRICT causes the latter definition to be used. */
646: #ifndef REG_OK_STRICT
647: /* Nonzero if X is a hard reg that can be used as a base reg
648: or if it is a pseudo reg. */
649: #define REG_OK_FOR_BASE_P(X) \
650: (REGNO (X) < 16 || REGNO (X) >= 24)
651: /* Nonzero if X is a hard reg that can be used as an index
652: or if it is a pseudo reg. */
653: #define REG_OK_FOR_INDEX_P(X) \
654: REG_OK_FOR_BASE_P(X)
655: #define REG_OK_FOR_PRE_POST_P(X) \
656: (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
657: #else
658: /* Nonzero if X is a hard reg that can be used as a base reg. */
659: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
660: /* Nonzero if X is a hard reg that can be used as an index. */
661: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
662: #define REG_OK_FOR_PRE_POST_P(X) \
663: (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16)
664: #endif
665:
666: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
667: that is a valid memory address for an instruction.
668: The MODE argument is the machine mode for the MEM expression
669: that wants to use this address.
670:
671: The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
672: #define BASE_REGISTER_RTX_P(X) \
673: (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
674:
675: #define INDEX_REGISTER_RTX_P(X) \
676: (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
677:
678: /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
679: used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
680: only be small constants. */
681: #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
682: do \
683: { \
684: int range; \
685: \
686: if (GET_MODE_CLASS (MODE) == MODE_FLOAT) \
687: range = 1024; \
688: else \
689: { \
690: if (INDEX_REGISTER_RTX_P (INDEX)) \
691: goto LABEL; \
692: if (GET_MODE_SIZE (MODE) <= 4 && GET_CODE (INDEX) == MULT) \
693: { \
694: rtx xiop0 = XEXP (INDEX, 0); \
695: rtx xiop1 = XEXP (INDEX, 1); \
696: if (INDEX_REGISTER_RTX_P (xiop0) \
697: && power_of_two_operand (xiop1, SImode)) \
698: goto LABEL; \
699: if (INDEX_REGISTER_RTX_P (xiop1) \
700: && power_of_two_operand (xiop0, SImode)) \
701: goto LABEL; \
702: } \
703: range = 4096; \
704: } \
705: \
706: if (GET_CODE (INDEX) == CONST_INT && INTVAL (INDEX) < range \
707: && INTVAL (INDEX) > -range) \
708: goto LABEL; \
709: } while (0)
710:
711: /* Jump to LABEL if X is a valid address RTX. This must also take
712: REG_OK_STRICT into account when deciding about valid registers, but it uses
713: the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
714: INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
715: Allow REG-only and AUTINC-REG if handling TImode. Other symbol refs must
716: be forced though a static cell to ensure addressability. */
717: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
718: { \
719: if (BASE_REGISTER_RTX_P (X)) \
720: goto LABEL; \
721: else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
722: && GET_CODE (XEXP (X, 0)) == REG \
723: && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
724: goto LABEL; \
725: else if ((MODE) == TImode) \
726: ; \
727: else if (GET_CODE (X) == PLUS) \
728: { \
729: rtx xop0 = XEXP(X,0); \
730: rtx xop1 = XEXP(X,1); \
731: \
732: if (BASE_REGISTER_RTX_P (xop0)) \
733: GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
734: else if (BASE_REGISTER_RTX_P (xop1)) \
735: GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
736: } \
737: else if (GET_CODE (X) == MINUS) \
738: { \
739: rtx xop0 = XEXP (X,0); \
740: rtx xop1 = XEXP (X,1); \
741: \
742: if (BASE_REGISTER_RTX_P (xop0)) \
743: GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
744: } \
745: else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
746: && GET_CODE (X) == SYMBOL_REF \
747: && CONSTANT_POOL_ADDRESS_P (X)) \
748: goto LABEL; \
749: else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
750: && GET_CODE (XEXP (X, 0)) == REG \
751: && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
752: goto LABEL; \
753: }
754:
755: /* Try machine-dependent ways of modifying an illegitimate address
756: to be legitimate. If we find one, return the new, valid address.
757: This macro is used in only one place: `memory_address' in explow.c.
758:
759: OLDX is the address as it was before break_out_memory_refs was called.
760: In some cases it is useful to look at this to decide what needs to be done.
761:
762: MODE and WIN are passed so that this macro can use
763: GO_IF_LEGITIMATE_ADDRESS.
764:
765: It is always safe for this macro to do nothing. It exists to recognize
766: opportunities to optimize the output.
767:
768: On the ARM, try to convert [REG, #BIGCONST]
769: into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
770: where VALIDCONST == 0 in case of TImode. */
771: #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
772: { \
773: if (GET_CODE (X) == PLUS) \
774: { \
775: rtx xop0 = XEXP (X, 0); \
776: rtx xop1 = XEXP (X, 1); \
777: \
778: if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
779: { \
780: int n = INTVAL (xop1); \
781: int low_n = ((MODE) == TImode ? 0 \
782: : n >= 0 ? (n & 0xFFF) : -((-n) & 0xFFF)); \
783: rtx base_reg = gen_reg_rtx (SImode); \
784: rtx val = force_operand (gen_rtx (PLUS, SImode, xop0, \
785: gen_rtx (CONST_INT, \
786: VOIDmode, n - low_n)), \
787: 0); \
788: emit_move_insn (base_reg, val); \
789: (X) = (low_n == 0 ? base_reg \
790: : gen_rtx (PLUS, SImode, base_reg, \
791: gen_rtx (CONST_INT, VOIDmode, low_n))); \
792: } \
793: else if (BASE_REGISTER_RTX_P (xop1) && GET_CODE (xop0) == CONST_INT) \
794: { \
795: int n = INTVAL (xop0); \
796: int low_n = ((MODE) == TImode ? 0 \
797: : n >= 0 ? (n & 0xFFF) : -((-n) & 0xFFF)); \
798: rtx base_reg = gen_reg_rtx (SImode); \
799: rtx val = force_operand (gen_rtx (PLUS, SImode, xop1, \
800: gen_rtx (CONST_INT, \
801: VOIDmode, n - low_n)), \
802: 0); \
803: emit_move_insn (base_reg, val); \
804: (X) = (low_n == 0 ? base_reg \
805: : gen_rtx (PLUS, SImode, base_reg, \
806: gen_rtx (CONST_INT, VOIDmode, low_n))); \
807: } \
808: } \
809: if (memory_address_p (MODE, X)) \
810: goto win; \
811: }
812:
813: /* Go to LABEL if ADDR (a legitimate address expression)
814: has an effect that depends on the machine mode it is used for. */
815: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
816: { \
817: if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
818: || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
819: goto LABEL; \
820: }
821:
822: /* Specify the machine mode that this machine uses
823: for the index in the tablejump instruction. */
824: #define CASE_VECTOR_MODE SImode
825:
826: /* Define this if the tablejump instruction expects the table
827: to contain offsets from the address of the table.
828: Do not define this if the table should contain absolute addresses. */
829: /* #define CASE_VECTOR_PC_RELATIVE */
830:
831: /* Specify the tree operation to be used to convert reals to integers. */
832: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
833:
834: /* This is the kind of divide that is easiest to do in the general case. */
835: #define EASY_DIV_EXPR TRUNC_DIV_EXPR
836:
837: /* 'char' is signed by default on RISCiX, unsigned on RISCOS. */
838: #ifdef riscos
839: #define DEFAULT_SIGNED_CHAR 0
840: #else
841: #define DEFAULT_SIGNED_CHAR 1
842: #endif
843:
844: /* Don't cse the address of the function being compiled. */
845: #define NO_RECURSIVE_FUNCTION_CSE 1
846:
847: /* Max number of bytes we can move from memory to memory
848: in one reasonably fast instruction. */
849: #define MOVE_MAX 4
850:
851: /* Define if normal loads of shorter-than-word items from memory clears
852: the rest of the bigs in the register.
853: On the ARM, movhi does a garbage extend. */
854: /* #define BYTE_LOADS_ZERO_EXTEND */
855:
856: /* Define this if zero-extension is slow (more than one real instruction).
857: On the ARM, it is more than one instruction only if not fetching from
858: memory. */
859: /* #define SLOW_ZERO_EXTEND */
860:
861: /* Nonzero if access to memory by bytes is slow and undesirable. */
862: #define SLOW_BYTE_ACCESS 0
863:
864: /* Immediate shift counts are truncated by the output routines (or was it
865: the assembler?). Shift counts in a register are truncated by ARM. Note
866: that the native compiler puts too large (> 32) immediate shift counts
867: into a register and shifts by the register, letting the ARM decide what
868: to do instead of doing that itself. */
869: #define SHIFT_COUNT_TRUNCATED 1
870:
871: /* We have the vprintf function. */
872: #define HAVE_VPRINTF 1
873:
874: /* XX This is not true, is it? */
875: /* All integers have the same format so truncation is easy. */
876: #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
877:
878: /* Calling from registers is a massive pain. */
879: #define NO_FUNCTION_CSE 1
880:
881: /* Chars and shorts should be passed as ints. */
882: #define PROMOTE_PROTOTYPES 1
883:
884: /* The machine modes of pointers and functions */
885: #define Pmode SImode
886: #define FUNCTION_MODE Pmode
887:
888: /* The structure type of the machine dependent info field of insns
889: No uses for this yet. */
890: /* #define INSN_MACHINE_INFO struct machine_info */
891:
892: /* The relative costs of various types of constants. Note that cse.c defines
893: REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
894: #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
895: case CONST_INT: \
896: if (const_ok_for_arm (INTVAL (RTX))) \
897: return (2); \
898: else \
899: return (5); \
900: \
901: case CONST: \
902: case LABEL_REF: \
903: case SYMBOL_REF: \
904: return (6); \
905: \
906: case CONST_DOUBLE: \
907: if (const_double_rtx_ok_for_fpu (RTX)) \
908: return(2); \
909: else \
910: return(7);
911:
912: /* Condition code information. */
913:
914: /* Store in cc_status the expressions
915: that the condition codes will describe
916: after execution of an instruction whose pattern is EXP.
917: Do not alter them if the instruction would not alter the cc's. */
918:
919: /* On the ARM nothing sets the condition code implicitly---apart from DImode
920: operations excluding moves---but we have to watch for registers in the
921: condition code value being clobbered. This clobbering includes (alas)
922: function calls. XXX They could just be considered to clobber regs 0-3 and
923: 10-15 with extra work. */
924: #define NOTICE_UPDATE_CC(EXP, INSN) \
925: { \
926: if (GET_MODE (EXP) == DImode \
927: && GET_CODE (EXP) == SET \
928: && GET_CODE (SET_SRC (EXP)) != REG \
929: && GET_CODE (SET_SRC (EXP)) != MEM \
930: && GET_CODE (SET_SRC (EXP)) != CONST_INT) \
931: CC_STATUS_INIT; \
932: else if (GET_CODE (EXP) == SET) \
933: { \
934: rtx dest = SET_DEST (EXP); \
935: if (dest == cc0_rtx) \
936: { \
937: cc_status.flags = 0; \
938: cc_status.value1 = SET_DEST (EXP); \
939: cc_status.value2 = SET_SRC (EXP); \
940: } \
941: if (BASE_REGISTER_RTX_P (dest)) \
942: { \
943: if (cc_status.value1 \
944: && reg_overlap_mentioned_p (dest, cc_status.value1)) \
945: cc_status.value1 = 0; \
946: if (cc_status.value2 \
947: && reg_overlap_mentioned_p (dest, cc_status.value2)) \
948: cc_status.value2 = 0; \
949: } \
950: } \
951: else if (GET_CODE (INSN) != JUMP_INSN && GET_CODE (EXP) == PARALLEL) \
952: { \
953: CC_STATUS_INIT; \
954: } \
955: }
956:
957: /* Assembler output control */
958:
959: /* The text to go at the start of the assembler file */
960: #define ASM_FILE_START(STREAM) \
961: { \
962: extern char *version_string; \
963: \
964: fprintf (STREAM,"@ Generated by gcc %s for ARM/RISCiX\n", version_string); \
965: fprintf (STREAM,"rfp\t.req\tr9\n"); \
966: fprintf (STREAM,"fp\t.req\tr11\n"); \
967: fprintf (STREAM,"ip\t.req\tr12\n"); \
968: fprintf (STREAM,"sp\t.req\tr13\n"); \
969: fprintf (STREAM,"lr\t.req\tr14\n"); \
970: fprintf (STREAM,"pc\t.req\tr15\n"); \
971: }
972:
973: #define ASM_APP_ON ""
974: #define ASM_APP_OFF ""
975:
976: /* Switch to the text or data segment. */
977: #define TEXT_SECTION_ASM_OP ".text"
978: #define DATA_SECTION_ASM_OP ".data"
979:
980: /* The assembler's names for the registers. RFP need not always be used as
981: the Real framepointer; it can also be used as a normal general register.
982: Note that the name `fp' is horribly misleading since `fp' is in fact only
983: the argument-and-return-context pointer. */
984: #define REGISTER_NAMES \
985: { \
986: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
987: "r8","rfp", "sl", "fp", "ip", "sp", "lr", "pc", \
988: "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7" \
989: }
990:
991: /* DBX register number for a given compiler register number */
992: #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
993:
994: /* Generate DBX debugging information. */
995: #define DBX_DEBUGGING_INFO 1
996:
997: /* Acorn dbx moans about continuation chars, so don't use any. */
998: #define DBX_CONTIN_LENGTH 0
999:
1000: /* Output a label definition. */
1001: #define ASM_OUTPUT_LABEL(STREAM,NAME) \
1002: arm_asm_output_label ((STREAM), (NAME))
1003:
1004: /* Output a function label definition. */
1005: #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
1006: ASM_OUTPUT_LABEL(STREAM, NAME)
1007:
1008: /* Output a globalising directive for a label. */
1009: #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1010: (fprintf (STREAM, "\t.global\t"), \
1011: assemble_name (STREAM, NAME), \
1012: fputc ('\n',STREAM)) \
1013:
1014: /* Output a reference to a label. */
1015: #define ASM_OUTPUT_LABELREF(STREAM,NAME) \
1016: fprintf (STREAM, "_%s", NAME)
1017:
1018: /* Make an internal label into a string. */
1019: #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1020: sprintf (STRING, "*%s%d", PREFIX, NUM)
1021:
1022: /* Output an internal label definition. */
1023: #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
1024: do \
1025: { \
1026: char *s = (char *) alloca (11 + strlen (PREFIX)); \
1027: extern int arm_target_label, arm_ccfsm_state; \
1028: \
1029: if (arm_ccfsm_state == 3 && arm_target_label == (NUM)) \
1030: arm_ccfsm_state = 0; \
1031: strcpy (s, "*"); \
1032: sprintf (&s[strlen (s)], "%s%d", (PREFIX), (NUM)); \
1033: arm_asm_output_label (STREAM, s); \
1034: } while (0)
1035:
1036: /* Nothing special is done about jump tables */
1037: /* #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) */
1038: /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1039:
1040: /* Construct a private name. */
1041: #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1042: ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1043: sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
1044:
1045: /* Output a push or a pop instruction (only used when profiling). */
1046: #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
1047: (arm_increase_location (4) \
1048: , fprintf(STREAM,"\tstmfd\tsp!,{%s}\n", reg_names[REGNO]))
1049:
1050: #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
1051: (arm_increase_location (4) \
1052: , fprintf(STREAM,"\tldmfd\tsp!,{%s}\n", reg_names[REGNO]))
1053:
1054: /* Output a relative address. Not needed since jump tables are absolute
1055: but we must define it anyway. */
1056: #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \
1057: fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM)
1058:
1059: /* Output an element of a dispatch table. */
1060: #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1061: (arm_increase_location (4) \
1062: , fprintf (STREAM, "\t.word\tL%d\n", VALUE))
1063:
1064: /* Output various types of constants. */
1065: #define ASM_OUTPUT_DOUBLE(STREAM, VALUE) \
1066: (arm_increase_location (sizeof (double)) \
1067: , fprintf (STREAM, "\t.double\t%20.20f\n", VALUE))
1068:
1069: #define ASM_OUTPUT_FLOAT(STREAM, VALUE) \
1070: (arm_increase_location (sizeof (float)) \
1071: , fprintf (STREAM, "\t.float\t%20.20f\n", VALUE))
1072:
1073: #define ASM_OUTPUT_INT(STREAM, EXP) \
1074: (fprintf (STREAM, "\t.word\t"), \
1075: output_addr_const (STREAM, (EXP)), \
1076: arm_increase_location (4), \
1077: fputc ('\n', STREAM))
1078:
1079: #define ASM_OUTPUT_SHORT(STREAM, EXP) \
1080: (fprintf (STREAM, "\t.short\t"), \
1081: output_addr_const (STREAM, (EXP)), \
1082: arm_increase_location (2), \
1083: fputc ('\n', STREAM))
1084:
1085: #define ASM_OUTPUT_CHAR(STREAM, EXP) \
1086: (fprintf (STREAM, "\t.byte\t"), \
1087: output_addr_const (STREAM, (EXP)), \
1088: arm_increase_location (1), \
1089: fputc ('\n', STREAM))
1090:
1091: #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1092: (fprintf (STREAM, "\t.byte\t%d\n", VALUE), \
1093: arm_increase_location (1))
1094:
1095: #define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) \
1096: output_ascii_pseudo_op ((STREAM), (PTR), (LEN))
1097:
1098: /* Output a gap. In fact we fill it with nulls. */
1099: #define ASM_OUTPUT_SKIP(STREAM, NBYTES) \
1100: (arm_increase_location (NBYTES), \
1101: fprintf (STREAM, "\t.space\t%d\n", NBYTES))
1102:
1103: /* Align output to a power of two. Horrible /bin/as. */
1104: #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
1105: do \
1106: { \
1107: register int amount = 1 << (POWER); \
1108: extern int arm_text_location; \
1109: \
1110: if (amount == 2) \
1111: fprintf (STREAM, "\t.even\n"); \
1112: else \
1113: fprintf (STREAM, "\t.align\t%d\n", amount - 4); \
1114: \
1115: if (in_text_section ()) \
1116: arm_text_location = ((arm_text_location + amount - 1) \
1117: & ~(amount - 1)); \
1118: } while (0)
1119:
1120: /* Output a common block */
1121: #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
1122: (fprintf (STREAM, "\t.comm\t"), \
1123: assemble_name ((STREAM), (NAME)), \
1124: fprintf(STREAM, ", %d\t@%d\n", ROUNDED, SIZE))
1125:
1126: /* Output a local common block. /bin/as can't do this, so hack a `.space' into
1127: the bss segment. Note that this is *bad* practice. */
1128: #define ASM_OUTPUT_LOCAL(STREAM,NAME,SIZE,ROUNDED) \
1129: output_lcomm_directive (STREAM, NAME, SIZE, ROUNDED)
1130:
1131: /* Output a source filename for the debugger. RISCiX dbx insists that the
1132: ``desc'' field is set to compiler version number >= 315 (sic). */
1133: #if 0
1134: #define ASM_OUTPUT_SOURCE_FILENAME(STREAM,NAME) \
1135: fprintf (STREAM, "\t.stabs\t\"%s\", %d, 0, 315, Ltext\n", (NAME), N_SOL)
1136: #endif
1137:
1138: /* Output a source line for the debugger. */
1139: /* #define ASM_OUTPUT_SOURCE_LINE(STREAM,LINE) */
1140:
1141: /* Output a #ident directive. */
1142: #define ASM_OUTPUT_IDENT(STREAM,STRING) \
1143: fprintf (STREAM,"- - - ident %s\n",STRING)
1144:
1145: /* The assembler's parentheses characters. */
1146: #define ASM_OPEN_PAREN "("
1147: #define ASM_CLOSE_PAREN ")"
1148:
1149: /* Target characters. */
1150: #define TARGET_BELL 007
1151: #define TARGET_BS 010
1152: #define TARGET_TAB 011
1153: #define TARGET_NEWLINE 012
1154: #define TARGET_VT 013
1155: #define TARGET_FF 014
1156: #define TARGET_CR 015
1157:
1158: /* FINAL_PRESCAN_INSN is used to take a look at the insns, in order to delete
1159: small-distance conditional branches and have ASM_OUTPUT_OPCODE make the
1160: instructions conditional. Suffixes like s (affect flags) and b (bytewise
1161: load/store) need to stay suffixes, so the possible condition code comes
1162: before these suffixes. */
1163: #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1164: { \
1165: extern int arm_ccfsm_state, arm_current_cc; \
1166: extern char *arm_condition_codes[]; \
1167: int i; \
1168: \
1169: fflush (STREAM); /* XXX for debugging only. */ \
1170: if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2) \
1171: { \
1172: fprintf (STREAM, "@ \t"); \
1173: arm_ccfsm_state += 2; \
1174: } \
1175: else if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4) \
1176: { \
1177: for (i = 0; *(PTR) != ' ' && *(PTR) != '\t' && i < 3; i++, (PTR)++) \
1178: putc (*(PTR), STREAM); \
1179: fprintf (STREAM, "%s", arm_condition_codes[arm_current_cc]); \
1180: for (; *(PTR) != ' ' && *(PTR) != '\t'; (PTR)++) \
1181: putc (*(PTR), STREAM); \
1182: } \
1183: }
1184:
1185: /* Only perform branch elimination (by making instructions conditional) if
1186: we're optimising. Otherwise it's of no use anyway. */
1187: #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1188: if (optimize) \
1189: final_prescan_insn (INSN, OPVEC, NOPERANDS)
1190:
1191: /* Output an operand of an instruction. If X is a REG and CODE is `M', output
1192: a ldm/stm style multi-reg. */
1193: #define PRINT_OPERAND(STREAM, X, CODE) \
1194: { \
1195: if ((CODE) == 'R') \
1196: fputs (reg_names[REGNO (X) + 1], (STREAM)); \
1197: else if (GET_CODE (X) == REG) \
1198: { \
1199: if ((CODE) != 'M') \
1200: fputs (reg_names[REGNO (X)], (STREAM)); \
1201: else \
1202: fprintf ((STREAM), "{%s-%s}", \
1203: reg_names[REGNO (X)], \
1204: reg_names[REGNO (X) - 1 \
1205: + ((GET_MODE_SIZE (GET_MODE (X)) \
1206: + GET_MODE_SIZE (SImode) - 1) \
1207: / GET_MODE_SIZE (SImode))]); \
1208: } \
1209: else if (GET_CODE (X) == MEM) \
1210: { \
1211: extern int output_memory_reference_mode; \
1212: output_memory_reference_mode = GET_MODE (X); \
1213: output_address (XEXP (X, 0)); \
1214: } \
1215: else if (GET_CODE(X) == CONST_DOUBLE) \
1216: { \
1217: union real_extract u; \
1218: u.i[0] = CONST_DOUBLE_LOW (X); \
1219: u.i[1] = CONST_DOUBLE_HIGH (X); \
1220: fprintf(STREAM,"#%20.20f",u.d); \
1221: } \
1222: else if (GET_CODE (X) == NEG) \
1223: { \
1224: fputc ('-', (STREAM)); \
1225: output_operand ((X), 0); \
1226: } \
1227: else \
1228: { \
1229: fputc('#', STREAM); \
1230: output_addr_const(STREAM, X); \
1231: } \
1232: }
1233:
1234: /* Output the address of an operand. */
1235: #define PRINT_OPERAND_ADDRESS(STREAM,X) \
1236: { \
1237: int is_minus = GET_CODE (X) == MINUS; \
1238: \
1239: if (GET_CODE (X) == REG) \
1240: fprintf (STREAM, "[%s, #0]", reg_names[REGNO (X)]); \
1241: else if (GET_CODE (X) == PLUS || is_minus) \
1242: { \
1243: rtx base = XEXP (X, 0); \
1244: rtx index = XEXP (X, 1); \
1245: char *base_reg_name; \
1246: int offset = 0; \
1247: int shift; \
1248: if (GET_CODE (base) != REG) \
1249: { \
1250: /* Ensure that BASE is a register (one of them must be). */ \
1251: rtx temp = base; \
1252: base = index; \
1253: index = temp; \
1254: } \
1255: base_reg_name = reg_names[REGNO (base)]; \
1256: switch (GET_CODE (index)) \
1257: { \
1258: case CONST_INT: \
1259: offset = INTVAL (index); \
1260: if (is_minus) \
1261: offset = -offset; \
1262: fprintf (STREAM, "[%s, #%d]", base_reg_name, offset); \
1263: break; \
1264: \
1265: case REG: \
1266: fprintf (STREAM, "[%s, %s%s]", base_reg_name, \
1267: is_minus ? "-" : "", reg_names[REGNO (index)] ); \
1268: break; \
1269: \
1270: case MULT: \
1271: if (GET_CODE (XEXP (index,0)) == CONST_INT) \
1272: { \
1273: shift = int_log2 (INTVAL (XEXP (index, 0))); \
1274: index = XEXP (index, 1); \
1275: } \
1276: else if (GET_CODE(XEXP(index,1)) == CONST_INT) \
1277: { \
1278: shift = int_log2 (INTVAL (XEXP (index, 1))); \
1279: index = XEXP (index, 0); \
1280: } \
1281: else \
1282: abort(); \
1283: fprintf (STREAM, "[%s, %s%s, asl#%d]", base_reg_name, \
1284: is_minus ? "-" : "", reg_names[REGNO (index)], \
1285: shift); \
1286: break; \
1287: \
1288: default: \
1289: abort(); \
1290: } \
1291: } \
1292: else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
1293: || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
1294: { \
1295: extern int output_memory_reference_mode; \
1296: \
1297: if (GET_CODE (XEXP (X, 0)) != REG) \
1298: abort (); \
1299: \
1300: if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
1301: fprintf (STREAM, "[%s, #%s%d]!", reg_names[REGNO (XEXP (X, 0))],\
1302: GET_CODE (X) == PRE_DEC ? "-" : "", \
1303: GET_MODE_SIZE (output_memory_reference_mode)); \
1304: else \
1305: fprintf (STREAM, "[%s], #%s%d", reg_names[REGNO (XEXP (X, 0))], \
1306: GET_CODE (X) == POST_DEC ? "-" : "", \
1307: GET_MODE_SIZE (output_memory_reference_mode)); \
1308: } \
1309: else output_addr_const(STREAM, X); \
1310: }
1311:
1312: /* EOF arm.h */
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