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1.1 root 1: /* Definitions of target machine for GNU compiler, for Acorn RISC Machine. 1.1.1.3 ! root 2: Copyright (C) 1991, 1993, 1994 Free Software Foundation, Inc. 1.1 root 3: Contributed by Pieter `Tiggr' Schoenmakers ([email protected]) 4: and Martin Simmons (@harleqn.co.uk). 1.1.1.2 root 5: More major hacks by Richard Earnshaw ([email protected]) 6: 1.1 root 7: This file is part of GNU CC. 8: 9: GNU CC is free software; you can redistribute it and/or modify 10: it under the terms of the GNU General Public License as published by 11: the Free Software Foundation; either version 2, or (at your option) 12: any later version. 13: 14: GNU CC is distributed in the hope that it will be useful, 15: but WITHOUT ANY WARRANTY; without even the implied warranty of 16: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17: GNU General Public License for more details. 18: 19: You should have received a copy of the GNU General Public License 20: along with GNU CC; see the file COPYING. If not, write to 21: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ 22: 23: /* Sometimes the directive `riscos' is checked. This does not imply that this 24: tm file can be used unchanged to build a GCC for RISC OS. 25: (Since in fact, it can't.) */ 26: 1.1.1.3 ! root 27: extern void output_func_prologue (); ! 28: extern void output_func_epilogue (); 1.1 root 29: extern char *output_add_immediate (); 30: extern char *output_call (); 1.1.1.2 root 31: extern char *output_call_mem (); 1.1 root 32: extern char *output_move_double (); 33: extern char *output_mov_double_fpu_from_arm (); 34: extern char *output_mov_double_arm_from_fpu (); 1.1.1.2 root 35: extern char *output_mov_long_double_fpu_from_arm (); 36: extern char *output_mov_long_double_arm_from_fpu (); 37: extern char *output_mov_long_double_arm_from_arm (); 1.1 root 38: extern char *output_mov_immediate (); 39: extern char *output_multi_immediate (); 1.1.1.2 root 40: extern char *output_return_instruction (); 41: extern char *output_load_symbol (); 42: extern char *fp_immediate_constant (); 43: extern struct rtx_def *gen_compare_reg (); 44: extern struct rtx_def *arm_gen_store_multiple (); 45: extern struct rtx_def *arm_gen_load_multiple (); 46: 47: extern char *arm_condition_codes[]; 48: 49: /* This is needed by the tail-calling peepholes */ 50: extern int frame_pointer_needed; 51: 1.1 root 52: 1.1.1.2 root 53: #ifndef CPP_PREDEFINES 54: #define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)" 55: #endif 1.1 root 56: 1.1.1.2 root 57: #ifndef CPP_SPEC 58: #define CPP_SPEC "%{m6:-D__arm6__}" 1.1 root 59: #endif 60: 61: /* Run-time Target Specification. */ 1.1.1.2 root 62: #ifndef TARGET_VERSION 1.1 root 63: #define TARGET_VERSION \ 1.1.1.2 root 64: fputs (" (ARM/generic)", stderr); 65: #endif 1.1 root 66: 67: /* Run-time compilation parameters selecting different hardware subsets. 68: On the ARM, misuse it in a different way. */ 69: extern int target_flags; 70: 71: /* Nonzero if the function prologue (and epilogue) should obey 72: the ARM Procedure Call Standard. */ 73: #define TARGET_APCS (target_flags & 1) 74: 75: /* Nonzero if the function prologue should output the function name to enable 76: the post mortem debugger to print a backtrace (very useful on RISCOS, 77: unused on RISCiX). Specifying this flag also enables -mapcs. 78: XXX Must still be implemented in the prologue. */ 79: #define TARGET_POKE_FUNCTION_NAME (target_flags & 2) 80: 81: /* Nonzero if floating point instructions are emulated by the FPE, in which 82: case instruction scheduling becomes very uninteresting. */ 83: #define TARGET_FPE (target_flags & 4) 84: 1.1.1.2 root 85: /* Nonzero if destined for an ARM6xx. Takes out bits that assume restoration 86: of condition flags when returning from a branch & link (ie. a function) */ 87: #define TARGET_6 (target_flags & 8) 88: 1.1.1.3 ! root 89: /* Leave some bits for new processor variants */ ! 90: ! 91: /* Nonzero if shorts must be loaded byte at a time. This is not necessary ! 92: for the arm processor chip, but it is needed for some MMU chips. */ ! 93: #define TARGET_SHORT_BY_BYTES (target_flags & 0x200) ! 94: 1.1.1.2 root 95: /* ARM_EXTRA_TARGET_SWITCHES is used in riscix.h to define some options which 96: are passed to the preprocessor and the assembler post-processor. They 97: aren't needed in the main pass of the compiler, but if we don't define 98: them in target switches cc1 complains about them. For the sake of 99: argument lets allocate bit 31 of target flags for such options. */ 100: 101: #ifndef ARM_EXTRA_TARGET_SWITCHES 102: #define ARM_EXTRA_TARGET_SWITCHES 103: #endif 104: 1.1.1.3 ! root 105: #define TARGET_SWITCHES \ ! 106: { \ ! 107: {"apcs", 1}, \ ! 108: {"poke-function-name", 2}, \ ! 109: {"fpe", 4}, \ ! 110: {"6", 8}, \ ! 111: {"2", -8}, \ ! 112: {"3", -8}, \ ! 113: {"short-load-bytes", (0x200)}, \ ! 114: {"no-short-load-bytes", -(0x200)}, \ ! 115: {"short-load-words", -(0x200)}, \ ! 116: {"no-short-load-words", (0x200)}, \ ! 117: ARM_EXTRA_TARGET_SWITCHES \ ! 118: {"", TARGET_DEFAULT } \ 1.1 root 119: } 120: 1.1.1.2 root 121: /* Which processor we are running on. Currently this is only used to 122: get the condition code clobbering attribute right when we are running on 123: an arm 6 */ 124: 125: enum processor_type 126: { 127: PROCESSOR_ARM2, 128: PROCESSOR_ARM3, 129: PROCESSOR_ARM6 130: }; 131: 132: /* Recast the cpu class to be the cpu attribute. */ 133: 134: /* Recast the cpu class to be the cpu attribute. */ 135: #define arm_cpu_attr ((enum attr_cpu)arm_cpu) 136: 137: extern enum processor_type arm_cpu; 138: 1.1.1.3 ! root 139: /* What sort of floating point unit do we have? Hardware or software. */ ! 140: enum floating_point_type ! 141: { ! 142: FP_HARD, ! 143: FP_SOFT ! 144: }; ! 145: ! 146: /* Recast the floating point class to be the floating point attribute. */ ! 147: #define arm_fpu_attr ((enum attr_fpu) arm_fpu) ! 148: ! 149: extern enum floating_point_type arm_fpu; ! 150: ! 151: #ifndef TARGET_DEFAULT 1.1 root 152: #define TARGET_DEFAULT 0 1.1.1.3 ! root 153: #endif 1.1 root 154: 155: #define TARGET_MEM_FUNCTIONS 1 156: 157: /* OVERRIDE_OPTIONS takes care of the following: 158: - if -mpoke-function-name, then -mapcs. 159: - if doing debugging, then -mapcs; if RISCOS, then -mpoke-function-name. 160: - if floating point is done by emulation, forget about instruction 161: scheduling. Note that this only saves compilation time; it doesn't 162: matter for the final code. */ 163: 164: #define OVERRIDE_OPTIONS \ 165: { \ 1.1.1.2 root 166: if (write_symbols != NO_DEBUG && flag_omit_frame_pointer) \ 167: warning ("-g without a frame pointer may not give sensible debugging");\ 168: if (TARGET_POKE_FUNCTION_NAME) \ 1.1 root 169: target_flags |= 1; \ 170: if (TARGET_FPE) \ 171: flag_schedule_insns = flag_schedule_insns_after_reload = 0; \ 1.1.1.2 root 172: arm_cpu = TARGET_6 ? PROCESSOR_ARM6: PROCESSOR_ARM2; \ 1.1 root 173: } 174: 175: /* Target machine storage Layout. */ 176: 1.1.1.2 root 177: 178: /* Define this macro if it is advisable to hold scalars in registers 179: in a wider mode than that declared by the program. In such cases, 180: the value is constrained to be within the bounds of the declared 181: type, but kept valid in the wider mode. The signedness of the 182: extension may differ from that of the type. */ 183: 184: /* It is far faster to zero extend chars than to sign extend them */ 185: 186: #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 1.1.1.3 ! root 187: if (GET_MODE_CLASS (MODE) == MODE_INT \ ! 188: && GET_MODE_SIZE (MODE) < 4) \ ! 189: { \ ! 190: if (MODE == QImode) \ ! 191: UNSIGNEDP = 1; \ ! 192: else if (MODE == HImode) \ ! 193: UNSIGNEDP = TARGET_SHORT_BY_BYTES != 0; \ ! 194: (MODE) = SImode; \ 1.1.1.2 root 195: } 196: 197: /* Define for XFmode extended real floating point support. 198: This will automatically cause REAL_ARITHMETIC to be defined. */ 199: /* For the ARM: 200: I think I have added all the code to make this work. Unfortunately, 201: early releases of the floating point emulation code on RISCiX used a 202: different format for extended precision numbers. On my RISCiX box there 203: is a bug somewhere which causes the machine to lock up when running enquire 204: with long doubles. There is the additional aspect that Norcroft C 205: treats long doubles as doubles and we ought to remain compatible. 206: Perhaps someone with an FPA coprocessor and not running RISCiX would like 207: to try this someday. */ 208: /* #define LONG_DOUBLE_TYPE_SIZE 96 */ 209: 210: /* Disable XFmode patterns in md file */ 211: #define ENABLE_XF_PATTERNS 0 212: 213: /* Define if you don't want extended real, but do want to use the 214: software floating point emulator for REAL_ARITHMETIC and 215: decimal <-> binary conversion. */ 216: /* See comment above */ 217: #define REAL_ARITHMETIC 218: 1.1 root 219: /* Define this if most significant bit is lowest numbered 220: in instructions that operate on numbered bit-fields. */ 221: #define BITS_BIG_ENDIAN 0 222: 1.1.1.3 ! root 223: /* Define this if most significant byte of a word is the lowest numbered. ! 224: Most ARM processors are run in little endian mode, but it should now be ! 225: possible to build the compiler to support big endian code. (Note: This ! 226: is currently a compiler-build-time option, not a run-time one. */ ! 227: #ifndef BYTES_BIG_ENDIAN 1.1 root 228: #define BYTES_BIG_ENDIAN 0 1.1.1.3 ! root 229: #endif 1.1 root 230: 231: /* Define this if most significant word of a multiword number is the lowest 232: numbered. */ 233: #define WORDS_BIG_ENDIAN 0 234: 1.1.1.2 root 235: /* Define this if most significant word of doubles is the lowest numbered */ 236: #define FLOAT_WORDS_BIG_ENDIAN 1 237: 1.1 root 238: /* Number of bits in an addressable storage unit */ 239: #define BITS_PER_UNIT 8 240: 241: #define BITS_PER_WORD 32 242: 243: #define UNITS_PER_WORD 4 244: 245: #define POINTER_SIZE 32 246: 247: #define PARM_BOUNDARY 32 248: 249: #define STACK_BOUNDARY 32 250: 251: #define FUNCTION_BOUNDARY 32 252: 253: #define EMPTY_FIELD_BOUNDARY 32 254: 255: #define BIGGEST_ALIGNMENT 32 256: 1.1.1.2 root 257: /* Make strings word-aligned so strcpy from constants will be faster. */ 258: #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 259: (TREE_CODE (EXP) == STRING_CST \ 260: && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 261: 1.1 root 262: /* Every structures size must be a multiple of 32 bits. */ 263: #define STRUCTURE_SIZE_BOUNDARY 32 264: 1.1.1.2 root 265: /* Non-zero if move instructions will actually fail to work 266: when given unaligned data. */ 1.1 root 267: #define STRICT_ALIGNMENT 1 268: 1.1.1.2 root 269: #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT 270: 1.1 root 271: /* Define number of bits in most basic integer type. 272: (If undefined, default is BITS_PER_WORD). */ 273: /* #define INT_TYPE_SIZE */ 274: 275: /* Standard register usage. */ 276: 277: /* Register allocation in ARM Procedure Call Standard (as used on RISCiX): 278: (S - saved over call). 279: 280: r0 * argument word/integer result 281: r1-r3 argument word 282: 283: r4-r8 S register variable 284: r9 S (rfp) register variable (real frame pointer) 285: 286: r10 F S (sl) stack limit (not currently used) 287: r11 F S (fp) argument pointer 288: r12 (ip) temp workspace 289: r13 F S (sp) lower end of current stack frame 290: r14 (lr) link address/workspace 291: r15 F (pc) program counter 292: 293: f0 floating point result 294: f1-f3 floating point scratch 295: 296: f4-f7 S floating point variable 297: 1.1.1.2 root 298: cc This is NOT a real register, but is used internally 299: to represent things that use or set the condition 300: codes. 301: sfp This isn't either. It is used during rtl generation 302: since the offset between the frame pointer and the 303: auto's isn't known until after register allocation. 304: afp Nor this, we only need this because of non-local 305: goto. Without it fp appears to be used and the 306: elimination code won't get rid of sfp. It tracks 307: fp exactly at all times. 308: 1.1 root 309: *: See CONDITIONAL_REGISTER_USAGE */ 310: 1.1.1.2 root 311: /* The stack backtrace structure is as follows: 312: fp points to here: | save code pointer | [fp] 313: | return link value | [fp, #-4] 314: | return sp value | [fp, #-8] 315: | return fp value | [fp, #-12] 316: [| saved r10 value |] 317: [| saved r9 value |] 318: [| saved r8 value |] 319: [| saved r7 value |] 320: [| saved r6 value |] 321: [| saved r5 value |] 322: [| saved r4 value |] 323: [| saved r3 value |] 324: [| saved r2 value |] 325: [| saved r1 value |] 326: [| saved r0 value |] 327: [| saved f7 value |] three words 328: [| saved f6 value |] three words 329: [| saved f5 value |] three words 330: [| saved f4 value |] three words 331: r0-r3 are not normally saved in a C function. */ 332: 333: /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */ 334: #define FIRST_PSEUDO_REGISTER 27 1.1 root 335: 336: /* 1 for registers that have pervasive standard uses 337: and are not available for the register allocator. */ 338: #define FIXED_REGISTERS \ 339: { \ 340: 0,0,0,0,0,0,0,0, \ 341: 0,0,1,1,0,1,0,1, \ 1.1.1.2 root 342: 0,0,0,0,0,0,0,0, \ 343: 1,1,1 \ 1.1 root 344: } 345: 346: /* 1 for registers not available across function calls. 347: These must include the FIXED_REGISTERS and also any 348: registers that can be used without being saved. 349: The latter must include the registers where values are returned 350: and the register where structure-value addresses are passed. 1.1.1.2 root 351: Aside from that, you can include as many other registers as you like. 352: The CC is not preserved over function calls on the ARM 6, so it is 353: easier to assume this for all. SFP is preserved, since FP is. */ 1.1 root 354: #define CALL_USED_REGISTERS \ 355: { \ 356: 1,1,1,1,0,0,0,0, \ 357: 0,0,1,1,1,1,1,1, \ 1.1.1.2 root 358: 1,1,1,1,0,0,0,0, \ 359: 1,1,1 \ 1.1 root 360: } 361: 362: /* If doing stupid life analysis, avoid a bug causing a return value r0 to be 363: trampled. This effectively reduces the number of available registers by 1. 364: XXX It is a hack, I know. 365: XXX Is this still needed? */ 366: #define CONDITIONAL_REGISTER_USAGE \ 367: { \ 368: if (obey_regdecls) \ 369: fixed_regs[0] = 1; \ 370: } 371: 372: /* Return number of consecutive hard regs needed starting at reg REGNO 373: to hold something of mode MODE. 374: This is ordinarily the length in words of a value of mode MODE 375: but can be less for certain modes in special long registers. 376: 377: On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP 378: mode. */ 1.1.1.2 root 379: #define HARD_REGNO_NREGS(REGNO, MODE) \ 380: (((REGNO) >= 16 && REGNO != FRAME_POINTER_REGNUM \ 381: && (REGNO) != ARG_POINTER_REGNUM) ? 1 \ 1.1 root 382: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 383: 384: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 385: This is TRUE for ARM regs since they can hold anything, and TRUE for FPU 386: regs holding FP. */ 1.1.1.2 root 387: #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 388: ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \ 389: ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \ 390: || REGNO == ARG_POINTER_REGNUM \ 391: || GET_MODE_CLASS (MODE) == MODE_FLOAT)) 1.1 root 392: 393: /* Value is 1 if it is a good idea to tie two pseudo registers 394: when one has mode MODE1 and one has mode MODE2. 395: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 396: for any hard reg, then this must be 0 for correct output. */ 397: #define MODES_TIEABLE_P(MODE1, MODE2) \ 1.1.1.3 ! root 398: (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) 1.1 root 399: 400: /* Specify the registers used for certain standard purposes. 401: The values of these macros are register numbers. */ 402: 403: /* Define this if the program counter is overloaded on a register. */ 404: #define PC_REGNUM 15 405: 406: /* Register to use for pushing function arguments. */ 407: #define STACK_POINTER_REGNUM 13 408: 409: /* Base register for access to local variables of the function. */ 1.1.1.2 root 410: #define FRAME_POINTER_REGNUM 25 411: 412: /* Define this to be where the real frame pointer is if it is not possible to 413: work out the offset between the frame pointer and the automatic variables 414: until after register allocation has taken place. FRAME_POINTER_REGNUM 415: should point to a special register that we will make sure is eliminated. */ 416: #define HARD_FRAME_POINTER_REGNUM 11 1.1 root 417: 418: /* Value should be nonzero if functions must have frame pointers. 419: Zero means the frame pointer need not be set up (and parms may be accessed 1.1.1.2 root 420: via the stack pointer) in functions that seem suitable. 421: If we have to have a frame pointer we might as well make use of it. 422: APCS says that the frame pointer does not need to be pushed in leaf 423: functions. */ 1.1.1.3 ! root 424: #define FRAME_POINTER_REQUIRED \ ! 425: (current_function_has_nonlocal_label || (TARGET_APCS && !leaf_function_p ())) 1.1 root 426: 427: /* Base register for access to arguments of the function. */ 1.1.1.2 root 428: #define ARG_POINTER_REGNUM 26 1.1 root 429: 430: /* The native (Norcroft) Pascal compiler for the ARM passes the static chain 431: as an invisible last argument (possible since varargs don't exist in 432: Pascal), so the following is not true. */ 433: #define STATIC_CHAIN_REGNUM 8 434: 435: /* Register in which address to store a structure value 436: is passed to a function. */ 437: #define STRUCT_VALUE_REGNUM 0 438: 1.1.1.2 root 439: /* Internal, so that we don't need to refer to a raw number */ 440: #define CC_REGNUM 24 441: 1.1 root 442: /* The order in which register should be allocated. It is good to use ip 1.1.1.2 root 443: since no saving is required (though calls clobber it) and it never contains 444: function parameters. It is quite good to use lr since other calls may 445: clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 446: least likely to contain a function parameter; in addition results are 447: returned in r0. 448: */ 1.1 root 449: #define REG_ALLOC_ORDER \ 450: { \ 1.1.1.2 root 451: 3, 2, 1, 0, 12, 14, 4, 5, \ 1.1 root 452: 6, 7, 8, 10, 9, 11, 13, 15, \ 1.1.1.2 root 453: 16, 17, 18, 19, 20, 21, 22, 23, \ 454: 24, 25 \ 1.1 root 455: } 456: 457: /* Register and constant classes. */ 458: 459: /* Register classes: all ARM regs or all FPU regs---simple! */ 460: enum reg_class 461: { 462: NO_REGS, 463: FPU_REGS, 464: GENERAL_REGS, 465: ALL_REGS, 466: LIM_REG_CLASSES 467: }; 468: 469: #define N_REG_CLASSES (int) LIM_REG_CLASSES 470: 471: /* Give names of register classes as strings for dump file. */ 472: #define REG_CLASS_NAMES \ 473: { \ 474: "NO_REGS", \ 475: "FPU_REGS", \ 476: "GENERAL_REGS", \ 477: "ALL_REGS", \ 478: } 479: 480: /* Define which registers fit in which classes. 481: This is an initializer for a vector of HARD_REG_SET 482: of length N_REG_CLASSES. */ 483: #define REG_CLASS_CONTENTS \ 484: { \ 1.1.1.2 root 485: 0x0000000, /* NO_REGS */ \ 486: 0x0FF0000, /* FPU_REGS */ \ 487: 0x200FFFF, /* GENERAL_REGS */ \ 488: 0x2FFFFFF /* ALL_REGS */ \ 1.1 root 489: } 490: 491: /* The same information, inverted: 492: Return the class number of the smallest class containing 493: reg number REGNO. This could be a conditional expression 494: or could index an array. */ 1.1.1.2 root 495: #define REGNO_REG_CLASS(REGNO) \ 496: (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \ 497: || REGNO == ARG_POINTER_REGNUM) \ 498: ? GENERAL_REGS : (REGNO) == CC_REGNUM \ 499: ? NO_REGS : FPU_REGS) 1.1 root 500: 501: /* The class value for index registers, and the one for base regs. */ 502: #define INDEX_REG_CLASS GENERAL_REGS 503: #define BASE_REG_CLASS GENERAL_REGS 504: 505: /* Get reg_class from a letter such as appears in the machine description. 506: We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */ 507: #define REG_CLASS_FROM_LETTER(C) \ 508: ((C)=='f' ? FPU_REGS : NO_REGS) 509: 510: /* The letters I, J, K, L and M in a register constraint string 511: can be used to stand for particular ranges of immediate operands. 512: This macro defines what the ranges are. 513: C is the letter, and VALUE is a constant value. 514: Return 1 if VALUE is in the range specified by C. 515: I: immediate arithmetic operand (i.e. 8 bits shifted as required). 1.1.1.2 root 516: J: valid indexing constants. 1.1.1.3 ! root 517: K: ~value ok in rhs argument of data operand. ! 518: L: -value ok in rhs argument of data operand. ! 519: M: 0..32, or a power of 2 (for shifts, or mult done by shift). */ ! 520: #define CONST_OK_FOR_LETTER_P(VALUE, C) \ ! 521: ((C) == 'I' ? const_ok_for_arm (VALUE) : \ ! 522: (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \ ! 523: (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \ ! 524: (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \ ! 525: (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \ ! 526: || (((VALUE) & ((VALUE) - 1)) == 0)) \ ! 527: : 0) 1.1.1.2 root 528: 529: /* For the ARM, `Q' means that this is a memory operand that is just 530: an offset from a register. 531: `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL 532: address. This means that the symbol is in the text segment and can be 533: accessed without using a load. */ 534: 535: #define EXTRA_CONSTRAINT(OP, C) \ 536: ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \ 1.1.1.3 ! root 537: : (C) == 'R' ? (GET_CODE (OP) == MEM \ ! 538: && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ ! 539: && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \ ! 540: : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : 0) 1.1.1.2 root 541: 542: /* Constant letter 'G' for the FPU immediate constants. 543: 'H' means the same constant negated. */ 544: #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \ 545: ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \ 546: : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0) 1.1 root 547: 548: /* Given an rtx X being reloaded into a reg required to be 549: in class CLASS, return the class of reg to actually use. 550: In general this is just CLASS; but on some machines 551: in some cases it is preferable to use a more restrictive class. */ 552: #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS) 553: 1.1.1.2 root 554: /* Return the register class of a scratch register needed to copy IN into 555: or out of a register in CLASS in MODE. If it can be done directly, 556: NO_REGS is returned. */ 557: #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \ 558: (((MODE) == DFmode && (CLASS) == GENERAL_REGS \ 559: && true_regnum (X) == -1) ? GENERAL_REGS \ 560: : ((MODE) == HImode && true_regnum (X) == -1) ? GENERAL_REGS : NO_REGS) 561: 1.1.1.3 ! root 562: /* If we need to load shorts byte-at-a-time, then we need a scratch. */ ! 563: #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \ ! 564: (((MODE) == HImode && TARGET_SHORT_BY_BYTES && true_regnum (X) == -1) \ ! 565: ? GENERAL_REGS : NO_REGS) ! 566: 1.1 root 567: /* Return the maximum number of consecutive registers 568: needed to represent mode MODE in a register of class CLASS. 569: ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */ 570: #define CLASS_MAX_NREGS(CLASS, MODE) \ 571: ((CLASS) == FPU_REGS ? 1 \ 572: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 573: 1.1.1.2 root 574: /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */ 1.1 root 575: #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ 576: ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \ 577: || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \ 1.1.1.2 root 578: ? 20 : 2) 1.1 root 579: 580: /* Stack layout; function entry, exit and calling. */ 581: 582: /* Define this if pushing a word on the stack 583: makes the stack pointer a smaller address. */ 584: #define STACK_GROWS_DOWNWARD 1 585: 586: /* Define this if the nominal address of the stack frame 587: is at the high-address end of the local variables; 588: that is, each additional local variable allocated 589: goes at a more negative offset in the frame. */ 590: #define FRAME_GROWS_DOWNWARD 1 591: 592: /* Offset within stack frame to start allocating local variables at. 593: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 594: first local allocated. Otherwise, it is the offset to the BEGINNING 595: of the first local allocated. */ 596: #define STARTING_FRAME_OFFSET 0 597: 598: /* If we generate an insn to push BYTES bytes, 599: this says how many the stack pointer really advances by. */ 600: #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) 601: 602: /* Offset of first parameter from the argument pointer register value. */ 603: #define FIRST_PARM_OFFSET(FNDECL) 4 604: 605: /* Value is the number of byte of arguments automatically 606: popped when returning from a subroutine call. 607: FUNTYPE is the data type of the function (as a tree), 608: or for a library call it is an identifier node for the subroutine name. 609: SIZE is the number of bytes of arguments passed on the stack. 610: 611: On the ARM, the caller does not pop any of its arguments that were passed 612: on the stack. */ 613: #define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0 614: 615: /* Define how to find the value returned by a function. 616: VALTYPE is the data type of the value (as a tree). 617: If the precise function being called is known, FUNC is its FUNCTION_DECL; 618: otherwise, FUNC is 0. */ 619: #define FUNCTION_VALUE(VALTYPE, FUNC) \ 620: (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT \ 621: ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \ 622: : gen_rtx (REG, TYPE_MODE (VALTYPE), 0)) 623: 624: /* Define how to find the value returned by a library function 625: assuming the value has mode MODE. */ 626: #define LIBCALL_VALUE(MODE) \ 627: (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 628: ? gen_rtx (REG, MODE, 16) \ 629: : gen_rtx (REG, MODE, 0)) 630: 631: /* 1 if N is a possible register number for a function value. 632: On the ARM, only r0 and f0 can return results. */ 633: #define FUNCTION_VALUE_REGNO_P(REGNO) \ 634: ((REGNO) == 0 || (REGNO) == 16) 635: 636: /* Define where to put the arguments to a function. 637: Value is zero to push the argument on the stack, 638: or a hard register in which to store the argument. 639: 640: MODE is the argument's machine mode. 641: TYPE is the data type of the argument (as a tree). 642: This is null for libcalls where that information may 643: not be available. 644: CUM is a variable of type CUMULATIVE_ARGS which gives info about 645: the preceding args and about the function being called. 646: NAMED is nonzero if this argument is a named parameter 647: (otherwise it is an extra parameter matching an ellipsis). 648: 649: On the ARM, normally the first 16 bytes are passed in registers r0-r3; all 650: other arguments are passed on the stack. If (NAMED == 0) (which happens 651: only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is 652: passed in the stack (function_prologue will indeed make it pass in the 653: stack if necessary). */ 654: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 655: ((NAMED) \ 656: ? ((CUM) >= 16 ? 0 : gen_rtx (REG, MODE, (CUM) / 4)) \ 657: : 0) 658: 659: /* For an arg passed partly in registers and partly in memory, 660: this is the number of registers used. 661: For args passed entirely in registers or entirely in memory, zero. */ 662: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 663: ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \ 664: ? GET_MODE_SIZE (MODE) \ 665: : int_size_in_bytes (TYPE)) \ 666: ? 4 - (CUM) / 4 : 0) 667: 668: /* A C type for declaring a variable that is used as the first argument of 669: `FUNCTION_ARG' and other related values. For some target machines, the 670: type `int' suffices and can hold the number of bytes of argument so far. 671: 672: On the ARM, this is the number of bytes of arguments scanned so far. */ 673: #define CUMULATIVE_ARGS int 674: 675: /* Initialize a variable CUM of type CUMULATIVE_ARGS 676: for a call to a function whose data type is FNTYPE. 677: For a library call, FNTYPE is 0. 678: On the ARM, the offset starts at 0. */ 679: #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \ 1.1.1.2 root 680: ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 4 : 0)) 1.1 root 681: 682: /* Update the data in CUM to advance over an argument 683: of mode MODE and data type TYPE. 684: (TYPE is null for libcalls where that information may not be available.) */ 685: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 686: (CUM) += ((MODE) != BLKmode \ 687: ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ 688: : (int_size_in_bytes (TYPE) + 3) & ~3) \ 689: 690: /* 1 if N is a possible register number for function argument passing. 691: On the ARM, r0-r3 are used to pass args. */ 692: #define FUNCTION_ARG_REGNO_P(REGNO) \ 693: ((REGNO) >= 0 && (REGNO) <= 3) 694: 695: /* Perform any actions needed for a function that is receiving a variable 696: number of arguments. CUM is as above. MODE and TYPE are the mode and type 697: of the current parameter. PRETEND_SIZE is a variable that should be set to 698: the amount of stack that must be pushed by the prolog to pretend that our 699: caller pushed it. 700: 701: Normally, this macro will push all remaining incoming registers on the 702: stack and set PRETEND_SIZE to the length of the registers pushed. 703: 704: On the ARM, PRETEND_SIZE is set in order to have the prologue push the last 705: named arg and all anonymous args onto the stack. 706: XXX I know the prologue shouldn't be pushing registers, but it is faster 707: that way. */ 708: #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ 709: { \ 710: extern int current_function_anonymous_args; \ 711: current_function_anonymous_args = 1; \ 712: if ((CUM) < 16) \ 713: (PRETEND_SIZE) = 16 - (CUM); \ 714: } 715: 716: /* Generate assembly output for the start of a function. */ 717: #define FUNCTION_PROLOGUE(STREAM, SIZE) \ 1.1.1.3 ! root 718: output_func_prologue ((STREAM), (SIZE)) 1.1 root 719: 720: /* Call the function profiler with a given profile label. The Acorn compiler 721: puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr'' 722: seems like a good idea to stick with cc convention. ``prof'' doesn't seem 723: to mind about this! */ 1.1.1.3 ! root 724: #define FUNCTION_PROFILER(STREAM,LABELNO) \ ! 725: { \ ! 726: fprintf(STREAM, "\tmov\t%sip, %slr\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \ ! 727: fprintf(STREAM, "\tbl\tmcount\n"); \ ! 728: fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \ 1.1 root 729: } 730: 731: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 732: the stack pointer does not matter. The value is tested only in 733: functions that have frame pointers. 734: No definition is equivalent to always zero. 735: 736: On the ARM, the function epilogue recovers the stack pointer from the 737: frame. */ 738: #define EXIT_IGNORE_STACK 1 739: 740: /* Generate the assembly code for function exit. */ 741: #define FUNCTION_EPILOGUE(STREAM, SIZE) \ 1.1.1.3 ! root 742: output_func_epilogue ((STREAM), (SIZE)) 1.1 root 743: 744: /* Determine if the epilogue should be output as RTL. 745: You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1.1.1.2 root 746: #define USE_RETURN_INSN use_return_insn () 747: 748: /* Definitions for register eliminations. 749: 750: This is an array of structures. Each structure initializes one pair 751: of eliminable registers. The "from" register number is given first, 752: followed by "to". Eliminations of the same "from" register are listed 753: in order of preference. 754: 755: We have two registers that can be eliminated on the ARM. First, the 756: arg pointer register can often be eliminated in favor of the stack 757: pointer register. Secondly, the pseudo frame pointer register can always 758: be eliminated; it is replaced with either the stack or the real frame 759: pointer. */ 760: 761: #define ELIMINABLE_REGS \ 762: {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 763: {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 764: {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 765: {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} 766: 767: /* Given FROM and TO register numbers, say whether this elimination is allowed. 768: Frame pointer elimination is automatically handled. 769: 770: All eliminations are permissible. Note that ARG_POINTER_REGNUM and 771: HARD_FRAME_POINTER_REGNUM are infact the same thing. If we need a frame 772: pointer, we must eliminate FRAME_POINTER_REGNUM into 773: HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */ 774: #define CAN_ELIMINATE(FROM, TO) \ 775: (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1) 776: 777: /* Define the offset between two registers, one to be eliminated, and the other 778: its replacement, at the start of a routine. */ 779: #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 780: { \ 1.1.1.3 ! root 781: int volatile_func = arm_volatile_func (); \ 1.1.1.2 root 782: if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\ 783: (OFFSET) = 0; \ 784: else if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)\ 785: (OFFSET) = (get_frame_size () + 3 & ~3); \ 786: else \ 787: { \ 788: int regno; \ 789: int offset = 12; \ 1.1.1.3 ! root 790: int saved_hard_reg = 0; \ 1.1.1.2 root 791: \ 1.1.1.3 ! root 792: if (! volatile_func) \ ! 793: { \ ! 794: for (regno = 0; regno <= 10; regno++) \ ! 795: if (regs_ever_live[regno] && ! call_used_regs[regno]) \ ! 796: saved_hard_reg = 1, offset += 4; \ ! 797: for (regno = 16; regno <=23; regno++) \ ! 798: if (regs_ever_live[regno] && ! call_used_regs[regno]) \ ! 799: offset += 12; \ ! 800: } \ 1.1.1.2 root 801: if ((FROM) == FRAME_POINTER_REGNUM) \ 802: (OFFSET) = -offset; \ 803: else \ 804: { \ 1.1.1.3 ! root 805: if (! frame_pointer_needed) \ 1.1.1.2 root 806: offset -= 16; \ 1.1.1.3 ! root 807: if (! volatile_func && (regs_ever_live[14] || saved_hard_reg)) \ 1.1.1.2 root 808: offset += 4; \ 809: (OFFSET) = (get_frame_size () + 3 & ~3) + offset; \ 810: } \ 811: } \ 812: } 1.1 root 813: 814: /* Output assembler code for a block containing the constant parts 815: of a trampoline, leaving space for the variable parts. 816: 817: On the ARM, (if r8 is the static chain regnum, and remembering that 818: referencing pc adds an offset of 8) the trampoline looks like: 819: ldr r8, [pc, #0] 820: ldr pc, [pc] 821: .word static chain value 822: .word function's address */ 1.1.1.3 ! root 823: #define TRAMPOLINE_TEMPLATE(FILE) \ ! 824: { \ ! 825: fprintf ((FILE), "\tldr\t%sr8, [%spc, #0]\n", ARM_REG_PREFIX, \ ! 826: ARM_REG_PREFIX); \ ! 827: fprintf ((FILE), "\tldr\t%spc, [%spc, #0]\n", ARM_REG_PREFIX, \ ! 828: ARM_REG_PREFIX); \ ! 829: fprintf ((FILE), "\t.word\t0\n"); \ ! 830: fprintf ((FILE), "\t.word\t0\n"); \ 1.1 root 831: } 832: 833: /* Length in units of the trampoline for entering a nested function. */ 834: #define TRAMPOLINE_SIZE 16 835: 836: /* Alignment required for a trampoline in units. */ 837: #define TRAMPOLINE_ALIGN 4 838: 839: /* Emit RTL insns to initialize the variable parts of a trampoline. 840: FNADDR is an RTX for the address of the function's pure code. 841: CXT is an RTX for the static chain value for the function. */ 842: #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 843: { \ 844: emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \ 845: (CXT)); \ 846: emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \ 847: (FNADDR)); \ 848: } 849: 850: 851: /* Addressing modes, and classification of registers for them. */ 852: 853: #define HAVE_POST_INCREMENT 1 854: #define HAVE_PRE_INCREMENT 1 855: #define HAVE_POST_DECREMENT 1 856: #define HAVE_PRE_DECREMENT 1 857: 858: /* Macros to check register numbers against specific register classes. */ 859: 860: /* These assume that REGNO is a hard or pseudo reg number. 861: They give nonzero only if REGNO is a hard reg of the suitable class 862: or a pseudo reg currently allocated to a suitable hard reg. 863: Since they use reg_renumber, they are safe only once reg_renumber 864: has been allocated, which happens in local-alloc.c. 865: 866: On the ARM, don't allow the pc to be used. */ 1.1.1.2 root 867: #define REGNO_OK_FOR_BASE_P(REGNO) \ 868: ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \ 869: || (REGNO) == ARG_POINTER_REGNUM \ 870: || (unsigned) reg_renumber[(REGNO)] < 15 \ 871: || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \ 872: || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM) 873: #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1.1 root 874: REGNO_OK_FOR_BASE_P(REGNO) 875: 876: /* Maximum number of registers that can appear in a valid memory address. 1.1.1.2 root 877: Shifts in addresses can't be by a register. */ 878: 879: #define MAX_REGS_PER_ADDRESS 2 1.1 root 880: 881: /* Recognize any constant value that is a valid address. */ 882: /* XXX We can address any constant, eventually... */ 883: #if 0 884: #define CONSTANT_ADDRESS_P(X) \ 885: ( GET_CODE(X) == LABEL_REF \ 886: || GET_CODE(X) == SYMBOL_REF \ 887: || GET_CODE(X) == CONST_INT \ 888: || GET_CODE(X) == CONST ) 889: #endif 890: 1.1.1.3 ! root 891: #define CONSTANT_ADDRESS_P(X) \ ! 892: (GET_CODE (X) == SYMBOL_REF \ ! 893: && (CONSTANT_POOL_ADDRESS_P (X) \ ! 894: || (optimize > 0 && SYMBOL_REF_FLAG (X)))) 1.1 root 895: 896: /* Nonzero if the constant value X is a legitimate general operand. 897: It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. 898: 899: On the ARM, allow any integer (invalid ones are removed later by insn 900: patterns), nice doubles and symbol_refs which refer to the function's 901: constant pool XXX. */ 902: #define LEGITIMATE_CONSTANT_P(X) \ 903: (GET_CODE (X) == CONST_INT \ 904: || (GET_CODE (X) == CONST_DOUBLE \ 1.1.1.2 root 905: && (const_double_rtx_ok_for_fpu (X) \ 906: || neg_const_double_rtx_ok_for_fpu (X))) \ 907: || CONSTANT_ADDRESS_P (X)) 908: 909: /* Symbols in the text segment can be accessed without indirecting via the 910: constant pool; it may take an extra binary operation, but this is still 1.1.1.3 ! root 911: faster than indirecting via memory. Don't do this when not optimizing, ! 912: since we won't be calculating al of the offsets necessary to do this ! 913: simplification. */ 1.1.1.2 root 914: 915: #define ENCODE_SECTION_INFO(decl) \ 916: { \ 1.1.1.3 ! root 917: if (optimize > 0 && TREE_CONSTANT (decl) \ 1.1.1.2 root 918: && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \ 919: { \ 920: rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \ 921: ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \ 922: SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \ 923: } \ 924: } 1.1 root 925: 926: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 927: and check its validity for a certain class. 928: We have two alternate definitions for each of them. 929: The usual definition accepts all pseudo regs; the other rejects 930: them unless they have been allocated suitable hard regs. 931: The symbol REG_OK_STRICT causes the latter definition to be used. */ 932: #ifndef REG_OK_STRICT 1.1.1.2 root 933: 1.1 root 934: /* Nonzero if X is a hard reg that can be used as a base reg 935: or if it is a pseudo reg. */ 1.1.1.2 root 936: #define REG_OK_FOR_BASE_P(X) \ 937: (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 938: || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM) 939: 1.1 root 940: /* Nonzero if X is a hard reg that can be used as an index 941: or if it is a pseudo reg. */ 942: #define REG_OK_FOR_INDEX_P(X) \ 943: REG_OK_FOR_BASE_P(X) 1.1.1.2 root 944: 945: #define REG_OK_FOR_PRE_POST_P(X) \ 946: (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 947: || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM) 948: 1.1 root 949: #else 1.1.1.2 root 950: 1.1 root 951: /* Nonzero if X is a hard reg that can be used as a base reg. */ 952: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1.1.1.2 root 953: 1.1 root 954: /* Nonzero if X is a hard reg that can be used as an index. */ 955: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1.1.1.2 root 956: 957: #define REG_OK_FOR_PRE_POST_P(X) \ 958: (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \ 959: || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \ 960: || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \ 961: || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM) 962: 1.1 root 963: #endif 964: 965: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 966: that is a valid memory address for an instruction. 967: The MODE argument is the machine mode for the MEM expression 968: that wants to use this address. 969: 970: The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ 971: #define BASE_REGISTER_RTX_P(X) \ 972: (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) 973: 974: #define INDEX_REGISTER_RTX_P(X) \ 975: (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) 976: 977: /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs 978: used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can 979: only be small constants. */ 1.1.1.2 root 980: #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \ 1.1 root 981: do \ 982: { \ 1.1.1.3 ! root 983: HOST_WIDE_INT range; \ ! 984: enum rtx_code code = GET_CODE (INDEX); \ 1.1 root 985: \ 986: if (GET_MODE_CLASS (MODE) == MODE_FLOAT) \ 1.1.1.2 root 987: { \ 988: if (code == CONST_INT && INTVAL (INDEX) < 1024 \ 989: && INTVAL (INDEX) > -1024 \ 990: && (INTVAL (INDEX) & 3) == 0) \ 991: goto LABEL; \ 992: } \ 1.1 root 993: else \ 994: { \ 1.1.1.2 root 995: if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \ 1.1 root 996: goto LABEL; \ 1.1.1.2 root 997: if (GET_MODE_SIZE (MODE) <= 4 && code == MULT) \ 1.1 root 998: { \ 999: rtx xiop0 = XEXP (INDEX, 0); \ 1000: rtx xiop1 = XEXP (INDEX, 1); \ 1001: if (INDEX_REGISTER_RTX_P (xiop0) \ 1002: && power_of_two_operand (xiop1, SImode)) \ 1003: goto LABEL; \ 1004: if (INDEX_REGISTER_RTX_P (xiop1) \ 1005: && power_of_two_operand (xiop0, SImode)) \ 1006: goto LABEL; \ 1007: } \ 1.1.1.2 root 1008: if (GET_MODE_SIZE (MODE) <= 4 \ 1.1.1.3 ! root 1009: && (code == LSHIFTRT || code == ASHIFTRT \ 1.1.1.2 root 1010: || code == ASHIFT || code == ROTATERT)) \ 1011: { \ 1012: rtx op = XEXP (INDEX, 1); \ 1013: if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \ 1014: && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \ 1015: && INTVAL (op) <= 31) \ 1016: goto LABEL; \ 1017: } \ 1018: range = (MODE) == HImode ? 4095 : 4096; \ 1019: if (code == CONST_INT && INTVAL (INDEX) < range \ 1020: && INTVAL (INDEX) > -range) \ 1021: goto LABEL; \ 1.1 root 1022: } \ 1023: } while (0) 1024: 1025: /* Jump to LABEL if X is a valid address RTX. This must also take 1026: REG_OK_STRICT into account when deciding about valid registers, but it uses 1027: the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX, 1028: INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool. 1.1.1.2 root 1029: Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol 1030: refs must be forced though a static cell to ensure addressability. */ 1.1 root 1031: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ 1032: { \ 1033: if (BASE_REGISTER_RTX_P (X)) \ 1034: goto LABEL; \ 1035: else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \ 1036: && GET_CODE (XEXP (X, 0)) == REG \ 1037: && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \ 1038: goto LABEL; \ 1039: else if ((MODE) == TImode) \ 1040: ; \ 1041: else if (GET_CODE (X) == PLUS) \ 1042: { \ 1043: rtx xop0 = XEXP(X,0); \ 1044: rtx xop1 = XEXP(X,1); \ 1045: \ 1046: if (BASE_REGISTER_RTX_P (xop0)) \ 1047: GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \ 1048: else if (BASE_REGISTER_RTX_P (xop1)) \ 1049: GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \ 1050: } \ 1051: else if (GET_CODE (X) == MINUS) \ 1052: { \ 1053: rtx xop0 = XEXP (X,0); \ 1054: rtx xop1 = XEXP (X,1); \ 1055: \ 1056: if (BASE_REGISTER_RTX_P (xop0)) \ 1057: GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \ 1058: } \ 1059: else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \ 1060: && GET_CODE (X) == SYMBOL_REF \ 1061: && CONSTANT_POOL_ADDRESS_P (X)) \ 1062: goto LABEL; \ 1063: else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \ 1064: && GET_CODE (XEXP (X, 0)) == REG \ 1065: && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \ 1066: goto LABEL; \ 1067: } 1068: 1069: /* Try machine-dependent ways of modifying an illegitimate address 1070: to be legitimate. If we find one, return the new, valid address. 1071: This macro is used in only one place: `memory_address' in explow.c. 1072: 1073: OLDX is the address as it was before break_out_memory_refs was called. 1074: In some cases it is useful to look at this to decide what needs to be done. 1075: 1076: MODE and WIN are passed so that this macro can use 1077: GO_IF_LEGITIMATE_ADDRESS. 1078: 1079: It is always safe for this macro to do nothing. It exists to recognize 1080: opportunities to optimize the output. 1081: 1082: On the ARM, try to convert [REG, #BIGCONST] 1083: into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST], 1084: where VALIDCONST == 0 in case of TImode. */ 1.1.1.3 ! root 1085: #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ ! 1086: { \ ! 1087: if (GET_CODE (X) == PLUS) \ ! 1088: { \ ! 1089: rtx xop0 = XEXP (X, 0); \ ! 1090: rtx xop1 = XEXP (X, 1); \ ! 1091: \ ! 1092: if (CONSTANT_P (xop0) && ! LEGITIMATE_CONSTANT_P (xop0)) \ ! 1093: xop0 = force_reg (SImode, xop0); \ ! 1094: if (CONSTANT_P (xop1) && ! LEGITIMATE_CONSTANT_P (xop1)) \ ! 1095: xop1 = force_reg (SImode, xop1); \ ! 1096: if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \ ! 1097: { \ ! 1098: HOST_WIDE_INT n, low_n; \ ! 1099: rtx base_reg, val; \ ! 1100: n = INTVAL (xop1); \ ! 1101: \ ! 1102: if (MODE == DImode) \ ! 1103: { \ ! 1104: low_n = n & 0x0f; \ ! 1105: n &= ~0x0f; \ ! 1106: if (low_n > 4) \ ! 1107: { \ ! 1108: n += 16; \ ! 1109: low_n -= 16; \ ! 1110: } \ ! 1111: } \ ! 1112: else \ ! 1113: { \ ! 1114: low_n = ((MODE) == TImode ? 0 \ ! 1115: : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \ ! 1116: n -= low_n; \ ! 1117: } \ ! 1118: base_reg = gen_reg_rtx (SImode); \ ! 1119: val = force_operand (gen_rtx (PLUS, SImode, xop0, \ ! 1120: GEN_INT (n)), NULL_RTX); \ ! 1121: emit_move_insn (base_reg, val); \ ! 1122: (X) = (low_n == 0 ? base_reg \ ! 1123: : gen_rtx (PLUS, SImode, base_reg, GEN_INT (low_n))); \ ! 1124: } \ ! 1125: else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \ ! 1126: (X) = gen_rtx (PLUS, SImode, xop0, xop1); \ ! 1127: } \ ! 1128: else if (GET_CODE (X) == MINUS) \ ! 1129: { \ ! 1130: rtx xop0 = XEXP (X, 0); \ ! 1131: rtx xop1 = XEXP (X, 1); \ ! 1132: \ ! 1133: if (CONSTANT_P (xop0)) \ ! 1134: xop0 = force_reg (SImode, xop0); \ ! 1135: if (CONSTANT_P (xop1) && ! LEGITIMATE_CONSTANT_P (xop1)) \ ! 1136: xop1 = force_reg (SImode, xop1); \ ! 1137: if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \ ! 1138: (X) = gen_rtx (MINUS, SImode, xop0, xop1); \ ! 1139: } \ ! 1140: if (memory_address_p (MODE, X)) \ ! 1141: goto WIN; \ 1.1 root 1142: } 1143: 1.1.1.3 ! root 1144: 1.1 root 1145: /* Go to LABEL if ADDR (a legitimate address expression) 1146: has an effect that depends on the machine mode it is used for. */ 1147: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 1148: { \ 1149: if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \ 1150: || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \ 1151: goto LABEL; \ 1152: } 1153: 1154: /* Specify the machine mode that this machine uses 1155: for the index in the tablejump instruction. */ 1156: #define CASE_VECTOR_MODE SImode 1157: 1158: /* Define this if the tablejump instruction expects the table 1159: to contain offsets from the address of the table. 1160: Do not define this if the table should contain absolute addresses. */ 1161: /* #define CASE_VECTOR_PC_RELATIVE */ 1162: 1163: /* Specify the tree operation to be used to convert reals to integers. */ 1164: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR 1165: 1166: /* This is the kind of divide that is easiest to do in the general case. */ 1167: #define EASY_DIV_EXPR TRUNC_DIV_EXPR 1168: 1.1.1.2 root 1169: /* signed 'char' is most compatible, but RISC OS wants it unsigned. 1170: unsigned is probably best, but may break some code. */ 1171: #ifndef DEFAULT_SIGNED_CHAR 1.1.1.3 ! root 1172: #define DEFAULT_SIGNED_CHAR 0 1.1 root 1173: #endif 1174: 1175: /* Don't cse the address of the function being compiled. */ 1176: #define NO_RECURSIVE_FUNCTION_CSE 1 1177: 1178: /* Max number of bytes we can move from memory to memory 1179: in one reasonably fast instruction. */ 1180: #define MOVE_MAX 4 1181: 1.1.1.2 root 1182: /* Define if operations between registers always perform the operation 1183: on the full register even if a narrower mode is specified. */ 1184: #define WORD_REGISTER_OPERATIONS 1185: 1186: /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1187: will either zero-extend or sign-extend. The value of this macro should 1188: be the code that says which one of the two operations is implicitly 1189: done, NIL if none. */ 1.1.1.3 ! root 1190: #define LOAD_EXTEND_OP(MODE) \ ! 1191: ((MODE) == QImode ? ZERO_EXTEND \ ! 1192: : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)) 1.1 root 1193: 1194: /* Define this if zero-extension is slow (more than one real instruction). 1195: On the ARM, it is more than one instruction only if not fetching from 1196: memory. */ 1197: /* #define SLOW_ZERO_EXTEND */ 1198: 1199: /* Nonzero if access to memory by bytes is slow and undesirable. */ 1200: #define SLOW_BYTE_ACCESS 0 1201: 1202: /* Immediate shift counts are truncated by the output routines (or was it 1203: the assembler?). Shift counts in a register are truncated by ARM. Note 1204: that the native compiler puts too large (> 32) immediate shift counts 1205: into a register and shifts by the register, letting the ARM decide what 1206: to do instead of doing that itself. */ 1.1.1.2 root 1207: /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 1208: code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 1209: On the arm, Y in a register is used modulo 256 for the shift. Only for 1210: rotates is modulo 32 used. */ 1211: /* #define SHIFT_COUNT_TRUNCATED 1 */ 1.1 root 1212: 1213: /* XX This is not true, is it? */ 1214: /* All integers have the same format so truncation is easy. */ 1215: #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1 1216: 1217: /* Calling from registers is a massive pain. */ 1218: #define NO_FUNCTION_CSE 1 1219: 1220: /* Chars and shorts should be passed as ints. */ 1221: #define PROMOTE_PROTOTYPES 1 1222: 1223: /* The machine modes of pointers and functions */ 1224: #define Pmode SImode 1225: #define FUNCTION_MODE Pmode 1226: 1227: /* The structure type of the machine dependent info field of insns 1228: No uses for this yet. */ 1229: /* #define INSN_MACHINE_INFO struct machine_info */ 1230: 1231: /* The relative costs of various types of constants. Note that cse.c defines 1232: REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */ 1.1.1.2 root 1233: #define CONST_COSTS(RTX, CODE, OUTER_CODE) \ 1234: case CONST_INT: \ 1235: if (const_ok_for_arm (INTVAL (RTX))) \ 1236: return (OUTER_CODE) == SET ? 2 : -1; \ 1237: else if (OUTER_CODE == AND \ 1238: && const_ok_for_arm (~INTVAL (RTX))) \ 1239: return -1; \ 1240: else if ((OUTER_CODE == COMPARE \ 1241: || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \ 1242: && const_ok_for_arm (-INTVAL (RTX))) \ 1243: return -1; \ 1244: else \ 1245: return 5; \ 1246: case CONST: \ 1247: case LABEL_REF: \ 1248: case SYMBOL_REF: \ 1249: return 6; \ 1250: case CONST_DOUBLE: \ 1251: if (const_double_rtx_ok_for_fpu (RTX)) \ 1252: return (OUTER_CODE) == SET ? 2 : -1; \ 1253: else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \ 1254: && neg_const_double_rtx_ok_for_fpu (RTX)) \ 1255: return -1; \ 1256: return(7); 1257: 1.1.1.3 ! root 1258: #define ARM_FRAME_RTX(X) \ ! 1259: ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ ! 1260: || (X) == arg_pointer_rtx) ! 1261: 1.1.1.2 root 1262: #define RTX_COSTS(X,CODE,OUTER_CODE) \ 1.1.1.3 ! root 1263: default: \ ! 1264: return arm_rtx_costs (X, CODE, OUTER_CODE); 1.1.1.2 root 1265: 1266: /* Moves to and from memory are quite expensive */ 1267: #define MEMORY_MOVE_COST(MODE) 10 1268: 1.1.1.3 ! root 1269: /* All address computations that can be done are free, but rtx cost returns ! 1270: the same for practically all of them. So we weight the differnt types ! 1271: of address here in the order (most pref first): ! 1272: PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ ! 1273: #define ADDRESS_COST(X) \ ! 1274: (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \ ! 1275: || GET_CODE (X) == SYMBOL_REF) \ ! 1276: ? 0 \ ! 1277: : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \ ! 1278: || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \ ! 1279: ? 10 \ ! 1280: : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \ ! 1281: ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \ ! 1282: : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \ ! 1283: || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \ ! 1284: || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \ ! 1285: || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \ ! 1286: ? 1 : 0)) \ ! 1287: : 4))))) ! 1288: ! 1289: 1.1.1.2 root 1290: 1291: /* Try to generate sequences that don't involve branches, we can then use 1292: conditional instructions */ 1293: #define BRANCH_COST 4 1.1 root 1294: 1.1.1.2 root 1295: /* Condition code information. */ 1296: /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 1297: return the mode to be used for the comparison. 1298: CCFPEmode should be used with floating inequalites, 1299: CCFPmode should be used with floating equalities. 1300: CC_NOOVmode should be used with SImode integer equalites 1301: CCmode should be used otherwise. */ 1302: 1303: #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode 1304: 1305: #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE" 1306: 1307: #define SELECT_CC_MODE(OP,X,Y) \ 1308: (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ 1309: ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \ 1310: : ((GET_MODE (X) == SImode) \ 1311: && ((OP) == EQ || (OP) == NE) \ 1312: && (GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \ 1313: || GET_CODE (X) == AND || GET_CODE (X) == IOR \ 1314: || GET_CODE (X) == XOR || GET_CODE (X) == MULT \ 1315: || GET_CODE (X) == NOT || GET_CODE (X) == NEG \ 1.1.1.3 ! root 1316: || GET_CODE (X) == LSHIFTRT \ 1.1.1.2 root 1317: || GET_CODE (X) == ASHIFT || GET_CODE (X) == ASHIFTRT \ 1318: || GET_CODE (X) == ROTATERT || GET_CODE (X) == ZERO_EXTRACT) \ 1319: ? CC_NOOVmode \ 1320: : GET_MODE (X) == QImode ? CC_NOOVmode : CCmode)) 1321: 1.1.1.3 ! root 1322: #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) ! 1323: 1.1.1.2 root 1324: #define STORE_FLAG_VALUE 1 1325: 1326: /* Define the information needed to generate branch insns. This is 1327: stored from the compare operation. Note that we can't use "rtx" here 1328: since it hasn't been defined! */ 1329: 1330: extern struct rtx_def *arm_compare_op0, *arm_compare_op1; 1331: extern int arm_compare_fp; 1332: 1333: /* Define the codes that are matched by predicates in arm.c */ 1334: #define PREDICATE_CODES \ 1335: {"s_register_operand", {SUBREG, REG}}, \ 1336: {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \ 1337: {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \ 1338: {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \ 1339: {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \ 1340: {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \ 1341: {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \ 1342: {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \ 1.1.1.3 ! root 1343: {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \ 1.1.1.2 root 1344: {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \ 1345: {"load_multiple_operation", {PARALLEL}}, \ 1346: {"store_multiple_operation", {PARALLEL}}, \ 1347: {"equality_operator", {EQ, NE}}, \ 1348: {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \ 1349: {"const_shift_operand", {CONST_INT}}, \ 1350: {"index_operand", {SUBREG, REG, CONST_INT}}, \ 1.1.1.3 ! root 1351: {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \ ! 1352: {"multi_register_push", {PARALLEL}}, \ ! 1353: {"cc_register", {REG}}, \ ! 1354: {"reversible_cc_register", {REG}}, 1.1 root 1355: 1356: 1357: /* Assembler output control */ 1358: 1.1.1.2 root 1359: #ifndef ARM_OS_NAME 1360: #define ARM_OS_NAME "(generic)" 1361: #endif 1362: 1.1 root 1363: /* The text to go at the start of the assembler file */ 1.1.1.3 ! root 1364: #define ASM_FILE_START(STREAM) \ ! 1365: { \ ! 1366: extern char *version_string; \ ! 1367: fprintf (STREAM,"%c Generated by gcc %s for ARM/%s\n", \ ! 1368: ARM_COMMENT_CHAR, version_string, ARM_OS_NAME); \ ! 1369: fprintf (STREAM,"%srfp\t.req\t%sr9\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \ ! 1370: fprintf (STREAM,"%ssl\t.req\t%sr10\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \ ! 1371: fprintf (STREAM,"%sfp\t.req\t%sr11\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \ ! 1372: fprintf (STREAM,"%sip\t.req\t%sr12\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \ ! 1373: fprintf (STREAM,"%ssp\t.req\t%sr13\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \ ! 1374: fprintf (STREAM,"%slr\t.req\t%sr14\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \ ! 1375: fprintf (STREAM,"%spc\t.req\t%sr15\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \ 1.1 root 1376: } 1377: 1378: #define ASM_APP_ON "" 1379: #define ASM_APP_OFF "" 1380: 1381: /* Switch to the text or data segment. */ 1382: #define TEXT_SECTION_ASM_OP ".text" 1383: #define DATA_SECTION_ASM_OP ".data" 1384: 1.1.1.3 ! root 1385: /* The assembler's names for the registers. */ ! 1386: #ifndef REGISTER_NAMES 1.1 root 1387: #define REGISTER_NAMES \ 1388: { \ 1389: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 1.1.1.3 ! root 1390: "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc", \ 1.1.1.2 root 1391: "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ 1392: "cc", "sfp", "afp" \ 1.1 root 1393: } 1.1.1.3 ! root 1394: #endif ! 1395: ! 1396: #ifndef ADDITIONAL_REGISTER_NAMES ! 1397: #define ADDITIONAL_REGISTER_NAMES \ ! 1398: { \ ! 1399: {"a1", 0}, \ ! 1400: {"a2", 1}, \ ! 1401: {"a3", 2}, \ ! 1402: {"a4", 3}, \ ! 1403: {"v1", 4}, \ ! 1404: {"v2", 5}, \ ! 1405: {"v3", 6}, \ ! 1406: {"v4", 7}, \ ! 1407: {"v5", 8}, \ ! 1408: {"v6", 9}, \ ! 1409: {"rfp", 9}, /* Gcc used to call it this */ \ ! 1410: {"sb", 9}, \ ! 1411: {"v7", 10}, \ ! 1412: {"r10", 10}, \ ! 1413: {"r11", 11}, /* fp */ \ ! 1414: {"r12", 12}, /* ip */ \ ! 1415: {"r13", 13}, /* sp */ \ ! 1416: {"r14", 14}, /* lr */ \ ! 1417: {"r15", 15} /* pc */ \ ! 1418: } ! 1419: #endif 1.1 root 1420: 1.1.1.2 root 1421: /* Arm Assembler barfs on dollars */ 1422: #define DOLLARS_IN_IDENTIFIERS 0 1423: 1424: #define NO_DOLLAR_IN_LABEL 1425: 1.1 root 1426: /* DBX register number for a given compiler register number */ 1427: #define DBX_REGISTER_NUMBER(REGNO) (REGNO) 1428: 1.1.1.2 root 1429: /* Generate DBX debugging information. riscix.h will undefine this because 1430: the native assembler does not support stabs. */ 1.1 root 1431: #define DBX_DEBUGGING_INFO 1 1432: 1433: /* Acorn dbx moans about continuation chars, so don't use any. */ 1.1.1.3 ! root 1434: #ifndef DBX_CONTIN_LENGTH 1.1 root 1435: #define DBX_CONTIN_LENGTH 0 1.1.1.3 ! root 1436: #endif 1.1 root 1437: 1.1.1.2 root 1438: /* Output a source filename for the debugger. RISCiX dbx insists that the 1439: ``desc'' field is set to compiler version number >= 315 (sic). */ 1440: #define DBX_OUTPUT_MAIN_SOURCE_FILENAME(STREAM,NAME) \ 1441: do { \ 1442: fprintf (STREAM, ".stabs \"%s\",%d,0,315,%s\n", (NAME), N_SO, \ 1443: <ext_label_name[1]); \ 1444: text_section (); \ 1445: ASM_OUTPUT_INTERNAL_LABEL (STREAM, "Ltext", 0); \ 1446: } while (0) 1447: 1.1 root 1448: /* Output a label definition. */ 1449: #define ASM_OUTPUT_LABEL(STREAM,NAME) \ 1450: arm_asm_output_label ((STREAM), (NAME)) 1451: 1452: /* Output a function label definition. */ 1453: #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \ 1454: ASM_OUTPUT_LABEL(STREAM, NAME) 1455: 1456: /* Output a globalising directive for a label. */ 1457: #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \ 1458: (fprintf (STREAM, "\t.global\t"), \ 1459: assemble_name (STREAM, NAME), \ 1460: fputc ('\n',STREAM)) \ 1461: 1462: /* Output a reference to a label. */ 1463: #define ASM_OUTPUT_LABELREF(STREAM,NAME) \ 1464: fprintf (STREAM, "_%s", NAME) 1465: 1466: /* Make an internal label into a string. */ 1467: #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \ 1468: sprintf (STRING, "*%s%d", PREFIX, NUM) 1469: 1470: /* Output an internal label definition. */ 1471: #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \ 1472: do \ 1473: { \ 1474: char *s = (char *) alloca (11 + strlen (PREFIX)); \ 1475: extern int arm_target_label, arm_ccfsm_state; \ 1.1.1.2 root 1476: extern rtx arm_target_insn; \ 1.1 root 1477: \ 1.1.1.2 root 1478: if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \ 1479: && !strcmp (PREFIX, "L")) \ 1480: { \ 1481: arm_ccfsm_state = 0; \ 1482: arm_target_insn = NULL; \ 1483: } \ 1484: strcpy (s, "*"); \ 1485: sprintf (&s[strlen (s)], "%s%d", (PREFIX), (NUM)); \ 1486: arm_asm_output_label (STREAM, s); \ 1.1 root 1487: } while (0) 1488: 1489: /* Nothing special is done about jump tables */ 1490: /* #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) */ 1491: /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */ 1492: 1493: /* Construct a private name. */ 1494: #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \ 1495: ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \ 1496: sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER))) 1497: 1498: /* Output a push or a pop instruction (only used when profiling). */ 1.1.1.3 ! root 1499: #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ ! 1500: fprintf(STREAM,"\tstmfd\t%ssp!,{%s%s}\n", ARM_REG_PREFIX, ARM_REG_PREFIX, \ ! 1501: reg_names[REGNO]) ! 1502: ! 1503: #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ ! 1504: fprintf(STREAM,"\tldmfd\t%ssp!,{%s%s}\n", ARM_REG_PREFIX, ARM_REG_PREFIX, \ ! 1505: reg_names[REGNO]) 1.1 root 1506: 1507: /* Output a relative address. Not needed since jump tables are absolute 1508: but we must define it anyway. */ 1509: #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \ 1510: fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM) 1511: 1512: /* Output an element of a dispatch table. */ 1513: #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ 1.1.1.3 ! root 1514: fprintf (STREAM, "\t.word\tL%d\n", VALUE) 1.1 root 1515: 1.1.1.2 root 1516: /* Output various types of constants. For real numbers we output hex, with 1517: a comment containing the "human" value, this allows us to pass NaN's which 1518: the riscix assembler doesn't understand (it also makes cross-assembling 1519: less likely to fail). */ 1520: 1521: #define ASM_OUTPUT_LONG_DOUBLE(STREAM,VALUE) \ 1522: do { char dstr[30]; \ 1523: long l[3]; \ 1524: arm_increase_location (12); \ 1525: REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \ 1526: REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ 1527: if (sizeof (int) == sizeof (long)) \ 1.1.1.3 ! root 1528: fprintf (STREAM, "\t.long 0x%x,0x%x,0x%x\t%c long double %s\n", \ ! 1529: l[2], l[1], l[0], ARM_COMMENT_CHAR, dstr); \ 1.1.1.2 root 1530: else \ 1.1.1.3 ! root 1531: fprintf (STREAM, "\t.long 0x%lx,0x%lx,0x%lx\t%c long double %s\n",\ ! 1532: l[0], l[1], l[2], ARM_COMMENT_CHAR, dstr); \ 1.1.1.2 root 1533: } while (0) 1534: 1535: 1536: #define ASM_OUTPUT_DOUBLE(STREAM, VALUE) \ 1537: do { char dstr[30]; \ 1538: long l[2]; \ 1539: arm_increase_location (8); \ 1540: REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \ 1541: REAL_VALUE_TO_DECIMAL (VALUE, "%.14g", dstr); \ 1542: if (sizeof (int) == sizeof (long)) \ 1.1.1.3 ! root 1543: fprintf (STREAM, "\t.long 0x%x, 0x%x\t%c double %s\n", l[0], \ ! 1544: l[1], ARM_COMMENT_CHAR, dstr); \ 1.1.1.2 root 1545: else \ 1.1.1.3 ! root 1546: fprintf (STREAM, "\t.long 0x%lx, 0x%lx\t%c double %s\n", l[0], \ ! 1547: l[1], ARM_COMMENT_CHAR, dstr); \ 1.1.1.2 root 1548: } while (0) 1549: 1550: #define ASM_OUTPUT_FLOAT(STREAM, VALUE) \ 1551: do { char dstr[30]; \ 1552: long l; \ 1553: arm_increase_location (4); \ 1554: REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ 1555: REAL_VALUE_TO_DECIMAL (VALUE, "%.7g", dstr); \ 1556: if (sizeof (int) == sizeof (long)) \ 1.1.1.3 ! root 1557: fprintf (STREAM, "\t.word 0x%x\t%c float %s\n", l, \ ! 1558: ARM_COMMENT_CHAR, dstr); \ 1.1.1.2 root 1559: else \ 1.1.1.3 ! root 1560: fprintf (STREAM, "\t.word 0x%lx\t%c float %s\n", l, \ ! 1561: ARM_COMMENT_CHAR, dstr); \ 1.1.1.2 root 1562: } while (0); 1563: 1564: #define ASM_OUTPUT_INT(STREAM, EXP) \ 1565: (fprintf (STREAM, "\t.word\t"), \ 1566: output_addr_const (STREAM, (EXP)), \ 1567: arm_increase_location (4), \ 1.1 root 1568: fputc ('\n', STREAM)) 1569: 1570: #define ASM_OUTPUT_SHORT(STREAM, EXP) \ 1571: (fprintf (STREAM, "\t.short\t"), \ 1572: output_addr_const (STREAM, (EXP)), \ 1573: arm_increase_location (2), \ 1574: fputc ('\n', STREAM)) 1575: 1576: #define ASM_OUTPUT_CHAR(STREAM, EXP) \ 1577: (fprintf (STREAM, "\t.byte\t"), \ 1578: output_addr_const (STREAM, (EXP)), \ 1579: arm_increase_location (1), \ 1580: fputc ('\n', STREAM)) 1581: 1582: #define ASM_OUTPUT_BYTE(STREAM, VALUE) \ 1583: (fprintf (STREAM, "\t.byte\t%d\n", VALUE), \ 1584: arm_increase_location (1)) 1585: 1586: #define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) \ 1.1.1.2 root 1587: output_ascii_pseudo_op ((STREAM), (unsigned char *)(PTR), (LEN)) 1.1 root 1588: 1589: /* Output a gap. In fact we fill it with nulls. */ 1590: #define ASM_OUTPUT_SKIP(STREAM, NBYTES) \ 1591: (arm_increase_location (NBYTES), \ 1592: fprintf (STREAM, "\t.space\t%d\n", NBYTES)) 1593: 1594: /* Align output to a power of two. Horrible /bin/as. */ 1595: #define ASM_OUTPUT_ALIGN(STREAM, POWER) \ 1596: do \ 1597: { \ 1598: register int amount = 1 << (POWER); \ 1599: extern int arm_text_location; \ 1600: \ 1601: if (amount == 2) \ 1602: fprintf (STREAM, "\t.even\n"); \ 1603: else \ 1604: fprintf (STREAM, "\t.align\t%d\n", amount - 4); \ 1605: \ 1606: if (in_text_section ()) \ 1607: arm_text_location = ((arm_text_location + amount - 1) \ 1608: & ~(amount - 1)); \ 1609: } while (0) 1610: 1611: /* Output a common block */ 1.1.1.3 ! root 1612: #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \ ! 1613: (fprintf (STREAM, "\t.comm\t"), \ ! 1614: assemble_name ((STREAM), (NAME)), \ ! 1615: fprintf(STREAM, ", %d\t%c%d\n", ROUNDED, ARM_COMMENT_CHAR, SIZE)) 1.1 root 1616: 1617: /* Output a local common block. /bin/as can't do this, so hack a `.space' into 1618: the bss segment. Note that this is *bad* practice. */ 1619: #define ASM_OUTPUT_LOCAL(STREAM,NAME,SIZE,ROUNDED) \ 1620: output_lcomm_directive (STREAM, NAME, SIZE, ROUNDED) 1621: 1622: /* Output a source line for the debugger. */ 1623: /* #define ASM_OUTPUT_SOURCE_LINE(STREAM,LINE) */ 1624: 1625: /* Output a #ident directive. */ 1626: #define ASM_OUTPUT_IDENT(STREAM,STRING) \ 1627: fprintf (STREAM,"- - - ident %s\n",STRING) 1628: 1629: /* The assembler's parentheses characters. */ 1630: #define ASM_OPEN_PAREN "(" 1631: #define ASM_CLOSE_PAREN ")" 1632: 1633: /* Target characters. */ 1634: #define TARGET_BELL 007 1635: #define TARGET_BS 010 1636: #define TARGET_TAB 011 1637: #define TARGET_NEWLINE 012 1638: #define TARGET_VT 013 1639: #define TARGET_FF 014 1640: #define TARGET_CR 015 1641: 1642: /* Only perform branch elimination (by making instructions conditional) if 1643: we're optimising. Otherwise it's of no use anyway. */ 1644: #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 1645: if (optimize) \ 1646: final_prescan_insn (INSN, OPVEC, NOPERANDS) 1647: 1.1.1.3 ! root 1648: #ifndef ARM_COMMENT_CHAR ! 1649: #define ARM_COMMENT_CHAR '@' ! 1650: #endif ! 1651: ! 1652: /* Default is for register names not to have a prefix. */ ! 1653: #ifndef ARM_REG_PREFIX ! 1654: #define ARM_REG_PREFIX "" ! 1655: #endif ! 1656: ! 1657: #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ ! 1658: ((CODE) == '?' || (CODE) == '|' || (CODE) == '@') ! 1659: /* Output an operand of an instruction. */ 1.1 root 1660: #define PRINT_OPERAND(STREAM, X, CODE) \ 1.1.1.3 ! root 1661: arm_print_operand (STREAM, X, CODE) ! 1662: ! 1663: #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ ! 1664: (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \ ! 1665: : (((x) & (unsigned HOST_WIDE_INT) 0xffffffff) | \ ! 1666: (((x) & (unsigned HOST_WIDE_INT) 0x80000000) \ ! 1667: ? ((~ (HOST_WIDE_INT) 0) \ ! 1668: & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ ! 1669: : 0)))) 1.1 root 1670: 1671: /* Output the address of an operand. */ 1672: #define PRINT_OPERAND_ADDRESS(STREAM,X) \ 1673: { \ 1674: int is_minus = GET_CODE (X) == MINUS; \ 1675: \ 1676: if (GET_CODE (X) == REG) \ 1.1.1.3 ! root 1677: fprintf (STREAM, "[%s%s, #0]", ARM_REG_PREFIX, \ ! 1678: reg_names[REGNO (X)]); \ 1.1 root 1679: else if (GET_CODE (X) == PLUS || is_minus) \ 1680: { \ 1681: rtx base = XEXP (X, 0); \ 1682: rtx index = XEXP (X, 1); \ 1683: char *base_reg_name; \ 1.1.1.3 ! root 1684: HOST_WIDE_INT offset = 0; \ 1.1 root 1685: if (GET_CODE (base) != REG) \ 1686: { \ 1687: /* Ensure that BASE is a register (one of them must be). */ \ 1688: rtx temp = base; \ 1689: base = index; \ 1690: index = temp; \ 1691: } \ 1692: base_reg_name = reg_names[REGNO (base)]; \ 1693: switch (GET_CODE (index)) \ 1694: { \ 1695: case CONST_INT: \ 1696: offset = INTVAL (index); \ 1697: if (is_minus) \ 1698: offset = -offset; \ 1.1.1.3 ! root 1699: fprintf (STREAM, "[%s%s, #%d]", ARM_REG_PREFIX, \ ! 1700: base_reg_name, offset); \ 1.1 root 1701: break; \ 1702: \ 1703: case REG: \ 1.1.1.3 ! root 1704: fprintf (STREAM, "[%s%s, %s%s%s]", ARM_REG_PREFIX, \ ! 1705: base_reg_name, is_minus ? "-" : "", \ ! 1706: ARM_REG_PREFIX, reg_names[REGNO (index)] ); \ 1.1 root 1707: break; \ 1708: \ 1709: case MULT: \ 1.1.1.2 root 1710: case ASHIFTRT: \ 1711: case LSHIFTRT: \ 1712: case ASHIFT: \ 1713: case ROTATERT: \ 1714: { \ 1.1.1.3 ! root 1715: fprintf (STREAM, "[%s%s, %s%s%s", ARM_REG_PREFIX, \ ! 1716: base_reg_name, is_minus ? "-" : "", ARM_REG_PREFIX,\ ! 1717: reg_names[REGNO (XEXP (index, 0))]); \ ! 1718: arm_print_operand (STREAM, index, 'S'); \ ! 1719: fputs ("]", STREAM); \ 1.1.1.2 root 1720: break; \ 1721: } \ 1.1 root 1722: \ 1723: default: \ 1724: abort(); \ 1725: } \ 1726: } \ 1727: else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \ 1728: || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \ 1729: { \ 1730: extern int output_memory_reference_mode; \ 1731: \ 1732: if (GET_CODE (XEXP (X, 0)) != REG) \ 1733: abort (); \ 1734: \ 1735: if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ 1.1.1.3 ! root 1736: fprintf (STREAM, "[%s%s, #%s%d]!", ARM_REG_PREFIX, \ ! 1737: reg_names[REGNO (XEXP (X, 0))], \ 1.1 root 1738: GET_CODE (X) == PRE_DEC ? "-" : "", \ 1739: GET_MODE_SIZE (output_memory_reference_mode)); \ 1740: else \ 1.1.1.3 ! root 1741: fprintf (STREAM, "[%s%s], #%s%d", ARM_REG_PREFIX, \ ! 1742: reg_names[REGNO (XEXP (X, 0))], \ 1.1 root 1743: GET_CODE (X) == POST_DEC ? "-" : "", \ 1744: GET_MODE_SIZE (output_memory_reference_mode)); \ 1745: } \ 1746: else output_addr_const(STREAM, X); \ 1747: }
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