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1.1 root 1: /* Definitions of target machine for GNU compiler, for Acorn RISC Machine. 1.1.1.4 ! root 2: Copyright (C) 1991, 1993, 1994, 1995 Free Software Foundation, Inc. 1.1 root 3: Contributed by Pieter `Tiggr' Schoenmakers ([email protected]) 1.1.1.4 ! root 4: and Martin Simmons (@harleqn.co.uk). 1.1.1.2 root 5: More major hacks by Richard Earnshaw ([email protected]) 6: 1.1 root 7: This file is part of GNU CC. 8: 9: GNU CC is free software; you can redistribute it and/or modify 10: it under the terms of the GNU General Public License as published by 11: the Free Software Foundation; either version 2, or (at your option) 12: any later version. 13: 14: GNU CC is distributed in the hope that it will be useful, 15: but WITHOUT ANY WARRANTY; without even the implied warranty of 16: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17: GNU General Public License for more details. 18: 19: You should have received a copy of the GNU General Public License 20: along with GNU CC; see the file COPYING. If not, write to 1.1.1.4 ! root 21: the Free Software Foundation, 59 Temple Place - Suite 330, ! 22: Boston, MA 02111-1307, USA. */ 1.1 root 23: 24: /* Sometimes the directive `riscos' is checked. This does not imply that this 25: tm file can be used unchanged to build a GCC for RISC OS. 26: (Since in fact, it can't.) */ 27: 1.1.1.3 root 28: extern void output_func_prologue (); 29: extern void output_func_epilogue (); 1.1 root 30: extern char *output_add_immediate (); 31: extern char *output_call (); 1.1.1.2 root 32: extern char *output_call_mem (); 1.1 root 33: extern char *output_move_double (); 34: extern char *output_mov_double_fpu_from_arm (); 35: extern char *output_mov_double_arm_from_fpu (); 1.1.1.2 root 36: extern char *output_mov_long_double_fpu_from_arm (); 37: extern char *output_mov_long_double_arm_from_fpu (); 38: extern char *output_mov_long_double_arm_from_arm (); 1.1 root 39: extern char *output_mov_immediate (); 40: extern char *output_multi_immediate (); 1.1.1.2 root 41: extern char *output_return_instruction (); 42: extern char *output_load_symbol (); 43: extern char *fp_immediate_constant (); 44: extern struct rtx_def *gen_compare_reg (); 45: extern struct rtx_def *arm_gen_store_multiple (); 46: extern struct rtx_def *arm_gen_load_multiple (); 47: 48: extern char *arm_condition_codes[]; 49: 50: /* This is needed by the tail-calling peepholes */ 51: extern int frame_pointer_needed; 52: 1.1 root 53: 1.1.1.2 root 54: #ifndef CPP_PREDEFINES 55: #define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)" 56: #endif 1.1 root 57: 1.1.1.2 root 58: #ifndef CPP_SPEC 59: #define CPP_SPEC "%{m6:-D__arm6__}" 1.1 root 60: #endif 61: 62: /* Run-time Target Specification. */ 1.1.1.2 root 63: #ifndef TARGET_VERSION 1.1 root 64: #define TARGET_VERSION \ 1.1.1.2 root 65: fputs (" (ARM/generic)", stderr); 66: #endif 1.1 root 67: 68: /* Run-time compilation parameters selecting different hardware subsets. 69: On the ARM, misuse it in a different way. */ 70: extern int target_flags; 71: 72: /* Nonzero if the function prologue (and epilogue) should obey 73: the ARM Procedure Call Standard. */ 74: #define TARGET_APCS (target_flags & 1) 75: 76: /* Nonzero if the function prologue should output the function name to enable 77: the post mortem debugger to print a backtrace (very useful on RISCOS, 78: unused on RISCiX). Specifying this flag also enables -mapcs. 79: XXX Must still be implemented in the prologue. */ 80: #define TARGET_POKE_FUNCTION_NAME (target_flags & 2) 81: 82: /* Nonzero if floating point instructions are emulated by the FPE, in which 83: case instruction scheduling becomes very uninteresting. */ 84: #define TARGET_FPE (target_flags & 4) 85: 1.1.1.2 root 86: /* Nonzero if destined for an ARM6xx. Takes out bits that assume restoration 87: of condition flags when returning from a branch & link (ie. a function) */ 88: #define TARGET_6 (target_flags & 8) 89: 1.1.1.3 root 90: /* Leave some bits for new processor variants */ 91: 92: /* Nonzero if shorts must be loaded byte at a time. This is not necessary 93: for the arm processor chip, but it is needed for some MMU chips. */ 94: #define TARGET_SHORT_BY_BYTES (target_flags & 0x200) 95: 1.1.1.4 ! root 96: /* Nonzero if GCC should use a floating point library. ! 97: GCC will assume the fp regs don't exist and will not emit any fp insns. ! 98: Note that this is different than fp emulation which still uses fp regs ! 99: and insns - the kernel catches the trap and performs the operation. */ ! 100: #define TARGET_SOFT_FLOAT (target_flags & 0x400) ! 101: #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT) ! 102: ! 103: /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. ! 104: Bit 31 is reserved. See riscix.h. */ ! 105: #ifndef SUBTARGET_SWITCHES ! 106: #define SUBTARGET_SWITCHES 1.1.1.2 root 107: #endif 108: 1.1.1.3 root 109: #define TARGET_SWITCHES \ 110: { \ 111: {"apcs", 1}, \ 112: {"poke-function-name", 2}, \ 113: {"fpe", 4}, \ 114: {"6", 8}, \ 115: {"2", -8}, \ 116: {"3", -8}, \ 117: {"short-load-bytes", (0x200)}, \ 118: {"no-short-load-bytes", -(0x200)}, \ 119: {"short-load-words", -(0x200)}, \ 120: {"no-short-load-words", (0x200)}, \ 1.1.1.4 ! root 121: {"soft-float", (0x400)}, \ ! 122: {"hard-float", -(0x400)}, \ ! 123: SUBTARGET_SWITCHES \ 1.1.1.3 root 124: {"", TARGET_DEFAULT } \ 1.1 root 125: } 126: 1.1.1.2 root 127: /* Which processor we are running on. Currently this is only used to 128: get the condition code clobbering attribute right when we are running on 129: an arm 6 */ 130: 131: enum processor_type 132: { 133: PROCESSOR_ARM2, 134: PROCESSOR_ARM3, 135: PROCESSOR_ARM6 136: }; 137: 138: /* Recast the cpu class to be the cpu attribute. */ 139: 140: /* Recast the cpu class to be the cpu attribute. */ 141: #define arm_cpu_attr ((enum attr_cpu)arm_cpu) 142: 143: extern enum processor_type arm_cpu; 144: 1.1.1.3 root 145: /* What sort of floating point unit do we have? Hardware or software. */ 146: enum floating_point_type 147: { 148: FP_HARD, 149: FP_SOFT 150: }; 151: 152: /* Recast the floating point class to be the floating point attribute. */ 153: #define arm_fpu_attr ((enum attr_fpu) arm_fpu) 154: 155: extern enum floating_point_type arm_fpu; 156: 157: #ifndef TARGET_DEFAULT 1.1 root 158: #define TARGET_DEFAULT 0 1.1.1.3 root 159: #endif 1.1 root 160: 161: #define TARGET_MEM_FUNCTIONS 1 162: 163: /* OVERRIDE_OPTIONS takes care of the following: 164: - if -mpoke-function-name, then -mapcs. 165: - if doing debugging, then -mapcs; if RISCOS, then -mpoke-function-name. 166: - if floating point is done by emulation, forget about instruction 167: scheduling. Note that this only saves compilation time; it doesn't 168: matter for the final code. */ 169: 170: #define OVERRIDE_OPTIONS \ 171: { \ 1.1.1.2 root 172: if (write_symbols != NO_DEBUG && flag_omit_frame_pointer) \ 173: warning ("-g without a frame pointer may not give sensible debugging");\ 174: if (TARGET_POKE_FUNCTION_NAME) \ 1.1 root 175: target_flags |= 1; \ 176: if (TARGET_FPE) \ 177: flag_schedule_insns = flag_schedule_insns_after_reload = 0; \ 1.1.1.2 root 178: arm_cpu = TARGET_6 ? PROCESSOR_ARM6: PROCESSOR_ARM2; \ 1.1 root 179: } 180: 181: /* Target machine storage Layout. */ 182: 1.1.1.2 root 183: 184: /* Define this macro if it is advisable to hold scalars in registers 185: in a wider mode than that declared by the program. In such cases, 186: the value is constrained to be within the bounds of the declared 187: type, but kept valid in the wider mode. The signedness of the 188: extension may differ from that of the type. */ 189: 190: /* It is far faster to zero extend chars than to sign extend them */ 191: 192: #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 1.1.1.3 root 193: if (GET_MODE_CLASS (MODE) == MODE_INT \ 194: && GET_MODE_SIZE (MODE) < 4) \ 195: { \ 196: if (MODE == QImode) \ 197: UNSIGNEDP = 1; \ 198: else if (MODE == HImode) \ 199: UNSIGNEDP = TARGET_SHORT_BY_BYTES != 0; \ 200: (MODE) = SImode; \ 1.1.1.2 root 201: } 202: 203: /* Define for XFmode extended real floating point support. 204: This will automatically cause REAL_ARITHMETIC to be defined. */ 205: /* For the ARM: 206: I think I have added all the code to make this work. Unfortunately, 207: early releases of the floating point emulation code on RISCiX used a 208: different format for extended precision numbers. On my RISCiX box there 209: is a bug somewhere which causes the machine to lock up when running enquire 210: with long doubles. There is the additional aspect that Norcroft C 211: treats long doubles as doubles and we ought to remain compatible. 212: Perhaps someone with an FPA coprocessor and not running RISCiX would like 213: to try this someday. */ 214: /* #define LONG_DOUBLE_TYPE_SIZE 96 */ 215: 216: /* Disable XFmode patterns in md file */ 217: #define ENABLE_XF_PATTERNS 0 218: 219: /* Define if you don't want extended real, but do want to use the 220: software floating point emulator for REAL_ARITHMETIC and 221: decimal <-> binary conversion. */ 222: /* See comment above */ 223: #define REAL_ARITHMETIC 224: 1.1 root 225: /* Define this if most significant bit is lowest numbered 226: in instructions that operate on numbered bit-fields. */ 227: #define BITS_BIG_ENDIAN 0 228: 1.1.1.3 root 229: /* Define this if most significant byte of a word is the lowest numbered. 1.1.1.4 ! root 230: Most ARM processors are run in little endian mode, so that is the default. ! 231: If you want to have it run-time selectable, change the definition in a ! 232: cover file to be TARGET_BIG_ENDIAN. */ 1.1 root 233: #define BYTES_BIG_ENDIAN 0 234: 235: /* Define this if most significant word of a multiword number is the lowest 236: numbered. */ 237: #define WORDS_BIG_ENDIAN 0 238: 1.1.1.2 root 239: /* Define this if most significant word of doubles is the lowest numbered */ 240: #define FLOAT_WORDS_BIG_ENDIAN 1 241: 1.1 root 242: /* Number of bits in an addressable storage unit */ 243: #define BITS_PER_UNIT 8 244: 245: #define BITS_PER_WORD 32 246: 247: #define UNITS_PER_WORD 4 248: 249: #define POINTER_SIZE 32 250: 251: #define PARM_BOUNDARY 32 252: 253: #define STACK_BOUNDARY 32 254: 255: #define FUNCTION_BOUNDARY 32 256: 257: #define EMPTY_FIELD_BOUNDARY 32 258: 259: #define BIGGEST_ALIGNMENT 32 260: 1.1.1.2 root 261: /* Make strings word-aligned so strcpy from constants will be faster. */ 262: #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 263: (TREE_CODE (EXP) == STRING_CST \ 264: && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 265: 1.1 root 266: /* Every structures size must be a multiple of 32 bits. */ 267: #define STRUCTURE_SIZE_BOUNDARY 32 268: 1.1.1.2 root 269: /* Non-zero if move instructions will actually fail to work 270: when given unaligned data. */ 1.1 root 271: #define STRICT_ALIGNMENT 1 272: 1.1.1.2 root 273: #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT 274: 1.1 root 275: /* Define number of bits in most basic integer type. 276: (If undefined, default is BITS_PER_WORD). */ 277: /* #define INT_TYPE_SIZE */ 278: 279: /* Standard register usage. */ 280: 281: /* Register allocation in ARM Procedure Call Standard (as used on RISCiX): 282: (S - saved over call). 283: 284: r0 * argument word/integer result 285: r1-r3 argument word 286: 287: r4-r8 S register variable 288: r9 S (rfp) register variable (real frame pointer) 289: 290: r10 F S (sl) stack limit (not currently used) 291: r11 F S (fp) argument pointer 292: r12 (ip) temp workspace 293: r13 F S (sp) lower end of current stack frame 294: r14 (lr) link address/workspace 295: r15 F (pc) program counter 296: 297: f0 floating point result 298: f1-f3 floating point scratch 299: 300: f4-f7 S floating point variable 301: 1.1.1.2 root 302: cc This is NOT a real register, but is used internally 303: to represent things that use or set the condition 304: codes. 305: sfp This isn't either. It is used during rtl generation 306: since the offset between the frame pointer and the 307: auto's isn't known until after register allocation. 308: afp Nor this, we only need this because of non-local 309: goto. Without it fp appears to be used and the 310: elimination code won't get rid of sfp. It tracks 311: fp exactly at all times. 312: 1.1 root 313: *: See CONDITIONAL_REGISTER_USAGE */ 314: 1.1.1.2 root 315: /* The stack backtrace structure is as follows: 316: fp points to here: | save code pointer | [fp] 317: | return link value | [fp, #-4] 318: | return sp value | [fp, #-8] 319: | return fp value | [fp, #-12] 320: [| saved r10 value |] 321: [| saved r9 value |] 322: [| saved r8 value |] 323: [| saved r7 value |] 324: [| saved r6 value |] 325: [| saved r5 value |] 326: [| saved r4 value |] 327: [| saved r3 value |] 328: [| saved r2 value |] 329: [| saved r1 value |] 330: [| saved r0 value |] 331: [| saved f7 value |] three words 332: [| saved f6 value |] three words 333: [| saved f5 value |] three words 334: [| saved f4 value |] three words 335: r0-r3 are not normally saved in a C function. */ 336: 337: /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */ 338: #define FIRST_PSEUDO_REGISTER 27 1.1 root 339: 340: /* 1 for registers that have pervasive standard uses 341: and are not available for the register allocator. */ 342: #define FIXED_REGISTERS \ 343: { \ 344: 0,0,0,0,0,0,0,0, \ 345: 0,0,1,1,0,1,0,1, \ 1.1.1.2 root 346: 0,0,0,0,0,0,0,0, \ 347: 1,1,1 \ 1.1 root 348: } 349: 350: /* 1 for registers not available across function calls. 351: These must include the FIXED_REGISTERS and also any 352: registers that can be used without being saved. 353: The latter must include the registers where values are returned 354: and the register where structure-value addresses are passed. 1.1.1.2 root 355: Aside from that, you can include as many other registers as you like. 356: The CC is not preserved over function calls on the ARM 6, so it is 357: easier to assume this for all. SFP is preserved, since FP is. */ 1.1 root 358: #define CALL_USED_REGISTERS \ 359: { \ 360: 1,1,1,1,0,0,0,0, \ 361: 0,0,1,1,1,1,1,1, \ 1.1.1.2 root 362: 1,1,1,1,0,0,0,0, \ 363: 1,1,1 \ 1.1 root 364: } 365: 366: /* If doing stupid life analysis, avoid a bug causing a return value r0 to be 367: trampled. This effectively reduces the number of available registers by 1. 368: XXX It is a hack, I know. 369: XXX Is this still needed? */ 370: #define CONDITIONAL_REGISTER_USAGE \ 1.1.1.4 ! root 371: { \ ! 372: if (obey_regdecls) \ ! 373: fixed_regs[0] = 1; \ ! 374: if (TARGET_SOFT_FLOAT) \ ! 375: { \ ! 376: int regno; \ ! 377: for (regno = 16; regno < 24; ++regno) \ ! 378: fixed_regs[regno] = call_used_regs[regno] = 1; \ ! 379: } \ 1.1 root 380: } 381: 382: /* Return number of consecutive hard regs needed starting at reg REGNO 383: to hold something of mode MODE. 384: This is ordinarily the length in words of a value of mode MODE 385: but can be less for certain modes in special long registers. 386: 387: On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP 388: mode. */ 1.1.1.2 root 389: #define HARD_REGNO_NREGS(REGNO, MODE) \ 390: (((REGNO) >= 16 && REGNO != FRAME_POINTER_REGNUM \ 391: && (REGNO) != ARG_POINTER_REGNUM) ? 1 \ 1.1 root 392: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 393: 394: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 395: This is TRUE for ARM regs since they can hold anything, and TRUE for FPU 396: regs holding FP. */ 1.1.1.2 root 397: #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 398: ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \ 399: ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \ 400: || REGNO == ARG_POINTER_REGNUM \ 401: || GET_MODE_CLASS (MODE) == MODE_FLOAT)) 1.1 root 402: 403: /* Value is 1 if it is a good idea to tie two pseudo registers 404: when one has mode MODE1 and one has mode MODE2. 405: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 406: for any hard reg, then this must be 0 for correct output. */ 407: #define MODES_TIEABLE_P(MODE1, MODE2) \ 1.1.1.3 root 408: (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) 1.1 root 409: 410: /* Specify the registers used for certain standard purposes. 411: The values of these macros are register numbers. */ 412: 413: /* Define this if the program counter is overloaded on a register. */ 414: #define PC_REGNUM 15 415: 416: /* Register to use for pushing function arguments. */ 417: #define STACK_POINTER_REGNUM 13 418: 419: /* Base register for access to local variables of the function. */ 1.1.1.2 root 420: #define FRAME_POINTER_REGNUM 25 421: 422: /* Define this to be where the real frame pointer is if it is not possible to 423: work out the offset between the frame pointer and the automatic variables 424: until after register allocation has taken place. FRAME_POINTER_REGNUM 425: should point to a special register that we will make sure is eliminated. */ 426: #define HARD_FRAME_POINTER_REGNUM 11 1.1 root 427: 428: /* Value should be nonzero if functions must have frame pointers. 429: Zero means the frame pointer need not be set up (and parms may be accessed 1.1.1.2 root 430: via the stack pointer) in functions that seem suitable. 431: If we have to have a frame pointer we might as well make use of it. 432: APCS says that the frame pointer does not need to be pushed in leaf 433: functions. */ 1.1.1.3 root 434: #define FRAME_POINTER_REQUIRED \ 435: (current_function_has_nonlocal_label || (TARGET_APCS && !leaf_function_p ())) 1.1 root 436: 437: /* Base register for access to arguments of the function. */ 1.1.1.2 root 438: #define ARG_POINTER_REGNUM 26 1.1 root 439: 440: /* The native (Norcroft) Pascal compiler for the ARM passes the static chain 441: as an invisible last argument (possible since varargs don't exist in 442: Pascal), so the following is not true. */ 443: #define STATIC_CHAIN_REGNUM 8 444: 445: /* Register in which address to store a structure value 446: is passed to a function. */ 447: #define STRUCT_VALUE_REGNUM 0 448: 1.1.1.2 root 449: /* Internal, so that we don't need to refer to a raw number */ 450: #define CC_REGNUM 24 451: 1.1 root 452: /* The order in which register should be allocated. It is good to use ip 1.1.1.2 root 453: since no saving is required (though calls clobber it) and it never contains 454: function parameters. It is quite good to use lr since other calls may 455: clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 456: least likely to contain a function parameter; in addition results are 457: returned in r0. 458: */ 1.1 root 459: #define REG_ALLOC_ORDER \ 460: { \ 1.1.1.2 root 461: 3, 2, 1, 0, 12, 14, 4, 5, \ 1.1 root 462: 6, 7, 8, 10, 9, 11, 13, 15, \ 1.1.1.2 root 463: 16, 17, 18, 19, 20, 21, 22, 23, \ 464: 24, 25 \ 1.1 root 465: } 466: 467: /* Register and constant classes. */ 468: 469: /* Register classes: all ARM regs or all FPU regs---simple! */ 470: enum reg_class 471: { 472: NO_REGS, 473: FPU_REGS, 474: GENERAL_REGS, 475: ALL_REGS, 476: LIM_REG_CLASSES 477: }; 478: 479: #define N_REG_CLASSES (int) LIM_REG_CLASSES 480: 481: /* Give names of register classes as strings for dump file. */ 482: #define REG_CLASS_NAMES \ 483: { \ 484: "NO_REGS", \ 485: "FPU_REGS", \ 486: "GENERAL_REGS", \ 487: "ALL_REGS", \ 488: } 489: 490: /* Define which registers fit in which classes. 491: This is an initializer for a vector of HARD_REG_SET 492: of length N_REG_CLASSES. */ 493: #define REG_CLASS_CONTENTS \ 494: { \ 1.1.1.2 root 495: 0x0000000, /* NO_REGS */ \ 496: 0x0FF0000, /* FPU_REGS */ \ 497: 0x200FFFF, /* GENERAL_REGS */ \ 498: 0x2FFFFFF /* ALL_REGS */ \ 1.1 root 499: } 500: 501: /* The same information, inverted: 502: Return the class number of the smallest class containing 503: reg number REGNO. This could be a conditional expression 504: or could index an array. */ 1.1.1.2 root 505: #define REGNO_REG_CLASS(REGNO) \ 506: (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \ 507: || REGNO == ARG_POINTER_REGNUM) \ 508: ? GENERAL_REGS : (REGNO) == CC_REGNUM \ 509: ? NO_REGS : FPU_REGS) 1.1 root 510: 511: /* The class value for index registers, and the one for base regs. */ 512: #define INDEX_REG_CLASS GENERAL_REGS 513: #define BASE_REG_CLASS GENERAL_REGS 514: 515: /* Get reg_class from a letter such as appears in the machine description. 516: We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */ 517: #define REG_CLASS_FROM_LETTER(C) \ 518: ((C)=='f' ? FPU_REGS : NO_REGS) 519: 520: /* The letters I, J, K, L and M in a register constraint string 521: can be used to stand for particular ranges of immediate operands. 522: This macro defines what the ranges are. 523: C is the letter, and VALUE is a constant value. 524: Return 1 if VALUE is in the range specified by C. 525: I: immediate arithmetic operand (i.e. 8 bits shifted as required). 1.1.1.2 root 526: J: valid indexing constants. 1.1.1.3 root 527: K: ~value ok in rhs argument of data operand. 528: L: -value ok in rhs argument of data operand. 529: M: 0..32, or a power of 2 (for shifts, or mult done by shift). */ 530: #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 531: ((C) == 'I' ? const_ok_for_arm (VALUE) : \ 532: (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \ 533: (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \ 534: (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \ 535: (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \ 536: || (((VALUE) & ((VALUE) - 1)) == 0)) \ 537: : 0) 1.1.1.2 root 538: 539: /* For the ARM, `Q' means that this is a memory operand that is just 540: an offset from a register. 541: `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL 542: address. This means that the symbol is in the text segment and can be 543: accessed without using a load. */ 544: 545: #define EXTRA_CONSTRAINT(OP, C) \ 546: ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \ 1.1.1.3 root 547: : (C) == 'R' ? (GET_CODE (OP) == MEM \ 548: && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ 549: && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \ 550: : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : 0) 1.1.1.2 root 551: 552: /* Constant letter 'G' for the FPU immediate constants. 553: 'H' means the same constant negated. */ 554: #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \ 555: ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \ 556: : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0) 1.1 root 557: 558: /* Given an rtx X being reloaded into a reg required to be 559: in class CLASS, return the class of reg to actually use. 560: In general this is just CLASS; but on some machines 561: in some cases it is preferable to use a more restrictive class. */ 562: #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS) 563: 1.1.1.2 root 564: /* Return the register class of a scratch register needed to copy IN into 565: or out of a register in CLASS in MODE. If it can be done directly, 566: NO_REGS is returned. */ 567: #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \ 568: (((MODE) == DFmode && (CLASS) == GENERAL_REGS \ 1.1.1.4 ! root 569: && true_regnum (X) == -1 && TARGET_HARD_FLOAT) \ ! 570: ? GENERAL_REGS \ 1.1.1.2 root 571: : ((MODE) == HImode && true_regnum (X) == -1) ? GENERAL_REGS : NO_REGS) 572: 1.1.1.3 root 573: /* If we need to load shorts byte-at-a-time, then we need a scratch. */ 574: #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \ 575: (((MODE) == HImode && TARGET_SHORT_BY_BYTES && true_regnum (X) == -1) \ 576: ? GENERAL_REGS : NO_REGS) 577: 1.1 root 578: /* Return the maximum number of consecutive registers 579: needed to represent mode MODE in a register of class CLASS. 580: ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */ 581: #define CLASS_MAX_NREGS(CLASS, MODE) \ 582: ((CLASS) == FPU_REGS ? 1 \ 583: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 584: 1.1.1.2 root 585: /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */ 1.1 root 586: #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ 587: ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \ 588: || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \ 1.1.1.2 root 589: ? 20 : 2) 1.1 root 590: 591: /* Stack layout; function entry, exit and calling. */ 592: 593: /* Define this if pushing a word on the stack 594: makes the stack pointer a smaller address. */ 595: #define STACK_GROWS_DOWNWARD 1 596: 597: /* Define this if the nominal address of the stack frame 598: is at the high-address end of the local variables; 599: that is, each additional local variable allocated 600: goes at a more negative offset in the frame. */ 601: #define FRAME_GROWS_DOWNWARD 1 602: 603: /* Offset within stack frame to start allocating local variables at. 604: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 605: first local allocated. Otherwise, it is the offset to the BEGINNING 606: of the first local allocated. */ 607: #define STARTING_FRAME_OFFSET 0 608: 609: /* If we generate an insn to push BYTES bytes, 610: this says how many the stack pointer really advances by. */ 611: #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) 612: 613: /* Offset of first parameter from the argument pointer register value. */ 614: #define FIRST_PARM_OFFSET(FNDECL) 4 615: 616: /* Value is the number of byte of arguments automatically 617: popped when returning from a subroutine call. 1.1.1.4 ! root 618: FUNDECL is the declaration node of the function (as a tree), 1.1 root 619: FUNTYPE is the data type of the function (as a tree), 620: or for a library call it is an identifier node for the subroutine name. 621: SIZE is the number of bytes of arguments passed on the stack. 622: 623: On the ARM, the caller does not pop any of its arguments that were passed 624: on the stack. */ 1.1.1.4 ! root 625: #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 1.1 root 626: 627: /* Define how to find the value returned by a function. 628: VALTYPE is the data type of the value (as a tree). 629: If the precise function being called is known, FUNC is its FUNCTION_DECL; 630: otherwise, FUNC is 0. */ 631: #define FUNCTION_VALUE(VALTYPE, FUNC) \ 1.1.1.4 ! root 632: (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT && TARGET_HARD_FLOAT \ ! 633: ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \ 1.1 root 634: : gen_rtx (REG, TYPE_MODE (VALTYPE), 0)) 635: 636: /* Define how to find the value returned by a library function 637: assuming the value has mode MODE. */ 638: #define LIBCALL_VALUE(MODE) \ 1.1.1.4 ! root 639: (GET_MODE_CLASS (MODE) == MODE_FLOAT && TARGET_HARD_FLOAT \ ! 640: ? gen_rtx (REG, MODE, 16) \ 1.1 root 641: : gen_rtx (REG, MODE, 0)) 642: 643: /* 1 if N is a possible register number for a function value. 644: On the ARM, only r0 and f0 can return results. */ 645: #define FUNCTION_VALUE_REGNO_P(REGNO) \ 1.1.1.4 ! root 646: ((REGNO) == 0 || ((REGNO) == 16) && TARGET_HARD_FLOAT) 1.1 root 647: 648: /* Define where to put the arguments to a function. 649: Value is zero to push the argument on the stack, 650: or a hard register in which to store the argument. 651: 652: MODE is the argument's machine mode. 653: TYPE is the data type of the argument (as a tree). 654: This is null for libcalls where that information may 655: not be available. 656: CUM is a variable of type CUMULATIVE_ARGS which gives info about 657: the preceding args and about the function being called. 658: NAMED is nonzero if this argument is a named parameter 659: (otherwise it is an extra parameter matching an ellipsis). 660: 661: On the ARM, normally the first 16 bytes are passed in registers r0-r3; all 662: other arguments are passed on the stack. If (NAMED == 0) (which happens 663: only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is 664: passed in the stack (function_prologue will indeed make it pass in the 665: stack if necessary). */ 666: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 667: ((NAMED) \ 668: ? ((CUM) >= 16 ? 0 : gen_rtx (REG, MODE, (CUM) / 4)) \ 669: : 0) 670: 671: /* For an arg passed partly in registers and partly in memory, 672: this is the number of registers used. 673: For args passed entirely in registers or entirely in memory, zero. */ 674: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 675: ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \ 676: ? GET_MODE_SIZE (MODE) \ 677: : int_size_in_bytes (TYPE)) \ 678: ? 4 - (CUM) / 4 : 0) 679: 680: /* A C type for declaring a variable that is used as the first argument of 681: `FUNCTION_ARG' and other related values. For some target machines, the 682: type `int' suffices and can hold the number of bytes of argument so far. 683: 684: On the ARM, this is the number of bytes of arguments scanned so far. */ 685: #define CUMULATIVE_ARGS int 686: 687: /* Initialize a variable CUM of type CUMULATIVE_ARGS 688: for a call to a function whose data type is FNTYPE. 689: For a library call, FNTYPE is 0. 690: On the ARM, the offset starts at 0. */ 691: #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \ 1.1.1.2 root 692: ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 4 : 0)) 1.1 root 693: 694: /* Update the data in CUM to advance over an argument 695: of mode MODE and data type TYPE. 696: (TYPE is null for libcalls where that information may not be available.) */ 697: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 698: (CUM) += ((MODE) != BLKmode \ 699: ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ 700: : (int_size_in_bytes (TYPE) + 3) & ~3) \ 701: 702: /* 1 if N is a possible register number for function argument passing. 703: On the ARM, r0-r3 are used to pass args. */ 704: #define FUNCTION_ARG_REGNO_P(REGNO) \ 705: ((REGNO) >= 0 && (REGNO) <= 3) 706: 707: /* Perform any actions needed for a function that is receiving a variable 708: number of arguments. CUM is as above. MODE and TYPE are the mode and type 709: of the current parameter. PRETEND_SIZE is a variable that should be set to 710: the amount of stack that must be pushed by the prolog to pretend that our 711: caller pushed it. 712: 713: Normally, this macro will push all remaining incoming registers on the 714: stack and set PRETEND_SIZE to the length of the registers pushed. 715: 716: On the ARM, PRETEND_SIZE is set in order to have the prologue push the last 717: named arg and all anonymous args onto the stack. 718: XXX I know the prologue shouldn't be pushing registers, but it is faster 719: that way. */ 720: #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ 721: { \ 722: extern int current_function_anonymous_args; \ 723: current_function_anonymous_args = 1; \ 724: if ((CUM) < 16) \ 725: (PRETEND_SIZE) = 16 - (CUM); \ 726: } 727: 728: /* Generate assembly output for the start of a function. */ 729: #define FUNCTION_PROLOGUE(STREAM, SIZE) \ 1.1.1.3 root 730: output_func_prologue ((STREAM), (SIZE)) 1.1 root 731: 732: /* Call the function profiler with a given profile label. The Acorn compiler 733: puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr'' 734: seems like a good idea to stick with cc convention. ``prof'' doesn't seem 735: to mind about this! */ 1.1.1.3 root 736: #define FUNCTION_PROFILER(STREAM,LABELNO) \ 737: { \ 1.1.1.4 ! root 738: fprintf(STREAM, "\tmov\t%sip, %slr\n", REGISTER_PREFIX, REGISTER_PREFIX); \ 1.1.1.3 root 739: fprintf(STREAM, "\tbl\tmcount\n"); \ 740: fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \ 1.1 root 741: } 742: 743: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 744: the stack pointer does not matter. The value is tested only in 745: functions that have frame pointers. 746: No definition is equivalent to always zero. 747: 748: On the ARM, the function epilogue recovers the stack pointer from the 749: frame. */ 750: #define EXIT_IGNORE_STACK 1 751: 752: /* Generate the assembly code for function exit. */ 753: #define FUNCTION_EPILOGUE(STREAM, SIZE) \ 1.1.1.3 root 754: output_func_epilogue ((STREAM), (SIZE)) 1.1 root 755: 756: /* Determine if the epilogue should be output as RTL. 757: You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1.1.1.2 root 758: #define USE_RETURN_INSN use_return_insn () 759: 760: /* Definitions for register eliminations. 761: 762: This is an array of structures. Each structure initializes one pair 763: of eliminable registers. The "from" register number is given first, 764: followed by "to". Eliminations of the same "from" register are listed 765: in order of preference. 766: 767: We have two registers that can be eliminated on the ARM. First, the 768: arg pointer register can often be eliminated in favor of the stack 769: pointer register. Secondly, the pseudo frame pointer register can always 770: be eliminated; it is replaced with either the stack or the real frame 771: pointer. */ 772: 773: #define ELIMINABLE_REGS \ 774: {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 775: {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 776: {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 777: {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} 778: 779: /* Given FROM and TO register numbers, say whether this elimination is allowed. 780: Frame pointer elimination is automatically handled. 781: 782: All eliminations are permissible. Note that ARG_POINTER_REGNUM and 1.1.1.4 ! root 783: HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame 1.1.1.2 root 784: pointer, we must eliminate FRAME_POINTER_REGNUM into 785: HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */ 786: #define CAN_ELIMINATE(FROM, TO) \ 787: (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1) 788: 789: /* Define the offset between two registers, one to be eliminated, and the other 790: its replacement, at the start of a routine. */ 791: #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 792: { \ 1.1.1.3 root 793: int volatile_func = arm_volatile_func (); \ 1.1.1.2 root 794: if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\ 795: (OFFSET) = 0; \ 796: else if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)\ 797: (OFFSET) = (get_frame_size () + 3 & ~3); \ 798: else \ 799: { \ 800: int regno; \ 801: int offset = 12; \ 1.1.1.3 root 802: int saved_hard_reg = 0; \ 1.1.1.2 root 803: \ 1.1.1.3 root 804: if (! volatile_func) \ 805: { \ 806: for (regno = 0; regno <= 10; regno++) \ 807: if (regs_ever_live[regno] && ! call_used_regs[regno]) \ 808: saved_hard_reg = 1, offset += 4; \ 809: for (regno = 16; regno <=23; regno++) \ 810: if (regs_ever_live[regno] && ! call_used_regs[regno]) \ 811: offset += 12; \ 812: } \ 1.1.1.2 root 813: if ((FROM) == FRAME_POINTER_REGNUM) \ 814: (OFFSET) = -offset; \ 815: else \ 816: { \ 1.1.1.3 root 817: if (! frame_pointer_needed) \ 1.1.1.2 root 818: offset -= 16; \ 1.1.1.3 root 819: if (! volatile_func && (regs_ever_live[14] || saved_hard_reg)) \ 1.1.1.2 root 820: offset += 4; \ 821: (OFFSET) = (get_frame_size () + 3 & ~3) + offset; \ 822: } \ 823: } \ 824: } 1.1 root 825: 826: /* Output assembler code for a block containing the constant parts 827: of a trampoline, leaving space for the variable parts. 828: 829: On the ARM, (if r8 is the static chain regnum, and remembering that 830: referencing pc adds an offset of 8) the trampoline looks like: 831: ldr r8, [pc, #0] 832: ldr pc, [pc] 833: .word static chain value 834: .word function's address */ 1.1.1.3 root 835: #define TRAMPOLINE_TEMPLATE(FILE) \ 836: { \ 1.1.1.4 ! root 837: fprintf ((FILE), "\tldr\t%sr8, [%spc, #0]\n", \ ! 838: REGISTER_PREFIX, REGISTER_PREFIX); \ ! 839: fprintf ((FILE), "\tldr\t%spc, [%spc, #0]\n", \ ! 840: REGISTER_PREFIX, REGISTER_PREFIX); \ 1.1.1.3 root 841: fprintf ((FILE), "\t.word\t0\n"); \ 842: fprintf ((FILE), "\t.word\t0\n"); \ 1.1 root 843: } 844: 845: /* Length in units of the trampoline for entering a nested function. */ 846: #define TRAMPOLINE_SIZE 16 847: 848: /* Alignment required for a trampoline in units. */ 849: #define TRAMPOLINE_ALIGN 4 850: 851: /* Emit RTL insns to initialize the variable parts of a trampoline. 852: FNADDR is an RTX for the address of the function's pure code. 853: CXT is an RTX for the static chain value for the function. */ 854: #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 855: { \ 856: emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \ 857: (CXT)); \ 858: emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \ 859: (FNADDR)); \ 860: } 861: 862: 863: /* Addressing modes, and classification of registers for them. */ 864: 865: #define HAVE_POST_INCREMENT 1 866: #define HAVE_PRE_INCREMENT 1 867: #define HAVE_POST_DECREMENT 1 868: #define HAVE_PRE_DECREMENT 1 869: 870: /* Macros to check register numbers against specific register classes. */ 871: 872: /* These assume that REGNO is a hard or pseudo reg number. 873: They give nonzero only if REGNO is a hard reg of the suitable class 874: or a pseudo reg currently allocated to a suitable hard reg. 875: Since they use reg_renumber, they are safe only once reg_renumber 876: has been allocated, which happens in local-alloc.c. 877: 878: On the ARM, don't allow the pc to be used. */ 1.1.1.2 root 879: #define REGNO_OK_FOR_BASE_P(REGNO) \ 880: ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \ 881: || (REGNO) == ARG_POINTER_REGNUM \ 882: || (unsigned) reg_renumber[(REGNO)] < 15 \ 883: || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \ 884: || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM) 885: #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1.1 root 886: REGNO_OK_FOR_BASE_P(REGNO) 887: 888: /* Maximum number of registers that can appear in a valid memory address. 1.1.1.2 root 889: Shifts in addresses can't be by a register. */ 890: 891: #define MAX_REGS_PER_ADDRESS 2 1.1 root 892: 893: /* Recognize any constant value that is a valid address. */ 894: /* XXX We can address any constant, eventually... */ 895: #if 0 896: #define CONSTANT_ADDRESS_P(X) \ 897: ( GET_CODE(X) == LABEL_REF \ 898: || GET_CODE(X) == SYMBOL_REF \ 899: || GET_CODE(X) == CONST_INT \ 900: || GET_CODE(X) == CONST ) 901: #endif 902: 1.1.1.3 root 903: #define CONSTANT_ADDRESS_P(X) \ 904: (GET_CODE (X) == SYMBOL_REF \ 905: && (CONSTANT_POOL_ADDRESS_P (X) \ 906: || (optimize > 0 && SYMBOL_REF_FLAG (X)))) 1.1 root 907: 908: /* Nonzero if the constant value X is a legitimate general operand. 909: It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. 910: 911: On the ARM, allow any integer (invalid ones are removed later by insn 912: patterns), nice doubles and symbol_refs which refer to the function's 913: constant pool XXX. */ 914: #define LEGITIMATE_CONSTANT_P(X) \ 915: (GET_CODE (X) == CONST_INT \ 916: || (GET_CODE (X) == CONST_DOUBLE \ 1.1.1.2 root 917: && (const_double_rtx_ok_for_fpu (X) \ 918: || neg_const_double_rtx_ok_for_fpu (X))) \ 919: || CONSTANT_ADDRESS_P (X)) 920: 921: /* Symbols in the text segment can be accessed without indirecting via the 922: constant pool; it may take an extra binary operation, but this is still 1.1.1.3 root 923: faster than indirecting via memory. Don't do this when not optimizing, 924: since we won't be calculating al of the offsets necessary to do this 925: simplification. */ 1.1.1.2 root 926: 927: #define ENCODE_SECTION_INFO(decl) \ 928: { \ 1.1.1.3 root 929: if (optimize > 0 && TREE_CONSTANT (decl) \ 1.1.1.2 root 930: && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \ 931: { \ 932: rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \ 933: ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \ 934: SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \ 935: } \ 936: } 1.1 root 937: 938: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 939: and check its validity for a certain class. 940: We have two alternate definitions for each of them. 941: The usual definition accepts all pseudo regs; the other rejects 942: them unless they have been allocated suitable hard regs. 943: The symbol REG_OK_STRICT causes the latter definition to be used. */ 944: #ifndef REG_OK_STRICT 1.1.1.2 root 945: 1.1 root 946: /* Nonzero if X is a hard reg that can be used as a base reg 947: or if it is a pseudo reg. */ 1.1.1.2 root 948: #define REG_OK_FOR_BASE_P(X) \ 949: (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 950: || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM) 951: 1.1 root 952: /* Nonzero if X is a hard reg that can be used as an index 953: or if it is a pseudo reg. */ 954: #define REG_OK_FOR_INDEX_P(X) \ 955: REG_OK_FOR_BASE_P(X) 1.1.1.2 root 956: 957: #define REG_OK_FOR_PRE_POST_P(X) \ 958: (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 959: || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM) 960: 1.1 root 961: #else 1.1.1.2 root 962: 1.1 root 963: /* Nonzero if X is a hard reg that can be used as a base reg. */ 964: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1.1.1.2 root 965: 1.1 root 966: /* Nonzero if X is a hard reg that can be used as an index. */ 967: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1.1.1.2 root 968: 969: #define REG_OK_FOR_PRE_POST_P(X) \ 970: (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \ 971: || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \ 972: || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \ 973: || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM) 974: 1.1 root 975: #endif 976: 977: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 978: that is a valid memory address for an instruction. 979: The MODE argument is the machine mode for the MEM expression 980: that wants to use this address. 981: 982: The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ 983: #define BASE_REGISTER_RTX_P(X) \ 984: (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) 985: 986: #define INDEX_REGISTER_RTX_P(X) \ 987: (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) 988: 989: /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs 990: used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can 991: only be small constants. */ 1.1.1.2 root 992: #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \ 1.1 root 993: do \ 994: { \ 1.1.1.3 root 995: HOST_WIDE_INT range; \ 996: enum rtx_code code = GET_CODE (INDEX); \ 1.1 root 997: \ 998: if (GET_MODE_CLASS (MODE) == MODE_FLOAT) \ 1.1.1.2 root 999: { \ 1000: if (code == CONST_INT && INTVAL (INDEX) < 1024 \ 1001: && INTVAL (INDEX) > -1024 \ 1002: && (INTVAL (INDEX) & 3) == 0) \ 1003: goto LABEL; \ 1004: } \ 1.1 root 1005: else \ 1006: { \ 1.1.1.2 root 1007: if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \ 1.1 root 1008: goto LABEL; \ 1.1.1.2 root 1009: if (GET_MODE_SIZE (MODE) <= 4 && code == MULT) \ 1.1 root 1010: { \ 1011: rtx xiop0 = XEXP (INDEX, 0); \ 1012: rtx xiop1 = XEXP (INDEX, 1); \ 1013: if (INDEX_REGISTER_RTX_P (xiop0) \ 1014: && power_of_two_operand (xiop1, SImode)) \ 1015: goto LABEL; \ 1016: if (INDEX_REGISTER_RTX_P (xiop1) \ 1017: && power_of_two_operand (xiop0, SImode)) \ 1018: goto LABEL; \ 1019: } \ 1.1.1.2 root 1020: if (GET_MODE_SIZE (MODE) <= 4 \ 1.1.1.3 root 1021: && (code == LSHIFTRT || code == ASHIFTRT \ 1.1.1.2 root 1022: || code == ASHIFT || code == ROTATERT)) \ 1023: { \ 1024: rtx op = XEXP (INDEX, 1); \ 1025: if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \ 1026: && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \ 1027: && INTVAL (op) <= 31) \ 1028: goto LABEL; \ 1029: } \ 1030: range = (MODE) == HImode ? 4095 : 4096; \ 1031: if (code == CONST_INT && INTVAL (INDEX) < range \ 1032: && INTVAL (INDEX) > -range) \ 1033: goto LABEL; \ 1.1 root 1034: } \ 1035: } while (0) 1036: 1037: /* Jump to LABEL if X is a valid address RTX. This must also take 1038: REG_OK_STRICT into account when deciding about valid registers, but it uses 1039: the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX, 1040: INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool. 1.1.1.2 root 1041: Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol 1042: refs must be forced though a static cell to ensure addressability. */ 1.1 root 1043: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ 1044: { \ 1045: if (BASE_REGISTER_RTX_P (X)) \ 1046: goto LABEL; \ 1047: else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \ 1048: && GET_CODE (XEXP (X, 0)) == REG \ 1049: && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \ 1050: goto LABEL; \ 1051: else if ((MODE) == TImode) \ 1052: ; \ 1053: else if (GET_CODE (X) == PLUS) \ 1054: { \ 1055: rtx xop0 = XEXP(X,0); \ 1056: rtx xop1 = XEXP(X,1); \ 1057: \ 1058: if (BASE_REGISTER_RTX_P (xop0)) \ 1059: GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \ 1060: else if (BASE_REGISTER_RTX_P (xop1)) \ 1061: GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \ 1062: } \ 1063: else if (GET_CODE (X) == MINUS) \ 1064: { \ 1065: rtx xop0 = XEXP (X,0); \ 1066: rtx xop1 = XEXP (X,1); \ 1067: \ 1068: if (BASE_REGISTER_RTX_P (xop0)) \ 1069: GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \ 1070: } \ 1071: else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \ 1072: && GET_CODE (X) == SYMBOL_REF \ 1073: && CONSTANT_POOL_ADDRESS_P (X)) \ 1074: goto LABEL; \ 1075: else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \ 1076: && GET_CODE (XEXP (X, 0)) == REG \ 1077: && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \ 1078: goto LABEL; \ 1079: } 1080: 1081: /* Try machine-dependent ways of modifying an illegitimate address 1082: to be legitimate. If we find one, return the new, valid address. 1083: This macro is used in only one place: `memory_address' in explow.c. 1084: 1085: OLDX is the address as it was before break_out_memory_refs was called. 1086: In some cases it is useful to look at this to decide what needs to be done. 1087: 1088: MODE and WIN are passed so that this macro can use 1089: GO_IF_LEGITIMATE_ADDRESS. 1090: 1091: It is always safe for this macro to do nothing. It exists to recognize 1092: opportunities to optimize the output. 1093: 1094: On the ARM, try to convert [REG, #BIGCONST] 1095: into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST], 1096: where VALIDCONST == 0 in case of TImode. */ 1.1.1.3 root 1097: #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 1098: { \ 1099: if (GET_CODE (X) == PLUS) \ 1100: { \ 1101: rtx xop0 = XEXP (X, 0); \ 1102: rtx xop1 = XEXP (X, 1); \ 1103: \ 1104: if (CONSTANT_P (xop0) && ! LEGITIMATE_CONSTANT_P (xop0)) \ 1105: xop0 = force_reg (SImode, xop0); \ 1106: if (CONSTANT_P (xop1) && ! LEGITIMATE_CONSTANT_P (xop1)) \ 1107: xop1 = force_reg (SImode, xop1); \ 1108: if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \ 1109: { \ 1110: HOST_WIDE_INT n, low_n; \ 1111: rtx base_reg, val; \ 1112: n = INTVAL (xop1); \ 1113: \ 1114: if (MODE == DImode) \ 1115: { \ 1116: low_n = n & 0x0f; \ 1117: n &= ~0x0f; \ 1118: if (low_n > 4) \ 1119: { \ 1120: n += 16; \ 1121: low_n -= 16; \ 1122: } \ 1123: } \ 1124: else \ 1125: { \ 1126: low_n = ((MODE) == TImode ? 0 \ 1127: : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \ 1128: n -= low_n; \ 1129: } \ 1130: base_reg = gen_reg_rtx (SImode); \ 1131: val = force_operand (gen_rtx (PLUS, SImode, xop0, \ 1132: GEN_INT (n)), NULL_RTX); \ 1133: emit_move_insn (base_reg, val); \ 1134: (X) = (low_n == 0 ? base_reg \ 1135: : gen_rtx (PLUS, SImode, base_reg, GEN_INT (low_n))); \ 1136: } \ 1137: else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \ 1138: (X) = gen_rtx (PLUS, SImode, xop0, xop1); \ 1139: } \ 1140: else if (GET_CODE (X) == MINUS) \ 1141: { \ 1142: rtx xop0 = XEXP (X, 0); \ 1143: rtx xop1 = XEXP (X, 1); \ 1144: \ 1145: if (CONSTANT_P (xop0)) \ 1146: xop0 = force_reg (SImode, xop0); \ 1147: if (CONSTANT_P (xop1) && ! LEGITIMATE_CONSTANT_P (xop1)) \ 1148: xop1 = force_reg (SImode, xop1); \ 1149: if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \ 1150: (X) = gen_rtx (MINUS, SImode, xop0, xop1); \ 1151: } \ 1152: if (memory_address_p (MODE, X)) \ 1153: goto WIN; \ 1.1 root 1154: } 1155: 1.1.1.3 root 1156: 1.1 root 1157: /* Go to LABEL if ADDR (a legitimate address expression) 1158: has an effect that depends on the machine mode it is used for. */ 1159: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 1160: { \ 1161: if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \ 1162: || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \ 1163: goto LABEL; \ 1164: } 1165: 1166: /* Specify the machine mode that this machine uses 1167: for the index in the tablejump instruction. */ 1168: #define CASE_VECTOR_MODE SImode 1169: 1170: /* Define this if the tablejump instruction expects the table 1171: to contain offsets from the address of the table. 1172: Do not define this if the table should contain absolute addresses. */ 1173: /* #define CASE_VECTOR_PC_RELATIVE */ 1174: 1175: /* Specify the tree operation to be used to convert reals to integers. */ 1176: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR 1177: 1178: /* This is the kind of divide that is easiest to do in the general case. */ 1179: #define EASY_DIV_EXPR TRUNC_DIV_EXPR 1180: 1.1.1.2 root 1181: /* signed 'char' is most compatible, but RISC OS wants it unsigned. 1182: unsigned is probably best, but may break some code. */ 1183: #ifndef DEFAULT_SIGNED_CHAR 1.1.1.3 root 1184: #define DEFAULT_SIGNED_CHAR 0 1.1 root 1185: #endif 1186: 1187: /* Don't cse the address of the function being compiled. */ 1188: #define NO_RECURSIVE_FUNCTION_CSE 1 1189: 1190: /* Max number of bytes we can move from memory to memory 1191: in one reasonably fast instruction. */ 1192: #define MOVE_MAX 4 1193: 1.1.1.2 root 1194: /* Define if operations between registers always perform the operation 1195: on the full register even if a narrower mode is specified. */ 1196: #define WORD_REGISTER_OPERATIONS 1197: 1198: /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1199: will either zero-extend or sign-extend. The value of this macro should 1200: be the code that says which one of the two operations is implicitly 1201: done, NIL if none. */ 1.1.1.3 root 1202: #define LOAD_EXTEND_OP(MODE) \ 1203: ((MODE) == QImode ? ZERO_EXTEND \ 1204: : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)) 1.1 root 1205: 1206: /* Define this if zero-extension is slow (more than one real instruction). 1207: On the ARM, it is more than one instruction only if not fetching from 1208: memory. */ 1209: /* #define SLOW_ZERO_EXTEND */ 1210: 1211: /* Nonzero if access to memory by bytes is slow and undesirable. */ 1212: #define SLOW_BYTE_ACCESS 0 1213: 1214: /* Immediate shift counts are truncated by the output routines (or was it 1215: the assembler?). Shift counts in a register are truncated by ARM. Note 1216: that the native compiler puts too large (> 32) immediate shift counts 1217: into a register and shifts by the register, letting the ARM decide what 1218: to do instead of doing that itself. */ 1.1.1.2 root 1219: /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 1220: code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 1221: On the arm, Y in a register is used modulo 256 for the shift. Only for 1222: rotates is modulo 32 used. */ 1223: /* #define SHIFT_COUNT_TRUNCATED 1 */ 1.1 root 1224: 1225: /* XX This is not true, is it? */ 1226: /* All integers have the same format so truncation is easy. */ 1227: #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1 1228: 1229: /* Calling from registers is a massive pain. */ 1230: #define NO_FUNCTION_CSE 1 1231: 1232: /* Chars and shorts should be passed as ints. */ 1233: #define PROMOTE_PROTOTYPES 1 1234: 1235: /* The machine modes of pointers and functions */ 1236: #define Pmode SImode 1237: #define FUNCTION_MODE Pmode 1238: 1239: /* The structure type of the machine dependent info field of insns 1240: No uses for this yet. */ 1241: /* #define INSN_MACHINE_INFO struct machine_info */ 1242: 1243: /* The relative costs of various types of constants. Note that cse.c defines 1244: REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */ 1.1.1.2 root 1245: #define CONST_COSTS(RTX, CODE, OUTER_CODE) \ 1246: case CONST_INT: \ 1247: if (const_ok_for_arm (INTVAL (RTX))) \ 1248: return (OUTER_CODE) == SET ? 2 : -1; \ 1249: else if (OUTER_CODE == AND \ 1250: && const_ok_for_arm (~INTVAL (RTX))) \ 1251: return -1; \ 1252: else if ((OUTER_CODE == COMPARE \ 1253: || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \ 1254: && const_ok_for_arm (-INTVAL (RTX))) \ 1255: return -1; \ 1256: else \ 1257: return 5; \ 1258: case CONST: \ 1259: case LABEL_REF: \ 1260: case SYMBOL_REF: \ 1261: return 6; \ 1262: case CONST_DOUBLE: \ 1263: if (const_double_rtx_ok_for_fpu (RTX)) \ 1264: return (OUTER_CODE) == SET ? 2 : -1; \ 1265: else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \ 1266: && neg_const_double_rtx_ok_for_fpu (RTX)) \ 1267: return -1; \ 1268: return(7); 1269: 1.1.1.3 root 1270: #define ARM_FRAME_RTX(X) \ 1271: ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 1272: || (X) == arg_pointer_rtx) 1273: 1.1.1.2 root 1274: #define RTX_COSTS(X,CODE,OUTER_CODE) \ 1.1.1.3 root 1275: default: \ 1276: return arm_rtx_costs (X, CODE, OUTER_CODE); 1.1.1.2 root 1277: 1278: /* Moves to and from memory are quite expensive */ 1279: #define MEMORY_MOVE_COST(MODE) 10 1280: 1.1.1.3 root 1281: /* All address computations that can be done are free, but rtx cost returns 1.1.1.4 ! root 1282: the same for practically all of them. So we weight the different types 1.1.1.3 root 1283: of address here in the order (most pref first): 1284: PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ 1285: #define ADDRESS_COST(X) \ 1286: (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \ 1287: || GET_CODE (X) == SYMBOL_REF) \ 1288: ? 0 \ 1289: : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \ 1290: || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \ 1291: ? 10 \ 1292: : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \ 1293: ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \ 1294: : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \ 1295: || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \ 1296: || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \ 1297: || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \ 1298: ? 1 : 0)) \ 1299: : 4))))) 1300: 1301: 1.1.1.2 root 1302: 1303: /* Try to generate sequences that don't involve branches, we can then use 1304: conditional instructions */ 1305: #define BRANCH_COST 4 1.1 root 1306: 1.1.1.2 root 1307: /* Condition code information. */ 1308: /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 1309: return the mode to be used for the comparison. 1.1.1.4 ! root 1310: CCFPEmode should be used with floating inequalities, 1.1.1.2 root 1311: CCFPmode should be used with floating equalities. 1.1.1.4 ! root 1312: CC_NOOVmode should be used with SImode integer equalities. 1.1.1.2 root 1313: CCmode should be used otherwise. */ 1314: 1315: #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode 1316: 1317: #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE" 1318: 1319: #define SELECT_CC_MODE(OP,X,Y) \ 1320: (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ 1321: ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \ 1322: : ((GET_MODE (X) == SImode) \ 1323: && ((OP) == EQ || (OP) == NE) \ 1324: && (GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \ 1325: || GET_CODE (X) == AND || GET_CODE (X) == IOR \ 1326: || GET_CODE (X) == XOR || GET_CODE (X) == MULT \ 1327: || GET_CODE (X) == NOT || GET_CODE (X) == NEG \ 1.1.1.3 root 1328: || GET_CODE (X) == LSHIFTRT \ 1.1.1.2 root 1329: || GET_CODE (X) == ASHIFT || GET_CODE (X) == ASHIFTRT \ 1330: || GET_CODE (X) == ROTATERT || GET_CODE (X) == ZERO_EXTRACT) \ 1331: ? CC_NOOVmode \ 1332: : GET_MODE (X) == QImode ? CC_NOOVmode : CCmode)) 1333: 1.1.1.3 root 1334: #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) 1335: 1.1.1.2 root 1336: #define STORE_FLAG_VALUE 1 1337: 1338: /* Define the information needed to generate branch insns. This is 1339: stored from the compare operation. Note that we can't use "rtx" here 1340: since it hasn't been defined! */ 1341: 1342: extern struct rtx_def *arm_compare_op0, *arm_compare_op1; 1343: extern int arm_compare_fp; 1344: 1345: /* Define the codes that are matched by predicates in arm.c */ 1346: #define PREDICATE_CODES \ 1347: {"s_register_operand", {SUBREG, REG}}, \ 1348: {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \ 1349: {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \ 1350: {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \ 1351: {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \ 1352: {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \ 1353: {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \ 1354: {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \ 1.1.1.3 root 1355: {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \ 1.1.1.2 root 1356: {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \ 1.1.1.4 ! root 1357: {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \ 1.1.1.2 root 1358: {"load_multiple_operation", {PARALLEL}}, \ 1359: {"store_multiple_operation", {PARALLEL}}, \ 1360: {"equality_operator", {EQ, NE}}, \ 1361: {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \ 1362: {"const_shift_operand", {CONST_INT}}, \ 1363: {"index_operand", {SUBREG, REG, CONST_INT}}, \ 1.1.1.3 root 1364: {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \ 1365: {"multi_register_push", {PARALLEL}}, \ 1366: {"cc_register", {REG}}, \ 1367: {"reversible_cc_register", {REG}}, 1.1 root 1368: 1369: 1370: /* Assembler output control */ 1371: 1.1.1.2 root 1372: #ifndef ARM_OS_NAME 1373: #define ARM_OS_NAME "(generic)" 1374: #endif 1375: 1.1 root 1376: /* The text to go at the start of the assembler file */ 1.1.1.3 root 1377: #define ASM_FILE_START(STREAM) \ 1378: { \ 1379: extern char *version_string; \ 1.1.1.4 ! root 1380: fprintf (STREAM,"%s Generated by gcc %s for ARM/%s\n", \ ! 1381: ASM_COMMENT_START, version_string, ARM_OS_NAME); \ ! 1382: fprintf (STREAM,"%srfp\t.req\t%sr9\n", REGISTER_PREFIX, REGISTER_PREFIX); \ ! 1383: fprintf (STREAM,"%ssl\t.req\t%sr10\n", REGISTER_PREFIX, REGISTER_PREFIX); \ ! 1384: fprintf (STREAM,"%sfp\t.req\t%sr11\n", REGISTER_PREFIX, REGISTER_PREFIX); \ ! 1385: fprintf (STREAM,"%sip\t.req\t%sr12\n", REGISTER_PREFIX, REGISTER_PREFIX); \ ! 1386: fprintf (STREAM,"%ssp\t.req\t%sr13\n", REGISTER_PREFIX, REGISTER_PREFIX); \ ! 1387: fprintf (STREAM,"%slr\t.req\t%sr14\n", REGISTER_PREFIX, REGISTER_PREFIX); \ ! 1388: fprintf (STREAM,"%spc\t.req\t%sr15\n", REGISTER_PREFIX, REGISTER_PREFIX); \ 1.1 root 1389: } 1390: 1391: #define ASM_APP_ON "" 1392: #define ASM_APP_OFF "" 1393: 1394: /* Switch to the text or data segment. */ 1395: #define TEXT_SECTION_ASM_OP ".text" 1396: #define DATA_SECTION_ASM_OP ".data" 1397: 1.1.1.4 ! root 1398: #define REGISTER_PREFIX "" ! 1399: #define USER_LABEL_PREFIX "_" ! 1400: #define LOCAL_LABEL_PREFIX "" ! 1401: 1.1.1.3 root 1402: /* The assembler's names for the registers. */ 1403: #ifndef REGISTER_NAMES 1.1 root 1404: #define REGISTER_NAMES \ 1405: { \ 1406: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 1.1.1.3 root 1407: "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc", \ 1.1.1.2 root 1408: "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ 1409: "cc", "sfp", "afp" \ 1.1 root 1410: } 1.1.1.3 root 1411: #endif 1412: 1413: #ifndef ADDITIONAL_REGISTER_NAMES 1414: #define ADDITIONAL_REGISTER_NAMES \ 1415: { \ 1416: {"a1", 0}, \ 1417: {"a2", 1}, \ 1418: {"a3", 2}, \ 1419: {"a4", 3}, \ 1420: {"v1", 4}, \ 1421: {"v2", 5}, \ 1422: {"v3", 6}, \ 1423: {"v4", 7}, \ 1424: {"v5", 8}, \ 1425: {"v6", 9}, \ 1426: {"rfp", 9}, /* Gcc used to call it this */ \ 1427: {"sb", 9}, \ 1428: {"v7", 10}, \ 1429: {"r10", 10}, \ 1430: {"r11", 11}, /* fp */ \ 1431: {"r12", 12}, /* ip */ \ 1432: {"r13", 13}, /* sp */ \ 1433: {"r14", 14}, /* lr */ \ 1434: {"r15", 15} /* pc */ \ 1435: } 1436: #endif 1.1 root 1437: 1.1.1.2 root 1438: /* Arm Assembler barfs on dollars */ 1439: #define DOLLARS_IN_IDENTIFIERS 0 1440: 1441: #define NO_DOLLAR_IN_LABEL 1442: 1.1 root 1443: /* DBX register number for a given compiler register number */ 1444: #define DBX_REGISTER_NUMBER(REGNO) (REGNO) 1445: 1.1.1.2 root 1446: /* Generate DBX debugging information. riscix.h will undefine this because 1447: the native assembler does not support stabs. */ 1.1 root 1448: #define DBX_DEBUGGING_INFO 1 1449: 1450: /* Acorn dbx moans about continuation chars, so don't use any. */ 1.1.1.3 root 1451: #ifndef DBX_CONTIN_LENGTH 1.1 root 1452: #define DBX_CONTIN_LENGTH 0 1.1.1.3 root 1453: #endif 1.1 root 1454: 1.1.1.2 root 1455: /* Output a source filename for the debugger. RISCiX dbx insists that the 1456: ``desc'' field is set to compiler version number >= 315 (sic). */ 1457: #define DBX_OUTPUT_MAIN_SOURCE_FILENAME(STREAM,NAME) \ 1458: do { \ 1459: fprintf (STREAM, ".stabs \"%s\",%d,0,315,%s\n", (NAME), N_SO, \ 1460: <ext_label_name[1]); \ 1461: text_section (); \ 1462: ASM_OUTPUT_INTERNAL_LABEL (STREAM, "Ltext", 0); \ 1463: } while (0) 1464: 1.1 root 1465: /* Output a label definition. */ 1466: #define ASM_OUTPUT_LABEL(STREAM,NAME) \ 1467: arm_asm_output_label ((STREAM), (NAME)) 1468: 1469: /* Output a function label definition. */ 1470: #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \ 1471: ASM_OUTPUT_LABEL(STREAM, NAME) 1472: 1473: /* Output a globalising directive for a label. */ 1474: #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \ 1475: (fprintf (STREAM, "\t.global\t"), \ 1476: assemble_name (STREAM, NAME), \ 1477: fputc ('\n',STREAM)) \ 1478: 1479: /* Output a reference to a label. */ 1480: #define ASM_OUTPUT_LABELREF(STREAM,NAME) \ 1.1.1.4 ! root 1481: fprintf (STREAM, "%s%s", USER_LABEL_PREFIX, NAME) 1.1 root 1482: 1483: /* Make an internal label into a string. */ 1484: #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \ 1485: sprintf (STRING, "*%s%d", PREFIX, NUM) 1486: 1487: /* Output an internal label definition. */ 1488: #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \ 1489: do \ 1490: { \ 1491: char *s = (char *) alloca (11 + strlen (PREFIX)); \ 1492: extern int arm_target_label, arm_ccfsm_state; \ 1.1.1.2 root 1493: extern rtx arm_target_insn; \ 1.1 root 1494: \ 1.1.1.2 root 1495: if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \ 1496: && !strcmp (PREFIX, "L")) \ 1497: { \ 1498: arm_ccfsm_state = 0; \ 1499: arm_target_insn = NULL; \ 1500: } \ 1501: strcpy (s, "*"); \ 1502: sprintf (&s[strlen (s)], "%s%d", (PREFIX), (NUM)); \ 1503: arm_asm_output_label (STREAM, s); \ 1.1 root 1504: } while (0) 1505: 1506: /* Nothing special is done about jump tables */ 1507: /* #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) */ 1508: /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */ 1509: 1510: /* Construct a private name. */ 1511: #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \ 1512: ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \ 1513: sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER))) 1514: 1515: /* Output a push or a pop instruction (only used when profiling). */ 1.1.1.4 ! root 1516: #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ ! 1517: fprintf(STREAM,"\tstmfd\t%ssp!,{%s%s}\n", \ ! 1518: REGISTER_PREFIX, REGISTER_PREFIX, reg_names[REGNO]) ! 1519: ! 1520: #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ ! 1521: fprintf(STREAM,"\tldmfd\t%ssp!,{%s%s}\n", \ ! 1522: REGISTER_PREFIX, REGISTER_PREFIX, reg_names[REGNO]) 1.1 root 1523: 1524: /* Output a relative address. Not needed since jump tables are absolute 1525: but we must define it anyway. */ 1526: #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \ 1527: fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM) 1528: 1529: /* Output an element of a dispatch table. */ 1530: #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ 1.1.1.3 root 1531: fprintf (STREAM, "\t.word\tL%d\n", VALUE) 1.1 root 1532: 1.1.1.2 root 1533: /* Output various types of constants. For real numbers we output hex, with 1534: a comment containing the "human" value, this allows us to pass NaN's which 1535: the riscix assembler doesn't understand (it also makes cross-assembling 1536: less likely to fail). */ 1537: 1538: #define ASM_OUTPUT_LONG_DOUBLE(STREAM,VALUE) \ 1539: do { char dstr[30]; \ 1540: long l[3]; \ 1541: arm_increase_location (12); \ 1542: REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \ 1543: REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ 1544: if (sizeof (int) == sizeof (long)) \ 1.1.1.4 ! root 1545: fprintf (STREAM, "\t.long 0x%x,0x%x,0x%x\t%s long double %s\n", \ ! 1546: l[2], l[1], l[0], ASM_COMMENT_START, dstr); \ 1.1.1.2 root 1547: else \ 1.1.1.4 ! root 1548: fprintf (STREAM, "\t.long 0x%lx,0x%lx,0x%lx\t%s long double %s\n",\ ! 1549: l[0], l[1], l[2], ASM_COMMENT_START, dstr); \ 1.1.1.2 root 1550: } while (0) 1551: 1552: 1553: #define ASM_OUTPUT_DOUBLE(STREAM, VALUE) \ 1554: do { char dstr[30]; \ 1555: long l[2]; \ 1556: arm_increase_location (8); \ 1557: REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \ 1558: REAL_VALUE_TO_DECIMAL (VALUE, "%.14g", dstr); \ 1559: if (sizeof (int) == sizeof (long)) \ 1.1.1.4 ! root 1560: fprintf (STREAM, "\t.long 0x%x, 0x%x\t%s double %s\n", l[0], \ ! 1561: l[1], ASM_COMMENT_START, dstr); \ 1.1.1.2 root 1562: else \ 1.1.1.4 ! root 1563: fprintf (STREAM, "\t.long 0x%lx, 0x%lx\t%s double %s\n", l[0], \ ! 1564: l[1], ASM_COMMENT_START, dstr); \ 1.1.1.2 root 1565: } while (0) 1566: 1567: #define ASM_OUTPUT_FLOAT(STREAM, VALUE) \ 1568: do { char dstr[30]; \ 1569: long l; \ 1570: arm_increase_location (4); \ 1571: REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ 1572: REAL_VALUE_TO_DECIMAL (VALUE, "%.7g", dstr); \ 1573: if (sizeof (int) == sizeof (long)) \ 1.1.1.4 ! root 1574: fprintf (STREAM, "\t.word 0x%x\t%s float %s\n", l, \ ! 1575: ASM_COMMENT_START, dstr); \ 1.1.1.2 root 1576: else \ 1.1.1.4 ! root 1577: fprintf (STREAM, "\t.word 0x%lx\t%s float %s\n", l, \ ! 1578: ASM_COMMENT_START, dstr); \ 1.1.1.2 root 1579: } while (0); 1580: 1581: #define ASM_OUTPUT_INT(STREAM, EXP) \ 1582: (fprintf (STREAM, "\t.word\t"), \ 1583: output_addr_const (STREAM, (EXP)), \ 1584: arm_increase_location (4), \ 1.1 root 1585: fputc ('\n', STREAM)) 1586: 1587: #define ASM_OUTPUT_SHORT(STREAM, EXP) \ 1588: (fprintf (STREAM, "\t.short\t"), \ 1589: output_addr_const (STREAM, (EXP)), \ 1590: arm_increase_location (2), \ 1591: fputc ('\n', STREAM)) 1592: 1593: #define ASM_OUTPUT_CHAR(STREAM, EXP) \ 1594: (fprintf (STREAM, "\t.byte\t"), \ 1595: output_addr_const (STREAM, (EXP)), \ 1596: arm_increase_location (1), \ 1597: fputc ('\n', STREAM)) 1598: 1599: #define ASM_OUTPUT_BYTE(STREAM, VALUE) \ 1600: (fprintf (STREAM, "\t.byte\t%d\n", VALUE), \ 1601: arm_increase_location (1)) 1602: 1603: #define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) \ 1.1.1.2 root 1604: output_ascii_pseudo_op ((STREAM), (unsigned char *)(PTR), (LEN)) 1.1 root 1605: 1606: /* Output a gap. In fact we fill it with nulls. */ 1607: #define ASM_OUTPUT_SKIP(STREAM, NBYTES) \ 1608: (arm_increase_location (NBYTES), \ 1609: fprintf (STREAM, "\t.space\t%d\n", NBYTES)) 1610: 1611: /* Align output to a power of two. Horrible /bin/as. */ 1612: #define ASM_OUTPUT_ALIGN(STREAM, POWER) \ 1613: do \ 1614: { \ 1615: register int amount = 1 << (POWER); \ 1616: extern int arm_text_location; \ 1617: \ 1618: if (amount == 2) \ 1619: fprintf (STREAM, "\t.even\n"); \ 1620: else \ 1621: fprintf (STREAM, "\t.align\t%d\n", amount - 4); \ 1622: \ 1623: if (in_text_section ()) \ 1624: arm_text_location = ((arm_text_location + amount - 1) \ 1625: & ~(amount - 1)); \ 1626: } while (0) 1627: 1628: /* Output a common block */ 1.1.1.3 root 1629: #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \ 1630: (fprintf (STREAM, "\t.comm\t"), \ 1631: assemble_name ((STREAM), (NAME)), \ 1.1.1.4 ! root 1632: fprintf(STREAM, ", %d\t%s %d\n", ROUNDED, ASM_COMMENT_START, SIZE)) 1.1 root 1633: 1634: /* Output a local common block. /bin/as can't do this, so hack a `.space' into 1635: the bss segment. Note that this is *bad* practice. */ 1636: #define ASM_OUTPUT_LOCAL(STREAM,NAME,SIZE,ROUNDED) \ 1637: output_lcomm_directive (STREAM, NAME, SIZE, ROUNDED) 1638: 1639: /* Output a source line for the debugger. */ 1640: /* #define ASM_OUTPUT_SOURCE_LINE(STREAM,LINE) */ 1641: 1642: /* Output a #ident directive. */ 1643: #define ASM_OUTPUT_IDENT(STREAM,STRING) \ 1644: fprintf (STREAM,"- - - ident %s\n",STRING) 1645: 1646: /* The assembler's parentheses characters. */ 1647: #define ASM_OPEN_PAREN "(" 1648: #define ASM_CLOSE_PAREN ")" 1649: 1650: /* Target characters. */ 1651: #define TARGET_BELL 007 1652: #define TARGET_BS 010 1653: #define TARGET_TAB 011 1654: #define TARGET_NEWLINE 012 1655: #define TARGET_VT 013 1656: #define TARGET_FF 014 1657: #define TARGET_CR 015 1658: 1659: /* Only perform branch elimination (by making instructions conditional) if 1660: we're optimising. Otherwise it's of no use anyway. */ 1661: #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 1662: if (optimize) \ 1663: final_prescan_insn (INSN, OPVEC, NOPERANDS) 1664: 1.1.1.4 ! root 1665: #ifndef ASM_COMMENT_START ! 1666: #define ASM_COMMENT_START "@" 1.1.1.3 root 1667: #endif 1668: 1669: #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 1670: ((CODE) == '?' || (CODE) == '|' || (CODE) == '@') 1671: /* Output an operand of an instruction. */ 1.1 root 1672: #define PRINT_OPERAND(STREAM, X, CODE) \ 1.1.1.3 root 1673: arm_print_operand (STREAM, X, CODE) 1674: 1675: #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 1676: (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \ 1677: : (((x) & (unsigned HOST_WIDE_INT) 0xffffffff) | \ 1678: (((x) & (unsigned HOST_WIDE_INT) 0x80000000) \ 1679: ? ((~ (HOST_WIDE_INT) 0) \ 1680: & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 1681: : 0)))) 1.1 root 1682: 1683: /* Output the address of an operand. */ 1684: #define PRINT_OPERAND_ADDRESS(STREAM,X) \ 1685: { \ 1686: int is_minus = GET_CODE (X) == MINUS; \ 1687: \ 1688: if (GET_CODE (X) == REG) \ 1.1.1.4 ! root 1689: fprintf (STREAM, "[%s%s, #0]", REGISTER_PREFIX, \ 1.1.1.3 root 1690: reg_names[REGNO (X)]); \ 1.1 root 1691: else if (GET_CODE (X) == PLUS || is_minus) \ 1692: { \ 1693: rtx base = XEXP (X, 0); \ 1694: rtx index = XEXP (X, 1); \ 1695: char *base_reg_name; \ 1.1.1.3 root 1696: HOST_WIDE_INT offset = 0; \ 1.1 root 1697: if (GET_CODE (base) != REG) \ 1698: { \ 1699: /* Ensure that BASE is a register (one of them must be). */ \ 1700: rtx temp = base; \ 1701: base = index; \ 1702: index = temp; \ 1703: } \ 1704: base_reg_name = reg_names[REGNO (base)]; \ 1705: switch (GET_CODE (index)) \ 1706: { \ 1707: case CONST_INT: \ 1708: offset = INTVAL (index); \ 1709: if (is_minus) \ 1710: offset = -offset; \ 1.1.1.4 ! root 1711: fprintf (STREAM, "[%s%s, #%d]", REGISTER_PREFIX, \ 1.1.1.3 root 1712: base_reg_name, offset); \ 1.1 root 1713: break; \ 1714: \ 1715: case REG: \ 1.1.1.4 ! root 1716: fprintf (STREAM, "[%s%s, %s%s%s]", REGISTER_PREFIX, \ 1.1.1.3 root 1717: base_reg_name, is_minus ? "-" : "", \ 1.1.1.4 ! root 1718: REGISTER_PREFIX, reg_names[REGNO (index)] ); \ 1.1 root 1719: break; \ 1720: \ 1721: case MULT: \ 1.1.1.2 root 1722: case ASHIFTRT: \ 1723: case LSHIFTRT: \ 1724: case ASHIFT: \ 1725: case ROTATERT: \ 1726: { \ 1.1.1.4 ! root 1727: fprintf (STREAM, "[%s%s, %s%s%s", REGISTER_PREFIX, \ ! 1728: base_reg_name, is_minus ? "-" : "", REGISTER_PREFIX,\ 1.1.1.3 root 1729: reg_names[REGNO (XEXP (index, 0))]); \ 1730: arm_print_operand (STREAM, index, 'S'); \ 1731: fputs ("]", STREAM); \ 1.1.1.2 root 1732: break; \ 1733: } \ 1.1 root 1734: \ 1735: default: \ 1736: abort(); \ 1737: } \ 1738: } \ 1739: else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \ 1740: || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \ 1741: { \ 1742: extern int output_memory_reference_mode; \ 1743: \ 1744: if (GET_CODE (XEXP (X, 0)) != REG) \ 1745: abort (); \ 1746: \ 1747: if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ 1.1.1.4 ! root 1748: fprintf (STREAM, "[%s%s, #%s%d]!", REGISTER_PREFIX, \ 1.1.1.3 root 1749: reg_names[REGNO (XEXP (X, 0))], \ 1.1 root 1750: GET_CODE (X) == PRE_DEC ? "-" : "", \ 1751: GET_MODE_SIZE (output_memory_reference_mode)); \ 1752: else \ 1.1.1.4 ! root 1753: fprintf (STREAM, "[%s%s], #%s%d", REGISTER_PREFIX, \ 1.1.1.3 root 1754: reg_names[REGNO (XEXP (X, 0))], \ 1.1 root 1755: GET_CODE (X) == POST_DEC ? "-" : "", \ 1756: GET_MODE_SIZE (output_memory_reference_mode)); \ 1757: } \ 1758: else output_addr_const(STREAM, X); \ 1759: }
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