--- gcc/config/arm/arm.md	2018/04/24 18:22:25	1.1.1.3
+++ gcc/config/arm/arm.md	2018/04/24 18:30:07	1.1.1.4
@@ -1,5 +1,5 @@
 ;;- Machine description for Advanced RISC Machines' ARM for GNU compiler
-;;  Copyright (C) 1991, 1993, 1994 Free Software Foundation, Inc.
+;;  Copyright (C) 1991, 1993, 1994, 1995 Free Software Foundation, Inc.
 ;;  Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
 ;;             and Martin Simmons (@harleqn.co.uk).
 ;;  More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
@@ -18,7 +18,8 @@
 
 ;; You should have received a copy of the GNU General Public License
 ;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
 
 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
 
@@ -54,7 +55,7 @@
 ; but are if the branch wasn't taken; the effect is to limit the branch
 ; elimination scanning.
 
-; NOCOND means that the condition codes are niether altered nor affect the
+; NOCOND means that the condition codes are neither altered nor affect the
 ; output of this insn
 
 (define_attr "conds" "use,set,clob,jump_clob,nocond"
@@ -355,7 +356,7 @@
   [(set (match_operand:SF 0 "s_register_operand" "=f,f")
 	(plus:SF (match_operand:SF 1 "s_register_operand" "f,f")
 		 (match_operand:SF 2 "fpu_add_operand" "fG,H")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "@
    adf%?s\\t%0, %1, %2
    suf%?s\\t%0, %1, #%N2"
@@ -365,7 +366,7 @@
   [(set (match_operand:DF 0 "s_register_operand" "=f,f")
 	(plus:DF (match_operand:DF 1 "s_register_operand" "f,f")
 		 (match_operand:DF 2 "fpu_add_operand" "fG,H")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "@
    adf%?d\\t%0, %1, %2
    suf%?d\\t%0, %1, #%N2"
@@ -376,7 +377,7 @@
 	(plus:DF (float_extend:DF
 		  (match_operand:SF 1 "s_register_operand" "f,f"))
 		 (match_operand:DF 2 "fpu_add_operand" "fG,H")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "@
    adf%?d\\t%0, %1, %2
    suf%?d\\t%0, %1, #%N2"
@@ -387,7 +388,7 @@
 	(plus:DF (match_operand:DF 1 "s_register_operand" "f")
 		 (float_extend:DF
 		  (match_operand:SF 2 "s_register_operand" "f"))))]
-  ""
+  "TARGET_HARD_FLOAT"
   "adf%?d\\t%0, %1, %2"
 [(set_attr "type" "farith")])
 
@@ -397,7 +398,7 @@
 		  (match_operand:SF 1 "s_register_operand" "f"))
 		 (float_extend:DF
 		  (match_operand:SF 2 "s_register_operand" "f"))))]
-  ""
+  "TARGET_HARD_FLOAT"
   "adf%?d\\t%0, %1, %2"
 [(set_attr "type" "farith")])
 
@@ -405,7 +406,7 @@
   [(set (match_operand:XF 0 "s_register_operand" "=f,f")
 	(plus:XF (match_operand:XF 1 "s_register_operand" "f,f")
 		 (match_operand:XF 2 "fpu_add_operand" "fG,H")))]
-  "ENABLE_XF_PATTERNS"
+  "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
   "@
    adf%?e\\t%0, %1, %2
    suf%?e\\t%0, %1, #%N2"
@@ -544,7 +545,7 @@
   [(set (match_operand:SF 0 "s_register_operand" "=f,f")
 	(minus:SF (match_operand:SF 1 "fpu_rhs_operand" "f,G")
 		  (match_operand:SF 2 "fpu_rhs_operand" "fG,f")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "@
    suf%?s\\t%0, %1, %2
    rsf%?s\\t%0, %2, %1"
@@ -554,7 +555,7 @@
   [(set (match_operand:DF 0 "s_register_operand" "=f,f")
 	(minus:DF (match_operand:DF 1 "fpu_rhs_operand" "f,G")
 		  (match_operand:DF 2 "fpu_rhs_operand" "fG,f")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "@
    suf%?d\\t%0, %1, %2
    rsf%?d\\t%0, %2, %1"
@@ -565,7 +566,7 @@
 	(minus:DF (float_extend:DF
 		   (match_operand:SF 1 "s_register_operand" "f"))
 		  (match_operand:DF 2 "fpu_rhs_operand" "fG")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "suf%?d\\t%0, %1, %2"
 [(set_attr "type" "farith")])
 
@@ -574,7 +575,7 @@
 	(minus:DF (match_operand:DF 1 "fpu_rhs_operand" "f,G")
 		  (float_extend:DF
 		   (match_operand:SF 2 "s_register_operand" "f,f"))))]
-  ""
+  "TARGET_HARD_FLOAT"
   "@
    suf%?d\\t%0, %1, %2
    rsf%?d\\t%0, %2, %1"
@@ -586,7 +587,7 @@
 		   (match_operand:SF 1 "s_register_operand" "f"))
 		  (float_extend:DF
 		   (match_operand:SF 2 "s_register_operand" "f"))))]
-  ""
+  "TARGET_HARD_FLOAT"
   "suf%?d\\t%0, %1, %2"
 [(set_attr "type" "farith")])
 
@@ -594,7 +595,7 @@
   [(set (match_operand:XF 0 "s_register_operand" "=f,f")
 	(minus:XF (match_operand:XF 1 "fpu_rhs_operand" "f,G")
 		  (match_operand:XF 2 "fpu_rhs_operand" "fG,f")))]
-  "ENABLE_XF_PATTERNS"
+  "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
   "@
    suf%?e\\t%0, %1, %2
    rsf%?e\\t%0, %2, %1"
@@ -676,7 +677,7 @@
   [(set (match_operand:SF 0 "s_register_operand" "=f")
 	(mult:SF (match_operand:SF 1 "s_register_operand" "f")
 		 (match_operand:SF 2 "fpu_rhs_operand" "fG")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "fml%?s\\t%0, %1, %2"
 [(set_attr "type" "ffmul")])
 
@@ -684,7 +685,7 @@
   [(set (match_operand:DF 0 "s_register_operand" "=f")
 	(mult:DF (match_operand:DF 1 "s_register_operand" "f")
 		 (match_operand:DF 2 "fpu_rhs_operand" "fG")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "muf%?d\\t%0, %1, %2"
 [(set_attr "type" "fmul")])
 
@@ -693,7 +694,7 @@
 	(mult:DF (float_extend:DF
 		  (match_operand:SF 1 "s_register_operand" "f"))
 		 (match_operand:DF 2 "fpu_rhs_operand" "fG")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "muf%?d\\t%0, %1, %2"
 [(set_attr "type" "fmul")])
 
@@ -702,7 +703,7 @@
 	(mult:DF (match_operand:DF 1 "s_register_operand" "f")
 		 (float_extend:DF
 		  (match_operand:SF 2 "s_register_operand" "f"))))]
-  ""
+  "TARGET_HARD_FLOAT"
   "muf%?d\\t%0, %1, %2"
 [(set_attr "type" "fmul")])
 
@@ -712,7 +713,7 @@
 		  (match_operand:SF 1 "s_register_operand" "f"))
 		 (float_extend:DF
 		  (match_operand:SF 2 "s_register_operand" "f"))))]
-  ""
+  "TARGET_HARD_FLOAT"
   "muf%?d\\t%0, %1, %2"
 [(set_attr "type" "fmul")])
 
@@ -720,7 +721,7 @@
   [(set (match_operand:XF 0 "s_register_operand" "=f")
 	(mult:XF (match_operand:XF 1 "s_register_operand" "f")
 		 (match_operand:XF 2 "fpu_rhs_operand" "fG")))]
-  "ENABLE_XF_PATTERNS"
+  "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
   "muf%?e\\t%0, %1, %2"
 [(set_attr "type" "fmul")])
 
@@ -730,7 +731,7 @@
   [(set (match_operand:SF 0 "s_register_operand" "=f,f")
 	(div:SF (match_operand:SF 1 "fpu_rhs_operand" "f,G")
 		(match_operand:SF 2 "fpu_rhs_operand" "fG,f")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "@
    fdv%?s\\t%0, %1, %2
    frd%?s\\t%0, %2, %1"
@@ -740,7 +741,7 @@
   [(set (match_operand:DF 0 "s_register_operand" "=f,f")
 	(div:DF (match_operand:DF 1 "fpu_rhs_operand" "f,G")
 		(match_operand:DF 2 "fpu_rhs_operand" "fG,f")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "@
    dvf%?d\\t%0, %1, %2
    rdf%?d\\t%0, %2, %1"
@@ -751,7 +752,7 @@
 	(div:DF (float_extend:DF
 		 (match_operand:SF 1 "s_register_operand" "f"))
 		(match_operand:DF 2 "fpu_rhs_operand" "fG")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "dvf%?d\\t%0, %1, %2"
 [(set_attr "type" "fdivd")])
 
@@ -760,7 +761,7 @@
 	(div:DF (match_operand:DF 1 "fpu_rhs_operand" "fG")
 		(float_extend:DF
 		 (match_operand:SF 2 "s_register_operand" "f"))))]
-  ""
+  "TARGET_HARD_FLOAT"
   "rdf%?d\\t%0, %2, %1"
 [(set_attr "type" "fdivd")])
 
@@ -770,7 +771,7 @@
 		 (match_operand:SF 1 "s_register_operand" "f"))
 		(float_extend:DF
 		 (match_operand:SF 2 "s_register_operand" "f"))))]
-  ""
+  "TARGET_HARD_FLOAT"
   "dvf%?d\\t%0, %1, %2"
 [(set_attr "type" "fdivd")])
 
@@ -778,7 +779,7 @@
   [(set (match_operand:XF 0 "s_register_operand" "=f,f")
 	(div:XF (match_operand:XF 1 "fpu_rhs_operand" "f,G")
 		(match_operand:XF 2 "fpu_rhs_operand" "fG,f")))]
-  "ENABLE_XF_PATTERNS"
+  "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
   "@
    dvf%?e\\t%0, %1, %2
    rdf%?e\\t%0, %2, %1"
@@ -790,7 +791,7 @@
   [(set (match_operand:SF 0 "s_register_operand" "=f")
 	(mod:SF (match_operand:SF 1 "s_register_operand" "f")
 		(match_operand:SF 2 "fpu_rhs_operand" "fG")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "rmf%?s\\t%0, %1, %2"
 [(set_attr "type" "fdivs")])
 
@@ -798,7 +799,7 @@
   [(set (match_operand:DF 0 "s_register_operand" "=f")
 	(mod:DF (match_operand:DF 1 "s_register_operand" "f")
 		(match_operand:DF 2 "fpu_rhs_operand" "fG")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "rmf%?d\\t%0, %1, %2"
 [(set_attr "type" "fdivd")])
 
@@ -807,7 +808,7 @@
 	(mod:DF (float_extend:DF
 		 (match_operand:SF 1 "s_register_operand" "f"))
 		(match_operand:DF 2 "fpu_rhs_operand" "fG")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "rmf%?d\\t%0, %1, %2"
 [(set_attr "type" "fdivd")])
 
@@ -816,7 +817,7 @@
 	(mod:DF (match_operand:DF 1 "s_register_operand" "f")
 		(float_extend:DF
 		 (match_operand:SF 2 "s_register_operand" "f"))))]
-  ""
+  "TARGET_HARD_FLOAT"
   "rmf%?d\\t%0, %1, %2"
 [(set_attr "type" "fdivd")])
 
@@ -826,7 +827,7 @@
 		 (match_operand:SF 1 "s_register_operand" "f"))
 		(float_extend:DF
 		 (match_operand:SF 2 "s_register_operand" "f"))))]
-  ""
+  "TARGET_HARD_FLOAT"
   "rmf%?d\\t%0, %1, %2"
 [(set_attr "type" "fdivd")])
 
@@ -834,7 +835,7 @@
   [(set (match_operand:XF 0 "s_register_operand" "=f")
 	(mod:XF (match_operand:XF 1 "s_register_operand" "f")
 		(match_operand:XF 2 "fpu_rhs_operand" "fG")))]
-  "ENABLE_XF_PATTERNS"
+  "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
   "rmf%?e\\t%0, %1, %2"
 [(set_attr "type" "fdivx")])
 
@@ -1463,14 +1464,14 @@
 (define_insn "negsf2"
   [(set (match_operand:SF 0 "s_register_operand" "=f")
 	(neg:SF (match_operand:SF 1 "s_register_operand" "f")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "mnf%?s\\t%0, %1"
 [(set_attr "type" "ffarith")])
 
 (define_insn "negdf2"
   [(set (match_operand:DF 0 "s_register_operand" "=f")
 	(neg:DF (match_operand:DF 1 "s_register_operand" "f")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "mnf%?d\\t%0, %1"
 [(set_attr "type" "ffarith")])
 
@@ -1478,14 +1479,14 @@
   [(set (match_operand:DF 0 "s_register_operand" "=f")
 	(neg:DF (float_extend:DF
 		 (match_operand:SF 1 "s_register_operand" "f"))))]
-  ""
+  "TARGET_HARD_FLOAT"
   "mnf%?d\\t%0, %1"
 [(set_attr "type" "ffarith")])
 
 (define_insn "negxf2"
   [(set (match_operand:XF 0 "s_register_operand" "=f")
 	(neg:XF (match_operand:XF 1 "s_register_operand" "f")))]
-  "ENABLE_XF_PATTERNS"
+  "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
   "mnf%?e\\t%0, %1"
 [(set_attr "type" "ffarith")])
 
@@ -1519,14 +1520,14 @@
 (define_insn "abssf2"
   [(set (match_operand:SF 0 "s_register_operand" "=f")
 	 (abs:SF (match_operand:SF 1 "s_register_operand" "f")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "abs%?s\\t%0, %1"
 [(set_attr "type" "ffarith")])
 
 (define_insn "absdf2"
   [(set (match_operand:DF 0 "s_register_operand" "=f")
 	(abs:DF (match_operand:DF 1 "s_register_operand" "f")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "abs%?d\\t%0, %1"
 [(set_attr "type" "ffarith")])
 
@@ -1534,28 +1535,28 @@
   [(set (match_operand:DF 0 "s_register_operand" "=f")
 	(abs:DF (float_extend:DF
 		 (match_operand:SF 1 "s_register_operand" "f"))))]
-  ""
+  "TARGET_HARD_FLOAT"
   "abs%?d\\t%0, %1"
 [(set_attr "type" "ffarith")])
 
 (define_insn "absxf2"
   [(set (match_operand:XF 0 "s_register_operand" "=f")
 	(abs:XF (match_operand:XF 1 "s_register_operand" "f")))]
-  "ENABLE_XF_PATTERNS"
+  "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
   "abs%?e\\t%0, %1"
 [(set_attr "type" "ffarith")])
 
 (define_insn "sqrtsf2"
   [(set (match_operand:SF 0 "s_register_operand" "=f")
 	(sqrt:SF (match_operand:SF 1 "s_register_operand" "f")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "sqt%?s\\t%0, %1"
 [(set_attr "type" "float_em")])
 
 (define_insn "sqrtdf2"
   [(set (match_operand:DF 0 "s_register_operand" "=f")
 	(sqrt:DF (match_operand:DF 1 "s_register_operand" "f")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "sqt%?d\\t%0, %1"
 [(set_attr "type" "float_em")])
 
@@ -1563,28 +1564,28 @@
   [(set (match_operand:DF 0 "s_register_operand" "=f")
 	(sqrt:DF (float_extend:DF
 		  (match_operand:SF 1 "s_register_operand" "f"))))]
-  ""
+  "TARGET_HARD_FLOAT"
   "sqt%?d\\t%0, %1"
 [(set_attr "type" "float_em")])
 
 (define_insn "sqrtxf2"
   [(set (match_operand:XF 0 "s_register_operand" "=f")
 	(sqrt:XF (match_operand:XF 1 "s_register_operand" "f")))]
-  "ENABLE_XF_PATTERNS"
+  "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
   "sqt%?e\\t%0, %1"
 [(set_attr "type" "float_em")])
 
 (define_insn "sinsf2"
   [(set (match_operand:SF 0 "s_register_operand" "=f")
 	(unspec:SF [(match_operand:SF 1 "s_register_operand" "f")] 0))]
-  ""
+  "TARGET_HARD_FLOAT"
   "sin%?s\\t%0, %1"
 [(set_attr "type" "float_em")])
 
 (define_insn "sindf2"
   [(set (match_operand:DF 0 "s_register_operand" "=f")
 	(unspec:DF [(match_operand:DF 1 "s_register_operand" "f")] 0))]
-  ""
+  "TARGET_HARD_FLOAT"
   "sin%?d\\t%0, %1"
 [(set_attr "type" "float_em")])
 
@@ -1592,28 +1593,28 @@
   [(set (match_operand:DF 0 "s_register_operand" "=f")
 	(unspec:DF [(float_extend:DF
 		     (match_operand:SF 1 "s_register_operand" "f"))] 0))]
-  ""
+  "TARGET_HARD_FLOAT"
   "sin%?d\\t%0, %1"
 [(set_attr "type" "float_em")])
 
 (define_insn "sinxf2"
   [(set (match_operand:XF 0 "s_register_operand" "=f")
 	(unspec:XF [(match_operand:XF 1 "s_register_operand" "f")] 0))]
-  "ENABLE_XF_PATTERNS"
+  "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
   "sin%?e\\t%0, %1"
 [(set_attr "type" "float_em")])
 
 (define_insn "cossf2"
   [(set (match_operand:SF 0 "s_register_operand" "=f")
 	(unspec:SF [(match_operand:SF 1 "s_register_operand" "f")] 1))]
-  ""
+  "TARGET_HARD_FLOAT"
   "cos%?s\\t%0, %1"
 [(set_attr "type" "float_em")])
 
 (define_insn "cosdf2"
   [(set (match_operand:DF 0 "s_register_operand" "=f")
 	(unspec:DF [(match_operand:DF 1 "s_register_operand" "f")] 1))]
-  ""
+  "TARGET_HARD_FLOAT"
   "cos%?d\\t%0, %1"
 [(set_attr "type" "float_em")])
 
@@ -1621,14 +1622,14 @@
   [(set (match_operand:DF 0 "s_register_operand" "=f")
 	(unspec:DF [(float_extend:DF
 		     (match_operand:SF 1 "s_register_operand" "f"))] 1))]
-  ""
+  "TARGET_HARD_FLOAT"
   "cos%?d\\t%0, %1"
 [(set_attr "type" "float_em")])
 
 (define_insn "cosxf2"
   [(set (match_operand:XF 0 "s_register_operand" "=f")
 	(unspec:XF [(match_operand:XF 1 "s_register_operand" "f")] 1))]
-  "ENABLE_XF_PATTERNS"
+  "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
   "cos%?e\\t%0, %1"
 [(set_attr "type" "float_em")])
 
@@ -1669,42 +1670,42 @@
 (define_insn "floatsisf2"
   [(set (match_operand:SF 0 "s_register_operand" "=f")
 	(float:SF (match_operand:SI 1 "s_register_operand" "r")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "flt%?s\\t%0, %1"
 [(set_attr "type" "r_2_f")])
 
 (define_insn "floatsidf2"
   [(set (match_operand:DF 0 "s_register_operand" "=f")
 	(float:DF (match_operand:SI 1 "s_register_operand" "r")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "flt%?d\\t%0, %1"
 [(set_attr "type" "r_2_f")])
 
 (define_insn "floatsixf2"
   [(set (match_operand:XF 0 "s_register_operand" "=f")
 	(float:XF (match_operand:SI 1 "s_register_operand" "r")))]
-  "ENABLE_XF_PATTERNS"
+  "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
   "flt%?e\\t%0, %1"
 [(set_attr "type" "r_2_f")])
 
 (define_insn "fix_truncsfsi2"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
 	(fix:SI (match_operand:SF 1 "s_register_operand" "f")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "fix%?z\\t%0, %1"
 [(set_attr "type" "f_2_r")])
 
 (define_insn "fix_truncdfsi2"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
 	(fix:SI (match_operand:DF 1 "s_register_operand" "f")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "fix%?z\\t%0, %1"
 [(set_attr "type" "f_2_r")])
 
 (define_insn "fix_truncxfsi2"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
 	(fix:SI (match_operand:XF 1 "s_register_operand" "f")))]
-  "ENABLE_XF_PATTERNS"
+  "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
   "fix%?z\\t%0, %1"
 [(set_attr "type" "f_2_r")])
 
@@ -1714,7 +1715,7 @@
   [(set (match_operand:SF 0 "s_register_operand" "=f")
 	(float_truncate:SF
 	 (match_operand:DF 1 "s_register_operand" "f")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "mvf%?s\\t%0, %1"
 [(set_attr "type" "ffarith")])
 
@@ -1722,7 +1723,7 @@
   [(set (match_operand:SF 0 "s_register_operand" "=f")
 	(float_truncate:SF
 	 (match_operand:XF 1 "s_register_operand" "f")))]
-  "ENABLE_XF_PATTERNS"
+  "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
   "mvf%?s\\t%0, %1"
 [(set_attr "type" "ffarith")])
 
@@ -1730,7 +1731,7 @@
   [(set (match_operand:DF 0 "s_register_operand" "=f")
 	(float_truncate:DF
 	 (match_operand:XF 1 "s_register_operand" "f")))]
-  "ENABLE_XF_PATTERNS"
+  "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
   "mvf%?d\\t%0, %1"
 [(set_attr "type" "ffarith")])
 
@@ -1901,21 +1902,21 @@
 (define_insn "extendsfdf2"
   [(set (match_operand:DF 0 "s_register_operand" "=f")
 	(float_extend:DF (match_operand:SF 1 "s_register_operand" "f")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "mvf%?d\\t%0, %1"
 [(set_attr "type" "ffarith")])
 
 (define_insn "extendsfxf2"
   [(set (match_operand:XF 0 "s_register_operand" "=f")
 	(float_extend:XF (match_operand:SF 1 "s_register_operand" "f")))]
-  "ENABLE_XF_PATTERNS"
+  "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
   "mvf%?e\\t%0, %1"
 [(set_attr "type" "ffarith")])
 
 (define_insn "extenddfxf2"
   [(set (match_operand:XF 0 "s_register_operand" "=f")
 	(float_extend:XF (match_operand:DF 1 "s_register_operand" "f")))]
-  "ENABLE_XF_PATTERNS"
+  "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
   "mvf%?e\\t%0, %1"
 [(set_attr "type" "ffarith")])
 
@@ -2104,7 +2105,7 @@
 ;; Operand 1 is the destination address in a register (SImode)
 
 ;; In both this routine and the next, we must be careful not to spill
-;; a memory address of reg+large_const into a seperate PLUS insn, since this
+;; a memory address of reg+large_const into a separate PLUS insn, since this
 ;; can generate unrecognizable rtl.
 
 (define_expand "storehi"
@@ -2409,8 +2410,9 @@
   ""
   "
   if (GET_CODE (operands[1]) == CONST_DOUBLE
-      && ((GET_CODE (operands[0]) == REG
-	   && REGNO (operands[0]) < 16)
+      && (TARGET_SOFT_FLOAT
+	  || (GET_CODE (operands[0]) == REG
+	      && REGNO (operands[0]) < 16)
 	  || ! (const_double_rtx_ok_for_fpu (operands[1])
 		|| neg_const_double_rtx_ok_for_fpu (operands[1]))))
     {
@@ -2438,7 +2440,8 @@
 (define_insn ""
   [(set (match_operand:SF 0 "general_operand" "=f,f,f,m,f,r,r,r,m")
 	(match_operand:SF 1 "general_operand" "fG,H,m,f,r,f,r,m,r"))]
-  "GET_CODE (operands[0]) != MEM || register_operand (operands[1], SFmode)"
+  "TARGET_HARD_FLOAT
+   && (GET_CODE (operands[0]) != MEM || register_operand (operands[1], SFmode))"
   "@
    mvf%?s\\t%0, %1
    mnf%?s\\t%0, #%N1
@@ -2453,14 +2456,31 @@
  (set_attr "type"
 	 "ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*,load,store1")])
 
+;; Exactly the same as above, except that all `f' cases are deleted.
+;; This is necessary to prevent reload from ever trying to use a `f' reg
+;; when -msoft-float.
+
+(define_insn "*movsf_soft_insn"
+  [(set (match_operand:SF 0 "general_operand" "=r,r,m")
+	(match_operand:SF 1 "general_operand" "r,m,r"))]
+  "TARGET_SOFT_FLOAT
+   && (GET_CODE (operands[0]) != MEM || register_operand (operands[1], SFmode))"
+  "@
+   mov%?\\t%0, %1
+   ldr%?\\t%0, %1\\t%@ float
+   str%?\\t%1, %0\\t%@ float"
+[(set_attr "length" "4,4,4")
+ (set_attr "type" "*,load,store1")])
+
 (define_expand "movdf"
   [(set (match_operand:DF 0 "general_operand" "")
 	(match_operand:DF 1 "general_operand" ""))]
   ""
   "
   if (GET_CODE (operands[1]) == CONST_DOUBLE
-      && ((GET_CODE (operands[0]) == REG
-	   && REGNO (operands[0]) < 16)
+      && (TARGET_SOFT_FLOAT
+	  || (GET_CODE (operands[0]) == REG
+	      && REGNO (operands[0]) < 16)
 	  || ! (const_double_rtx_ok_for_fpu (operands[1])
 		|| neg_const_double_rtx_ok_for_fpu (operands[1]))))
     {
@@ -2507,7 +2527,8 @@
   [(set (match_operand:DF 0 "general_operand" "=r,Q#m,r,f,f,f,f,m,!f,!r,r")
 	(match_operand:DF 1 "general_operand" 
 	 	"Q,r,?o,?f,!G,!H,m,f,r,f,??r"))]
-  "GET_CODE (operands[0]) != MEM || register_operand (operands[1], DFmode)"
+  "TARGET_HARD_FLOAT
+   && (GET_CODE (operands[0]) != MEM || register_operand (operands[1], DFmode))"
   "*
 {
   rtx ops[3];
@@ -2547,10 +2568,22 @@
  (set_attr "type" 
 "load,store2,load,ffarith,ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*")])
 
+;; Software floating point version.  This is essentially the same as movdi.
+;; Do not use `f' as a constraint to prevent reload from ever trying to use
+;; an `f' reg.
+
+(define_insn "*movdf_soft_insn"
+  [(set (match_operand:DF 0 "soft_df_operand" "=r,r,o<>,r")
+	(match_operand:DF 1 "soft_df_operand" "r,o<>,r,F"))]
+  "TARGET_SOFT_FLOAT"
+  "* return output_move_double (operands);"
+[(set_attr "length" "8,8,8,32")
+ (set_attr "type" "*,load,store2,*")])
+
 (define_expand "movxf"
   [(set (match_operand:XF 0 "general_operand" "")
 	(match_operand:XF 1 "general_operand" ""))]
-  "ENABLE_XF_PATTERNS"
+  "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
   "")
 
 ;; Even when the XFmode patterns aren't enabled, we enable this after
@@ -2559,7 +2592,7 @@
 (define_insn ""
   [(set (match_operand:XF 0 "general_operand" "=f,f,f,m,f,r,r")
 	(match_operand:XF 1 "general_operand" "fG,H,m,f,r,f,r"))]
-  "ENABLE_XF_PATTERNS || reload_completed"
+  "TARGET_HARD_FLOAT && (ENABLE_XF_PATTERNS || reload_completed)"
   "*
   switch (which_alternative)
     {
@@ -2765,7 +2798,7 @@
   [(set (reg:CC 24)
 	(compare:CC (match_operand:SF 0 "s_register_operand" "")
 		    (match_operand:SF 1 "fpu_rhs_operand" "")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "
 {
   arm_compare_op0 = operands[0];
@@ -2779,7 +2812,7 @@
   [(set (reg:CC 24)
 	(compare:CC (match_operand:DF 0 "s_register_operand" "")
 		    (match_operand:DF 1 "fpu_rhs_operand" "")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "
 {
   arm_compare_op0 = operands[0];
@@ -2793,7 +2826,7 @@
   [(set (reg:CC 24)
 	(compare:CC (match_operand:XF 0 "s_register_operand" "")
 		    (match_operand:XF 1 "fpu_rhs_operand" "")))]
-  "ENABLE_XF_PATTERNS"
+  "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
   "
 {
   arm_compare_op0 = operands[0];
@@ -2845,7 +2878,7 @@
   [(set (reg:CCFP 24)
 	(compare:CCFP (match_operand:SF 0 "s_register_operand" "f,f")
 		      (match_operand:SF 1 "fpu_add_operand" "fG,H")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "@
    cmf%?\\t%0, %1
    cnf%?\\t%0, #%N1"
@@ -2856,7 +2889,7 @@
   [(set (reg:CCFP 24)
 	(compare:CCFP (match_operand:DF 0 "s_register_operand" "f,f")
 		      (match_operand:DF 1 "fpu_add_operand" "fG,H")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "@
    cmf%?\\t%0, %1
    cnf%?\\t%0, #%N1"
@@ -2868,7 +2901,7 @@
 	(compare:CCFP (float_extend:DF
 		       (match_operand:SF 0 "s_register_operand" "f,f"))
 		      (match_operand:DF 1 "fpu_add_operand" "fG,H")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "@
    cmf%?\\t%0, %1
    cnf%?\\t%0, #%N1"
@@ -2880,7 +2913,7 @@
 	(compare:CCFP (match_operand:DF 0 "s_register_operand" "f")
 		      (float_extend:DF
 		       (match_operand:SF 1 "s_register_operand" "f"))))]
-  ""
+  "TARGET_HARD_FLOAT"
   "cmf%?\\t%0, %1"
 [(set_attr "conds" "set")
  (set_attr "type" "f_2_r")])
@@ -2889,7 +2922,7 @@
   [(set (reg:CCFP 24)
 	(compare:CCFP (match_operand:XF 0 "s_register_operand" "f,f")
 		      (match_operand:XF 1 "fpu_add_operand" "fG,H")))]
-  "ENABLE_XF_PATTERNS"
+  "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
   "@
    cmf%?\\t%0, %1
    cnf%?\\t%0, #%N1"
@@ -2900,7 +2933,7 @@
   [(set (reg:CCFPE 24)
 	(compare:CCFPE (match_operand:SF 0 "s_register_operand" "f,f")
 		       (match_operand:SF 1 "fpu_add_operand" "fG,H")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "@
    cmf%?e\\t%0, %1
    cnf%?e\\t%0, #%N1"
@@ -2911,7 +2944,7 @@
   [(set (reg:CCFPE 24)
 	(compare:CCFPE (match_operand:DF 0 "s_register_operand" "f,f")
 		       (match_operand:DF 1 "fpu_add_operand" "fG,H")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "@
    cmf%?e\\t%0, %1
    cnf%?e\\t%0, #%N1"
@@ -2923,7 +2956,7 @@
 	(compare:CCFPE (float_extend:DF
 			(match_operand:SF 0 "s_register_operand" "f,f"))
 		       (match_operand:DF 1 "fpu_add_operand" "fG,H")))]
-  ""
+  "TARGET_HARD_FLOAT"
   "@
    cmf%?e\\t%0, %1
    cnf%?e\\t%0, #%N1"
@@ -2935,7 +2968,7 @@
 	(compare:CCFPE (match_operand:DF 0 "s_register_operand" "f")
 		       (float_extend:DF
 			(match_operand:SF 1 "s_register_operand" "f"))))]
-  ""
+  "TARGET_HARD_FLOAT"
   "cmf%?e\\t%0, %1"
 [(set_attr "conds" "set")
  (set_attr "type" "f_2_r")])
@@ -2944,7 +2977,7 @@
   [(set (reg:CCFPE 24)
 	(compare:CCFPE (match_operand:XF 0 "s_register_operand" "f,f")
 		       (match_operand:XF 1 "fpu_add_operand" "fG,H")))]
-  "ENABLE_XF_PATTERNS"
+  "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
   "@
    cmf%?e\\t%0, %1
    cnf%?e\\t%0, #%N1"
@@ -3279,6 +3312,99 @@
  (set_attr "length" "8")])
 
 
+;; Conditional move insns
+
+(define_expand "movsicc"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(if_then_else (match_operand 1 "comparison_operator" "")
+		      (match_operand:SI 2 "arm_not_operand" "")
+		      (match_operand:SI 3 "register_operand" "")))]
+  ""
+  "
+{
+  enum rtx_code code = GET_CODE (operands[1]);
+  rtx ccreg = gen_compare_reg (code, arm_compare_op0, arm_compare_op1,
+			       arm_compare_fp);
+
+  operands[1] = gen_rtx (code, VOIDmode, ccreg, const0_rtx);
+}")
+
+(define_expand "movsfcc"
+  [(set (match_operand:SF 0 "register_operand" "")
+	(if_then_else (match_operand 1 "comparison_operator" "")
+		      (match_operand:SF 2 "nonmemory_operand" "")
+		      (match_operand:SF 3 "register_operand" "")))]
+  ""
+  "
+{
+  enum rtx_code code = GET_CODE (operands[1]);
+  rtx ccreg = gen_compare_reg (code, arm_compare_op0, arm_compare_op1,
+			       arm_compare_fp);
+
+  operands[1] = gen_rtx (code, VOIDmode, ccreg, const0_rtx);
+}")
+
+(define_expand "movdfcc"
+  [(set (match_operand:DF 0 "register_operand" "")
+	(if_then_else (match_operand 1 "comparison_operator" "")
+		      (match_operand:DF 2 "nonmemory_operand" "")
+		      (match_operand:DF 3 "register_operand" "")))]
+  "TARGET_HARD_FLOAT"
+  "
+{
+  enum rtx_code code = GET_CODE (operands[1]);
+  rtx ccreg = gen_compare_reg (code, arm_compare_op0, arm_compare_op1,
+			       arm_compare_fp);
+
+  operands[1] = gen_rtx (code, VOIDmode, ccreg, const0_rtx);
+}")
+
+(define_insn "*movsicc_insn"
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(if_then_else (match_operator 1 "comparison_operator" 
+		       [(reg 24) (const_int 0)])
+		      (match_operand:SI 2 "arm_not_operand" "rI,K")
+		      (match_operand:SI 3 "register_operand" "0,0")))]
+  ""
+  "@
+   mov%d1\\t%0, %2
+   mvn%d1\\t%0, #%B2"
+  [(set_attr "type" "*,*")
+   (set_attr "conds" "use,use")])
+
+(define_insn "*movsfcc_hard_insn"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(if_then_else (match_operator 1 "comparison_operator" 
+		       [(reg 24) (const_int 0)])
+		      (match_operand:SF 2 "register_operand" "f")
+		      (match_operand:SF 3 "register_operand" "0")))]
+  "TARGET_HARD_FLOAT"
+  "mvf%d1s\\t%0, %2"
+  [(set_attr "type" "ffarith")
+   (set_attr "conds" "use")])
+
+(define_insn "*movsfcc_soft_insn"
+  [(set (match_operand:SF 0 "register_operand" "=r")
+	(if_then_else (match_operator 1 "comparison_operator"
+		       [(reg 24) (const_int 0)])
+		      (match_operand:SF 2 "register_operand" "r")
+		      (match_operand:SF 3 "register_operand" "0")))]
+  "TARGET_SOFT_FLOAT"
+  "mov%d1\\t%0, %2"
+  [(set_attr "type" "*")
+   (set_attr "conds" "use")])
+
+(define_insn "*movdfcc_insn"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(if_then_else (match_operator 1 "comparison_operator"
+		       [(reg 24) (const_int 0)])
+		      (match_operand:DF 2 "register_operand" "f")
+		      (match_operand:DF 3 "register_operand" "0")))]
+  "TARGET_HARD_FLOAT"
+  "mvf%d1d\\t%0, %2"
+  [(set_attr "type" "ffarith")
+   (set_attr "conds" "use")])
+
 ;; Jump and linkage insns
 
 (define_insn "jump"
@@ -3868,7 +3994,7 @@
 ")
 
 ;; Don't match these patterns if we can use a conditional compare, since they
-;; tell the final prescan branch elimator code that full branch inlining
+;; tell the final prescan branch eliminator code that full branch inlining
 ;; can't be done.
 
 (define_insn ""
@@ -3992,6 +4118,8 @@
   output_asm_insn (\"cmp\\t%2, %3\", operands);
   if (GET_CODE (operands[5]) == AND)
     output_asm_insn (\"mov%D4\\t%0, #0\", operands);
+  else if (GET_CODE (operands[5]) == MINUS)
+    output_asm_insn (\"rsb%D4\\t%0, %1, #0\", operands);
   else if (which_alternative != 0)
     output_asm_insn (\"mov%D4\\t%0, %1\", operands);
   return \"%i5%d4\\t%0, %1, #1\";
@@ -4105,7 +4233,7 @@
 ")
 
 ;; Don't match these patterns if we can use a conditional compare, since they
-;; tell the final prescan branch elimator code that full branch inlining
+;; tell the final prescan branch eliminator code that full branch inlining
 ;; can't be done.
 
 (define_insn ""
@@ -4268,7 +4396,7 @@
   ""
   "*
   /* If we have an operation where (op x 0) is the identity operation and
-     the condtional operator is LT or GE and we are comparing against zero and
+     the conditional operator is LT or GE and we are comparing against zero and
      everything is in registers then we can do this in two instructions */
   if (operands[3] == const0_rtx
       && GET_CODE (operands[7]) != AND
@@ -4313,7 +4441,7 @@
   ""
   "*
   /* If we have an operation where (op x 0) is the identity operation and
-     the condtional operator is LT or GE and we are comparing against zero and
+     the conditional operator is LT or GE and we are comparing against zero and
      everything is in registers then we can do this in two instructions */
   if (operands[5] == const0_rtx
       && GET_CODE (operands[7]) != AND
@@ -5184,7 +5312,7 @@
 ;; any of our local variables.  If we call alloca then this is unsafe
 ;; since restoring the frame frees the memory, which is not what we want.
 ;; Sometimes the return might have been targeted by the final prescan:
-;; if so then emit a propper return insn as well.
+;; if so then emit a proper return insn as well.
 ;; Unfortunately, if the frame pointer is required, we don't know if the
 ;; current function has any implicit stack pointer adjustments that will 
 ;; be restored by the return: we can't therefore do a tail call.
@@ -5294,7 +5422,7 @@
 ;; and jump direct to the subroutine.  On return from the subroutine
 ;; execution continues at the branch; this avoids a prefetch stall.
 ;; We use the length attribute (via short_branch ()) to establish whether or
-;; not this is possible, this is the same asthe sparc does.
+;; not this is possible, this is the same as the sparc does.
 
 (define_peephole
   [(parallel[(call (mem:SI (match_operand:SI 0 "" "i"))