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1.1.1.3 root 1: ;;- Machine description for Advanced RISC Machines' ARM for GNU compiler 1.1.1.4 root 2: ;; Copyright (C) 1991, 1993, 1994, 1995 Free Software Foundation, Inc. 1.1 root 3: ;; Contributed by Pieter `Tiggr' Schoenmakers ([email protected]) 4: ;; and Martin Simmons (@harleqn.co.uk). 1.1.1.2 root 5: ;; More major hacks by Richard Earnshaw ([email protected]) 1.1 root 6: 7: ;; This file is part of GNU CC. 8: 9: ;; GNU CC is free software; you can redistribute it and/or modify 10: ;; it under the terms of the GNU General Public License as published by 11: ;; the Free Software Foundation; either version 2, or (at your option) 12: ;; any later version. 13: 14: ;; GNU CC is distributed in the hope that it will be useful, 15: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 16: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17: ;; GNU General Public License for more details. 18: 19: ;; You should have received a copy of the GNU General Public License 20: ;; along with GNU CC; see the file COPYING. If not, write to 1.1.1.4 root 21: ;; the Free Software Foundation, 59 Temple Place - Suite 330, 22: ;; Boston, MA 02111-1307, USA. 1.1 root 23: 24: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 25: 1.1.1.2 root 26: ;; There are patterns in this file to support XFmode arithmetic. 1.1.1.3 root 27: ;; Unfortunately RISC iX doesn't work well with these so they are disabled. 1.1.1.2 root 28: ;; (See arm.h) 29: 30: ;; UNSPEC Usage: 31: ;; 0 `sin' operation: operand 0 is the result, operand 1 the parameter, 32: ;; the mode is MODE_FLOAT 33: ;; 1 `cos' operation: operand 0 is the result, operand 1 the parameter, 34: ;; the mode is MODE_FLOAT 1.1.1.3 root 35: ;; 2 `push multiple' operation: operand 0 is the first register. Subsequent 36: ;; registers are in parallel (use...) expressions. 1.1.1.2 root 37: 38: ;; Attributes 39: 40: ; condition codes: this one is used by final_prescan_insn to speed up 41: ; conditionalizing instructions. It saves having to scan the rtl to see if 42: ; it uses or alters the condition codes. 43: 44: ; USE means that the condition codes are used by the insn in the process of 45: ; outputting code, this means (at present) that we can't use the insn in 46: ; inlined branches 47: 48: ; SET means that the purpose of the insn is to set the condition codes in a 49: ; well defined manner. 50: 51: ; CLOB means that the condition codes are altered in an undefined manner, if 52: ; they are altered at all 53: 54: ; JUMP_CLOB is used when the conditions are not defined if a branch is taken, 55: ; but are if the branch wasn't taken; the effect is to limit the branch 56: ; elimination scanning. 57: 1.1.1.4 root 58: ; NOCOND means that the condition codes are neither altered nor affect the 1.1.1.2 root 59: ; output of this insn 60: 61: (define_attr "conds" "use,set,clob,jump_clob,nocond" 62: (const_string "nocond")) 63: 64: ; CPU attribute is used to determine whether condition codes are clobbered 65: ; by a call insn: on the arm6 they are if in 32-bit addressing mode; on the 66: ; arm2 and arm3 the condition codes are restored by the return. 67: 68: (define_attr "cpu" "arm2,arm3,arm6" (const (symbol_ref "arm_cpu_attr"))) 69: 1.1.1.3 root 70: ; Floating Point Unit. If we only have floating point emulation, then there 71: ; is no point in scheduling the floating point insns. (Well, for best 72: ; performance we should try and group them together). 73: 74: (define_attr "fpu" "fpa,fpe" (const (symbol_ref "arm_fpu_attr"))) 75: 76: ; LENGTH of an instruction (in bytes) 77: (define_attr "length" "" (const_int 4)) 1.1.1.2 root 78: 79: ; An assembler sequence may clobber the condition codes without us knowing 80: (define_asm_attributes 81: [(set_attr "conds" "clob") 1.1.1.3 root 82: (set_attr "length" "4")]) 1.1.1.2 root 83: 84: ; TYPE attribute is used to detect floating point instructions which, if 85: ; running on a co-processor can run in parallel with other, basic instructions 86: ; If write-buffer scheduling is enabled then it can also be used in the 87: ; scheduling of writes. 88: 89: ; Classification of each insn 90: ; normal any data instruction that doesn't hit memory or fp regs 91: ; block blockage insn, this blocks all functional units 92: ; float a floating point arithmetic operation (subject to expansion) 1.1.1.3 root 93: ; fdivx XFmode floating point division 94: ; fdivd DFmode floating point division 95: ; fdivs SFmode floating point division 96: ; fmul Floating point multiply 97: ; ffmul Fast floating point multiply 98: ; farith Floating point arithmetic (4 cycle) 99: ; ffarith Fast floating point arithmetic (2 cycle) 1.1.1.2 root 100: ; float_em a floating point arithmetic operation that is normally emulated 1.1.1.3 root 101: ; even on a machine with an fpa. 1.1.1.2 root 102: ; f_load a floating point load from memory 103: ; f_store a floating point store to memory 104: ; f_mem_r a transfer of a floating point register to a real reg via mem 105: ; r_mem_f the reverse of f_mem_r 106: ; f_2_r fast transfer float to arm (no memory needed) 107: ; r_2_f fast transfer arm to float 108: ; call a subroutine call 109: ; load any load from memory 110: ; store1 store 1 word to memory from arm registers 111: ; store2 store 2 words 112: ; store3 store 3 words 113: ; store4 store 4 words 114: ; 115: (define_attr "type" 1.1.1.3 root 116: "normal,block,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith,float_em,f_load,f_store,f_mem_r,r_mem_f,f_2_r,r_2_f,call,load,store1,store2,store3,store4" 1.1.1.2 root 117: (const_string "normal")) 118: 119: (define_attr "write_conflict" "no,yes" 120: (if_then_else (eq_attr "type" 121: "block,float_em,f_load,f_store,f_mem_r,r_mem_f,call,load") 122: (const_string "yes") 123: (const_string "no"))) 124: 125: ; The write buffer on some of the arm6 processors is hard to model exactly. 126: ; There is room in the buffer for up to two addresses and up to eight words 127: ; of memory, but the two needn't be split evenly. When writing the two 128: ; addresses are fully pipelined. However, a read from memory that is not 129: ; currently in the cache will block until the writes have completed. 130: ; It is normally the case that FCLK and MCLK will be in the ratio 2:1, so 131: ; writes will take 2 FCLK cycles per word, if FCLK and MCLK are asynchronous 132: ; (they aren't allowed to be at present) then there is a startup cost of 1MCLK 133: ; cycle to add as well. 134: 135: ;; (define_function_unit {name} {num-units} {n-users} {test} 136: ;; {ready-delay} {issue-delay} [{conflict-list}]) 1.1.1.3 root 137: (define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa") 138: (eq_attr "type" "fdivx")) 71 69) 139: 140: (define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa") 141: (eq_attr "type" "fdivd")) 59 57) 142: 143: (define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa") 144: (eq_attr "type" "fdivs")) 31 29) 145: 146: (define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa") 147: (eq_attr "type" "fmul")) 9 7) 148: 149: (define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa") 150: (eq_attr "type" "ffmul")) 6 4) 151: 152: (define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa") 153: (eq_attr "type" "farith")) 4 2) 154: 155: (define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa") 156: (eq_attr "type" "ffarith")) 2 2) 157: 158: (define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa") 159: (eq_attr "type" "r_2_f")) 5 3) 160: 161: (define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa") 162: (eq_attr "type" "f_2_r")) 1 2) 163: 164: ;; The fpa10 doesn't really have a memory read unit, but it can start to 165: ;; speculatively execute the instruction in the pipeline, provided the data 166: ;; is already loaded, so pretend reads have a delay of 2 (and that the 167: ;; pipeline is infinite. 168: 169: (define_function_unit "fpa_mem" 1 0 (and (eq_attr "fpu" "fpa") 170: (eq_attr "type" "f_load")) 3 1) 1.1.1.2 root 171: 172: (define_function_unit "write_buf" 1 2 (eq_attr "type" "store1") 3 3 173: [(eq_attr "write_conflict" "yes")]) 174: (define_function_unit "write_buf" 1 2 (eq_attr "type" "store2") 5 5 175: [(eq_attr "write_conflict" "yes")]) 176: (define_function_unit "write_buf" 1 2 (eq_attr "type" "store3") 7 7 177: [(eq_attr "write_conflict" "yes")]) 178: (define_function_unit "write_buf" 1 2 (eq_attr "type" "store4") 9 9 179: [(eq_attr "write_conflict" "yes")]) 180: (define_function_unit "write_buf" 1 2 (eq_attr "type" "r_mem_f") 3 3 181: [(eq_attr "write_conflict" "yes")]) 1.1 root 182: 1.1.1.2 root 183: ;; Note: For DImode insns, there is normally no reason why operands should 184: ;; not be in the same register, what we don't want is for something being 185: ;; written to partially overlap something that is an input. 186: 1.1 root 187: ;; Addition insns. 188: 189: (define_insn "adddi3" 1.1.1.2 root 190: [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 191: (plus:DI (match_operand:DI 1 "s_register_operand" "%0,0") 192: (match_operand:DI 2 "s_register_operand" "r,0"))) 193: (clobber (reg:CC 24))] 1.1 root 194: "" 1.1.1.3 root 195: "adds\\t%0, %1, %2\;adc\\t%R0, %R1, %R2" 1.1.1.2 root 196: [(set_attr "conds" "clob") 1.1.1.3 root 197: (set_attr "length" "8")]) 1.1.1.2 root 198: 199: (define_insn "" 200: [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 201: (plus:DI (sign_extend:DI 202: (match_operand:SI 1 "s_register_operand" "r,r")) 203: (match_operand:DI 2 "s_register_operand" "r,0"))) 204: (clobber (reg:CC 24))] 205: "" 1.1.1.3 root 206: "adds\\t%0, %2, %1\;adc\\t%R0, %R2, %1, asr #31" 1.1.1.2 root 207: [(set_attr "conds" "clob") 1.1.1.3 root 208: (set_attr "length" "8")]) 1.1.1.2 root 209: 210: (define_insn "" 211: [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 212: (plus:DI (zero_extend:DI 213: (match_operand:SI 1 "s_register_operand" "r,r")) 214: (match_operand:DI 2 "s_register_operand" "r,0"))) 215: (clobber (reg:CC 24))] 216: "" 1.1.1.3 root 217: "adds\\t%0, %2, %1\;adc\\t%R0, %R2, #0" 1.1.1.2 root 218: [(set_attr "conds" "clob") 1.1.1.3 root 219: (set_attr "length" "8")]) 1.1 root 220: 1.1.1.3 root 221: (define_expand "addsi3" 222: [(set (match_operand:SI 0 "s_register_operand" "") 223: (plus:SI (match_operand:SI 1 "s_register_operand" "") 224: (match_operand:SI 2 "reg_or_int_operand" "")))] 1.1 root 225: "" 1.1.1.3 root 226: " 227: if (GET_CODE (operands[2]) == CONST_INT) 1.1 root 228: { 1.1.1.3 root 229: arm_split_constant (PLUS, SImode, INTVAL (operands[2]), operands[0], 230: operands[1], 231: (reload_in_progress || reload_completed ? 0 232: : preserve_subexpressions_p ())); 233: DONE; 1.1 root 234: } 1.1.1.3 root 235: ") 236: 237: (define_split 238: [(set (match_operand:SI 0 "s_register_operand" "") 239: (plus:SI (match_operand:SI 1 "s_register_operand" "") 240: (match_operand:SI 2 "const_int_operand" "")))] 241: "! (const_ok_for_arm (INTVAL (operands[2])) 242: || const_ok_for_arm (-INTVAL (operands[2])))" 243: [(clobber (const_int 0))] 244: " 245: arm_split_constant (PLUS, SImode, INTVAL (operands[2]), operands[0], 246: operands[1], 0); 247: DONE; 1.1 root 248: ") 249: 1.1.1.2 root 250: (define_insn "" 1.1.1.3 root 251: [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") 252: (plus:SI (match_operand:SI 1 "s_register_operand" "r,r,r") 253: (match_operand:SI 2 "reg_or_int_operand" "rI,L,?n")))] 254: "" 255: "@ 256: add%?\\t%0, %1, %2 257: sub%?\\t%0, %1, #%n2 258: #" 259: [(set_attr "length" "4,4,16")]) 260: 261: (define_insn "" 1.1.1.2 root 262: [(set (reg:CC_NOOV 24) 1.1.1.3 root 263: (compare:CC_NOOV 264: (plus:SI (match_operand:SI 1 "s_register_operand" "r,r") 265: (match_operand:SI 2 "arm_add_operand" "rI,L")) 266: (const_int 0))) 267: (set (match_operand:SI 0 "s_register_operand" "=r,r") 1.1.1.2 root 268: (plus:SI (match_dup 1) (match_dup 2)))] 269: "" 1.1.1.3 root 270: "@ 271: add%?s\\t%0, %1, %2 272: sub%?s\\t%0, %1, #%n2" 1.1.1.2 root 273: [(set_attr "conds" "set")]) 274: 275: (define_insn "" 276: [(set (reg:CC 24) 1.1.1.3 root 277: (compare:CC (match_operand:SI 1 "s_register_operand" "r,r") 278: (neg:SI (match_operand:SI 2 "arm_add_operand" "rI,L")))) 279: (set (match_operand:SI 0 "s_register_operand" "=r,r") 1.1.1.2 root 280: (plus:SI (match_dup 1) (match_dup 2)))] 1.1 root 281: "" 1.1.1.3 root 282: "@ 283: add%?s\\t%0, %1, %2 284: sub%?s\\t%0, %1, #%n2" 1.1.1.2 root 285: [(set_attr "conds" "set")]) 286: 287: (define_insn "incscc" 288: [(set (match_operand:SI 0 "s_register_operand" "=r,r") 289: (plus:SI (match_operator:SI 2 "comparison_operator" 290: [(reg 24) (const_int 0)]) 291: (match_operand:SI 1 "s_register_operand" "0,?r")))] 292: "" 1.1.1.3 root 293: "@ 294: add%d2\\t%0, %1, #1 295: mov%D2\\t%0, %1\;add%d2\\t%0, %1, #1" 1.1.1.2 root 296: [(set_attr "conds" "use") 1.1.1.3 root 297: (set_attr "length" "4,8")]) 1.1.1.2 root 298: 299: ; If a constant is too big to fit in a single instruction then the constant 300: ; will be pre-loaded into a register taking at least two insns, we might be 301: ; able to merge it with an add, but it depends on the exact value. 302: 303: (define_split 304: [(set (match_operand:SI 0 "s_register_operand" "=r") 305: (plus:SI (match_operand:SI 1 "s_register_operand" "r") 306: (match_operand:SI 2 "immediate_operand" "n")))] 307: "!(const_ok_for_arm (INTVAL (operands[2])) 308: || const_ok_for_arm (-INTVAL (operands[2])))" 309: [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2))) 310: (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))] 311: " 312: { 313: unsigned int val = (unsigned) INTVAL (operands[2]); 314: int i; 315: unsigned int temp; 316: 317: /* this code is similar to the approach followed in movsi, but it must 318: generate exactly two insns */ 319: 320: for (i = 30; i >= 0; i -= 2) 321: { 322: if (val & (3 << i)) 323: { 324: i -= 6; 325: if (i < 0) i = 0; 326: if (const_ok_for_arm (temp = (val & ~(255 << i)))) 327: { 328: val &= 255 << i; 329: break; 330: } 331: /* we might be able to do this as (larger number - small number) */ 332: temp = ((val >> i) & 255) + 1; 333: if (temp > 255 && i < 24) 334: { 335: i += 2; 336: temp = ((val >> i) & 255) + 1; 337: } 338: if (const_ok_for_arm ((temp << i) - val)) 339: { 340: i = temp << i; 341: temp = (unsigned) - (int) (i - val); 342: val = i; 343: break; 344: } 345: FAIL; 346: } 347: } 348: /* if we got here, we have found a way of doing it in two instructions. 349: the two constants are in val and temp */ 350: operands[2] = GEN_INT ((int)val); 351: operands[3] = GEN_INT ((int)temp); 352: } 1.1 root 353: ") 354: 1.1.1.2 root 355: (define_insn "addsf3" 356: [(set (match_operand:SF 0 "s_register_operand" "=f,f") 357: (plus:SF (match_operand:SF 1 "s_register_operand" "f,f") 358: (match_operand:SF 2 "fpu_add_operand" "fG,H")))] 1.1.1.4 root 359: "TARGET_HARD_FLOAT" 1.1.1.3 root 360: "@ 361: adf%?s\\t%0, %1, %2 362: suf%?s\\t%0, %1, #%N2" 363: [(set_attr "type" "farith")]) 1.1.1.2 root 364: 1.1 root 365: (define_insn "adddf3" 1.1.1.2 root 366: [(set (match_operand:DF 0 "s_register_operand" "=f,f") 367: (plus:DF (match_operand:DF 1 "s_register_operand" "f,f") 368: (match_operand:DF 2 "fpu_add_operand" "fG,H")))] 1.1.1.4 root 369: "TARGET_HARD_FLOAT" 1.1.1.3 root 370: "@ 371: adf%?d\\t%0, %1, %2 372: suf%?d\\t%0, %1, #%N2" 373: [(set_attr "type" "farith")]) 1.1.1.2 root 374: 375: (define_insn "" 376: [(set (match_operand:DF 0 "s_register_operand" "=f,f") 377: (plus:DF (float_extend:DF 378: (match_operand:SF 1 "s_register_operand" "f,f")) 379: (match_operand:DF 2 "fpu_add_operand" "fG,H")))] 1.1.1.4 root 380: "TARGET_HARD_FLOAT" 1.1.1.3 root 381: "@ 382: adf%?d\\t%0, %1, %2 383: suf%?d\\t%0, %1, #%N2" 384: [(set_attr "type" "farith")]) 1.1.1.2 root 385: 386: (define_insn "" 387: [(set (match_operand:DF 0 "s_register_operand" "=f") 388: (plus:DF (match_operand:DF 1 "s_register_operand" "f") 389: (float_extend:DF 390: (match_operand:SF 2 "s_register_operand" "f"))))] 1.1.1.4 root 391: "TARGET_HARD_FLOAT" 1.1.1.3 root 392: "adf%?d\\t%0, %1, %2" 393: [(set_attr "type" "farith")]) 1.1.1.2 root 394: 395: (define_insn "" 396: [(set (match_operand:DF 0 "s_register_operand" "=f") 397: (plus:DF (float_extend:DF 398: (match_operand:SF 1 "s_register_operand" "f")) 399: (float_extend:DF 400: (match_operand:SF 2 "s_register_operand" "f"))))] 1.1.1.4 root 401: "TARGET_HARD_FLOAT" 1.1.1.3 root 402: "adf%?d\\t%0, %1, %2" 403: [(set_attr "type" "farith")]) 1.1.1.2 root 404: 405: (define_insn "addxf3" 406: [(set (match_operand:XF 0 "s_register_operand" "=f,f") 407: (plus:XF (match_operand:XF 1 "s_register_operand" "f,f") 408: (match_operand:XF 2 "fpu_add_operand" "fG,H")))] 1.1.1.4 root 409: "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" 1.1.1.3 root 410: "@ 411: adf%?e\\t%0, %1, %2 412: suf%?e\\t%0, %1, #%N2" 413: [(set_attr "type" "farith")]) 1.1 root 414: 415: (define_insn "subdi3" 1.1.1.2 root 416: [(set (match_operand:DI 0 "s_register_operand" "=&r,&r,&r") 417: (minus:DI (match_operand:DI 1 "s_register_operand" "0,r,0") 418: (match_operand:DI 2 "s_register_operand" "r,0,0"))) 419: (clobber (reg:CC 24))] 1.1 root 420: "" 1.1.1.3 root 421: "subs\\t%0, %1, %2\;sbc\\t%R0, %R1, %R2" 1.1.1.2 root 422: [(set_attr "conds" "clob") 1.1.1.3 root 423: (set_attr "length" "8")]) 1.1.1.2 root 424: 425: (define_insn "" 426: [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 427: (minus:DI (match_operand:DI 1 "s_register_operand" "?r,0") 428: (zero_extend:DI 429: (match_operand:SI 2 "s_register_operand" "r,r")))) 430: (clobber (reg:CC 24))] 431: "" 1.1.1.3 root 432: "subs\\t%0, %1, %2\;sbc\\t%R0, %R1, #0" 1.1.1.2 root 433: [(set_attr "conds" "clob") 1.1.1.3 root 434: (set_attr "length" "8")]) 1.1.1.2 root 435: 436: (define_insn "" 437: [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 438: (minus:DI (match_operand:DI 1 "s_register_operand" "r,0") 439: (sign_extend:DI 440: (match_operand:SI 2 "s_register_operand" "r,r")))) 441: (clobber (reg:CC 24))] 442: "" 1.1.1.3 root 443: "subs\\t%0, %1, %2\;sbc\\t%R0, %R1, %2, asr #31" 1.1.1.2 root 444: [(set_attr "conds" "clob") 1.1.1.3 root 445: (set_attr "length" "8")]) 1.1.1.2 root 446: 447: (define_insn "" 448: [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 449: (minus:DI (zero_extend:DI 450: (match_operand:SI 2 "s_register_operand" "r,r")) 451: (match_operand:DI 1 "s_register_operand" "?r,0"))) 452: (clobber (reg:CC 24))] 453: "" 1.1.1.3 root 454: "rsbs\\t%0, %1, %2\;rsc\\t%R0, %R1, #0" 1.1.1.2 root 455: [(set_attr "conds" "clob") 1.1.1.3 root 456: (set_attr "length" "8")]) 1.1.1.2 root 457: 458: (define_insn "" 459: [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 460: (minus:DI (sign_extend:DI 461: (match_operand:SI 2 "s_register_operand" "r,r")) 462: (match_operand:DI 1 "s_register_operand" "?r,0"))) 463: (clobber (reg:CC 24))] 464: "" 1.1.1.3 root 465: "rsbs\\t%0, %1, %2\;rsc\\t%R0, %R1, %2, asr #31" 1.1.1.2 root 466: [(set_attr "conds" "clob") 1.1.1.3 root 467: (set_attr "length" "8")]) 1.1.1.2 root 468: 469: (define_insn "" 470: [(set (match_operand:DI 0 "s_register_operand" "=r") 471: (minus:DI (zero_extend:DI 472: (match_operand:SI 1 "s_register_operand" "r")) 473: (zero_extend:DI 474: (match_operand:SI 2 "s_register_operand" "r")))) 475: (clobber (reg:CC 24))] 476: "" 1.1.1.3 root 477: "subs\\t%0, %1, %2\;rsc\\t%R0, %1, %1" 1.1.1.2 root 478: [(set_attr "conds" "clob") 1.1.1.3 root 479: (set_attr "length" "8")]) 1.1 root 480: 1.1.1.3 root 481: (define_expand "subsi3" 482: [(set (match_operand:SI 0 "s_register_operand" "") 483: (minus:SI (match_operand:SI 1 "reg_or_int_operand" "") 484: (match_operand:SI 2 "s_register_operand" "")))] 1.1 root 485: "" 1.1.1.3 root 486: " 487: if (GET_CODE (operands[1]) == CONST_INT) 1.1 root 488: { 1.1.1.3 root 489: arm_split_constant (MINUS, SImode, INTVAL (operands[1]), operands[0], 490: operands[2], 491: (reload_in_progress || reload_completed ? 0 492: : preserve_subexpressions_p ())); 493: DONE; 1.1 root 494: } 495: ") 496: 1.1.1.2 root 497: (define_insn "" 1.1.1.3 root 498: [(set (match_operand:SI 0 "s_register_operand" "=r,r") 499: (minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,?n") 500: (match_operand:SI 2 "s_register_operand" "r,r")))] 501: "" 502: "@ 503: rsb%?\\t%0, %2, %1 504: #" 505: [(set_attr "length" "4,16")]) 506: 507: (define_split 508: [(set (match_operand:SI 0 "s_register_operand" "") 509: (minus:SI (match_operand:SI 1 "const_int_operand" "") 510: (match_operand:SI 2 "s_register_operand" "")))] 511: "! const_ok_for_arm (INTVAL (operands[1]))" 512: [(clobber (const_int 0))] 513: " 514: arm_split_constant (MINUS, SImode, INTVAL (operands[1]), operands[0], 515: operands[2], 0); 516: DONE; 517: ") 518: 519: (define_insn "" 1.1.1.2 root 520: [(set (reg:CC_NOOV 24) 521: (compare:CC_NOOV (minus:SI (match_operand:SI 1 "arm_rhs_operand" "r,I") 522: (match_operand:SI 2 "arm_rhs_operand" "rI,r")) 523: (const_int 0))) 524: (set (match_operand:SI 0 "s_register_operand" "=r,r") 525: (minus:SI (match_dup 1) (match_dup 2)))] 526: "" 1.1.1.3 root 527: "@ 528: sub%?s\\t%0, %1, %2 529: rsb%?s\\t%0, %2, %1" 1.1.1.2 root 530: [(set_attr "conds" "set")]) 531: 532: (define_insn "decscc" 533: [(set (match_operand:SI 0 "s_register_operand" "=r,r") 534: (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r") 535: (match_operator:SI 2 "comparison_operator" 536: [(reg 24) (const_int 0)])))] 537: "" 1.1.1.3 root 538: "@ 539: sub%d2\\t%0, %1, #1 540: mov%D2\\t%0, %1\;sub%d2\\t%0, %1, #1" 1.1.1.2 root 541: [(set_attr "conds" "use") 1.1.1.3 root 542: (set_attr "length" "*,8")]) 1.1.1.2 root 543: 1.1 root 544: (define_insn "subsf3" 1.1.1.2 root 545: [(set (match_operand:SF 0 "s_register_operand" "=f,f") 1.1 root 546: (minus:SF (match_operand:SF 1 "fpu_rhs_operand" "f,G") 547: (match_operand:SF 2 "fpu_rhs_operand" "fG,f")))] 1.1.1.4 root 548: "TARGET_HARD_FLOAT" 1.1.1.3 root 549: "@ 550: suf%?s\\t%0, %1, %2 551: rsf%?s\\t%0, %2, %1" 552: [(set_attr "type" "farith")]) 1.1 root 553: 554: (define_insn "subdf3" 1.1.1.2 root 555: [(set (match_operand:DF 0 "s_register_operand" "=f,f") 1.1 root 556: (minus:DF (match_operand:DF 1 "fpu_rhs_operand" "f,G") 1.1.1.2 root 557: (match_operand:DF 2 "fpu_rhs_operand" "fG,f")))] 1.1.1.4 root 558: "TARGET_HARD_FLOAT" 1.1.1.3 root 559: "@ 560: suf%?d\\t%0, %1, %2 561: rsf%?d\\t%0, %2, %1" 562: [(set_attr "type" "farith")]) 1.1.1.2 root 563: 564: (define_insn "" 565: [(set (match_operand:DF 0 "s_register_operand" "=f") 566: (minus:DF (float_extend:DF 567: (match_operand:SF 1 "s_register_operand" "f")) 568: (match_operand:DF 2 "fpu_rhs_operand" "fG")))] 1.1.1.4 root 569: "TARGET_HARD_FLOAT" 1.1.1.3 root 570: "suf%?d\\t%0, %1, %2" 571: [(set_attr "type" "farith")]) 1.1.1.2 root 572: 573: (define_insn "" 574: [(set (match_operand:DF 0 "s_register_operand" "=f,f") 575: (minus:DF (match_operand:DF 1 "fpu_rhs_operand" "f,G") 576: (float_extend:DF 577: (match_operand:SF 2 "s_register_operand" "f,f"))))] 1.1.1.4 root 578: "TARGET_HARD_FLOAT" 1.1.1.3 root 579: "@ 580: suf%?d\\t%0, %1, %2 581: rsf%?d\\t%0, %2, %1" 582: [(set_attr "type" "farith")]) 1.1.1.2 root 583: 584: (define_insn "" 585: [(set (match_operand:DF 0 "s_register_operand" "=f") 586: (minus:DF (float_extend:DF 587: (match_operand:SF 1 "s_register_operand" "f")) 588: (float_extend:DF 589: (match_operand:SF 2 "s_register_operand" "f"))))] 1.1.1.4 root 590: "TARGET_HARD_FLOAT" 1.1.1.3 root 591: "suf%?d\\t%0, %1, %2" 592: [(set_attr "type" "farith")]) 1.1.1.2 root 593: 594: (define_insn "subxf3" 595: [(set (match_operand:XF 0 "s_register_operand" "=f,f") 596: (minus:XF (match_operand:XF 1 "fpu_rhs_operand" "f,G") 597: (match_operand:XF 2 "fpu_rhs_operand" "fG,f")))] 1.1.1.4 root 598: "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" 1.1.1.3 root 599: "@ 600: suf%?e\\t%0, %1, %2 601: rsf%?e\\t%0, %2, %1" 602: [(set_attr "type" "farith")]) 1.1 root 603: 604: ;; Multiplication insns 605: 1.1.1.2 root 606: ;; Use `&' and then `0' to prevent the operands 0 and 1 being the same 1.1 root 607: (define_insn "mulsi3" 1.1.1.2 root 608: [(set (match_operand:SI 0 "s_register_operand" "=&r,&r") 609: (mult:SI (match_operand:SI 2 "s_register_operand" "r,r") 610: (match_operand:SI 1 "s_register_operand" "%?r,0")))] 1.1 root 611: "" 1.1.1.3 root 612: "mul%?\\t%0, %2, %1") 1.1 root 613: 1.1.1.2 root 614: (define_insn "" 615: [(set (reg:CC_NOOV 24) 616: (compare:CC_NOOV (mult:SI 617: (match_operand:SI 2 "s_register_operand" "r,r") 618: (match_operand:SI 1 "s_register_operand" "%?r,0")) 619: (const_int 0))) 620: (set (match_operand:SI 0 "s_register_operand" "=&r,&r") 621: (mult:SI (match_dup 2) (match_dup 1)))] 622: "" 1.1.1.3 root 623: "mul%?s\\t%0, %2, %1" 1.1.1.2 root 624: [(set_attr "conds" "set")]) 625: 626: (define_insn "" 627: [(set (reg:CC_NOOV 24) 628: (compare:CC_NOOV (mult:SI 629: (match_operand:SI 2 "s_register_operand" "r,r") 630: (match_operand:SI 1 "s_register_operand" "%?r,0")) 631: (const_int 0))) 632: (clobber (match_scratch:SI 0 "=&r,&r"))] 633: "" 1.1.1.3 root 634: "mul%?s\\t%0, %2, %1" 1.1.1.2 root 635: [(set_attr "conds" "set")]) 636: 1.1 root 637: ;; Unnamed templates to match MLA instruction. 638: 639: (define_insn "" 1.1.1.2 root 640: [(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r") 1.1 root 641: (plus:SI 1.1.1.2 root 642: (mult:SI (match_operand:SI 2 "s_register_operand" "r,r,r,r") 643: (match_operand:SI 1 "s_register_operand" "%r,0,r,0")) 644: (match_operand:SI 3 "s_register_operand" "?r,r,0,0")))] 1.1 root 645: "" 1.1.1.3 root 646: "mla%?\\t%0, %2, %1, %3") 1.1 root 647: 648: (define_insn "" 1.1.1.2 root 649: [(set (reg:CC_NOOV 24) 650: (compare:CC_NOOV (plus:SI 651: (mult:SI 652: (match_operand:SI 2 "s_register_operand" "r,r,r,r") 653: (match_operand:SI 1 "s_register_operand" "%r,0,r,0")) 654: (match_operand:SI 3 "s_register_operand" "?r,r,0,0")) 655: (const_int 0))) 656: (set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r") 657: (plus:SI (mult:SI (match_dup 2) (match_dup 1)) 658: (match_dup 3)))] 1.1 root 659: "" 1.1.1.3 root 660: "mla%?s\\t%0, %2, %1, %3" 1.1.1.2 root 661: [(set_attr "conds" "set")]) 662: 663: (define_insn "" 664: [(set (reg:CC_NOOV 24) 665: (compare:CC_NOOV (plus:SI 666: (mult:SI 667: (match_operand:SI 2 "s_register_operand" "r,r,r,r") 668: (match_operand:SI 1 "s_register_operand" "%r,0,r,0")) 669: (match_operand:SI 3 "s_register_operand" "?r,r,0,0")) 670: (const_int 0))) 671: (clobber (match_scratch:SI 0 "=&r,&r,&r,&r"))] 672: "" 1.1.1.3 root 673: "mla%?s\\t%0, %2, %1, %3" 1.1.1.2 root 674: [(set_attr "conds" "set")]) 1.1 root 675: 676: (define_insn "mulsf3" 1.1.1.2 root 677: [(set (match_operand:SF 0 "s_register_operand" "=f") 678: (mult:SF (match_operand:SF 1 "s_register_operand" "f") 1.1 root 679: (match_operand:SF 2 "fpu_rhs_operand" "fG")))] 1.1.1.4 root 680: "TARGET_HARD_FLOAT" 1.1.1.3 root 681: "fml%?s\\t%0, %1, %2" 682: [(set_attr "type" "ffmul")]) 1.1 root 683: 684: (define_insn "muldf3" 1.1.1.2 root 685: [(set (match_operand:DF 0 "s_register_operand" "=f") 686: (mult:DF (match_operand:DF 1 "s_register_operand" "f") 1.1 root 687: (match_operand:DF 2 "fpu_rhs_operand" "fG")))] 1.1.1.4 root 688: "TARGET_HARD_FLOAT" 1.1.1.3 root 689: "muf%?d\\t%0, %1, %2" 690: [(set_attr "type" "fmul")]) 1.1.1.2 root 691: 692: (define_insn "" 693: [(set (match_operand:DF 0 "s_register_operand" "=f") 694: (mult:DF (float_extend:DF 695: (match_operand:SF 1 "s_register_operand" "f")) 696: (match_operand:DF 2 "fpu_rhs_operand" "fG")))] 1.1.1.4 root 697: "TARGET_HARD_FLOAT" 1.1.1.3 root 698: "muf%?d\\t%0, %1, %2" 699: [(set_attr "type" "fmul")]) 1.1.1.2 root 700: 701: (define_insn "" 702: [(set (match_operand:DF 0 "s_register_operand" "=f") 703: (mult:DF (match_operand:DF 1 "s_register_operand" "f") 704: (float_extend:DF 705: (match_operand:SF 2 "s_register_operand" "f"))))] 1.1.1.4 root 706: "TARGET_HARD_FLOAT" 1.1.1.3 root 707: "muf%?d\\t%0, %1, %2" 708: [(set_attr "type" "fmul")]) 1.1.1.2 root 709: 710: (define_insn "" 711: [(set (match_operand:DF 0 "s_register_operand" "=f") 712: (mult:DF (float_extend:DF 713: (match_operand:SF 1 "s_register_operand" "f")) 714: (float_extend:DF 715: (match_operand:SF 2 "s_register_operand" "f"))))] 1.1.1.4 root 716: "TARGET_HARD_FLOAT" 1.1.1.3 root 717: "muf%?d\\t%0, %1, %2" 718: [(set_attr "type" "fmul")]) 1.1.1.2 root 719: 720: (define_insn "mulxf3" 721: [(set (match_operand:XF 0 "s_register_operand" "=f") 722: (mult:XF (match_operand:XF 1 "s_register_operand" "f") 723: (match_operand:XF 2 "fpu_rhs_operand" "fG")))] 1.1.1.4 root 724: "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" 1.1.1.3 root 725: "muf%?e\\t%0, %1, %2" 726: [(set_attr "type" "fmul")]) 1.1 root 727: 728: ;; Division insns 729: 730: (define_insn "divsf3" 1.1.1.2 root 731: [(set (match_operand:SF 0 "s_register_operand" "=f,f") 1.1 root 732: (div:SF (match_operand:SF 1 "fpu_rhs_operand" "f,G") 733: (match_operand:SF 2 "fpu_rhs_operand" "fG,f")))] 1.1.1.4 root 734: "TARGET_HARD_FLOAT" 1.1.1.3 root 735: "@ 736: fdv%?s\\t%0, %1, %2 737: frd%?s\\t%0, %2, %1" 738: [(set_attr "type" "fdivs")]) 1.1 root 739: 740: (define_insn "divdf3" 1.1.1.2 root 741: [(set (match_operand:DF 0 "s_register_operand" "=f,f") 1.1 root 742: (div:DF (match_operand:DF 1 "fpu_rhs_operand" "f,G") 743: (match_operand:DF 2 "fpu_rhs_operand" "fG,f")))] 1.1.1.4 root 744: "TARGET_HARD_FLOAT" 1.1.1.3 root 745: "@ 746: dvf%?d\\t%0, %1, %2 747: rdf%?d\\t%0, %2, %1" 748: [(set_attr "type" "fdivd")]) 1.1.1.2 root 749: 750: (define_insn "" 751: [(set (match_operand:DF 0 "s_register_operand" "=f") 752: (div:DF (float_extend:DF 753: (match_operand:SF 1 "s_register_operand" "f")) 754: (match_operand:DF 2 "fpu_rhs_operand" "fG")))] 1.1.1.4 root 755: "TARGET_HARD_FLOAT" 1.1.1.3 root 756: "dvf%?d\\t%0, %1, %2" 757: [(set_attr "type" "fdivd")]) 1.1.1.2 root 758: 759: (define_insn "" 760: [(set (match_operand:DF 0 "s_register_operand" "=f") 761: (div:DF (match_operand:DF 1 "fpu_rhs_operand" "fG") 762: (float_extend:DF 763: (match_operand:SF 2 "s_register_operand" "f"))))] 1.1.1.4 root 764: "TARGET_HARD_FLOAT" 1.1.1.3 root 765: "rdf%?d\\t%0, %2, %1" 766: [(set_attr "type" "fdivd")]) 1.1.1.2 root 767: 768: (define_insn "" 769: [(set (match_operand:DF 0 "s_register_operand" "=f") 770: (div:DF (float_extend:DF 771: (match_operand:SF 1 "s_register_operand" "f")) 772: (float_extend:DF 773: (match_operand:SF 2 "s_register_operand" "f"))))] 1.1.1.4 root 774: "TARGET_HARD_FLOAT" 1.1.1.3 root 775: "dvf%?d\\t%0, %1, %2" 776: [(set_attr "type" "fdivd")]) 1.1.1.2 root 777: 778: (define_insn "divxf3" 779: [(set (match_operand:XF 0 "s_register_operand" "=f,f") 780: (div:XF (match_operand:XF 1 "fpu_rhs_operand" "f,G") 781: (match_operand:XF 2 "fpu_rhs_operand" "fG,f")))] 1.1.1.4 root 782: "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" 1.1.1.3 root 783: "@ 784: dvf%?e\\t%0, %1, %2 785: rdf%?e\\t%0, %2, %1" 786: [(set_attr "type" "fdivx")]) 1.1 root 787: 788: ;; Modulo insns 789: 790: (define_insn "modsf3" 1.1.1.2 root 791: [(set (match_operand:SF 0 "s_register_operand" "=f") 792: (mod:SF (match_operand:SF 1 "s_register_operand" "f") 1.1 root 793: (match_operand:SF 2 "fpu_rhs_operand" "fG")))] 1.1.1.4 root 794: "TARGET_HARD_FLOAT" 1.1.1.3 root 795: "rmf%?s\\t%0, %1, %2" 796: [(set_attr "type" "fdivs")]) 1.1 root 797: 798: (define_insn "moddf3" 1.1.1.2 root 799: [(set (match_operand:DF 0 "s_register_operand" "=f") 800: (mod:DF (match_operand:DF 1 "s_register_operand" "f") 1.1 root 801: (match_operand:DF 2 "fpu_rhs_operand" "fG")))] 1.1.1.4 root 802: "TARGET_HARD_FLOAT" 1.1.1.3 root 803: "rmf%?d\\t%0, %1, %2" 804: [(set_attr "type" "fdivd")]) 1.1.1.2 root 805: 806: (define_insn "" 807: [(set (match_operand:DF 0 "s_register_operand" "=f") 808: (mod:DF (float_extend:DF 809: (match_operand:SF 1 "s_register_operand" "f")) 810: (match_operand:DF 2 "fpu_rhs_operand" "fG")))] 1.1.1.4 root 811: "TARGET_HARD_FLOAT" 1.1.1.3 root 812: "rmf%?d\\t%0, %1, %2" 813: [(set_attr "type" "fdivd")]) 1.1.1.2 root 814: 815: (define_insn "" 816: [(set (match_operand:DF 0 "s_register_operand" "=f") 817: (mod:DF (match_operand:DF 1 "s_register_operand" "f") 818: (float_extend:DF 819: (match_operand:SF 2 "s_register_operand" "f"))))] 1.1.1.4 root 820: "TARGET_HARD_FLOAT" 1.1.1.3 root 821: "rmf%?d\\t%0, %1, %2" 822: [(set_attr "type" "fdivd")]) 1.1.1.2 root 823: 824: (define_insn "" 825: [(set (match_operand:DF 0 "s_register_operand" "=f") 826: (mod:DF (float_extend:DF 827: (match_operand:SF 1 "s_register_operand" "f")) 828: (float_extend:DF 829: (match_operand:SF 2 "s_register_operand" "f"))))] 1.1.1.4 root 830: "TARGET_HARD_FLOAT" 1.1.1.3 root 831: "rmf%?d\\t%0, %1, %2" 832: [(set_attr "type" "fdivd")]) 1.1.1.2 root 833: 834: (define_insn "modxf3" 835: [(set (match_operand:XF 0 "s_register_operand" "=f") 836: (mod:XF (match_operand:XF 1 "s_register_operand" "f") 837: (match_operand:XF 2 "fpu_rhs_operand" "fG")))] 1.1.1.4 root 838: "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" 1.1.1.3 root 839: "rmf%?e\\t%0, %1, %2" 840: [(set_attr "type" "fdivx")]) 1.1 root 841: 842: ;; Boolean and,ior,xor insns 843: 844: (define_insn "anddi3" 1.1.1.2 root 845: [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 846: (and:DI (match_operand:DI 1 "s_register_operand" "%0,0") 847: (match_operand:DI 2 "s_register_operand" "r,0")))] 1.1 root 848: "" 1.1.1.3 root 849: "and%?\\t%0, %1, %2\;and%?\\t%R0, %R1, %R2" 850: [(set_attr "length" "8")]) 1.1 root 851: 1.1.1.2 root 852: (define_insn "" 853: [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 854: (and:DI (zero_extend:DI 855: (match_operand:SI 2 "s_register_operand" "r,r")) 856: (match_operand:DI 1 "s_register_operand" "?r,0")))] 1.1 root 857: "" 1.1.1.3 root 858: "and%?\\t%0, %1, %2\;mov%?\\t%R0, #0" 859: [(set_attr "length" "8")]) 1.1 root 860: 1.1.1.2 root 861: (define_insn "" 862: [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 863: (and:DI (sign_extend:DI 864: (match_operand:SI 2 "s_register_operand" "r,r")) 865: (match_operand:DI 1 "s_register_operand" "?r,0")))] 1.1 root 866: "" 1.1.1.3 root 867: "and%?\\t%0, %1, %2\;and%?\\t%R0, %R1, %2, asr #31" 868: [(set_attr "length" "8")]) 1.1 root 869: 1.1.1.3 root 870: (define_expand "andsi3" 871: [(set (match_operand:SI 0 "s_register_operand" "") 872: (and:SI (match_operand:SI 1 "s_register_operand" "") 873: (match_operand:SI 2 "reg_or_int_operand" "")))] 1.1 root 874: "" 1.1.1.3 root 875: " 876: if (GET_CODE (operands[2]) == CONST_INT) 1.1.1.2 root 877: { 1.1.1.3 root 878: arm_split_constant (AND, SImode, INTVAL (operands[2]), operands[0], 879: operands[1], 880: (reload_in_progress || reload_completed 881: ? 0 : preserve_subexpressions_p ())); 882: DONE; 1.1.1.2 root 883: } 1.1 root 884: ") 885: 1.1.1.2 root 886: (define_insn "" 1.1.1.3 root 887: [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") 888: (and:SI (match_operand:SI 1 "s_register_operand" "r,r,r") 889: (match_operand:SI 2 "reg_or_int_operand" "rI,K,?n")))] 1.1 root 890: "" 1.1.1.3 root 891: "@ 892: and%?\\t%0, %1, %2 893: bic%?\\t%0, %1, #%B2 894: #" 895: [(set_attr "length" "4,4,16")]) 896: 897: (define_split 898: [(set (match_operand:SI 0 "s_register_operand" "") 899: (and:SI (match_operand:SI 1 "s_register_operand" "") 900: (match_operand:SI 2 "const_int_operand" "")))] 901: "! (const_ok_for_arm (INTVAL (operands[2])) 902: || const_ok_for_arm (~ INTVAL (operands[2])))" 903: [(clobber (const_int 0))] 904: " 905: arm_split_constant (AND, SImode, INTVAL (operands[2]), operands[0], 906: operands[1], 0); 907: DONE; 908: ") 1.1.1.2 root 909: 910: (define_insn "" 911: [(set (reg:CC_NOOV 24) 1.1.1.3 root 912: (compare:CC_NOOV 913: (and:SI (match_operand:SI 1 "s_register_operand" "r,r") 914: (match_operand:SI 2 "arm_not_operand" "rI,K")) 915: (const_int 0))) 916: (set (match_operand:SI 0 "s_register_operand" "=r,r") 917: (and:SI (match_dup 1) (match_dup 2)))] 1.1.1.2 root 918: "" 1.1.1.3 root 919: "@ 920: and%?s\\t%0, %1, %2 921: bic%?s\\t%0, %1, #%B2" 1.1.1.2 root 922: [(set_attr "conds" "set")]) 923: 924: (define_insn "" 925: [(set (reg:CC_NOOV 24) 1.1.1.3 root 926: (compare:CC_NOOV 927: (and:SI (match_operand:SI 0 "s_register_operand" "r,r") 928: (match_operand:SI 1 "arm_not_operand" "rI,K")) 929: (const_int 0))) 930: (clobber (match_scratch:SI 3 "=X,r"))] 931: "" 932: "@ 933: tst%?\\t%0, %1 934: bic%?s\\t%3, %0, #%B1" 1.1.1.2 root 935: [(set_attr "conds" "set")]) 936: 937: (define_insn "" 938: [(set (reg:CC_NOOV 24) 939: (compare:CC_NOOV (zero_extract:SI 940: (match_operand:SI 0 "s_register_operand" "r") 941: (match_operand:SI 1 "immediate_operand" "n") 942: (match_operand:SI 2 "immediate_operand" "n")) 943: (const_int 0)))] 944: "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32 945: && INTVAL (operands[1]) > 0 946: && INTVAL (operands[1]) + (INTVAL (operands[2]) & 1) <= 8 947: && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32" 948: "* 949: { 950: unsigned int mask = 0; 951: int cnt = INTVAL (operands[1]); 952: 953: while (cnt--) 954: mask = (mask << 1) | 1; 1.1.1.3 root 955: operands[1] = GEN_INT (mask << INTVAL (operands[2])); 956: output_asm_insn (\"tst%?\\t%0, %1\", operands); 957: return \"\"; 1.1.1.2 root 958: } 959: " 960: [(set_attr "conds" "set")]) 961: 962: (define_insn "" 963: [(set (reg:CC_NOOV 24) 964: (compare:CC_NOOV (zero_extract:SI 965: (match_operand:QI 0 "memory_operand" "m") 966: (match_operand 1 "immediate_operand" "n") 967: (match_operand 2 "immediate_operand" "n")) 968: (const_int 0))) 969: (clobber (match_scratch:QI 3 "=r"))] 970: "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 8 971: && INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8" 972: "* 973: { 974: unsigned int mask = 0; 975: int cnt = INTVAL (operands[1]); 976: 977: while (cnt--) 978: mask = (mask << 1) | 1; 1.1.1.3 root 979: operands[1] = GEN_INT (mask << INTVAL (operands[2])); 980: output_asm_insn (\"ldr%?b\\t%3, %0\", operands); 981: output_asm_insn (\"tst%?\\t%3, %1\", operands); 982: return \"\"; 1.1.1.2 root 983: } 984: " 985: [(set_attr "conds" "set") 1.1.1.3 root 986: (set_attr "length" "8")]) 1.1.1.2 root 987: 988: ;; constants for op 2 will never be given to these patterns. 989: (define_insn "" 990: [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 991: (and:DI (not:DI (match_operand:DI 2 "s_register_operand" "r,0")) 992: (match_operand:DI 1 "s_register_operand" "0,r")))] 993: "" 1.1.1.3 root 994: "bic%?\\t%0, %1, %2\;bic%?\\t%R0, %R1, %R2" 995: [(set_attr "length" "8")]) 1.1.1.2 root 996: 997: (define_insn "" 998: [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 999: (and:DI (not:DI (zero_extend:DI 1000: (match_operand:SI 2 "s_register_operand" "r,r"))) 1.1.1.3 root 1001: (match_operand:DI 1 "s_register_operand" "0,?r")))] 1.1.1.2 root 1002: "" 1.1.1.3 root 1003: "@ 1004: bic%?\\t%0, %1, %2 1005: bic%?\\t%0, %1, %2\;mov%?\\t%R0, %R1" 1006: [(set_attr "length" "4,8")]) 1.1.1.2 root 1007: 1008: (define_insn "" 1009: [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 1010: (and:DI (not:DI (sign_extend:DI 1011: (match_operand:SI 2 "s_register_operand" "r,r"))) 1012: (match_operand:DI 1 "s_register_operand" "?r,0")))] 1013: "" 1.1.1.3 root 1014: "bic%?\\t%0, %1, %2\;bic%?\\t%R0, %R1, %2, asr #31" 1015: [(set_attr "length" "8")]) 1.1.1.2 root 1016: 1017: (define_insn "" 1018: [(set (match_operand:SI 0 "s_register_operand" "=r") 1019: (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r")) 1020: (match_operand:SI 1 "s_register_operand" "r")))] 1021: "" 1.1.1.3 root 1022: "bic%?\\t%0, %1, %2") 1.1.1.2 root 1023: 1024: (define_insn "" 1025: [(set (reg:CC_NOOV 24) 1.1.1.3 root 1026: (compare:CC_NOOV 1027: (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r")) 1028: (match_operand:SI 1 "s_register_operand" "r")) 1029: (const_int 0))) 1.1.1.2 root 1030: (set (match_operand:SI 0 "s_register_operand" "=r") 1031: (and:SI (not:SI (match_dup 2)) (match_dup 1)))] 1032: "" 1.1.1.3 root 1033: "bic%?s\\t%0, %1, %2" 1.1.1.2 root 1034: [(set_attr "conds" "set")]) 1035: 1036: (define_insn "" 1037: [(set (reg:CC_NOOV 24) 1.1.1.3 root 1038: (compare:CC_NOOV 1039: (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r")) 1040: (match_operand:SI 1 "s_register_operand" "r")) 1041: (const_int 0))) 1.1.1.2 root 1042: (clobber (match_scratch:SI 0 "=r"))] 1043: "" 1.1.1.3 root 1044: "bic%?s\\t%0, %1, %2" 1.1.1.2 root 1045: [(set_attr "conds" "set")]) 1046: 1047: (define_insn "iordi3" 1048: [(set (match_operand:DI 0 "s_register_operand" "=&r") 1049: (ior:DI (match_operand:DI 1 "s_register_operand" "%0") 1050: (match_operand:DI 2 "s_register_operand" "r")))] 1051: "" 1.1.1.3 root 1052: "orr%?\\t%0, %1, %2\;orr%?\\t%R0, %R1, %R2" 1053: [(set_attr "length" "8")]) 1.1.1.2 root 1054: 1055: (define_insn "" 1056: [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 1057: (ior:DI (zero_extend:DI 1058: (match_operand:SI 2 "s_register_operand" "r,r")) 1.1.1.3 root 1059: (match_operand:DI 1 "s_register_operand" "0,?r")))] 1.1.1.2 root 1060: "" 1.1.1.3 root 1061: "@ 1062: orr%?\\t%0, %1, %2 1063: orr%?\\t%0, %1, %2\;mov%?\\t%R0, %R1" 1064: [(set_attr "length" "4,8")]) 1.1.1.2 root 1065: 1066: (define_insn "" 1067: [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 1068: (ior:DI (sign_extend:DI 1069: (match_operand:SI 2 "s_register_operand" "r,r")) 1070: (match_operand:DI 1 "s_register_operand" "?r,0")))] 1071: "" 1.1.1.3 root 1072: "orr%?\\t%0, %1, %2\;orr%?\\t%R0, %R1, %2, asr #31" 1073: [(set_attr "length" "8")]) 1.1.1.2 root 1074: 1.1.1.3 root 1075: (define_expand "iorsi3" 1076: [(set (match_operand:SI 0 "s_register_operand" "") 1077: (ior:SI (match_operand:SI 1 "s_register_operand" "") 1078: (match_operand:SI 2 "reg_or_int_operand" "")))] 1.1.1.2 root 1079: "" 1.1.1.3 root 1080: " 1081: if (GET_CODE (operands[2]) == CONST_INT) 1082: { 1083: arm_split_constant (IOR, SImode, INTVAL (operands[2]), operands[0], 1084: operands[1], 1085: (reload_in_progress || reload_completed 1086: ? 0 : preserve_subexpressions_p ())); 1087: DONE; 1088: } 1.1.1.2 root 1089: ") 1090: 1091: (define_insn "" 1.1.1.3 root 1092: [(set (match_operand:SI 0 "s_register_operand" "=r,r") 1093: (ior:SI (match_operand:SI 1 "s_register_operand" "r,r") 1094: (match_operand:SI 2 "reg_or_int_operand" "rI,?n")))] 1095: "" 1096: "@ 1097: orr%?\\t%0, %1, %2 1098: #" 1099: [(set_attr "length" "4,16")]) 1100: 1101: (define_split 1102: [(set (match_operand:SI 0 "s_register_operand" "") 1103: (ior:SI (match_operand:SI 1 "s_register_operand" "") 1104: (match_operand:SI 2 "const_int_operand" "")))] 1105: "! const_ok_for_arm (INTVAL (operands[2]))" 1106: [(clobber (const_int 0))] 1107: " 1108: arm_split_constant (IOR, SImode, INTVAL (operands[2]), operands[0], 1109: operands[1], 0); 1110: DONE; 1111: ") 1112: 1113: (define_insn "" 1.1.1.2 root 1114: [(set (reg:CC_NOOV 24) 1115: (compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r") 1116: (match_operand:SI 2 "arm_rhs_operand" "rI")) 1117: (const_int 0))) 1118: (set (match_operand:SI 0 "s_register_operand" "=r") 1119: (ior:SI (match_dup 1) (match_dup 2)))] 1120: "" 1.1.1.3 root 1121: "orr%?s\\t%0, %1, %2" 1.1.1.2 root 1122: [(set_attr "conds" "set")]) 1123: 1124: (define_insn "" 1125: [(set (reg:CC_NOOV 24) 1126: (compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r") 1127: (match_operand:SI 2 "arm_rhs_operand" "rI")) 1128: (const_int 0))) 1129: (clobber (match_scratch:SI 0 "=r"))] 1130: "" 1.1.1.3 root 1131: "orr%?s\\t%0, %1, %2" 1.1.1.2 root 1132: [(set_attr "conds" "set")]) 1133: 1134: (define_insn "xordi3" 1135: [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 1136: (xor:DI (match_operand:DI 1 "s_register_operand" "%0,0") 1137: (match_operand:DI 2 "s_register_operand" "r,0")))] 1138: "" 1.1.1.3 root 1139: "eor%?\\t%0, %1, %2\;eor%?\\t%R0, %R1, %R2" 1140: [(set_attr "length" "8")]) 1.1.1.2 root 1141: 1142: (define_insn "" 1143: [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 1144: (xor:DI (zero_extend:DI 1145: (match_operand:SI 2 "s_register_operand" "r,r")) 1.1.1.3 root 1146: (match_operand:DI 1 "s_register_operand" "0,?r")))] 1.1.1.2 root 1147: "" 1.1.1.3 root 1148: "@ 1149: eor%?\\t%0, %1, %2 1150: eor%?\\t%0, %1, %2\;mov%?\\t%R0, %R1" 1151: [(set_attr "length" "4,8")]) 1.1.1.2 root 1152: 1153: (define_insn "" 1154: [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 1155: (xor:DI (sign_extend:DI 1156: (match_operand:SI 2 "s_register_operand" "r,r")) 1157: (match_operand:DI 1 "s_register_operand" "?r,0")))] 1158: "" 1.1.1.3 root 1159: "eor%?\\t%0, %1, %2\;eor%?\\t%R0, %R1, %2, asr #31" 1160: [(set_attr "length" "8")]) 1.1 root 1161: 1162: (define_insn "xorsi3" 1.1.1.2 root 1163: [(set (match_operand:SI 0 "s_register_operand" "=r") 1164: (xor:SI (match_operand:SI 1 "s_register_operand" "r") 1165: (match_operand:SI 2 "arm_rhs_operand" "rI")))] 1.1 root 1166: "" 1.1.1.3 root 1167: "eor%?\\t%0, %1, %2") 1.1.1.2 root 1168: 1169: (define_insn "" 1170: [(set (reg:CC_NOOV 24) 1171: (compare:CC_NOOV (xor:SI (match_operand:SI 1 "s_register_operand" "r") 1172: (match_operand:SI 2 "arm_rhs_operand" "rI")) 1173: (const_int 0))) 1174: (set (match_operand:SI 0 "s_register_operand" "=r") 1175: (xor:SI (match_dup 1) (match_dup 2)))] 1176: "" 1.1.1.3 root 1177: "eor%?s\\t%0, %1, %2" 1.1.1.2 root 1178: [(set_attr "conds" "set")]) 1179: 1180: (define_insn "" 1181: [(set (reg:CC_NOOV 24) 1182: (compare:CC_NOOV (xor:SI (match_operand:SI 0 "s_register_operand" "r") 1183: (match_operand:SI 1 "arm_rhs_operand" "rI")) 1184: (const_int 0)))] 1185: "" 1.1.1.3 root 1186: "teq%?\\t%0, %1" 1.1.1.2 root 1187: [(set_attr "conds" "set")]) 1188: 1189: ;; by splitting (IOR (AND (NOT A) (NOT B)) C) as D = AND (IOR A B) (NOT C), 1190: ;; (NOT D) we can sometimes merge the final NOT into one of the following 1191: ;; insns 1192: 1193: (define_split 1194: [(set (match_operand:SI 0 "s_register_operand" "=r") 1195: (ior:SI (and:SI (not:SI (match_operand:SI 1 "s_register_operand" "r")) 1196: (not:SI (match_operand:SI 2 "arm_rhs_operand" "rI"))) 1197: (match_operand:SI 3 "arm_rhs_operand" "rI"))) 1198: (clobber (match_operand:SI 4 "s_register_operand" "=r"))] 1199: "" 1200: [(set (match_dup 4) (and:SI (ior:SI (match_dup 1) (match_dup 2)) 1201: (not:SI (match_dup 3)))) 1202: (set (match_dup 0) (not:SI (match_dup 4)))] 1203: "" 1204: ) 1205: 1206: (define_insn "" 1207: [(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r") 1208: (and:SI (ior:SI (match_operand:SI 1 "s_register_operand" "r,r,0") 1209: (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")) 1210: (not:SI (match_operand:SI 3 "arm_rhs_operand" "rI,rI,rI"))))] 1211: "" 1.1.1.3 root 1212: "orr%?\\t%0, %1, %2\;bic%?\\t%0, %0, %3" 1213: [(set_attr "length" "8")]) 1.1.1.2 root 1214: 1215: 1216: 1217: ;; Minimum and maximum insns 1218: 1219: (define_insn "smaxsi3" 1220: [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") 1221: (smax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") 1222: (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) 1223: (clobber (reg:CC 24))] 1224: "" 1.1.1.3 root 1225: "@ 1226: cmp\\t%1, %2\;movlt\\t%0, %2 1227: cmp\\t%1, %2\;movge\\t%0, %1 1228: cmp\\t%1, %2\;movge\\t%0, %1\;movlt\\t%0, %2" 1.1.1.2 root 1229: [(set_attr "conds" "clob") 1.1.1.3 root 1230: (set_attr "length" "8,8,12")]) 1.1.1.2 root 1231: 1232: (define_insn "sminsi3" 1233: [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") 1234: (smin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") 1235: (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) 1236: (clobber (reg:CC 24))] 1237: "" 1.1.1.3 root 1238: "@ 1239: cmp\\t%1, %2\;movge\\t%0, %2 1240: cmp\\t%1, %2\;movlt\\t%0, %1 1241: cmp\\t%1, %2\;movlt\\t%0, %1\;movge\\t%0, %2" 1.1.1.2 root 1242: [(set_attr "conds" "clob") 1.1.1.3 root 1243: (set_attr "length" "8,8,12")]) 1.1.1.2 root 1244: 1245: (define_insn "umaxsi3" 1246: [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") 1247: (umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") 1248: (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) 1249: (clobber (reg:CC 24))] 1250: "" 1.1.1.3 root 1251: "@ 1252: cmp\\t%1, %2\;movcc\\t%0, %2 1253: cmp\\t%1, %2\;movcs\\t%0, %1 1254: cmp\\t%1, %2\;movcs\\t%0, %1\;movcc\\t%0, %2" 1.1.1.2 root 1255: [(set_attr "conds" "clob") 1.1.1.3 root 1256: (set_attr "length" "8,8,12")]) 1.1.1.2 root 1257: 1258: (define_insn "uminsi3" 1259: [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") 1260: (umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") 1261: (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) 1262: (clobber (reg:CC 24))] 1263: "" 1.1.1.3 root 1264: "@ 1265: cmp\\t%1, %2\;movcs\\t%0, %2 1266: cmp\\t%1, %2\;movcc\\t%0, %1 1267: cmp\\t%1, %2\;movcc\\t%0, %1\;movcs\\t%0, %2" 1.1.1.2 root 1268: [(set_attr "conds" "clob") 1.1.1.3 root 1269: (set_attr "length" "8,8,12")]) 1.1.1.2 root 1270: 1271: (define_insn "" 1272: [(set (match_operand:SI 0 "memory_operand" "=m") 1273: (match_operator:SI 3 "minmax_operator" 1274: [(match_operand:SI 1 "s_register_operand" "r") 1275: (match_operand:SI 2 "s_register_operand" "r")])) 1276: (clobber (reg:CC 24))] 1277: "" 1278: "* 1279: operands[3] = gen_rtx (minmax_code (operands[3]), SImode, operands[1], 1280: operands[2]); 1.1.1.3 root 1281: output_asm_insn (\"cmp\\t%1, %2\", operands); 1282: output_asm_insn (\"str%d3\\t%1, %0\", operands); 1283: output_asm_insn (\"str%D3\\t%2, %0\", operands); 1284: return \"\"; 1.1.1.2 root 1285: " 1286: [(set_attr "conds" "clob") 1.1.1.3 root 1287: (set_attr "length" "12") 1.1.1.2 root 1288: (set_attr "type" "store1")]) 1289: 1290: (define_insn "" 1291: [(set (match_operand:SI 0 "s_register_operand" "=r,r") 1292: (match_operator:SI 4 "shiftable_operator" 1293: [(match_operator:SI 5 "minmax_operator" 1294: [(match_operand:SI 2 "s_register_operand" "r,r") 1295: (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]) 1296: (match_operand:SI 1 "s_register_operand" "0,?r")])) 1297: (clobber (reg:CC 24))] 1298: "" 1299: "* 1300: { 1301: enum rtx_code code = GET_CODE (operands[4]); 1302: 1303: operands[5] = gen_rtx (minmax_code (operands[5]), SImode, operands[2], 1304: operands[3]); 1.1.1.3 root 1305: output_asm_insn (\"cmp\\t%2, %3\", operands); 1306: output_asm_insn (\"%i4%d5\\t%0, %1, %2\", operands); 1.1.1.2 root 1307: if (which_alternative != 0 || operands[3] != const0_rtx 1308: || (code != PLUS && code != MINUS && code != IOR && code != XOR)) 1.1.1.3 root 1309: output_asm_insn (\"%i4%D5\\t%0, %1, %3\", operands); 1.1.1.2 root 1310: return \"\"; 1311: } 1312: " 1313: [(set_attr "conds" "clob") 1.1.1.3 root 1314: (set_attr "length" "12")]) 1.1.1.2 root 1315: 1.1 root 1316: 1317: ;; Shift and rotation insns 1318: 1.1.1.3 root 1319: (define_expand "ashlsi3" 1320: [(set (match_operand:SI 0 "s_register_operand" "") 1321: (ashift:SI (match_operand:SI 1 "s_register_operand" "") 1322: (match_operand:SI 2 "arm_rhs_operand" "")))] 1.1 root 1323: "" 1.1.1.3 root 1324: " 1325: if (GET_CODE (operands[2]) == CONST_INT 1326: && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31) 1327: { 1328: emit_insn (gen_movsi (operands[0], const0_rtx)); 1329: DONE; 1330: } 1.1 root 1331: ") 1332: 1.1.1.3 root 1333: (define_expand "ashrsi3" 1334: [(set (match_operand:SI 0 "s_register_operand" "") 1335: (ashiftrt:SI (match_operand:SI 1 "s_register_operand" "") 1336: (match_operand:SI 2 "arm_rhs_operand" "")))] 1.1 root 1337: "" 1.1.1.3 root 1338: " 1339: if (GET_CODE (operands[2]) == CONST_INT 1340: && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31) 1341: operands[2] = GEN_INT (31); 1.1 root 1342: ") 1343: 1.1.1.3 root 1344: (define_expand "lshrsi3" 1345: [(set (match_operand:SI 0 "s_register_operand" "") 1346: (lshiftrt:SI (match_operand:SI 1 "s_register_operand" "") 1347: (match_operand:SI 2 "arm_rhs_operand" "")))] 1.1 root 1348: "" 1.1.1.3 root 1349: " 1350: if (GET_CODE (operands[2]) == CONST_INT 1351: && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31) 1352: { 1353: emit_insn (gen_movsi (operands[0], const0_rtx)); 1354: DONE; 1355: } 1.1 root 1356: ") 1357: 1.1.1.3 root 1358: (define_expand "rotlsi3" 1359: [(set (match_operand:SI 0 "s_register_operand" "") 1360: (rotatert:SI (match_operand:SI 1 "s_register_operand" "") 1361: (match_operand:SI 2 "reg_or_int_operand" "")))] 1.1 root 1362: "" 1.1.1.3 root 1363: " 1364: if (GET_CODE (operands[2]) == CONST_INT) 1365: operands[2] = GEN_INT ((32 - INTVAL (operands[2])) % 32); 1366: else 1367: { 1368: rtx reg = gen_reg_rtx (SImode); 1369: emit_insn (gen_subsi3 (reg, GEN_INT (32), operands[2])); 1370: operands[2] = reg; 1371: } 1.1 root 1372: ") 1373: 1.1.1.3 root 1374: (define_expand "rotrsi3" 1375: [(set (match_operand:SI 0 "s_register_operand" "") 1376: (rotatert:SI (match_operand:SI 1 "s_register_operand" "") 1377: (match_operand:SI 2 "arm_rhs_operand" "")))] 1.1 root 1378: "" 1.1.1.3 root 1379: " 1380: if (GET_CODE (operands[2]) == CONST_INT 1381: && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31) 1382: operands[2] = GEN_INT (INTVAL (operands[2]) % 32); 1.1 root 1383: ") 1.1.1.2 root 1384: 1385: (define_insn "" 1.1.1.3 root 1386: [(set (match_operand:SI 0 "s_register_operand" "=r") 1387: (match_operator:SI 3 "shift_operator" 1388: [(match_operand:SI 1 "s_register_operand" "r") 1389: (match_operand:SI 2 "reg_or_int_operand" "rM")]))] 1390: "" 1391: "mov%?\\t%0, %1%S3") 1392: 1393: (define_insn "" 1.1.1.2 root 1394: [(set (reg:CC_NOOV 24) 1.1.1.3 root 1395: (compare:CC_NOOV (match_operator:SI 3 "shift_operator" 1396: [(match_operand:SI 1 "s_register_operand" "r") 1397: (match_operand:SI 2 "arm_rhs_operand" "rM")]) 1.1.1.2 root 1398: (const_int 0))) 1399: (set (match_operand:SI 0 "s_register_operand" "=r") 1.1.1.3 root 1400: (match_op_dup 3 [(match_dup 1) (match_dup 2)]))] 1.1.1.2 root 1401: "" 1.1.1.3 root 1402: "mov%?s\\t%0, %1%S3" 1.1.1.2 root 1403: [(set_attr "conds" "set")]) 1404: 1405: (define_insn "" 1406: [(set (reg:CC_NOOV 24) 1.1.1.3 root 1407: (compare:CC_NOOV (match_operator:SI 3 "shift_operator" 1408: [(match_operand:SI 1 "s_register_operand" "r") 1409: (match_operand:SI 2 "arm_rhs_operand" "rM")]) 1.1.1.2 root 1410: (const_int 0))) 1411: (clobber (match_scratch:SI 0 "=r"))] 1412: "" 1.1.1.3 root 1413: "mov%?s\\t%0, %1%S3" 1.1.1.2 root 1414: [(set_attr "conds" "set")]) 1415: 1416: (define_insn "" 1417: [(set (match_operand:SI 0 "s_register_operand" "=r") 1.1.1.3 root 1418: (not:SI (match_operator:SI 3 "shift_operator" 1419: [(match_operand:SI 1 "s_register_operand" "r") 1420: (match_operand:SI 2 "arm_rhs_operand" "rM")])))] 1.1.1.2 root 1421: "" 1.1.1.3 root 1422: "mvn%?\\t%0, %1%S3") 1.1.1.2 root 1423: 1424: (define_insn "" 1425: [(set (reg:CC_NOOV 24) 1.1.1.3 root 1426: (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator" 1427: [(match_operand:SI 1 "s_register_operand" "r") 1428: (match_operand:SI 2 "arm_rhs_operand" "rM")])) 1.1.1.2 root 1429: (const_int 0))) 1430: (set (match_operand:SI 0 "s_register_operand" "=r") 1.1.1.3 root 1431: (not:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])))] 1.1.1.2 root 1432: "" 1.1.1.3 root 1433: "mvn%?s\\t%0, %1%S3" 1.1.1.2 root 1434: [(set_attr "conds" "set")]) 1435: 1436: (define_insn "" 1437: [(set (reg:CC_NOOV 24) 1.1.1.3 root 1438: (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator" 1439: [(match_operand:SI 1 "s_register_operand" "r") 1440: (match_operand:SI 2 "arm_rhs_operand" "rM")])) 1.1.1.2 root 1441: (const_int 0))) 1442: (clobber (match_scratch:SI 0 "=r"))] 1443: "" 1.1.1.3 root 1444: "mvn%?s\\t%0, %1%S3" 1.1.1.2 root 1445: [(set_attr "conds" "set")]) 1446: 1.1 root 1447: 1448: ;; Unary arithmetic insns 1449: 1450: (define_insn "negdi2" 1.1.1.2 root 1451: [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 1452: (neg:DI (match_operand:DI 1 "s_register_operand" "?r,0")))] 1.1 root 1453: "" 1.1.1.3 root 1454: "rsbs\\t%0, %1, #0\;rsc\\t%R0, %R1, #0" 1.1.1.2 root 1455: [(set_attr "conds" "clob") 1.1.1.3 root 1456: (set_attr "length" "8")]) 1.1 root 1457: 1458: (define_insn "negsi2" 1.1.1.2 root 1459: [(set (match_operand:SI 0 "s_register_operand" "=r") 1460: (neg:SI (match_operand:SI 1 "s_register_operand" "r")))] 1.1 root 1461: "" 1.1.1.3 root 1462: "rsb%?\\t%0, %1, #0") 1.1 root 1463: 1464: (define_insn "negsf2" 1.1.1.2 root 1465: [(set (match_operand:SF 0 "s_register_operand" "=f") 1466: (neg:SF (match_operand:SF 1 "s_register_operand" "f")))] 1.1.1.4 root 1467: "TARGET_HARD_FLOAT" 1.1.1.3 root 1468: "mnf%?s\\t%0, %1" 1469: [(set_attr "type" "ffarith")]) 1.1 root 1470: 1471: (define_insn "negdf2" 1.1.1.2 root 1472: [(set (match_operand:DF 0 "s_register_operand" "=f") 1473: (neg:DF (match_operand:DF 1 "s_register_operand" "f")))] 1.1.1.4 root 1474: "TARGET_HARD_FLOAT" 1.1.1.3 root 1475: "mnf%?d\\t%0, %1" 1476: [(set_attr "type" "ffarith")]) 1.1.1.2 root 1477: 1478: (define_insn "" 1479: [(set (match_operand:DF 0 "s_register_operand" "=f") 1480: (neg:DF (float_extend:DF 1481: (match_operand:SF 1 "s_register_operand" "f"))))] 1.1.1.4 root 1482: "TARGET_HARD_FLOAT" 1.1.1.3 root 1483: "mnf%?d\\t%0, %1" 1484: [(set_attr "type" "ffarith")]) 1.1.1.2 root 1485: 1486: (define_insn "negxf2" 1487: [(set (match_operand:XF 0 "s_register_operand" "=f") 1488: (neg:XF (match_operand:XF 1 "s_register_operand" "f")))] 1.1.1.4 root 1489: "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" 1.1.1.3 root 1490: "mnf%?e\\t%0, %1" 1491: [(set_attr "type" "ffarith")]) 1.1.1.2 root 1492: 1493: ;; abssi2 doesn't really clobber the condition codes if a different register 1494: ;; is being set. To keep things simple, assume during rtl manipulations that 1495: ;; it does, but tell the final scan operator the truth. Similarly for 1496: ;; (neg (abs...)) 1497: 1498: (define_insn "abssi2" 1499: [(set (match_operand:SI 0 "s_register_operand" "=r,&r") 1500: (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))) 1501: (clobber (reg 24))] 1502: "" 1.1.1.3 root 1503: "@ 1504: cmp\\t%0, #0\;rsblt\\t%0, %0, #0 1505: eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31" 1.1.1.2 root 1506: [(set_attr "conds" "clob,*") 1.1.1.3 root 1507: (set_attr "length" "8")]) 1.1.1.2 root 1508: 1509: (define_insn "" 1510: [(set (match_operand:SI 0 "s_register_operand" "=r,&r") 1511: (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))) 1512: (clobber (reg 24))] 1513: "" 1.1.1.3 root 1514: "@ 1515: cmp\\t%0, #0\;rsbgt\\t%0, %0, #0 1516: eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31" 1.1.1.2 root 1517: [(set_attr "conds" "clob,*") 1.1.1.3 root 1518: (set_attr "length" "8")]) 1.1 root 1519: 1520: (define_insn "abssf2" 1.1.1.2 root 1521: [(set (match_operand:SF 0 "s_register_operand" "=f") 1522: (abs:SF (match_operand:SF 1 "s_register_operand" "f")))] 1.1.1.4 root 1523: "TARGET_HARD_FLOAT" 1.1.1.3 root 1524: "abs%?s\\t%0, %1" 1525: [(set_attr "type" "ffarith")]) 1.1 root 1526: 1527: (define_insn "absdf2" 1.1.1.2 root 1528: [(set (match_operand:DF 0 "s_register_operand" "=f") 1529: (abs:DF (match_operand:DF 1 "s_register_operand" "f")))] 1.1.1.4 root 1530: "TARGET_HARD_FLOAT" 1.1.1.3 root 1531: "abs%?d\\t%0, %1" 1532: [(set_attr "type" "ffarith")]) 1.1.1.2 root 1533: 1534: (define_insn "" 1535: [(set (match_operand:DF 0 "s_register_operand" "=f") 1536: (abs:DF (float_extend:DF 1537: (match_operand:SF 1 "s_register_operand" "f"))))] 1.1.1.4 root 1538: "TARGET_HARD_FLOAT" 1.1.1.3 root 1539: "abs%?d\\t%0, %1" 1540: [(set_attr "type" "ffarith")]) 1.1.1.2 root 1541: 1542: (define_insn "absxf2" 1543: [(set (match_operand:XF 0 "s_register_operand" "=f") 1544: (abs:XF (match_operand:XF 1 "s_register_operand" "f")))] 1.1.1.4 root 1545: "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" 1.1.1.3 root 1546: "abs%?e\\t%0, %1" 1547: [(set_attr "type" "ffarith")]) 1.1 root 1548: 1549: (define_insn "sqrtsf2" 1.1.1.2 root 1550: [(set (match_operand:SF 0 "s_register_operand" "=f") 1551: (sqrt:SF (match_operand:SF 1 "s_register_operand" "f")))] 1.1.1.4 root 1552: "TARGET_HARD_FLOAT" 1.1.1.3 root 1553: "sqt%?s\\t%0, %1" 1.1.1.2 root 1554: [(set_attr "type" "float_em")]) 1.1 root 1555: 1556: (define_insn "sqrtdf2" 1.1.1.2 root 1557: [(set (match_operand:DF 0 "s_register_operand" "=f") 1558: (sqrt:DF (match_operand:DF 1 "s_register_operand" "f")))] 1.1.1.4 root 1559: "TARGET_HARD_FLOAT" 1.1.1.3 root 1560: "sqt%?d\\t%0, %1" 1.1.1.2 root 1561: [(set_attr "type" "float_em")]) 1562: 1563: (define_insn "" 1564: [(set (match_operand:DF 0 "s_register_operand" "=f") 1565: (sqrt:DF (float_extend:DF 1566: (match_operand:SF 1 "s_register_operand" "f"))))] 1.1.1.4 root 1567: "TARGET_HARD_FLOAT" 1.1.1.3 root 1568: "sqt%?d\\t%0, %1" 1.1.1.2 root 1569: [(set_attr "type" "float_em")]) 1570: 1571: (define_insn "sqrtxf2" 1572: [(set (match_operand:XF 0 "s_register_operand" "=f") 1573: (sqrt:XF (match_operand:XF 1 "s_register_operand" "f")))] 1.1.1.4 root 1574: "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" 1.1.1.3 root 1575: "sqt%?e\\t%0, %1" 1.1.1.2 root 1576: [(set_attr "type" "float_em")]) 1577: 1578: (define_insn "sinsf2" 1579: [(set (match_operand:SF 0 "s_register_operand" "=f") 1580: (unspec:SF [(match_operand:SF 1 "s_register_operand" "f")] 0))] 1.1.1.4 root 1581: "TARGET_HARD_FLOAT" 1.1.1.3 root 1582: "sin%?s\\t%0, %1" 1.1.1.2 root 1583: [(set_attr "type" "float_em")]) 1584: 1585: (define_insn "sindf2" 1586: [(set (match_operand:DF 0 "s_register_operand" "=f") 1587: (unspec:DF [(match_operand:DF 1 "s_register_operand" "f")] 0))] 1.1.1.4 root 1588: "TARGET_HARD_FLOAT" 1.1.1.3 root 1589: "sin%?d\\t%0, %1" 1.1.1.2 root 1590: [(set_attr "type" "float_em")]) 1591: 1592: (define_insn "" 1593: [(set (match_operand:DF 0 "s_register_operand" "=f") 1594: (unspec:DF [(float_extend:DF 1595: (match_operand:SF 1 "s_register_operand" "f"))] 0))] 1.1.1.4 root 1596: "TARGET_HARD_FLOAT" 1.1.1.3 root 1597: "sin%?d\\t%0, %1" 1.1.1.2 root 1598: [(set_attr "type" "float_em")]) 1599: 1600: (define_insn "sinxf2" 1601: [(set (match_operand:XF 0 "s_register_operand" "=f") 1602: (unspec:XF [(match_operand:XF 1 "s_register_operand" "f")] 0))] 1.1.1.4 root 1603: "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" 1.1.1.3 root 1604: "sin%?e\\t%0, %1" 1.1.1.2 root 1605: [(set_attr "type" "float_em")]) 1606: 1607: (define_insn "cossf2" 1608: [(set (match_operand:SF 0 "s_register_operand" "=f") 1609: (unspec:SF [(match_operand:SF 1 "s_register_operand" "f")] 1))] 1.1.1.4 root 1610: "TARGET_HARD_FLOAT" 1.1.1.3 root 1611: "cos%?s\\t%0, %1" 1.1.1.2 root 1612: [(set_attr "type" "float_em")]) 1613: 1614: (define_insn "cosdf2" 1615: [(set (match_operand:DF 0 "s_register_operand" "=f") 1616: (unspec:DF [(match_operand:DF 1 "s_register_operand" "f")] 1))] 1.1.1.4 root 1617: "TARGET_HARD_FLOAT" 1.1.1.3 root 1618: "cos%?d\\t%0, %1" 1.1.1.2 root 1619: [(set_attr "type" "float_em")]) 1620: 1621: (define_insn "" 1622: [(set (match_operand:DF 0 "s_register_operand" "=f") 1623: (unspec:DF [(float_extend:DF 1624: (match_operand:SF 1 "s_register_operand" "f"))] 1))] 1.1.1.4 root 1625: "TARGET_HARD_FLOAT" 1.1.1.3 root 1626: "cos%?d\\t%0, %1" 1.1.1.2 root 1627: [(set_attr "type" "float_em")]) 1628: 1629: (define_insn "cosxf2" 1630: [(set (match_operand:XF 0 "s_register_operand" "=f") 1631: (unspec:XF [(match_operand:XF 1 "s_register_operand" "f")] 1))] 1.1.1.4 root 1632: "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" 1.1.1.3 root 1633: "cos%?e\\t%0, %1" 1.1.1.2 root 1634: [(set_attr "type" "float_em")]) 1635: 1636: (define_insn "one_cmpldi2" 1637: [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 1638: (not:DI (match_operand:DI 1 "s_register_operand" "?r,0")))] 1639: "" 1.1.1.3 root 1640: "mvn%?\\t%0, %1\;mvn%?\\t%R0, %R1" 1641: [(set_attr "length" "8")]) 1.1 root 1642: 1643: (define_insn "one_cmplsi2" 1.1.1.2 root 1644: [(set (match_operand:SI 0 "s_register_operand" "=r") 1645: (not:SI (match_operand:SI 1 "s_register_operand" "r")))] 1.1 root 1646: "" 1.1.1.3 root 1647: "mvn%?\\t%0, %1") 1.1.1.2 root 1648: 1649: (define_insn "" 1650: [(set (reg:CC_NOOV 24) 1651: (compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r")) 1652: (const_int 0))) 1653: (set (match_operand:SI 0 "s_register_operand" "=r") 1654: (not:SI (match_dup 1)))] 1655: "" 1.1.1.3 root 1656: "mvn%?s\\t%0, %1" 1.1.1.2 root 1657: [(set_attr "conds" "set")]) 1658: 1659: (define_insn "" 1660: [(set (reg:CC_NOOV 24) 1661: (compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r")) 1662: (const_int 0))) 1663: (clobber (match_scratch:SI 0 "=r"))] 1664: "" 1.1.1.3 root 1665: "mvn%?s\\t%0, %1" 1.1.1.2 root 1666: [(set_attr "conds" "set")]) 1.1 root 1667: 1668: ;; Fixed <--> Floating conversion insns 1669: 1670: (define_insn "floatsisf2" 1.1.1.2 root 1671: [(set (match_operand:SF 0 "s_register_operand" "=f") 1672: (float:SF (match_operand:SI 1 "s_register_operand" "r")))] 1.1.1.4 root 1673: "TARGET_HARD_FLOAT" 1.1.1.3 root 1674: "flt%?s\\t%0, %1" 1.1.1.2 root 1675: [(set_attr "type" "r_2_f")]) 1.1 root 1676: 1677: (define_insn "floatsidf2" 1.1.1.2 root 1678: [(set (match_operand:DF 0 "s_register_operand" "=f") 1679: (float:DF (match_operand:SI 1 "s_register_operand" "r")))] 1.1.1.4 root 1680: "TARGET_HARD_FLOAT" 1.1.1.3 root 1681: "flt%?d\\t%0, %1" 1.1.1.2 root 1682: [(set_attr "type" "r_2_f")]) 1683: 1684: (define_insn "floatsixf2" 1685: [(set (match_operand:XF 0 "s_register_operand" "=f") 1686: (float:XF (match_operand:SI 1 "s_register_operand" "r")))] 1.1.1.4 root 1687: "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" 1.1.1.3 root 1688: "flt%?e\\t%0, %1" 1.1.1.2 root 1689: [(set_attr "type" "r_2_f")]) 1690: 1691: (define_insn "fix_truncsfsi2" 1692: [(set (match_operand:SI 0 "s_register_operand" "=r") 1693: (fix:SI (match_operand:SF 1 "s_register_operand" "f")))] 1.1.1.4 root 1694: "TARGET_HARD_FLOAT" 1.1.1.3 root 1695: "fix%?z\\t%0, %1" 1.1.1.2 root 1696: [(set_attr "type" "f_2_r")]) 1697: 1698: (define_insn "fix_truncdfsi2" 1699: [(set (match_operand:SI 0 "s_register_operand" "=r") 1700: (fix:SI (match_operand:DF 1 "s_register_operand" "f")))] 1.1.1.4 root 1701: "TARGET_HARD_FLOAT" 1.1.1.3 root 1702: "fix%?z\\t%0, %1" 1.1.1.2 root 1703: [(set_attr "type" "f_2_r")]) 1704: 1705: (define_insn "fix_truncxfsi2" 1706: [(set (match_operand:SI 0 "s_register_operand" "=r") 1707: (fix:SI (match_operand:XF 1 "s_register_operand" "f")))] 1.1.1.4 root 1708: "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" 1.1.1.3 root 1709: "fix%?z\\t%0, %1" 1.1.1.2 root 1710: [(set_attr "type" "f_2_r")]) 1.1 root 1711: 1712: ;; Truncation insns 1713: 1714: (define_insn "truncdfsf2" 1.1.1.2 root 1715: [(set (match_operand:SF 0 "s_register_operand" "=f") 1.1 root 1716: (float_truncate:SF 1.1.1.2 root 1717: (match_operand:DF 1 "s_register_operand" "f")))] 1.1.1.4 root 1718: "TARGET_HARD_FLOAT" 1.1.1.3 root 1719: "mvf%?s\\t%0, %1" 1720: [(set_attr "type" "ffarith")]) 1.1.1.2 root 1721: 1722: (define_insn "truncxfsf2" 1723: [(set (match_operand:SF 0 "s_register_operand" "=f") 1724: (float_truncate:SF 1725: (match_operand:XF 1 "s_register_operand" "f")))] 1.1.1.4 root 1726: "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" 1.1.1.3 root 1727: "mvf%?s\\t%0, %1" 1728: [(set_attr "type" "ffarith")]) 1.1.1.2 root 1729: 1730: (define_insn "truncxfdf2" 1731: [(set (match_operand:DF 0 "s_register_operand" "=f") 1732: (float_truncate:DF 1733: (match_operand:XF 1 "s_register_operand" "f")))] 1.1.1.4 root 1734: "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" 1.1.1.3 root 1735: "mvf%?d\\t%0, %1" 1736: [(set_attr "type" "ffarith")]) 1.1 root 1737: 1.1.1.2 root 1738: ;; Zero and sign extension instructions. 1739: 1740: (define_insn "zero_extendsidi2" 1741: [(set (match_operand:DI 0 "s_register_operand" "=r") 1742: (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")))] 1743: "" 1744: "* 1745: if (REGNO (operands[1]) != REGNO (operands[0])) 1.1.1.3 root 1746: output_asm_insn (\"mov%?\\t%0, %1\", operands); 1747: return \"mov%?\\t%R0, #0\"; 1.1.1.2 root 1748: " 1.1.1.3 root 1749: [(set_attr "length" "8")]) 1.1.1.2 root 1750: 1751: (define_insn "zero_extendqidi2" 1752: [(set (match_operand:DI 0 "s_register_operand" "=r,r") 1753: (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] 1754: "" 1.1.1.3 root 1755: "@ 1756: and%?\\t%0, %1, #255\;mov%?\\t%R0, #0 1757: ldr%?b\\t%0, %1\;mov%?\\t%R0, #0" 1758: [(set_attr "length" "8") 1.1.1.2 root 1759: (set_attr "type" "*,load")]) 1760: 1761: (define_insn "extendsidi2" 1762: [(set (match_operand:DI 0 "s_register_operand" "=r") 1763: (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r")))] 1764: "" 1765: "* 1766: if (REGNO (operands[1]) != REGNO (operands[0])) 1.1.1.3 root 1767: output_asm_insn (\"mov%?\\t%0, %1\", operands); 1768: return \"mov%?\\t%R0, %0, asr #31\"; 1.1.1.2 root 1769: " 1.1.1.3 root 1770: [(set_attr "length" "8")]) 1.1 root 1771: 1772: (define_expand "zero_extendhisi2" 1.1.1.3 root 1773: [(set (match_dup 2) (ashift:SI (match_operand:HI 1 "nonimmediate_operand" "") 1774: (const_int 16))) 1.1.1.2 root 1775: (set (match_operand:SI 0 "s_register_operand" "") 1.1.1.3 root 1776: (lshiftrt:SI (match_dup 2) (const_int 16)))] 1.1 root 1777: "" 1778: " 1.1.1.3 root 1779: { 1780: if (TARGET_SHORT_BY_BYTES && GET_CODE (operands[1]) == MEM) 1781: { 1782: emit_insn (gen_movhi_bytes (operands[0], operands[1])); 1783: DONE; 1784: } 1785: if (! s_register_operand (operands[1], HImode)) 1786: operands[1] = copy_to_mode_reg (HImode, operands[1]); 1787: operands[1] = gen_lowpart (SImode, operands[1]); 1788: operands[2] = gen_reg_rtx (SImode); 1789: }") 1.1.1.2 root 1790: 1.1.1.3 root 1791: (define_expand "zero_extendqisi2" 1.1.1.2 root 1792: [(set (match_operand:SI 0 "s_register_operand" "=r,r") 1.1 root 1793: (zero_extend:SI 1794: (match_operand:QI 1 "nonimmediate_operand" "r,m")))] 1795: "" 1.1.1.3 root 1796: " 1797: if (GET_CODE (operands[1]) != MEM) 1.1 root 1798: { 1.1.1.3 root 1799: emit_insn (gen_andsi3 (operands[0], gen_lowpart (SImode, operands[1]), 1800: GEN_INT (255))); 1801: DONE; 1.1 root 1802: } 1.1.1.3 root 1803: ") 1.1 root 1804: 1.1.1.2 root 1805: (define_insn "" 1.1.1.3 root 1806: [(set (match_operand:SI 0 "s_register_operand" "=r") 1807: (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] 1.1 root 1808: "" 1.1.1.3 root 1809: "ldr%?b\\t%0, %1\\t%@ zero_extendqisi2" 1810: [(set_attr "type" "load")]) 1811: 1812: (define_split 1813: [(set (match_operand:SI 0 "s_register_operand" "") 1814: (zero_extend:SI (subreg:QI (match_operand:SI 1 "" "") 0))) 1815: (clobber (match_operand:SI 2 "s_register_operand" ""))] 1816: "GET_CODE (operands[1]) != MEM" 1817: [(set (match_dup 2) (match_dup 1)) 1818: (set (match_dup 0) (and:SI (match_dup 2) (const_int 255)))] 1819: "") 1.1.1.2 root 1820: 1821: (define_insn "" 1822: [(set (reg:CC_NOOV 24) 1.1.1.3 root 1823: (compare:CC_NOOV (match_operand:QI 0 "s_register_operand" "r") 1824: (const_int 0)))] 1.1.1.2 root 1825: "" 1.1.1.3 root 1826: "tst\\t%0, #255" 1.1.1.2 root 1827: [(set_attr "conds" "set")]) 1828: 1829: (define_expand "extendhisi2" 1830: [(set (match_dup 2) 1.1.1.3 root 1831: (ashift:SI (match_operand:HI 1 "nonimmediate_operand" "") 1.1.1.2 root 1832: (const_int 16))) 1833: (set (match_operand:SI 0 "s_register_operand" "") 1834: (ashiftrt:SI (match_dup 2) 1835: (const_int 16)))] 1836: "" 1837: " 1.1.1.3 root 1838: { 1839: if (TARGET_SHORT_BY_BYTES && GET_CODE (operands[1]) == MEM) 1840: { 1841: emit_insn (gen_extendhisi2_mem (operands[0], operands[1])); 1842: DONE; 1843: } 1844: if (! s_register_operand (operands[1], HImode)) 1845: operands[1] = copy_to_mode_reg (HImode, operands[1]); 1846: operands[1] = gen_lowpart (SImode, operands[1]); 1847: operands[2] = gen_reg_rtx (SImode); 1848: }") 1849: 1850: (define_expand "extendhisi2_mem" 1851: [(set (match_dup 2) (zero_extend:SI (mem:QI (match_operand:HI 1 "" "")))) 1852: (set (match_dup 3) 1853: (zero_extend:SI (mem:QI (plus:SI (match_dup 1) (const_int 1))))) 1854: (set (match_dup 6) (ashift:SI (match_dup 4) (const_int 24))) 1855: (set (match_operand:SI 0 "" "") 1856: (ior:SI (ashiftrt:SI (match_dup 6) (const_int 16)) (match_dup 5)))] 1857: "" 1858: " 1859: operands[0] = gen_lowpart (SImode, operands[0]); 1860: operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); 1861: operands[2] = gen_reg_rtx (SImode); 1862: operands[3] = gen_reg_rtx (SImode); 1863: operands[6] = gen_reg_rtx (SImode); 1864: 1865: if (BYTES_BIG_ENDIAN) 1866: { 1867: operands[4] = operands[2]; 1868: operands[5] = operands[3]; 1869: } 1870: else 1871: { 1872: operands[4] = operands[3]; 1873: operands[5] = operands[2]; 1874: } 1875: ") 1.1 root 1876: 1877: (define_expand "extendqihi2" 1878: [(set (match_dup 2) 1.1.1.2 root 1879: (ashift:SI (match_operand:QI 1 "s_register_operand" "") 1.1 root 1880: (const_int 24))) 1.1.1.2 root 1881: (set (match_operand:HI 0 "s_register_operand" "") 1.1 root 1882: (ashiftrt:SI (match_dup 2) 1883: (const_int 24)))] 1884: "" 1885: " 1886: { operands[0] = gen_lowpart (SImode, operands[0]); 1887: operands[1] = gen_lowpart (SImode, operands[1]); 1888: operands[2] = gen_reg_rtx (SImode); }") 1889: 1890: (define_expand "extendqisi2" 1891: [(set (match_dup 2) 1.1.1.2 root 1892: (ashift:SI (match_operand:QI 1 "s_register_operand" "") 1.1 root 1893: (const_int 24))) 1.1.1.2 root 1894: (set (match_operand:SI 0 "s_register_operand" "") 1.1 root 1895: (ashiftrt:SI (match_dup 2) 1896: (const_int 24)))] 1897: "" 1898: " 1899: { operands[1] = gen_lowpart (SImode, operands[1]); 1900: operands[2] = gen_reg_rtx (SImode); }") 1901: 1902: (define_insn "extendsfdf2" 1.1.1.2 root 1903: [(set (match_operand:DF 0 "s_register_operand" "=f") 1904: (float_extend:DF (match_operand:SF 1 "s_register_operand" "f")))] 1.1.1.4 root 1905: "TARGET_HARD_FLOAT" 1.1.1.3 root 1906: "mvf%?d\\t%0, %1" 1907: [(set_attr "type" "ffarith")]) 1.1.1.2 root 1908: 1909: (define_insn "extendsfxf2" 1910: [(set (match_operand:XF 0 "s_register_operand" "=f") 1911: (float_extend:XF (match_operand:SF 1 "s_register_operand" "f")))] 1.1.1.4 root 1912: "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" 1.1.1.3 root 1913: "mvf%?e\\t%0, %1" 1914: [(set_attr "type" "ffarith")]) 1.1.1.2 root 1915: 1916: (define_insn "extenddfxf2" 1917: [(set (match_operand:XF 0 "s_register_operand" "=f") 1918: (float_extend:XF (match_operand:DF 1 "s_register_operand" "f")))] 1.1.1.4 root 1919: "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" 1.1.1.3 root 1920: "mvf%?e\\t%0, %1" 1921: [(set_attr "type" "ffarith")]) 1.1.1.2 root 1922: 1.1 root 1923: 1924: ;; Move insns (including loads and stores) 1925: 1926: ;; XXX Just some ideas about movti. 1.1.1.2 root 1927: ;; I don't think these are a good idea on the arm, there just aren't enough 1928: ;; registers 1.1 root 1929: ;;(define_expand "loadti" 1.1.1.2 root 1930: ;; [(set (match_operand:TI 0 "s_register_operand" "") 1.1 root 1931: ;; (mem:TI (match_operand:SI 1 "address_operand" "")))] 1932: ;; "" "") 1933: 1934: ;;(define_expand "storeti" 1935: ;; [(set (mem:TI (match_operand:TI 0 "address_operand" "")) 1.1.1.2 root 1936: ;; (match_operand:TI 1 "s_register_operand" ""))] 1.1 root 1937: ;; "" "") 1938: 1939: ;;(define_expand "movti" 1940: ;; [(set (match_operand:TI 0 "general_operand" "") 1941: ;; (match_operand:TI 1 "general_operand" ""))] 1942: ;; "" 1943: ;; " 1944: ;;{ 1945: ;; rtx insn; 1946: ;; 1947: ;; if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 1948: ;; operands[1] = copy_to_reg (operands[1]); 1949: ;; if (GET_CODE (operands[0]) == MEM) 1950: ;; insn = gen_storeti (XEXP (operands[0], 0), operands[1]); 1951: ;; else if (GET_CODE (operands[1]) == MEM) 1952: ;; insn = gen_loadti (operands[0], XEXP (operands[1], 0)); 1953: ;; else 1954: ;; FAIL; 1955: ;; 1956: ;; emit_insn (insn); 1957: ;; DONE; 1958: ;;}") 1959: 1960: ;; Recognise garbage generated above. 1961: 1962: ;;(define_insn "" 1963: ;; [(set (match_operand:TI 0 "general_operand" "=r,r,r,<,>,m") 1964: ;; (match_operand:TI 1 "general_operand" "<,>,m,r,r,r"))] 1965: ;; "" 1966: ;; "* 1967: ;; { 1968: ;; register mem = (which_alternative < 3); 1969: ;; register char *template; 1970: ;; 1971: ;; operands[mem] = XEXP (operands[mem], 0); 1972: ;; switch (which_alternative) 1973: ;; { 1974: ;; case 0: template = \"ldmdb\\t%1!, %M0\"; break; 1975: ;; case 1: template = \"ldmia\\t%1!, %M0\"; break; 1976: ;; case 2: template = \"ldmia\\t%1, %M0\"; break; 1977: ;; case 3: template = \"stmdb\\t%0!, %M1\"; break; 1978: ;; case 4: template = \"stmia\\t%0!, %M1\"; break; 1979: ;; case 5: template = \"stmia\\t%0, %M1\"; break; 1980: ;; } 1.1.1.3 root 1981: ;; output_asm_insn (template, operands); 1982: ;; return \"\"; 1.1 root 1983: ;; }") 1984: 1985: 1986: (define_insn "movdi" 1.1.1.2 root 1987: [(set (match_operand:DI 0 "di_operand" "=r,r,r,o<>,r") 1.1.1.3 root 1988: (match_operand:DI 1 "di_operand" "rIK,n,o<>,r,F"))] 1.1 root 1989: "" 1990: "* 1991: return (output_move_double (operands)); 1.1.1.2 root 1992: " 1.1.1.3 root 1993: [(set_attr "length" "8,32,8,8,32") 1.1.1.2 root 1994: (set_attr "type" "*,*,load,store2,*")]) 1995: 1996: (define_expand "movsi" 1997: [(set (match_operand:SI 0 "general_operand" "") 1998: (match_operand:SI 1 "general_operand" ""))] 1999: "" 2000: " 2001: /* Everything except mem = const or mem = mem can be done easily */ 2002: if (GET_CODE (operands[0]) == MEM) 2003: operands[1] = force_reg (SImode, operands[1]); 2004: if (GET_CODE (operands[1]) == CONST_INT 2005: && !(const_ok_for_arm (INTVAL (operands[1])) 2006: || const_ok_for_arm (~INTVAL (operands[1])))) 2007: { 1.1.1.3 root 2008: arm_split_constant (SET, SImode, INTVAL (operands[1]), operands[0], 2009: NULL_RTX, 2010: (reload_in_progress || reload_completed ? 0 2011: : preserve_subexpressions_p ())); 1.1.1.2 root 2012: DONE; 2013: } 1.1 root 2014: ") 2015: 1.1.1.2 root 2016: (define_insn "" 1.1.1.3 root 2017: [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,m,r,r") 2018: (match_operand:SI 1 "general_operand" "R,m,K,rI,r,S,?n"))] 1.1.1.2 root 2019: "(register_operand (operands[0], SImode) 2020: && (GET_CODE (operands[1]) != SYMBOL_REF 2021: || CONSTANT_ADDRESS_P (operands[1]))) 2022: || register_operand (operands[1], SImode)" 1.1 root 2023: "* 2024: switch (which_alternative) 2025: { 1.1.1.3 root 2026: case 0: 2027: /* NB Calling get_attr_length may cause the insn to be re-extracted... */ 2028: if (get_attr_length (insn) == 8) 1.1.1.2 root 2029: { 1.1.1.3 root 2030: /* ... so modify the operands here. */ 2031: operands[1] = XEXP (operands[1], 0); 2032: output_asm_insn (\"sub%?\\t%0, %|pc, #(8 + . - %a1) & ~4095\", 2033: operands); 2034: output_asm_insn (\"ldr%?\\t%0, [%0, #- ((4 + . - %a1) & 4095)]\", 2035: operands); 1.1.1.2 root 2036: } 1.1.1.3 root 2037: else 2038: { 2039: /* ... and here. */ 2040: operands[1] = XEXP (operands[1], 0); 2041: output_asm_insn (\"ldr%?\\t%0, [%|pc, %1 - . - 8]\", operands); 2042: } 2043: return \"\"; 2044: 2045: case 1: 1.1 root 2046: if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF 2047: && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))) 1.1.1.3 root 2048: abort (); 2049: return \"ldr%?\\t%0, %1\"; 2050: 1.1 root 2051: case 3: 1.1.1.3 root 2052: return \"mov%?\\t%0, %1\"; 2053: case 2: 2054: return \"mvn%?\\t%0, #%B1\"; 1.1.1.2 root 2055: case 4: 1.1.1.3 root 2056: return \"str%?\\t%1, %0\"; 2057: case 5: 2058: return output_load_symbol (insn, operands); 2059: case 6: 2060: return \"#\"; 1.1 root 2061: } 1.1.1.2 root 2062: " 1.1.1.3 root 2063: [(set (attr "length") 2064: (cond [(eq_attr "alternative" "0") 2065: (if_then_else 2066: (gt (minus 2067: (pc) 2068: (symbol_ref "const_pool_offset (XEXP (operands[1], 0))")) 2069: (const_int 4087)) 2070: (const_int 8) 2071: (const_int 4)) 2072: (ior (eq_attr "alternative" "5") 2073: (eq_attr "alternative" "6")) (const_int 16)] 2074: (const_int 4))) 2075: (set_attr "type" "load,load,*,*,store1,*,*")]) 2076: 2077: (define_split 2078: [(set (match_operand:SI 0 "s_register_operand" "") 2079: (match_operand:SI 1 "const_int_operand" ""))] 2080: "! (const_ok_for_arm (INTVAL (operands[1])) 2081: || const_ok_for_arm (~INTVAL (operands[1])))" 2082: [(clobber (const_int 0))] 2083: " 2084: arm_split_constant (SET, SImode, INTVAL (operands[1]), operands[0], 2085: NULL_RTX, 0); 2086: DONE; 2087: ") 1.1.1.2 root 2088: 2089: ;; If copying one reg to another we can set the condition codes according to 2090: ;; its value. Such a move is common after a return from subroutine and the 2091: ;; result is being tested against zero. 1.1 root 2092: 1.1.1.2 root 2093: (define_insn "" 1.1.1.3 root 2094: [(set (reg:CC 24) (compare (match_operand:SI 1 "s_register_operand" "0,r") 1.1.1.2 root 2095: (const_int 0))) 1.1.1.3 root 2096: (set (match_operand:SI 0 "s_register_operand" "=r,r") (match_dup 1))] 1.1 root 2097: "" 1.1.1.3 root 2098: "@ 2099: cmp%?\\t%0, #0 2100: sub%?s\\t%0, %1, #0" 1.1.1.2 root 2101: [(set_attr "conds" "set")]) 1.1 root 2102: 2103: ;; Subroutine to store a half word from a register into memory. 2104: ;; Operand 0 is the source register (HImode) 2105: ;; Operand 1 is the destination address in a register (SImode) 2106: 1.1.1.2 root 2107: ;; In both this routine and the next, we must be careful not to spill 1.1.1.4 root 2108: ;; a memory address of reg+large_const into a separate PLUS insn, since this 1.1.1.2 root 2109: ;; can generate unrecognizable rtl. 2110: 1.1 root 2111: (define_expand "storehi" 2112: [;; store the low byte 2113: (set (mem:QI (match_operand:SI 1 "" "")) (match_dup 3)) 2114: ;; extract the high byte 2115: (set (match_dup 2) 2116: (ashiftrt:SI (match_operand 0 "" "") (const_int 8))) 2117: ;; store the high byte 1.1.1.2 root 2118: (set (mem:QI (match_dup 4)) 1.1 root 2119: (subreg:QI (match_dup 2) 0))] ;explicit subreg safe 2120: "" 2121: " 1.1.1.2 root 2122: { 2123: enum rtx_code code = GET_CODE (operands[1]); 2124: 2125: if ((code == PLUS || code == MINUS) 2126: && (GET_CODE (XEXP (operands[1], 1)) == REG 2127: || GET_CODE (XEXP (operands[1], 0)) != REG)) 2128: operands[1] = force_reg (SImode, operands[1]); 2129: operands[4] = plus_constant (operands[1], 1); 2130: operands[3] = gen_lowpart (QImode, operands[0]); 1.1 root 2131: operands[0] = gen_lowpart (SImode, operands[0]); 1.1.1.2 root 2132: operands[2] = gen_reg_rtx (SImode); 2133: } 2134: ") 1.1 root 2135: 1.1.1.3 root 2136: (define_expand "storehi_bigend" 2137: [(set (mem:QI (match_dup 4)) (match_dup 3)) 2138: (set (match_dup 2) 2139: (ashiftrt:SI (match_operand 0 "" "") (const_int 8))) 2140: (set (mem:QI (match_operand 1 "" "")) 2141: (subreg:QI (match_dup 2) 0))] 1.1 root 2142: "" 2143: " 1.1.1.2 root 2144: { 2145: enum rtx_code code = GET_CODE (operands[1]); 2146: if ((code == PLUS || code == MINUS) 2147: && (GET_CODE (XEXP (operands[1], 1)) == REG 2148: || GET_CODE (XEXP (operands[1], 0)) != REG)) 1.1.1.3 root 2149: operands[1] = force_reg (SImode, operands[1]); 2150: 2151: operands[4] = plus_constant (operands[1], 1); 2152: operands[3] = gen_lowpart (QImode, operands[0]); 2153: operands[0] = gen_lowpart (SImode, operands[0]); 2154: operands[2] = gen_reg_rtx (SImode); 2155: } 2156: ") 2157: 2158: ;; Subroutine to store a half word integer constant into memory. 2159: (define_expand "storeinthi" 2160: [(set (mem:QI (match_operand:SI 0 "" "")) 2161: (subreg:QI (match_operand 1 "" "") 0)) 2162: (set (mem:QI (match_dup 3)) (subreg:QI (match_dup 2) 0))] 2163: "" 2164: " 2165: { 2166: HOST_WIDE_INT value = INTVAL (operands[1]); 2167: enum rtx_code code = GET_CODE (operands[0]); 1.1.1.2 root 2168: 1.1.1.3 root 2169: if ((code == PLUS || code == MINUS) 2170: && (GET_CODE (XEXP (operands[0], 1)) == REG 2171: || GET_CODE (XEXP (operands[0], 0)) != REG)) 2172: operands[0] = force_reg (SImode, operands[0]); 2173: 2174: operands[1] = gen_reg_rtx (SImode); 2175: if (BYTES_BIG_ENDIAN) 2176: { 2177: emit_insn (gen_movsi (operands[1], GEN_INT ((value >> 8) & 255))); 2178: if ((value & 255) == ((value >> 8) & 255)) 2179: operands[2] = operands[1]; 2180: else 2181: { 2182: operands[2] = gen_reg_rtx (SImode); 2183: emit_insn (gen_movsi (operands[2], GEN_INT (value & 255))); 2184: } 2185: } 2186: else 2187: { 2188: emit_insn (gen_movsi (operands[1], GEN_INT (value & 255))); 2189: if ((value & 255) == ((value >> 8) & 255)) 2190: operands[2] = operands[1]; 2191: else 2192: { 2193: operands[2] = gen_reg_rtx (SImode); 2194: emit_insn (gen_movsi (operands[2], GEN_INT ((value >> 8) & 255))); 2195: } 2196: } 2197: 2198: operands[3] = plus_constant (operands[0], 1); 1.1.1.2 root 2199: } 1.1 root 2200: ") 2201: 2202: (define_expand "movhi" 2203: [(set (match_operand:HI 0 "general_operand" "") 2204: (match_operand:HI 1 "general_operand" ""))] 2205: "" 2206: " 2207: { 2208: rtx insn; 2209: 1.1.1.3 root 2210: if (! (reload_in_progress || reload_completed)) 1.1 root 2211: { 2212: if (GET_CODE (operands[0]) == MEM) 2213: { 2214: if (GET_CODE (operands[1]) == CONST_INT) 1.1.1.3 root 2215: emit_insn (gen_storeinthi (XEXP (operands[0], 0), operands[1])); 1.1 root 2216: else 2217: { 2218: if (GET_CODE (operands[1]) == MEM) 1.1.1.2 root 2219: operands[1] = force_reg (HImode, operands[1]); 1.1.1.3 root 2220: if (BYTES_BIG_ENDIAN) 2221: emit_insn (gen_storehi_bigend (operands[1], 2222: XEXP (operands[0], 0))); 2223: else 2224: emit_insn (gen_storehi (operands[1], XEXP (operands[0], 0))); 1.1 root 2225: } 1.1.1.3 root 2226: DONE; 1.1 root 2227: } 1.1.1.3 root 2228: /* Sign extend a constant, and keep it in an SImode reg. */ 2229: else if (GET_CODE (operands[1]) == CONST_INT) 1.1 root 2230: { 1.1.1.3 root 2231: rtx reg = gen_reg_rtx (SImode); 2232: HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffff; 1.1.1.2 root 2233: 1.1.1.3 root 2234: /* If the constant is already valid, leave it alone. */ 2235: if (! const_ok_for_arm (val)) 1.1.1.2 root 2236: { 1.1.1.3 root 2237: /* If setting all the top bits will make the constant 2238: loadable in a single instruction, then set them. 2239: Otherwise, sign extend the number. */ 2240: 2241: if (const_ok_for_arm (~ (val | ~0xffff))) 2242: val |= ~0xffff; 2243: else if (val & 0x8000) 2244: val |= ~0xffff; 1.1.1.2 root 2245: } 1.1.1.3 root 2246: 2247: emit_insn (gen_movsi (reg, GEN_INT (val))); 2248: operands[1] = gen_rtx (SUBREG, HImode, reg, 0); 2249: } 2250: else if (TARGET_SHORT_BY_BYTES && GET_CODE (operands[1]) == MEM) 2251: { 2252: rtx reg = gen_reg_rtx (SImode); 2253: emit_insn (gen_movhi_bytes (reg, operands[1])); 2254: operands[1] = gen_lowpart (HImode, reg); 2255: } 2256: else if (BYTES_BIG_ENDIAN && GET_CODE (operands[1]) == MEM) 2257: { 2258: emit_insn (gen_movhi_bigend (operands[0], operands[1])); 2259: DONE; 1.1 root 2260: } 2261: } 1.1.1.3 root 2262: } 2263: ") 1.1 root 2264: 1.1.1.3 root 2265: (define_expand "movhi_bytes" 2266: [(set (match_dup 2) (zero_extend:SI (mem:QI (match_operand:HI 1 "" "")))) 2267: (set (match_dup 3) 2268: (zero_extend:SI (mem:QI (plus:SI (match_dup 1) (const_int 1))))) 2269: (set (match_operand:SI 0 "" "") 2270: (ior:SI (ashift:SI (match_dup 4) (const_int 8)) (match_dup 5)))] 2271: "" 2272: " 2273: operands[0] = gen_lowpart (SImode, operands[0]); 2274: operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); 2275: operands[2] = gen_reg_rtx (SImode); 2276: operands[3] = gen_reg_rtx (SImode); 2277: 2278: if (BYTES_BIG_ENDIAN) 2279: { 2280: operands[4] = operands[2]; 2281: operands[5] = operands[3]; 2282: } 2283: else 2284: { 2285: operands[4] = operands[3]; 2286: operands[5] = operands[2]; 2287: } 2288: ") 2289: 2290: (define_expand "movhi_bigend" 2291: [(set (match_dup 2) 2292: (rotate:SI (subreg:SI (match_operand:HI 1 "memory_operand" "") 0) 2293: (const_int 16))) 2294: (set (match_dup 3) 2295: (ashiftrt:SI (match_dup 2) (const_int 16))) 2296: (set (match_operand:HI 0 "s_register_operand" "") 2297: (subreg:HI (match_dup 3) 0))] 2298: "" 2299: " 2300: operands[2] = gen_reg_rtx (SImode); 2301: operands[3] = gen_reg_rtx (SImode); 2302: ") 1.1 root 2303: 2304: ;; Pattern to recognise insn generated default case above 2305: 2306: (define_insn "" 1.1.1.3 root 2307: [(set (match_operand:HI 0 "general_operand" "=r,r,r") 2308: (match_operand:HI 1 "general_operand" "rI,K,m"))] 2309: "! BYTES_BIG_ENDIAN 2310: && ! TARGET_SHORT_BY_BYTES 2311: && (GET_CODE (operands[1]) != CONST_INT 2312: || const_ok_for_arm (INTVAL (operands[1])) 2313: || const_ok_for_arm (~INTVAL (operands[1])))" 2314: "@ 2315: mov%?\\t%0, %1\\t%@ movhi 2316: mvn%?\\t%0, #%B1\\t%@ movhi 2317: ldr%?\\t%0, %1\\t%@ movhi" 2318: [(set_attr "type" "*,*,load")]) 2319: 2320: (define_insn "" 2321: [(set (match_operand:HI 0 "s_register_operand" "=r,r,r") 2322: (match_operand:HI 1 "general_operand" "rI,K,m"))] 2323: "BYTES_BIG_ENDIAN 2324: && ! TARGET_SHORT_BY_BYTES 2325: && (GET_CODE (operands[1]) != CONST_INT 2326: || const_ok_for_arm (INTVAL (operands[1])) 2327: || const_ok_for_arm (~INTVAL (operands[1])))" 2328: "@ 2329: mov%?\\t%0, %1\\t%@ movhi 2330: mvn%?\\t%0, #%B1\\t%@ movhi 2331: ldr%?\\t%0, %1\\t%@ movhi_bigend\;mov%?\\t%0, %0, asr #16" 2332: [(set_attr "type" "*,*,load") 2333: (set_attr "length" "4,4,8")]) 2334: 2335: (define_insn "" 2336: [(set (match_operand:SI 0 "s_register_operand" "=r") 2337: (rotate:SI (subreg:SI (match_operand:HI 1 "memory_operand" "m") 0) 2338: (const_int 16)))] 2339: "BYTES_BIG_ENDIAN 2340: && ! TARGET_SHORT_BY_BYTES" 2341: "ldr%?\\t%0, %1\\t%@ movhi_bigend" 2342: [(set_attr "type" "load")]) 2343: 2344: (define_insn "" 2345: [(set (match_operand:HI 0 "s_register_operand" "=r,r") 2346: (match_operand:HI 1 "arm_rhs_operand" "rI,K"))] 2347: "TARGET_SHORT_BY_BYTES" 2348: "@ 2349: mov%?\\t%0, %1\\t%@ movhi 2350: mvn%?\\t%0, #%B1\\t%@ movhi") 2351: 1.1.1.2 root 2352: 2353: (define_expand "reload_outhi" 2354: [(parallel [(match_operand:HI 0 "reload_memory_operand" "=o") 2355: (match_operand:HI 1 "s_register_operand" "r") 2356: (match_operand:SI 2 "s_register_operand" "=&r")])] 2357: "" 2358: " 2359: arm_reload_out_hi (operands); 2360: DONE; 1.1 root 2361: ") 2362: 1.1.1.3 root 2363: (define_expand "reload_inhi" 2364: [(parallel [(match_operand:HI 0 "s_register_operand" "=r") 2365: (match_operand:HI 1 "reload_memory_operand" "o") 2366: (match_operand:SI 2 "s_register_operand" "=&r")])] 2367: "TARGET_SHORT_BY_BYTES" 2368: " 2369: arm_reload_in_hi (operands); 2370: DONE; 2371: ") 2372: 1.1.1.2 root 2373: (define_expand "movqi" 2374: [(set (match_operand:QI 0 "general_operand" "") 2375: (match_operand:QI 1 "general_operand" ""))] 1.1 root 2376: "" 1.1.1.2 root 2377: " 2378: /* Everything except mem = const or mem = mem can be done easily */ 2379: 2380: if (!(reload_in_progress || reload_completed)) 2381: { 2382: if (GET_CODE (operands[1]) == CONST_INT) 2383: { 1.1.1.3 root 2384: rtx reg = gen_reg_rtx (SImode); 2385: 2386: emit_insn (gen_movsi (reg, operands[1])); 1.1.1.2 root 2387: operands[1] = gen_rtx (SUBREG, QImode, reg, 0); 2388: } 1.1.1.3 root 2389: if (GET_CODE (operands[0]) == MEM) 2390: operands[1] = force_reg (QImode, operands[1]); 1.1.1.2 root 2391: } 2392: ") 2393: 2394: 2395: (define_insn "" 2396: [(set (match_operand:QI 0 "general_operand" "=r,r,r,m") 1.1.1.3 root 2397: (match_operand:QI 1 "general_operand" "rI,K,m,r"))] 1.1.1.2 root 2398: "register_operand (operands[0], QImode) 2399: || register_operand (operands[1], QImode)" 1.1.1.3 root 2400: "@ 2401: mov%?\\t%0, %1 2402: mvn%?\\t%0, #%B1 2403: ldr%?b\\t%0, %1 2404: str%?b\\t%1, %0" 2405: [(set_attr "type" "*,*,load,store1")]) 2406: 2407: (define_expand "movsf" 2408: [(set (match_operand:SF 0 "general_operand" "") 2409: (match_operand:SF 1 "general_operand" ""))] 2410: "" 2411: " 2412: if (GET_CODE (operands[1]) == CONST_DOUBLE 1.1.1.4 root 2413: && (TARGET_SOFT_FLOAT 2414: || (GET_CODE (operands[0]) == REG 2415: && REGNO (operands[0]) < 16) 1.1.1.3 root 2416: || ! (const_double_rtx_ok_for_fpu (operands[1]) 2417: || neg_const_double_rtx_ok_for_fpu (operands[1])))) 2418: { 2419: extern int optimize; 2420: rtx mem = force_const_mem (SFmode, operands[1]); 2421: rtx addr; 2422: 2423: if (reload_in_progress || reload_completed) 2424: addr = gen_rtx (REG, SImode, REGNO (operands[0])); 2425: else 2426: addr = gen_reg_rtx (SImode); 2427: if (optimize == 0) 1.1.1.2 root 2428: { 1.1.1.3 root 2429: rtx ptr = force_const_mem (SImode, XEXP (mem, 0)); 2430: emit_insn (gen_movsi (addr, ptr)); 1.1.1.2 root 2431: } 1.1.1.3 root 2432: else 2433: emit_insn (gen_movsi (addr, XEXP (mem, 0))); 2434: operands[1] = gen_rtx (MEM, SFmode, addr); 1.1 root 2435: } 1.1.1.3 root 2436: if (GET_CODE (operands[0]) == MEM) 2437: operands[1] = force_reg (SFmode, operands[1]); 2438: ") 1.1 root 2439: 1.1.1.3 root 2440: (define_insn "" 1.1.1.2 root 2441: [(set (match_operand:SF 0 "general_operand" "=f,f,f,m,f,r,r,r,m") 2442: (match_operand:SF 1 "general_operand" "fG,H,m,f,r,f,r,m,r"))] 1.1.1.4 root 2443: "TARGET_HARD_FLOAT 2444: && (GET_CODE (operands[0]) != MEM || register_operand (operands[1], SFmode))" 1.1.1.3 root 2445: "@ 2446: mvf%?s\\t%0, %1 2447: mnf%?s\\t%0, #%N1 2448: ldf%?s\\t%0, %1 2449: stf%?s\\t%1, %0 2450: str%?\\t%1, [%|sp, #-4]!\;ldf%?s\\t%0, [%|sp], #4 2451: stf%?s\\t%1, [%|sp, #-4]!\;ldr%?\\t%0, [%|sp], #4 2452: mov%?\\t%0, %1 2453: ldr%?\\t%0, %1\\t%@ float 2454: str%?\\t%1, %0\\t%@ float" 2455: [(set_attr "length" "4,4,4,4,8,8,4,4,4") 2456: (set_attr "type" 2457: "ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*,load,store1")]) 1.1.1.2 root 2458: 1.1.1.4 root 2459: ;; Exactly the same as above, except that all `f' cases are deleted. 2460: ;; This is necessary to prevent reload from ever trying to use a `f' reg 2461: ;; when -msoft-float. 2462: 2463: (define_insn "*movsf_soft_insn" 2464: [(set (match_operand:SF 0 "general_operand" "=r,r,m") 2465: (match_operand:SF 1 "general_operand" "r,m,r"))] 2466: "TARGET_SOFT_FLOAT 2467: && (GET_CODE (operands[0]) != MEM || register_operand (operands[1], SFmode))" 2468: "@ 2469: mov%?\\t%0, %1 2470: ldr%?\\t%0, %1\\t%@ float 2471: str%?\\t%1, %0\\t%@ float" 2472: [(set_attr "length" "4,4,4") 2473: (set_attr "type" "*,load,store1")]) 2474: 1.1.1.2 root 2475: (define_expand "movdf" 1.1.1.3 root 2476: [(set (match_operand:DF 0 "general_operand" "") 2477: (match_operand:DF 1 "general_operand" ""))] 1.1.1.2 root 2478: "" 2479: " 1.1.1.3 root 2480: if (GET_CODE (operands[1]) == CONST_DOUBLE 1.1.1.4 root 2481: && (TARGET_SOFT_FLOAT 2482: || (GET_CODE (operands[0]) == REG 2483: && REGNO (operands[0]) < 16) 1.1.1.3 root 2484: || ! (const_double_rtx_ok_for_fpu (operands[1]) 2485: || neg_const_double_rtx_ok_for_fpu (operands[1])))) 2486: { 2487: extern int optimize; 2488: rtx mem = force_const_mem (DFmode, operands[1]); 2489: rtx addr; 2490: 2491: if (reload_in_progress || reload_completed) 2492: addr = gen_rtx (REG, SImode, REGNO (operands[0])); 2493: else 2494: addr = gen_reg_rtx (SImode); 2495: if (optimize == 0) 2496: { 2497: rtx ptr = force_const_mem (SImode, XEXP (mem, 0)); 2498: emit_insn (gen_movsi (addr, ptr)); 2499: } 2500: else 2501: emit_insn (gen_movsi (addr, XEXP (mem, 0))); 2502: operands[1] = gen_rtx (MEM, DFmode, addr); 2503: } 1.1.1.2 root 2504: if (GET_CODE (operands[0]) == MEM) 2505: operands[1] = force_reg (DFmode, operands[1]); 1.1 root 2506: ") 2507: 1.1.1.2 root 2508: ;; Reloading a df mode value stored in integer regs to memory can require a 2509: ;; scratch reg. 2510: (define_expand "reload_outdf" 1.1.1.3 root 2511: [(match_operand:DF 0 "reload_memory_operand" "=o") 2512: (match_operand:DF 1 "s_register_operand" "r") 2513: (match_operand:SI 2 "s_register_operand" "=&r")] 1.1 root 2514: "" 1.1.1.3 root 2515: " 2516: if (GET_CODE (XEXP (operands[0], 0)) == REG) 2517: operands[2] = XEXP (operands[0], 0); 2518: else 2519: emit_insn (gen_addsi3 (operands[2], XEXP (XEXP (operands[0], 0), 0), 2520: XEXP (XEXP (operands[0], 0), 1))); 2521: emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (MEM, DFmode, operands[2]), 2522: operands[1])); 2523: DONE; 2524: ") 1.1.1.2 root 2525: 2526: (define_insn "" 1.1.1.3 root 2527: [(set (match_operand:DF 0 "general_operand" "=r,Q#m,r,f,f,f,f,m,!f,!r,r") 1.1.1.2 root 2528: (match_operand:DF 1 "general_operand" 1.1.1.3 root 2529: "Q,r,?o,?f,!G,!H,m,f,r,f,??r"))] 1.1.1.4 root 2530: "TARGET_HARD_FLOAT 2531: && (GET_CODE (operands[0]) != MEM || register_operand (operands[1], DFmode))" 1.1.1.2 root 2532: "* 2533: { 2534: rtx ops[3]; 2535: 2536: switch (which_alternative) 2537: { 2538: case 0: 1.1.1.3 root 2539: return \"ldm%?ia\\t%m1, {%0, %R0}\\t%@ double\"; 2540: 1.1.1.2 root 2541: case 1: 1.1.1.3 root 2542: return \"stm%?ia\\t%m0, {%1, %R1}\\t%@ double\"; 2543: 1.1.1.2 root 2544: case 2: 2545: ops[0] = operands[0]; 2546: ops[1] = XEXP (XEXP (operands[1], 0), 0); 2547: ops[2] = XEXP (XEXP (operands[1], 0), 1); 2548: if (!INTVAL (ops[2]) || const_ok_for_arm (INTVAL (ops[2]))) 1.1.1.3 root 2549: output_asm_insn (\"add%?\\t%0, %1, %2\", ops); 1.1.1.2 root 2550: else 1.1.1.3 root 2551: output_asm_insn (\"sub%?\\t%0, %1, #%n2\", ops); 2552: return \"ldm%?ia\\t%0, {%0, %R0}\\t%@ double\"; 1.1.1.2 root 2553: 1.1.1.3 root 2554: case 3: 1.1.1.2 root 2555: case 4: 1.1.1.3 root 2556: return \"mvf%?d\\t%0, %1\"; 2557: 2558: case 5: return \"mnf%?d\\t%0, #%N1\"; 2559: case 6: return \"ldf%?d\\t%0, %1\"; 2560: case 7: return \"stf%?d\\t%1, %0\"; 2561: case 8: return output_mov_double_fpu_from_arm (operands); 2562: case 9: return output_mov_double_arm_from_fpu (operands); 2563: case 10: return output_move_double (operands); 1.1.1.2 root 2564: } 2565: } 2566: " 1.1.1.3 root 2567: [(set_attr "length" "4,4,8,4,4,4,4,4,8,8,8") 1.1.1.2 root 2568: (set_attr "type" 1.1.1.3 root 2569: "load,store2,load,ffarith,ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*")]) 2570: 1.1.1.4 root 2571: ;; Software floating point version. This is essentially the same as movdi. 2572: ;; Do not use `f' as a constraint to prevent reload from ever trying to use 2573: ;; an `f' reg. 2574: 2575: (define_insn "*movdf_soft_insn" 2576: [(set (match_operand:DF 0 "soft_df_operand" "=r,r,o<>,r") 2577: (match_operand:DF 1 "soft_df_operand" "r,o<>,r,F"))] 2578: "TARGET_SOFT_FLOAT" 2579: "* return output_move_double (operands);" 2580: [(set_attr "length" "8,8,8,32") 2581: (set_attr "type" "*,load,store2,*")]) 2582: 1.1.1.3 root 2583: (define_expand "movxf" 2584: [(set (match_operand:XF 0 "general_operand" "") 2585: (match_operand:XF 1 "general_operand" ""))] 1.1.1.4 root 2586: "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" 1.1.1.3 root 2587: "") 2588: 2589: ;; Even when the XFmode patterns aren't enabled, we enable this after 2590: ;; reloading so that we can push floating point registers in the prologue. 1.1.1.2 root 2591: 1.1.1.3 root 2592: (define_insn "" 1.1.1.2 root 2593: [(set (match_operand:XF 0 "general_operand" "=f,f,f,m,f,r,r") 2594: (match_operand:XF 1 "general_operand" "fG,H,m,f,r,f,r"))] 1.1.1.4 root 2595: "TARGET_HARD_FLOAT && (ENABLE_XF_PATTERNS || reload_completed)" 1.1 root 2596: "* 2597: switch (which_alternative) 2598: { 1.1.1.3 root 2599: case 0: return \"mvf%?e\\t%0, %1\"; 2600: case 1: return \"mnf%?e\\t%0, #%N1\"; 2601: case 2: return \"ldf%?e\\t%0, %1\"; 2602: case 3: return \"stf%?e\\t%1, %0\"; 1.1.1.2 root 2603: case 4: return output_mov_long_double_fpu_from_arm (operands); 2604: case 5: return output_mov_long_double_arm_from_fpu (operands); 2605: case 6: return output_mov_long_double_arm_from_arm (operands); 1.1 root 2606: } 1.1.1.2 root 2607: " 1.1.1.3 root 2608: [(set_attr "length" "4,4,4,4,8,8,12") 2609: (set_attr "type" "ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*")]) 1.1 root 2610: 2611: 1.1.1.2 root 2612: ;; load- and store-multiple insns 2613: ;; The arm can load/store any set of registers, provided that they are in 2614: ;; ascending order; but that is beyond GCC so stick with what it knows. 2615: 2616: (define_expand "load_multiple" 2617: [(match_par_dup 3 [(set (match_operand:SI 0 "" "") 2618: (match_operand:SI 1 "" "")) 2619: (use (match_operand:SI 2 "" ""))])] 1.1 root 2620: "" 1.1.1.2 root 2621: " 2622: /* Support only fixed point registers */ 2623: if (GET_CODE (operands[2]) != CONST_INT 2624: || INTVAL (operands[2]) > 14 2625: || INTVAL (operands[2]) < 2 2626: || GET_CODE (operands[1]) != MEM 2627: || GET_CODE (operands[0]) != REG 2628: || REGNO (operands[0]) > 14 2629: || REGNO (operands[0]) + INTVAL (operands[2]) > 15) 2630: FAIL; 2631: 2632: operands[3] 2633: = arm_gen_load_multiple (REGNO (operands[0]), INTVAL (operands[2]), 2634: force_reg (SImode, XEXP (operands[1], 0)), 2635: TRUE, FALSE); 1.1 root 2636: ") 2637: 1.1.1.2 root 2638: ;; Load multiple with write-back 1.1 root 2639: 2640: (define_insn "" 1.1.1.2 root 2641: [(match_parallel 0 "load_multiple_operation" 2642: [(set (match_operand:SI 1 "s_register_operand" "+r") 2643: (plus:SI (match_dup 1) 2644: (match_operand:SI 2 "immediate_operand" "n"))) 2645: (set (match_operand:SI 3 "s_register_operand" "=r") 2646: (mem:SI (match_dup 1)))])] 2647: "(INTVAL (operands[2]) == 4 * (XVECLEN (operands[0], 0) - 2))" 1.1 root 2648: "* 1.1.1.2 root 2649: { 2650: rtx ops[3]; 2651: int count = XVECLEN (operands[0], 0); 1.1 root 2652: 1.1.1.2 root 2653: ops[0] = XEXP (SET_SRC (XVECEXP (operands[0], 0, 0)), 0); 2654: ops[1] = SET_DEST (XVECEXP (operands[0], 0, 1)); 2655: ops[2] = SET_DEST (XVECEXP (operands[0], 0, count - 2)); 2656: 1.1.1.3 root 2657: output_asm_insn (\"ldm%?ia\\t%0!, {%1-%2}\\t%@ load multiple\", ops); 2658: return \"\"; 1.1.1.2 root 2659: } 2660: " 2661: [(set_attr "type" "load")]) 1.1 root 2662: 1.1.1.2 root 2663: ;; Ordinary load multiple 1.1 root 2664: 1.1.1.2 root 2665: (define_insn "" 2666: [(match_parallel 0 "load_multiple_operation" 2667: [(set (match_operand:SI 1 "s_register_operand" "=r") 2668: (match_operand:SI 2 "indirect_operand" "Q"))])] 1.1 root 2669: "" 2670: "* 1.1.1.2 root 2671: { 2672: rtx ops[3]; 2673: int count = XVECLEN (operands[0], 0); 1.1 root 2674: 1.1.1.2 root 2675: ops[0] = XEXP (SET_SRC (XVECEXP (operands[0], 0, 0)), 0); 2676: ops[1] = SET_DEST (XVECEXP (operands[0], 0, 0)); 2677: ops[2] = SET_DEST (XVECEXP (operands[0], 0, count - 1)); 2678: 1.1.1.3 root 2679: output_asm_insn (\"ldm%?ia\\t%0, {%1-%2}\\t%@ load multiple\", ops); 2680: return \"\"; 1.1.1.2 root 2681: } 2682: " 2683: [(set_attr "type" "load")]) 2684: 2685: (define_expand "store_multiple" 2686: [(match_par_dup 3 [(set (match_operand:SI 0 "" "") 2687: (match_operand:SI 1 "" "")) 2688: (use (match_operand:SI 2 "" ""))])] 1.1 root 2689: "" 1.1.1.2 root 2690: " 2691: /* Support only fixed point registers */ 2692: if (GET_CODE (operands[2]) != CONST_INT 2693: || INTVAL (operands[2]) > 14 2694: || INTVAL (operands[2]) < 2 2695: || GET_CODE (operands[1]) != REG 2696: || GET_CODE (operands[0]) != MEM 2697: || REGNO (operands[1]) > 14 2698: || REGNO (operands[1]) + INTVAL (operands[2]) > 15) 2699: FAIL; 2700: 2701: operands[3] 2702: = arm_gen_store_multiple (REGNO (operands[1]), INTVAL (operands[2]), 2703: force_reg (SImode, XEXP (operands[0], 0)), 2704: TRUE, FALSE); 1.1 root 2705: ") 2706: 1.1.1.2 root 2707: ;; Store multiple with write-back 2708: 2709: (define_insn "" 2710: [(match_parallel 0 "store_multiple_operation" 2711: [(set (match_operand:SI 1 "s_register_operand" "+r") 2712: (plus:SI (match_dup 1) 2713: (match_operand:SI 2 "immediate_operand" "n"))) 2714: (set (mem:SI (match_dup 1)) 2715: (match_operand:SI 3 "s_register_operand" "r"))])] 2716: "(INTVAL (operands[2]) == 4 * (XVECLEN (operands[0], 0) - 2))" 1.1 root 2717: "* 1.1.1.2 root 2718: { 2719: rtx ops[3]; 2720: int count = XVECLEN (operands[0], 0); 1.1 root 2721: 1.1.1.2 root 2722: ops[0] = XEXP (SET_SRC (XVECEXP (operands[0], 0, 0)), 0); 2723: ops[1] = SET_SRC (XVECEXP (operands[0], 0, 1)); 2724: ops[2] = SET_SRC (XVECEXP (operands[0], 0, count - 2)); 2725: 1.1.1.3 root 2726: output_asm_insn (\"stm%?ia\\t%0!, {%1-%2}\\t%@ str multiple\", ops); 2727: return \"\"; 1.1.1.2 root 2728: } 2729: " 2730: [(set (attr "type") 2731: (cond [(eq (symbol_ref "XVECLEN (operands[0],0)") (const_int 4)) 2732: (const_string "store2") 2733: (eq (symbol_ref "XVECLEN (operands[0],0)") (const_int 5)) 2734: (const_string "store3")] 2735: (const_string "store4")))]) 2736: 2737: ;; Ordinary store multiple 2738: 2739: (define_insn "" 2740: [(match_parallel 0 "store_multiple_operation" 2741: [(set (match_operand:SI 2 "indirect_operand" "=Q") 2742: (match_operand:SI 1 "s_register_operand" "r"))])] 1.1 root 2743: "" 2744: "* 1.1.1.2 root 2745: { 2746: rtx ops[3]; 2747: int count = XVECLEN (operands[0], 0); 1.1 root 2748: 1.1.1.2 root 2749: ops[0] = XEXP (SET_DEST (XVECEXP (operands[0], 0, 0)), 0); 2750: ops[1] = SET_SRC (XVECEXP (operands[0], 0, 0)); 2751: ops[2] = SET_SRC (XVECEXP (operands[0], 0, count - 1)); 2752: 1.1.1.3 root 2753: output_asm_insn (\"stm%?ia\\t%0, {%1-%2}\\t%@ str multiple\", ops); 2754: return \"\"; 1.1.1.2 root 2755: } 2756: " 2757: [(set (attr "type") 2758: (cond [(eq (symbol_ref "XVECLEN (operands[0],0)") (const_int 3)) 2759: (const_string "store2") 2760: (eq (symbol_ref "XVECLEN (operands[0],0)") (const_int 4)) 2761: (const_string "store3")] 2762: (const_string "store4")))]) 2763: 2764: ;; Move a block of memory if it is word aligned and MORE than 2 words long. 2765: ;; We could let this apply for blocks of less than this, but it clobbers so 2766: ;; many registers that there is then probably a better way. 2767: 1.1.1.3 root 2768: (define_expand "movstrqi" 2769: [(match_operand:BLK 0 "general_operand" "") 2770: (match_operand:BLK 1 "general_operand" "") 2771: (match_operand:SI 2 "const_int_operand" "") 2772: (match_operand:SI 3 "const_int_operand" "")] 1.1 root 2773: "" 1.1.1.2 root 2774: " 1.1.1.3 root 2775: if (arm_gen_movstrqi (operands)) 2776: DONE; 2777: FAIL; 1.1 root 2778: ") 1.1.1.2 root 2779: 1.1 root 2780: 1.1.1.2 root 2781: ;; Comparison and test insns 2782: 2783: (define_expand "cmpsi" 2784: [(set (reg:CC 24) 2785: (compare:CC (match_operand:SI 0 "s_register_operand" "") 2786: (match_operand:SI 1 "arm_add_operand" "")))] 1.1 root 2787: "" 1.1.1.2 root 2788: " 2789: { 2790: arm_compare_op0 = operands[0]; 2791: arm_compare_op1 = operands[1]; 2792: arm_compare_fp = 0; 2793: DONE; 2794: } 1.1 root 2795: ") 2796: 1.1.1.2 root 2797: (define_expand "cmpsf" 2798: [(set (reg:CC 24) 2799: (compare:CC (match_operand:SF 0 "s_register_operand" "") 2800: (match_operand:SF 1 "fpu_rhs_operand" "")))] 1.1.1.4 root 2801: "TARGET_HARD_FLOAT" 1.1.1.2 root 2802: " 2803: { 2804: arm_compare_op0 = operands[0]; 2805: arm_compare_op1 = operands[1]; 2806: arm_compare_fp = 1; 2807: DONE; 2808: } 1.1 root 2809: ") 2810: 1.1.1.2 root 2811: (define_expand "cmpdf" 2812: [(set (reg:CC 24) 2813: (compare:CC (match_operand:DF 0 "s_register_operand" "") 2814: (match_operand:DF 1 "fpu_rhs_operand" "")))] 1.1.1.4 root 2815: "TARGET_HARD_FLOAT" 1.1.1.2 root 2816: " 2817: { 2818: arm_compare_op0 = operands[0]; 2819: arm_compare_op1 = operands[1]; 2820: arm_compare_fp = 1; 2821: DONE; 2822: } 1.1 root 2823: ") 2824: 1.1.1.2 root 2825: (define_expand "cmpxf" 2826: [(set (reg:CC 24) 2827: (compare:CC (match_operand:XF 0 "s_register_operand" "") 2828: (match_operand:XF 1 "fpu_rhs_operand" "")))] 1.1.1.4 root 2829: "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" 1.1.1.2 root 2830: " 2831: { 2832: arm_compare_op0 = operands[0]; 2833: arm_compare_op1 = operands[1]; 2834: arm_compare_fp = 1; 2835: DONE; 2836: } 1.1 root 2837: ") 2838: 1.1.1.2 root 2839: (define_insn "" 2840: [(set (match_operand 0 "cc_register" "") 1.1.1.3 root 2841: (compare (match_operand:SI 1 "s_register_operand" "r,r") 2842: (match_operand:SI 2 "arm_add_operand" "rI,L")))] 1.1 root 2843: "" 1.1.1.3 root 2844: "@ 2845: cmp%?\\t%1, %2 2846: cmn%?\\t%1, #%n2" 1.1.1.2 root 2847: [(set_attr "conds" "set")]) 1.1 root 2848: 2849: (define_insn "" 1.1.1.2 root 2850: [(set (match_operand 0 "cc_register" "") 2851: (compare (match_operand:SI 1 "s_register_operand" "r") 2852: (neg:SI (match_operand:SI 2 "s_register_operand" "r"))))] 1.1 root 2853: "" 1.1.1.3 root 2854: "cmn%?\\t%1, %2" 1.1.1.2 root 2855: [(set_attr "conds" "set")]) 1.1 root 2856: 2857: (define_insn "" 1.1.1.2 root 2858: [(set (match_operand 0 "cc_register" "") 2859: (compare (match_operand:SI 1 "s_register_operand" "r") 2860: (match_operator:SI 2 "shift_operator" 2861: [(match_operand:SI 3 "s_register_operand" "r") 1.1.1.3 root 2862: (match_operand:SI 4 "arm_rhs_operand" "rM")])))] 1.1 root 2863: "" 1.1.1.3 root 2864: "cmp%?\\t%1, %3%S2" 1.1.1.2 root 2865: [(set_attr "conds" "set")]) 1.1 root 2866: 2867: (define_insn "" 1.1.1.2 root 2868: [(set (match_operand 0 "cc_register" "") 2869: (compare (match_operand:SI 1 "s_register_operand" "r") 2870: (neg:SI (match_operator:SI 2 "shift_operator" 2871: [(match_operand:SI 3 "s_register_operand" "r") 1.1.1.3 root 2872: (match_operand:SI 4 "arm_rhs_operand" "rM")]))))] 1.1 root 2873: "" 1.1.1.3 root 2874: "cmn%?\\t%1, %3%S2" 1.1.1.2 root 2875: [(set_attr "conds" "set")]) 1.1 root 2876: 2877: (define_insn "" 1.1.1.2 root 2878: [(set (reg:CCFP 24) 2879: (compare:CCFP (match_operand:SF 0 "s_register_operand" "f,f") 2880: (match_operand:SF 1 "fpu_add_operand" "fG,H")))] 1.1.1.4 root 2881: "TARGET_HARD_FLOAT" 1.1.1.3 root 2882: "@ 2883: cmf%?\\t%0, %1 2884: cnf%?\\t%0, #%N1" 1.1.1.2 root 2885: [(set_attr "conds" "set") 2886: (set_attr "type" "f_2_r")]) 1.1 root 2887: 2888: (define_insn "" 1.1.1.2 root 2889: [(set (reg:CCFP 24) 2890: (compare:CCFP (match_operand:DF 0 "s_register_operand" "f,f") 2891: (match_operand:DF 1 "fpu_add_operand" "fG,H")))] 1.1.1.4 root 2892: "TARGET_HARD_FLOAT" 1.1.1.3 root 2893: "@ 2894: cmf%?\\t%0, %1 2895: cnf%?\\t%0, #%N1" 1.1.1.2 root 2896: [(set_attr "conds" "set") 2897: (set_attr "type" "f_2_r")]) 1.1 root 2898: 2899: (define_insn "" 1.1.1.2 root 2900: [(set (reg:CCFP 24) 2901: (compare:CCFP (float_extend:DF 2902: (match_operand:SF 0 "s_register_operand" "f,f")) 2903: (match_operand:DF 1 "fpu_add_operand" "fG,H")))] 1.1.1.4 root 2904: "TARGET_HARD_FLOAT" 1.1.1.3 root 2905: "@ 2906: cmf%?\\t%0, %1 2907: cnf%?\\t%0, #%N1" 1.1.1.2 root 2908: [(set_attr "conds" "set") 2909: (set_attr "type" "f_2_r")]) 1.1 root 2910: 2911: (define_insn "" 1.1.1.2 root 2912: [(set (reg:CCFP 24) 2913: (compare:CCFP (match_operand:DF 0 "s_register_operand" "f") 2914: (float_extend:DF 2915: (match_operand:SF 1 "s_register_operand" "f"))))] 1.1.1.4 root 2916: "TARGET_HARD_FLOAT" 1.1.1.3 root 2917: "cmf%?\\t%0, %1" 1.1.1.2 root 2918: [(set_attr "conds" "set") 2919: (set_attr "type" "f_2_r")]) 1.1 root 2920: 2921: (define_insn "" 1.1.1.2 root 2922: [(set (reg:CCFP 24) 2923: (compare:CCFP (match_operand:XF 0 "s_register_operand" "f,f") 2924: (match_operand:XF 1 "fpu_add_operand" "fG,H")))] 1.1.1.4 root 2925: "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" 1.1.1.3 root 2926: "@ 2927: cmf%?\\t%0, %1 2928: cnf%?\\t%0, #%N1" 1.1.1.2 root 2929: [(set_attr "conds" "set") 2930: (set_attr "type" "f_2_r")]) 1.1 root 2931: 2932: (define_insn "" 1.1.1.2 root 2933: [(set (reg:CCFPE 24) 2934: (compare:CCFPE (match_operand:SF 0 "s_register_operand" "f,f") 2935: (match_operand:SF 1 "fpu_add_operand" "fG,H")))] 1.1.1.4 root 2936: "TARGET_HARD_FLOAT" 1.1.1.3 root 2937: "@ 2938: cmf%?e\\t%0, %1 2939: cnf%?e\\t%0, #%N1" 1.1.1.2 root 2940: [(set_attr "conds" "set") 2941: (set_attr "type" "f_2_r")]) 1.1 root 2942: 2943: (define_insn "" 1.1.1.2 root 2944: [(set (reg:CCFPE 24) 2945: (compare:CCFPE (match_operand:DF 0 "s_register_operand" "f,f") 2946: (match_operand:DF 1 "fpu_add_operand" "fG,H")))] 1.1.1.4 root 2947: "TARGET_HARD_FLOAT" 1.1.1.3 root 2948: "@ 2949: cmf%?e\\t%0, %1 2950: cnf%?e\\t%0, #%N1" 1.1.1.2 root 2951: [(set_attr "conds" "set") 2952: (set_attr "type" "f_2_r")]) 1.1 root 2953: 1.1.1.2 root 2954: (define_insn "" 2955: [(set (reg:CCFPE 24) 2956: (compare:CCFPE (float_extend:DF 2957: (match_operand:SF 0 "s_register_operand" "f,f")) 2958: (match_operand:DF 1 "fpu_add_operand" "fG,H")))] 1.1.1.4 root 2959: "TARGET_HARD_FLOAT" 1.1.1.3 root 2960: "@ 2961: cmf%?e\\t%0, %1 2962: cnf%?e\\t%0, #%N1" 1.1.1.2 root 2963: [(set_attr "conds" "set") 2964: (set_attr "type" "f_2_r")]) 2965: 2966: (define_insn "" 2967: [(set (reg:CCFPE 24) 2968: (compare:CCFPE (match_operand:DF 0 "s_register_operand" "f") 2969: (float_extend:DF 2970: (match_operand:SF 1 "s_register_operand" "f"))))] 1.1.1.4 root 2971: "TARGET_HARD_FLOAT" 1.1.1.3 root 2972: "cmf%?e\\t%0, %1" 1.1.1.2 root 2973: [(set_attr "conds" "set") 2974: (set_attr "type" "f_2_r")]) 1.1 root 2975: 2976: (define_insn "" 1.1.1.2 root 2977: [(set (reg:CCFPE 24) 2978: (compare:CCFPE (match_operand:XF 0 "s_register_operand" "f,f") 2979: (match_operand:XF 1 "fpu_add_operand" "fG,H")))] 1.1.1.4 root 2980: "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" 1.1.1.3 root 2981: "@ 2982: cmf%?e\\t%0, %1 2983: cnf%?e\\t%0, #%N1" 1.1.1.2 root 2984: [(set_attr "conds" "set") 2985: (set_attr "type" "f_2_r")]) 2986: 2987: ; This insn allows redundant compares to be removed by cse, nothing should 2988: ; ever appear in the output file since (set (reg x) (reg x)) is a no-op that 2989: ; is deleted later on. The match_dup will match the mode here, so that 2990: ; mode changes of the condition codes aren't lost by this even though we don't 2991: ; specify what they are. 1.1 root 2992: 2993: (define_insn "" 1.1.1.2 root 2994: [(set (match_operand 0 "cc_register" "") (match_dup 0))] 2995: "" 1.1.1.3 root 2996: "\\t%@ deleted compare" 1.1.1.2 root 2997: [(set_attr "conds" "set") 2998: (set_attr "length" "0")]) 1.1 root 2999: 1.1.1.2 root 3000: 3001: ;; Conditional branch insns 1.1 root 3002: 1.1.1.2 root 3003: (define_expand "beq" 3004: [(set (pc) 3005: (if_then_else (eq (match_dup 1) (const_int 0)) 3006: (label_ref (match_operand 0 "" "")) 3007: (pc)))] 1.1 root 3008: "" 3009: " 3010: { 1.1.1.2 root 3011: operands[1] = gen_compare_reg (EQ, arm_compare_op0, arm_compare_op1, 3012: arm_compare_fp); 3013: } 3014: ") 1.1 root 3015: 1.1.1.2 root 3016: (define_expand "bne" 3017: [(set (pc) 3018: (if_then_else (ne (match_dup 1) (const_int 0)) 3019: (label_ref (match_operand 0 "" "")) 3020: (pc)))] 3021: "" 3022: " 3023: { 3024: operands[1] = gen_compare_reg (NE, arm_compare_op0, arm_compare_op1, 3025: arm_compare_fp); 3026: } 3027: ") 1.1 root 3028: 1.1.1.2 root 3029: (define_expand "bgt" 3030: [(set (pc) 3031: (if_then_else (gt (match_dup 1) (const_int 0)) 3032: (label_ref (match_operand 0 "" "")) 3033: (pc)))] 3034: "" 3035: " 3036: { 3037: operands[1] = gen_compare_reg (GT, arm_compare_op0, arm_compare_op1, 3038: arm_compare_fp); 3039: } 3040: ") 1.1 root 3041: 1.1.1.2 root 3042: (define_expand "ble" 3043: [(set (pc) 3044: (if_then_else (le (match_dup 1) (const_int 0)) 3045: (label_ref (match_operand 0 "" "")) 3046: (pc)))] 3047: "" 3048: " 3049: { 3050: operands[1] = gen_compare_reg (LE, arm_compare_op0, arm_compare_op1, 3051: arm_compare_fp); 3052: } 3053: ") 1.1 root 3054: 1.1.1.2 root 3055: (define_expand "bge" 3056: [(set (pc) 3057: (if_then_else (ge (match_dup 1) (const_int 0)) 3058: (label_ref (match_operand 0 "" "")) 3059: (pc)))] 3060: "" 3061: " 3062: { 3063: operands[1] = gen_compare_reg (GE, arm_compare_op0, arm_compare_op1, 3064: arm_compare_fp); 3065: } 3066: ") 1.1 root 3067: 1.1.1.2 root 3068: (define_expand "blt" 3069: [(set (pc) 3070: (if_then_else (lt (match_dup 1) (const_int 0)) 3071: (label_ref (match_operand 0 "" "")) 3072: (pc)))] 3073: "" 3074: " 3075: { 3076: operands[1] = gen_compare_reg (LT, arm_compare_op0, arm_compare_op1, 3077: arm_compare_fp); 3078: } 3079: ") 1.1 root 3080: 1.1.1.2 root 3081: (define_expand "bgtu" 3082: [(set (pc) 3083: (if_then_else (gtu (match_dup 1) (const_int 0)) 3084: (label_ref (match_operand 0 "" "")) 3085: (pc)))] 1.1 root 3086: "" 1.1.1.2 root 3087: " 3088: { 3089: operands[1] = gen_compare_reg (GTU, arm_compare_op0, arm_compare_op1, 3090: arm_compare_fp); 3091: } 3092: ") 1.1 root 3093: 1.1.1.2 root 3094: (define_expand "bleu" 1.1 root 3095: [(set (pc) 1.1.1.2 root 3096: (if_then_else (leu (match_dup 1) (const_int 0)) 3097: (label_ref (match_operand 0 "" "")) 3098: (pc)))] 1.1 root 3099: "" 1.1.1.2 root 3100: " 3101: { 3102: operands[1] = gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1, 3103: arm_compare_fp); 3104: } 1.1 root 3105: ") 3106: 1.1.1.2 root 3107: (define_expand "bgeu" 1.1 root 3108: [(set (pc) 1.1.1.2 root 3109: (if_then_else (geu (match_dup 1) (const_int 0)) 3110: (label_ref (match_operand 0 "" "")) 3111: (pc)))] 1.1 root 3112: "" 1.1.1.2 root 3113: " 3114: { 3115: operands[1] = gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1, 3116: arm_compare_fp); 3117: } 1.1 root 3118: ") 3119: 1.1.1.2 root 3120: (define_expand "bltu" 3121: [(set (pc) 3122: (if_then_else (ltu (match_dup 1) (const_int 0)) 3123: (label_ref (match_operand 0 "" "")) 3124: (pc)))] 1.1 root 3125: "" 1.1.1.2 root 3126: " 3127: { 3128: operands[1] = gen_compare_reg (LTU, arm_compare_op0, arm_compare_op1, 3129: arm_compare_fp); 3130: } 1.1 root 3131: ") 3132: 1.1.1.2 root 3133: ;; patterns to match conditional branch insns 1.1 root 3134: 3135: (define_insn "" 1.1.1.2 root 3136: [(set (pc) 3137: (if_then_else (match_operator 1 "comparison_operator" 3138: [(reg 24) (const_int 0)]) 3139: (label_ref (match_operand 0 "" "")) 3140: (pc)))] 1.1 root 3141: "" 3142: "* 1.1.1.2 root 3143: { 3144: extern int arm_ccfsm_state; 1.1 root 3145: 1.1.1.2 root 3146: if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2) 3147: { 3148: arm_ccfsm_state += 2; 3149: return \"\"; 3150: } 1.1.1.3 root 3151: return \"b%d1\\t%l0\"; 1.1.1.2 root 3152: }" 3153: [(set_attr "conds" "use")]) 1.1 root 3154: 3155: (define_insn "" 1.1.1.2 root 3156: [(set (pc) 3157: (if_then_else (match_operator 1 "comparison_operator" 3158: [(reg 24) (const_int 0)]) 3159: (pc) 3160: (label_ref (match_operand 0 "" ""))))] 1.1.1.3 root 3161: "REVERSIBLE_CC_MODE (GET_MODE (XEXP (operands[1], 0)))" 1.1 root 3162: "* 3163: { 1.1.1.2 root 3164: extern int arm_ccfsm_state; 3165: 3166: if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2) 3167: { 3168: arm_ccfsm_state += 2; 3169: return \"\"; 3170: } 1.1.1.3 root 3171: return \"b%D1\\t%l0\"; 1.1.1.2 root 3172: }" 3173: [(set_attr "conds" "use")]) 1.1 root 3174: 3175: 1.1.1.2 root 3176: ; scc insns 3177: 3178: (define_expand "seq" 3179: [(set (match_operand:SI 0 "s_register_operand" "=r") 3180: (eq:SI (match_dup 1) (const_int 0)))] 3181: "" 3182: " 3183: { 3184: operands[1] = gen_compare_reg (EQ, arm_compare_op0, arm_compare_op1, 3185: arm_compare_fp); 3186: } 3187: ") 3188: 3189: (define_expand "sne" 3190: [(set (match_operand:SI 0 "s_register_operand" "=r") 3191: (ne:SI (match_dup 1) (const_int 0)))] 3192: "" 3193: " 3194: { 3195: operands[1] = gen_compare_reg (NE, arm_compare_op0, arm_compare_op1, 3196: arm_compare_fp); 3197: } 3198: ") 3199: 3200: (define_expand "sgt" 3201: [(set (match_operand:SI 0 "s_register_operand" "=r") 3202: (gt:SI (match_dup 1) (const_int 0)))] 3203: "" 3204: " 3205: { 3206: operands[1] = gen_compare_reg (GT, arm_compare_op0, arm_compare_op1, 3207: arm_compare_fp); 3208: } 3209: ") 3210: 3211: (define_expand "sle" 3212: [(set (match_operand:SI 0 "s_register_operand" "=r") 3213: (le:SI (match_dup 1) (const_int 0)))] 3214: "" 3215: " 3216: { 3217: operands[1] = gen_compare_reg (LE, arm_compare_op0, arm_compare_op1, 3218: arm_compare_fp); 3219: } 3220: ") 3221: 3222: (define_expand "sge" 3223: [(set (match_operand:SI 0 "s_register_operand" "=r") 3224: (ge:SI (match_dup 1) (const_int 0)))] 3225: "" 3226: " 3227: { 3228: operands[1] = gen_compare_reg (GE, arm_compare_op0, arm_compare_op1, 3229: arm_compare_fp); 3230: } 3231: ") 3232: 3233: (define_expand "slt" 3234: [(set (match_operand:SI 0 "s_register_operand" "=r") 3235: (lt:SI (match_dup 1) (const_int 0)))] 3236: "" 3237: " 3238: { 3239: operands[1] = gen_compare_reg (LT, arm_compare_op0, arm_compare_op1, 3240: arm_compare_fp); 3241: } 3242: ") 3243: 3244: (define_expand "sgtu" 3245: [(set (match_operand:SI 0 "s_register_operand" "=r") 3246: (gtu:SI (match_dup 1) (const_int 0)))] 3247: "" 3248: " 3249: { 3250: operands[1] = gen_compare_reg (GTU, arm_compare_op0, arm_compare_op1, 3251: arm_compare_fp); 3252: } 3253: ") 3254: 3255: (define_expand "sleu" 3256: [(set (match_operand:SI 0 "s_register_operand" "=r") 3257: (leu:SI (match_dup 1) (const_int 0)))] 3258: "" 3259: " 3260: { 3261: operands[1] = gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1, 3262: arm_compare_fp); 3263: } 3264: ") 3265: 3266: (define_expand "sgeu" 3267: [(set (match_operand:SI 0 "s_register_operand" "=r") 3268: (geu:SI (match_dup 1) (const_int 0)))] 3269: "" 3270: " 3271: { 3272: operands[1] = gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1, 3273: arm_compare_fp); 3274: } 3275: ") 3276: 3277: (define_expand "sltu" 3278: [(set (match_operand:SI 0 "s_register_operand" "=r") 3279: (ltu:SI (match_dup 1) (const_int 0)))] 3280: "" 3281: " 3282: { 3283: operands[1] = gen_compare_reg (LTU, arm_compare_op0, arm_compare_op1, 3284: arm_compare_fp); 3285: } 3286: ") 3287: 3288: (define_insn "" 3289: [(set (match_operand:SI 0 "s_register_operand" "=r") 3290: (match_operator:SI 1 "comparison_operator" [(reg 24) (const_int 0)]))] 3291: "" 1.1.1.3 root 3292: "mov%D1\\t%0, #0\;mov%d1\\t%0, #1" 1.1.1.2 root 3293: [(set_attr "conds" "use") 1.1.1.3 root 3294: (set_attr "length" "8")]) 1.1.1.2 root 3295: 3296: (define_insn "" 3297: [(set (match_operand:SI 0 "s_register_operand" "=r") 3298: (neg:SI (match_operator:SI 1 "comparison_operator" 3299: [(reg 24) (const_int 0)])))] 3300: "" 1.1.1.3 root 3301: "mov%D1\\t%0, #0\;mvn%d1\\t%0, #0" 1.1.1.2 root 3302: [(set_attr "conds" "use") 1.1.1.3 root 3303: (set_attr "length" "8")]) 1.1.1.2 root 3304: 3305: (define_insn "" 3306: [(set (match_operand:SI 0 "s_register_operand" "=r") 3307: (not:SI (match_operator:SI 1 "comparison_operator" 3308: [(reg 24) (const_int 0)])))] 3309: "" 1.1.1.3 root 3310: "mov%D1\\t%0, #0\;mvn%d1\\t%0, #1" 1.1.1.2 root 3311: [(set_attr "conds" "use") 1.1.1.3 root 3312: (set_attr "length" "8")]) 1.1.1.2 root 3313: 3314: 1.1.1.4 root 3315: ;; Conditional move insns 3316: 3317: (define_expand "movsicc" 3318: [(set (match_operand:SI 0 "register_operand" "") 1.1.1.5 ! root 3319: (if_then_else:SI (match_operand 1 "comparison_operator" "") ! 3320: (match_operand:SI 2 "arm_not_operand" "") ! 3321: (match_operand:SI 3 "register_operand" "")))] 1.1.1.4 root 3322: "" 3323: " 3324: { 3325: enum rtx_code code = GET_CODE (operands[1]); 3326: rtx ccreg = gen_compare_reg (code, arm_compare_op0, arm_compare_op1, 3327: arm_compare_fp); 3328: 3329: operands[1] = gen_rtx (code, VOIDmode, ccreg, const0_rtx); 3330: }") 3331: 3332: (define_expand "movsfcc" 3333: [(set (match_operand:SF 0 "register_operand" "") 1.1.1.5 ! root 3334: (if_then_else:SF (match_operand 1 "comparison_operator" "") ! 3335: (match_operand:SF 2 "nonmemory_operand" "") ! 3336: (match_operand:SF 3 "register_operand" "")))] 1.1.1.4 root 3337: "" 3338: " 3339: { 3340: enum rtx_code code = GET_CODE (operands[1]); 3341: rtx ccreg = gen_compare_reg (code, arm_compare_op0, arm_compare_op1, 3342: arm_compare_fp); 3343: 3344: operands[1] = gen_rtx (code, VOIDmode, ccreg, const0_rtx); 3345: }") 3346: 3347: (define_expand "movdfcc" 3348: [(set (match_operand:DF 0 "register_operand" "") 1.1.1.5 ! root 3349: (if_then_else:DF (match_operand 1 "comparison_operator" "") ! 3350: (match_operand:DF 2 "nonmemory_operand" "") ! 3351: (match_operand:DF 3 "register_operand" "")))] 1.1.1.4 root 3352: "TARGET_HARD_FLOAT" 3353: " 3354: { 3355: enum rtx_code code = GET_CODE (operands[1]); 3356: rtx ccreg = gen_compare_reg (code, arm_compare_op0, arm_compare_op1, 3357: arm_compare_fp); 3358: 3359: operands[1] = gen_rtx (code, VOIDmode, ccreg, const0_rtx); 3360: }") 3361: 3362: (define_insn "*movsicc_insn" 3363: [(set (match_operand:SI 0 "register_operand" "=r,r") 1.1.1.5 ! root 3364: (if_then_else:SI (match_operator 1 "comparison_operator" ! 3365: [(reg 24) (const_int 0)]) ! 3366: (match_operand:SI 2 "arm_not_operand" "rI,K") ! 3367: (match_operand:SI 3 "register_operand" "0,0")))] 1.1.1.4 root 3368: "" 3369: "@ 3370: mov%d1\\t%0, %2 3371: mvn%d1\\t%0, #%B2" 3372: [(set_attr "type" "*,*") 3373: (set_attr "conds" "use,use")]) 3374: 3375: (define_insn "*movsfcc_hard_insn" 3376: [(set (match_operand:SF 0 "register_operand" "=f") 1.1.1.5 ! root 3377: (if_then_else:SF (match_operator 1 "comparison_operator" ! 3378: [(reg 24) (const_int 0)]) ! 3379: (match_operand:SF 2 "register_operand" "f") ! 3380: (match_operand:SF 3 "register_operand" "0")))] 1.1.1.4 root 3381: "TARGET_HARD_FLOAT" 3382: "mvf%d1s\\t%0, %2" 3383: [(set_attr "type" "ffarith") 3384: (set_attr "conds" "use")]) 3385: 3386: (define_insn "*movsfcc_soft_insn" 3387: [(set (match_operand:SF 0 "register_operand" "=r") 1.1.1.5 ! root 3388: (if_then_else:SF (match_operator 1 "comparison_operator" ! 3389: [(reg 24) (const_int 0)]) ! 3390: (match_operand:SF 2 "register_operand" "r") ! 3391: (match_operand:SF 3 "register_operand" "0")))] 1.1.1.4 root 3392: "TARGET_SOFT_FLOAT" 3393: "mov%d1\\t%0, %2" 3394: [(set_attr "type" "*") 3395: (set_attr "conds" "use")]) 3396: 3397: (define_insn "*movdfcc_insn" 3398: [(set (match_operand:DF 0 "register_operand" "=f") 1.1.1.5 ! root 3399: (if_then_else:DF (match_operator 1 "comparison_operator" ! 3400: [(reg 24) (const_int 0)]) ! 3401: (match_operand:DF 2 "register_operand" "f") ! 3402: (match_operand:DF 3 "register_operand" "0")))] 1.1.1.4 root 3403: "TARGET_HARD_FLOAT" 3404: "mvf%d1d\\t%0, %2" 3405: [(set_attr "type" "ffarith") 3406: (set_attr "conds" "use")]) 3407: 1.1.1.2 root 3408: ;; Jump and linkage insns 3409: 3410: (define_insn "jump" 3411: [(set (pc) 3412: (label_ref (match_operand 0 "" "")))] 3413: "" 3414: "* 3415: { 3416: extern int arm_ccfsm_state; 3417: 3418: if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2) 3419: { 3420: arm_ccfsm_state += 2; 3421: return \"\"; 3422: } 1.1.1.3 root 3423: return \"b%?\\t%l0\"; 1.1.1.2 root 3424: }") 3425: 3426: (define_expand "call" 3427: [(parallel [(call (match_operand 0 "memory_operand" "") 3428: (match_operand 1 "general_operand" "")) 3429: (clobber (reg:SI 14))])] 3430: "" 3431: "") 3432: 3433: (define_insn "" 3434: [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r")) 3435: (match_operand 1 "" "g")) 3436: (clobber (reg:SI 14))] 3437: "" 3438: "* 1.1.1.3 root 3439: return output_call (operands); 1.1.1.2 root 3440: " 3441: [(set (attr "conds") 3442: (if_then_else (eq_attr "cpu" "arm6") 3443: (const_string "clob") 3444: (const_string "nocond"))) 3445: ;; length is worst case, normally it is only two 1.1.1.3 root 3446: (set_attr "length" "12") 1.1.1.2 root 3447: (set_attr "type" "call")]) 3448: 3449: (define_insn "" 3450: [(call (mem:SI (match_operand 0 "memory_operand" "m")) 3451: (match_operand 1 "general_operand" "g")) 3452: (clobber (reg:SI 14))] 3453: "" 3454: "* 1.1.1.3 root 3455: return output_call_mem (operands); 1.1.1.2 root 3456: " 3457: [(set (attr "conds") 3458: (if_then_else (eq_attr "cpu" "arm6") 3459: (const_string "clob") 3460: (const_string "nocond"))) 1.1.1.3 root 3461: (set_attr "length" "12") 1.1.1.2 root 3462: (set_attr "type" "call")]) 3463: 3464: (define_expand "call_value" 3465: [(parallel [(set (match_operand 0 "" "=rf") 3466: (call (match_operand 1 "memory_operand" "m") 3467: (match_operand 2 "general_operand" "g"))) 3468: (clobber (reg:SI 14))])] 3469: "" 3470: "") 3471: 3472: (define_insn "" 3473: [(set (match_operand 0 "" "=rf") 3474: (call (mem:SI (match_operand:SI 1 "s_register_operand" "r")) 3475: (match_operand 2 "general_operand" "g"))) 3476: (clobber (reg:SI 14))] 3477: "" 3478: "* 1.1.1.3 root 3479: return output_call (&operands[1]); 1.1.1.2 root 3480: " 3481: [(set (attr "conds") 3482: (if_then_else (eq_attr "cpu" "arm6") 3483: (const_string "clob") 3484: (const_string "nocond"))) 1.1.1.3 root 3485: (set_attr "length" "12") 1.1.1.2 root 3486: (set_attr "type" "call")]) 3487: 3488: (define_insn "" 3489: [(set (match_operand 0 "" "=rf") 3490: (call (mem:SI (match_operand 1 "memory_operand" "m")) 3491: (match_operand 2 "general_operand" "g"))) 3492: (clobber (reg:SI 14))] 3493: "! CONSTANT_ADDRESS_P (XEXP (operands[1], 0))" 3494: "* 1.1.1.3 root 3495: return output_call_mem (&operands[1]); 1.1.1.2 root 3496: " 3497: [(set (attr "conds") 3498: (if_then_else (eq_attr "cpu" "arm6") 3499: (const_string "clob") 3500: (const_string "nocond"))) 1.1.1.3 root 3501: (set_attr "length" "12") 1.1.1.2 root 3502: (set_attr "type" "call")]) 3503: 3504: ;; Allow calls to SYMBOL_REFs specially as they are not valid general addresses 3505: ;; The 'a' causes the operand to be treated as an address, i.e. no '#' output. 3506: 3507: (define_insn "" 3508: [(call (mem:SI (match_operand:SI 0 "" "i")) 3509: (match_operand:SI 1 "general_operand" "g")) 3510: (clobber (reg:SI 14))] 3511: "GET_CODE (operands[0]) == SYMBOL_REF" 1.1.1.3 root 3512: "bl%?\\t%a0" 1.1.1.2 root 3513: [(set (attr "conds") 3514: (if_then_else (eq_attr "cpu" "arm6") 3515: (const_string "clob") 3516: (const_string "nocond"))) 3517: (set_attr "type" "call")]) 3518: 3519: (define_insn "" 3520: [(set (match_operand 0 "s_register_operand" "=rf") 3521: (call (mem:SI (match_operand:SI 1 "" "i")) 3522: (match_operand:SI 2 "general_operand" "g"))) 3523: (clobber (reg:SI 14))] 3524: "GET_CODE(operands[1]) == SYMBOL_REF" 1.1.1.3 root 3525: "bl%?\\t%a1" 1.1.1.2 root 3526: [(set (attr "conds") 3527: (if_then_else (eq_attr "cpu" "arm6") 3528: (const_string "clob") 3529: (const_string "nocond"))) 3530: (set_attr "type" "call")]) 3531: 3532: ;; Often the return insn will be the same as loading from memory, so set attr 3533: (define_insn "return" 3534: [(return)] 3535: "USE_RETURN_INSN" 3536: "* 3537: { 3538: extern int arm_ccfsm_state; 3539: 3540: if (arm_ccfsm_state == 2) 3541: { 3542: arm_ccfsm_state += 2; 3543: return \"\"; 3544: } 3545: return output_return_instruction (NULL, TRUE); 3546: }" 3547: [(set_attr "type" "load")]) 3548: 3549: (define_insn "" 3550: [(set (pc) 3551: (if_then_else (match_operator 0 "comparison_operator" 3552: [(reg 24) (const_int 0)]) 3553: (return) 3554: (pc)))] 3555: "USE_RETURN_INSN" 3556: "* 3557: { 3558: extern int arm_ccfsm_state; 3559: 3560: if (arm_ccfsm_state == 2) 3561: { 3562: arm_ccfsm_state += 2; 3563: return \"\"; 3564: } 3565: return output_return_instruction (operands[0], TRUE); 3566: }" 3567: [(set_attr "conds" "use") 3568: (set_attr "type" "load")]) 3569: 3570: (define_insn "" 3571: [(set (pc) 3572: (if_then_else (match_operator 0 "comparison_operator" 3573: [(reg 24) (const_int 0)]) 3574: (pc) 3575: (return)))] 3576: "USE_RETURN_INSN" 3577: "* 3578: { 3579: extern int arm_ccfsm_state; 3580: 3581: if (arm_ccfsm_state == 2) 3582: { 3583: arm_ccfsm_state += 2; 3584: return \"\"; 3585: } 3586: return output_return_instruction 3587: (gen_rtx (reverse_condition (GET_CODE (operands[0])), 3588: GET_MODE (operands[0]), XEXP (operands[0], 0), 3589: XEXP (operands[0], 1)), 3590: TRUE); 3591: }" 3592: [(set_attr "conds" "use") 3593: (set_attr "type" "load")]) 3594: 3595: ;; Call subroutine returning any type. 3596: 3597: (define_expand "untyped_call" 3598: [(parallel [(call (match_operand 0 "" "") 3599: (const_int 0)) 3600: (match_operand 1 "" "") 3601: (match_operand 2 "" "")])] 3602: "" 3603: " 3604: { 3605: int i; 3606: 3607: emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); 3608: 3609: for (i = 0; i < XVECLEN (operands[2], 0); i++) 3610: { 3611: rtx set = XVECEXP (operands[2], 0, i); 3612: emit_move_insn (SET_DEST (set), SET_SRC (set)); 3613: } 3614: 3615: /* The optimizer does not know that the call sets the function value 3616: registers we stored in the result block. We avoid problems by 3617: claiming that all hard registers are used and clobbered at this 3618: point. */ 3619: emit_insn (gen_blockage ()); 3620: 3621: DONE; 3622: }") 3623: 3624: ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 3625: ;; all of memory. This blocks insns from being moved across this point. 3626: 3627: (define_insn "blockage" 3628: [(unspec_volatile [(const_int 0)] 0)] 3629: "" 3630: "" 3631: [(set_attr "length" "0") 3632: (set_attr "type" "block")]) 3633: 3634: (define_insn "tablejump" 3635: [(set (pc) 3636: (match_operand:SI 0 "s_register_operand" "r")) 3637: (use (label_ref (match_operand 1 "" "")))] 3638: "" 1.1.1.3 root 3639: "mov%?\\t%|pc, %0\\t%@ table jump, label %l1") 1.1.1.2 root 3640: 3641: (define_insn "" 3642: [(set (pc) 3643: (match_operand:SI 0 "memory_operand" "m")) 3644: (use (label_ref (match_operand 1 "" "")))] 3645: "" 1.1.1.3 root 3646: "ldr%?\\t%|pc, %0\\t%@ table jump, label %l1" 1.1.1.2 root 3647: [(set_attr "type" "load")]) 3648: 3649: (define_insn "indirect_jump" 3650: [(set (pc) 3651: (match_operand:SI 0 "s_register_operand" "r"))] 3652: "" 1.1.1.3 root 3653: "mov%?\\t%|pc, %0\\t%@ indirect jump") 1.1.1.2 root 3654: 3655: (define_insn "" 3656: [(set (pc) 3657: (match_operand:SI 0 "memory_operand" "m"))] 3658: "" 1.1.1.3 root 3659: "ldr%?\\t%|pc, %0\\t%@ indirect jump" 1.1.1.2 root 3660: [(set_attr "type" "load")]) 3661: 3662: ;; Misc insns 3663: 3664: (define_insn "nop" 3665: [(const_int 0)] 3666: "" 1.1.1.3 root 3667: "mov%?\\tr0, r0\\t%@ nop") 1.1.1.2 root 3668: 3669: ;; Patterns to allow combination of arithmetic, cond code and shifts 3670: 3671: (define_insn "" 3672: [(set (match_operand:SI 0 "s_register_operand" "=r") 3673: (match_operator:SI 1 "shiftable_operator" 3674: [(match_operator:SI 3 "shift_operator" 3675: [(match_operand:SI 4 "s_register_operand" "r") 1.1.1.3 root 3676: (match_operand:SI 5 "reg_or_int_operand" "rI")]) 1.1.1.2 root 3677: (match_operand:SI 2 "s_register_operand" "r")]))] 3678: "" 1.1.1.3 root 3679: "%i1%?\\t%0, %2, %4%S3") 1.1.1.2 root 3680: 3681: (define_insn "" 3682: [(set (reg:CC_NOOV 24) 3683: (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator" 3684: [(match_operator:SI 3 "shift_operator" 3685: [(match_operand:SI 4 "s_register_operand" "r") 1.1.1.3 root 3686: (match_operand:SI 5 "reg_or_int_operand" "rI")]) 1.1.1.2 root 3687: (match_operand:SI 2 "s_register_operand" "r")]) 3688: (const_int 0))) 3689: (set (match_operand:SI 0 "s_register_operand" "=r") 3690: (match_op_dup 1 [(match_op_dup 3 [(match_dup 4) (match_dup 5)]) 3691: (match_dup 2)]))] 3692: "" 1.1.1.3 root 3693: "%i1%?s\\t%0, %2, %4%S3" 1.1.1.2 root 3694: [(set_attr "conds" "set")]) 3695: 3696: (define_insn "" 3697: [(set (reg:CC_NOOV 24) 3698: (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator" 3699: [(match_operator:SI 3 "shift_operator" 3700: [(match_operand:SI 4 "s_register_operand" "r") 1.1.1.3 root 3701: (match_operand:SI 5 "reg_or_int_operand" "rI")]) 1.1.1.2 root 3702: (match_operand:SI 2 "s_register_operand" "r")]) 3703: (const_int 0))) 3704: (clobber (match_scratch:SI 0 "=r"))] 3705: "" 1.1.1.3 root 3706: "%i1%?s\\t%0, %2, %4%S3" 1.1.1.2 root 3707: [(set_attr "conds" "set")]) 3708: 3709: (define_insn "" 3710: [(set (match_operand:SI 0 "s_register_operand" "=r") 3711: (minus:SI (match_operand:SI 1 "s_register_operand" "r") 3712: (match_operator:SI 2 "shift_operator" 3713: [(match_operand:SI 3 "s_register_operand" "r") 1.1.1.3 root 3714: (match_operand:SI 4 "reg_or_int_operand" "rM")])))] 1.1.1.2 root 3715: "" 1.1.1.3 root 3716: "sub%?\\t%0, %1, %3%S2") 1.1.1.2 root 3717: 3718: (define_insn "" 3719: [(set (reg:CC_NOOV 24) 1.1.1.3 root 3720: (compare:CC_NOOV 3721: (minus:SI (match_operand:SI 1 "s_register_operand" "r") 3722: (match_operator:SI 2 "shift_operator" 3723: [(match_operand:SI 3 "s_register_operand" "r") 3724: (match_operand:SI 4 "reg_or_int_operand" "rM")])) 3725: (const_int 0))) 1.1.1.2 root 3726: (set (match_operand:SI 0 "s_register_operand" "=r") 3727: (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3) 3728: (match_dup 4)])))] 3729: "" 1.1.1.3 root 3730: "sub%?s\\t%0, %1, %3%S2" 1.1.1.2 root 3731: [(set_attr "conds" "set")]) 3732: 3733: (define_insn "" 3734: [(set (reg:CC_NOOV 24) 1.1.1.3 root 3735: (compare:CC_NOOV 3736: (minus:SI (match_operand:SI 1 "s_register_operand" "r") 3737: (match_operator:SI 2 "shift_operator" 3738: [(match_operand:SI 3 "s_register_operand" "r") 3739: (match_operand:SI 4 "reg_or_int_operand" "rM")])) 3740: (const_int 0))) 1.1.1.2 root 3741: (clobber (match_scratch:SI 0 "=r"))] 3742: "" 1.1.1.3 root 3743: "sub%?s\\t%0, %1, %3%S2" 1.1.1.2 root 3744: [(set_attr "conds" "set")]) 3745: 3746: ;; These variants of the above insns can occur if the first operand is the 3747: ;; frame pointer and we eliminate that. This is a kludge, but there doesn't 3748: ;; seem to be a way around it. Most of the predicates have to be null 3749: ;; because the format can be generated part way through reload, so 3750: ;; if we don't match it as soon as it becomes available, reload doesn't know 3751: ;; how to reload pseudos that haven't got hard registers; the constraints will 3752: ;; sort everything out. 3753: 3754: (define_insn "" 3755: [(set (match_operand:SI 0 "" "=&r") 3756: (plus:SI (plus:SI (match_operator:SI 5 "shift_operator" 3757: [(match_operand:SI 3 "" "r") 1.1.1.3 root 3758: (match_operand:SI 4 "" "rM")]) 1.1.1.2 root 3759: (match_operand:SI 2 "" "r")) 3760: (match_operand:SI 1 "const_int_operand" "n")))] 3761: "reload_in_progress" 3762: "* 1.1.1.3 root 3763: output_asm_insn (\"add%?\\t%0, %2, %3%S5\", operands); 1.1.1.2 root 3764: operands[2] = operands[1]; 3765: operands[1] = operands[0]; 3766: return output_add_immediate (operands); 1.1.1.3 root 3767: " 1.1.1.2 root 3768: ; we have no idea how long the add_immediate is, it could be up to 4. 1.1.1.3 root 3769: [(set_attr "length" "20")]) 1.1.1.2 root 3770: 3771: (define_insn "" 3772: [(set (reg:CC_NOOV 24) 3773: (compare:CC_NOOV (plus:SI 3774: (plus:SI 3775: (match_operator:SI 5 "shift_operator" 3776: [(match_operand:SI 3 "" "r") 1.1.1.3 root 3777: (match_operand:SI 4 "" "rM")]) 1.1.1.2 root 3778: (match_operand:SI 1 "" "r")) 3779: (match_operand:SI 2 "const_int_operand" "n")) 3780: (const_int 0))) 3781: (set (match_operand:SI 0 "" "=&r") 3782: (plus:SI (plus:SI (match_op_dup 5 [(match_dup 3) (match_dup 4)]) 3783: (match_dup 1)) 3784: (match_dup 2)))] 3785: "reload_in_progress" 3786: "* 3787: output_add_immediate (operands); 1.1.1.3 root 3788: return \"add%?s\\t%0, %0, %3%S5\"; 3789: " 1.1.1.2 root 3790: [(set_attr "conds" "set") 1.1.1.3 root 3791: (set_attr "length" "20")]) 1.1.1.2 root 3792: 3793: (define_insn "" 3794: [(set (reg:CC_NOOV 24) 3795: (compare:CC_NOOV (plus:SI 3796: (plus:SI 3797: (match_operator:SI 5 "shift_operator" 3798: [(match_operand:SI 3 "" "r") 1.1.1.3 root 3799: (match_operand:SI 4 "" "rM")]) 1.1.1.2 root 3800: (match_operand:SI 1 "" "r")) 3801: (match_operand:SI 2 "const_int_operand" "n")) 3802: (const_int 0))) 3803: (clobber (match_scratch:SI 0 "=&r"))] 3804: "reload_in_progress" 3805: "* 3806: output_add_immediate (operands); 1.1.1.3 root 3807: return \"add%?s\\t%0, %0, %3%S5\"; 3808: " 1.1.1.2 root 3809: [(set_attr "conds" "set") 1.1.1.3 root 3810: (set_attr "length" "20")]) 1.1.1.2 root 3811: 3812: ;; These are similar, but are needed when the mla pattern contains the 3813: ;; eliminated register as operand 3. 3814: 3815: (define_insn "" 3816: [(set (match_operand:SI 0 "" "=&r,&r") 3817: (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "" "%0,r") 3818: (match_operand:SI 2 "" "r,r")) 3819: (match_operand:SI 3 "" "r,r")) 3820: (match_operand:SI 4 "const_int_operand" "n,n")))] 3821: "reload_in_progress" 3822: "* 1.1.1.3 root 3823: output_asm_insn (\"mla%?\\t%0, %2, %1, %3\", operands); 1.1.1.2 root 3824: operands[2] = operands[4]; 3825: operands[1] = operands[0]; 3826: return output_add_immediate (operands); 3827: " 1.1.1.3 root 3828: [(set_attr "length" "20")]) 1.1.1.2 root 3829: 3830: (define_insn "" 3831: [(set (reg:CC_NOOV 24) 3832: (compare:CC_NOOV (plus:SI (plus:SI (mult:SI 3833: (match_operand:SI 3 "" "r") 3834: (match_operand:SI 4 "" "r")) 3835: (match_operand:SI 1 "" "r")) 3836: (match_operand:SI 2 "const_int_operand" "n")) 3837: (const_int 0))) 3838: (set (match_operand:SI 0 "" "=&r") 3839: (plus:SI (plus:SI (mult:SI (match_dup 3) (match_dup 4)) (match_dup 1)) 3840: (match_dup 2)))] 3841: "reload_in_progress" 3842: "* 3843: output_add_immediate (operands); 1.1.1.3 root 3844: output_asm_insn (\"mla%?s\\t%0, %3, %4, %0\", operands); 3845: return \"\"; 1.1.1.2 root 3846: " 1.1.1.3 root 3847: [(set_attr "length" "20") 1.1.1.2 root 3848: (set_attr "conds" "set")]) 3849: 3850: (define_insn "" 3851: [(set (reg:CC_NOOV 24) 3852: (compare:CC_NOOV (plus:SI (plus:SI (mult:SI 3853: (match_operand:SI 3 "" "r") 3854: (match_operand:SI 4 "" "r")) 3855: (match_operand:SI 1 "" "r")) 3856: (match_operand:SI 2 "const_int_operand" "n")) 3857: (const_int 0))) 3858: (clobber (match_scratch:SI 0 "=&r"))] 3859: "reload_in_progress" 3860: "* 3861: output_add_immediate (operands); 1.1.1.3 root 3862: return \"mla%?s\\t%0, %3, %4, %0\"; 1.1.1.2 root 3863: " 1.1.1.3 root 3864: [(set_attr "length" "20") 1.1.1.2 root 3865: (set_attr "conds" "set")]) 3866: 3867: 3868: 3869: 3870: (define_insn "" 3871: [(set (match_operand:SI 0 "s_register_operand" "=r") 3872: (and:SI (match_operator 1 "comparison_operator" 1.1.1.3 root 3873: [(match_operand 3 "reversible_cc_register" "") (const_int 0)]) 1.1.1.2 root 3874: (match_operand:SI 2 "s_register_operand" "r")))] 3875: "" 1.1.1.3 root 3876: "mov%D1\\t%0, #0\;and%d1\\t%0, %2, #1" 1.1.1.2 root 3877: [(set_attr "conds" "use") 1.1.1.3 root 3878: (set_attr "length" "8")]) 1.1.1.2 root 3879: 3880: (define_insn "" 3881: [(set (match_operand:SI 0 "s_register_operand" "=r,r") 3882: (ior:SI (match_operator 2 "comparison_operator" 3883: [(reg 24) (const_int 0)]) 3884: (match_operand:SI 1 "s_register_operand" "0,?r")))] 3885: "" 1.1.1.3 root 3886: "@ 3887: orr%d2\\t%0, %1, #1 3888: mov%D2\\t%0, %1\;orr%d2\\t%0, %1, #1" 1.1.1.2 root 3889: [(set_attr "conds" "use") 1.1.1.3 root 3890: (set_attr "length" "4,8")]) 1.1.1.2 root 3891: 3892: (define_insn "" 1.1.1.3 root 3893: [(set (match_operand:SI 0 "s_register_operand" "=r,r") 1.1.1.2 root 3894: (match_operator 1 "comparison_operator" 1.1.1.3 root 3895: [(match_operand:SI 2 "s_register_operand" "r,r") 3896: (match_operand:SI 3 "arm_add_operand" "rI,L")])) 1.1.1.2 root 3897: (clobber (reg 24))] 3898: "" 3899: "* 3900: if (GET_CODE (operands[1]) == LT && operands[3] == const0_rtx) 1.1.1.3 root 3901: return \"mov\\t%0, %2, lsr #31\"; 3902: 1.1.1.2 root 3903: if (GET_CODE (operands[1]) == GE && operands[3] == const0_rtx) 1.1.1.3 root 3904: return \"mvn\\t%0, %2\;mov\\t%0, %0, lsr #31\"; 3905: 1.1.1.2 root 3906: if (GET_CODE (operands[1]) == NE) 3907: { 1.1.1.3 root 3908: if (which_alternative == 1) 3909: return \"adds\\t%0, %2, #%n3\;movne\\t%0, #1\"; 3910: return \"subs\\t%0, %2, %3\;movne\\t%0, #1\"; 1.1.1.2 root 3911: } 1.1.1.3 root 3912: if (which_alternative == 1) 3913: output_asm_insn (\"cmn\\t%2, #%n3\", operands); 1.1.1.2 root 3914: else 1.1.1.3 root 3915: output_asm_insn (\"cmp\\t%2, %3\", operands); 3916: return \"mov%D1\\t%0, #0\;mov%d1\\t%0, #1\"; 1.1.1.2 root 3917: " 3918: [(set_attr "conds" "clob") 1.1.1.3 root 3919: (set_attr "length" "12")]) 1.1.1.2 root 3920: 3921: (define_insn "" 3922: [(set (match_operand:SI 0 "s_register_operand" "=&r") 3923: (ior:SI (match_operator 1 "comparison_operator" 3924: [(match_operand:SI 2 "s_register_operand" "r") 3925: (match_operand:SI 3 "arm_rhs_operand" "rI")]) 3926: (match_operator 4 "comparison_operator" 3927: [(match_operand:SI 5 "s_register_operand" "r") 3928: (match_operand:SI 6 "arm_rhs_operand" "rI")]))) 3929: (clobber (reg 24))] 3930: "" 3931: "* 3932: { 3933: int dominant = comparison_dominates_p (GET_CODE (operands[4]), 3934: GET_CODE (operands[1])); 3935: 1.1.1.3 root 3936: output_asm_insn (dominant ? \"cmp\\t%5, %6\" : \"cmp\\t%2, %3\", 3937: operands); 3938: output_asm_insn (\"mov\\t%0, #0\", operands); 1.1.1.2 root 3939: if (GET_CODE (operands[1]) == GET_CODE (operands[4]) 3940: || comparison_dominates_p (GET_CODE (operands[1]), 3941: GET_CODE (operands[4])) 3942: || dominant) 1.1.1.3 root 3943: output_asm_insn (dominant ? \"cmp%D4\\t%2, %3\" : \"cmp%D1\\t%5,%6\", 3944: operands); 1.1.1.2 root 3945: else 1.1.1.3 root 3946: output_asm_insn (\"mov%d1\\t%0, #1\;cmp\\t%5, %6\", operands); 3947: return dominant ? \"mov%d1\\t%0, #1\" : \"mov%d4\\t%0, #1\"; 1.1.1.2 root 3948: } 3949: " 3950: [(set_attr "conds" "clob") 3951: ; worst case length 1.1.1.3 root 3952: (set_attr "length" "20")]) 1.1.1.2 root 3953: 3954: (define_split 3955: [(set (pc) 1.1.1.3 root 3956: (if_then_else 3957: (match_operator 5 "equality_operator" 3958: [(ior:SI (match_operator 6 "comparison_operator" 3959: [(match_operand:SI 0 "s_register_operand" "") 3960: (match_operand:SI 1 "arm_add_operand" "")]) 3961: (match_operator 7 "comparison_operator" 3962: [(match_operand:SI 2 "s_register_operand" "") 3963: (match_operand:SI 3 "arm_add_operand" "")])) 3964: (const_int 0)]) 3965: (label_ref (match_operand 4 "" "")) 3966: (pc))) 1.1.1.2 root 3967: (clobber (reg 24))] 3968: "(GET_CODE (operands[6]) == GET_CODE (operands[7]) 3969: || comparison_dominates_p (GET_CODE (operands[6]), GET_CODE (operands[7])) 3970: || comparison_dominates_p (GET_CODE (operands[7]), GET_CODE (operands[6])))" 3971: [(set (reg:CC 24) 3972: (compare:CC (ior:CC (match_op_dup 6 3973: [(match_dup 0) (match_dup 1)]) 3974: (match_op_dup 7 3975: [(match_dup 2) (match_dup 3)])) 3976: (const_int 0))) 3977: (set (pc) 3978: (if_then_else (match_op_dup 5 [(reg:CC 24) (const_int 0)]) 3979: (label_ref (match_dup 4)) 3980: (pc)))] 3981: " 3982: { 3983: enum rtx_code code = comparison_dominates_p (GET_CODE (operands[6]), 3984: GET_CODE (operands[7])) 3985: ? GET_CODE (operands[7]) : GET_CODE (operands[6]); 3986: 3987: if (GET_CODE (operands[5]) == NE) 3988: operands[5] = gen_rtx (code, CCmode, 3989: XEXP (operands[5], 0), XEXP (operands[5], 1)); 3990: else 3991: operands[5] = gen_rtx (reverse_condition (code), CCmode, 3992: XEXP (operands[5], 0), XEXP (operands[5], 1)); 3993: } 3994: ") 3995: 3996: ;; Don't match these patterns if we can use a conditional compare, since they 1.1.1.4 root 3997: ;; tell the final prescan branch eliminator code that full branch inlining 1.1.1.2 root 3998: ;; can't be done. 3999: 4000: (define_insn "" 4001: [(set (pc) 1.1.1.3 root 4002: (if_then_else 4003: (ne (ior:SI (match_operator 5 "comparison_operator" 4004: [(match_operand:SI 0 "s_register_operand" "r,r,r,r") 4005: (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")]) 4006: (match_operator 6 "comparison_operator" 4007: [(match_operand:SI 2 "s_register_operand" "r,r,r,r") 4008: (match_operand:SI 3 "arm_rhs_operand" "rI,rI,L,L")])) 4009: (const_int 0)) 4010: (label_ref (match_operand 4 "" "")) 4011: (pc))) 1.1.1.2 root 4012: (clobber (reg 24))] 4013: "!(GET_CODE (operands[5]) == GET_CODE (operands[6]) 4014: || comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[6])) 4015: || comparison_dominates_p (GET_CODE (operands[6]), GET_CODE (operands[5])))" 4016: "* 4017: { 4018: extern int arm_ccfsm_state; 4019: 1.1.1.3 root 4020: if (which_alternative & 1) 4021: output_asm_insn (\"cmn\\t%0, #%n1\;b%d5\\t%l4\", operands); 1.1.1.2 root 4022: else 1.1.1.3 root 4023: output_asm_insn (\"cmp\\t%0, %1\;b%d5\\t%l4\", operands); 4024: 4025: if (which_alternative >= 2) 4026: output_asm_insn (\"cmn\\t%2, #%n3\", operands); 1.1.1.2 root 4027: else 1.1.1.3 root 4028: output_asm_insn (\"cmp\\t%2, %3\", operands); 4029: 1.1.1.2 root 4030: if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2) 4031: { 4032: arm_ccfsm_state += 2; 4033: return \"\"; 4034: } 1.1.1.3 root 4035: return \"b%d6\\t%l4\"; 1.1.1.2 root 4036: }" 4037: [(set_attr "conds" "jump_clob") 1.1.1.3 root 4038: (set_attr "length" "16")]) 1.1.1.2 root 4039: 4040: (define_insn "" 4041: [(set (reg:CC 24) 1.1.1.3 root 4042: (compare:CC 4043: (ior:CC (match_operator 4 "comparison_operator" 4044: [(match_operand:SI 0 "s_register_operand" "r,r,r,r") 4045: (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")]) 4046: (match_operator 5 "comparison_operator" 4047: [(match_operand:SI 2 "s_register_operand" "r,r,r,r") 4048: (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")])) 4049: (const_int 0)))] 1.1.1.2 root 4050: "(GET_CODE (operands[4]) == GET_CODE (operands[5]) 4051: || comparison_dominates_p (GET_CODE (operands[4]), GET_CODE (operands[5])) 4052: || comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4])))" 4053: "* 4054: if (comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4]))) 4055: { 1.1.1.3 root 4056: if (which_alternative >= 2) 4057: output_asm_insn (\"cmn\\t%2, #%n3\", operands); 1.1.1.2 root 4058: else 1.1.1.3 root 4059: output_asm_insn (\"cmp\\t%2, %3\", operands); 4060: 4061: if (which_alternative & 1) 4062: return \"cmn%D5\\t%0, #%n1\"; 4063: return \"cmp%D5\\t%0, %1\"; 1.1.1.2 root 4064: } 1.1.1.3 root 4065: 4066: if (which_alternative & 1) 4067: output_asm_insn (\"cmn\\t%0, #%n1\", operands); 1.1.1.2 root 4068: else 1.1.1.3 root 4069: output_asm_insn (\"cmp\\t%0, %1\", operands); 4070: 4071: if (which_alternative >= 2) 4072: return \"cmn%D4\\t%2, #%n3\"; 4073: return \"cmp%D4\\t%2, %3\"; 1.1.1.2 root 4074: " 4075: [(set_attr "conds" "set") 1.1.1.3 root 4076: (set_attr "length" "8")]) 1.1.1.2 root 4077: 4078: (define_insn "" 4079: [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") 4080: (if_then_else (match_operator 3 "equality_operator" 4081: [(match_operator 4 "comparison_operator" 4082: [(reg 24) (const_int 0)]) 4083: (const_int 0)]) 4084: (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI") 4085: (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))] 4086: "" 4087: "* 4088: if (GET_CODE (operands[3]) == NE) 4089: { 4090: if (which_alternative != 1) 1.1.1.3 root 4091: output_asm_insn (\"mov%D4\\t%0, %2\", operands); 4092: if (which_alternative != 0) 4093: output_asm_insn (\"mov%d4\\t%0, %1\", operands); 1.1.1.2 root 4094: return \"\"; 4095: } 4096: if (which_alternative != 0) 1.1.1.3 root 4097: output_asm_insn (\"mov%D4\\t%0, %1\", operands); 1.1.1.2 root 4098: if (which_alternative != 1) 1.1.1.3 root 4099: output_asm_insn (\"mov%d4\\t%0, %2\", operands); 1.1.1.2 root 4100: return \"\"; 4101: " 4102: [(set_attr "conds" "use") 1.1.1.3 root 4103: (set_attr "length" "4,4,8")]) 1.1.1.2 root 4104: 4105: (define_insn "" 4106: [(set (match_operand:SI 0 "s_register_operand" "=r,r") 4107: (match_operator:SI 5 "shiftable_operator" 4108: [(match_operator:SI 4 "comparison_operator" 4109: [(match_operand:SI 2 "s_register_operand" "r,r") 4110: (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]) 4111: (match_operand:SI 1 "s_register_operand" "0,?r")])) 4112: (clobber (reg 24))] 4113: "" 4114: "* 4115: if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx) 1.1.1.3 root 4116: return \"%i5\\t%0, %1, %2, lsr #31\"; 4117: 4118: output_asm_insn (\"cmp\\t%2, %3\", operands); 1.1.1.2 root 4119: if (GET_CODE (operands[5]) == AND) 1.1.1.3 root 4120: output_asm_insn (\"mov%D4\\t%0, #0\", operands); 1.1.1.4 root 4121: else if (GET_CODE (operands[5]) == MINUS) 4122: output_asm_insn (\"rsb%D4\\t%0, %1, #0\", operands); 1.1.1.2 root 4123: else if (which_alternative != 0) 1.1.1.3 root 4124: output_asm_insn (\"mov%D4\\t%0, %1\", operands); 4125: return \"%i5%d4\\t%0, %1, #1\"; 1.1.1.2 root 4126: " 4127: [(set_attr "conds" "clob") 1.1.1.3 root 4128: (set_attr "length" "12")]) 1.1.1.2 root 4129: 4130: (define_insn "" 4131: [(set (match_operand:SI 0 "s_register_operand" "=r,r") 4132: (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r") 4133: (match_operator:SI 4 "comparison_operator" 4134: [(match_operand:SI 2 "s_register_operand" "r,r") 4135: (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]))) 4136: (clobber (reg 24))] 4137: "" 4138: "* 1.1.1.3 root 4139: output_asm_insn (\"cmp\\t%2, %3\", operands); 1.1.1.2 root 4140: if (which_alternative != 0) 1.1.1.3 root 4141: output_asm_insn (\"mov%D4\\t%0, %1\", operands); 4142: return \"sub%d4\\t%0, %1, #1\"; 1.1.1.2 root 4143: " 4144: [(set_attr "conds" "clob") 1.1.1.3 root 4145: (set_attr "length" "8,12")]) 1.1.1.2 root 4146: 4147: (define_insn "" 4148: [(set (match_operand:SI 0 "s_register_operand" "=&r") 4149: (and:SI (match_operator 1 "comparison_operator" 4150: [(match_operand:SI 2 "s_register_operand" "r") 4151: (match_operand:SI 3 "arm_rhs_operand" "rI")]) 4152: (match_operator 4 "comparison_operator" 4153: [(match_operand:SI 5 "s_register_operand" "r") 4154: (match_operand:SI 6 "arm_rhs_operand" "rI")]))) 4155: (clobber (reg 24))] 4156: "" 4157: "* 4158: { 4159: int dominant = 4160: comparison_dominates_p (reverse_condition (GET_CODE (operands[1])), 4161: reverse_condition (GET_CODE (operands[4]))) 4162: ? 1 4163: : comparison_dominates_p (reverse_condition (GET_CODE (operands[4])), 4164: reverse_condition (GET_CODE (operands[1]))) 4165: ? 2 : 0; 1.1.1.3 root 4166: output_asm_insn (dominant == 2 ? \"cmp\\t%5, %6\" : \"cmp\\t%2, %3\", 1.1.1.2 root 4167: operands); 1.1.1.3 root 4168: output_asm_insn (\"mov\\t%0, #1\", operands); 1.1.1.2 root 4169: if (GET_CODE (operands[1]) == GET_CODE (operands[4]) || dominant) 4170: { 1.1.1.3 root 4171: output_asm_insn (dominant == 2 ? \"cmp%d4\\t%2, %3\" 1.1.1.2 root 4172: : \"cmp%d1\\t%5, %6\", operands); 4173: } 4174: else 4175: { 1.1.1.3 root 4176: output_asm_insn (\"mov%D1\\t%0, #0\", operands); 4177: output_asm_insn (\"cmp\\t%5, %6\", operands); 1.1.1.2 root 4178: } 1.1.1.3 root 4179: return dominant == 2 ? \"mov%D1\\t%0, #0\" : \"mov%D4\\t%0, #0\"; 1.1.1.2 root 4180: } 4181: " 4182: [(set_attr "conds" "clob") 1.1.1.3 root 4183: (set_attr "length" "20")]) 1.1.1.2 root 4184: 4185: (define_split 4186: [(set (pc) 4187: (if_then_else (match_operator 1 "equality_operator" 4188: [(and:SI (match_operator 2 "comparison_operator" 1.1.1.3 root 4189: [(match_operand:SI 3 "s_register_operand" "") 4190: (match_operand:SI 4 "arm_add_operand" "")]) 1.1.1.2 root 4191: (match_operator 0 "comparison_operator" 1.1.1.3 root 4192: [(match_operand:SI 5 "s_register_operand" "") 4193: (match_operand:SI 6 "arm_add_operand" "")])) 1.1.1.2 root 4194: (const_int 0)]) 4195: (label_ref (match_operand 7 "" "")) 4196: (pc))) 4197: (clobber (reg 24))] 4198: "(GET_CODE (operands[2]) == GET_CODE (operands[0]) 4199: || comparison_dominates_p (reverse_condition (GET_CODE (operands[2])), 4200: reverse_condition (GET_CODE (operands[0]))) 4201: || comparison_dominates_p (reverse_condition (GET_CODE (operands[0])), 4202: reverse_condition (GET_CODE (operands[2]))))" 4203: [(set (reg:CC 24) 4204: (compare:CC (ior:CC (match_op_dup 2 4205: [(match_dup 3) (match_dup 4)]) 4206: (match_op_dup 0 4207: [(match_dup 5) (match_dup 6)])) 4208: (const_int 0))) 4209: (set (pc) 4210: (if_then_else (match_op_dup 1 [(reg:CC 24) (const_int 0)]) 4211: (label_ref (match_dup 7)) 4212: (pc)))] 4213: " 4214: { 4215: /* Use DeMorgans law to convert this into an IOR of the inverse conditions 4216: This is safe since we only do it for integer comparisons. */ 4217: enum rtx_code code = 4218: comparison_dominates_p (reverse_condition (GET_CODE (operands[2])), 4219: reverse_condition (GET_CODE (operands[0]))) 4220: ? GET_CODE (operands[0]) : GET_CODE (operands[2]); 4221: 4222: operands[2] = gen_rtx (reverse_condition (GET_CODE (operands[2])), 4223: GET_MODE (operands[2]), operands[3], operands[4]); 4224: operands[0] = gen_rtx (reverse_condition (GET_CODE (operands[0])), 4225: GET_MODE (operands[0]), operands[5], operands[6]); 4226: if (GET_CODE (operands[1]) == NE) 4227: operands[1] = gen_rtx (code, CCmode, 4228: XEXP (operands[1], 0), XEXP (operands[1], 1)); 4229: else 4230: operands[1] = gen_rtx (reverse_condition (code), CCmode, 4231: XEXP (operands[1], 0), XEXP (operands[1], 1)); 4232: } 4233: ") 4234: 4235: ;; Don't match these patterns if we can use a conditional compare, since they 1.1.1.4 root 4236: ;; tell the final prescan branch eliminator code that full branch inlining 1.1.1.2 root 4237: ;; can't be done. 4238: 4239: (define_insn "" 4240: [(set (pc) 1.1.1.3 root 4241: (if_then_else 4242: (eq (and:SI (match_operator 1 "comparison_operator" 4243: [(match_operand:SI 2 "s_register_operand" "r,r,r,r") 4244: (match_operand:SI 3 "arm_add_operand" "rI,L,rI,L")]) 4245: (match_operator 4 "comparison_operator" 4246: [(match_operand:SI 5 "s_register_operand" "r,r,r,r") 4247: (match_operand:SI 6 "arm_rhs_operand" "rI,rI,L,L")])) 4248: (const_int 0)) 4249: (label_ref (match_operand 0 "" "")) 4250: (pc))) 1.1.1.2 root 4251: (clobber (reg 24))] 4252: "!(GET_CODE (operands[1]) == GET_CODE (operands[4]) 4253: || comparison_dominates_p (reverse_condition (GET_CODE (operands[1])), 4254: reverse_condition (GET_CODE (operands[4]))) 4255: || comparison_dominates_p (reverse_condition (GET_CODE (operands[4])), 4256: reverse_condition (GET_CODE (operands[1]))))" 4257: "* 4258: { 4259: extern int arm_ccfsm_state; 4260: 1.1.1.3 root 4261: if (which_alternative & 1) 4262: output_asm_insn (\"cmn\\t%2, #%n3\;b%D1\\t%l0\", operands); 1.1.1.2 root 4263: else 1.1.1.3 root 4264: output_asm_insn (\"cmp\\t%2, %3\;b%D1\\t%l0\", operands); 4265: 4266: if (which_alternative >= 2) 4267: output_asm_insn (\"cmn\\t%5, #%n6\", operands); 1.1.1.2 root 4268: else 1.1.1.3 root 4269: output_asm_insn (\"cmp\\t%5, %6\", operands); 4270: 1.1.1.2 root 4271: if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2) 4272: { 4273: arm_ccfsm_state += 2; 4274: return \"\"; 4275: } 1.1.1.3 root 4276: return \"b%D4\\t%l0\"; 1.1.1.2 root 4277: }" 4278: [(set_attr "conds" "jump_clob") 1.1.1.3 root 4279: (set_attr "length" "16")]) 1.1.1.2 root 4280: 4281: (define_insn "" 4282: [(set (match_operand:SI 0 "s_register_operand" "=r") 4283: (neg:SI (match_operator 3 "comparison_operator" 4284: [(match_operand:SI 1 "s_register_operand" "r") 4285: (match_operand:SI 2 "arm_rhs_operand" "rI")]))) 4286: (clobber (reg 24))] 4287: "" 4288: "* 4289: if (GET_CODE (operands[3]) == LT && operands[3] == const0_rtx) 1.1.1.3 root 4290: return \"mov\\t%0, %1, asr #31\"; 4291: 1.1.1.2 root 4292: if (GET_CODE (operands[3]) == NE) 1.1.1.3 root 4293: return \"subs\\t%0, %1, %2\;mvnne\\t%0, #0\"; 4294: 1.1.1.2 root 4295: if (GET_CODE (operands[3]) == GT) 1.1.1.3 root 4296: return \"subs\\t%0, %1, %2\;mvnne\\t%0, %0, asr #31\"; 4297: 4298: output_asm_insn (\"cmp\\t%1, %2\", operands); 4299: output_asm_insn (\"mov%D3\\t%0, #0\", operands); 4300: return \"mvn%d3\\t%0, #0\"; 1.1.1.2 root 4301: " 4302: [(set_attr "conds" "clob") 1.1.1.3 root 4303: (set_attr "length" "12")]) 1.1.1.2 root 4304: 4305: (define_insn "movcond" 4306: [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") 1.1.1.3 root 4307: (if_then_else:SI 4308: (match_operator 5 "comparison_operator" 4309: [(match_operand:SI 3 "s_register_operand" "r,r,r") 4310: (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")]) 4311: (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI") 4312: (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) 1.1.1.2 root 4313: (clobber (reg 24))] 4314: "" 4315: "* 4316: if (GET_CODE (operands[5]) == LT 4317: && (operands[4] == const0_rtx)) 4318: { 1.1.1.3 root 4319: if (which_alternative != 1 && GET_CODE (operands[1]) == REG) 1.1.1.2 root 4320: { 4321: if (operands[2] == const0_rtx) 1.1.1.3 root 4322: return \"and\\t%0, %1, %3, asr #31\"; 4323: return \"ands\\t%0, %1, %3, asr #32\;movcc\\t%0, %2\"; 1.1.1.2 root 4324: } 4325: else if (which_alternative != 0 && GET_CODE (operands[2]) == REG) 4326: { 4327: if (operands[1] == const0_rtx) 1.1.1.3 root 4328: return \"bic\\t%0, %2, %3, asr #31\"; 4329: return \"bics\\t%0, %2, %3, asr #32\;movcs\\t%0, %1\"; 1.1.1.2 root 4330: } 4331: /* The only case that falls through to here is when both ops 1 & 2 4332: are constants */ 4333: } 1.1.1.3 root 4334: 1.1.1.2 root 4335: if (GET_CODE (operands[5]) == GE 4336: && (operands[4] == const0_rtx)) 4337: { 4338: if (which_alternative != 1 && GET_CODE (operands[1]) == REG) 4339: { 4340: if (operands[2] == const0_rtx) 1.1.1.3 root 4341: return \"bic\\t%0, %1, %3, asr #31\"; 4342: return \"bics\\t%0, %1, %3, asr #32\;movcs\\t%0, %2\"; 1.1.1.2 root 4343: } 4344: else if (which_alternative != 0 && GET_CODE (operands[2]) == REG) 4345: { 4346: if (operands[1] == const0_rtx) 1.1.1.3 root 4347: return \"and\\t%0, %2, %3, asr #31\"; 4348: return \"ands\\t%0, %2, %3, asr #32\;movcc\\t%0, %1\"; 1.1.1.2 root 4349: } 4350: /* The only case that falls through to here is when both ops 1 & 2 4351: are constants */ 4352: } 4353: if (GET_CODE (operands[4]) == CONST_INT 4354: && !const_ok_for_arm (INTVAL (operands[4]))) 1.1.1.3 root 4355: output_asm_insn (\"cmn\\t%3, #%n4\", operands); 1.1.1.2 root 4356: else 1.1.1.3 root 4357: output_asm_insn (\"cmp\\t%3, %4\", operands); 1.1.1.2 root 4358: if (which_alternative != 0) 1.1.1.3 root 4359: output_asm_insn (\"mov%d5\\t%0, %1\", operands); 1.1.1.2 root 4360: if (which_alternative != 1) 1.1.1.3 root 4361: output_asm_insn (\"mov%D5\\t%0, %2\", operands); 1.1.1.2 root 4362: return \"\"; 4363: " 4364: [(set_attr "conds" "clob") 1.1.1.3 root 4365: (set_attr "length" "8,8,12")]) 1.1.1.2 root 4366: 4367: (define_insn "" 1.1.1.3 root 4368: [(set (match_operand:SI 0 "s_register_operand" "=r,r") 1.1.1.2 root 4369: (if_then_else:SI (match_operator 9 "comparison_operator" 1.1.1.3 root 4370: [(match_operand:SI 5 "s_register_operand" "r,r") 4371: (match_operand:SI 6 "arm_add_operand" "rI,L")]) 1.1.1.2 root 4372: (match_operator:SI 8 "shiftable_operator" 1.1.1.3 root 4373: [(match_operand:SI 1 "s_register_operand" "r,r") 4374: (match_operand:SI 2 "arm_rhs_operand" "rI,rI")]) 1.1.1.2 root 4375: (match_operator:SI 7 "shiftable_operator" 1.1.1.3 root 4376: [(match_operand:SI 3 "s_register_operand" "r,r") 4377: (match_operand:SI 4 "arm_rhs_operand" "rI,rI")]))) 1.1.1.2 root 4378: (clobber (reg 24))] 4379: "" 1.1.1.3 root 4380: "@ 4381: cmp\\t%5, %6\;%I8%d9\\t%0, %1, %2\;%I7%D9\\t%0, %3, %4 4382: cmn\\t%5, #%n6\;%I8%d9\\t%0, %1, %2\;%I7%D9\\t%0, %3, %4" 1.1.1.2 root 4383: [(set_attr "conds" "clob") 1.1.1.3 root 4384: (set_attr "length" "12")]) 1.1.1.2 root 4385: 4386: (define_insn "" 4387: [(set (match_operand:SI 0 "s_register_operand" "=r,r") 4388: (if_then_else:SI (match_operator 6 "comparison_operator" 4389: [(match_operand:SI 2 "s_register_operand" "r,r") 1.1.1.3 root 4390: (match_operand:SI 3 "arm_add_operand" "rIL,rIL")]) 1.1.1.2 root 4391: (match_operator:SI 7 "shiftable_operator" 4392: [(match_operand:SI 4 "s_register_operand" "r,r") 4393: (match_operand:SI 5 "arm_rhs_operand" "rI,rI")]) 4394: (match_operand:SI 1 "arm_rhsm_operand" "0,?rIm"))) 4395: (clobber (reg 24))] 4396: "" 4397: "* 4398: /* If we have an operation where (op x 0) is the identity operation and 1.1.1.4 root 4399: the conditional operator is LT or GE and we are comparing against zero and 1.1.1.2 root 4400: everything is in registers then we can do this in two instructions */ 4401: if (operands[3] == const0_rtx 4402: && GET_CODE (operands[7]) != AND 4403: && GET_CODE (operands[5]) == REG 4404: && GET_CODE (operands[1]) == REG 4405: && REGNO (operands[1]) == REGNO (operands[4]) 4406: && REGNO (operands[4]) != REGNO (operands[0])) 4407: { 4408: if (GET_CODE (operands[6]) == LT) 1.1.1.3 root 4409: return \"and\\t%0, %5, %2, asr #31\;%I7\\t%0, %4, %0\"; 1.1.1.2 root 4410: else if (GET_CODE (operands[6]) == GE) 1.1.1.3 root 4411: return \"bic\\t%0, %5, %2, asr #31\;%I7\\t%0, %4, %0\"; 1.1.1.2 root 4412: } 4413: if (GET_CODE (operands[3]) == CONST_INT 4414: && !const_ok_for_arm (INTVAL (operands[3]))) 1.1.1.3 root 4415: output_asm_insn (\"cmn\\t%2, #%n3\", operands); 1.1.1.2 root 4416: else 1.1.1.3 root 4417: output_asm_insn (\"cmp\\t%2, %3\", operands); 4418: output_asm_insn (\"%I7%d6\\t%0, %4, %5\", operands); 1.1.1.2 root 4419: if (which_alternative != 0) 4420: { 4421: if (GET_CODE (operands[1]) == MEM) 1.1.1.3 root 4422: return \"ldr%D6\\t%0, %1\"; 1.1.1.2 root 4423: else 1.1.1.3 root 4424: return \"mov%D6\\t%0, %1\"; 1.1.1.2 root 4425: } 4426: return \"\"; 4427: " 4428: [(set_attr "conds" "clob") 1.1.1.3 root 4429: (set_attr "length" "8,12")]) 1.1.1.2 root 4430: 4431: (define_insn "" 4432: [(set (match_operand:SI 0 "s_register_operand" "=r,r") 4433: (if_then_else:SI (match_operator 6 "comparison_operator" 4434: [(match_operand:SI 4 "s_register_operand" "r,r") 1.1.1.3 root 4435: (match_operand:SI 5 "arm_add_operand" "rIL,rIL")]) 1.1.1.2 root 4436: (match_operand:SI 1 "arm_rhsm_operand" "0,?rIm") 4437: (match_operator:SI 7 "shiftable_operator" 4438: [(match_operand:SI 2 "s_register_operand" "r,r") 4439: (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]))) 4440: (clobber (reg 24))] 4441: "" 4442: "* 4443: /* If we have an operation where (op x 0) is the identity operation and 1.1.1.4 root 4444: the conditional operator is LT or GE and we are comparing against zero and 1.1.1.2 root 4445: everything is in registers then we can do this in two instructions */ 4446: if (operands[5] == const0_rtx 4447: && GET_CODE (operands[7]) != AND 4448: && GET_CODE (operands[3]) == REG 4449: && GET_CODE (operands[1]) == REG 4450: && REGNO (operands[1]) == REGNO (operands[2]) 4451: && REGNO (operands[2]) != REGNO (operands[0])) 4452: { 4453: if (GET_CODE (operands[6]) == GE) 1.1.1.3 root 4454: return \"and\\t%0, %3, %4, asr #31\;%I7\\t%0, %2, %0\"; 1.1.1.2 root 4455: else if (GET_CODE (operands[6]) == LT) 1.1.1.3 root 4456: return \"bic\\t%0, %3, %4, asr #31\;%I7\\t%0, %2, %0\"; 1.1.1.2 root 4457: } 1.1.1.3 root 4458: 1.1.1.2 root 4459: if (GET_CODE (operands[5]) == CONST_INT 4460: && !const_ok_for_arm (INTVAL (operands[5]))) 1.1.1.3 root 4461: output_asm_insn (\"cmn\\t%4, #%n5\", operands); 1.1.1.2 root 4462: else 1.1.1.3 root 4463: output_asm_insn (\"cmp\\t%4, %5\", operands); 4464: 1.1.1.2 root 4465: if (which_alternative != 0) 4466: { 4467: if (GET_CODE (operands[1]) == MEM) 1.1.1.3 root 4468: output_asm_insn (\"ldr%d6\\t%0, %1\", operands); 1.1.1.2 root 4469: else 1.1.1.3 root 4470: output_asm_insn (\"mov%d6\\t%0, %1\", operands); 1.1.1.2 root 4471: } 1.1.1.3 root 4472: return \"%I7%D6\\t%0, %2, %3\"; 1.1.1.2 root 4473: " 4474: [(set_attr "conds" "clob") 1.1.1.3 root 4475: (set_attr "length" "8,12")]) 1.1.1.2 root 4476: 4477: (define_insn "" 4478: [(set (match_operand:SI 0 "s_register_operand" "=r,r") 4479: (if_then_else:SI (match_operator 6 "comparison_operator" 4480: [(match_operand:SI 4 "s_register_operand" "r,r") 1.1.1.3 root 4481: (match_operand:SI 5 "arm_add_operand" "rIL,rIL")]) 1.1.1.2 root 4482: (plus:SI 4483: (match_operand:SI 2 "s_register_operand" "r,r") 4484: (match_operand:SI 3 "arm_add_operand" "rL,rL")) 4485: (match_operand:SI 1 "arm_rhsm_operand" "0,?rIm"))) 4486: (clobber (reg 24))] 4487: "" 4488: "* 4489: { 4490: if (GET_CODE (operands[5]) == CONST_INT 4491: && !const_ok_for_arm (INTVAL (operands[5]))) 1.1.1.3 root 4492: output_asm_insn (\"cmn\\t%4, #%n5\", operands); 1.1.1.2 root 4493: else 1.1.1.3 root 4494: output_asm_insn (\"cmp\\t%4, %5\", operands); 1.1.1.2 root 4495: if (GET_CODE (operands[3]) == CONST_INT 4496: && !const_ok_for_arm (INTVAL (operands[3]))) 1.1.1.3 root 4497: output_asm_insn (\"sub%d6\\t%0, %2, #%n3\", operands); 1.1.1.2 root 4498: else 1.1.1.3 root 4499: output_asm_insn (\"add%d6\\t%0, %2, %3\", operands); 1.1.1.2 root 4500: if (which_alternative != 0) 4501: { 4502: if (GET_CODE (operands[1]) == MEM) 1.1.1.3 root 4503: output_asm_insn (\"ldr%D6\\t%0, %1\", operands); 1.1.1.2 root 4504: else 1.1.1.3 root 4505: output_asm_insn (\"mov%D6\\t%0, %1\", operands); 1.1.1.2 root 4506: } 4507: return \"\"; 4508: } 4509: " 4510: [(set_attr "conds" "clob") 1.1.1.3 root 4511: (set_attr "length" "8,12")]) 1.1.1.2 root 4512: 4513: (define_insn "" 4514: [(set (match_operand:SI 0 "s_register_operand" "=r,r") 4515: (if_then_else:SI (match_operator 6 "comparison_operator" 4516: [(match_operand:SI 4 "s_register_operand" "r,r") 1.1.1.3 root 4517: (match_operand:SI 5 "arm_add_operand" "rIL,rIL")]) 1.1.1.2 root 4518: (match_operand:SI 1 "arm_rhsm_operand" "0,?rIm") 4519: (plus:SI 4520: (match_operand:SI 2 "s_register_operand" "r,r") 1.1.1.3 root 4521: (match_operand:SI 3 "arm_add_operand" "rIL,rIL")))) 1.1.1.2 root 4522: (clobber (reg 24))] 4523: "" 4524: "* 4525: { 4526: if (GET_CODE (operands[5]) == CONST_INT 4527: && !const_ok_for_arm (INTVAL (operands[5]))) 1.1.1.3 root 4528: output_asm_insn (\"cmn\\t%4, #%n5\", operands); 1.1.1.2 root 4529: else 1.1.1.3 root 4530: output_asm_insn (\"cmp\\t%4, %5\", operands); 1.1.1.2 root 4531: if (GET_CODE (operands[3]) == CONST_INT 4532: && !const_ok_for_arm (INTVAL (operands[3]))) 1.1.1.3 root 4533: output_asm_insn (\"sub%D6\\t%0, %2, #%n3\", operands); 1.1.1.2 root 4534: else 1.1.1.3 root 4535: output_asm_insn (\"add%D6\\t%0, %2, %3\", operands); 1.1.1.2 root 4536: if (which_alternative != 0) 4537: { 4538: if (GET_CODE (operands[6]) == MEM) 1.1.1.3 root 4539: output_asm_insn (\"ldr%d6\\t%0, %1\", operands); 1.1.1.2 root 4540: else 1.1.1.3 root 4541: output_asm_insn (\"mov%d6\\t%0, %1\", operands); 1.1.1.2 root 4542: } 4543: return \"\"; 4544: } 4545: " 4546: [(set_attr "conds" "clob") 1.1.1.3 root 4547: (set_attr "length" "8,12")]) 1.1.1.2 root 4548: 4549: (define_insn "" 4550: [(set (match_operand:SI 0 "s_register_operand" "=r,r") 4551: (if_then_else:SI (match_operator 5 "comparison_operator" 4552: [(match_operand:SI 3 "s_register_operand" "r,r") 1.1.1.3 root 4553: (match_operand:SI 4 "arm_add_operand" "rIL,rIL")]) 1.1.1.2 root 4554: (match_operand:SI 1 "arm_rhs_operand" "0,?rI") 4555: (not:SI 4556: (match_operand:SI 2 "s_register_operand" "r,r")))) 4557: (clobber (reg 24))] 4558: "" 4559: "#" 4560: [(set_attr "conds" "clob") 1.1.1.3 root 4561: (set_attr "length" "8,12")]) 1.1.1.2 root 4562: 4563: (define_insn "" 1.1.1.3 root 4564: [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r") 4565: (if_then_else:SI 4566: (match_operator 5 "comparison_operator" 4567: [(match_operand:SI 3 "s_register_operand" "r,r,r,r") 4568: (match_operand:SI 4 "arm_add_operand" "rI,L,rI,L")]) 4569: (not:SI 4570: (match_operand:SI 2 "s_register_operand" "r,r,r,r")) 4571: (match_operand:SI 1 "arm_rhs_operand" "0,0,?rI,?rI"))) 1.1.1.2 root 4572: (clobber (reg 24))] 4573: "" 1.1.1.3 root 4574: "@ 4575: cmp\\t%3, %4\;mvn%d5\\t%0, %2 4576: cmn\\t%3, #%n4\;mvn%d5\\t%0, %2 4577: cmp\\t%3, %4\;mov%D5\\t%0, %1\;mvn%d5\\t%0, %2 4578: cmn\\t%3, #%n4\;mov%D5\\t%0, %1\;mvn%d5\\t%0, %2" 1.1.1.2 root 4579: [(set_attr "conds" "clob") 1.1.1.3 root 4580: (set_attr "length" "8,8,12,12")]) 1.1.1.2 root 4581: 4582: (define_insn "" 1.1.1.3 root 4583: [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r") 4584: (if_then_else:SI 4585: (match_operator 6 "comparison_operator" 4586: [(match_operand:SI 4 "s_register_operand" "r,r,r,r") 4587: (match_operand:SI 5 "arm_add_operand" "rI,L,rI,L")]) 4588: (match_operator:SI 7 "shift_operator" 4589: [(match_operand:SI 2 "s_register_operand" "r,r,r,r") 4590: (match_operand:SI 3 "arm_rhs_operand" "rM,rM,rM,rM")]) 4591: (match_operand:SI 1 "arm_rhs_operand" "0,0,?rI,?rI"))) 1.1.1.2 root 4592: (clobber (reg 24))] 4593: "" 1.1.1.3 root 4594: "@ 4595: cmp\\t%4, %5\;mov%d6\\t%0, %2%S7 4596: cmn\\t%4, #%n5\;mov%d6\\t%0, %2%S7 4597: cmp\\t%4, %5\;mov%D6\\t%0, %1\;mov%d6\\t%0, %2%S7 4598: cmn\\t%4, #%n5\;mov%D6\\t%0, %1\;mov%d6\\t%0, %2%S7" 1.1.1.2 root 4599: [(set_attr "conds" "clob") 1.1.1.3 root 4600: (set_attr "length" "8,8,12,12")]) 1.1.1.2 root 4601: 4602: (define_insn "" 1.1.1.3 root 4603: [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r") 4604: (if_then_else:SI 4605: (match_operator 6 "comparison_operator" 4606: [(match_operand:SI 4 "s_register_operand" "r,r,r,r") 4607: (match_operand:SI 5 "arm_add_operand" "rI,L,rI,L")]) 4608: (match_operand:SI 1 "arm_rhs_operand" "0,0,?rI,?rI") 4609: (match_operator:SI 7 "shift_operator" 4610: [(match_operand:SI 2 "s_register_operand" "r,r,r,r") 4611: (match_operand:SI 3 "arm_rhs_operand" "rM,rM,rM,rM")]))) 1.1.1.2 root 4612: (clobber (reg 24))] 4613: "" 1.1.1.3 root 4614: "@ 4615: cmp\\t%4, %5\;mov%D6\\t%0, %2%S7 4616: cmn\\t%4, #%n5\;mov%D6\\t%0, %2%S7 4617: cmp\\t%4, %5\;mov%d6\\t%0, %1\;mov%D6\\t%0, %2%S7 4618: cmn\\t%4, #%n5\;mov%d6\\t%0, %1\;mov%D6\\t%0, %2%S7" 1.1.1.2 root 4619: [(set_attr "conds" "clob") 1.1.1.3 root 4620: (set_attr "length" "8,8,12,12")]) 1.1.1.2 root 4621: 4622: (define_insn "" 1.1.1.3 root 4623: [(set (match_operand:SI 0 "s_register_operand" "=r,r") 4624: (if_then_else:SI 4625: (match_operator 7 "comparison_operator" 4626: [(match_operand:SI 5 "s_register_operand" "r,r") 4627: (match_operand:SI 6 "arm_add_operand" "rI,L")]) 4628: (match_operator:SI 8 "shift_operator" 4629: [(match_operand:SI 1 "s_register_operand" "r,r") 4630: (match_operand:SI 2 "arm_rhs_operand" "rM,rM")]) 4631: (match_operator:SI 9 "shift_operator" 4632: [(match_operand:SI 3 "s_register_operand" "r,r") 4633: (match_operand:SI 4 "arm_rhs_operand" "rI,rI")]))) 1.1.1.2 root 4634: (clobber (reg 24))] 4635: "" 1.1.1.3 root 4636: "@ 4637: cmp\\t%5, %6\;mov%d7\\t%0, %1%S8\;mov%D7\\t%0, %3%S9 4638: cmn\\t%5, #%n6\;mov%d7\\t%0, %1%S8\;mov%D7\\t%0, %3%S9" 1.1.1.2 root 4639: [(set_attr "conds" "clob") 1.1.1.3 root 4640: (set_attr "length" "12")]) 1.1.1.2 root 4641: 4642: (define_insn "" 1.1.1.3 root 4643: [(set (match_operand:SI 0 "s_register_operand" "=r,r") 4644: (if_then_else:SI 4645: (match_operator 6 "comparison_operator" 4646: [(match_operand:SI 4 "s_register_operand" "r,r") 4647: (match_operand:SI 5 "arm_add_operand" "rI,L")]) 4648: (not:SI (match_operand:SI 1 "s_register_operand" "r,r")) 4649: (match_operator:SI 7 "shiftable_operator" 4650: [(match_operand:SI 2 "s_register_operand" "r,r") 4651: (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]))) 1.1.1.2 root 4652: (clobber (reg 24))] 4653: "" 1.1.1.3 root 4654: "@ 4655: cmp\\t%4, %5\;mvn%d6\\t%0, %1\;%I7%D6\\t%0, %2, %3 4656: cmn\\t%4, #%n5\;mvn%d6\\t%0, %1\;%I7%D6\\t%0, %2, %3" 1.1.1.2 root 4657: [(set_attr "conds" "clob") 1.1.1.3 root 4658: (set_attr "length" "12")]) 1.1.1.2 root 4659: 4660: (define_insn "" 1.1.1.3 root 4661: [(set (match_operand:SI 0 "s_register_operand" "=r,r") 4662: (if_then_else:SI 4663: (match_operator 6 "comparison_operator" 4664: [(match_operand:SI 4 "s_register_operand" "r,r") 4665: (match_operand:SI 5 "arm_add_operand" "rI,L")]) 4666: (match_operator:SI 7 "shiftable_operator" 4667: [(match_operand:SI 2 "s_register_operand" "r,r") 4668: (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]) 4669: (not:SI (match_operand:SI 1 "s_register_operand" "r,r")))) 1.1.1.2 root 4670: (clobber (reg 24))] 4671: "" 1.1.1.3 root 4672: "@ 4673: cmp\\t%4, %5\;mvn%D6\\t%0, %1\;%I7%d6\\t%0, %2, %3 4674: cmn\\t%4, #%n5\;mvn%D6\\t%0, %1\;%I7%d6\\t%0, %2, %3" 1.1.1.2 root 4675: [(set_attr "conds" "clob") 1.1.1.3 root 4676: (set_attr "length" "12")]) 1.1.1.2 root 4677: 4678: (define_insn "" 1.1.1.3 root 4679: [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r") 4680: (if_then_else:SI 4681: (match_operator 5 "comparison_operator" 4682: [(match_operand:SI 3 "s_register_operand" "r,r,r,r") 4683: (match_operand:SI 4 "arm_add_operand" "rI,L,rI,L")]) 4684: (neg:SI (match_operand:SI 2 "s_register_operand" "r,r,r,r")) 4685: (match_operand:SI 1 "arm_rhs_operand" "0,0,?rI,?rI"))) 1.1.1.2 root 4686: (clobber (reg:CC 24))] 4687: "" 1.1.1.3 root 4688: "@ 4689: cmp\\t%3, %4\;rsb%d5\\t%0, %2, #0 4690: cmn\\t%3, #%n4\;rsb%d5\\t%0, %2, #0 4691: cmp\\t%3, %4\;mov%D5\\t%0, %1\;rsb%d5\\t%0, %2, #0 4692: cmn\\t%3, #%n4\;mov%D5\\t%0, %1\;rsb%d5\\t%0, %2, #0" 1.1.1.2 root 4693: [(set_attr "conds" "clob") 1.1.1.3 root 4694: (set_attr "length" "8,8,12,12")]) 1.1.1.2 root 4695: 4696: (define_insn "" 1.1.1.3 root 4697: [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r") 4698: (if_then_else:SI 4699: (match_operator 5 "comparison_operator" 4700: [(match_operand:SI 3 "s_register_operand" "r,r,r,r") 4701: (match_operand:SI 4 "arm_add_operand" "rI,L,rI,L")]) 4702: (match_operand:SI 1 "arm_rhs_operand" "0,0,?rI,?rI") 4703: (neg:SI (match_operand:SI 2 "s_register_operand" "r,r,r,r")))) 1.1.1.2 root 4704: (clobber (reg:CC 24))] 4705: "" 1.1.1.3 root 4706: "@ 4707: cmp\\t%3, %4\;rsb%D5\\t%0, %2, #0 4708: cmn\\t%3, #%n4\;rsb%D5\\t%0, %2, #0 4709: cmp\\t%3, %4\;mov%d5\\t%0, %1\;rsb%D5\\t%0, %2, #0 4710: cmn\\t%3, #%n4\;mov%d5\\t%0, %1\;rsb%D5\\t%0, %2, #0" 1.1.1.2 root 4711: [(set_attr "conds" "clob") 1.1.1.3 root 4712: (set_attr "length" "8,8,12,12")]) 1.1.1.2 root 4713: 4714: (define_insn "" 4715: [(set (match_operand:SI 0 "s_register_operand" "=r") 4716: (match_operator:SI 1 "shiftable_operator" 4717: [(match_operand:SI 2 "memory_operand" "m") 4718: (match_operand:SI 3 "memory_operand" "m")])) 4719: (clobber (match_scratch:SI 4 "=r"))] 4720: "adjacent_mem_locations (operands[2], operands[3])" 4721: "* 4722: { 4723: rtx ldm[3]; 1.1.1.3 root 4724: rtx arith[4]; 1.1.1.2 root 4725: int val1 = 0, val2 = 0; 4726: 4727: if (REGNO (operands[0]) > REGNO (operands[4])) 4728: { 4729: ldm[1] = operands[4]; 4730: ldm[2] = operands[0]; 4731: } 4732: else 4733: { 4734: ldm[1] = operands[0]; 4735: ldm[2] = operands[4]; 4736: } 4737: if (GET_CODE (XEXP (operands[2], 0)) != REG) 4738: val1 = INTVAL (XEXP (XEXP (operands[2], 0), 1)); 4739: if (GET_CODE (XEXP (operands[3], 0)) != REG) 4740: val2 = INTVAL (XEXP (XEXP (operands[3], 0), 1)); 4741: arith[0] = operands[0]; 1.1.1.3 root 4742: arith[3] = operands[1]; 1.1.1.2 root 4743: if (val1 < val2) 4744: { 4745: arith[1] = ldm[1]; 4746: arith[2] = ldm[2]; 4747: } 4748: else 4749: { 4750: arith[1] = ldm[2]; 4751: arith[2] = ldm[1]; 4752: } 4753: if (val1 && val2) 4754: { 4755: rtx ops[3]; 4756: ldm[0] = ops[0] = operands[4]; 4757: ops[1] = XEXP (XEXP (operands[2], 0), 0); 4758: ops[2] = XEXP (XEXP (operands[2], 0), 1); 4759: output_add_immediate (ops); 4760: if (val1 < val2) 1.1.1.3 root 4761: output_asm_insn (\"ldm%?ia\\t%0, {%1, %2}\", ldm); 1.1.1.2 root 4762: else 1.1.1.3 root 4763: output_asm_insn (\"ldm%?da\\t%0, {%1, %2}\", ldm); 1.1.1.2 root 4764: } 4765: else if (val1) 4766: { 4767: ldm[0] = XEXP (operands[3], 0); 4768: if (val1 < val2) 1.1.1.3 root 4769: output_asm_insn (\"ldm%?da\\t%0, {%1, %2}\", ldm); 1.1.1.2 root 4770: else 1.1.1.3 root 4771: output_asm_insn (\"ldm%?ia\\t%0, {%1, %2}\", ldm); 1.1.1.2 root 4772: } 4773: else 4774: { 4775: ldm[0] = XEXP (operands[2], 0); 4776: if (val1 < val2) 1.1.1.3 root 4777: output_asm_insn (\"ldm%?ia\\t%0, {%1, %2}\", ldm); 1.1.1.2 root 4778: else 1.1.1.3 root 4779: output_asm_insn (\"ldm%?da\\t%0, {%1, %2}\", ldm); 1.1.1.2 root 4780: } 1.1.1.3 root 4781: output_asm_insn (\"%I3%?\\t%0, %1, %2\", arith); 4782: return \"\"; 1.1.1.2 root 4783: } 4784: " 1.1.1.3 root 4785: [(set_attr "length" "12") 1.1.1.2 root 4786: (set_attr "type" "load")]) 4787: 4788: ;; the arm can support extended pre-inc instructions 4789: 4790: ;; In all these cases, we use operands 0 and 1 for the register being 4791: ;; incremented because those are the operands that local-alloc will 4792: ;; tie and these are the pair most likely to be tieable (and the ones 4793: ;; that will benefit the most). 4794: 4795: ;; We reject the frame pointer if it occurs anywhere in these patterns since 4796: ;; elimination will cause too many headaches. 4797: 4798: (define_insn "" 4799: [(set (mem:QI (plus:SI (match_operand:SI 1 "s_register_operand" "%0") 4800: (match_operand:SI 2 "index_operand" "rJ"))) 4801: (match_operand:QI 3 "s_register_operand" "r")) 4802: (set (match_operand:SI 0 "s_register_operand" "=r") 4803: (plus:SI (match_dup 1) (match_dup 2)))] 4804: "REGNO (operands[0]) != FRAME_POINTER_REGNUM 4805: && REGNO (operands[1]) != FRAME_POINTER_REGNUM 4806: && (GET_CODE (operands[2]) != REG 4807: || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" 1.1.1.3 root 4808: "str%?b\\t%3, [%0, %2]!" 1.1.1.2 root 4809: [(set_attr "type" "store1")]) 4810: 4811: (define_insn "" 4812: [(set (mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0") 4813: (match_operand:SI 2 "s_register_operand" "r"))) 4814: (match_operand:QI 3 "s_register_operand" "r")) 4815: (set (match_operand:SI 0 "s_register_operand" "=r") 4816: (minus:SI (match_dup 1) (match_dup 2)))] 4817: "REGNO (operands[0]) != FRAME_POINTER_REGNUM 4818: && REGNO (operands[1]) != FRAME_POINTER_REGNUM 4819: && (GET_CODE (operands[2]) != REG 4820: || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" 1.1.1.3 root 4821: "str%?b\\t%3, [%0, -%2]!" 1.1.1.2 root 4822: [(set_attr "type" "store1")]) 4823: 4824: (define_insn "" 4825: [(set (match_operand:QI 3 "s_register_operand" "=r") 4826: (mem:QI (plus:SI (match_operand:SI 1 "s_register_operand" "%0") 4827: (match_operand:SI 2 "index_operand" "rJ")))) 4828: (set (match_operand:SI 0 "s_register_operand" "=r") 4829: (plus:SI (match_dup 1) (match_dup 2)))] 4830: "REGNO (operands[0]) != FRAME_POINTER_REGNUM 4831: && REGNO (operands[1]) != FRAME_POINTER_REGNUM 4832: && (GET_CODE (operands[2]) != REG 4833: || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" 1.1.1.3 root 4834: "ldr%?b\\t%3, [%0, %2]!" 1.1.1.2 root 4835: [(set_attr "type" "load")]) 4836: 4837: (define_insn "" 4838: [(set (match_operand:QI 3 "s_register_operand" "=r") 4839: (mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0") 4840: (match_operand:SI 2 "s_register_operand" "r")))) 4841: (set (match_operand:SI 0 "s_register_operand" "=r") 4842: (minus:SI (match_dup 1) (match_dup 2)))] 4843: "REGNO (operands[0]) != FRAME_POINTER_REGNUM 4844: && REGNO (operands[1]) != FRAME_POINTER_REGNUM 4845: && (GET_CODE (operands[2]) != REG 4846: || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" 1.1.1.3 root 4847: "ldr%?b\\t%3, [%0, -%2]!" 1.1.1.2 root 4848: [(set_attr "type" "load")]) 4849: 4850: (define_insn "" 4851: [(set (match_operand:SI 3 "s_register_operand" "=r") 4852: (zero_extend:SI 4853: (mem:QI (plus:SI (match_operand:SI 1 "s_register_operand" "%0") 4854: (match_operand:SI 2 "index_operand" "rJ"))))) 4855: (set (match_operand:SI 0 "s_register_operand" "=r") 4856: (plus:SI (match_dup 1) (match_dup 2)))] 4857: "REGNO (operands[0]) != FRAME_POINTER_REGNUM 4858: && REGNO (operands[1]) != FRAME_POINTER_REGNUM 4859: && (GET_CODE (operands[2]) != REG 4860: || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" 1.1.1.3 root 4861: "ldr%?b\\t%3, [%0, %2]!\\t%@ z_extendqisi" 1.1.1.2 root 4862: [(set_attr "type" "load")]) 4863: 4864: (define_insn "" 4865: [(set (match_operand:SI 3 "s_register_operand" "=r") 4866: (zero_extend:SI 4867: (mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0") 4868: (match_operand:SI 2 "s_register_operand" "r"))))) 4869: (set (match_operand:SI 0 "s_register_operand" "=r") 4870: (minus:SI (match_dup 1) (match_dup 2)))] 4871: "REGNO (operands[0]) != FRAME_POINTER_REGNUM 4872: && REGNO (operands[1]) != FRAME_POINTER_REGNUM 4873: && (GET_CODE (operands[2]) != REG 4874: || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" 1.1.1.3 root 4875: "ldr%?b\\t%3, [%0, -%2]!\\t%@ z_extendqisi" 1.1.1.2 root 4876: [(set_attr "type" "load")]) 4877: 4878: (define_insn "" 4879: [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%0") 4880: (match_operand:SI 2 "index_operand" "rJ"))) 4881: (match_operand:SI 3 "s_register_operand" "r")) 4882: (set (match_operand:SI 0 "s_register_operand" "=r") 4883: (plus:SI (match_dup 1) (match_dup 2)))] 4884: "REGNO (operands[0]) != FRAME_POINTER_REGNUM 4885: && REGNO (operands[1]) != FRAME_POINTER_REGNUM 4886: && (GET_CODE (operands[2]) != REG 4887: || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" 1.1.1.3 root 4888: "str%?\\t%3, [%0, %2]!" 1.1.1.2 root 4889: [(set_attr "type" "store1")]) 4890: 4891: (define_insn "" 4892: [(set (mem:SI (minus:SI (match_operand:SI 1 "s_register_operand" "0") 4893: (match_operand:SI 2 "s_register_operand" "r"))) 4894: (match_operand:SI 3 "s_register_operand" "r")) 4895: (set (match_operand:SI 0 "s_register_operand" "=r") 4896: (minus:SI (match_dup 1) (match_dup 2)))] 4897: "REGNO (operands[0]) != FRAME_POINTER_REGNUM 4898: && REGNO (operands[1]) != FRAME_POINTER_REGNUM 4899: && (GET_CODE (operands[2]) != REG 4900: || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" 1.1.1.3 root 4901: "str%?\\t%3, [%0, -%2]!" 1.1.1.2 root 4902: [(set_attr "type" "store1")]) 4903: 4904: (define_insn "" 4905: [(set (match_operand:SI 3 "s_register_operand" "=r") 4906: (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%0") 4907: (match_operand:SI 2 "index_operand" "rJ")))) 4908: (set (match_operand:SI 0 "s_register_operand" "=r") 4909: (plus:SI (match_dup 1) (match_dup 2)))] 4910: "REGNO (operands[0]) != FRAME_POINTER_REGNUM 4911: && REGNO (operands[1]) != FRAME_POINTER_REGNUM 4912: && (GET_CODE (operands[2]) != REG 4913: || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" 1.1.1.3 root 4914: "ldr%?\\t%3, [%0, %2]!" 1.1.1.2 root 4915: [(set_attr "type" "load")]) 4916: 4917: (define_insn "" 4918: [(set (match_operand:SI 3 "s_register_operand" "=r") 4919: (mem:SI (minus:SI (match_operand:SI 1 "s_register_operand" "0") 4920: (match_operand:SI 2 "s_register_operand" "r")))) 4921: (set (match_operand:SI 0 "s_register_operand" "=r") 4922: (minus:SI (match_dup 1) (match_dup 2)))] 4923: "REGNO (operands[0]) != FRAME_POINTER_REGNUM 4924: && REGNO (operands[1]) != FRAME_POINTER_REGNUM 4925: && (GET_CODE (operands[2]) != REG 4926: || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" 1.1.1.3 root 4927: "ldr%?\\t%3, [%0, -%2]!" 1.1.1.2 root 4928: [(set_attr "type" "load")]) 4929: 4930: (define_insn "" 4931: [(set (match_operand:HI 3 "s_register_operand" "=r") 4932: (mem:HI (plus:SI (match_operand:SI 1 "s_register_operand" "%0") 4933: (match_operand:SI 2 "index_operand" "rJ")))) 4934: (set (match_operand:SI 0 "s_register_operand" "=r") 4935: (plus:SI (match_dup 1) (match_dup 2)))] 1.1.1.3 root 4936: "(! BYTES_BIG_ENDIAN) 4937: && ! TARGET_SHORT_BY_BYTES 4938: && REGNO (operands[0]) != FRAME_POINTER_REGNUM 1.1.1.2 root 4939: && REGNO (operands[1]) != FRAME_POINTER_REGNUM 4940: && (GET_CODE (operands[2]) != REG 4941: || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" 1.1.1.3 root 4942: "ldr%?\\t%3, [%0, %2]!\\t%@ loadhi" 1.1.1.2 root 4943: [(set_attr "type" "load")]) 4944: 4945: (define_insn "" 4946: [(set (match_operand:HI 3 "s_register_operand" "=r") 4947: (mem:HI (minus:SI (match_operand:SI 1 "s_register_operand" "0") 4948: (match_operand:SI 2 "s_register_operand" "r")))) 4949: (set (match_operand:SI 0 "s_register_operand" "=r") 4950: (minus:SI (match_dup 1) (match_dup 2)))] 1.1.1.3 root 4951: "(!BYTES_BIG_ENDIAN) 4952: && ! TARGET_SHORT_BY_BYTES 4953: && REGNO (operands[0]) != FRAME_POINTER_REGNUM 1.1.1.2 root 4954: && REGNO (operands[1]) != FRAME_POINTER_REGNUM 4955: && (GET_CODE (operands[2]) != REG 4956: || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" 1.1.1.3 root 4957: "ldr%?\\t%3, [%0, -%2]!\\t%@ loadhi" 1.1.1.2 root 4958: [(set_attr "type" "load")]) 4959: 4960: (define_insn "" 4961: [(set (mem:QI (plus:SI (match_operator:SI 2 "shift_operator" 4962: [(match_operand:SI 3 "s_register_operand" "r") 4963: (match_operand:SI 4 "const_shift_operand" "n")]) 4964: (match_operand:SI 1 "s_register_operand" "0"))) 4965: (match_operand:QI 5 "s_register_operand" "r")) 4966: (set (match_operand:SI 0 "s_register_operand" "=r") 4967: (plus:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)]) 4968: (match_dup 1)))] 4969: "REGNO (operands[0]) != FRAME_POINTER_REGNUM 4970: && REGNO (operands[1]) != FRAME_POINTER_REGNUM 4971: && REGNO (operands[3]) != FRAME_POINTER_REGNUM" 1.1.1.3 root 4972: "str%?b\\t%5, [%0, %3%S2]!" 1.1.1.2 root 4973: [(set_attr "type" "store1")]) 4974: 4975: (define_insn "" 4976: [(set (mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0") 4977: (match_operator:SI 2 "shift_operator" 4978: [(match_operand:SI 3 "s_register_operand" "r") 4979: (match_operand:SI 4 "const_shift_operand" "n")]))) 4980: (match_operand:QI 5 "s_register_operand" "r")) 4981: (set (match_operand:SI 0 "s_register_operand" "=r") 4982: (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3) 4983: (match_dup 4)])))] 4984: "REGNO (operands[0]) != FRAME_POINTER_REGNUM 4985: && REGNO (operands[1]) != FRAME_POINTER_REGNUM 4986: && REGNO (operands[3]) != FRAME_POINTER_REGNUM" 1.1.1.3 root 4987: "str%?b\\t%5, [%0, -%3%S2]!" 1.1.1.2 root 4988: [(set_attr "type" "store1")]) 4989: 4990: (define_insn "" 4991: [(set (match_operand:QI 5 "s_register_operand" "=r") 4992: (mem:QI (plus:SI (match_operator:SI 2 "shift_operator" 4993: [(match_operand:SI 3 "s_register_operand" "r") 4994: (match_operand:SI 4 "const_shift_operand" "n")]) 4995: (match_operand:SI 1 "s_register_operand" "0")))) 4996: (set (match_operand:SI 0 "s_register_operand" "=r") 4997: (plus:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)]) 4998: (match_dup 1)))] 4999: "REGNO (operands[0]) != FRAME_POINTER_REGNUM 5000: && REGNO (operands[1]) != FRAME_POINTER_REGNUM 5001: && REGNO (operands[3]) != FRAME_POINTER_REGNUM" 1.1.1.3 root 5002: "ldr%?b\\t%5, [%0, %3%S2]!" 1.1.1.2 root 5003: [(set_attr "type" "load")]) 5004: 5005: (define_insn "" 5006: [(set (match_operand:QI 5 "s_register_operand" "=r") 5007: (mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0") 5008: (match_operator:SI 2 "shift_operator" 5009: [(match_operand:SI 3 "s_register_operand" "r") 5010: (match_operand:SI 4 "const_shift_operand" "n")])))) 5011: (set (match_operand:SI 0 "s_register_operand" "=r") 5012: (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3) 5013: (match_dup 4)])))] 5014: "REGNO (operands[0]) != FRAME_POINTER_REGNUM 5015: && REGNO (operands[1]) != FRAME_POINTER_REGNUM 5016: && REGNO (operands[3]) != FRAME_POINTER_REGNUM" 1.1.1.3 root 5017: "ldr%?b\\t%5, [%0, -%3%S2]!" 1.1.1.2 root 5018: [(set_attr "type" "load")]) 5019: 5020: (define_insn "" 5021: [(set (mem:SI (plus:SI (match_operator:SI 2 "shift_operator" 5022: [(match_operand:SI 3 "s_register_operand" "r") 5023: (match_operand:SI 4 "const_shift_operand" "n")]) 5024: (match_operand:SI 1 "s_register_operand" "0"))) 5025: (match_operand:SI 5 "s_register_operand" "r")) 5026: (set (match_operand:SI 0 "s_register_operand" "=r") 5027: (plus:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)]) 5028: (match_dup 1)))] 5029: "REGNO (operands[0]) != FRAME_POINTER_REGNUM 5030: && REGNO (operands[1]) != FRAME_POINTER_REGNUM 5031: && REGNO (operands[3]) != FRAME_POINTER_REGNUM" 1.1.1.3 root 5032: "str%?\\t%5, [%0, %3%S2]!" 1.1.1.2 root 5033: [(set_attr "type" "store1")]) 5034: 5035: (define_insn "" 5036: [(set (mem:SI (minus:SI (match_operand:SI 1 "s_register_operand" "0") 5037: (match_operator:SI 2 "shift_operator" 5038: [(match_operand:SI 3 "s_register_operand" "r") 5039: (match_operand:SI 4 "const_shift_operand" "n")]))) 5040: (match_operand:SI 5 "s_register_operand" "r")) 5041: (set (match_operand:SI 0 "s_register_operand" "=r") 5042: (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3) 5043: (match_dup 4)])))] 5044: "REGNO (operands[0]) != FRAME_POINTER_REGNUM 5045: && REGNO (operands[1]) != FRAME_POINTER_REGNUM 5046: && REGNO (operands[3]) != FRAME_POINTER_REGNUM" 1.1.1.3 root 5047: "str%?\\t%5, [%0, -%3%S2]!" 1.1.1.2 root 5048: [(set_attr "type" "store1")]) 5049: 5050: (define_insn "" 5051: [(set (match_operand:SI 5 "s_register_operand" "=r") 5052: (mem:SI (plus:SI (match_operator:SI 2 "shift_operator" 5053: [(match_operand:SI 3 "s_register_operand" "r") 5054: (match_operand:SI 4 "const_shift_operand" "n")]) 5055: (match_operand:SI 1 "s_register_operand" "0")))) 5056: (set (match_operand:SI 0 "s_register_operand" "=r") 5057: (plus:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)]) 5058: (match_dup 1)))] 5059: "REGNO (operands[0]) != FRAME_POINTER_REGNUM 5060: && REGNO (operands[1]) != FRAME_POINTER_REGNUM 5061: && REGNO (operands[3]) != FRAME_POINTER_REGNUM" 1.1.1.3 root 5062: "ldr%?\\t%5, [%0, %3%S2]!" 1.1.1.2 root 5063: [(set_attr "type" "load")]) 5064: 5065: (define_insn "" 5066: [(set (match_operand:SI 5 "s_register_operand" "=r") 5067: (mem:SI (minus:SI (match_operand:SI 1 "s_register_operand" "0") 5068: (match_operator:SI 2 "shift_operator" 5069: [(match_operand:SI 3 "s_register_operand" "r") 5070: (match_operand:SI 4 "const_shift_operand" "n")])))) 5071: (set (match_operand:SI 0 "s_register_operand" "=r") 5072: (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3) 5073: (match_dup 4)])))] 5074: "REGNO (operands[0]) != FRAME_POINTER_REGNUM 5075: && REGNO (operands[1]) != FRAME_POINTER_REGNUM 5076: && REGNO (operands[3]) != FRAME_POINTER_REGNUM" 1.1.1.3 root 5077: "ldr%?\\t%5, [%0, -%3%S2]!" 1.1.1.2 root 5078: [(set_attr "type" "load")]) 5079: 5080: (define_insn "" 5081: [(set (match_operand:HI 5 "s_register_operand" "=r") 5082: (mem:HI (plus:SI (match_operator:SI 2 "shift_operator" 5083: [(match_operand:SI 3 "s_register_operand" "r") 5084: (match_operand:SI 4 "const_shift_operand" "n")]) 5085: (match_operand:SI 1 "s_register_operand" "0")))) 5086: (set (match_operand:SI 0 "s_register_operand" "=r") 5087: (plus:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)]) 5088: (match_dup 1)))] 1.1.1.3 root 5089: "(! BYTES_BIG_ENDIAN) 5090: && ! TARGET_SHORT_BY_BYTES 5091: && REGNO (operands[0]) != FRAME_POINTER_REGNUM 1.1.1.2 root 5092: && REGNO (operands[1]) != FRAME_POINTER_REGNUM 5093: && REGNO (operands[3]) != FRAME_POINTER_REGNUM" 1.1.1.3 root 5094: "ldr%?\\t%5, [%0, %3%S2]!\\t%@ loadhi" 1.1.1.2 root 5095: [(set_attr "type" "load")]) 5096: 5097: (define_insn "" 5098: [(set (match_operand:HI 5 "s_register_operand" "=r") 5099: (mem:HI (minus:SI (match_operand:SI 1 "s_register_operand" "0") 5100: (match_operator:SI 2 "shift_operator" 5101: [(match_operand:SI 3 "s_register_operand" "r") 5102: (match_operand:SI 4 "const_shift_operand" "n")])))) 5103: (set (match_operand:SI 0 "s_register_operand" "=r") 5104: (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3) 5105: (match_dup 4)])))] 1.1.1.3 root 5106: "(! BYTES_BIG_ENDIAN) 5107: && ! TARGET_SHORT_BY_BYTES 5108: && REGNO (operands[0]) != FRAME_POINTER_REGNUM 1.1.1.2 root 5109: && REGNO (operands[1]) != FRAME_POINTER_REGNUM 5110: && REGNO (operands[3]) != FRAME_POINTER_REGNUM" 1.1.1.3 root 5111: "ldr%?\\t%5, [%0, -%3%S2]!\\t%@ loadhi" 1.1.1.2 root 5112: [(set_attr "type" "load")]) 5113: 5114: ; It can also support extended post-inc expressions, but combine doesn't 5115: ; try these.... 5116: ; It doesn't seem worth adding peepholes for anything but the most common 5117: ; cases since, unlike combine, the increment must immediately follow the load 5118: ; for this pattern to match. 5119: ; When loading we must watch to see that the base register isn't trampled by 5120: ; the load. In such cases this isn't a post-inc expression. 5121: 5122: (define_peephole 5123: [(set (mem:QI (match_operand:SI 0 "s_register_operand" "+r")) 5124: (match_operand:QI 2 "s_register_operand" "r")) 5125: (set (match_dup 0) 5126: (plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))] 5127: "" 1.1.1.3 root 5128: "str%?b\\t%2, [%0], %1") 1.1.1.2 root 5129: 5130: (define_peephole 5131: [(set (match_operand:QI 0 "s_register_operand" "=r") 5132: (mem:QI (match_operand:SI 1 "s_register_operand" "+r"))) 5133: (set (match_dup 1) 5134: (plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))] 5135: "REGNO(operands[0]) != REGNO(operands[1]) 5136: && (GET_CODE (operands[2]) != REG 5137: || REGNO(operands[0]) != REGNO (operands[2]))" 1.1.1.3 root 5138: "ldr%?b\\t%0, [%1], %2") 1.1.1.2 root 5139: 5140: (define_peephole 5141: [(set (mem:SI (match_operand:SI 0 "s_register_operand" "+r")) 5142: (match_operand:SI 2 "s_register_operand" "r")) 5143: (set (match_dup 0) 5144: (plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))] 5145: "" 1.1.1.3 root 5146: "str%?\\t%2, [%0], %1") 1.1.1.2 root 5147: 5148: (define_peephole 5149: [(set (match_operand:HI 0 "s_register_operand" "=r") 5150: (mem:HI (match_operand:SI 1 "s_register_operand" "+r"))) 5151: (set (match_dup 1) 5152: (plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))] 1.1.1.3 root 5153: "(! BYTES_BIG_ENDIAN) 5154: && ! TARGET_SHORT_BY_BYTES 5155: && REGNO(operands[0]) != REGNO(operands[1]) 1.1.1.2 root 5156: && (GET_CODE (operands[2]) != REG 5157: || REGNO(operands[0]) != REGNO (operands[2]))" 1.1.1.3 root 5158: "ldr%?\\t%0, [%1], %2\\t%@ loadhi") 1.1.1.2 root 5159: 5160: (define_peephole 5161: [(set (match_operand:SI 0 "s_register_operand" "=r") 5162: (mem:SI (match_operand:SI 1 "s_register_operand" "+r"))) 5163: (set (match_dup 1) 5164: (plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))] 5165: "REGNO(operands[0]) != REGNO(operands[1]) 5166: && (GET_CODE (operands[2]) != REG 5167: || REGNO(operands[0]) != REGNO (operands[2]))" 1.1.1.3 root 5168: "ldr%?\\t%0, [%1], %2") 5169: 5170: (define_peephole 5171: [(set (mem:QI (plus:SI (match_operand:SI 0 "s_register_operand" "+r") 5172: (match_operand:SI 1 "index_operand" "rJ"))) 5173: (match_operand:QI 2 "s_register_operand" "r")) 5174: (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))] 5175: "" 5176: "str%?b\\t%2, [%0, %1]!") 5177: 5178: (define_peephole 5179: [(set (mem:QI (plus:SI (match_operator:SI 4 "shift_operator" 5180: [(match_operand:SI 0 "s_register_operand" "r") 5181: (match_operand:SI 1 "const_int_operand" "n")]) 5182: (match_operand:SI 2 "s_register_operand" "+r"))) 5183: (match_operand:QI 3 "s_register_operand" "r")) 5184: (set (match_dup 2) (plus:SI (match_op_dup 4 [(match_dup 0) (match_dup 1)]) 5185: (match_dup 2)))] 5186: "" 5187: "str%?b\\t%3, [%2, %0%S4]!") 1.1.1.2 root 5188: 5189: ; This pattern is never tried by combine, so do it as a peephole 5190: 5191: (define_peephole 5192: [(set (match_operand:SI 0 "s_register_operand" "=r") 5193: (match_operand:SI 1 "s_register_operand" "r")) 5194: (set (match_operand 2 "cc_register" "") 5195: (compare (match_dup 1) (const_int 0)))] 5196: "" 1.1.1.3 root 5197: "sub%?s\\t%0, %1, #0" 1.1.1.2 root 5198: [(set_attr "conds" "set")]) 5199: 5200: ; Peepholes to spot possible load- and store-multiples, if the ordering is 5201: ; reversed, check that the memory references aren't volatile. 5202: 5203: (define_peephole 5204: [(set (match_operand:SI 0 "s_register_operand" "=r") 5205: (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r") 5206: (const_int 12)))) 5207: (set (match_operand:SI 2 "s_register_operand" "=r") 5208: (mem:SI (plus:SI (match_dup 1) (const_int 8)))) 5209: (set (match_operand:SI 3 "s_register_operand" "=r") 5210: (mem:SI (plus:SI (match_dup 1) (const_int 4)))) 5211: (set (match_operand:SI 4 "s_register_operand" "=r") 5212: (mem:SI (match_dup 1)))] 5213: "REGNO (operands[0]) > REGNO (operands[2]) 5214: && REGNO (operands[2]) > REGNO (operands[3]) 5215: && REGNO (operands[3]) > REGNO (operands[4]) 5216: && !(REGNO (operands[1]) == REGNO (operands[0]) 5217: || REGNO (operands[1]) == REGNO (operands[2]) 5218: || REGNO (operands[1]) == REGNO (operands[3]) 5219: || REGNO (operands[1]) == REGNO (operands[4])) 5220: && !MEM_VOLATILE_P (SET_SRC (PATTERN (insn))) 5221: && !MEM_VOLATILE_P (SET_SRC (PATTERN (prev_nonnote_insn (insn)))) 5222: && !MEM_VOLATILE_P (SET_SRC (PATTERN (prev_nonnote_insn 5223: (prev_nonnote_insn (insn))))) 5224: && !MEM_VOLATILE_P (SET_SRC (PATTERN (prev_nonnote_insn 5225: (prev_nonnote_insn 5226: (prev_nonnote_insn (insn))))))" 1.1.1.3 root 5227: "ldm%?ia\\t%1, {%4, %3, %2, %0}\\t%@ phole ldm") 1.1.1.2 root 5228: 5229: (define_peephole 5230: [(set (match_operand:SI 0 "s_register_operand" "=r") 5231: (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r") 5232: (const_int 8)))) 5233: (set (match_operand:SI 2 "s_register_operand" "=r") 5234: (mem:SI (plus:SI (match_dup 1) (const_int 4)))) 5235: (set (match_operand:SI 3 "s_register_operand" "=r") 5236: (mem:SI (match_dup 1)))] 5237: "REGNO (operands[0]) > REGNO (operands[2]) 5238: && REGNO (operands[2]) > REGNO (operands[3]) 5239: && !(REGNO (operands[1]) == REGNO (operands[0]) 5240: || REGNO (operands[1]) == REGNO (operands[2]) 5241: || REGNO (operands[1]) == REGNO (operands[3])) 5242: && !MEM_VOLATILE_P (SET_SRC (PATTERN (insn))) 5243: && !MEM_VOLATILE_P (SET_SRC (PATTERN (prev_nonnote_insn (insn)))) 5244: && !MEM_VOLATILE_P (SET_SRC (PATTERN (prev_nonnote_insn 5245: (prev_nonnote_insn (insn)))))" 1.1.1.3 root 5246: "ldm%?ia\\t%1, {%3, %2, %0}\\t%@ phole ldm") 1.1.1.2 root 5247: 5248: (define_peephole 5249: [(set (match_operand:SI 0 "s_register_operand" "=r") 5250: (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r") 5251: (const_int 4)))) 5252: (set (match_operand:SI 2 "s_register_operand" "=r") 5253: (mem:SI (match_dup 1)))] 5254: "REGNO (operands[0]) > REGNO (operands[2]) 5255: && !(REGNO (operands[1]) == REGNO (operands[0]) 5256: || REGNO (operands[1]) == REGNO (operands[2])) 5257: && !MEM_VOLATILE_P (SET_SRC (PATTERN (insn))) 5258: && !MEM_VOLATILE_P (SET_SRC (PATTERN (prev_nonnote_insn (insn))))" 1.1.1.3 root 5259: "ldm%?ia\\t%1, {%2, %0}\\t%@ phole ldm") 1.1.1.2 root 5260: 5261: (define_peephole 5262: [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r") 5263: (const_int 12))) 5264: (match_operand:SI 0 "s_register_operand" "r")) 5265: (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 5266: (match_operand:SI 2 "s_register_operand" "r")) 5267: (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 5268: (match_operand:SI 3 "s_register_operand" "r")) 5269: (set (mem:SI (match_dup 1)) 5270: (match_operand:SI 4 "s_register_operand" "r"))] 5271: "REGNO (operands[0]) > REGNO (operands[2]) 5272: && REGNO (operands[2]) > REGNO (operands[3]) 5273: && REGNO (operands[3]) > REGNO (operands[4]) 5274: && !MEM_VOLATILE_P (SET_DEST (PATTERN (insn))) 5275: && !MEM_VOLATILE_P (SET_DEST (PATTERN (prev_nonnote_insn (insn)))) 5276: && !MEM_VOLATILE_P (SET_DEST (PATTERN (prev_nonnote_insn 5277: (prev_nonnote_insn (insn))))) 5278: && !MEM_VOLATILE_P (SET_DEST (PATTERN (prev_nonnote_insn 5279: (prev_nonnote_insn 5280: (prev_nonnote_insn (insn))))))" 1.1.1.3 root 5281: "stm%?ia\\t%1, {%4, %3, %2, %0}\\t%@ phole stm") 1.1.1.2 root 5282: 5283: (define_peephole 5284: [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r") 5285: (const_int 8))) 5286: (match_operand:SI 0 "s_register_operand" "r")) 5287: (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 5288: (match_operand:SI 2 "s_register_operand" "r")) 5289: (set (mem:SI (match_dup 1)) 5290: (match_operand:SI 3 "s_register_operand" "r"))] 5291: "REGNO (operands[0]) > REGNO (operands[2]) 5292: && REGNO (operands[2]) > REGNO (operands[3]) 5293: && !MEM_VOLATILE_P (SET_DEST (PATTERN (insn))) 5294: && !MEM_VOLATILE_P (SET_DEST (PATTERN (prev_nonnote_insn (insn)))) 5295: && !MEM_VOLATILE_P (SET_DEST (PATTERN (prev_nonnote_insn 5296: (prev_nonnote_insn (insn)))))" 1.1.1.3 root 5297: "stm%?ia\\t%1, {%3, %2, %0}\\t%@ phole stm") 1.1.1.2 root 5298: 5299: (define_peephole 5300: [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r") 5301: (const_int 4))) 5302: (match_operand:SI 0 "s_register_operand" "r")) 5303: (set (mem:SI (match_dup 1)) 5304: (match_operand:SI 2 "s_register_operand" "r"))] 5305: "REGNO (operands[0]) > REGNO (operands[2]) 5306: && !MEM_VOLATILE_P (SET_DEST (PATTERN (insn))) 5307: && !MEM_VOLATILE_P (SET_DEST (PATTERN (prev_nonnote_insn (insn))))" 1.1.1.3 root 5308: "stm%?ia\\t%1, {%2, %0}\\t%@ phole stm") 1.1.1.2 root 5309: 5310: ;; A call followed by return can be replaced by restoring the regs and 5311: ;; jumping to the subroutine, provided we aren't passing the address of 5312: ;; any of our local variables. If we call alloca then this is unsafe 5313: ;; since restoring the frame frees the memory, which is not what we want. 5314: ;; Sometimes the return might have been targeted by the final prescan: 1.1.1.4 root 5315: ;; if so then emit a proper return insn as well. 1.1.1.2 root 5316: ;; Unfortunately, if the frame pointer is required, we don't know if the 5317: ;; current function has any implicit stack pointer adjustments that will 5318: ;; be restored by the return: we can't therefore do a tail call. 5319: ;; Another unfortunate that we can't handle is if current_function_args_size 5320: ;; is non-zero: in this case elimination of the argument pointer assumed 5321: ;; that lr was pushed onto the stack, so eliminating upsets the offset 5322: ;; calculations. 5323: 5324: (define_peephole 5325: [(parallel [(call (mem:SI (match_operand:SI 0 "" "i")) 5326: (match_operand:SI 1 "general_operand" "g")) 5327: (clobber (reg:SI 14))]) 5328: (return)] 5329: "(GET_CODE (operands[0]) == SYMBOL_REF && USE_RETURN_INSN 5330: && !get_frame_size () && !current_function_calls_alloca 5331: && !frame_pointer_needed && !current_function_args_size)" 5332: "* 5333: { 5334: extern rtx arm_target_insn; 5335: extern int arm_ccfsm_state, arm_current_cc; 5336: 5337: if (arm_ccfsm_state && arm_target_insn && INSN_DELETED_P (arm_target_insn)) 5338: { 5339: arm_current_cc ^= 1; 5340: output_return_instruction (NULL, TRUE); 5341: arm_ccfsm_state = 0; 5342: arm_target_insn = NULL; 5343: } 5344: 5345: output_return_instruction (NULL, FALSE); 1.1.1.3 root 5346: return \"b%?\\t%a0\"; 1.1.1.2 root 5347: }" 5348: [(set (attr "conds") 5349: (if_then_else (eq_attr "cpu" "arm6") 5350: (const_string "clob") 5351: (const_string "nocond"))) 1.1.1.3 root 5352: (set_attr "length" "8")]) 1.1.1.2 root 5353: 5354: (define_peephole 5355: [(parallel [(set (match_operand 0 "s_register_operand" "=rf") 5356: (call (mem:SI (match_operand:SI 1 "" "i")) 5357: (match_operand:SI 2 "general_operand" "g"))) 5358: (clobber (reg:SI 14))]) 5359: (return)] 5360: "(GET_CODE (operands[1]) == SYMBOL_REF && USE_RETURN_INSN 5361: && !get_frame_size () && !current_function_calls_alloca 5362: && !frame_pointer_needed && !current_function_args_size)" 5363: "* 5364: { 5365: extern rtx arm_target_insn; 5366: extern int arm_ccfsm_state, arm_current_cc; 5367: 5368: if (arm_ccfsm_state && arm_target_insn && INSN_DELETED_P (arm_target_insn)) 5369: { 5370: arm_current_cc ^= 1; 5371: output_return_instruction (NULL, TRUE); 5372: arm_ccfsm_state = 0; 5373: arm_target_insn = NULL; 5374: } 5375: 5376: output_return_instruction (NULL, FALSE); 1.1.1.3 root 5377: return \"b%?\\t%a1\"; 1.1.1.2 root 5378: }" 5379: [(set (attr "conds") 5380: (if_then_else (eq_attr "cpu" "arm6") 5381: (const_string "clob") 5382: (const_string "nocond"))) 1.1.1.3 root 5383: (set_attr "length" "8")]) 1.1.1.2 root 5384: 5385: ;; As above but when this function is not void, we must be returning the 5386: ;; result of the called subroutine. 5387: 5388: (define_peephole 5389: [(parallel [(set (match_operand 0 "s_register_operand" "=rf") 5390: (call (mem:SI (match_operand:SI 1 "" "i")) 5391: (match_operand:SI 2 "general_operand" "g"))) 5392: (clobber (reg:SI 14))]) 5393: (use (match_dup 0)) 5394: (return)] 5395: "(GET_CODE (operands[1]) == SYMBOL_REF && USE_RETURN_INSN 5396: && !get_frame_size () && !current_function_calls_alloca 5397: && !frame_pointer_needed && !current_function_args_size)" 5398: "* 5399: { 5400: extern rtx arm_target_insn; 5401: extern int arm_ccfsm_state, arm_current_cc; 5402: 5403: if (arm_ccfsm_state && arm_target_insn && INSN_DELETED_P (arm_target_insn)) 5404: { 5405: arm_current_cc ^= 1; 5406: output_return_instruction (NULL, TRUE); 5407: arm_ccfsm_state = 0; 5408: arm_target_insn = NULL; 5409: } 5410: 5411: output_return_instruction (NULL, FALSE); 1.1.1.3 root 5412: return \"b%?\\t%a1\"; 1.1.1.2 root 5413: }" 5414: [(set (attr "conds") 5415: (if_then_else (eq_attr "cpu" "arm6") 5416: (const_string "clob") 5417: (const_string "nocond"))) 1.1.1.3 root 5418: (set_attr "length" "8")]) 1.1.1.2 root 5419: 5420: ;; If calling a subroutine and then jumping back to somewhere else, but not 5421: ;; too far away, then we can set the link register with the branch address 5422: ;; and jump direct to the subroutine. On return from the subroutine 5423: ;; execution continues at the branch; this avoids a prefetch stall. 5424: ;; We use the length attribute (via short_branch ()) to establish whether or 1.1.1.4 root 5425: ;; not this is possible, this is the same as the sparc does. 1.1.1.2 root 5426: 5427: (define_peephole 5428: [(parallel[(call (mem:SI (match_operand:SI 0 "" "i")) 5429: (match_operand:SI 1 "general_operand" "g")) 5430: (clobber (reg:SI 14))]) 5431: (set (pc) 5432: (label_ref (match_operand 2 "" "")))] 1.1.1.3 root 5433: "0 && GET_CODE (operands[0]) == SYMBOL_REF 1.1.1.2 root 5434: && short_branch (INSN_UID (insn), INSN_UID (operands[2])) 5435: && arm_insn_not_targeted (insn)" 5436: "* 5437: { 5438: int backward = arm_backwards_branch (INSN_UID (insn), 5439: INSN_UID (operands[2])); 5440: 5441: #if 0 5442: /* Putting this in means that TARGET_6 code will ONLY run on an arm6 or 5443: * above, leaving it out means that the code will still run on an arm 2 or 3 5444: */ 5445: if (TARGET_6) 5446: { 5447: if (backward) 1.1.1.3 root 5448: output_asm_insn (\"sub%?\\t%|lr, %|pc, #(8 + . -%l2)\", operands); 1.1.1.2 root 5449: else 1.1.1.3 root 5450: output_asm_insn (\"add%?\\t%|lr, %|pc, #(%l2 - . -8)\", operands); 1.1.1.2 root 5451: } 5452: else 5453: #endif 5454: { 1.1.1.3 root 5455: output_asm_insn (\"mov%?\\t%|lr, %|pc\\t%@ protect cc\", operands); 1.1.1.2 root 5456: if (backward) 1.1.1.3 root 5457: output_asm_insn (\"sub%?\\t%|lr, %|lr, #(4 + . -%l2)\", operands); 1.1.1.2 root 5458: else 1.1.1.3 root 5459: output_asm_insn (\"add%?\\t%|lr, %|lr, #(%l2 - . -4)\", operands); 1.1.1.2 root 5460: } 1.1.1.3 root 5461: return \"b%?\\t%a0\"; 1.1.1.2 root 5462: }" 5463: [(set (attr "conds") 5464: (if_then_else (eq_attr "cpu" "arm6") 5465: (const_string "clob") 5466: (const_string "nocond"))) 5467: (set (attr "length") 5468: (if_then_else (eq_attr "cpu" "arm6") 1.1.1.3 root 5469: (const_int 8) 5470: (const_int 12)))]) 1.1.1.2 root 5471: 5472: (define_peephole 5473: [(parallel[(set (match_operand:SI 0 "s_register_operand" "=r") 5474: (call (mem:SI (match_operand:SI 1 "" "i")) 5475: (match_operand:SI 2 "general_operand" "g"))) 5476: (clobber (reg:SI 14))]) 5477: (set (pc) 5478: (label_ref (match_operand 3 "" "")))] 1.1.1.3 root 5479: "0 && GET_CODE (operands[0]) == SYMBOL_REF 1.1.1.2 root 5480: && short_branch (INSN_UID (insn), INSN_UID (operands[3])) 5481: && arm_insn_not_targeted (insn)" 5482: "* 5483: { 5484: int backward = arm_backwards_branch (INSN_UID (insn), 5485: INSN_UID (operands[3])); 5486: 5487: #if 0 5488: /* Putting this in means that TARGET_6 code will ONLY run on an arm6 or 5489: * above, leaving it out means that the code will still run on an arm 2 or 3 5490: */ 5491: if (TARGET_6) 5492: { 5493: if (backward) 1.1.1.3 root 5494: output_asm_insn (\"sub%?\\t%|lr, %|pc, #(8 + . -%l3)\", operands); 1.1.1.2 root 5495: else 1.1.1.3 root 5496: output_asm_insn (\"add%?\\t%|lr, %|pc, #(%l3 - . -8)\", operands); 1.1.1.2 root 5497: } 5498: else 5499: #endif 5500: { 1.1.1.3 root 5501: output_asm_insn (\"mov%?\\t%|lr, %|pc\\t%@ protect cc\", operands); 1.1.1.2 root 5502: if (backward) 1.1.1.3 root 5503: output_asm_insn (\"sub%?\\t%|lr, %|lr, #(4 + . -%l3)\", operands); 1.1.1.2 root 5504: else 1.1.1.3 root 5505: output_asm_insn (\"add%?\\t%|lr, %|lr, #(%l3 - . -4)\", operands); 1.1.1.2 root 5506: } 1.1.1.3 root 5507: return \"b%?\\t%a1\"; 1.1.1.2 root 5508: }" 5509: [(set (attr "conds") 5510: (if_then_else (eq_attr "cpu" "arm6") 5511: (const_string "clob") 5512: (const_string "nocond"))) 5513: (set (attr "length") 5514: (if_then_else (eq_attr "cpu" "arm6") 1.1.1.3 root 5515: (const_int 8) 5516: (const_int 12)))]) 1.1.1.2 root 5517: 5518: (define_split 5519: [(set (pc) 5520: (if_then_else (match_operator 0 "comparison_operator" 5521: [(match_operator:SI 1 "shift_operator" 5522: [(match_operand:SI 2 "s_register_operand" "r") 1.1.1.3 root 5523: (match_operand:SI 3 "reg_or_int_operand" "rM")]) 1.1.1.2 root 5524: (match_operand:SI 4 "s_register_operand" "r")]) 5525: (label_ref (match_operand 5 "" "")) 5526: (pc))) 5527: (clobber (reg 24))] 5528: "" 5529: [(set (reg:CC 24) 5530: (compare:CC (match_dup 4) 5531: (match_op_dup 1 [(match_dup 2) (match_dup 3)]))) 5532: (set (pc) 5533: (if_then_else (match_op_dup 0 [(reg 24) (const_int 0)]) 5534: (label_ref (match_dup 5)) 5535: (pc)))] 5536: " 5537: operands[0] = gen_rtx (swap_condition (GET_CODE (operands[0])), VOIDmode, 5538: operands[1], operands[2]); 5539: ") 5540: 5541: (define_split 5542: [(set (match_operand:SI 0 "s_register_operand" "") 5543: (and:SI (ge:SI (match_operand:SI 1 "s_register_operand" "") 5544: (const_int 0)) 5545: (neg:SI (match_operator:SI 2 "comparison_operator" 5546: [(match_operand:SI 3 "s_register_operand" "") 5547: (match_operand:SI 4 "arm_rhs_operand" "")])))) 5548: (clobber (match_operand:SI 5 "s_register_operand" ""))] 5549: "" 5550: [(set (match_dup 5) (not:SI (ashiftrt:SI (match_dup 1) (const_int 31)))) 5551: (set (match_dup 0) (and:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)]) 5552: (match_dup 5)))] 5553: "") 5554: 5555: ;; This pattern can be used because cc_noov mode implies that the following 5556: ;; branch will be an equality (EQ or NE), so the sign extension is not 5557: ;; needed. Combine doesn't eliminate these because by the time it sees the 5558: ;; branch it no-longer knows that the data came from memory. 5559: 5560: (define_insn "" 5561: [(set (reg:CC_NOOV 24) 5562: (compare:CC_NOOV 5563: (ashift:SI (subreg:SI (match_operand:QI 0 "memory_operand" "m") 0) 5564: (const_int 24)) 5565: (match_operand 1 "immediate_operand" "I"))) 5566: (clobber (match_scratch:SI 2 "=r"))] 5567: "((unsigned long) INTVAL (operands[1])) 5568: == (((unsigned long) INTVAL (operands[1])) >> 24) << 24" 5569: "* 5570: operands[1] = GEN_INT (((unsigned long) INTVAL (operands[1])) >> 24); 1.1.1.3 root 5571: output_asm_insn (\"ldr%?b\\t%2, %0\", operands); 5572: output_asm_insn (\"cmp%?\\t%2, %1\", operands); 5573: return \"\"; 1.1.1.2 root 5574: " 5575: [(set_attr "conds" "set") 1.1.1.3 root 5576: (set_attr "length" "8") 1.1.1.2 root 5577: (set_attr "type" "load")]) 5578: 1.1.1.3 root 5579: (define_expand "prologue" 5580: [(clobber (const_int 0))] 1.1.1.2 root 5581: "" 5582: " 1.1.1.3 root 5583: arm_expand_prologue (); 1.1.1.2 root 5584: DONE; 1.1.1.3 root 5585: ") 1.1.1.2 root 5586: 5587: ;; This split is only used during output to reduce the number of patterns 5588: ;; that need assembler instructions adding to them. We allowed the setting 5589: ;; of the conditions to be implicit during rtl generation so that 5590: ;; the conditional compare patterns would work. However this conflicts to 5591: ;; some extend with the conditional data operations, so we have to split them 5592: ;; up again here. 5593: 5594: (define_split 5595: [(set (match_operand:SI 0 "s_register_operand" "") 5596: (if_then_else:SI (match_operator 1 "comparison_operator" 5597: [(match_operand 2 "" "") (match_operand 3 "" "")]) 5598: (match_operand 4 "" "") 5599: (match_operand 5 "" ""))) 5600: (clobber (reg 24))] 5601: "reload_completed" 5602: [(set (match_dup 6) (match_dup 7)) 5603: (set (match_dup 0) 5604: (if_then_else:SI (match_op_dup 1 [(match_dup 6) (const_int 0)]) 5605: (match_dup 4) 5606: (match_dup 5)))] 5607: " 5608: { 5609: enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]), operands[2], 5610: operands[3]); 5611: 5612: operands[6] = gen_rtx (REG, mode, 24); 5613: operands[7] = gen_rtx (COMPARE, mode, operands[2], operands[3]); 5614: } 5615: ") 5616: 5617: 5618: (define_insn "" 5619: [(set (match_operand:SI 0 "s_register_operand" "=r,r") 5620: (if_then_else:SI (match_operator 4 "comparison_operator" 1.1.1.3 root 5621: [(match_operand 3 "reversible_cc_register" "") 5622: (const_int 0)]) 1.1.1.2 root 5623: (match_operand:SI 1 "arm_rhs_operand" "0,?rI") 5624: (not:SI 5625: (match_operand:SI 2 "s_register_operand" "r,r"))))] 5626: "" 1.1.1.3 root 5627: "@ 5628: mvn%D4\\t%0, %2 5629: mov%d4\\t%0, %1\;mvn%D4\\t%0, %2" 1.1.1.2 root 5630: [(set_attr "conds" "use") 1.1.1.3 root 5631: (set_attr "length" "4,8")]) 1.1.1.2 root 5632: 5633: ;; The next two patterns occur when an AND operation is followed by a 5634: ;; scc insn sequence 5635: 5636: (define_insn "" 5637: [(set (match_operand:SI 0 "s_register_operand" "=r") 5638: (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r") 5639: (const_int 1) 5640: (match_operand:SI 2 "immediate_operand" "n")))] 5641: "" 5642: "* 5643: operands[2] = GEN_INT (1 << INTVAL (operands[2])); 1.1.1.3 root 5644: output_asm_insn (\"ands\\t%0, %1, %2\", operands); 5645: return \"mvnne\\t%0, #0\"; 1.1.1.2 root 5646: " 5647: [(set_attr "conds" "clob") 1.1.1.3 root 5648: (set_attr "length" "8")]) 1.1.1.2 root 5649: 5650: (define_insn "" 5651: [(set (match_operand:SI 0 "s_register_operand" "=r") 5652: (not:SI 5653: (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r") 5654: (const_int 1) 5655: (match_operand:SI 2 "immediate_operand" "n"))))] 5656: "" 5657: "* 5658: operands[2] = GEN_INT (1 << INTVAL (operands[2])); 1.1.1.3 root 5659: output_asm_insn (\"tst\\t%1, %2\", operands); 5660: output_asm_insn (\"mvneq\\t%0, #0\", operands); 5661: return \"movne\\t%0, #0\"; 1.1.1.2 root 5662: " 5663: [(set_attr "conds" "clob") 1.1.1.3 root 5664: (set_attr "length" "12")]) 5665: 5666: ;; Push multiple registers to the stack. The first register is in the 5667: ;; unspec part of the insn; subsequent registers are in parallel (use ...) 5668: ;; expressions. 5669: (define_insn "" 5670: [(match_parallel 2 "multi_register_push" 5671: [(set (match_operand:BLK 0 "memory_operand" "=m") 5672: (unspec:BLK [(match_operand:SI 1 "s_register_operand" "r")] 2))])] 5673: "" 5674: "* 5675: { 5676: char pattern[100]; 5677: int i; 5678: extern int lr_save_eliminated; 5679: 5680: if (lr_save_eliminated) 5681: { 5682: if (XVECLEN (operands[2], 0) > 1) 5683: abort (); 5684: return \"\"; 5685: } 5686: strcpy (pattern, \"stmfd\\t%m0!, {%|%1\"); 5687: for (i = 1; i < XVECLEN (operands[2], 0); i++) 5688: { 5689: strcat (pattern, \", %|\"); 5690: strcat (pattern, reg_names[REGNO (XEXP (XVECEXP (operands[2], 0, i), 5691: 0))]); 5692: } 5693: strcat (pattern, \"}\"); 5694: output_asm_insn (pattern, operands); 5695: return \"\"; 5696: }" 5697: [(set_attr "type" "store4")])
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