--- gcc/config/clipper/clipper.md	2018/04/24 18:10:23	1.1
+++ gcc/config/clipper/clipper.md	2018/04/24 18:27:51	1.1.1.4
@@ -1,6 +1,5 @@
 ;;- Machine description for GNU compiler, Clipper Version
-;;   Copyright (C) 1987, 1988, 1991 Free Software Foundation, Inc.
-
+;;   Copyright (C) 1987, 1988, 1991, 1993, 1994 Free Software Foundation, Inc.
 ;; Contributed by Holger Teutsch (holger@hotbso.rhein-main.de)
 
 ;; This file is part of GNU CC.
@@ -17,7 +16,8 @@
 
 ;; You should have received a copy of the GNU General Public License
 ;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
 
 
 ;;- Instruction patterns.  When multiple patterns apply,
@@ -60,7 +60,7 @@
   (const_string "clobber")))
 
 ;;
-;; clipper seems to be a tradional risc processor
+;; clipper seems to be a traditional risc processor
 ;; we define a functional unit 'memory'
 ;;
 (define_function_unit "memory" 1 1 (eq_attr "type" "load") 4 0)     
@@ -148,8 +148,8 @@
 ;; to recombine a mem -> mem move
 ;; 
 (define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=rf")
-	(match_operand:DF 1 "nonimmediate_operand" "rfo"))]
+  [(set (match_operand:DF 0 "register_operand" "=*rf")
+	(match_operand:DF 1 "nonimmediate_operand" "*rfo"))]
   ""
   "*
 {
@@ -203,22 +203,21 @@
 
 (define_insn ""
   [(set (match_operand:DF 0 "memory_operand" "=o,m")
-	(match_operand:DF 1 "register_operand" "r,f"))]
+	(match_operand:DF 1 "register_operand" "*rf,f"))]
   ""
   "*
 {
-  if (which_alternative == 0)		/* r -> o */
-    {
-      rtx xops[4];
-      xops[0] = operands[0];
-      xops[1] = adj_offsettable_operand (operands[0], 4);
-      xops[2] = operands[1];
-      xops[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
-      output_asm_insn (\"storw  %2,%0\;storw  %3,%1\", xops);
-      return \"\";
-    }
+  rtx xops[4];
+
+  if (REGNO (operands[1]) >= 16)	/* f -> m */
+    return \"stord  %1,%0\";
 
-  return \"stord  %1,%0\";		/* f-> m */
+  xops[0] = operands[0];		/* r -> o */
+  xops[1] = adj_offsettable_operand (operands[0], 4);
+  xops[2] = operands[1];
+  xops[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
+  output_asm_insn (\"storw  %2,%0\;storw  %3,%1\", xops);
+  return \"\";
 }"
 [(set_attr "type" "store,store")
  (set_attr "cc" "clobber,unchanged")])
@@ -248,8 +247,8 @@
 ;; to recombine a mem -> mem move
 ;; 
 (define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=rf")
-	(match_operand:SF 1 "nonimmediate_operand" "rfm"))]
+  [(set (match_operand:SF 0 "register_operand" "=*rf")
+	(match_operand:SF 1 "nonimmediate_operand" "*rfm"))]
   ""
   "*
 {
@@ -285,7 +284,7 @@
 
 (define_insn ""
   [(set (match_operand:SF 0 "memory_operand" "=m")
-	(match_operand:SF 1 "register_operand" "rf"))]
+	(match_operand:SF 1 "register_operand" "*rf"))]
   ""
   "*
 {
@@ -307,8 +306,11 @@
     operands[1] = force_reg (DImode, operands[1]);
 }")
 
+;; If an operand is a MEM but not offsettable, we can't load it into
+;; a register, so we must force the third alternative to be the one
+;; reloaded.  Hence we show the first as more expensive.
 (define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r,r,r")
+  [(set (match_operand:DI 0 "register_operand" "=?r,r,r")
 	(match_operand:DI 1 "general_operand"   "r,n,o"))]
   ""
   "*
@@ -384,14 +386,19 @@
     operands[1] = force_reg (SImode, operands[1]);
 }")
 
-;; provide 2 patterns with different predicates as 'general_operand' in both
-;; positions results in a 'mem -> mem' move from combine that must be reloaded 
-;;
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
-	(match_operand:SI 1 "general_operand"   "r,m,n,i"))]
-  ""
+;; Reject both args with `general_operand' if not reloading because a
+;; mem -> mem move that was split by 'movsi' can be recombined to
+;; mem -> mem by the combiner.
+;;
+;; As a pseudo register can end up in a stack slot during reloading we must
+;; allow a r->m move for the next pattern. 
+;; The first predicate must be `general_operand' because a predicate must
+;; be true for each constraint.
+;;  
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,m")
+	(match_operand:SI 1 "general_operand"  "r,m,n,i,r"))]
+  "reload_in_progress || register_operand (operands[0], SImode)"
   "*
 {
   int val;
@@ -417,9 +424,11 @@
 
   if (which_alternative == 3)		/* unknown const */
     return \"loada  %a1,%0\";
+
+  return \"storw  %1,%0\";
 }"
-[(set_attr "type" "arith,load,arith,load")
- (set_attr "cc" "set2,change0,set1,change0")])
+[(set_attr "type" "arith,load,arith,load,store")
+ (set_attr "cc" "set2,change0,set1,change0,unchanged")])
 
 
 (define_insn ""
@@ -752,7 +761,7 @@
 
 (define_insn "subdi3"
   [(set (match_operand:DI 0 "int_reg_operand" "=r")
-	(minus:DI (match_operand:DI 1 "int_reg_operand" "%0")
+	(minus:DI (match_operand:DI 1 "int_reg_operand" "0")
 		  (match_operand:DI 2 "int_reg_operand" "r")))]
   ""
   "*
@@ -1127,25 +1136,6 @@
   "shlw   %2,%0"
  [(set_attr "type" "arith")])
 
-(define_insn "lshldi3"
-  [(set (match_operand:DI 0 "int_reg_operand" "=r,r")
-	(lshift:DI (match_operand:DI 1 "int_reg_operand" "0,0")
-		   (match_operand:SI 2 "nonmemory_operand" "r,n")))]
-  ""
-  "@
-   shll   %2,%0
-   shlli  %2,%0"
- [(set_attr "type" "arith")])
-
-(define_insn "lshlsi3"
-  [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
-	(lshift:SI (match_operand:SI 1 "int_reg_operand" "0,0")
-		   (match_operand:SI 2 "nonmemory_operand" "r,n")))]
-  ""
-  "@
-   shlw   %2,%0
-   shli   %2,%0"
- [(set_attr "type" "arith")])
 
 ;;
 ;; rotate insn