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1.1 root 1: ;;- Machine description for GNU compiler, Clipper Version
2: ;; Copyright (C) 1987, 1988, 1991 Free Software Foundation, Inc.
3:
4: ;; Contributed by Holger Teutsch ([email protected])
5:
6: ;; This file is part of GNU CC.
7:
8: ;; GNU CC is free software; you can redistribute it and/or modify
9: ;; it under the terms of the GNU General Public License as published by
10: ;; the Free Software Foundation; either version 2, or (at your option)
11: ;; any later version.
12:
13: ;; GNU CC is distributed in the hope that it will be useful,
14: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16: ;; GNU General Public License for more details.
17:
18: ;; You should have received a copy of the GNU General Public License
19: ;; along with GNU CC; see the file COPYING. If not, write to
20: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21:
22:
23: ;;- Instruction patterns. When multiple patterns apply,
24: ;;- the first one in the file is chosen.
25: ;;-
26: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
27: ;;-
28: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
29: ;;- updates for most instructions.
30:
31: ;;
32: ;; define attributes
33: ;;
34: ;; instruction type
35: ;;
36: ;; unknown is temporary in order to generate 'cc clobber' until attribute
37: ;; assignment is consistent
38: ;;
39: (define_attr "type" "load,store,arith,fp,branch,unknown"
40: (const_string "unknown"))
41:
42: ;; condition code setting
43: ;;
44: ;; clobber destroyed
45: ;; unchanged
46: ;; set1 set cc_status.value1, e.g. sub r0,r1
47: ;; set2 set value1 and value2, e.g. mov r0,r1
48: ;; change0 may be side effect, i.e. load mem,r0
49: ;;
50: ;; note: loadi and loadq are 'arith' instructions that set the condition codes
51: ;; mul,div,mod do NOT set the condition codes
52: ;;
53: (define_attr "cc" "clobber,unchanged,set1,set2,change0"
54: (cond [(eq_attr "type" "load") (const_string "change0")
55: (eq_attr "type" "store,branch") (const_string "unchanged")
56: (eq_attr "type" "arith") (if_then_else (match_operand:SI 0 "" "")
57: (const_string "set1")
58: (const_string "clobber"))
59: ]
60: (const_string "clobber")))
61:
62: ;;
63: ;; clipper seems to be a tradional risc processor
64: ;; we define a functional unit 'memory'
65: ;;
66: (define_function_unit "memory" 1 1 (eq_attr "type" "load") 4 0)
67:
68:
69: ;; We don't want to allow a constant operand for test insns because
70: ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
71: ;; be folded while optimizing anyway.
72:
73: (define_insn "tstsi"
74: [(set (cc0)
75: (match_operand:SI 0 "int_reg_operand" "r"))]
76: ""
77: "cmpq $0,%0")
78:
79: (define_insn "cmpsi"
80: [(set (cc0)
81: (compare (match_operand:SI 0 "nonimmediate_operand" "r,r,n")
82: (match_operand:SI 1 "nonmemory_operand" "r,n,r")))]
83: ""
84: "*
85: {
86: int val;
87:
88: if (which_alternative == 0)
89: return \"cmpw %1,%0\";
90:
91: if (which_alternative == 1)
92: {
93: val = INTVAL (operands[1]);
94: if (0 <= val && val < 16)
95: return \"cmpq %1,%0\";
96: return \"cmpi %1,%0\";
97: }
98:
99: cc_status.flags |= CC_REVERSED; /* immediate must be first */
100:
101: val = INTVAL (operands[0]);
102:
103: if (0 <= val && val < 16)
104: return \"cmpq %0,%1\";
105:
106: return \"cmpi %0,%1\";
107: }")
108:
109: (define_insn "cmpdf"
110: [(set (cc0)
111: (compare (match_operand:DF 0 "fp_reg_operand" "f")
112: (match_operand:DF 1 "fp_reg_operand" "f")))]
113: ""
114: "cmpd %1,%0")
115:
116: (define_insn "cmpsf"
117: [(set (cc0)
118: (compare (match_operand:SF 0 "fp_reg_operand" "f")
119: (match_operand:SF 1 "fp_reg_operand" "f")))]
120: ""
121: "cmps %1,%0")
122:
123:
124: ;;
125: ;; double and single float move
126: ;;
127: (define_expand "movdf"
128: [(set (match_operand:DF 0 "general_operand" "")
129: (match_operand:DF 1 "general_operand" ""))]
130: ""
131: "
132: {
133: if (GET_CODE (operands[0]) == MEM)
134: {
135: if (GET_CODE (operands[1]) == CONST_DOUBLE)
136: operands[1] = force_reg (DFmode,
137: force_const_mem (DFmode, operands[1]));
138: else if (GET_CODE (operands[1]) != REG)
139: operands[1] = force_reg (DFmode, operands[1]);
140: }
141:
142: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
143: operands[1] = force_const_mem (DFmode, operands[1]);
144: }")
145:
146: ;;
147: ;; provide two patterns with different predicates as we don't want combine
148: ;; to recombine a mem -> mem move
149: ;;
150: (define_insn ""
151: [(set (match_operand:DF 0 "register_operand" "=rf")
152: (match_operand:DF 1 "nonimmediate_operand" "rfo"))]
153: ""
154: "*
155: {
156: #define FP_REG_P(X) (GET_CODE (X) == REG && REGNO (X) >= 16)
157:
158: if (FP_REG_P (operands[0]))
159: {
160: if (FP_REG_P (operands[1])) /* f -> f */
161: return \"movd %1,%0\";
162:
163: if (GET_CODE (operands[1]) == REG) /* r -> f */
164: return \"movld %1,%0\";
165:
166: return \"loadd %1,%0\"; /* m -> f */
167: }
168:
169: if (FP_REG_P (operands[1]))
170: {
171: if (GET_CODE (operands[0]) == REG) /* f -> r */
172: return \"movdl %1,%0\";
173:
174: abort ();
175: }
176:
177: if (GET_CODE (operands[1]) == MEM) /* m -> r */
178: {
179: rtx xops[4];
180: xops[0] = operands[0];
181: xops[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
182: xops[2] = operands[1];
183: xops[3] = adj_offsettable_operand (operands[1], 4);
184: output_asm_insn (\"loadw %2,%0\;loadw %3,%1\", xops);
185: return \"\";
186: }
187:
188: if (GET_CODE (operands[1]) == REG) /* r -> r */
189: {
190: rtx xops[4];
191: xops[0] = operands[0];
192: xops[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
193: xops[2] = operands[1];
194: xops[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
195: output_asm_insn (\"movw %2,%0\;movw %3,%1\", xops);
196: return \"\";
197: }
198:
199: abort ();
200: #undef FP_REG_P
201: }")
202:
203:
204: (define_insn ""
205: [(set (match_operand:DF 0 "memory_operand" "=o,m")
206: (match_operand:DF 1 "register_operand" "r,f"))]
207: ""
208: "*
209: {
210: if (which_alternative == 0) /* r -> o */
211: {
212: rtx xops[4];
213: xops[0] = operands[0];
214: xops[1] = adj_offsettable_operand (operands[0], 4);
215: xops[2] = operands[1];
216: xops[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
217: output_asm_insn (\"storw %2,%0\;storw %3,%1\", xops);
218: return \"\";
219: }
220:
221: return \"stord %1,%0\"; /* f-> m */
222: }"
223: [(set_attr "type" "store,store")
224: (set_attr "cc" "clobber,unchanged")])
225:
226:
227: (define_expand "movsf"
228: [(set (match_operand:SF 0 "general_operand" "")
229: (match_operand:SF 1 "general_operand" ""))]
230: ""
231: "
232: {
233: if (GET_CODE (operands[0]) == MEM)
234: {
235: if (GET_CODE (operands[1]) == CONST_DOUBLE)
236: operands[1] = force_reg (SFmode,
237: force_const_mem (SFmode, operands[1]));
238: else if (GET_CODE (operands[1]) != REG)
239: operands[1] = force_reg (SFmode, operands[1]);
240: }
241:
242: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
243: operands[1] = force_const_mem (SFmode, operands[1]);
244: }")
245:
246: ;;
247: ;; provide two patterns with different predicates as we don't want combine
248: ;; to recombine a mem -> mem move
249: ;;
250: (define_insn ""
251: [(set (match_operand:SF 0 "register_operand" "=rf")
252: (match_operand:SF 1 "nonimmediate_operand" "rfm"))]
253: ""
254: "*
255: {
256: #define FP_REG_P(X) (GET_CODE (X) == REG && REGNO (X) >= 16)
257:
258: if (FP_REG_P (operands[0]))
259: {
260: if (FP_REG_P (operands[1])) /* f -> f */
261: return \"movs %1,%0\";
262: if (GET_CODE (operands[1]) == REG) /* r -> f */
263: return
264: \"subq $8,sp\;storw %1,(sp)\;loads (sp),%0\;addq $8,sp\";
265: return \"loads %1,%0\"; /* m -> f */
266: }
267:
268: if (FP_REG_P (operands[1]))
269: {
270: if (GET_CODE (operands[0]) == REG) /* f -> r */
271: return
272: \"subq $8,sp\;stors %1,(sp)\;loadw (sp),%0\;addq $8,sp\";
273: abort ();
274: }
275:
276: if (GET_CODE (operands[1]) == MEM) /* m -> r */
277: return \"loadw %1,%0\";
278:
279: if (GET_CODE (operands[1]) == REG) /* r -> r */
280: return \"movw %1,%0\";
281:
282: abort ();
283: #undef FP_REG_P
284: }")
285:
286: (define_insn ""
287: [(set (match_operand:SF 0 "memory_operand" "=m")
288: (match_operand:SF 1 "register_operand" "rf"))]
289: ""
290: "*
291: {
292: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) >= 16)
293: return \"stors %1,%0\"; /* f-> m */
294:
295: return \"storw %1,%0\"; /* r -> m */
296: }"
297: [(set_attr "type" "store")])
298:
299:
300: (define_expand "movdi"
301: [(set (match_operand:DI 0 "general_operand" "")
302: (match_operand:DI 1 "general_operand" ""))]
303: ""
304: "
305: {
306: if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) != REG)
307: operands[1] = force_reg (DImode, operands[1]);
308: }")
309:
310: (define_insn ""
311: [(set (match_operand:DI 0 "register_operand" "=r,r,r")
312: (match_operand:DI 1 "general_operand" "r,n,o"))]
313: ""
314: "*
315: {
316: rtx xoperands[2],yoperands[2];
317:
318: xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
319:
320: if (which_alternative == 0) /* r -> r */
321: {
322: output_asm_insn (\"movw %1,%0\", operands);
323: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
324: output_asm_insn (\"movw %1,%0\", xoperands);
325: return \"\";
326: }
327:
328: if (which_alternative == 1) /* n -> r */
329: {
330: if (GET_CODE (operands[1]) == CONST_INT)
331: {
332: output_asm_insn (\"loadi %1,%0\", operands);
333: output_asm_insn (\"loadq $0,%0\", xoperands);
334: return \"\";
335: }
336:
337: if (GET_CODE (operands[1]) != CONST_DOUBLE)
338: abort ();
339:
340: yoperands[0] = operands[0];
341: yoperands[1] = gen_rtx (CONST_INT, VOIDmode,
342: CONST_DOUBLE_LOW (operands[1]));
343: output_asm_insn (\"loadi %1,%0\", yoperands);
344:
345: xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
346: CONST_DOUBLE_HIGH (operands[1]));
347: output_asm_insn (\"loadi %1,%0\", xoperands);
348: return \"\";
349: }
350: /* m -> r */
351: output_asm_insn (\"loadw %1,%0\", operands);
352: xoperands[1] = adj_offsettable_operand (operands[1], 4);
353: output_asm_insn (\"loadw %1,%0\", xoperands);
354: return \"\";
355: }"
356: [(set_attr "type" "arith,arith,load")
357: (set_attr "cc" "clobber,clobber,clobber")])
358:
359: (define_insn ""
360: [(set (match_operand:DI 0 "memory_operand" "=o")
361: (match_operand:DI 1 "register_operand" "r"))]
362: ""
363: "*
364: {
365: rtx xops[4];
366: xops[0] = operands[0];
367: xops[1] = adj_offsettable_operand (operands[0], 4);
368: xops[2] = operands[1];
369: xops[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
370: output_asm_insn (\"storw %2,%0\;storw %3,%1\", xops);
371: return \"\";
372: }"
373: [(set_attr "type" "store")
374: (set_attr "cc" "clobber")])
375:
376: (define_expand "movsi"
377: [(set (match_operand:SI 0 "general_operand" "")
378: (match_operand:SI 1 "general_operand" ""))]
379: ""
380: "
381: {
382: if (GET_CODE (operands[0]) == MEM &&
383: GET_CODE (operands[1]) != REG)
384: operands[1] = force_reg (SImode, operands[1]);
385: }")
386:
387: ;; provide 2 patterns with different predicates as 'general_operand' in both
388: ;; positions results in a 'mem -> mem' move from combine that must be reloaded
389: ;;
390:
391: (define_insn ""
392: [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
393: (match_operand:SI 1 "general_operand" "r,m,n,i"))]
394: ""
395: "*
396: {
397: int val;
398:
399: if (which_alternative == 0)
400: return \"movw %1,%0\"; /* reg -> reg */
401:
402: if (which_alternative == 1)
403: return \"loadw %1,%0\"; /* mem -> reg */
404:
405: if (which_alternative == 2)
406: {
407: val = INTVAL (operands[1]); /* known const ->reg */
408:
409: if (val == -1)
410: return \"notq $0,%0\";
411:
412: if (val < 0 || val >= 16)
413: return \"loadi %1,%0\";
414:
415: return \"loadq %1,%0\";
416: }
417:
418: if (which_alternative == 3) /* unknown const */
419: return \"loada %a1,%0\";
420: }"
421: [(set_attr "type" "arith,load,arith,load")
422: (set_attr "cc" "set2,change0,set1,change0")])
423:
424:
425: (define_insn ""
426: [(set (match_operand:SI 0 "memory_operand" "=m")
427: (match_operand:SI 1 "int_reg_operand" "r"))]
428: ""
429: "storw %1,%0"
430: [(set_attr "type" "store")])
431:
432: ;; movhi
433: ;;
434: ;; loadh mem to reg
435: ;; storh reg to mem
436: ;;
437: ;;
438: (define_expand "movhi"
439: [(set (match_operand:HI 0 "general_operand" "")
440: (match_operand:HI 1 "general_operand" ""))]
441: ""
442: "
443: {
444: if (GET_CODE (operands[0]) == MEM
445: && ! register_operand (operands[1], HImode))
446: operands[1] = force_reg (HImode, operands[1]);
447: }")
448:
449:
450: (define_insn ""
451: [(set (match_operand:HI 0 "register_operand" "=r,r,r")
452: (match_operand:HI 1 "general_operand" "r,m,n"))]
453: ""
454: "@
455: movw %1,%0
456: loadh %1,%0
457: loadi %1,%0"
458: [(set_attr "type" "arith,load,arith")])
459:
460: (define_insn ""
461: [(set (match_operand:HI 0 "memory_operand" "=m")
462: (match_operand:HI 1 "register_operand" "r"))]
463: ""
464: "storh %1,%0"
465: [(set_attr "type" "store")])
466:
467: ;; movqi
468: ;;
469: ;; loadb mem to reg
470: ;; storb reg to mem
471: ;;
472: (define_expand "movqi"
473: [(set (match_operand:QI 0 "general_operand" "")
474: (match_operand:QI 1 "general_operand" ""))]
475: ""
476: "
477: {
478: if (GET_CODE (operands[0]) == MEM &&
479: ! register_operand (operands[1], QImode))
480: operands[1] = force_reg (QImode, operands[1]);
481: }")
482:
483:
484: (define_insn ""
485: [(set (match_operand:QI 0 "register_operand" "=r,r,r")
486: (match_operand:QI 1 "general_operand" "r,m,n"))]
487: ""
488: "@
489: movw %1,%0
490: loadb %1,%0
491: loadi %1,%0"
492: [(set_attr "type" "arith,load,arith")])
493:
494: (define_insn ""
495: [(set (match_operand:QI 0 "memory_operand" "=m")
496: (match_operand:QI 1 "register_operand" "r"))]
497: ""
498: "storb %1,%0"
499: [(set_attr "type" "store")])
500:
501:
502: ;;
503: ;; block move
504: ;;
505: (define_expand "movstrsi"
506: [(parallel
507: [(set (match_operand:BLK 0 "memory_operand" "")
508: (match_operand:BLK 1 "memory_operand" ""))
509: (use (match_operand:SI 2 "general_operand" ""))
510: (use (match_operand:SI 3 "const_int_operand" ""))
511: (clobber (match_scratch:SI 4 ""))
512: (clobber (match_scratch:SI 5 ""))
513: (clobber (match_dup 6))
514: (clobber (match_dup 7))])]
515: ""
516: "
517: {
518: rtx addr0, addr1;
519:
520: addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
521: addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
522:
523: operands[6] = addr0;
524: operands[7] = addr1;
525:
526: operands[0] = gen_rtx (MEM, BLKmode, addr0);
527: operands[1] = gen_rtx (MEM, BLKmode, addr1);
528:
529: if (GET_CODE (operands[2]) != CONST_INT)
530: operands[2] = force_reg (SImode, operands[2]);
531: }")
532:
533: ;;
534: ;; there is a problem with this insn in gcc-2.2.3
535: ;; (clobber (match_dup 2)) does not prevent use of this operand later
536: ;; we always use a scratch register and leave operand 2 unchanged
537: ;;
538: (define_insn ""
539: [(set (mem:BLK (match_operand:SI 0 "register_operand" "r"))
540: (mem:BLK (match_operand:SI 1 "register_operand" "r")))
541: (use (match_operand:SI 2 "nonmemory_operand" "rn"))
542: (use (match_operand:SI 3 "const_int_operand" "n"))
543: (clobber (match_scratch:SI 4 "=r"))
544: (clobber (match_scratch:SI 5 "=r"))
545: (clobber (match_dup 0))
546: (clobber (match_dup 1))]
547: ""
548: "*
549: {
550: extern void clipper_movstr ();
551: clipper_movstr (operands);
552: return \"\";
553: }"
554: [(set_attr "cc" "clobber")])
555:
556:
557:
558: ;; Extension and truncation insns.
559: (define_insn "extendhisi2"
560: [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
561: (sign_extend:SI (match_operand:HI 1 "general_operand" "0,m")))]
562: ""
563: "@
564: andi $65535,%0\;xori $32768,%0\;subi $32768,%0
565: loadh %1,%0"
566: [(set_attr "type" "arith,load")])
567:
568:
569: (define_insn "extendqihi2"
570: [(set (match_operand:HI 0 "int_reg_operand" "=r,r")
571: (sign_extend:HI (match_operand:QI 1 "general_operand" "0,m")))]
572: ""
573: "@
574: andi $255,%0\;xori $128,%0\;subi $128,%0
575: loadb %1,%0"
576: [(set_attr "type" "arith,load")
577: (set_attr "cc" "set1,change0")])
578:
579:
580: (define_insn "extendqisi2"
581: [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
582: (sign_extend:SI (match_operand:QI 1 "general_operand" "0,m")))]
583: ""
584: "@
585: andi $255,%0\;xori $128,%0\;subi $128,%0
586: loadb %1,%0"
587: [(set_attr "type" "arith,load")])
588:
589:
590: (define_insn "extendsfdf2"
591: [(set (match_operand:DF 0 "fp_reg_operand" "=f")
592: (float_extend:DF (match_operand:SF 1 "fp_reg_operand" "f")))]
593: ""
594: "cnvsd %1,%0")
595:
596: (define_insn "truncdfsf2"
597: [(set (match_operand:SF 0 "fp_reg_operand" "=f")
598: (float_truncate:SF (match_operand:DF 1 "fp_reg_operand" "f")))]
599: ""
600: "cnvds %1,%0")
601:
602: (define_insn "zero_extendhisi2"
603: [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
604: (zero_extend:SI (match_operand:HI 1 "general_operand" "0,m")))]
605: ""
606: "@
607: andi $65535,%0
608: loadhu %1,%0"
609: [(set_attr "type" "arith,load")])
610:
611:
612: (define_insn "zero_extendqihi2"
613: [(set (match_operand:HI 0 "int_reg_operand" "=r,r")
614: (zero_extend:HI (match_operand:QI 1 "general_operand" "0,m")))]
615: ""
616: "@
617: andi $255,%0
618: loadbu %1,%0"
619: [(set_attr "type" "arith,load")
620: (set_attr "cc" "clobber,clobber")])
621:
622:
623: (define_insn "zero_extendqisi2"
624: [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
625: (zero_extend:SI (match_operand:QI 1 "general_operand" "0,m")))]
626: ""
627: "@
628: andi $255,%0
629: loadbu %1,%0"
630: [(set_attr "type" "arith,load")])
631:
632:
633:
634: ;; Fix-to-float conversion insns.
635:
636: (define_insn "floatsisf2"
637: [(set (match_operand:SF 0 "fp_reg_operand" "=f")
638: (float:SF (match_operand:SI 1 "int_reg_operand" "r")))]
639: ""
640: "cnvws %1,%0")
641:
642: (define_insn "floatsidf2"
643: [(set (match_operand:DF 0 "fp_reg_operand" "=f")
644: (float:DF (match_operand:SI 1 "int_reg_operand" "r")))]
645: ""
646: "cnvwd %1,%0")
647:
648:
649: ;; Float-to-fix conversion insns.
650:
651: (define_insn "fix_truncsfsi2"
652: [(set (match_operand:SI 0 "int_reg_operand" "=r")
653: (fix:SI (fix:SF (match_operand:SF 1 "fp_reg_operand" "f"))))]
654: ""
655: "cnvtsw %1,%0")
656:
657: (define_insn "fix_truncdfsi2"
658: [(set (match_operand:SI 0 "int_reg_operand" "=r")
659: (fix:SI (fix:DF (match_operand:DF 1 "fp_reg_operand" "f"))))]
660: ""
661: "cnvtdw %1,%0")
662:
663: ;;- All kinds of add instructions.
664:
665: (define_insn "adddf3"
666: [(set (match_operand:DF 0 "fp_reg_operand" "=f")
667: (plus:DF (match_operand:DF 1 "fp_reg_operand" "0")
668: (match_operand:DF 2 "fp_reg_operand" "f")))]
669: ""
670: "addd %2,%0"
671: [(set_attr "type" "fp")])
672:
673:
674: (define_insn "addsf3"
675: [(set (match_operand:SF 0 "fp_reg_operand" "=f")
676: (plus:SF (match_operand:SF 1 "fp_reg_operand" "0")
677: (match_operand:SF 2 "fp_reg_operand" "f")))]
678: ""
679: "adds %2,%0"
680: [(set_attr "type" "fp")])
681:
682: (define_insn "adddi3"
683: [(set (match_operand:DI 0 "int_reg_operand" "=r")
684: (plus:DI (match_operand:DI 1 "int_reg_operand" "%0")
685: (match_operand:DI 2 "int_reg_operand" "r")))]
686: ""
687: "*
688: {
689: rtx xoperands[4];
690:
691: xoperands[0] = operands[0];
692: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
693: xoperands[2] = operands[2];
694: xoperands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
695: output_asm_insn (\"addw %2,%0\;addwc %3,%1\", xoperands);
696: return \"\";
697: }"
698: [(set_attr "type" "arith")
699: (set_attr "cc" "clobber")])
700:
701: (define_insn "addsi3"
702: [(set (match_operand:SI 0 "int_reg_operand" "=r,r,r")
703: (plus:SI (match_operand:SI 1 "int_reg_operand" "%0,r,r")
704: (match_operand:SI 2 "nonmemory_operand" "rn,0,rn")))]
705: ""
706: "*
707: {
708: if (which_alternative == 2) /* 3 address version */
709: {
710: if (GET_CODE (operands[2]) == CONST_INT)
711: return \"loada %a2(%1),%0\";
712: return \"loada [%2](%1),%0\";
713: }
714: /* 2 address version */
715: if (GET_CODE (operands[2]) == CONST_INT)
716: {
717: int val = INTVAL (operands[2]);
718:
719: if (val >= 16 || val == 0x80000000)
720: return \"addi %2,%0\";
721:
722: if (val < 0) /* change to sub */
723: {
724: rtx xops[2];
725:
726: val = -val;
727:
728: xops[0] = operands[0];
729: xops[1] = gen_rtx (CONST_INT, VOIDmode, val);
730:
731: if (val >= 16)
732: output_asm_insn (\"subi %1,%0\", xops);
733: else
734: output_asm_insn (\"subq %1,%0\", xops);
735:
736: return \"\";
737: }
738:
739: return \"addq %2,%0\";
740: }
741:
742: if (which_alternative == 0)
743: return \"addw %2,%0\";
744:
745: return \"addw %1,%0\";
746: }"
747: [(set_attr "type" "arith,arith,arith")
748: (set_attr "cc" "set1,set1,change0")])
749:
750:
751: ;;- All kinds of subtract instructions.
752:
753: (define_insn "subdi3"
754: [(set (match_operand:DI 0 "int_reg_operand" "=r")
755: (minus:DI (match_operand:DI 1 "int_reg_operand" "%0")
756: (match_operand:DI 2 "int_reg_operand" "r")))]
757: ""
758: "*
759: {
760: rtx xoperands[4];
761:
762: xoperands[0] = operands[0];
763: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
764: xoperands[2] = operands[2];
765: xoperands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
766: output_asm_insn (\"subw %2,%0\;subwc %3,%1\", xoperands);
767: return \"\";
768: }"
769: [(set_attr "type" "arith")
770: (set_attr "cc" "clobber")])
771:
772: (define_insn "subsi3"
773: [(set (match_operand:SI 0 "int_reg_operand" "=r")
774: (minus:SI (match_operand:SI 1 "int_reg_operand" "0")
775: (match_operand:SI 2 "nonmemory_operand" "rn")))]
776: ""
777: "*
778: {
779: if (GET_CODE (operands[2]) == CONST_INT)
780: {
781: int val = INTVAL (operands[2]);
782:
783: if (val < 0 || val >= 16)
784: return \"subi %2,%0\";
785: else
786: return \"subq %2,%0\";
787: }
788:
789: return \"subw %2,%0\";
790: }"
791: [(set_attr "type" "arith")])
792:
793: (define_insn "subdf3"
794: [(set (match_operand:DF 0 "fp_reg_operand" "=f")
795: (minus:DF (match_operand:DF 1 "fp_reg_operand" "0")
796: (match_operand:DF 2 "fp_reg_operand" "f")))]
797: ""
798: "subd %2,%0"
799: [(set_attr "type" "fp")])
800:
801: (define_insn "subsf3"
802: [(set (match_operand:SF 0 "fp_reg_operand" "=f")
803: (minus:SF (match_operand:SF 1 "fp_reg_operand" "0")
804: (match_operand:SF 2 "fp_reg_operand" "f")))]
805: ""
806: "subs %2,%0"
807: [(set_attr "type" "fp")])
808:
809:
810: ;;- Multiply instructions.
811:
812: (define_insn "muldf3"
813: [(set (match_operand:DF 0 "fp_reg_operand" "=f")
814: (mult:DF (match_operand:DF 1 "fp_reg_operand" "0")
815: (match_operand:DF 2 "fp_reg_operand" "f")))]
816: ""
817: "muld %2,%0"
818: [(set_attr "type" "fp")])
819:
820: (define_insn "mulsf3"
821: [(set (match_operand:SF 0 "fp_reg_operand" "=f")
822: (mult:SF (match_operand:SF 1 "fp_reg_operand" "0")
823: (match_operand:SF 2 "fp_reg_operand" "f")))]
824: ""
825: "muls %2,%0"
826: [(set_attr "type" "fp")])
827:
828: (define_insn "mulsidi3"
829: [(set (match_operand:DI 0 "int_reg_operand" "=r")
830: (mult:DI (sign_extend:DI (match_operand:SI 1 "int_reg_operand" "%0"))
831: (sign_extend:DI (match_operand:SI 2 "int_reg_operand" "r"))))]
832: ""
833: "mulwx %2,%0"
834: [(set_attr "type" "arith")
835: (set_attr "cc" "clobber")])
836:
837: (define_insn "umulsidi3"
838: [(set (match_operand:DI 0 "int_reg_operand" "=r")
839: (mult:DI (zero_extend:DI (match_operand:SI 1 "int_reg_operand" "%0"))
840: (zero_extend:DI (match_operand:SI 2 "int_reg_operand" "r"))))]
841: ""
842: "mulwux %2,%0"
843: [(set_attr "type" "arith")
844: (set_attr "cc" "clobber")])
845:
846: (define_insn "mulsi3"
847: [(set (match_operand:SI 0 "int_reg_operand" "=r")
848: (mult:SI (match_operand:SI 1 "int_reg_operand" "%0")
849: (match_operand:SI 2 "int_reg_operand" "r")))]
850: ""
851: "mulw %2,%0"
852: [(set_attr "type" "arith")
853: (set_attr "cc" "clobber")])
854:
855:
856: ;;- Divide and mod instructions.
857:
858: (define_insn "divdf3"
859: [(set (match_operand:DF 0 "fp_reg_operand" "=f")
860: (div:DF (match_operand:DF 1 "fp_reg_operand" "0")
861: (match_operand:DF 2 "fp_reg_operand" "f")))]
862: ""
863: "divd %2,%0"
864: [(set_attr "type" "fp")])
865:
866: (define_insn "divsf3"
867: [(set (match_operand:SF 0 "fp_reg_operand" "=f")
868: (div:SF (match_operand:SF 1 "fp_reg_operand" "0")
869: (match_operand:SF 2 "fp_reg_operand" "f")))]
870: ""
871: "divs %2,%0"
872: [(set_attr "type" "fp")])
873:
874: (define_insn "divsi3"
875: [(set (match_operand:SI 0 "int_reg_operand" "=r")
876: (div:SI (match_operand:SI 1 "int_reg_operand" "0")
877: (match_operand:SI 2 "int_reg_operand" "r")))]
878: ""
879: "divw %2,%0"
880: [(set_attr "type" "arith")
881: (set_attr "cc" "clobber")])
882:
883: (define_insn "udivsi3"
884: [(set (match_operand:SI 0 "int_reg_operand" "=r")
885: (udiv:SI (match_operand:SI 1 "int_reg_operand" "0")
886: (match_operand:SI 2 "int_reg_operand" "r")))]
887: ""
888: "divwu %2,%0"
889: [(set_attr "type" "arith")
890: (set_attr "cc" "clobber")])
891:
892:
893: (define_insn "modsi3"
894: [(set (match_operand:SI 0 "int_reg_operand" "=r")
895: (mod:SI (match_operand:SI 1 "int_reg_operand" "0")
896: (match_operand:SI 2 "int_reg_operand" "r")))]
897: ""
898: "modw %2,%0"
899: [(set_attr "type" "arith")
900: (set_attr "cc" "clobber")])
901:
902: (define_insn "umodsi3"
903: [(set (match_operand:SI 0 "int_reg_operand" "=r")
904: (umod:SI (match_operand:SI 1 "int_reg_operand" "0")
905: (match_operand:SI 2 "int_reg_operand" "r")))]
906: ""
907: "modwu %2,%0"
908: [(set_attr "type" "arith")
909: (set_attr "cc" "clobber")])
910:
911: ;;
912: ;; bit and/or instructions
913: ;;
914: (define_insn "andsi3"
915: [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
916: (and:SI (match_operand:SI 1 "int_reg_operand" "%0,0")
917: (match_operand:SI 2 "nonmemory_operand" "r,n")))]
918: ""
919: "@
920: andw %2,%0
921: andi %2,%0"
922: [(set_attr "type" "arith")])
923:
924: (define_insn "iorsi3"
925: [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
926: (ior:SI (match_operand:SI 1 "int_reg_operand" "%0,0")
927: (match_operand:SI 2 "nonmemory_operand" "r,n")))]
928: ""
929: "@
930: orw %2,%0
931: ori %2,%0"
932: [(set_attr "type" "arith")])
933:
934: (define_insn "xorsi3"
935: [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
936: (xor:SI (match_operand:SI 1 "int_reg_operand" "%0,0")
937: (match_operand:SI 2 "nonmemory_operand" "r,n")))]
938: ""
939: "@
940: xorw %2,%0
941: xori %2,%0"
942: [(set_attr "type" "arith")])
943:
944: (define_insn "negdf2"
945: [(set (match_operand:DF 0 "fp_reg_operand" "=f")
946: (neg:DF (match_operand:DF 1 "fp_reg_operand" "f")))]
947: ""
948: "negd %1,%0"
949: [(set_attr "type" "fp")])
950:
951: (define_insn "negsf2"
952: [(set (match_operand:SF 0 "fp_reg_operand" "=f")
953: (neg:SF (match_operand:SF 1 "fp_reg_operand" "f")))]
954: ""
955: "negs %1,%0"
956: [(set_attr "type" "fp")])
957:
958: (define_insn "negsi2"
959: [(set (match_operand:SI 0 "int_reg_operand" "=r")
960: (neg:SI (match_operand:SI 1 "int_reg_operand" "r")))]
961: ""
962: "negw %1,%0"
963: [(set_attr "type" "arith")])
964:
965:
966: (define_insn "one_cmplsi2"
967: [(set (match_operand:SI 0 "int_reg_operand" "=r")
968: (not:SI (match_operand:SI 1 "int_reg_operand" "r")))]
969: ""
970: "notw %1,%0"
971: [(set_attr "type" "arith")])
972:
973:
974:
975: ;; Right shift on the clipper works by negating the shift count,
976: ;; then emitting a right shift with the shift count negated. This means
977: ;; that all actual shift counts in the RTL will be positive.
978:
979: (define_expand "ashrdi3"
980: [(set (match_operand:DI 0 "int_reg_operand" "")
981: (ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "")
982: (match_operand:SI 2 "nonmemory_operand" "")))]
983: ""
984: "
985: {
986: if (GET_CODE (operands[2]) != CONST_INT)
987: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
988: }")
989:
990: (define_insn ""
991: [(set (match_operand:DI 0 "int_reg_operand" "=r")
992: (ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
993: (match_operand:SI 2 "const_int_operand" "n")))]
994: ""
995: "shali $%n2,%0"
996: [(set_attr "type" "arith")])
997:
998: (define_insn ""
999: [(set (match_operand:DI 0 "int_reg_operand" "=r")
1000: (ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
1001: (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
1002: ""
1003: "shal %2,%0"
1004: [(set_attr "type" "arith")])
1005:
1006: (define_expand "ashrsi3"
1007: [(set (match_operand:SI 0 "int_reg_operand" "")
1008: (ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "")
1009: (match_operand:SI 2 "nonmemory_operand" "")))]
1010: ""
1011: "
1012: {
1013: if (GET_CODE (operands[2]) != CONST_INT)
1014: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1015: }")
1016:
1017: (define_insn ""
1018: [(set (match_operand:SI 0 "int_reg_operand" "=r")
1019: (ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "0")
1020: (match_operand:SI 2 "const_int_operand" "n")))]
1021: ""
1022: "shai $%n2,%0"
1023: [(set_attr "type" "arith")])
1024:
1025: (define_insn ""
1026: [(set (match_operand:SI 0 "int_reg_operand" "=r")
1027: (ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "0")
1028: (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
1029: ""
1030: "shaw %2,%0"
1031: [(set_attr "type" "arith")])
1032:
1033: ;;
1034: ;; left shift
1035: ;;
1036:
1037: (define_insn "ashldi3"
1038: [(set (match_operand:DI 0 "int_reg_operand" "=r,r")
1039: (ashift:DI (match_operand:DI 1 "int_reg_operand" "0,0")
1040: (match_operand:SI 2 "nonmemory_operand" "r,n")))]
1041: ""
1042: "@
1043: shal %2,%0
1044: shali %2,%0"
1045: [(set_attr "type" "arith")])
1046:
1047:
1048: (define_insn "ashlsi3"
1049: [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
1050: (ashift:SI (match_operand:SI 1 "int_reg_operand" "0,0")
1051: (match_operand:SI 2 "nonmemory_operand" "r,n")))]
1052: ""
1053: "*
1054: {
1055: int val;
1056:
1057: if (which_alternative == 0)
1058: return \"shaw %2,%0\";
1059:
1060: val = INTVAL (operands[2]);
1061:
1062: if (val == 2)
1063: return \"addw %0,%0\;addw %0,%0\";
1064:
1065: if (val == 1)
1066: return \"addw %0,%0\";
1067:
1068: return \"shai %2,%0\";
1069: }"
1070: [(set_attr "type" "arith")])
1071:
1072: ;;
1073: ;; logical shift
1074: ;;
1075:
1076: (define_expand "lshrdi3"
1077: [(set (match_operand:DI 0 "int_reg_operand" "")
1078: (lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "")
1079: (match_operand:SI 2 "nonmemory_operand" "")))]
1080: ""
1081: "
1082: {
1083: if (GET_CODE (operands[2]) != CONST_INT)
1084: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1085: }")
1086:
1087: (define_insn ""
1088: [(set (match_operand:DI 0 "int_reg_operand" "=r")
1089: (lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
1090: (match_operand:SI 2 "const_int_operand" "n")))]
1091: ""
1092: "shlli $%n2,%0"
1093: [(set_attr "type" "arith")])
1094:
1095: (define_insn ""
1096: [(set (match_operand:DI 0 "int_reg_operand" "=r")
1097: (lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "0")
1098: (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
1099: ""
1100: "shll %2,%0"
1101: [(set_attr "type" "arith")])
1102:
1103: (define_expand "lshrsi3"
1104: [(set (match_operand:SI 0 "int_reg_operand" "")
1105: (lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "")
1106: (match_operand:SI 2 "nonmemory_operand" "")))]
1107: ""
1108: "
1109: {
1110: if (GET_CODE (operands[2]) != CONST_INT)
1111: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1112: }")
1113:
1114: (define_insn ""
1115: [(set (match_operand:SI 0 "int_reg_operand" "=r")
1116: (lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "0")
1117: (match_operand:SI 2 "const_int_operand" "n")))]
1118: ""
1119: "shli $%n2,%0"
1120: [(set_attr "type" "arith")])
1121:
1122: (define_insn ""
1123: [(set (match_operand:SI 0 "int_reg_operand" "=r")
1124: (lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "0")
1125: (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
1126: ""
1127: "shlw %2,%0"
1128: [(set_attr "type" "arith")])
1129:
1130: (define_insn "lshldi3"
1131: [(set (match_operand:DI 0 "int_reg_operand" "=r,r")
1132: (lshift:DI (match_operand:DI 1 "int_reg_operand" "0,0")
1133: (match_operand:SI 2 "nonmemory_operand" "r,n")))]
1134: ""
1135: "@
1136: shll %2,%0
1137: shlli %2,%0"
1138: [(set_attr "type" "arith")])
1139:
1140: (define_insn "lshlsi3"
1141: [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
1142: (lshift:SI (match_operand:SI 1 "int_reg_operand" "0,0")
1143: (match_operand:SI 2 "nonmemory_operand" "r,n")))]
1144: ""
1145: "@
1146: shlw %2,%0
1147: shli %2,%0"
1148: [(set_attr "type" "arith")])
1149:
1150: ;;
1151: ;; rotate insn
1152: ;;
1153: (define_expand "rotrdi3"
1154: [(set (match_operand:DI 0 "int_reg_operand" "")
1155: (rotatert:DI (match_operand:DI 1 "int_reg_operand" "")
1156: (match_operand:SI 2 "nonmemory_operand" "")))]
1157: ""
1158: "
1159: {
1160: if (GET_CODE (operands[2]) != CONST_INT)
1161: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1162: }")
1163:
1164: (define_insn ""
1165: [(set (match_operand:DI 0 "int_reg_operand" "=r")
1166: (rotatert:DI (match_operand:DI 1 "int_reg_operand" "0")
1167: (match_operand:SI 2 "const_int_operand" "n")))]
1168: ""
1169: "rotli $%n2,%0"
1170: [(set_attr "type" "arith")])
1171:
1172: (define_insn ""
1173: [(set (match_operand:DI 0 "int_reg_operand" "=r")
1174: (rotatert:DI (match_operand:DI 1 "int_reg_operand" "0")
1175: (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
1176: ""
1177: "rotl %2,%0"
1178: [(set_attr "type" "arith")])
1179:
1180: (define_expand "rotrsi3"
1181: [(set (match_operand:SI 0 "int_reg_operand" "")
1182: (rotatert:SI (match_operand:SI 1 "int_reg_operand" "")
1183: (match_operand:SI 2 "nonmemory_operand" "")))]
1184: ""
1185: "
1186: {
1187: if (GET_CODE (operands[2]) != CONST_INT)
1188: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1189: }")
1190:
1191: (define_insn ""
1192: [(set (match_operand:SI 0 "int_reg_operand" "=r")
1193: (rotatert:SI (match_operand:SI 1 "int_reg_operand" "0")
1194: (match_operand:SI 2 "const_int_operand" "n")))]
1195: ""
1196: "roti $%n2,%0"
1197: [(set_attr "type" "arith")])
1198:
1199: (define_insn ""
1200: [(set (match_operand:SI 0 "int_reg_operand" "=r")
1201: (rotatert:SI (match_operand:SI 1 "int_reg_operand" "0")
1202: (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))]
1203: ""
1204: "rotw %2,%0"
1205: [(set_attr "type" "arith")])
1206:
1207: (define_insn "rotldi3"
1208: [(set (match_operand:DI 0 "int_reg_operand" "=r,r")
1209: (rotate:DI (match_operand:DI 1 "int_reg_operand" "0,0")
1210: (match_operand:SI 2 "nonmemory_operand" "r,n")))]
1211: ""
1212: "@
1213: rotl %2,%0
1214: rotli %2,%0"
1215: [(set_attr "type" "arith")])
1216:
1217: (define_insn "rotlsi3"
1218: [(set (match_operand:SI 0 "int_reg_operand" "=r,r")
1219: (rotate:SI (match_operand:SI 1 "int_reg_operand" "0,0")
1220: (match_operand:SI 2 "nonmemory_operand" "r,n")))]
1221: ""
1222: "@
1223: rotw %2,%0
1224: roti %2,%0"
1225: [(set_attr "type" "arith")])
1226:
1227:
1228: ;;
1229: ;; jump and branch insns
1230: ;;
1231: (define_insn "jump"
1232: [(set (pc)
1233: (label_ref (match_operand 0 "" "")))]
1234: ""
1235: "b %l0"
1236: [(set_attr "type" "branch")])
1237:
1238: (define_insn "tablejump"
1239: [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1240: (use (label_ref (match_operand 1 "" "")))]
1241: ""
1242: "b (%0)"
1243: [(set_attr "type" "branch")])
1244:
1245: (define_insn "beq"
1246: [(set (pc)
1247: (if_then_else (eq (cc0)
1248: (const_int 0))
1249: (label_ref (match_operand 0 "" ""))
1250: (pc)))]
1251: ""
1252: "breq %l0"
1253: [(set_attr "type" "branch")])
1254:
1255: (define_insn "bne"
1256: [(set (pc)
1257: (if_then_else (ne (cc0)
1258: (const_int 0))
1259: (label_ref (match_operand 0 "" ""))
1260: (pc)))]
1261: ""
1262: "brne %l0"
1263: [(set_attr "type" "branch")])
1264:
1265: (define_insn "bgt"
1266: [(set (pc)
1267: (if_then_else (gt (cc0)
1268: (const_int 0))
1269: (label_ref (match_operand 0 "" ""))
1270: (pc)))]
1271: ""
1272: "brgt %l0"
1273: [(set_attr "type" "branch")])
1274:
1275: (define_insn "bgtu"
1276: [(set (pc)
1277: (if_then_else (gtu (cc0)
1278: (const_int 0))
1279: (label_ref (match_operand 0 "" ""))
1280: (pc)))]
1281: ""
1282: "brgtu %l0"
1283: [(set_attr "type" "branch")])
1284:
1285: (define_insn "blt"
1286: [(set (pc)
1287: (if_then_else (lt (cc0)
1288: (const_int 0))
1289: (label_ref (match_operand 0 "" ""))
1290: (pc)))]
1291: ""
1292: "brlt %l0"
1293: [(set_attr "type" "branch")])
1294:
1295: (define_insn "bltu"
1296: [(set (pc)
1297: (if_then_else (ltu (cc0)
1298: (const_int 0))
1299: (label_ref (match_operand 0 "" ""))
1300: (pc)))]
1301: ""
1302: "brltu %l0"
1303: [(set_attr "type" "branch")])
1304:
1305: (define_insn "bge"
1306: [(set (pc)
1307: (if_then_else (ge (cc0)
1308: (const_int 0))
1309: (label_ref (match_operand 0 "" ""))
1310: (pc)))]
1311: ""
1312: "brge %l0"
1313: [(set_attr "type" "branch")])
1314:
1315: (define_insn "bgeu"
1316: [(set (pc)
1317: (if_then_else (geu (cc0)
1318: (const_int 0))
1319: (label_ref (match_operand 0 "" ""))
1320: (pc)))]
1321: ""
1322: "brgeu %l0"
1323: [(set_attr "type" "branch")])
1324:
1325: (define_insn "ble"
1326: [(set (pc)
1327: (if_then_else (le (cc0)
1328: (const_int 0))
1329: (label_ref (match_operand 0 "" ""))
1330: (pc)))]
1331: ""
1332: "brle %l0"
1333: [(set_attr "type" "branch")])
1334:
1335: (define_insn "bleu"
1336: [(set (pc)
1337: (if_then_else (leu (cc0)
1338: (const_int 0))
1339: (label_ref (match_operand 0 "" ""))
1340: (pc)))]
1341: ""
1342: "brleu %l0"
1343: [(set_attr "type" "branch")])
1344:
1345: ;; Recognize reversed jumps.
1346: (define_insn ""
1347: [(set (pc)
1348: (if_then_else (match_operator 0 "comparison_operator"
1349: [(cc0)
1350: (const_int 0)])
1351: (pc)
1352: (label_ref (match_operand 1 "" ""))))]
1353: ""
1354: "br%C0 %l1" ; %C0 negates condition
1355: [(set_attr "type" "branch")])
1356:
1357: ;;
1358: ;; call instructions
1359: ;;
1360: (define_insn "call"
1361: [(call (match_operand:QI 0 "general_operand" "m")
1362: (match_operand:SI 1 "general_operand" ""))]
1363: ;; Operand 1 not used on the clipper.
1364: ""
1365: "call sp,%0")
1366:
1367: (define_insn "call_value"
1368: [(set (match_operand 0 "" "=rf")
1369: (call (match_operand:QI 1 "general_operand" "m")
1370: (match_operand:SI 2 "general_operand" "g")))]
1371: ;; Operand 2 not used on the clipper
1372: ""
1373: "call sp,%1")
1374:
1375: (define_insn "indirect_jump"
1376: [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
1377: ""
1378: "b (%0)"
1379: [(set_attr "type" "branch")])
1380:
1381:
1382: (define_insn "nop"
1383: [(const_int 0)]
1384: ""
1385: "noop"
1386: [(set_attr "type" "arith")
1387: (set_attr "cc" "unchanged")])
1388:
1389:
1390:
1391: ;; while (--foo >= 0)
1392: ;;
1393: ;; Combiners for 'decrement test and branch' do not work for clipper.
1394: ;; These patters are jump_insns that do not allow output reloads and clipper
1395: ;; can only decrement and test registers.
1396: ;;
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