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1.1 root 1: ;;- Machine description for GNU compiler, Clipper Version 1.1.1.3 ! root 2: ;; Copyright (C) 1987, 1988, 1991, 1993, 1994 Free Software Foundation, Inc. 1.1 root 3: ;; Contributed by Holger Teutsch ([email protected]) 4: 5: ;; This file is part of GNU CC. 6: 7: ;; GNU CC is free software; you can redistribute it and/or modify 8: ;; it under the terms of the GNU General Public License as published by 9: ;; the Free Software Foundation; either version 2, or (at your option) 10: ;; any later version. 11: 12: ;; GNU CC is distributed in the hope that it will be useful, 13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15: ;; GNU General Public License for more details. 16: 17: ;; You should have received a copy of the GNU General Public License 18: ;; along with GNU CC; see the file COPYING. If not, write to 19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 20: 21: 22: ;;- Instruction patterns. When multiple patterns apply, 23: ;;- the first one in the file is chosen. 24: ;;- 25: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 26: ;;- 27: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code 28: ;;- updates for most instructions. 29: 30: ;; 31: ;; define attributes 32: ;; 33: ;; instruction type 34: ;; 35: ;; unknown is temporary in order to generate 'cc clobber' until attribute 36: ;; assignment is consistent 37: ;; 38: (define_attr "type" "load,store,arith,fp,branch,unknown" 39: (const_string "unknown")) 40: 41: ;; condition code setting 42: ;; 43: ;; clobber destroyed 44: ;; unchanged 45: ;; set1 set cc_status.value1, e.g. sub r0,r1 46: ;; set2 set value1 and value2, e.g. mov r0,r1 47: ;; change0 may be side effect, i.e. load mem,r0 48: ;; 49: ;; note: loadi and loadq are 'arith' instructions that set the condition codes 50: ;; mul,div,mod do NOT set the condition codes 51: ;; 52: (define_attr "cc" "clobber,unchanged,set1,set2,change0" 53: (cond [(eq_attr "type" "load") (const_string "change0") 54: (eq_attr "type" "store,branch") (const_string "unchanged") 55: (eq_attr "type" "arith") (if_then_else (match_operand:SI 0 "" "") 56: (const_string "set1") 57: (const_string "clobber")) 58: ] 59: (const_string "clobber"))) 60: 61: ;; 62: ;; clipper seems to be a tradional risc processor 63: ;; we define a functional unit 'memory' 64: ;; 65: (define_function_unit "memory" 1 1 (eq_attr "type" "load") 4 0) 66: 67: 68: ;; We don't want to allow a constant operand for test insns because 69: ;; (set (cc0) (const_int foo)) has no mode information. Such insns will 70: ;; be folded while optimizing anyway. 71: 72: (define_insn "tstsi" 73: [(set (cc0) 74: (match_operand:SI 0 "int_reg_operand" "r"))] 75: "" 76: "cmpq $0,%0") 77: 78: (define_insn "cmpsi" 79: [(set (cc0) 80: (compare (match_operand:SI 0 "nonimmediate_operand" "r,r,n") 81: (match_operand:SI 1 "nonmemory_operand" "r,n,r")))] 82: "" 83: "* 84: { 85: int val; 86: 87: if (which_alternative == 0) 88: return \"cmpw %1,%0\"; 89: 90: if (which_alternative == 1) 91: { 92: val = INTVAL (operands[1]); 93: if (0 <= val && val < 16) 94: return \"cmpq %1,%0\"; 95: return \"cmpi %1,%0\"; 96: } 97: 98: cc_status.flags |= CC_REVERSED; /* immediate must be first */ 99: 100: val = INTVAL (operands[0]); 101: 102: if (0 <= val && val < 16) 103: return \"cmpq %0,%1\"; 104: 105: return \"cmpi %0,%1\"; 106: }") 107: 108: (define_insn "cmpdf" 109: [(set (cc0) 110: (compare (match_operand:DF 0 "fp_reg_operand" "f") 111: (match_operand:DF 1 "fp_reg_operand" "f")))] 112: "" 113: "cmpd %1,%0") 114: 115: (define_insn "cmpsf" 116: [(set (cc0) 117: (compare (match_operand:SF 0 "fp_reg_operand" "f") 118: (match_operand:SF 1 "fp_reg_operand" "f")))] 119: "" 120: "cmps %1,%0") 121: 122: 123: ;; 124: ;; double and single float move 125: ;; 126: (define_expand "movdf" 127: [(set (match_operand:DF 0 "general_operand" "") 128: (match_operand:DF 1 "general_operand" ""))] 129: "" 130: " 131: { 132: if (GET_CODE (operands[0]) == MEM) 133: { 134: if (GET_CODE (operands[1]) == CONST_DOUBLE) 135: operands[1] = force_reg (DFmode, 136: force_const_mem (DFmode, operands[1])); 137: else if (GET_CODE (operands[1]) != REG) 138: operands[1] = force_reg (DFmode, operands[1]); 139: } 140: 141: else if (GET_CODE (operands[1]) == CONST_DOUBLE) 142: operands[1] = force_const_mem (DFmode, operands[1]); 143: }") 144: 145: ;; 146: ;; provide two patterns with different predicates as we don't want combine 147: ;; to recombine a mem -> mem move 148: ;; 149: (define_insn "" 1.1.1.2 root 150: [(set (match_operand:DF 0 "register_operand" "=*rf") 151: (match_operand:DF 1 "nonimmediate_operand" "*rfo"))] 1.1 root 152: "" 153: "* 154: { 155: #define FP_REG_P(X) (GET_CODE (X) == REG && REGNO (X) >= 16) 156: 157: if (FP_REG_P (operands[0])) 158: { 159: if (FP_REG_P (operands[1])) /* f -> f */ 160: return \"movd %1,%0\"; 161: 162: if (GET_CODE (operands[1]) == REG) /* r -> f */ 163: return \"movld %1,%0\"; 164: 165: return \"loadd %1,%0\"; /* m -> f */ 166: } 167: 168: if (FP_REG_P (operands[1])) 169: { 170: if (GET_CODE (operands[0]) == REG) /* f -> r */ 171: return \"movdl %1,%0\"; 172: 173: abort (); 174: } 175: 176: if (GET_CODE (operands[1]) == MEM) /* m -> r */ 177: { 178: rtx xops[4]; 179: xops[0] = operands[0]; 180: xops[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 181: xops[2] = operands[1]; 182: xops[3] = adj_offsettable_operand (operands[1], 4); 183: output_asm_insn (\"loadw %2,%0\;loadw %3,%1\", xops); 184: return \"\"; 185: } 186: 187: if (GET_CODE (operands[1]) == REG) /* r -> r */ 188: { 189: rtx xops[4]; 190: xops[0] = operands[0]; 191: xops[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 192: xops[2] = operands[1]; 193: xops[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 194: output_asm_insn (\"movw %2,%0\;movw %3,%1\", xops); 195: return \"\"; 196: } 197: 198: abort (); 199: #undef FP_REG_P 200: }") 201: 202: 203: (define_insn "" 204: [(set (match_operand:DF 0 "memory_operand" "=o,m") 1.1.1.2 root 205: (match_operand:DF 1 "register_operand" "*rf,f"))] 1.1 root 206: "" 207: "* 208: { 1.1.1.2 root 209: rtx xops[4]; 210: 211: if (REGNO (operands[1]) >= 16) /* f -> m */ 212: return \"stord %1,%0\"; 1.1 root 213: 1.1.1.2 root 214: xops[0] = operands[0]; /* r -> o */ 215: xops[1] = adj_offsettable_operand (operands[0], 4); 216: xops[2] = operands[1]; 217: xops[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 218: output_asm_insn (\"storw %2,%0\;storw %3,%1\", xops); 219: return \"\"; 1.1 root 220: }" 221: [(set_attr "type" "store,store") 222: (set_attr "cc" "clobber,unchanged")]) 223: 224: 225: (define_expand "movsf" 226: [(set (match_operand:SF 0 "general_operand" "") 227: (match_operand:SF 1 "general_operand" ""))] 228: "" 229: " 230: { 231: if (GET_CODE (operands[0]) == MEM) 232: { 233: if (GET_CODE (operands[1]) == CONST_DOUBLE) 234: operands[1] = force_reg (SFmode, 235: force_const_mem (SFmode, operands[1])); 236: else if (GET_CODE (operands[1]) != REG) 237: operands[1] = force_reg (SFmode, operands[1]); 238: } 239: 240: else if (GET_CODE (operands[1]) == CONST_DOUBLE) 241: operands[1] = force_const_mem (SFmode, operands[1]); 242: }") 243: 244: ;; 245: ;; provide two patterns with different predicates as we don't want combine 246: ;; to recombine a mem -> mem move 247: ;; 248: (define_insn "" 1.1.1.2 root 249: [(set (match_operand:SF 0 "register_operand" "=*rf") 250: (match_operand:SF 1 "nonimmediate_operand" "*rfm"))] 1.1 root 251: "" 252: "* 253: { 254: #define FP_REG_P(X) (GET_CODE (X) == REG && REGNO (X) >= 16) 255: 256: if (FP_REG_P (operands[0])) 257: { 258: if (FP_REG_P (operands[1])) /* f -> f */ 259: return \"movs %1,%0\"; 260: if (GET_CODE (operands[1]) == REG) /* r -> f */ 261: return 262: \"subq $8,sp\;storw %1,(sp)\;loads (sp),%0\;addq $8,sp\"; 263: return \"loads %1,%0\"; /* m -> f */ 264: } 265: 266: if (FP_REG_P (operands[1])) 267: { 268: if (GET_CODE (operands[0]) == REG) /* f -> r */ 269: return 270: \"subq $8,sp\;stors %1,(sp)\;loadw (sp),%0\;addq $8,sp\"; 271: abort (); 272: } 273: 274: if (GET_CODE (operands[1]) == MEM) /* m -> r */ 275: return \"loadw %1,%0\"; 276: 277: if (GET_CODE (operands[1]) == REG) /* r -> r */ 278: return \"movw %1,%0\"; 279: 280: abort (); 281: #undef FP_REG_P 282: }") 283: 284: (define_insn "" 285: [(set (match_operand:SF 0 "memory_operand" "=m") 1.1.1.2 root 286: (match_operand:SF 1 "register_operand" "*rf"))] 1.1 root 287: "" 288: "* 289: { 290: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) >= 16) 291: return \"stors %1,%0\"; /* f-> m */ 292: 293: return \"storw %1,%0\"; /* r -> m */ 294: }" 295: [(set_attr "type" "store")]) 296: 297: 298: (define_expand "movdi" 299: [(set (match_operand:DI 0 "general_operand" "") 300: (match_operand:DI 1 "general_operand" ""))] 301: "" 302: " 303: { 304: if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) != REG) 305: operands[1] = force_reg (DImode, operands[1]); 306: }") 307: 1.1.1.2 root 308: ;; If an operand is a MEM but not offsetable, we can't load it into 309: ;; a register, so we must force the third alternative to be the one 310: ;; reloaded. Hence we show the first as more expensive. 1.1 root 311: (define_insn "" 1.1.1.2 root 312: [(set (match_operand:DI 0 "register_operand" "=?r,r,r") 1.1 root 313: (match_operand:DI 1 "general_operand" "r,n,o"))] 314: "" 315: "* 316: { 317: rtx xoperands[2],yoperands[2]; 318: 319: xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 320: 321: if (which_alternative == 0) /* r -> r */ 322: { 323: output_asm_insn (\"movw %1,%0\", operands); 324: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 325: output_asm_insn (\"movw %1,%0\", xoperands); 326: return \"\"; 327: } 328: 329: if (which_alternative == 1) /* n -> r */ 330: { 331: if (GET_CODE (operands[1]) == CONST_INT) 332: { 333: output_asm_insn (\"loadi %1,%0\", operands); 334: output_asm_insn (\"loadq $0,%0\", xoperands); 335: return \"\"; 336: } 337: 338: if (GET_CODE (operands[1]) != CONST_DOUBLE) 339: abort (); 340: 341: yoperands[0] = operands[0]; 342: yoperands[1] = gen_rtx (CONST_INT, VOIDmode, 343: CONST_DOUBLE_LOW (operands[1])); 344: output_asm_insn (\"loadi %1,%0\", yoperands); 345: 346: xoperands[1] = gen_rtx (CONST_INT, VOIDmode, 347: CONST_DOUBLE_HIGH (operands[1])); 348: output_asm_insn (\"loadi %1,%0\", xoperands); 349: return \"\"; 350: } 351: /* m -> r */ 352: output_asm_insn (\"loadw %1,%0\", operands); 353: xoperands[1] = adj_offsettable_operand (operands[1], 4); 354: output_asm_insn (\"loadw %1,%0\", xoperands); 355: return \"\"; 356: }" 357: [(set_attr "type" "arith,arith,load") 358: (set_attr "cc" "clobber,clobber,clobber")]) 359: 360: (define_insn "" 361: [(set (match_operand:DI 0 "memory_operand" "=o") 362: (match_operand:DI 1 "register_operand" "r"))] 363: "" 364: "* 365: { 366: rtx xops[4]; 367: xops[0] = operands[0]; 368: xops[1] = adj_offsettable_operand (operands[0], 4); 369: xops[2] = operands[1]; 370: xops[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 371: output_asm_insn (\"storw %2,%0\;storw %3,%1\", xops); 372: return \"\"; 373: }" 374: [(set_attr "type" "store") 375: (set_attr "cc" "clobber")]) 376: 377: (define_expand "movsi" 378: [(set (match_operand:SI 0 "general_operand" "") 379: (match_operand:SI 1 "general_operand" ""))] 380: "" 381: " 382: { 383: if (GET_CODE (operands[0]) == MEM && 384: GET_CODE (operands[1]) != REG) 385: operands[1] = force_reg (SImode, operands[1]); 386: }") 387: 1.1.1.3 ! root 388: ;; Reject both args with `general_operand' if not reloading because a ! 389: ;; mem -> mem move that was split by 'movsi' can be recombined to ! 390: ;; mem -> mem by the combiner. ! 391: ;; ! 392: ;; As a pseudo register can end up in a stack slot during reloading we must ! 393: ;; allow a r->m move for the next pattern. ! 394: ;; The first predicate must be `general_operand' because a predicate must ! 395: ;; be true for each constraint. ! 396: ;; ! 397: (define_insn "" ! 398: [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,m") ! 399: (match_operand:SI 1 "general_operand" "r,m,n,i,r"))] ! 400: "reload_in_progress || register_operand (operands[0], SImode)" 1.1 root 401: "* 402: { 403: int val; 404: 405: if (which_alternative == 0) 406: return \"movw %1,%0\"; /* reg -> reg */ 407: 408: if (which_alternative == 1) 409: return \"loadw %1,%0\"; /* mem -> reg */ 410: 411: if (which_alternative == 2) 412: { 413: val = INTVAL (operands[1]); /* known const ->reg */ 414: 415: if (val == -1) 416: return \"notq $0,%0\"; 417: 418: if (val < 0 || val >= 16) 419: return \"loadi %1,%0\"; 420: 421: return \"loadq %1,%0\"; 422: } 423: 424: if (which_alternative == 3) /* unknown const */ 425: return \"loada %a1,%0\"; 1.1.1.3 ! root 426: ! 427: return \"storw %1,%0\"; 1.1 root 428: }" 1.1.1.3 ! root 429: [(set_attr "type" "arith,load,arith,load,store") ! 430: (set_attr "cc" "set2,change0,set1,change0,unchanged")]) 1.1 root 431: 432: 433: (define_insn "" 434: [(set (match_operand:SI 0 "memory_operand" "=m") 435: (match_operand:SI 1 "int_reg_operand" "r"))] 436: "" 437: "storw %1,%0" 438: [(set_attr "type" "store")]) 439: 440: ;; movhi 441: ;; 442: ;; loadh mem to reg 443: ;; storh reg to mem 444: ;; 445: ;; 446: (define_expand "movhi" 447: [(set (match_operand:HI 0 "general_operand" "") 448: (match_operand:HI 1 "general_operand" ""))] 449: "" 450: " 451: { 452: if (GET_CODE (operands[0]) == MEM 453: && ! register_operand (operands[1], HImode)) 454: operands[1] = force_reg (HImode, operands[1]); 455: }") 456: 457: 458: (define_insn "" 459: [(set (match_operand:HI 0 "register_operand" "=r,r,r") 460: (match_operand:HI 1 "general_operand" "r,m,n"))] 461: "" 462: "@ 463: movw %1,%0 464: loadh %1,%0 465: loadi %1,%0" 466: [(set_attr "type" "arith,load,arith")]) 467: 468: (define_insn "" 469: [(set (match_operand:HI 0 "memory_operand" "=m") 470: (match_operand:HI 1 "register_operand" "r"))] 471: "" 472: "storh %1,%0" 473: [(set_attr "type" "store")]) 474: 475: ;; movqi 476: ;; 477: ;; loadb mem to reg 478: ;; storb reg to mem 479: ;; 480: (define_expand "movqi" 481: [(set (match_operand:QI 0 "general_operand" "") 482: (match_operand:QI 1 "general_operand" ""))] 483: "" 484: " 485: { 486: if (GET_CODE (operands[0]) == MEM && 487: ! register_operand (operands[1], QImode)) 488: operands[1] = force_reg (QImode, operands[1]); 489: }") 490: 491: 492: (define_insn "" 493: [(set (match_operand:QI 0 "register_operand" "=r,r,r") 494: (match_operand:QI 1 "general_operand" "r,m,n"))] 495: "" 496: "@ 497: movw %1,%0 498: loadb %1,%0 499: loadi %1,%0" 500: [(set_attr "type" "arith,load,arith")]) 501: 502: (define_insn "" 503: [(set (match_operand:QI 0 "memory_operand" "=m") 504: (match_operand:QI 1 "register_operand" "r"))] 505: "" 506: "storb %1,%0" 507: [(set_attr "type" "store")]) 508: 509: 510: ;; 511: ;; block move 512: ;; 513: (define_expand "movstrsi" 514: [(parallel 515: [(set (match_operand:BLK 0 "memory_operand" "") 516: (match_operand:BLK 1 "memory_operand" "")) 517: (use (match_operand:SI 2 "general_operand" "")) 518: (use (match_operand:SI 3 "const_int_operand" "")) 519: (clobber (match_scratch:SI 4 "")) 520: (clobber (match_scratch:SI 5 "")) 521: (clobber (match_dup 6)) 522: (clobber (match_dup 7))])] 523: "" 524: " 525: { 526: rtx addr0, addr1; 527: 528: addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); 529: addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); 530: 531: operands[6] = addr0; 532: operands[7] = addr1; 533: 534: operands[0] = gen_rtx (MEM, BLKmode, addr0); 535: operands[1] = gen_rtx (MEM, BLKmode, addr1); 536: 537: if (GET_CODE (operands[2]) != CONST_INT) 538: operands[2] = force_reg (SImode, operands[2]); 539: }") 540: 541: ;; 542: ;; there is a problem with this insn in gcc-2.2.3 543: ;; (clobber (match_dup 2)) does not prevent use of this operand later 544: ;; we always use a scratch register and leave operand 2 unchanged 545: ;; 546: (define_insn "" 547: [(set (mem:BLK (match_operand:SI 0 "register_operand" "r")) 548: (mem:BLK (match_operand:SI 1 "register_operand" "r"))) 549: (use (match_operand:SI 2 "nonmemory_operand" "rn")) 550: (use (match_operand:SI 3 "const_int_operand" "n")) 551: (clobber (match_scratch:SI 4 "=r")) 552: (clobber (match_scratch:SI 5 "=r")) 553: (clobber (match_dup 0)) 554: (clobber (match_dup 1))] 555: "" 556: "* 557: { 558: extern void clipper_movstr (); 559: clipper_movstr (operands); 560: return \"\"; 561: }" 562: [(set_attr "cc" "clobber")]) 563: 564: 565: 566: ;; Extension and truncation insns. 567: (define_insn "extendhisi2" 568: [(set (match_operand:SI 0 "int_reg_operand" "=r,r") 569: (sign_extend:SI (match_operand:HI 1 "general_operand" "0,m")))] 570: "" 571: "@ 572: andi $65535,%0\;xori $32768,%0\;subi $32768,%0 573: loadh %1,%0" 574: [(set_attr "type" "arith,load")]) 575: 576: 577: (define_insn "extendqihi2" 578: [(set (match_operand:HI 0 "int_reg_operand" "=r,r") 579: (sign_extend:HI (match_operand:QI 1 "general_operand" "0,m")))] 580: "" 581: "@ 582: andi $255,%0\;xori $128,%0\;subi $128,%0 583: loadb %1,%0" 584: [(set_attr "type" "arith,load") 585: (set_attr "cc" "set1,change0")]) 586: 587: 588: (define_insn "extendqisi2" 589: [(set (match_operand:SI 0 "int_reg_operand" "=r,r") 590: (sign_extend:SI (match_operand:QI 1 "general_operand" "0,m")))] 591: "" 592: "@ 593: andi $255,%0\;xori $128,%0\;subi $128,%0 594: loadb %1,%0" 595: [(set_attr "type" "arith,load")]) 596: 597: 598: (define_insn "extendsfdf2" 599: [(set (match_operand:DF 0 "fp_reg_operand" "=f") 600: (float_extend:DF (match_operand:SF 1 "fp_reg_operand" "f")))] 601: "" 602: "cnvsd %1,%0") 603: 604: (define_insn "truncdfsf2" 605: [(set (match_operand:SF 0 "fp_reg_operand" "=f") 606: (float_truncate:SF (match_operand:DF 1 "fp_reg_operand" "f")))] 607: "" 608: "cnvds %1,%0") 609: 610: (define_insn "zero_extendhisi2" 611: [(set (match_operand:SI 0 "int_reg_operand" "=r,r") 612: (zero_extend:SI (match_operand:HI 1 "general_operand" "0,m")))] 613: "" 614: "@ 615: andi $65535,%0 616: loadhu %1,%0" 617: [(set_attr "type" "arith,load")]) 618: 619: 620: (define_insn "zero_extendqihi2" 621: [(set (match_operand:HI 0 "int_reg_operand" "=r,r") 622: (zero_extend:HI (match_operand:QI 1 "general_operand" "0,m")))] 623: "" 624: "@ 625: andi $255,%0 626: loadbu %1,%0" 627: [(set_attr "type" "arith,load") 628: (set_attr "cc" "clobber,clobber")]) 629: 630: 631: (define_insn "zero_extendqisi2" 632: [(set (match_operand:SI 0 "int_reg_operand" "=r,r") 633: (zero_extend:SI (match_operand:QI 1 "general_operand" "0,m")))] 634: "" 635: "@ 636: andi $255,%0 637: loadbu %1,%0" 638: [(set_attr "type" "arith,load")]) 639: 640: 641: 642: ;; Fix-to-float conversion insns. 643: 644: (define_insn "floatsisf2" 645: [(set (match_operand:SF 0 "fp_reg_operand" "=f") 646: (float:SF (match_operand:SI 1 "int_reg_operand" "r")))] 647: "" 648: "cnvws %1,%0") 649: 650: (define_insn "floatsidf2" 651: [(set (match_operand:DF 0 "fp_reg_operand" "=f") 652: (float:DF (match_operand:SI 1 "int_reg_operand" "r")))] 653: "" 654: "cnvwd %1,%0") 655: 656: 657: ;; Float-to-fix conversion insns. 658: 659: (define_insn "fix_truncsfsi2" 660: [(set (match_operand:SI 0 "int_reg_operand" "=r") 661: (fix:SI (fix:SF (match_operand:SF 1 "fp_reg_operand" "f"))))] 662: "" 663: "cnvtsw %1,%0") 664: 665: (define_insn "fix_truncdfsi2" 666: [(set (match_operand:SI 0 "int_reg_operand" "=r") 667: (fix:SI (fix:DF (match_operand:DF 1 "fp_reg_operand" "f"))))] 668: "" 669: "cnvtdw %1,%0") 670: 671: ;;- All kinds of add instructions. 672: 673: (define_insn "adddf3" 674: [(set (match_operand:DF 0 "fp_reg_operand" "=f") 675: (plus:DF (match_operand:DF 1 "fp_reg_operand" "0") 676: (match_operand:DF 2 "fp_reg_operand" "f")))] 677: "" 678: "addd %2,%0" 679: [(set_attr "type" "fp")]) 680: 681: 682: (define_insn "addsf3" 683: [(set (match_operand:SF 0 "fp_reg_operand" "=f") 684: (plus:SF (match_operand:SF 1 "fp_reg_operand" "0") 685: (match_operand:SF 2 "fp_reg_operand" "f")))] 686: "" 687: "adds %2,%0" 688: [(set_attr "type" "fp")]) 689: 690: (define_insn "adddi3" 691: [(set (match_operand:DI 0 "int_reg_operand" "=r") 692: (plus:DI (match_operand:DI 1 "int_reg_operand" "%0") 693: (match_operand:DI 2 "int_reg_operand" "r")))] 694: "" 695: "* 696: { 697: rtx xoperands[4]; 698: 699: xoperands[0] = operands[0]; 700: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 701: xoperands[2] = operands[2]; 702: xoperands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1); 703: output_asm_insn (\"addw %2,%0\;addwc %3,%1\", xoperands); 704: return \"\"; 705: }" 706: [(set_attr "type" "arith") 707: (set_attr "cc" "clobber")]) 708: 709: (define_insn "addsi3" 710: [(set (match_operand:SI 0 "int_reg_operand" "=r,r,r") 711: (plus:SI (match_operand:SI 1 "int_reg_operand" "%0,r,r") 712: (match_operand:SI 2 "nonmemory_operand" "rn,0,rn")))] 713: "" 714: "* 715: { 716: if (which_alternative == 2) /* 3 address version */ 717: { 718: if (GET_CODE (operands[2]) == CONST_INT) 719: return \"loada %a2(%1),%0\"; 720: return \"loada [%2](%1),%0\"; 721: } 722: /* 2 address version */ 723: if (GET_CODE (operands[2]) == CONST_INT) 724: { 725: int val = INTVAL (operands[2]); 726: 727: if (val >= 16 || val == 0x80000000) 728: return \"addi %2,%0\"; 729: 730: if (val < 0) /* change to sub */ 731: { 732: rtx xops[2]; 733: 734: val = -val; 735: 736: xops[0] = operands[0]; 737: xops[1] = gen_rtx (CONST_INT, VOIDmode, val); 738: 739: if (val >= 16) 740: output_asm_insn (\"subi %1,%0\", xops); 741: else 742: output_asm_insn (\"subq %1,%0\", xops); 743: 744: return \"\"; 745: } 746: 747: return \"addq %2,%0\"; 748: } 749: 750: if (which_alternative == 0) 751: return \"addw %2,%0\"; 752: 753: return \"addw %1,%0\"; 754: }" 755: [(set_attr "type" "arith,arith,arith") 756: (set_attr "cc" "set1,set1,change0")]) 757: 758: 759: ;;- All kinds of subtract instructions. 760: 761: (define_insn "subdi3" 762: [(set (match_operand:DI 0 "int_reg_operand" "=r") 1.1.1.3 ! root 763: (minus:DI (match_operand:DI 1 "int_reg_operand" "0") 1.1 root 764: (match_operand:DI 2 "int_reg_operand" "r")))] 765: "" 766: "* 767: { 768: rtx xoperands[4]; 769: 770: xoperands[0] = operands[0]; 771: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 772: xoperands[2] = operands[2]; 773: xoperands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1); 774: output_asm_insn (\"subw %2,%0\;subwc %3,%1\", xoperands); 775: return \"\"; 776: }" 777: [(set_attr "type" "arith") 778: (set_attr "cc" "clobber")]) 779: 780: (define_insn "subsi3" 781: [(set (match_operand:SI 0 "int_reg_operand" "=r") 782: (minus:SI (match_operand:SI 1 "int_reg_operand" "0") 783: (match_operand:SI 2 "nonmemory_operand" "rn")))] 784: "" 785: "* 786: { 787: if (GET_CODE (operands[2]) == CONST_INT) 788: { 789: int val = INTVAL (operands[2]); 790: 791: if (val < 0 || val >= 16) 792: return \"subi %2,%0\"; 793: else 794: return \"subq %2,%0\"; 795: } 796: 797: return \"subw %2,%0\"; 798: }" 799: [(set_attr "type" "arith")]) 800: 801: (define_insn "subdf3" 802: [(set (match_operand:DF 0 "fp_reg_operand" "=f") 803: (minus:DF (match_operand:DF 1 "fp_reg_operand" "0") 804: (match_operand:DF 2 "fp_reg_operand" "f")))] 805: "" 806: "subd %2,%0" 807: [(set_attr "type" "fp")]) 808: 809: (define_insn "subsf3" 810: [(set (match_operand:SF 0 "fp_reg_operand" "=f") 811: (minus:SF (match_operand:SF 1 "fp_reg_operand" "0") 812: (match_operand:SF 2 "fp_reg_operand" "f")))] 813: "" 814: "subs %2,%0" 815: [(set_attr "type" "fp")]) 816: 817: 818: ;;- Multiply instructions. 819: 820: (define_insn "muldf3" 821: [(set (match_operand:DF 0 "fp_reg_operand" "=f") 822: (mult:DF (match_operand:DF 1 "fp_reg_operand" "0") 823: (match_operand:DF 2 "fp_reg_operand" "f")))] 824: "" 825: "muld %2,%0" 826: [(set_attr "type" "fp")]) 827: 828: (define_insn "mulsf3" 829: [(set (match_operand:SF 0 "fp_reg_operand" "=f") 830: (mult:SF (match_operand:SF 1 "fp_reg_operand" "0") 831: (match_operand:SF 2 "fp_reg_operand" "f")))] 832: "" 833: "muls %2,%0" 834: [(set_attr "type" "fp")]) 835: 836: (define_insn "mulsidi3" 837: [(set (match_operand:DI 0 "int_reg_operand" "=r") 838: (mult:DI (sign_extend:DI (match_operand:SI 1 "int_reg_operand" "%0")) 839: (sign_extend:DI (match_operand:SI 2 "int_reg_operand" "r"))))] 840: "" 841: "mulwx %2,%0" 842: [(set_attr "type" "arith") 843: (set_attr "cc" "clobber")]) 844: 845: (define_insn "umulsidi3" 846: [(set (match_operand:DI 0 "int_reg_operand" "=r") 847: (mult:DI (zero_extend:DI (match_operand:SI 1 "int_reg_operand" "%0")) 848: (zero_extend:DI (match_operand:SI 2 "int_reg_operand" "r"))))] 849: "" 850: "mulwux %2,%0" 851: [(set_attr "type" "arith") 852: (set_attr "cc" "clobber")]) 853: 854: (define_insn "mulsi3" 855: [(set (match_operand:SI 0 "int_reg_operand" "=r") 856: (mult:SI (match_operand:SI 1 "int_reg_operand" "%0") 857: (match_operand:SI 2 "int_reg_operand" "r")))] 858: "" 859: "mulw %2,%0" 860: [(set_attr "type" "arith") 861: (set_attr "cc" "clobber")]) 862: 863: 864: ;;- Divide and mod instructions. 865: 866: (define_insn "divdf3" 867: [(set (match_operand:DF 0 "fp_reg_operand" "=f") 868: (div:DF (match_operand:DF 1 "fp_reg_operand" "0") 869: (match_operand:DF 2 "fp_reg_operand" "f")))] 870: "" 871: "divd %2,%0" 872: [(set_attr "type" "fp")]) 873: 874: (define_insn "divsf3" 875: [(set (match_operand:SF 0 "fp_reg_operand" "=f") 876: (div:SF (match_operand:SF 1 "fp_reg_operand" "0") 877: (match_operand:SF 2 "fp_reg_operand" "f")))] 878: "" 879: "divs %2,%0" 880: [(set_attr "type" "fp")]) 881: 882: (define_insn "divsi3" 883: [(set (match_operand:SI 0 "int_reg_operand" "=r") 884: (div:SI (match_operand:SI 1 "int_reg_operand" "0") 885: (match_operand:SI 2 "int_reg_operand" "r")))] 886: "" 887: "divw %2,%0" 888: [(set_attr "type" "arith") 889: (set_attr "cc" "clobber")]) 890: 891: (define_insn "udivsi3" 892: [(set (match_operand:SI 0 "int_reg_operand" "=r") 893: (udiv:SI (match_operand:SI 1 "int_reg_operand" "0") 894: (match_operand:SI 2 "int_reg_operand" "r")))] 895: "" 896: "divwu %2,%0" 897: [(set_attr "type" "arith") 898: (set_attr "cc" "clobber")]) 899: 900: 901: (define_insn "modsi3" 902: [(set (match_operand:SI 0 "int_reg_operand" "=r") 903: (mod:SI (match_operand:SI 1 "int_reg_operand" "0") 904: (match_operand:SI 2 "int_reg_operand" "r")))] 905: "" 906: "modw %2,%0" 907: [(set_attr "type" "arith") 908: (set_attr "cc" "clobber")]) 909: 910: (define_insn "umodsi3" 911: [(set (match_operand:SI 0 "int_reg_operand" "=r") 912: (umod:SI (match_operand:SI 1 "int_reg_operand" "0") 913: (match_operand:SI 2 "int_reg_operand" "r")))] 914: "" 915: "modwu %2,%0" 916: [(set_attr "type" "arith") 917: (set_attr "cc" "clobber")]) 918: 919: ;; 920: ;; bit and/or instructions 921: ;; 922: (define_insn "andsi3" 923: [(set (match_operand:SI 0 "int_reg_operand" "=r,r") 924: (and:SI (match_operand:SI 1 "int_reg_operand" "%0,0") 925: (match_operand:SI 2 "nonmemory_operand" "r,n")))] 926: "" 927: "@ 928: andw %2,%0 929: andi %2,%0" 930: [(set_attr "type" "arith")]) 931: 932: (define_insn "iorsi3" 933: [(set (match_operand:SI 0 "int_reg_operand" "=r,r") 934: (ior:SI (match_operand:SI 1 "int_reg_operand" "%0,0") 935: (match_operand:SI 2 "nonmemory_operand" "r,n")))] 936: "" 937: "@ 938: orw %2,%0 939: ori %2,%0" 940: [(set_attr "type" "arith")]) 941: 942: (define_insn "xorsi3" 943: [(set (match_operand:SI 0 "int_reg_operand" "=r,r") 944: (xor:SI (match_operand:SI 1 "int_reg_operand" "%0,0") 945: (match_operand:SI 2 "nonmemory_operand" "r,n")))] 946: "" 947: "@ 948: xorw %2,%0 949: xori %2,%0" 950: [(set_attr "type" "arith")]) 951: 952: (define_insn "negdf2" 953: [(set (match_operand:DF 0 "fp_reg_operand" "=f") 954: (neg:DF (match_operand:DF 1 "fp_reg_operand" "f")))] 955: "" 956: "negd %1,%0" 957: [(set_attr "type" "fp")]) 958: 959: (define_insn "negsf2" 960: [(set (match_operand:SF 0 "fp_reg_operand" "=f") 961: (neg:SF (match_operand:SF 1 "fp_reg_operand" "f")))] 962: "" 963: "negs %1,%0" 964: [(set_attr "type" "fp")]) 965: 966: (define_insn "negsi2" 967: [(set (match_operand:SI 0 "int_reg_operand" "=r") 968: (neg:SI (match_operand:SI 1 "int_reg_operand" "r")))] 969: "" 970: "negw %1,%0" 971: [(set_attr "type" "arith")]) 972: 973: 974: (define_insn "one_cmplsi2" 975: [(set (match_operand:SI 0 "int_reg_operand" "=r") 976: (not:SI (match_operand:SI 1 "int_reg_operand" "r")))] 977: "" 978: "notw %1,%0" 979: [(set_attr "type" "arith")]) 980: 981: 982: 983: ;; Right shift on the clipper works by negating the shift count, 984: ;; then emitting a right shift with the shift count negated. This means 985: ;; that all actual shift counts in the RTL will be positive. 986: 987: (define_expand "ashrdi3" 988: [(set (match_operand:DI 0 "int_reg_operand" "") 989: (ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "") 990: (match_operand:SI 2 "nonmemory_operand" "")))] 991: "" 992: " 993: { 994: if (GET_CODE (operands[2]) != CONST_INT) 995: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); 996: }") 997: 998: (define_insn "" 999: [(set (match_operand:DI 0 "int_reg_operand" "=r") 1000: (ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "0") 1001: (match_operand:SI 2 "const_int_operand" "n")))] 1002: "" 1003: "shali $%n2,%0" 1004: [(set_attr "type" "arith")]) 1005: 1006: (define_insn "" 1007: [(set (match_operand:DI 0 "int_reg_operand" "=r") 1008: (ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "0") 1009: (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))] 1010: "" 1011: "shal %2,%0" 1012: [(set_attr "type" "arith")]) 1013: 1014: (define_expand "ashrsi3" 1015: [(set (match_operand:SI 0 "int_reg_operand" "") 1016: (ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "") 1017: (match_operand:SI 2 "nonmemory_operand" "")))] 1018: "" 1019: " 1020: { 1021: if (GET_CODE (operands[2]) != CONST_INT) 1022: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); 1023: }") 1024: 1025: (define_insn "" 1026: [(set (match_operand:SI 0 "int_reg_operand" "=r") 1027: (ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "0") 1028: (match_operand:SI 2 "const_int_operand" "n")))] 1029: "" 1030: "shai $%n2,%0" 1031: [(set_attr "type" "arith")]) 1032: 1033: (define_insn "" 1034: [(set (match_operand:SI 0 "int_reg_operand" "=r") 1035: (ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "0") 1036: (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))] 1037: "" 1038: "shaw %2,%0" 1039: [(set_attr "type" "arith")]) 1040: 1041: ;; 1042: ;; left shift 1043: ;; 1044: 1045: (define_insn "ashldi3" 1046: [(set (match_operand:DI 0 "int_reg_operand" "=r,r") 1047: (ashift:DI (match_operand:DI 1 "int_reg_operand" "0,0") 1048: (match_operand:SI 2 "nonmemory_operand" "r,n")))] 1049: "" 1050: "@ 1051: shal %2,%0 1052: shali %2,%0" 1053: [(set_attr "type" "arith")]) 1054: 1055: 1056: (define_insn "ashlsi3" 1057: [(set (match_operand:SI 0 "int_reg_operand" "=r,r") 1058: (ashift:SI (match_operand:SI 1 "int_reg_operand" "0,0") 1059: (match_operand:SI 2 "nonmemory_operand" "r,n")))] 1060: "" 1061: "* 1062: { 1063: int val; 1064: 1065: if (which_alternative == 0) 1066: return \"shaw %2,%0\"; 1067: 1068: val = INTVAL (operands[2]); 1069: 1070: if (val == 2) 1071: return \"addw %0,%0\;addw %0,%0\"; 1072: 1073: if (val == 1) 1074: return \"addw %0,%0\"; 1075: 1076: return \"shai %2,%0\"; 1077: }" 1078: [(set_attr "type" "arith")]) 1079: 1080: ;; 1081: ;; logical shift 1082: ;; 1083: 1084: (define_expand "lshrdi3" 1085: [(set (match_operand:DI 0 "int_reg_operand" "") 1086: (lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "") 1087: (match_operand:SI 2 "nonmemory_operand" "")))] 1088: "" 1089: " 1090: { 1091: if (GET_CODE (operands[2]) != CONST_INT) 1092: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); 1093: }") 1094: 1095: (define_insn "" 1096: [(set (match_operand:DI 0 "int_reg_operand" "=r") 1097: (lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "0") 1098: (match_operand:SI 2 "const_int_operand" "n")))] 1099: "" 1100: "shlli $%n2,%0" 1101: [(set_attr "type" "arith")]) 1102: 1103: (define_insn "" 1104: [(set (match_operand:DI 0 "int_reg_operand" "=r") 1105: (lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "0") 1106: (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))] 1107: "" 1108: "shll %2,%0" 1109: [(set_attr "type" "arith")]) 1110: 1111: (define_expand "lshrsi3" 1112: [(set (match_operand:SI 0 "int_reg_operand" "") 1113: (lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "") 1114: (match_operand:SI 2 "nonmemory_operand" "")))] 1115: "" 1116: " 1117: { 1118: if (GET_CODE (operands[2]) != CONST_INT) 1119: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); 1120: }") 1121: 1122: (define_insn "" 1123: [(set (match_operand:SI 0 "int_reg_operand" "=r") 1124: (lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "0") 1125: (match_operand:SI 2 "const_int_operand" "n")))] 1126: "" 1127: "shli $%n2,%0" 1128: [(set_attr "type" "arith")]) 1129: 1130: (define_insn "" 1131: [(set (match_operand:SI 0 "int_reg_operand" "=r") 1132: (lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "0") 1133: (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))] 1134: "" 1135: "shlw %2,%0" 1136: [(set_attr "type" "arith")]) 1137: 1138: 1139: ;; 1140: ;; rotate insn 1141: ;; 1142: (define_expand "rotrdi3" 1143: [(set (match_operand:DI 0 "int_reg_operand" "") 1144: (rotatert:DI (match_operand:DI 1 "int_reg_operand" "") 1145: (match_operand:SI 2 "nonmemory_operand" "")))] 1146: "" 1147: " 1148: { 1149: if (GET_CODE (operands[2]) != CONST_INT) 1150: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); 1151: }") 1152: 1153: (define_insn "" 1154: [(set (match_operand:DI 0 "int_reg_operand" "=r") 1155: (rotatert:DI (match_operand:DI 1 "int_reg_operand" "0") 1156: (match_operand:SI 2 "const_int_operand" "n")))] 1157: "" 1158: "rotli $%n2,%0" 1159: [(set_attr "type" "arith")]) 1160: 1161: (define_insn "" 1162: [(set (match_operand:DI 0 "int_reg_operand" "=r") 1163: (rotatert:DI (match_operand:DI 1 "int_reg_operand" "0") 1164: (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))] 1165: "" 1166: "rotl %2,%0" 1167: [(set_attr "type" "arith")]) 1168: 1169: (define_expand "rotrsi3" 1170: [(set (match_operand:SI 0 "int_reg_operand" "") 1171: (rotatert:SI (match_operand:SI 1 "int_reg_operand" "") 1172: (match_operand:SI 2 "nonmemory_operand" "")))] 1173: "" 1174: " 1175: { 1176: if (GET_CODE (operands[2]) != CONST_INT) 1177: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); 1178: }") 1179: 1180: (define_insn "" 1181: [(set (match_operand:SI 0 "int_reg_operand" "=r") 1182: (rotatert:SI (match_operand:SI 1 "int_reg_operand" "0") 1183: (match_operand:SI 2 "const_int_operand" "n")))] 1184: "" 1185: "roti $%n2,%0" 1186: [(set_attr "type" "arith")]) 1187: 1188: (define_insn "" 1189: [(set (match_operand:SI 0 "int_reg_operand" "=r") 1190: (rotatert:SI (match_operand:SI 1 "int_reg_operand" "0") 1191: (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))] 1192: "" 1193: "rotw %2,%0" 1194: [(set_attr "type" "arith")]) 1195: 1196: (define_insn "rotldi3" 1197: [(set (match_operand:DI 0 "int_reg_operand" "=r,r") 1198: (rotate:DI (match_operand:DI 1 "int_reg_operand" "0,0") 1199: (match_operand:SI 2 "nonmemory_operand" "r,n")))] 1200: "" 1201: "@ 1202: rotl %2,%0 1203: rotli %2,%0" 1204: [(set_attr "type" "arith")]) 1205: 1206: (define_insn "rotlsi3" 1207: [(set (match_operand:SI 0 "int_reg_operand" "=r,r") 1208: (rotate:SI (match_operand:SI 1 "int_reg_operand" "0,0") 1209: (match_operand:SI 2 "nonmemory_operand" "r,n")))] 1210: "" 1211: "@ 1212: rotw %2,%0 1213: roti %2,%0" 1214: [(set_attr "type" "arith")]) 1215: 1216: 1217: ;; 1218: ;; jump and branch insns 1219: ;; 1220: (define_insn "jump" 1221: [(set (pc) 1222: (label_ref (match_operand 0 "" "")))] 1223: "" 1224: "b %l0" 1225: [(set_attr "type" "branch")]) 1226: 1227: (define_insn "tablejump" 1228: [(set (pc) (match_operand:SI 0 "register_operand" "r")) 1229: (use (label_ref (match_operand 1 "" "")))] 1230: "" 1231: "b (%0)" 1232: [(set_attr "type" "branch")]) 1233: 1234: (define_insn "beq" 1235: [(set (pc) 1236: (if_then_else (eq (cc0) 1237: (const_int 0)) 1238: (label_ref (match_operand 0 "" "")) 1239: (pc)))] 1240: "" 1241: "breq %l0" 1242: [(set_attr "type" "branch")]) 1243: 1244: (define_insn "bne" 1245: [(set (pc) 1246: (if_then_else (ne (cc0) 1247: (const_int 0)) 1248: (label_ref (match_operand 0 "" "")) 1249: (pc)))] 1250: "" 1251: "brne %l0" 1252: [(set_attr "type" "branch")]) 1253: 1254: (define_insn "bgt" 1255: [(set (pc) 1256: (if_then_else (gt (cc0) 1257: (const_int 0)) 1258: (label_ref (match_operand 0 "" "")) 1259: (pc)))] 1260: "" 1261: "brgt %l0" 1262: [(set_attr "type" "branch")]) 1263: 1264: (define_insn "bgtu" 1265: [(set (pc) 1266: (if_then_else (gtu (cc0) 1267: (const_int 0)) 1268: (label_ref (match_operand 0 "" "")) 1269: (pc)))] 1270: "" 1271: "brgtu %l0" 1272: [(set_attr "type" "branch")]) 1273: 1274: (define_insn "blt" 1275: [(set (pc) 1276: (if_then_else (lt (cc0) 1277: (const_int 0)) 1278: (label_ref (match_operand 0 "" "")) 1279: (pc)))] 1280: "" 1281: "brlt %l0" 1282: [(set_attr "type" "branch")]) 1283: 1284: (define_insn "bltu" 1285: [(set (pc) 1286: (if_then_else (ltu (cc0) 1287: (const_int 0)) 1288: (label_ref (match_operand 0 "" "")) 1289: (pc)))] 1290: "" 1291: "brltu %l0" 1292: [(set_attr "type" "branch")]) 1293: 1294: (define_insn "bge" 1295: [(set (pc) 1296: (if_then_else (ge (cc0) 1297: (const_int 0)) 1298: (label_ref (match_operand 0 "" "")) 1299: (pc)))] 1300: "" 1301: "brge %l0" 1302: [(set_attr "type" "branch")]) 1303: 1304: (define_insn "bgeu" 1305: [(set (pc) 1306: (if_then_else (geu (cc0) 1307: (const_int 0)) 1308: (label_ref (match_operand 0 "" "")) 1309: (pc)))] 1310: "" 1311: "brgeu %l0" 1312: [(set_attr "type" "branch")]) 1313: 1314: (define_insn "ble" 1315: [(set (pc) 1316: (if_then_else (le (cc0) 1317: (const_int 0)) 1318: (label_ref (match_operand 0 "" "")) 1319: (pc)))] 1320: "" 1321: "brle %l0" 1322: [(set_attr "type" "branch")]) 1323: 1324: (define_insn "bleu" 1325: [(set (pc) 1326: (if_then_else (leu (cc0) 1327: (const_int 0)) 1328: (label_ref (match_operand 0 "" "")) 1329: (pc)))] 1330: "" 1331: "brleu %l0" 1332: [(set_attr "type" "branch")]) 1333: 1334: ;; Recognize reversed jumps. 1335: (define_insn "" 1336: [(set (pc) 1337: (if_then_else (match_operator 0 "comparison_operator" 1338: [(cc0) 1339: (const_int 0)]) 1340: (pc) 1341: (label_ref (match_operand 1 "" ""))))] 1342: "" 1343: "br%C0 %l1" ; %C0 negates condition 1344: [(set_attr "type" "branch")]) 1345: 1346: ;; 1347: ;; call instructions 1348: ;; 1349: (define_insn "call" 1350: [(call (match_operand:QI 0 "general_operand" "m") 1351: (match_operand:SI 1 "general_operand" ""))] 1352: ;; Operand 1 not used on the clipper. 1353: "" 1354: "call sp,%0") 1355: 1356: (define_insn "call_value" 1357: [(set (match_operand 0 "" "=rf") 1358: (call (match_operand:QI 1 "general_operand" "m") 1359: (match_operand:SI 2 "general_operand" "g")))] 1360: ;; Operand 2 not used on the clipper 1361: "" 1362: "call sp,%1") 1363: 1364: (define_insn "indirect_jump" 1365: [(set (pc) (match_operand:SI 0 "register_operand" "r"))] 1366: "" 1367: "b (%0)" 1368: [(set_attr "type" "branch")]) 1369: 1370: 1371: (define_insn "nop" 1372: [(const_int 0)] 1373: "" 1374: "noop" 1375: [(set_attr "type" "arith") 1376: (set_attr "cc" "unchanged")]) 1377: 1378: 1379: 1380: ;; while (--foo >= 0) 1381: ;; 1382: ;; Combiners for 'decrement test and branch' do not work for clipper. 1383: ;; These patters are jump_insns that do not allow output reloads and clipper 1384: ;; can only decrement and test registers. 1385: ;;
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