![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to clipper.md CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [GCC 2.x] / gcc / config / clipper|
Return to clipper.md CVS log | Up to [GCC 2.x] / gcc / config / clipper |
1.1 root 1: ;;- Machine description for GNU compiler, Clipper Version 1.1.1.3 root 2: ;; Copyright (C) 1987, 1988, 1991, 1993, 1994 Free Software Foundation, Inc. 1.1 root 3: ;; Contributed by Holger Teutsch ([email protected]) 4: 5: ;; This file is part of GNU CC. 6: 7: ;; GNU CC is free software; you can redistribute it and/or modify 8: ;; it under the terms of the GNU General Public License as published by 9: ;; the Free Software Foundation; either version 2, or (at your option) 10: ;; any later version. 11: 12: ;; GNU CC is distributed in the hope that it will be useful, 13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15: ;; GNU General Public License for more details. 16: 17: ;; You should have received a copy of the GNU General Public License 18: ;; along with GNU CC; see the file COPYING. If not, write to 1.1.1.4 ! root 19: ;; the Free Software Foundation, 59 Temple Place - Suite 330, ! 20: ;; Boston, MA 02111-1307, USA. 1.1 root 21: 22: 23: ;;- Instruction patterns. When multiple patterns apply, 24: ;;- the first one in the file is chosen. 25: ;;- 26: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 27: ;;- 28: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code 29: ;;- updates for most instructions. 30: 31: ;; 32: ;; define attributes 33: ;; 34: ;; instruction type 35: ;; 36: ;; unknown is temporary in order to generate 'cc clobber' until attribute 37: ;; assignment is consistent 38: ;; 39: (define_attr "type" "load,store,arith,fp,branch,unknown" 40: (const_string "unknown")) 41: 42: ;; condition code setting 43: ;; 44: ;; clobber destroyed 45: ;; unchanged 46: ;; set1 set cc_status.value1, e.g. sub r0,r1 47: ;; set2 set value1 and value2, e.g. mov r0,r1 48: ;; change0 may be side effect, i.e. load mem,r0 49: ;; 50: ;; note: loadi and loadq are 'arith' instructions that set the condition codes 51: ;; mul,div,mod do NOT set the condition codes 52: ;; 53: (define_attr "cc" "clobber,unchanged,set1,set2,change0" 54: (cond [(eq_attr "type" "load") (const_string "change0") 55: (eq_attr "type" "store,branch") (const_string "unchanged") 56: (eq_attr "type" "arith") (if_then_else (match_operand:SI 0 "" "") 57: (const_string "set1") 58: (const_string "clobber")) 59: ] 60: (const_string "clobber"))) 61: 62: ;; 1.1.1.4 ! root 63: ;; clipper seems to be a traditional risc processor 1.1 root 64: ;; we define a functional unit 'memory' 65: ;; 66: (define_function_unit "memory" 1 1 (eq_attr "type" "load") 4 0) 67: 68: 69: ;; We don't want to allow a constant operand for test insns because 70: ;; (set (cc0) (const_int foo)) has no mode information. Such insns will 71: ;; be folded while optimizing anyway. 72: 73: (define_insn "tstsi" 74: [(set (cc0) 75: (match_operand:SI 0 "int_reg_operand" "r"))] 76: "" 77: "cmpq $0,%0") 78: 79: (define_insn "cmpsi" 80: [(set (cc0) 81: (compare (match_operand:SI 0 "nonimmediate_operand" "r,r,n") 82: (match_operand:SI 1 "nonmemory_operand" "r,n,r")))] 83: "" 84: "* 85: { 86: int val; 87: 88: if (which_alternative == 0) 89: return \"cmpw %1,%0\"; 90: 91: if (which_alternative == 1) 92: { 93: val = INTVAL (operands[1]); 94: if (0 <= val && val < 16) 95: return \"cmpq %1,%0\"; 96: return \"cmpi %1,%0\"; 97: } 98: 99: cc_status.flags |= CC_REVERSED; /* immediate must be first */ 100: 101: val = INTVAL (operands[0]); 102: 103: if (0 <= val && val < 16) 104: return \"cmpq %0,%1\"; 105: 106: return \"cmpi %0,%1\"; 107: }") 108: 109: (define_insn "cmpdf" 110: [(set (cc0) 111: (compare (match_operand:DF 0 "fp_reg_operand" "f") 112: (match_operand:DF 1 "fp_reg_operand" "f")))] 113: "" 114: "cmpd %1,%0") 115: 116: (define_insn "cmpsf" 117: [(set (cc0) 118: (compare (match_operand:SF 0 "fp_reg_operand" "f") 119: (match_operand:SF 1 "fp_reg_operand" "f")))] 120: "" 121: "cmps %1,%0") 122: 123: 124: ;; 125: ;; double and single float move 126: ;; 127: (define_expand "movdf" 128: [(set (match_operand:DF 0 "general_operand" "") 129: (match_operand:DF 1 "general_operand" ""))] 130: "" 131: " 132: { 133: if (GET_CODE (operands[0]) == MEM) 134: { 135: if (GET_CODE (operands[1]) == CONST_DOUBLE) 136: operands[1] = force_reg (DFmode, 137: force_const_mem (DFmode, operands[1])); 138: else if (GET_CODE (operands[1]) != REG) 139: operands[1] = force_reg (DFmode, operands[1]); 140: } 141: 142: else if (GET_CODE (operands[1]) == CONST_DOUBLE) 143: operands[1] = force_const_mem (DFmode, operands[1]); 144: }") 145: 146: ;; 147: ;; provide two patterns with different predicates as we don't want combine 148: ;; to recombine a mem -> mem move 149: ;; 150: (define_insn "" 1.1.1.2 root 151: [(set (match_operand:DF 0 "register_operand" "=*rf") 152: (match_operand:DF 1 "nonimmediate_operand" "*rfo"))] 1.1 root 153: "" 154: "* 155: { 156: #define FP_REG_P(X) (GET_CODE (X) == REG && REGNO (X) >= 16) 157: 158: if (FP_REG_P (operands[0])) 159: { 160: if (FP_REG_P (operands[1])) /* f -> f */ 161: return \"movd %1,%0\"; 162: 163: if (GET_CODE (operands[1]) == REG) /* r -> f */ 164: return \"movld %1,%0\"; 165: 166: return \"loadd %1,%0\"; /* m -> f */ 167: } 168: 169: if (FP_REG_P (operands[1])) 170: { 171: if (GET_CODE (operands[0]) == REG) /* f -> r */ 172: return \"movdl %1,%0\"; 173: 174: abort (); 175: } 176: 177: if (GET_CODE (operands[1]) == MEM) /* m -> r */ 178: { 179: rtx xops[4]; 180: xops[0] = operands[0]; 181: xops[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 182: xops[2] = operands[1]; 183: xops[3] = adj_offsettable_operand (operands[1], 4); 184: output_asm_insn (\"loadw %2,%0\;loadw %3,%1\", xops); 185: return \"\"; 186: } 187: 188: if (GET_CODE (operands[1]) == REG) /* r -> r */ 189: { 190: rtx xops[4]; 191: xops[0] = operands[0]; 192: xops[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 193: xops[2] = operands[1]; 194: xops[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 195: output_asm_insn (\"movw %2,%0\;movw %3,%1\", xops); 196: return \"\"; 197: } 198: 199: abort (); 200: #undef FP_REG_P 201: }") 202: 203: 204: (define_insn "" 205: [(set (match_operand:DF 0 "memory_operand" "=o,m") 1.1.1.2 root 206: (match_operand:DF 1 "register_operand" "*rf,f"))] 1.1 root 207: "" 208: "* 209: { 1.1.1.2 root 210: rtx xops[4]; 211: 212: if (REGNO (operands[1]) >= 16) /* f -> m */ 213: return \"stord %1,%0\"; 1.1 root 214: 1.1.1.2 root 215: xops[0] = operands[0]; /* r -> o */ 216: xops[1] = adj_offsettable_operand (operands[0], 4); 217: xops[2] = operands[1]; 218: xops[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 219: output_asm_insn (\"storw %2,%0\;storw %3,%1\", xops); 220: return \"\"; 1.1 root 221: }" 222: [(set_attr "type" "store,store") 223: (set_attr "cc" "clobber,unchanged")]) 224: 225: 226: (define_expand "movsf" 227: [(set (match_operand:SF 0 "general_operand" "") 228: (match_operand:SF 1 "general_operand" ""))] 229: "" 230: " 231: { 232: if (GET_CODE (operands[0]) == MEM) 233: { 234: if (GET_CODE (operands[1]) == CONST_DOUBLE) 235: operands[1] = force_reg (SFmode, 236: force_const_mem (SFmode, operands[1])); 237: else if (GET_CODE (operands[1]) != REG) 238: operands[1] = force_reg (SFmode, operands[1]); 239: } 240: 241: else if (GET_CODE (operands[1]) == CONST_DOUBLE) 242: operands[1] = force_const_mem (SFmode, operands[1]); 243: }") 244: 245: ;; 246: ;; provide two patterns with different predicates as we don't want combine 247: ;; to recombine a mem -> mem move 248: ;; 249: (define_insn "" 1.1.1.2 root 250: [(set (match_operand:SF 0 "register_operand" "=*rf") 251: (match_operand:SF 1 "nonimmediate_operand" "*rfm"))] 1.1 root 252: "" 253: "* 254: { 255: #define FP_REG_P(X) (GET_CODE (X) == REG && REGNO (X) >= 16) 256: 257: if (FP_REG_P (operands[0])) 258: { 259: if (FP_REG_P (operands[1])) /* f -> f */ 260: return \"movs %1,%0\"; 261: if (GET_CODE (operands[1]) == REG) /* r -> f */ 262: return 263: \"subq $8,sp\;storw %1,(sp)\;loads (sp),%0\;addq $8,sp\"; 264: return \"loads %1,%0\"; /* m -> f */ 265: } 266: 267: if (FP_REG_P (operands[1])) 268: { 269: if (GET_CODE (operands[0]) == REG) /* f -> r */ 270: return 271: \"subq $8,sp\;stors %1,(sp)\;loadw (sp),%0\;addq $8,sp\"; 272: abort (); 273: } 274: 275: if (GET_CODE (operands[1]) == MEM) /* m -> r */ 276: return \"loadw %1,%0\"; 277: 278: if (GET_CODE (operands[1]) == REG) /* r -> r */ 279: return \"movw %1,%0\"; 280: 281: abort (); 282: #undef FP_REG_P 283: }") 284: 285: (define_insn "" 286: [(set (match_operand:SF 0 "memory_operand" "=m") 1.1.1.2 root 287: (match_operand:SF 1 "register_operand" "*rf"))] 1.1 root 288: "" 289: "* 290: { 291: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) >= 16) 292: return \"stors %1,%0\"; /* f-> m */ 293: 294: return \"storw %1,%0\"; /* r -> m */ 295: }" 296: [(set_attr "type" "store")]) 297: 298: 299: (define_expand "movdi" 300: [(set (match_operand:DI 0 "general_operand" "") 301: (match_operand:DI 1 "general_operand" ""))] 302: "" 303: " 304: { 305: if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) != REG) 306: operands[1] = force_reg (DImode, operands[1]); 307: }") 308: 1.1.1.4 ! root 309: ;; If an operand is a MEM but not offsettable, we can't load it into 1.1.1.2 root 310: ;; a register, so we must force the third alternative to be the one 311: ;; reloaded. Hence we show the first as more expensive. 1.1 root 312: (define_insn "" 1.1.1.2 root 313: [(set (match_operand:DI 0 "register_operand" "=?r,r,r") 1.1 root 314: (match_operand:DI 1 "general_operand" "r,n,o"))] 315: "" 316: "* 317: { 318: rtx xoperands[2],yoperands[2]; 319: 320: xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 321: 322: if (which_alternative == 0) /* r -> r */ 323: { 324: output_asm_insn (\"movw %1,%0\", operands); 325: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 326: output_asm_insn (\"movw %1,%0\", xoperands); 327: return \"\"; 328: } 329: 330: if (which_alternative == 1) /* n -> r */ 331: { 332: if (GET_CODE (operands[1]) == CONST_INT) 333: { 334: output_asm_insn (\"loadi %1,%0\", operands); 335: output_asm_insn (\"loadq $0,%0\", xoperands); 336: return \"\"; 337: } 338: 339: if (GET_CODE (operands[1]) != CONST_DOUBLE) 340: abort (); 341: 342: yoperands[0] = operands[0]; 343: yoperands[1] = gen_rtx (CONST_INT, VOIDmode, 344: CONST_DOUBLE_LOW (operands[1])); 345: output_asm_insn (\"loadi %1,%0\", yoperands); 346: 347: xoperands[1] = gen_rtx (CONST_INT, VOIDmode, 348: CONST_DOUBLE_HIGH (operands[1])); 349: output_asm_insn (\"loadi %1,%0\", xoperands); 350: return \"\"; 351: } 352: /* m -> r */ 353: output_asm_insn (\"loadw %1,%0\", operands); 354: xoperands[1] = adj_offsettable_operand (operands[1], 4); 355: output_asm_insn (\"loadw %1,%0\", xoperands); 356: return \"\"; 357: }" 358: [(set_attr "type" "arith,arith,load") 359: (set_attr "cc" "clobber,clobber,clobber")]) 360: 361: (define_insn "" 362: [(set (match_operand:DI 0 "memory_operand" "=o") 363: (match_operand:DI 1 "register_operand" "r"))] 364: "" 365: "* 366: { 367: rtx xops[4]; 368: xops[0] = operands[0]; 369: xops[1] = adj_offsettable_operand (operands[0], 4); 370: xops[2] = operands[1]; 371: xops[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 372: output_asm_insn (\"storw %2,%0\;storw %3,%1\", xops); 373: return \"\"; 374: }" 375: [(set_attr "type" "store") 376: (set_attr "cc" "clobber")]) 377: 378: (define_expand "movsi" 379: [(set (match_operand:SI 0 "general_operand" "") 380: (match_operand:SI 1 "general_operand" ""))] 381: "" 382: " 383: { 384: if (GET_CODE (operands[0]) == MEM && 385: GET_CODE (operands[1]) != REG) 386: operands[1] = force_reg (SImode, operands[1]); 387: }") 388: 1.1.1.3 root 389: ;; Reject both args with `general_operand' if not reloading because a 390: ;; mem -> mem move that was split by 'movsi' can be recombined to 391: ;; mem -> mem by the combiner. 392: ;; 393: ;; As a pseudo register can end up in a stack slot during reloading we must 394: ;; allow a r->m move for the next pattern. 395: ;; The first predicate must be `general_operand' because a predicate must 396: ;; be true for each constraint. 397: ;; 398: (define_insn "" 399: [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,m") 400: (match_operand:SI 1 "general_operand" "r,m,n,i,r"))] 401: "reload_in_progress || register_operand (operands[0], SImode)" 1.1 root 402: "* 403: { 404: int val; 405: 406: if (which_alternative == 0) 407: return \"movw %1,%0\"; /* reg -> reg */ 408: 409: if (which_alternative == 1) 410: return \"loadw %1,%0\"; /* mem -> reg */ 411: 412: if (which_alternative == 2) 413: { 414: val = INTVAL (operands[1]); /* known const ->reg */ 415: 416: if (val == -1) 417: return \"notq $0,%0\"; 418: 419: if (val < 0 || val >= 16) 420: return \"loadi %1,%0\"; 421: 422: return \"loadq %1,%0\"; 423: } 424: 425: if (which_alternative == 3) /* unknown const */ 426: return \"loada %a1,%0\"; 1.1.1.3 root 427: 428: return \"storw %1,%0\"; 1.1 root 429: }" 1.1.1.3 root 430: [(set_attr "type" "arith,load,arith,load,store") 431: (set_attr "cc" "set2,change0,set1,change0,unchanged")]) 1.1 root 432: 433: 434: (define_insn "" 435: [(set (match_operand:SI 0 "memory_operand" "=m") 436: (match_operand:SI 1 "int_reg_operand" "r"))] 437: "" 438: "storw %1,%0" 439: [(set_attr "type" "store")]) 440: 441: ;; movhi 442: ;; 443: ;; loadh mem to reg 444: ;; storh reg to mem 445: ;; 446: ;; 447: (define_expand "movhi" 448: [(set (match_operand:HI 0 "general_operand" "") 449: (match_operand:HI 1 "general_operand" ""))] 450: "" 451: " 452: { 453: if (GET_CODE (operands[0]) == MEM 454: && ! register_operand (operands[1], HImode)) 455: operands[1] = force_reg (HImode, operands[1]); 456: }") 457: 458: 459: (define_insn "" 460: [(set (match_operand:HI 0 "register_operand" "=r,r,r") 461: (match_operand:HI 1 "general_operand" "r,m,n"))] 462: "" 463: "@ 464: movw %1,%0 465: loadh %1,%0 466: loadi %1,%0" 467: [(set_attr "type" "arith,load,arith")]) 468: 469: (define_insn "" 470: [(set (match_operand:HI 0 "memory_operand" "=m") 471: (match_operand:HI 1 "register_operand" "r"))] 472: "" 473: "storh %1,%0" 474: [(set_attr "type" "store")]) 475: 476: ;; movqi 477: ;; 478: ;; loadb mem to reg 479: ;; storb reg to mem 480: ;; 481: (define_expand "movqi" 482: [(set (match_operand:QI 0 "general_operand" "") 483: (match_operand:QI 1 "general_operand" ""))] 484: "" 485: " 486: { 487: if (GET_CODE (operands[0]) == MEM && 488: ! register_operand (operands[1], QImode)) 489: operands[1] = force_reg (QImode, operands[1]); 490: }") 491: 492: 493: (define_insn "" 494: [(set (match_operand:QI 0 "register_operand" "=r,r,r") 495: (match_operand:QI 1 "general_operand" "r,m,n"))] 496: "" 497: "@ 498: movw %1,%0 499: loadb %1,%0 500: loadi %1,%0" 501: [(set_attr "type" "arith,load,arith")]) 502: 503: (define_insn "" 504: [(set (match_operand:QI 0 "memory_operand" "=m") 505: (match_operand:QI 1 "register_operand" "r"))] 506: "" 507: "storb %1,%0" 508: [(set_attr "type" "store")]) 509: 510: 511: ;; 512: ;; block move 513: ;; 514: (define_expand "movstrsi" 515: [(parallel 516: [(set (match_operand:BLK 0 "memory_operand" "") 517: (match_operand:BLK 1 "memory_operand" "")) 518: (use (match_operand:SI 2 "general_operand" "")) 519: (use (match_operand:SI 3 "const_int_operand" "")) 520: (clobber (match_scratch:SI 4 "")) 521: (clobber (match_scratch:SI 5 "")) 522: (clobber (match_dup 6)) 523: (clobber (match_dup 7))])] 524: "" 525: " 526: { 527: rtx addr0, addr1; 528: 529: addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); 530: addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); 531: 532: operands[6] = addr0; 533: operands[7] = addr1; 534: 535: operands[0] = gen_rtx (MEM, BLKmode, addr0); 536: operands[1] = gen_rtx (MEM, BLKmode, addr1); 537: 538: if (GET_CODE (operands[2]) != CONST_INT) 539: operands[2] = force_reg (SImode, operands[2]); 540: }") 541: 542: ;; 543: ;; there is a problem with this insn in gcc-2.2.3 544: ;; (clobber (match_dup 2)) does not prevent use of this operand later 545: ;; we always use a scratch register and leave operand 2 unchanged 546: ;; 547: (define_insn "" 548: [(set (mem:BLK (match_operand:SI 0 "register_operand" "r")) 549: (mem:BLK (match_operand:SI 1 "register_operand" "r"))) 550: (use (match_operand:SI 2 "nonmemory_operand" "rn")) 551: (use (match_operand:SI 3 "const_int_operand" "n")) 552: (clobber (match_scratch:SI 4 "=r")) 553: (clobber (match_scratch:SI 5 "=r")) 554: (clobber (match_dup 0)) 555: (clobber (match_dup 1))] 556: "" 557: "* 558: { 559: extern void clipper_movstr (); 560: clipper_movstr (operands); 561: return \"\"; 562: }" 563: [(set_attr "cc" "clobber")]) 564: 565: 566: 567: ;; Extension and truncation insns. 568: (define_insn "extendhisi2" 569: [(set (match_operand:SI 0 "int_reg_operand" "=r,r") 570: (sign_extend:SI (match_operand:HI 1 "general_operand" "0,m")))] 571: "" 572: "@ 573: andi $65535,%0\;xori $32768,%0\;subi $32768,%0 574: loadh %1,%0" 575: [(set_attr "type" "arith,load")]) 576: 577: 578: (define_insn "extendqihi2" 579: [(set (match_operand:HI 0 "int_reg_operand" "=r,r") 580: (sign_extend:HI (match_operand:QI 1 "general_operand" "0,m")))] 581: "" 582: "@ 583: andi $255,%0\;xori $128,%0\;subi $128,%0 584: loadb %1,%0" 585: [(set_attr "type" "arith,load") 586: (set_attr "cc" "set1,change0")]) 587: 588: 589: (define_insn "extendqisi2" 590: [(set (match_operand:SI 0 "int_reg_operand" "=r,r") 591: (sign_extend:SI (match_operand:QI 1 "general_operand" "0,m")))] 592: "" 593: "@ 594: andi $255,%0\;xori $128,%0\;subi $128,%0 595: loadb %1,%0" 596: [(set_attr "type" "arith,load")]) 597: 598: 599: (define_insn "extendsfdf2" 600: [(set (match_operand:DF 0 "fp_reg_operand" "=f") 601: (float_extend:DF (match_operand:SF 1 "fp_reg_operand" "f")))] 602: "" 603: "cnvsd %1,%0") 604: 605: (define_insn "truncdfsf2" 606: [(set (match_operand:SF 0 "fp_reg_operand" "=f") 607: (float_truncate:SF (match_operand:DF 1 "fp_reg_operand" "f")))] 608: "" 609: "cnvds %1,%0") 610: 611: (define_insn "zero_extendhisi2" 612: [(set (match_operand:SI 0 "int_reg_operand" "=r,r") 613: (zero_extend:SI (match_operand:HI 1 "general_operand" "0,m")))] 614: "" 615: "@ 616: andi $65535,%0 617: loadhu %1,%0" 618: [(set_attr "type" "arith,load")]) 619: 620: 621: (define_insn "zero_extendqihi2" 622: [(set (match_operand:HI 0 "int_reg_operand" "=r,r") 623: (zero_extend:HI (match_operand:QI 1 "general_operand" "0,m")))] 624: "" 625: "@ 626: andi $255,%0 627: loadbu %1,%0" 628: [(set_attr "type" "arith,load") 629: (set_attr "cc" "clobber,clobber")]) 630: 631: 632: (define_insn "zero_extendqisi2" 633: [(set (match_operand:SI 0 "int_reg_operand" "=r,r") 634: (zero_extend:SI (match_operand:QI 1 "general_operand" "0,m")))] 635: "" 636: "@ 637: andi $255,%0 638: loadbu %1,%0" 639: [(set_attr "type" "arith,load")]) 640: 641: 642: 643: ;; Fix-to-float conversion insns. 644: 645: (define_insn "floatsisf2" 646: [(set (match_operand:SF 0 "fp_reg_operand" "=f") 647: (float:SF (match_operand:SI 1 "int_reg_operand" "r")))] 648: "" 649: "cnvws %1,%0") 650: 651: (define_insn "floatsidf2" 652: [(set (match_operand:DF 0 "fp_reg_operand" "=f") 653: (float:DF (match_operand:SI 1 "int_reg_operand" "r")))] 654: "" 655: "cnvwd %1,%0") 656: 657: 658: ;; Float-to-fix conversion insns. 659: 660: (define_insn "fix_truncsfsi2" 661: [(set (match_operand:SI 0 "int_reg_operand" "=r") 662: (fix:SI (fix:SF (match_operand:SF 1 "fp_reg_operand" "f"))))] 663: "" 664: "cnvtsw %1,%0") 665: 666: (define_insn "fix_truncdfsi2" 667: [(set (match_operand:SI 0 "int_reg_operand" "=r") 668: (fix:SI (fix:DF (match_operand:DF 1 "fp_reg_operand" "f"))))] 669: "" 670: "cnvtdw %1,%0") 671: 672: ;;- All kinds of add instructions. 673: 674: (define_insn "adddf3" 675: [(set (match_operand:DF 0 "fp_reg_operand" "=f") 676: (plus:DF (match_operand:DF 1 "fp_reg_operand" "0") 677: (match_operand:DF 2 "fp_reg_operand" "f")))] 678: "" 679: "addd %2,%0" 680: [(set_attr "type" "fp")]) 681: 682: 683: (define_insn "addsf3" 684: [(set (match_operand:SF 0 "fp_reg_operand" "=f") 685: (plus:SF (match_operand:SF 1 "fp_reg_operand" "0") 686: (match_operand:SF 2 "fp_reg_operand" "f")))] 687: "" 688: "adds %2,%0" 689: [(set_attr "type" "fp")]) 690: 691: (define_insn "adddi3" 692: [(set (match_operand:DI 0 "int_reg_operand" "=r") 693: (plus:DI (match_operand:DI 1 "int_reg_operand" "%0") 694: (match_operand:DI 2 "int_reg_operand" "r")))] 695: "" 696: "* 697: { 698: rtx xoperands[4]; 699: 700: xoperands[0] = operands[0]; 701: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 702: xoperands[2] = operands[2]; 703: xoperands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1); 704: output_asm_insn (\"addw %2,%0\;addwc %3,%1\", xoperands); 705: return \"\"; 706: }" 707: [(set_attr "type" "arith") 708: (set_attr "cc" "clobber")]) 709: 710: (define_insn "addsi3" 711: [(set (match_operand:SI 0 "int_reg_operand" "=r,r,r") 712: (plus:SI (match_operand:SI 1 "int_reg_operand" "%0,r,r") 713: (match_operand:SI 2 "nonmemory_operand" "rn,0,rn")))] 714: "" 715: "* 716: { 717: if (which_alternative == 2) /* 3 address version */ 718: { 719: if (GET_CODE (operands[2]) == CONST_INT) 720: return \"loada %a2(%1),%0\"; 721: return \"loada [%2](%1),%0\"; 722: } 723: /* 2 address version */ 724: if (GET_CODE (operands[2]) == CONST_INT) 725: { 726: int val = INTVAL (operands[2]); 727: 728: if (val >= 16 || val == 0x80000000) 729: return \"addi %2,%0\"; 730: 731: if (val < 0) /* change to sub */ 732: { 733: rtx xops[2]; 734: 735: val = -val; 736: 737: xops[0] = operands[0]; 738: xops[1] = gen_rtx (CONST_INT, VOIDmode, val); 739: 740: if (val >= 16) 741: output_asm_insn (\"subi %1,%0\", xops); 742: else 743: output_asm_insn (\"subq %1,%0\", xops); 744: 745: return \"\"; 746: } 747: 748: return \"addq %2,%0\"; 749: } 750: 751: if (which_alternative == 0) 752: return \"addw %2,%0\"; 753: 754: return \"addw %1,%0\"; 755: }" 756: [(set_attr "type" "arith,arith,arith") 757: (set_attr "cc" "set1,set1,change0")]) 758: 759: 760: ;;- All kinds of subtract instructions. 761: 762: (define_insn "subdi3" 763: [(set (match_operand:DI 0 "int_reg_operand" "=r") 1.1.1.3 root 764: (minus:DI (match_operand:DI 1 "int_reg_operand" "0") 1.1 root 765: (match_operand:DI 2 "int_reg_operand" "r")))] 766: "" 767: "* 768: { 769: rtx xoperands[4]; 770: 771: xoperands[0] = operands[0]; 772: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 773: xoperands[2] = operands[2]; 774: xoperands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1); 775: output_asm_insn (\"subw %2,%0\;subwc %3,%1\", xoperands); 776: return \"\"; 777: }" 778: [(set_attr "type" "arith") 779: (set_attr "cc" "clobber")]) 780: 781: (define_insn "subsi3" 782: [(set (match_operand:SI 0 "int_reg_operand" "=r") 783: (minus:SI (match_operand:SI 1 "int_reg_operand" "0") 784: (match_operand:SI 2 "nonmemory_operand" "rn")))] 785: "" 786: "* 787: { 788: if (GET_CODE (operands[2]) == CONST_INT) 789: { 790: int val = INTVAL (operands[2]); 791: 792: if (val < 0 || val >= 16) 793: return \"subi %2,%0\"; 794: else 795: return \"subq %2,%0\"; 796: } 797: 798: return \"subw %2,%0\"; 799: }" 800: [(set_attr "type" "arith")]) 801: 802: (define_insn "subdf3" 803: [(set (match_operand:DF 0 "fp_reg_operand" "=f") 804: (minus:DF (match_operand:DF 1 "fp_reg_operand" "0") 805: (match_operand:DF 2 "fp_reg_operand" "f")))] 806: "" 807: "subd %2,%0" 808: [(set_attr "type" "fp")]) 809: 810: (define_insn "subsf3" 811: [(set (match_operand:SF 0 "fp_reg_operand" "=f") 812: (minus:SF (match_operand:SF 1 "fp_reg_operand" "0") 813: (match_operand:SF 2 "fp_reg_operand" "f")))] 814: "" 815: "subs %2,%0" 816: [(set_attr "type" "fp")]) 817: 818: 819: ;;- Multiply instructions. 820: 821: (define_insn "muldf3" 822: [(set (match_operand:DF 0 "fp_reg_operand" "=f") 823: (mult:DF (match_operand:DF 1 "fp_reg_operand" "0") 824: (match_operand:DF 2 "fp_reg_operand" "f")))] 825: "" 826: "muld %2,%0" 827: [(set_attr "type" "fp")]) 828: 829: (define_insn "mulsf3" 830: [(set (match_operand:SF 0 "fp_reg_operand" "=f") 831: (mult:SF (match_operand:SF 1 "fp_reg_operand" "0") 832: (match_operand:SF 2 "fp_reg_operand" "f")))] 833: "" 834: "muls %2,%0" 835: [(set_attr "type" "fp")]) 836: 837: (define_insn "mulsidi3" 838: [(set (match_operand:DI 0 "int_reg_operand" "=r") 839: (mult:DI (sign_extend:DI (match_operand:SI 1 "int_reg_operand" "%0")) 840: (sign_extend:DI (match_operand:SI 2 "int_reg_operand" "r"))))] 841: "" 842: "mulwx %2,%0" 843: [(set_attr "type" "arith") 844: (set_attr "cc" "clobber")]) 845: 846: (define_insn "umulsidi3" 847: [(set (match_operand:DI 0 "int_reg_operand" "=r") 848: (mult:DI (zero_extend:DI (match_operand:SI 1 "int_reg_operand" "%0")) 849: (zero_extend:DI (match_operand:SI 2 "int_reg_operand" "r"))))] 850: "" 851: "mulwux %2,%0" 852: [(set_attr "type" "arith") 853: (set_attr "cc" "clobber")]) 854: 855: (define_insn "mulsi3" 856: [(set (match_operand:SI 0 "int_reg_operand" "=r") 857: (mult:SI (match_operand:SI 1 "int_reg_operand" "%0") 858: (match_operand:SI 2 "int_reg_operand" "r")))] 859: "" 860: "mulw %2,%0" 861: [(set_attr "type" "arith") 862: (set_attr "cc" "clobber")]) 863: 864: 865: ;;- Divide and mod instructions. 866: 867: (define_insn "divdf3" 868: [(set (match_operand:DF 0 "fp_reg_operand" "=f") 869: (div:DF (match_operand:DF 1 "fp_reg_operand" "0") 870: (match_operand:DF 2 "fp_reg_operand" "f")))] 871: "" 872: "divd %2,%0" 873: [(set_attr "type" "fp")]) 874: 875: (define_insn "divsf3" 876: [(set (match_operand:SF 0 "fp_reg_operand" "=f") 877: (div:SF (match_operand:SF 1 "fp_reg_operand" "0") 878: (match_operand:SF 2 "fp_reg_operand" "f")))] 879: "" 880: "divs %2,%0" 881: [(set_attr "type" "fp")]) 882: 883: (define_insn "divsi3" 884: [(set (match_operand:SI 0 "int_reg_operand" "=r") 885: (div:SI (match_operand:SI 1 "int_reg_operand" "0") 886: (match_operand:SI 2 "int_reg_operand" "r")))] 887: "" 888: "divw %2,%0" 889: [(set_attr "type" "arith") 890: (set_attr "cc" "clobber")]) 891: 892: (define_insn "udivsi3" 893: [(set (match_operand:SI 0 "int_reg_operand" "=r") 894: (udiv:SI (match_operand:SI 1 "int_reg_operand" "0") 895: (match_operand:SI 2 "int_reg_operand" "r")))] 896: "" 897: "divwu %2,%0" 898: [(set_attr "type" "arith") 899: (set_attr "cc" "clobber")]) 900: 901: 902: (define_insn "modsi3" 903: [(set (match_operand:SI 0 "int_reg_operand" "=r") 904: (mod:SI (match_operand:SI 1 "int_reg_operand" "0") 905: (match_operand:SI 2 "int_reg_operand" "r")))] 906: "" 907: "modw %2,%0" 908: [(set_attr "type" "arith") 909: (set_attr "cc" "clobber")]) 910: 911: (define_insn "umodsi3" 912: [(set (match_operand:SI 0 "int_reg_operand" "=r") 913: (umod:SI (match_operand:SI 1 "int_reg_operand" "0") 914: (match_operand:SI 2 "int_reg_operand" "r")))] 915: "" 916: "modwu %2,%0" 917: [(set_attr "type" "arith") 918: (set_attr "cc" "clobber")]) 919: 920: ;; 921: ;; bit and/or instructions 922: ;; 923: (define_insn "andsi3" 924: [(set (match_operand:SI 0 "int_reg_operand" "=r,r") 925: (and:SI (match_operand:SI 1 "int_reg_operand" "%0,0") 926: (match_operand:SI 2 "nonmemory_operand" "r,n")))] 927: "" 928: "@ 929: andw %2,%0 930: andi %2,%0" 931: [(set_attr "type" "arith")]) 932: 933: (define_insn "iorsi3" 934: [(set (match_operand:SI 0 "int_reg_operand" "=r,r") 935: (ior:SI (match_operand:SI 1 "int_reg_operand" "%0,0") 936: (match_operand:SI 2 "nonmemory_operand" "r,n")))] 937: "" 938: "@ 939: orw %2,%0 940: ori %2,%0" 941: [(set_attr "type" "arith")]) 942: 943: (define_insn "xorsi3" 944: [(set (match_operand:SI 0 "int_reg_operand" "=r,r") 945: (xor:SI (match_operand:SI 1 "int_reg_operand" "%0,0") 946: (match_operand:SI 2 "nonmemory_operand" "r,n")))] 947: "" 948: "@ 949: xorw %2,%0 950: xori %2,%0" 951: [(set_attr "type" "arith")]) 952: 953: (define_insn "negdf2" 954: [(set (match_operand:DF 0 "fp_reg_operand" "=f") 955: (neg:DF (match_operand:DF 1 "fp_reg_operand" "f")))] 956: "" 957: "negd %1,%0" 958: [(set_attr "type" "fp")]) 959: 960: (define_insn "negsf2" 961: [(set (match_operand:SF 0 "fp_reg_operand" "=f") 962: (neg:SF (match_operand:SF 1 "fp_reg_operand" "f")))] 963: "" 964: "negs %1,%0" 965: [(set_attr "type" "fp")]) 966: 967: (define_insn "negsi2" 968: [(set (match_operand:SI 0 "int_reg_operand" "=r") 969: (neg:SI (match_operand:SI 1 "int_reg_operand" "r")))] 970: "" 971: "negw %1,%0" 972: [(set_attr "type" "arith")]) 973: 974: 975: (define_insn "one_cmplsi2" 976: [(set (match_operand:SI 0 "int_reg_operand" "=r") 977: (not:SI (match_operand:SI 1 "int_reg_operand" "r")))] 978: "" 979: "notw %1,%0" 980: [(set_attr "type" "arith")]) 981: 982: 983: 984: ;; Right shift on the clipper works by negating the shift count, 985: ;; then emitting a right shift with the shift count negated. This means 986: ;; that all actual shift counts in the RTL will be positive. 987: 988: (define_expand "ashrdi3" 989: [(set (match_operand:DI 0 "int_reg_operand" "") 990: (ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "") 991: (match_operand:SI 2 "nonmemory_operand" "")))] 992: "" 993: " 994: { 995: if (GET_CODE (operands[2]) != CONST_INT) 996: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); 997: }") 998: 999: (define_insn "" 1000: [(set (match_operand:DI 0 "int_reg_operand" "=r") 1001: (ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "0") 1002: (match_operand:SI 2 "const_int_operand" "n")))] 1003: "" 1004: "shali $%n2,%0" 1005: [(set_attr "type" "arith")]) 1006: 1007: (define_insn "" 1008: [(set (match_operand:DI 0 "int_reg_operand" "=r") 1009: (ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "0") 1010: (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))] 1011: "" 1012: "shal %2,%0" 1013: [(set_attr "type" "arith")]) 1014: 1015: (define_expand "ashrsi3" 1016: [(set (match_operand:SI 0 "int_reg_operand" "") 1017: (ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "") 1018: (match_operand:SI 2 "nonmemory_operand" "")))] 1019: "" 1020: " 1021: { 1022: if (GET_CODE (operands[2]) != CONST_INT) 1023: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); 1024: }") 1025: 1026: (define_insn "" 1027: [(set (match_operand:SI 0 "int_reg_operand" "=r") 1028: (ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "0") 1029: (match_operand:SI 2 "const_int_operand" "n")))] 1030: "" 1031: "shai $%n2,%0" 1032: [(set_attr "type" "arith")]) 1033: 1034: (define_insn "" 1035: [(set (match_operand:SI 0 "int_reg_operand" "=r") 1036: (ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "0") 1037: (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))] 1038: "" 1039: "shaw %2,%0" 1040: [(set_attr "type" "arith")]) 1041: 1042: ;; 1043: ;; left shift 1044: ;; 1045: 1046: (define_insn "ashldi3" 1047: [(set (match_operand:DI 0 "int_reg_operand" "=r,r") 1048: (ashift:DI (match_operand:DI 1 "int_reg_operand" "0,0") 1049: (match_operand:SI 2 "nonmemory_operand" "r,n")))] 1050: "" 1051: "@ 1052: shal %2,%0 1053: shali %2,%0" 1054: [(set_attr "type" "arith")]) 1055: 1056: 1057: (define_insn "ashlsi3" 1058: [(set (match_operand:SI 0 "int_reg_operand" "=r,r") 1059: (ashift:SI (match_operand:SI 1 "int_reg_operand" "0,0") 1060: (match_operand:SI 2 "nonmemory_operand" "r,n")))] 1061: "" 1062: "* 1063: { 1064: int val; 1065: 1066: if (which_alternative == 0) 1067: return \"shaw %2,%0\"; 1068: 1069: val = INTVAL (operands[2]); 1070: 1071: if (val == 2) 1072: return \"addw %0,%0\;addw %0,%0\"; 1073: 1074: if (val == 1) 1075: return \"addw %0,%0\"; 1076: 1077: return \"shai %2,%0\"; 1078: }" 1079: [(set_attr "type" "arith")]) 1080: 1081: ;; 1082: ;; logical shift 1083: ;; 1084: 1085: (define_expand "lshrdi3" 1086: [(set (match_operand:DI 0 "int_reg_operand" "") 1087: (lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "") 1088: (match_operand:SI 2 "nonmemory_operand" "")))] 1089: "" 1090: " 1091: { 1092: if (GET_CODE (operands[2]) != CONST_INT) 1093: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); 1094: }") 1095: 1096: (define_insn "" 1097: [(set (match_operand:DI 0 "int_reg_operand" "=r") 1098: (lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "0") 1099: (match_operand:SI 2 "const_int_operand" "n")))] 1100: "" 1101: "shlli $%n2,%0" 1102: [(set_attr "type" "arith")]) 1103: 1104: (define_insn "" 1105: [(set (match_operand:DI 0 "int_reg_operand" "=r") 1106: (lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "0") 1107: (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))] 1108: "" 1109: "shll %2,%0" 1110: [(set_attr "type" "arith")]) 1111: 1112: (define_expand "lshrsi3" 1113: [(set (match_operand:SI 0 "int_reg_operand" "") 1114: (lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "") 1115: (match_operand:SI 2 "nonmemory_operand" "")))] 1116: "" 1117: " 1118: { 1119: if (GET_CODE (operands[2]) != CONST_INT) 1120: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); 1121: }") 1122: 1123: (define_insn "" 1124: [(set (match_operand:SI 0 "int_reg_operand" "=r") 1125: (lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "0") 1126: (match_operand:SI 2 "const_int_operand" "n")))] 1127: "" 1128: "shli $%n2,%0" 1129: [(set_attr "type" "arith")]) 1130: 1131: (define_insn "" 1132: [(set (match_operand:SI 0 "int_reg_operand" "=r") 1133: (lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "0") 1134: (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))] 1135: "" 1136: "shlw %2,%0" 1137: [(set_attr "type" "arith")]) 1138: 1139: 1140: ;; 1141: ;; rotate insn 1142: ;; 1143: (define_expand "rotrdi3" 1144: [(set (match_operand:DI 0 "int_reg_operand" "") 1145: (rotatert:DI (match_operand:DI 1 "int_reg_operand" "") 1146: (match_operand:SI 2 "nonmemory_operand" "")))] 1147: "" 1148: " 1149: { 1150: if (GET_CODE (operands[2]) != CONST_INT) 1151: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); 1152: }") 1153: 1154: (define_insn "" 1155: [(set (match_operand:DI 0 "int_reg_operand" "=r") 1156: (rotatert:DI (match_operand:DI 1 "int_reg_operand" "0") 1157: (match_operand:SI 2 "const_int_operand" "n")))] 1158: "" 1159: "rotli $%n2,%0" 1160: [(set_attr "type" "arith")]) 1161: 1162: (define_insn "" 1163: [(set (match_operand:DI 0 "int_reg_operand" "=r") 1164: (rotatert:DI (match_operand:DI 1 "int_reg_operand" "0") 1165: (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))] 1166: "" 1167: "rotl %2,%0" 1168: [(set_attr "type" "arith")]) 1169: 1170: (define_expand "rotrsi3" 1171: [(set (match_operand:SI 0 "int_reg_operand" "") 1172: (rotatert:SI (match_operand:SI 1 "int_reg_operand" "") 1173: (match_operand:SI 2 "nonmemory_operand" "")))] 1174: "" 1175: " 1176: { 1177: if (GET_CODE (operands[2]) != CONST_INT) 1178: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); 1179: }") 1180: 1181: (define_insn "" 1182: [(set (match_operand:SI 0 "int_reg_operand" "=r") 1183: (rotatert:SI (match_operand:SI 1 "int_reg_operand" "0") 1184: (match_operand:SI 2 "const_int_operand" "n")))] 1185: "" 1186: "roti $%n2,%0" 1187: [(set_attr "type" "arith")]) 1188: 1189: (define_insn "" 1190: [(set (match_operand:SI 0 "int_reg_operand" "=r") 1191: (rotatert:SI (match_operand:SI 1 "int_reg_operand" "0") 1192: (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))] 1193: "" 1194: "rotw %2,%0" 1195: [(set_attr "type" "arith")]) 1196: 1197: (define_insn "rotldi3" 1198: [(set (match_operand:DI 0 "int_reg_operand" "=r,r") 1199: (rotate:DI (match_operand:DI 1 "int_reg_operand" "0,0") 1200: (match_operand:SI 2 "nonmemory_operand" "r,n")))] 1201: "" 1202: "@ 1203: rotl %2,%0 1204: rotli %2,%0" 1205: [(set_attr "type" "arith")]) 1206: 1207: (define_insn "rotlsi3" 1208: [(set (match_operand:SI 0 "int_reg_operand" "=r,r") 1209: (rotate:SI (match_operand:SI 1 "int_reg_operand" "0,0") 1210: (match_operand:SI 2 "nonmemory_operand" "r,n")))] 1211: "" 1212: "@ 1213: rotw %2,%0 1214: roti %2,%0" 1215: [(set_attr "type" "arith")]) 1216: 1217: 1218: ;; 1219: ;; jump and branch insns 1220: ;; 1221: (define_insn "jump" 1222: [(set (pc) 1223: (label_ref (match_operand 0 "" "")))] 1224: "" 1225: "b %l0" 1226: [(set_attr "type" "branch")]) 1227: 1228: (define_insn "tablejump" 1229: [(set (pc) (match_operand:SI 0 "register_operand" "r")) 1230: (use (label_ref (match_operand 1 "" "")))] 1231: "" 1232: "b (%0)" 1233: [(set_attr "type" "branch")]) 1234: 1235: (define_insn "beq" 1236: [(set (pc) 1237: (if_then_else (eq (cc0) 1238: (const_int 0)) 1239: (label_ref (match_operand 0 "" "")) 1240: (pc)))] 1241: "" 1242: "breq %l0" 1243: [(set_attr "type" "branch")]) 1244: 1245: (define_insn "bne" 1246: [(set (pc) 1247: (if_then_else (ne (cc0) 1248: (const_int 0)) 1249: (label_ref (match_operand 0 "" "")) 1250: (pc)))] 1251: "" 1252: "brne %l0" 1253: [(set_attr "type" "branch")]) 1254: 1255: (define_insn "bgt" 1256: [(set (pc) 1257: (if_then_else (gt (cc0) 1258: (const_int 0)) 1259: (label_ref (match_operand 0 "" "")) 1260: (pc)))] 1261: "" 1262: "brgt %l0" 1263: [(set_attr "type" "branch")]) 1264: 1265: (define_insn "bgtu" 1266: [(set (pc) 1267: (if_then_else (gtu (cc0) 1268: (const_int 0)) 1269: (label_ref (match_operand 0 "" "")) 1270: (pc)))] 1271: "" 1272: "brgtu %l0" 1273: [(set_attr "type" "branch")]) 1274: 1275: (define_insn "blt" 1276: [(set (pc) 1277: (if_then_else (lt (cc0) 1278: (const_int 0)) 1279: (label_ref (match_operand 0 "" "")) 1280: (pc)))] 1281: "" 1282: "brlt %l0" 1283: [(set_attr "type" "branch")]) 1284: 1285: (define_insn "bltu" 1286: [(set (pc) 1287: (if_then_else (ltu (cc0) 1288: (const_int 0)) 1289: (label_ref (match_operand 0 "" "")) 1290: (pc)))] 1291: "" 1292: "brltu %l0" 1293: [(set_attr "type" "branch")]) 1294: 1295: (define_insn "bge" 1296: [(set (pc) 1297: (if_then_else (ge (cc0) 1298: (const_int 0)) 1299: (label_ref (match_operand 0 "" "")) 1300: (pc)))] 1301: "" 1302: "brge %l0" 1303: [(set_attr "type" "branch")]) 1304: 1305: (define_insn "bgeu" 1306: [(set (pc) 1307: (if_then_else (geu (cc0) 1308: (const_int 0)) 1309: (label_ref (match_operand 0 "" "")) 1310: (pc)))] 1311: "" 1312: "brgeu %l0" 1313: [(set_attr "type" "branch")]) 1314: 1315: (define_insn "ble" 1316: [(set (pc) 1317: (if_then_else (le (cc0) 1318: (const_int 0)) 1319: (label_ref (match_operand 0 "" "")) 1320: (pc)))] 1321: "" 1322: "brle %l0" 1323: [(set_attr "type" "branch")]) 1324: 1325: (define_insn "bleu" 1326: [(set (pc) 1327: (if_then_else (leu (cc0) 1328: (const_int 0)) 1329: (label_ref (match_operand 0 "" "")) 1330: (pc)))] 1331: "" 1332: "brleu %l0" 1333: [(set_attr "type" "branch")]) 1334: 1335: ;; Recognize reversed jumps. 1336: (define_insn "" 1337: [(set (pc) 1338: (if_then_else (match_operator 0 "comparison_operator" 1339: [(cc0) 1340: (const_int 0)]) 1341: (pc) 1342: (label_ref (match_operand 1 "" ""))))] 1343: "" 1344: "br%C0 %l1" ; %C0 negates condition 1345: [(set_attr "type" "branch")]) 1346: 1347: ;; 1348: ;; call instructions 1349: ;; 1350: (define_insn "call" 1351: [(call (match_operand:QI 0 "general_operand" "m") 1352: (match_operand:SI 1 "general_operand" ""))] 1353: ;; Operand 1 not used on the clipper. 1354: "" 1355: "call sp,%0") 1356: 1357: (define_insn "call_value" 1358: [(set (match_operand 0 "" "=rf") 1359: (call (match_operand:QI 1 "general_operand" "m") 1360: (match_operand:SI 2 "general_operand" "g")))] 1361: ;; Operand 2 not used on the clipper 1362: "" 1363: "call sp,%1") 1364: 1365: (define_insn "indirect_jump" 1366: [(set (pc) (match_operand:SI 0 "register_operand" "r"))] 1367: "" 1368: "b (%0)" 1369: [(set_attr "type" "branch")]) 1370: 1371: 1372: (define_insn "nop" 1373: [(const_int 0)] 1374: "" 1375: "noop" 1376: [(set_attr "type" "arith") 1377: (set_attr "cc" "unchanged")]) 1378: 1379: 1380: 1381: ;; while (--foo >= 0) 1382: ;; 1383: ;; Combiners for 'decrement test and branch' do not work for clipper. 1384: ;; These patters are jump_insns that do not allow output reloads and clipper 1385: ;; can only decrement and test registers. 1386: ;;
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.