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1.1 ! root 1: ;;- Machine description for GNU compiler ! 2: ;;- Convex Version ! 3: ;; Copyright (C) 1989 Free Software Foundation, Inc. ! 4: ! 5: ;; This file is part of GNU CC. ! 6: ! 7: ;; GNU CC is free software; you can redistribute it and/or modify ! 8: ;; it under the terms of the GNU General Public License as published by ! 9: ;; the Free Software Foundation; either version 1, or (at your option) ! 10: ;; any later version. ! 11: ! 12: ;; GNU CC is distributed in the hope that it will be useful, ! 13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ! 14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! 15: ;; GNU General Public License for more details. ! 16: ! 17: ;; You should have received a copy of the GNU General Public License ! 18: ;; along with GNU CC; see the file COPYING. If not, write to ! 19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ! 20: ! 21: ! 22: ;;- Instruction patterns. When multiple patterns apply, ! 23: ;;- the first one in the file is chosen. ! 24: ;;- ! 25: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ! 26: ;;- ! 27: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code ! 28: ;;- updates for most instructions. ! 29: ! 30: ;; Put tstsi first among test insns so it matches a CONST_INT operand. ! 31: ! 32: (define_insn "tstsi" ! 33: [(set (cc0) ! 34: (match_operand:SI 0 "register_operand" "r"))] ! 35: "" ! 36: "* return set_cmp (operands[0], const0_rtx, 'w');") ! 37: ! 38: (define_insn "tsthi" ! 39: [(set (cc0) ! 40: (match_operand:HI 0 "register_operand" "r"))] ! 41: "" ! 42: "* return set_cmp (operands[0], const0_rtx, 'h');") ! 43: ! 44: (define_expand "tstqi" ! 45: [(set (match_dup 1) ! 46: (sign_extend:SI (match_operand:QI 0 "register_operand" "r"))) ! 47: (set (cc0) ! 48: (match_dup 1))] ! 49: "" ! 50: "operands[1] = gen_reg_rtx (SImode);") ! 51: ! 52: (define_insn "tstdi" ! 53: [(set (cc0) ! 54: (match_operand:DI 0 "register_operand" "d")) ! 55: (clobber (reg:DI 1))] ! 56: "" ! 57: "* ! 58: { ! 59: output_asm_insn (\"ld.l #0,s1\"); ! 60: return set_cmp (operands[0], gen_rtx (REG, DImode, 1), 'l'); ! 61: }") ! 62: ! 63: (define_expand "tstdf" ! 64: [(set (cc0) ! 65: (compare (match_operand:DF 0 "register_operand" "d") ! 66: (match_dup 1)))] ! 67: "" ! 68: "operands[1] = force_reg (DFmode, dconst0_rtx);") ! 69: ! 70: (define_insn "tstsf" ! 71: [(set (cc0) ! 72: (match_operand:SF 0 "register_operand" "d"))] ! 73: "" ! 74: "* return set_cmp (operands[0], fconst0_rtx, 's');") ! 75: ! 76: ;; Put cmpsi first among compare insns so it matches two CONST_INT operands. ! 77: ! 78: (define_insn "cmpsi" ! 79: [(set (cc0) ! 80: (compare (match_operand:SI 0 "nonmemory_operand" "d,a,i,r") ! 81: (match_operand:SI 1 "nonmemory_operand" "d,a,r,i")))] ! 82: "" ! 83: "* return set_cmp (operands[0], operands[1], 'w');") ! 84: ! 85: (define_insn "cmphi" ! 86: [(set (cc0) ! 87: (compare (match_operand:HI 0 "nonmemory_operand" "d,a,r,i") ! 88: (match_operand:HI 1 "nonmemory_operand" "d,a,i,r")))] ! 89: "" ! 90: "* return set_cmp (operands[0], operands[1], 'h');") ! 91: ! 92: (define_insn "" ! 93: [(set (cc0) ! 94: (compare (sign_extend:SI (match_operand:QI 0 "register_operand" "d")) ! 95: (sign_extend:SI (match_operand:QI 1 "register_operand" "d"))))] ! 96: "" ! 97: "* return set_cmp (operands[0], operands[1], 'b');") ! 98: ! 99: (define_insn "cmpdi" ! 100: [(set (cc0) ! 101: (compare (match_operand:DI 0 "register_operand" "d") ! 102: (match_operand:DI 1 "register_operand" "d")))] ! 103: "" ! 104: "* return set_cmp (operands[0], operands[1], 'l');") ! 105: ! 106: (define_insn "cmpdf" ! 107: [(set (cc0) ! 108: (compare (match_operand:DF 0 "register_operand" "d") ! 109: (match_operand:DF 1 "register_operand" "d")))] ! 110: "" ! 111: "* return set_cmp (operands[0], operands[1], 'd');") ! 112: ! 113: (define_insn "cmpsf" ! 114: [(set (cc0) ! 115: (compare (match_operand:SF 0 "nonmemory_operand" "dF,d") ! 116: (match_operand:SF 1 "nonmemory_operand" "d,F")))] ! 117: "" ! 118: "* return set_cmp (operands[0], operands[1], 's');") ! 119: ! 120: (define_insn "movdf" ! 121: [(set (match_operand:DF 0 "general_operand" "=g,d") ! 122: (match_operand:DF 1 "general_operand" "d,gG"))] ! 123: "" ! 124: "* ! 125: { ! 126: if (push_operand (operands[0], DFmode)) ! 127: return \"psh.l %1\"; ! 128: else if (GET_CODE (operands[0]) == MEM) ! 129: return \"st.l %1,%0\"; ! 130: else if (GET_CODE (operands[1]) == REG) ! 131: return \"mov %1,%0\"; ! 132: else if (GET_CODE (operands[1]) == CONST_DOUBLE && LD_D_P (operands[1])) ! 133: { ! 134: operands[1] = gen_rtx (CONST_INT, VOIDmode, ! 135: const_double_high_int (operands[1])); ! 136: return \"ld.d %1,%0\"; ! 137: } ! 138: else ! 139: return \"ld.l %1,%0\"; ! 140: }") ! 141: ! 142: (define_insn "movsf" ! 143: [(set (match_operand:SF 0 "general_operand" "=g,d") ! 144: (match_operand:SF 1 "general_operand" "d,gF"))] ! 145: "" ! 146: "* ! 147: { ! 148: if (push_operand (operands[0], SFmode)) ! 149: return \"psh.w %1\"; ! 150: else if (GET_CODE (operands[0]) == MEM) ! 151: return \"st.s %1,%0\"; ! 152: else if (GET_CODE (operands[1]) == REG) ! 153: return \"mov.s %1,%0\"; ! 154: else ! 155: return \"ld.s %1,%0\"; ! 156: }") ! 157: ! 158: (define_insn "movdi" ! 159: [(set (match_operand:DI 0 "general_operand" "=g,d") ! 160: (match_operand:DI 1 "general_operand" "d,gG"))] ! 161: "" ! 162: "* ! 163: { ! 164: if (push_operand (operands[0], DImode)) ! 165: return \"psh.l %1\"; ! 166: else if (GET_CODE (operands[0]) == MEM) ! 167: return \"st.l %1,%0\"; ! 168: else if (GET_CODE (operands[1]) == REG) ! 169: return \"mov %1,%0\"; ! 170: else if (GET_CODE (operands[1]) == CONST_DOUBLE && LD_D_P (operands[1])) ! 171: { ! 172: operands[1] = gen_rtx (CONST_INT, VOIDmode, ! 173: const_double_high_int (operands[1])); ! 174: return \"ld.d %1,%0\"; ! 175: } ! 176: else ! 177: return \"ld.l %1,%0\"; ! 178: }") ! 179: ! 180: ;; Special case of movsi, needed to express A-reg preference. ! 181: ! 182: (define_insn "" ! 183: [(set (match_operand:SI 0 "push_operand" "=<") ! 184: (plus:SI (match_operand:SI 1 "register_operand" "a") ! 185: (match_operand:SI 2 "immediate_operand" "i")))] ! 186: "operands[1] != stack_pointer_rtx" ! 187: "pshea %a2(%1)") ! 188: ! 189: (define_insn "movsi" ! 190: [(set (match_operand:SI 0 "general_operand" "=g,r,<") ! 191: (match_operand:SI 1 "general_operand" "r,g,io"))] ! 192: "" ! 193: "* ! 194: { ! 195: if (push_operand (operands[0], SImode)) ! 196: { ! 197: if (GET_CODE (operands[1]) == REG) ! 198: return \"psh.w %1\"; ! 199: else ! 200: return \"pshea %a1\"; ! 201: } ! 202: if (GET_CODE (operands[0]) == MEM) ! 203: return \"st.w %1,%0\"; ! 204: if (GET_CODE (operands[1]) != REG) ! 205: return \"ld.w %1,%0\"; ! 206: if (S_REG_P (operands[0]) && S_REG_P (operands[1])) ! 207: return \"mov.w %1,%0\"; ! 208: return \"mov %1,%0\"; ! 209: }") ! 210: ! 211: (define_insn "movhi" ! 212: [(set (match_operand:HI 0 "general_operand" "=g,r") ! 213: (match_operand:HI 1 "general_operand" "r,g"))] ! 214: "" ! 215: "* ! 216: { ! 217: if (push_operand (operands[0], HImode)) ! 218: abort (); ! 219: else if (GET_CODE (operands[0]) == MEM) ! 220: return \"st.h %1,%0\"; ! 221: else if (GET_CODE (operands[1]) == REG) ! 222: { ! 223: if (S_REG_P (operands[0]) && S_REG_P (operands[1])) ! 224: return \"mov.w %1,%0\"; ! 225: else ! 226: return \"mov %1,%0\"; ! 227: } ! 228: else if (GET_CODE (operands[1]) == CONST_INT) ! 229: return \"ld.w %1,%0\"; ! 230: else ! 231: return \"ld.h %1,%0\"; ! 232: }") ! 233: ! 234: (define_insn "movqi" ! 235: [(set (match_operand:QI 0 "general_operand" "=g,r") ! 236: (match_operand:QI 1 "general_operand" "r,g"))] ! 237: "" ! 238: "* ! 239: { ! 240: if (push_operand (operands[0], QImode)) ! 241: abort (); ! 242: else if (GET_CODE (operands[0]) == MEM) ! 243: return \"st.b %1,%0\"; ! 244: else if (GET_CODE (operands[1]) == REG) ! 245: { ! 246: if (S_REG_P (operands[0]) && S_REG_P (operands[1])) ! 247: return \"mov.w %1,%0\"; ! 248: else ! 249: return \"mov %1,%0\"; ! 250: } ! 251: else if (GET_CODE (operands[1]) == CONST_INT) ! 252: return \"ld.w %1,%0\"; ! 253: else ! 254: return \"ld.b %1,%0\"; ! 255: }") ! 256: ! 257: ;; Extension and truncation insns. ! 258: ;; Those for integer source operand ! 259: ;; are ordered widest source type first. ! 260: ! 261: (define_insn "truncsiqi2" ! 262: [(set (match_operand:QI 0 "register_operand" "=d,a") ! 263: (truncate:QI (match_operand:SI 1 "register_operand" "d,a")))] ! 264: "" ! 265: "cvtw.b %1,%0") ! 266: ! 267: (define_insn "truncsihi2" ! 268: [(set (match_operand:HI 0 "register_operand" "=d,a") ! 269: (truncate:HI (match_operand:SI 1 "register_operand" "d,a")))] ! 270: "" ! 271: "cvtw.h %1,%0") ! 272: ! 273: (define_insn "trunchiqi2" ! 274: [(set (match_operand:QI 0 "register_operand" "=r") ! 275: (truncate:QI (match_operand:HI 1 "register_operand" "0")))] ! 276: "" ! 277: "") ! 278: ! 279: (define_insn "truncdisi2" ! 280: [(set (match_operand:SI 0 "register_operand" "=d") ! 281: (truncate:SI (match_operand:DI 1 "register_operand" "d")))] ! 282: "" ! 283: "cvtl.w %1,%0") ! 284: ! 285: (define_insn "extendsidi2" ! 286: [(set (match_operand:DI 0 "register_operand" "=d") ! 287: (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))] ! 288: "" ! 289: "cvtw.l %1,%0") ! 290: ! 291: (define_insn "extendhisi2" ! 292: [(set (match_operand:SI 0 "register_operand" "=d,a") ! 293: (sign_extend:SI (match_operand:HI 1 "register_operand" "d,a")))] ! 294: "" ! 295: "cvth.w %1,%0") ! 296: ! 297: (define_insn "extendqihi2" ! 298: [(set (match_operand:HI 0 "register_operand" "=d,a") ! 299: (sign_extend:HI (match_operand:QI 1 "register_operand" "d,a")))] ! 300: "" ! 301: "cvtb.w %1,%0") ! 302: ! 303: (define_insn "extendqisi2" ! 304: [(set (match_operand:SI 0 "register_operand" "=d,a") ! 305: (sign_extend:SI (match_operand:QI 1 "register_operand" "d,a")))] ! 306: "" ! 307: "cvtb.w %1,%0") ! 308: ! 309: (define_insn "extendsfdf2" ! 310: [(set (match_operand:DF 0 "register_operand" "=d") ! 311: (float_extend:DF (match_operand:SF 1 "register_operand" "d")))] ! 312: "" ! 313: "cvts.d %1,%0") ! 314: ! 315: (define_insn "truncdfsf2" ! 316: [(set (match_operand:SF 0 "register_operand" "=d") ! 317: (float_truncate:SF (match_operand:DF 1 "register_operand" "d")))] ! 318: "" ! 319: "cvtd.s %1,%0") ! 320: ! 321: (define_insn "zero_extendhisi2" ! 322: [(set (match_operand:SI 0 "register_operand" "=r") ! 323: (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))] ! 324: "" ! 325: "and #0xffff,%0") ! 326: ! 327: (define_insn "zero_extendqihi2" ! 328: [(set (match_operand:HI 0 "register_operand" "=r") ! 329: (zero_extend:HI (match_operand:QI 1 "register_operand" "0")))] ! 330: "" ! 331: "and #0xff,%0") ! 332: ! 333: (define_insn "zero_extendqisi2" ! 334: [(set (match_operand:SI 0 "register_operand" "=r") ! 335: (zero_extend:SI (match_operand:QI 1 "register_operand" "0")))] ! 336: "" ! 337: "and #0xff,%0") ! 338: ! 339: (define_insn "zero_extendsidi2" ! 340: [(set (match_operand:DI 0 "register_operand" "=d") ! 341: (zero_extend:DI (match_operand:SI 1 "register_operand" "0")))] ! 342: "" ! 343: "ld.u #0,%0") ! 344: ! 345: ;; Fix-to-float conversion insns. ! 346: ;; Note that the ones that start with SImode come first. ! 347: ;; That is so that an operand that is a CONST_INT ! 348: ;; (and therefore lacks a specific machine mode). ! 349: ;; will be recognized as SImode (which is always valid) ! 350: ;; rather than as QImode or HImode. ! 351: ! 352: (define_insn "floatsisf2" ! 353: [(set (match_operand:SF 0 "register_operand" "=d") ! 354: (float:SF (match_operand:SI 1 "register_operand" "d")))] ! 355: "" ! 356: "cvtw.s %1,%0") ! 357: ! 358: (define_insn "floatdisf2" ! 359: [(set (match_operand:SF 0 "register_operand" "=d") ! 360: (float:SF (match_operand:DI 1 "register_operand" "d")))] ! 361: "" ! 362: "cvtl.s %1,%0") ! 363: ! 364: (define_insn "floatsidf2" ! 365: [(set (match_operand:DF 0 "register_operand" "=d") ! 366: (float:DF (match_operand:SI 1 "register_operand" "d")))] ! 367: "TARGET_C2" ! 368: "cvtw.d %1,%0") ! 369: ! 370: (define_insn "floatdidf2" ! 371: [(set (match_operand:DF 0 "register_operand" "=d") ! 372: (float:DF (match_operand:DI 1 "register_operand" "d")))] ! 373: "" ! 374: "cvtl.d %1,%0") ! 375: ! 376: ;; Float-to-fix conversion insns. ! 377: ! 378: (define_insn "fix_truncsfsi2" ! 379: [(set (match_operand:SI 0 "register_operand" "=d") ! 380: (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "d"))))] ! 381: "" ! 382: "cvts.w %1,%0") ! 383: ! 384: (define_insn "fix_truncsfdi2" ! 385: [(set (match_operand:DI 0 "register_operand" "=d") ! 386: (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "d"))))] ! 387: "" ! 388: "cvts.l %1,%0") ! 389: ! 390: (define_insn "fix_truncdfsi2" ! 391: [(set (match_operand:SI 0 "register_operand" "=d") ! 392: (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "d"))))] ! 393: "" ! 394: "* ! 395: { ! 396: if (TARGET_C2) ! 397: return \"cvtd.w %1,%0\"; ! 398: return \"cvtd.l %1,%0\"; ! 399: }") ! 400: ! 401: (define_insn "fix_truncdfdi2" ! 402: [(set (match_operand:DI 0 "register_operand" "=d") ! 403: (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))] ! 404: "" ! 405: "cvtd.l %1,%0") ! 406: ! 407: ;;- All kinds of add instructions. ! 408: ! 409: (define_insn "adddf3" ! 410: [(set (match_operand:DF 0 "register_operand" "=d") ! 411: (plus:DF (match_operand:DF 1 "register_operand" "%0") ! 412: (match_operand:DF 2 "register_operand" "d")))] ! 413: "" ! 414: "add.d %2,%0") ! 415: ! 416: (define_insn "addsf3" ! 417: [(set (match_operand:SF 0 "register_operand" "=d") ! 418: (plus:SF (match_operand:SF 1 "register_operand" "%0") ! 419: (match_operand:SF 2 "nonmemory_operand" "dF")))] ! 420: "" ! 421: "add.s %2,%0") ! 422: ! 423: (define_insn "adddi3" ! 424: [(set (match_operand:DI 0 "register_operand" "=d") ! 425: (plus:DI (match_operand:DI 1 "register_operand" "%0") ! 426: (match_operand:DI 2 "register_operand" "d")))] ! 427: "" ! 428: "add.l %2,%0") ! 429: ! 430: ;; special case of addsi3, needed to specify an A reg for the destination ! 431: ;; when the source is a sum involving FP or AP. ! 432: ! 433: (define_insn "" ! 434: [(set (match_operand:SI 0 "register_operand" "=a") ! 435: (plus:SI (match_operand:SI 1 "register_operand" "%a") ! 436: (match_operand:SI 2 "immediate_operand" "i")))] ! 437: "operands[1] == frame_pointer_rtx || operands[1] == arg_pointer_rtx" ! 438: "ldea %a2(%1),%0") ! 439: ! 440: (define_insn "addsi3" ! 441: [(set (match_operand:SI 0 "register_operand" "=d,a,a") ! 442: (plus:SI (match_operand:SI 1 "nonmemory_operand" "%0,0,a") ! 443: (match_operand:SI 2 "nonmemory_operand" "di,ri,i")))] ! 444: "" ! 445: "* switch (which_alternative) ! 446: { ! 447: case 0: ! 448: case 1: ! 449: return \"add.w %2,%0\"; ! 450: case 2: ! 451: if ((TARGET_C2 || A_REG_P (operands[0])) ! 452: && operands[1] != stack_pointer_rtx) ! 453: return \"ldea %a2(%1),%0\"; ! 454: else ! 455: return \"mov %1,%0\;add.w %2,%0\"; ! 456: }") ! 457: ! 458: (define_insn "addhi3" ! 459: [(set (match_operand:HI 0 "register_operand" "=d,a") ! 460: (plus:HI (match_operand:HI 1 "register_operand" "%0,0") ! 461: (match_operand:HI 2 "nonmemory_operand" "di,ai")))] ! 462: "" ! 463: "add.h %2,%0") ! 464: ! 465: (define_insn "addqi3" ! 466: [(set (match_operand:QI 0 "register_operand" "=d") ! 467: (plus:QI (match_operand:QI 1 "register_operand" "%0") ! 468: (match_operand:QI 2 "register_operand" "d")))] ! 469: "" ! 470: "add.b %2,%0") ! 471: ! 472: ;;- All kinds of subtract instructions. ! 473: ! 474: (define_insn "subdf3" ! 475: [(set (match_operand:DF 0 "register_operand" "=d") ! 476: (minus:DF (match_operand:DF 1 "register_operand" "0") ! 477: (match_operand:DF 2 "register_operand" "d")))] ! 478: "" ! 479: "sub.d %2,%0") ! 480: ! 481: (define_insn "subsf3" ! 482: [(set (match_operand:SF 0 "register_operand" "=d") ! 483: (minus:SF (match_operand:SF 1 "register_operand" "0") ! 484: (match_operand:SF 2 "nonmemory_operand" "dF")))] ! 485: "" ! 486: "sub.s %2,%0") ! 487: ! 488: (define_insn "subdi3" ! 489: [(set (match_operand:DI 0 "register_operand" "=d") ! 490: (minus:DI (match_operand:DI 1 "register_operand" "0") ! 491: (match_operand:DI 2 "register_operand" "d")))] ! 492: "" ! 493: "sub.l %2,%0") ! 494: ! 495: (define_insn "subsi3" ! 496: [(set (match_operand:SI 0 "register_operand" "=d,a") ! 497: (minus:SI (match_operand:SI 1 "register_operand" "0,0") ! 498: (match_operand:SI 2 "nonmemory_operand" "di,ai")))] ! 499: "" ! 500: "sub.w %2,%0") ! 501: ! 502: (define_insn "subhi3" ! 503: [(set (match_operand:HI 0 "register_operand" "=d,a") ! 504: (minus:HI (match_operand:HI 1 "register_operand" "0,0") ! 505: (match_operand:HI 2 "nonmemory_operand" "di,ai")))] ! 506: "" ! 507: "sub.h %2,%0") ! 508: ! 509: (define_insn "subqi3" ! 510: [(set (match_operand:QI 0 "register_operand" "=d") ! 511: (minus:QI (match_operand:QI 1 "register_operand" "0") ! 512: (match_operand:QI 2 "register_operand" "d")))] ! 513: "" ! 514: "sub.b %2,%0") ! 515: ! 516: ;;- Multiply instructions. ! 517: ! 518: (define_insn "muldf3" ! 519: [(set (match_operand:DF 0 "register_operand" "=d") ! 520: (mult:DF (match_operand:DF 1 "register_operand" "%0") ! 521: (match_operand:DF 2 "register_operand" "d")))] ! 522: "" ! 523: "mul.d %2,%0") ! 524: ! 525: (define_insn "mulsf3" ! 526: [(set (match_operand:SF 0 "register_operand" "=d") ! 527: (mult:SF (match_operand:SF 1 "register_operand" "%0") ! 528: (match_operand:SF 2 "nonmemory_operand" "dF")))] ! 529: "" ! 530: "mul.s %2,%0") ! 531: ! 532: (define_insn "muldi3" ! 533: [(set (match_operand:DI 0 "register_operand" "=d") ! 534: (mult:DI (match_operand:DI 1 "register_operand" "%0") ! 535: (match_operand:DI 2 "register_operand" "d")))] ! 536: "" ! 537: "mul.l %2,%0") ! 538: ! 539: (define_insn "mulsi3" ! 540: [(set (match_operand:SI 0 "register_operand" "=d,a") ! 541: (mult:SI (match_operand:SI 1 "register_operand" "%0,0") ! 542: (match_operand:SI 2 "nonmemory_operand" "di,ai")))] ! 543: "" ! 544: "mul.w %2,%0") ! 545: ! 546: (define_insn "mulhi3" ! 547: [(set (match_operand:HI 0 "register_operand" "=d,a") ! 548: (mult:HI (match_operand:HI 1 "register_operand" "%0,0") ! 549: (match_operand:HI 2 "nonmemory_operand" "di,ai")))] ! 550: "" ! 551: "mul.h %2,%0") ! 552: ! 553: (define_insn "mulqi3" ! 554: [(set (match_operand:QI 0 "register_operand" "=d") ! 555: (mult:QI (match_operand:QI 1 "register_operand" "%0") ! 556: (match_operand:QI 2 "register_operand" "d")))] ! 557: "" ! 558: "mul.b %2,%0") ! 559: ! 560: ;;- Divide instructions. ! 561: ! 562: (define_insn "divdf3" ! 563: [(set (match_operand:DF 0 "register_operand" "=d") ! 564: (div:DF (match_operand:DF 1 "register_operand" "0") ! 565: (match_operand:DF 2 "register_operand" "d")))] ! 566: "" ! 567: "div.d %2,%0") ! 568: ! 569: (define_insn "divsf3" ! 570: [(set (match_operand:SF 0 "register_operand" "=d") ! 571: (div:SF (match_operand:SF 1 "register_operand" "0") ! 572: (match_operand:SF 2 "nonmemory_operand" "dF")))] ! 573: "" ! 574: "div.s %2,%0") ! 575: ! 576: (define_insn "divdi3" ! 577: [(set (match_operand:DI 0 "register_operand" "=d") ! 578: (div:DI (match_operand:DI 1 "register_operand" "0") ! 579: (match_operand:DI 2 "register_operand" "d")))] ! 580: "" ! 581: "div.l %2,%0") ! 582: ! 583: (define_insn "udivdi3" ! 584: [(set (match_operand:DI 0 "register_operand" "=d") ! 585: (udiv:DI (match_operand:DI 1 "register_operand" "d") ! 586: (match_operand:DI 2 "register_operand" "d")))] ! 587: "" ! 588: "psh.l %2\;psh.l %1\;callq udiv64\;pop.l %0\;add.w #8,sp") ! 589: ! 590: (define_insn "divsi3" ! 591: [(set (match_operand:SI 0 "register_operand" "=d,a") ! 592: (div:SI (match_operand:SI 1 "register_operand" "0,0") ! 593: (match_operand:SI 2 "nonmemory_operand" "di,ai")))] ! 594: "" ! 595: "div.w %2,%0") ! 596: ! 597: (define_insn "divhi3" ! 598: [(set (match_operand:HI 0 "register_operand" "=d,a") ! 599: (div:HI (match_operand:HI 1 "register_operand" "0,0") ! 600: (match_operand:HI 2 "nonmemory_operand" "di,ai")))] ! 601: "" ! 602: "div.h %2,%0") ! 603: ! 604: (define_insn "divqi3" ! 605: [(set (match_operand:QI 0 "register_operand" "=d") ! 606: (div:QI (match_operand:QI 1 "register_operand" "0") ! 607: (match_operand:QI 2 "register_operand" "d")))] ! 608: "" ! 609: "div.b %2,%0") ! 610: ! 611: ;; - and, or, xor ! 612: ! 613: (define_insn "anddi3" ! 614: [(set (match_operand:DI 0 "register_operand" "=d") ! 615: (and:DI (match_operand:DI 1 "register_operand" "%0") ! 616: (match_operand:DI 2 "register_operand" "d")))] ! 617: "" ! 618: "and %2,%0") ! 619: ! 620: (define_insn "andsi3" ! 621: [(set (match_operand:SI 0 "register_operand" "=d,a") ! 622: (and:SI (match_operand:SI 1 "register_operand" "%0,0") ! 623: (match_operand:SI 2 "nonmemory_operand" "di,ai")))] ! 624: "" ! 625: "and %2,%0") ! 626: ! 627: (define_insn "andhi3" ! 628: [(set (match_operand:HI 0 "register_operand" "=d,a") ! 629: (and:HI (match_operand:HI 1 "register_operand" "%0,0") ! 630: (match_operand:HI 2 "nonmemory_operand" "di,ai")))] ! 631: "" ! 632: "and %2,%0") ! 633: ! 634: (define_insn "andqi3" ! 635: [(set (match_operand:QI 0 "register_operand" "=d,a") ! 636: (and:QI (match_operand:QI 1 "register_operand" "%0,0") ! 637: (match_operand:QI 2 "nonmemory_operand" "di,ai")))] ! 638: "" ! 639: "and %2,%0") ! 640: ! 641: ;;- Bit set instructions. ! 642: ! 643: (define_insn "iordi3" ! 644: [(set (match_operand:DI 0 "register_operand" "=d") ! 645: (ior:DI (match_operand:DI 1 "register_operand" "%0") ! 646: (match_operand:DI 2 "register_operand" "d")))] ! 647: "" ! 648: "or %2,%0") ! 649: ! 650: (define_insn "iorsi3" ! 651: [(set (match_operand:SI 0 "register_operand" "=d,a") ! 652: (ior:SI (match_operand:SI 1 "register_operand" "%0,0") ! 653: (match_operand:SI 2 "nonmemory_operand" "di,ai")))] ! 654: "" ! 655: "or %2,%0") ! 656: ! 657: (define_insn "iorhi3" ! 658: [(set (match_operand:HI 0 "register_operand" "=d,a") ! 659: (ior:HI (match_operand:HI 1 "register_operand" "%0,0") ! 660: (match_operand:HI 2 "nonmemory_operand" "di,ai")))] ! 661: "" ! 662: "or %2,%0") ! 663: ! 664: (define_insn "iorqi3" ! 665: [(set (match_operand:QI 0 "register_operand" "=d,a") ! 666: (ior:QI (match_operand:QI 1 "register_operand" "%0,0") ! 667: (match_operand:QI 2 "nonmemory_operand" "di,ai")))] ! 668: "" ! 669: "or %2,%0") ! 670: ! 671: ;;- xor instructions. ! 672: ! 673: (define_insn "xordi3" ! 674: [(set (match_operand:DI 0 "register_operand" "=d") ! 675: (xor:DI (match_operand:DI 1 "register_operand" "%0") ! 676: (match_operand:DI 2 "register_operand" "d")))] ! 677: "" ! 678: "xor %2,%0") ! 679: ! 680: (define_insn "xorsi3" ! 681: [(set (match_operand:SI 0 "register_operand" "=d,a") ! 682: (xor:SI (match_operand:SI 1 "register_operand" "%0,0") ! 683: (match_operand:SI 2 "nonmemory_operand" "di,ai")))] ! 684: "" ! 685: "xor %2,%0") ! 686: ! 687: (define_insn "xorhi3" ! 688: [(set (match_operand:HI 0 "register_operand" "=d,a") ! 689: (xor:HI (match_operand:HI 1 "register_operand" "%0,0") ! 690: (match_operand:HI 2 "nonmemory_operand" "di,ai")))] ! 691: "" ! 692: "xor %2,%0") ! 693: ! 694: (define_insn "xorqi3" ! 695: [(set (match_operand:QI 0 "register_operand" "=d,a") ! 696: (xor:QI (match_operand:QI 1 "register_operand" "%0,0") ! 697: (match_operand:QI 2 "nonmemory_operand" "di,ai")))] ! 698: "" ! 699: "xor %2,%0") ! 700: ! 701: (define_insn "negdf2" ! 702: [(set (match_operand:DF 0 "register_operand" "=d") ! 703: (neg:DF (match_operand:DF 1 "register_operand" "d")))] ! 704: "" ! 705: "neg.d %1,%0") ! 706: ! 707: (define_insn "negsf2" ! 708: [(set (match_operand:SF 0 "register_operand" "=d") ! 709: (neg:SF (match_operand:SF 1 "register_operand" "d")))] ! 710: "" ! 711: "neg.s %1,%0") ! 712: ! 713: (define_insn "negdi2" ! 714: [(set (match_operand:DI 0 "register_operand" "=d") ! 715: (neg:DI (match_operand:DI 1 "register_operand" "d")))] ! 716: "" ! 717: "neg.l %1,%0") ! 718: ! 719: (define_insn "negsi2" ! 720: [(set (match_operand:SI 0 "register_operand" "=d,a") ! 721: (neg:SI (match_operand:SI 1 "register_operand" "d,a")))] ! 722: "" ! 723: "neg.w %1,%0") ! 724: ! 725: (define_insn "neghi2" ! 726: [(set (match_operand:HI 0 "register_operand" "=d,a") ! 727: (neg:HI (match_operand:HI 1 "register_operand" "d,a")))] ! 728: "" ! 729: "neg.h %1,%0") ! 730: ! 731: (define_insn "negqi2" ! 732: [(set (match_operand:QI 0 "register_operand" "=d") ! 733: (neg:QI (match_operand:QI 1 "register_operand" "d")))] ! 734: "" ! 735: "neg.b %1,%0") ! 736: ! 737: (define_insn "one_cmpldi2" ! 738: [(set (match_operand:DI 0 "register_operand" "=d") ! 739: (not:DI (match_operand:DI 1 "register_operand" "d")))] ! 740: "" ! 741: "not %1,%0") ! 742: ! 743: (define_insn "one_cmplsi2" ! 744: [(set (match_operand:SI 0 "register_operand" "=d,a") ! 745: (not:SI (match_operand:SI 1 "register_operand" "d,a")))] ! 746: "" ! 747: "not %1,%0") ! 748: ! 749: (define_insn "one_cmplhi2" ! 750: [(set (match_operand:HI 0 "register_operand" "=d,a") ! 751: (not:HI (match_operand:HI 1 "register_operand" "d,a")))] ! 752: "" ! 753: "not %1,%0") ! 754: ! 755: (define_insn "one_cmplqi2" ! 756: [(set (match_operand:QI 0 "register_operand" "=d,a") ! 757: (not:QI (match_operand:QI 1 "register_operand" "d,a")))] ! 758: "" ! 759: "not %1,%0") ! 760: ! 761: ;;- shifts ! 762: ;; ! 763: ;; Convex shift instructions are unsigned. ! 764: ;; To make signed right shifts: ! 765: ;; for SImode, sign extend to DImode and shift, works for 0..32 ! 766: ;; for DImode, shift and then extend the sign, works for 0..63 ! 767: ;; ! 768: ;; It is very sad that DImode right shift 64 fails, but I don't see ! 769: ;; any reasonable way to handle it. ANSI only requires up to 63. ! 770: ! 771: (define_insn "" ! 772: [(set (match_operand:SI 0 "register_operand" "=r") ! 773: (ashift:SI (match_operand:SI 1 "register_operand" "0") ! 774: (match_operand:SI 2 "immediate_operand" "i")))] ! 775: "INTVAL (operands[2]) >= 0" ! 776: "* ! 777: { ! 778: if (operands[2] == const1_rtx) ! 779: return \"add.w %0,%0\"; ! 780: else if (TARGET_C2 && S_REG_P (operands[0])) ! 781: return \"shf.w %2,%0\"; ! 782: else ! 783: return \"shf %2,%0\"; ! 784: }") ! 785: ! 786: (define_insn "ashlsi3" ! 787: [(set (match_operand:SI 0 "register_operand" "=d") ! 788: (ashift:SI (match_operand:SI 1 "register_operand" "0") ! 789: (match_operand:SI 2 "nonmemory_operand" "di")))] ! 790: "" ! 791: "* ! 792: { ! 793: if (operands[2] == const1_rtx) ! 794: return \"add.w %0,%0\"; ! 795: else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0) ! 796: return TARGET_C2 ? \"shf.w %2,%0\" : \"shf %2,%0\"; ! 797: else ! 798: return \"cvtw.l %0,%0\;shf %2,%0\"; ! 799: }") ! 800: ! 801: (define_expand "ashrsi3" ! 802: [(set (match_operand:SI 0 "register_operand" "=d") ! 803: (ashift:SI (match_operand:SI 1 "register_operand" "0") ! 804: (match_operand:SI 2 "nonmemory_operand" "di")))] ! 805: "" ! 806: "operands[2] = negate_rtx (SImode, operands[2]);") ! 807: ! 808: (define_insn "lshlsi3" ! 809: [(set (match_operand:SI 0 "register_operand" "=d,a") ! 810: (lshift:SI (match_operand:SI 1 "register_operand" "0,0") ! 811: (match_operand:SI 2 "nonmemory_operand" "di,ai")))] ! 812: "" ! 813: "* ! 814: { ! 815: if (operands[2] == const1_rtx) ! 816: return \"add.w %0,%0\"; ! 817: if (S_REG_P (operands[0])) ! 818: { ! 819: if (TARGET_C2) ! 820: return \"shf.w %2,%0\"; ! 821: else if (GET_CODE (operands[2]) == CONST_INT ! 822: && INTVAL (operands[2]) >= 0) ! 823: return \"shf %2,%0\"; ! 824: else ! 825: return \"ld.u #0,%0\;shf %2,%0\"; ! 826: } ! 827: return \"shf %2,%0\"; ! 828: }") ! 829: ! 830: (define_expand "lshrsi3" ! 831: [(set (match_operand:SI 0 "register_operand" "=d") ! 832: (lshift:SI (match_operand:SI 1 "register_operand" "0") ! 833: (match_operand:SI 2 "nonmemory_operand" "di")))] ! 834: "" ! 835: "operands[2] = negate_rtx (SImode, operands[2]);") ! 836: ! 837: ;; signed a >> b is ! 838: ;; ((a >> b) ^ signbit) - signbit ! 839: ;; where signbit is (1 << 63) >> b ! 840: ! 841: (define_expand "ashldi3" ! 842: [(match_operand:DI 0 "register_operand" "=d") ! 843: (match_operand:DI 1 "register_operand" "0") ! 844: (match_operand:SI 2 "nonmemory_operand" "di") ! 845: (match_dup 3)] ! 846: "" ! 847: " ! 848: { ! 849: if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0) ! 850: emit_insn (gen_rtx (SET, VOIDmode, operands[0], ! 851: gen_rtx (LSHIFT, DImode, operands[1], operands[2]))); ! 852: else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) ! 853: { ! 854: int rshift = - INTVAL (operands[2]); ! 855: operands[3] = force_reg ! 856: (DImode, ! 857: immed_double_const (1 << (63 - rshift), 1 << (31 - rshift), DImode)); ! 858: emit_insn (gen_rtx (SET, VOIDmode, operands[0], ! 859: gen_rtx (LSHIFT, DImode, operands[1], operands[2]))); ! 860: emit_insn (gen_rtx (SET, VOIDmode, operands[0], ! 861: gen_rtx (XOR, DImode, operands[0], operands[3]))); ! 862: emit_insn (gen_rtx (SET, VOIDmode, operands[0], ! 863: gen_rtx (MINUS, DImode, operands[0], operands[3]))); ! 864: } ! 865: else ! 866: { ! 867: operands[3] = ! 868: force_reg (DImode, immed_double_const (0, 1 << 31, DImode)); ! 869: emit_insn (gen_rtx (SET, VOIDmode, operands[0], ! 870: gen_rtx (LSHIFT, DImode, operands[1], operands[2]))); ! 871: emit_insn (gen_rtx (SET, VOIDmode, operands[3], ! 872: gen_rtx (LSHIFT, DImode, operands[3], operands[2]))); ! 873: emit_insn (gen_rtx (SET, VOIDmode, operands[0], ! 874: gen_rtx (XOR, DImode, operands[0], operands[3]))); ! 875: emit_insn (gen_rtx (SET, VOIDmode, operands[0], ! 876: gen_rtx (MINUS, DImode, operands[0], operands[3]))); ! 877: } ! 878: DONE; ! 879: }") ! 880: ! 881: (define_expand "ashrdi3" ! 882: [(match_operand:DI 0 "register_operand" "=d") ! 883: (match_operand:DI 1 "register_operand" "0") ! 884: (match_operand:SI 2 "nonmemory_operand" "di")] ! 885: "" ! 886: " ! 887: { ! 888: emit_insn (gen_ashldi3 (operands[0], operands[1], ! 889: negate_rtx (SImode, operands[2]))); ! 890: DONE; ! 891: }") ! 892: ! 893: (define_insn "lshldi3" ! 894: [(set (match_operand:DI 0 "register_operand" "=d") ! 895: (lshift:DI (match_operand:DI 1 "register_operand" "0") ! 896: (match_operand:SI 2 "nonmemory_operand" "di")))] ! 897: "" ! 898: "shf %2,%0") ! 899: ! 900: (define_expand "lshrdi3" ! 901: [(set (match_operand:DI 0 "register_operand" "=d") ! 902: (lshift:DI (match_operand:DI 1 "register_operand" "0") ! 903: (match_operand:SI 2 "nonmemory_operand" "di")))] ! 904: "" ! 905: "operands[2] = negate_rtx (SImode, operands[2]);") ! 906: ! 907: ;; __builtin instructions ! 908: ! 909: (define_insn "sqrtdf2" ! 910: [(set (match_operand:DF 0 "register_operand" "=d") ! 911: (sqrt:DF (match_operand:DF 1 "register_operand" "0")))] ! 912: "TARGET_C2" ! 913: "sqrt.d %0") ! 914: ! 915: (define_insn "sqrtsf2" ! 916: [(set (match_operand:SF 0 "register_operand" "=d") ! 917: (sqrt:SF (match_operand:SF 1 "register_operand" "0")))] ! 918: "TARGET_C2" ! 919: "sqrt.s %0") ! 920: ! 921: (define_insn "" ! 922: [(set (match_operand:SI 0 "register_operand" "=d") ! 923: (minus:SI (ffs:SI (match_operand:SI 1 "register_operand" "d")) ! 924: (const_int 1)))] ! 925: "" ! 926: "tzc %1,%0\;le.w #32,%0\;jbrs.f .+6\;ld.w #-1,%0") ! 927: ! 928: (define_expand "ffssi2" ! 929: [(set (match_operand:SI 0 "register_operand" "=d") ! 930: (minus:SI (ffs:SI (match_operand:SI 1 "register_operand" "d")) ! 931: (const_int 1))) ! 932: (set (match_dup 0) ! 933: (plus:SI (match_dup 0) ! 934: (const_int 1)))] ! 935: "" ! 936: "") ! 937: ! 938: (define_insn "abssf2" ! 939: [(set (match_operand:SF 0 "register_operand" "=d") ! 940: (abs:SF (match_operand:SF 1 "register_operand" "0")))] ! 941: "" ! 942: "and #0x7fffffff,%0") ! 943: ! 944: (define_expand "absdf2" ! 945: [(set (subreg:DI (match_operand:DF 0 "register_operand" "=d") 0) ! 946: (and:DI (subreg:DI (match_operand:DF 1 "register_operand" "d") 0) ! 947: (match_dup 2)))] ! 948: "" ! 949: "operands[2] = force_reg (DImode, ! 950: immed_double_const (-1, 0x7fffffff, DImode));") ! 951: ! 952: (define_insn "jump" ! 953: [(set (pc) ! 954: (label_ref (match_operand 0 "" "")))] ! 955: "" ! 956: "jbr %l0") ! 957: ! 958: (define_insn "beq" ! 959: [(set (pc) ! 960: (if_then_else (eq (cc0) ! 961: (const_int 0)) ! 962: (label_ref (match_operand 0 "" "")) ! 963: (pc)))] ! 964: "" ! 965: "* return gen_cmp (operands[0], \"eq\", 't'); ") ! 966: ! 967: (define_insn "bne" ! 968: [(set (pc) ! 969: (if_then_else (ne (cc0) ! 970: (const_int 0)) ! 971: (label_ref (match_operand 0 "" "")) ! 972: (pc)))] ! 973: "" ! 974: "* return gen_cmp (operands[0], \"eq\", 'f'); ") ! 975: ! 976: (define_insn "bgt" ! 977: [(set (pc) ! 978: (if_then_else (gt (cc0) ! 979: (const_int 0)) ! 980: (label_ref (match_operand 0 "" "")) ! 981: (pc)))] ! 982: "" ! 983: "* return gen_cmp (operands[0], \"le\", 'f'); ") ! 984: ! 985: (define_insn "bgtu" ! 986: [(set (pc) ! 987: (if_then_else (gtu (cc0) ! 988: (const_int 0)) ! 989: (label_ref (match_operand 0 "" "")) ! 990: (pc)))] ! 991: "" ! 992: "* return gen_cmp (operands[0], \"leu\", 'f'); ") ! 993: ! 994: (define_insn "blt" ! 995: [(set (pc) ! 996: (if_then_else (lt (cc0) ! 997: (const_int 0)) ! 998: (label_ref (match_operand 0 "" "")) ! 999: (pc)))] ! 1000: "" ! 1001: "* return gen_cmp (operands[0], \"lt\", 't'); ") ! 1002: ! 1003: (define_insn "bltu" ! 1004: [(set (pc) ! 1005: (if_then_else (ltu (cc0) ! 1006: (const_int 0)) ! 1007: (label_ref (match_operand 0 "" "")) ! 1008: (pc)))] ! 1009: "" ! 1010: "* return gen_cmp (operands[0], \"ltu\", 't'); ") ! 1011: ! 1012: (define_insn "bge" ! 1013: [(set (pc) ! 1014: (if_then_else (ge (cc0) ! 1015: (const_int 0)) ! 1016: (label_ref (match_operand 0 "" "")) ! 1017: (pc)))] ! 1018: "" ! 1019: "* return gen_cmp (operands[0], \"lt\", 'f'); ") ! 1020: ! 1021: (define_insn "bgeu" ! 1022: [(set (pc) ! 1023: (if_then_else (geu (cc0) ! 1024: (const_int 0)) ! 1025: (label_ref (match_operand 0 "" "")) ! 1026: (pc)))] ! 1027: "" ! 1028: "* return gen_cmp (operands[0], \"ltu\", 'f'); ") ! 1029: ! 1030: (define_insn "ble" ! 1031: [(set (pc) ! 1032: (if_then_else (le (cc0) ! 1033: (const_int 0)) ! 1034: (label_ref (match_operand 0 "" "")) ! 1035: (pc)))] ! 1036: "" ! 1037: "* return gen_cmp (operands[0], \"le\", 't'); ") ! 1038: ! 1039: (define_insn "bleu" ! 1040: [(set (pc) ! 1041: (if_then_else (leu (cc0) ! 1042: (const_int 0)) ! 1043: (label_ref (match_operand 0 "" "")) ! 1044: (pc)))] ! 1045: "" ! 1046: "* return gen_cmp (operands[0], \"leu\", 't'); ") ! 1047: ! 1048: (define_insn "" ! 1049: [(set (pc) ! 1050: (if_then_else (eq (cc0) ! 1051: (const_int 0)) ! 1052: (pc) ! 1053: (label_ref (match_operand 0 "" ""))))] ! 1054: "" ! 1055: "* return gen_cmp (operands[0], \"eq\", 'f'); ") ! 1056: ! 1057: (define_insn "" ! 1058: [(set (pc) ! 1059: (if_then_else (ne (cc0) ! 1060: (const_int 0)) ! 1061: (pc) ! 1062: (label_ref (match_operand 0 "" ""))))] ! 1063: "" ! 1064: "* return gen_cmp (operands[0], \"eq\", 't'); ") ! 1065: ! 1066: (define_insn "" ! 1067: [(set (pc) ! 1068: (if_then_else (gt (cc0) ! 1069: (const_int 0)) ! 1070: (pc) ! 1071: (label_ref (match_operand 0 "" ""))))] ! 1072: "" ! 1073: "* return gen_cmp (operands[0], \"le\", 't'); ") ! 1074: ! 1075: (define_insn "" ! 1076: [(set (pc) ! 1077: (if_then_else (gtu (cc0) ! 1078: (const_int 0)) ! 1079: (pc) ! 1080: (label_ref (match_operand 0 "" ""))))] ! 1081: "" ! 1082: "* return gen_cmp (operands[0], \"leu\", 't'); ") ! 1083: ! 1084: (define_insn "" ! 1085: [(set (pc) ! 1086: (if_then_else (lt (cc0) ! 1087: (const_int 0)) ! 1088: (pc) ! 1089: (label_ref (match_operand 0 "" ""))))] ! 1090: "" ! 1091: "* return gen_cmp (operands[0], \"lt\", 'f'); ") ! 1092: ! 1093: (define_insn "" ! 1094: [(set (pc) ! 1095: (if_then_else (ltu (cc0) ! 1096: (const_int 0)) ! 1097: (pc) ! 1098: (label_ref (match_operand 0 "" ""))))] ! 1099: "" ! 1100: "* return gen_cmp (operands[0], \"ltu\", 'f'); ") ! 1101: ! 1102: (define_insn "" ! 1103: [(set (pc) ! 1104: (if_then_else (ge (cc0) ! 1105: (const_int 0)) ! 1106: (pc) ! 1107: (label_ref (match_operand 0 "" ""))))] ! 1108: "" ! 1109: "* return gen_cmp (operands[0], \"lt\", 't'); ") ! 1110: ! 1111: (define_insn "" ! 1112: [(set (pc) ! 1113: (if_then_else (geu (cc0) ! 1114: (const_int 0)) ! 1115: (pc) ! 1116: (label_ref (match_operand 0 "" ""))))] ! 1117: "" ! 1118: "* return gen_cmp (operands[0], \"ltu\", 't'); ") ! 1119: ! 1120: (define_insn "" ! 1121: [(set (pc) ! 1122: (if_then_else (le (cc0) ! 1123: (const_int 0)) ! 1124: (pc) ! 1125: (label_ref (match_operand 0 "" ""))))] ! 1126: "" ! 1127: "* return gen_cmp (operands[0], \"le\", 'f'); ") ! 1128: ! 1129: (define_insn "" ! 1130: [(set (pc) ! 1131: (if_then_else (leu (cc0) ! 1132: (const_int 0)) ! 1133: (pc) ! 1134: (label_ref (match_operand 0 "" ""))))] ! 1135: "" ! 1136: "* return gen_cmp (operands[0], \"leu\", 'f'); ") ! 1137: ! 1138: ;; - Calls ! 1139: ;; ! 1140: ;; arg count word may be omitted to save a push and let gcc try to ! 1141: ;; combine the arg list pop. RETURN_POPS_ARGS from tm.h decides this. ! 1142: ! 1143: (define_insn "call" ! 1144: [(call (match_operand:QI 0 "general_operand" "g") ! 1145: (match_operand:SI 1 "general_operand" "g"))] ! 1146: "" ! 1147: "* ! 1148: { ! 1149: if (! RETURN_POPS_ARGS (ignoreme)) ! 1150: { ! 1151: if (operands[1] == const0_rtx) ! 1152: return \"calls %0\"; ! 1153: if (! reg_mentioned_p (arg_pointer_rtx, operands[0])) ! 1154: return \"mov sp,ap\;calls %0\;ld.w 12(fp),ap\"; ! 1155: operands[0] = XEXP (operands[0], 0); ! 1156: return \"ld.w %0,a1\;mov sp,ap\;calls (a1)\;ld.w 12(fp),ap\"; ! 1157: } ! 1158: operands[1] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[1]) + 3)/ 4); ! 1159: if (! reg_mentioned_p (arg_pointer_rtx, operands[0])) ! 1160: return \"mov sp,ap\;pshea %a1\;calls %0\;ld.w 12(fp),ap\;add.w #4*%a1+4,sp\"; ! 1161: operands[0] = XEXP (operands[0], 0); ! 1162: return \"ld.w %0,a1\;mov sp,ap\;pshea %a1\;calls (a1)\;ld.w 12(fp),ap\;add.w #4*%a1+4,sp\"; ! 1163: }") ! 1164: ! 1165: (define_insn "call_value" ! 1166: [(set (match_operand 0 "" "=g") ! 1167: (call (match_operand:QI 1 "general_operand" "g") ! 1168: (match_operand:SI 2 "general_operand" "g")))] ! 1169: "" ! 1170: "* ! 1171: { ! 1172: if (! RETURN_POPS_ARGS (ignoreme)) ! 1173: { ! 1174: if (operands[2] == const0_rtx) ! 1175: return \"calls %1\"; ! 1176: if (! reg_mentioned_p (arg_pointer_rtx, operands[1])) ! 1177: return \"mov sp,ap\;calls %1\;ld.w 12(fp),ap\"; ! 1178: operands[1] = XEXP (operands[1], 0); ! 1179: return \"ld.w %1,a1\;mov sp,ap\;calls (a1)\;ld.w 12(fp),ap\"; ! 1180: } ! 1181: operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) + 3) / 4); ! 1182: if (! reg_mentioned_p (arg_pointer_rtx, operands[1])) ! 1183: return \"mov sp,ap\;pshea %a2\;calls %1\;ld.w 12(fp),ap\;add.w #4*%a2+4,sp\"; ! 1184: operands[1] = XEXP (operands[1], 0); ! 1185: return \"ld.w %1,a1\;mov sp,ap\;pshea %a2\;calls (a1)\;ld.w 12(fp),ap\;add.w #4*%a2+4,sp\"; ! 1186: }") ! 1187: ! 1188: (define_insn "return" ! 1189: [(return)] ! 1190: "" ! 1191: "rtn") ! 1192: ! 1193: (define_insn "nop" ! 1194: [(const_int 0)] ! 1195: "" ! 1196: "nop") ! 1197: ! 1198: (define_insn "tablejump" ! 1199: [(set (pc) (match_operand:SI 0 "address_operand" "p")) ! 1200: (use (label_ref (match_operand 1 "" "")))] ! 1201: "" ! 1202: "jmp %a0") ! 1203: ! 1204: ;; - fix up the code generated for bit field tests ! 1205: ! 1206: ;; cc0 = (x >> k1) & k2 --> cc0 = x & (k2 << k1) ! 1207: ;; cc0 = (x << k1) & k2 --> cc0 = x & (k2 >> k1) ! 1208: ;; provided k2 and (k2 << k1) don't include the sign bit ! 1209: ! 1210: (define_peephole ! 1211: [(set (match_operand:SI 0 "register_operand" "r") ! 1212: (lshift:SI (match_dup 0) ! 1213: (match_operand 1 "immediate_operand" "i"))) ! 1214: (set (match_dup 0) ! 1215: (and:SI (match_dup 0) ! 1216: (match_operand 2 "immediate_operand" "i"))) ! 1217: (set (cc0) (match_dup 0))] ! 1218: "dead_or_set_p (insn, operands[0]) ! 1219: && GET_CODE (operands[1]) == CONST_INT ! 1220: && GET_CODE (operands[2]) == CONST_INT ! 1221: && INTVAL (operands[2]) >= 0 ! 1222: && (INTVAL (operands[2]) << INTVAL (operands[1])) >= 0" ! 1223: "* ! 1224: { ! 1225: operands[2] = gen_rtx (CONST_INT, VOIDmode, ! 1226: INTVAL (operands[2]) >> INTVAL (operands[1])); ! 1227: output_asm_insn (\"and %2,%0\", operands); ! 1228: return set_cmp (operands[0], const0_rtx, 'w'); ! 1229: }") ! 1230: ! 1231: ;; same as above where x is (y & 0xff...) caused by a zero extend ! 1232: ! 1233: (define_peephole ! 1234: [(set (match_operand:SI 0 "register_operand" "r") ! 1235: (zero_extend:SI (match_operand 1 "register_operand" "0"))) ! 1236: (set (match_dup 0) ! 1237: (lshift:SI (match_dup 0) ! 1238: (match_operand 2 "immediate_operand" "i"))) ! 1239: (set (match_dup 0) ! 1240: (and:SI (match_dup 0) ! 1241: (match_operand 3 "immediate_operand" "i"))) ! 1242: (set (cc0) (match_dup 0))] ! 1243: "dead_or_set_p (insn, operands[0]) ! 1244: && REGNO (operands[0]) == REGNO (operands[1]) ! 1245: && GET_CODE (operands[2]) == CONST_INT ! 1246: && GET_CODE (operands[3]) == CONST_INT ! 1247: && (INTVAL (operands[3]) << INTVAL (operands[2])) >= 0" ! 1248: "* ! 1249: { ! 1250: operands[3] = gen_rtx (CONST_INT, VOIDmode, ! 1251: (INTVAL (operands[3]) >> INTVAL (operands[2])) & ! 1252: ~((-1) << GET_MODE_BITSIZE (GET_MODE (operands[1])))); ! 1253: output_asm_insn (\"and %3,%0\", operands); ! 1254: return set_cmp (operands[0], const0_rtx, 'w'); ! 1255: }") ! 1256: ! 1257: ;;- Local variables: ! 1258: ;;- mode:emacs-lisp ! 1259: ;;- comment-start: ";;- " ! 1260: ;;- eval: (set-syntax-table (copy-sequence (syntax-table))) ! 1261: ;;- eval: (modify-syntax-entry ?[ "(]") ! 1262: ;;- eval: (modify-syntax-entry ?] ")[") ! 1263: ;;- eval: (modify-syntax-entry ?{ "(}") ! 1264: ;;- eval: (modify-syntax-entry ?} "){") ! 1265: ;;- End: ! 1266:
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