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1.1 root 1: ;;- Machine description for GNU compiler
2: ;;- Convex Version
3: ;; Copyright (C) 1991 Free Software Foundation, Inc.
4:
5: ;; This file is part of GNU CC.
6:
7: ;; GNU CC is free software; you can redistribute it and/or modify
8: ;; it under the terms of the GNU General Public License as published by
9: ;; the Free Software Foundation; either version 2, or (at your option)
10: ;; any later version.
11:
12: ;; GNU CC is distributed in the hope that it will be useful,
13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: ;; GNU General Public License for more details.
16:
17: ;; You should have received a copy of the GNU General Public License
18: ;; along with GNU CC; see the file COPYING. If not, write to
19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20:
21: ;; Scheduling defs
22: ;;
23: ;; Insn scheduling is not used at present. Scheduling increases
24: ;; register pressure so much that many spills are generated
25: ;; even for very small functions.
26:
27: ;; Compares
28:
29: (define_insn "tstsi"
30: [(set (cc0)
31: (match_operand:SI 0 "register_operand" "r"))]
32: ""
33: "* return set_cmp (operands[0], const0_rtx, 'w');")
34:
35: (define_insn "tsthi"
36: [(set (cc0)
37: (match_operand:HI 0 "register_operand" "r"))]
38: ""
39: "* return set_cmp (operands[0], const0_rtx, 'h');")
40:
41: (define_expand "tstqi"
42: [(set (match_dup 1)
43: (sign_extend:SI (match_operand:QI 0 "register_operand" "r")))
44: (set (cc0)
45: (match_dup 1))]
46: ""
47: "operands[1] = gen_reg_rtx (SImode);")
48:
49: (define_expand "tstdi"
50: [(parallel [(set (cc0) (match_operand:DI 0 "register_operand" "d"))
51: (use (match_dup 1))])]
52: ""
53: "operands[1] = force_reg (DImode, const0_rtx);")
54:
55: (define_insn ""
56: [(set (cc0) (match_operand:DI 0 "register_operand" "d"))
57: (use (match_operand:DI 1 "register_operand" "d"))]
58: ""
59: "* return set_cmp (operands[0], operands[1], 'l');")
60:
61: (define_expand "tstdf"
62: [(set (cc0)
63: (compare (match_operand:DF 0 "register_operand" "d")
64: (match_dup 1)))]
65: ""
66: "operands[1] = force_reg (DFmode, CONST0_RTX (DFmode));")
67:
68: (define_insn "tstsf"
69: [(set (cc0)
70: (match_operand:SF 0 "register_operand" "d"))]
71: ""
72: "* return set_cmp (operands[0], CONST0_RTX (SFmode), 's');")
73:
74: (define_insn "cmpsi"
75: [(set (cc0)
76: (compare (match_operand:SI 0 "register_operand" "d,a,i,r")
77: (match_operand:SI 1 "nonmemory_operand" "d,a,r,i")))]
78: ""
79: "* return set_cmp (operands[0], operands[1], 'w');")
80:
81: (define_insn "cmphi"
82: [(set (cc0)
83: (compare (match_operand:HI 0 "register_operand" "d,a,r,i")
84: (match_operand:HI 1 "nonmemory_operand" "d,a,i,r")))]
85: ""
86: "* return set_cmp (operands[0], operands[1], 'h');")
87:
88: (define_insn "cmpqi"
89: [(set (cc0)
90: (compare (match_operand:QI 0 "register_operand" "d")
91: (match_operand:QI 1 "register_operand" "d")))]
92: ""
93: "* return set_cmp (operands[0], operands[1], 'b');")
94:
95: (define_insn "cmpdi"
96: [(set (cc0)
97: (compare (match_operand:DI 0 "register_operand" "d")
98: (match_operand:DI 1 "register_operand" "d")))]
99: ""
100: "* return set_cmp (operands[0], operands[1], 'l');")
101:
102: (define_insn "cmpdf"
103: [(set (cc0)
104: (compare (match_operand:DF 0 "register_operand" "d")
105: (match_operand:DF 1 "register_operand" "d")))]
106: ""
107: "* return set_cmp (operands[0], operands[1], 'd');")
108:
109: (define_insn "cmpsf"
110: [(set (cc0)
111: (compare (match_operand:SF 0 "nonmemory_operand" "dF,d")
112: (match_operand:SF 1 "nonmemory_operand" "d,F")))]
113: ""
114: "* return set_cmp (operands[0], operands[1], 's');")
115:
116: ;; Moves
117:
118: ;(define_insn "movtf"
119: ; [(set (match_operand:TF 0 "general_operand" "=g,d")
120: ; (match_operand:TF 1 "general_operand" "d,g"))]
121: ; ""
122: ; "*
123: ;{
124: ; rtx opaddr = 0;
125: ; rtx xoperands[4];
126: ; xoperands[0] = operands[0];
127: ; xoperands[2] = operands[1];
128: ;
129: ; if (REG_P (operands[0]))
130: ; xoperands[1] = gen_rtx (REG, TFmode, REGNO (operands[0]) + 1);
131: ; else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
132: ; xoperands[1] = 0;
133: ; else if (offsettable_memref_p (operands[0]))
134: ; xoperands[1] = adj_offsettable_operand (operands[0], 8);
135: ; else
136: ; {
137: ; opaddr = XEXP (operands[0], 0);
138: ; xoperands[0] = gen_rtx (MEM, TFmode, gen_rtx (REG, SImode, 13));
139: ; xoperands[1] = adj_offsettable_operand (xoperands[0], 8);
140: ; }
141: ;
142: ; if (REG_P (operands[1]))
143: ; xoperands[3] = gen_rtx (REG, TFmode, REGNO (operands[1]) + 1);
144: ; else if (offsettable_memref_p (operands[1]))
145: ; xoperands[3] = adj_offsettable_operand (operands[1], 8);
146: ; else
147: ; {
148: ; opaddr = XEXP (operands[1], 0);
149: ; xoperands[2] = gen_rtx (MEM, TFmode, gen_rtx (REG, SImode, 13));
150: ; xoperands[3] = adj_offsettable_operand (xoperands[2], 8);
151: ; }
152: ;
153: ; if (opaddr)
154: ; output_asm_insn (\"psh.w a5\;ld.w %0,a5\", &opaddr);
155: ; if (push_operand (operands[0], TFmode))
156: ; output_asm_insn (\"psh.l %3\;psh.l %2\", xoperands);
157: ; else if (GET_CODE (operands[0]) == MEM)
158: ; output_asm_insn (\"st.l %2,%0\;st.l %3,%1\", xoperands);
159: ; else if (GET_CODE (operands[1]) == REG)
160: ; output_asm_insn (\"mov %2,%0\;mov %3,%1\", xoperands);
161: ; else
162: ; output_asm_insn (\"ld.l %2,%0\;ld.l %3,%1\", xoperands);
163: ; if (opaddr)
164: ; output_asm_insn (\"pop.w a5\");
165: ; return \"\";
166: ;}")
167:
168: (define_insn "movdf"
169: [(set (match_operand:DF 0 "general_operand" "=g,d")
170: (match_operand:DF 1 "general_operand" "d,dmG"))]
171: ""
172: "*
173: {
174: if (push_operand (operands[0], DFmode))
175: return \"psh.l %1\";
176: else if (GET_CODE (operands[0]) == MEM)
177: return \"st.l %1,%0\";
178: else if (GET_CODE (operands[1]) == REG)
179: return \"mov %1,%0\";
180: else if (GET_CODE (operands[1]) == CONST_DOUBLE && LD_D_P (operands[1]))
181: {
182: operands[1] = gen_rtx (CONST_INT, VOIDmode,
183: const_double_high_int (operands[1]));
184: return \"ld.d %1,%0\";
185: }
186: else if (GET_CODE (operands[1]) == CONST_DOUBLE && LD_L_P (operands[1]))
187: {
188: operands[1] = gen_rtx (CONST_INT, VOIDmode,
189: const_double_low_int (operands[1]));
190: return \"ld.l %1,%0\";
191: }
192: else
193: return \"ld.l %1,%0\";
194: }")
195:
196: (define_insn "movsf"
197: [(set (match_operand:SF 0 "general_operand" "=g,d")
198: (match_operand:SF 1 "general_operand" "d,gF"))]
199: ""
200: "*
201: {
202: if (push_operand (operands[0], SFmode))
203: return \"psh.w %1\";
204: else if (GET_CODE (operands[0]) == MEM)
205: return \"st.s %1,%0\";
206: else if (GET_CODE (operands[1]) == REG)
207: return \"mov.s %1,%0\";
208: else
209: return \"ld.s %1,%0\";
210: }")
211:
212: (define_insn "movdi"
213: [(set (match_operand:DI 0 "general_operand" "=g,d")
214: (match_operand:DI 1 "general_operand" "d,dmiG"))]
215: ""
216: "*
217: {
218: if (push_operand (operands[0], DImode))
219: return \"psh.l %1\";
220: else if (GET_CODE (operands[0]) == MEM)
221: return \"st.l %1,%0\";
222: else if (GET_CODE (operands[1]) == REG)
223: return \"mov %1,%0\";
224: else if (GET_CODE (operands[1]) == CONST_DOUBLE && LD_D_P (operands[1]))
225: {
226: operands[1] = gen_rtx (CONST_INT, VOIDmode,
227: const_double_high_int (operands[1]));
228: return \"ld.d %1,%0\";
229: }
230: else
231: return \"ld.l %1,%0\";
232: }")
233:
234: ;; Special case of movsi, needed to express A-reg preference.
235:
236: (define_insn ""
237: [(set (match_operand:SI 0 "push_operand" "=<")
238: (plus:SI (match_operand:SI 1 "register_operand" "a")
239: (match_operand:SI 2 "immediate_operand" "i")))]
240: "operands[1] != stack_pointer_rtx"
241: "pshea %a2(%1)")
242:
243: ;; General movsi. Constraints will be selected based on TARGET_INDIRECTS
244: ;; to avoid indirect addressing on C3, where it is slow.
245:
246: (define_expand "movsi"
247: [(set (match_operand:SI 0 "general_operand" "")
248: (match_operand:SI 1 "general_operand" ""))]
249: ""
250: "")
251:
252: (define_insn ""
253: [(set (match_operand:SI 0 "general_operand" "=g,r,<")
254: (match_operand:SI 1 "general_operand" "r,g,io"))]
255: "TARGET_INDIRECTS"
256: "*
257: {
258: if (push_operand (operands[0], SImode))
259: {
260: if (GET_CODE (operands[1]) == REG)
261: return \"psh.w %1\";
262: else
263: return \"pshea %a1\";
264: }
265: if (GET_CODE (operands[0]) == MEM)
266: return \"st.w %1,%0\";
267: if (GET_CODE (operands[1]) != REG)
268: return \"ld.w %1,%0\";
269: if (S_REG_P (operands[0]) && S_REG_P (operands[1]))
270: return \"mov.w %1,%0\";
271: return \"mov %1,%0\";
272: }")
273:
274: (define_insn ""
275: [(set (match_operand:SI 0 "general_operand" "=g,r,<")
276: (match_operand:SI 1 "general_operand" "r,g,i"))]
277: "! TARGET_INDIRECTS"
278: "*
279: {
280: if (push_operand (operands[0], SImode))
281: {
282: if (GET_CODE (operands[1]) == REG)
283: return \"psh.w %1\";
284: else
285: return \"pshea %a1\";
286: }
287: if (GET_CODE (operands[0]) == MEM)
288: return \"st.w %1,%0\";
289: if (GET_CODE (operands[1]) != REG)
290: return \"ld.w %1,%0\";
291: if (S_REG_P (operands[0]) && S_REG_P (operands[1]))
292: return \"mov.w %1,%0\";
293: return \"mov %1,%0\";
294: }")
295:
296: (define_insn "movstrictsi"
297: [(set (strict_low_part (match_operand:SI 0 "general_operand" "=g,r"))
298: (match_operand:SI 1 "general_operand" "r,g"))]
299: ""
300: "*
301: {
302: if (GET_CODE (operands[0]) == MEM)
303: return \"st.w %1,%0\";
304: if (GET_CODE (operands[1]) != REG)
305: return \"ld.w %1,%0\";
306: if (S_REG_P (operands[0]) && S_REG_P (operands[1]))
307: return \"mov.w %1,%0\";
308: return \"mov %1,%0\";
309: }")
310:
311: (define_insn "movhi"
312: [(set (match_operand:HI 0 "general_operand" "=g,r")
313: (match_operand:HI 1 "general_operand" "r,g"))]
314: ""
315: "*
316: {
317: if (push_operand (operands[0], HImode))
318: abort ();
319: else if (GET_CODE (operands[0]) == MEM)
320: return \"st.h %1,%0\";
321: else if (GET_CODE (operands[1]) == REG)
322: {
323: if (S_REG_P (operands[0]) && S_REG_P (operands[1]))
324: return \"mov.w %1,%0\";
325: else
326: return \"mov %1,%0\";
327: }
328: else if (GET_CODE (operands[1]) == CONST_INT)
329: return \"ld.w %1,%0\";
330: else
331: return \"ld.h %1,%0\";
332: }")
333:
334: (define_insn "movqi"
335: [(set (match_operand:QI 0 "general_operand" "=g,r")
336: (match_operand:QI 1 "general_operand" "r,g"))]
337: ""
338: "*
339: {
340: if (push_operand (operands[0], QImode))
341: abort ();
342: else if (GET_CODE (operands[0]) == MEM)
343: return \"st.b %1,%0\";
344: else if (GET_CODE (operands[1]) == REG)
345: {
346: if (S_REG_P (operands[0]) && S_REG_P (operands[1]))
347: return \"mov.w %1,%0\";
348: else
349: return \"mov %1,%0\";
350: }
351: else if (GET_CODE (operands[1]) == CONST_INT)
352: return \"ld.w %1,%0\";
353: else
354: return \"ld.b %1,%0\";
355: }")
356:
357: ;; Extension and truncation insns.
358: ;; Those for integer source operand
359: ;; are ordered widest source type first.
360:
361: (define_insn "truncsiqi2"
362: [(set (match_operand:QI 0 "register_operand" "=d,a")
363: (truncate:QI (match_operand:SI 1 "register_operand" "d,a")))]
364: ""
365: "cvtw.b %1,%0")
366:
367: (define_insn "truncsihi2"
368: [(set (match_operand:HI 0 "register_operand" "=d,a")
369: (truncate:HI (match_operand:SI 1 "register_operand" "d,a")))]
370: ""
371: "cvtw.h %1,%0")
372:
373: (define_insn "trunchiqi2"
374: [(set (match_operand:QI 0 "register_operand" "=r")
375: (truncate:QI (match_operand:HI 1 "register_operand" "0")))]
376: ""
377: "")
378:
379: (define_insn "truncdisi2"
380: [(set (match_operand:SI 0 "register_operand" "=d")
381: (truncate:SI (match_operand:DI 1 "register_operand" "d")))]
382: ""
383: "cvtl.w %1,%0")
384:
385: (define_insn "extendsidi2"
386: [(set (match_operand:DI 0 "register_operand" "=d")
387: (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))]
388: ""
389: "cvtw.l %1,%0")
390:
391: (define_insn "extendhisi2"
392: [(set (match_operand:SI 0 "register_operand" "=d,a")
393: (sign_extend:SI (match_operand:HI 1 "register_operand" "d,a")))]
394: ""
395: "cvth.w %1,%0")
396:
397: (define_insn "extendqihi2"
398: [(set (match_operand:HI 0 "register_operand" "=d,a")
399: (sign_extend:HI (match_operand:QI 1 "register_operand" "d,a")))]
400: ""
401: "cvtb.w %1,%0")
402:
403: (define_insn "extendqisi2"
404: [(set (match_operand:SI 0 "register_operand" "=d,a")
405: (sign_extend:SI (match_operand:QI 1 "register_operand" "d,a")))]
406: ""
407: "cvtb.w %1,%0")
408:
409: (define_insn "extendsfdf2"
410: [(set (match_operand:DF 0 "register_operand" "=d")
411: (float_extend:DF (match_operand:SF 1 "register_operand" "d")))]
412: ""
413: "cvts.d %1,%0")
414:
415: (define_insn "truncdfsf2"
416: [(set (match_operand:SF 0 "register_operand" "=d")
417: (float_truncate:SF (match_operand:DF 1 "register_operand" "d")))]
418: ""
419: "cvtd.s %1,%0")
420:
421: (define_insn "zero_extendhisi2"
422: [(set (match_operand:SI 0 "register_operand" "=r")
423: (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
424: ""
425: "and #0xffff,%0")
426:
427: (define_insn "zero_extendqihi2"
428: [(set (match_operand:HI 0 "register_operand" "=r")
429: (zero_extend:HI (match_operand:QI 1 "register_operand" "0")))]
430: ""
431: "and #0xff,%0")
432:
433: (define_insn "zero_extendqisi2"
434: [(set (match_operand:SI 0 "register_operand" "=r")
435: (zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]
436: ""
437: "and #0xff,%0")
438:
439: (define_insn "zero_extendsidi2"
440: [(set (match_operand:DI 0 "register_operand" "=d")
441: (zero_extend:DI (match_operand:SI 1 "register_operand" "0")))]
442: ""
443: "ld.u #0,%0")
444:
445: ;; Fix-to-float conversion insns.
446: ;; Note that the ones that start with SImode come first.
447: ;; That is so that an operand that is a CONST_INT
448: ;; (and therefore lacks a specific machine mode).
449: ;; will be recognized as SImode (which is always valid)
450: ;; rather than as QImode or HImode.
451:
452: (define_insn "floatsisf2"
453: [(set (match_operand:SF 0 "register_operand" "=d")
454: (float:SF (match_operand:SI 1 "register_operand" "d")))]
455: ""
456: "cvtw.s %1,%0")
457:
458: (define_insn "floatdisf2"
459: [(set (match_operand:SF 0 "register_operand" "=d")
460: (float:SF (match_operand:DI 1 "register_operand" "d")))]
461: ""
462: "cvtl.s %1,%0")
463:
464: (define_insn "floatsidf2"
465: [(set (match_operand:DF 0 "register_operand" "=d")
466: (float:DF (match_operand:SI 1 "register_operand" "d")))]
467: "TARGET_C2"
468: "cvtw.d %1,%0")
469:
470: (define_insn "floatdidf2"
471: [(set (match_operand:DF 0 "register_operand" "=d")
472: (float:DF (match_operand:DI 1 "register_operand" "d")))]
473: ""
474: "cvtl.d %1,%0")
475:
476: ;; Float-to-fix conversion insns.
477:
478: (define_insn "fix_truncsfsi2"
479: [(set (match_operand:SI 0 "register_operand" "=d")
480: (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "d"))))]
481: ""
482: "cvts.w %1,%0")
483:
484: (define_insn "fix_truncsfdi2"
485: [(set (match_operand:DI 0 "register_operand" "=d")
486: (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "d"))))]
487: ""
488: "cvts.l %1,%0")
489:
490: (define_insn "fix_truncdfsi2"
491: [(set (match_operand:SI 0 "register_operand" "=d")
492: (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
493: ""
494: "*
495: {
496: if (TARGET_C2)
497: return \"cvtd.w %1,%0\";
498: return \"cvtd.l %1,%0\";
499: }")
500:
501: (define_insn "fix_truncdfdi2"
502: [(set (match_operand:DI 0 "register_operand" "=d")
503: (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
504: ""
505: "cvtd.l %1,%0")
506:
507: ;;- All kinds of add instructions.
508:
509: (define_insn "adddf3"
510: [(set (match_operand:DF 0 "register_operand" "=d")
511: (plus:DF (match_operand:DF 1 "register_operand" "%0")
512: (match_operand:DF 2 "register_operand" "d")))]
513: ""
514: "add.d %2,%0")
515:
516: (define_insn "addsf3"
517: [(set (match_operand:SF 0 "register_operand" "=d")
518: (plus:SF (match_operand:SF 1 "register_operand" "%0")
519: (match_operand:SF 2 "nonmemory_operand" "dF")))]
520: ""
521: "add.s %2,%0")
522:
523: (define_insn "adddi3"
524: [(set (match_operand:DI 0 "register_operand" "=d")
525: (plus:DI (match_operand:DI 1 "register_operand" "%0")
526: (match_operand:DI 2 "register_operand" "d")))]
527: ""
528: "add.l %2,%0")
529:
530: ;; special case of addsi3, needed to specify an A reg for the destination
531: ;; when the source is a sum involving FP or AP.
532:
533: (define_insn ""
534: [(set (match_operand:SI 0 "register_operand" "=a")
535: (plus:SI (match_operand:SI 1 "register_operand" "%a")
536: (match_operand:SI 2 "immediate_operand" "i")))]
537: "operands[1] == frame_pointer_rtx || operands[1] == arg_pointer_rtx"
538: "ldea %a2(%1),%0")
539:
540: (define_insn "addsi3"
541: [(set (match_operand:SI 0 "register_operand" "=d,a,a")
542: (plus:SI (match_operand:SI 1 "nonmemory_operand" "%0,0,a")
543: (match_operand:SI 2 "nonmemory_operand" "di,ri,i")))]
544: ""
545: "* switch (which_alternative)
546: {
547: case 0:
548: case 1:
549: return \"add.w %2,%0\";
550: case 2:
551: if ((TARGET_C2 || A_REG_P (operands[0]))
552: && operands[1] != stack_pointer_rtx)
553: return \"ldea %a2(%1),%0\";
554: else
555: return \"mov %1,%0\;add.w %2,%0\";
556: }")
557:
558: (define_insn "addhi3"
559: [(set (match_operand:HI 0 "register_operand" "=d,a")
560: (plus:HI (match_operand:HI 1 "register_operand" "%0,0")
561: (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
562: ""
563: "add.h %2,%0")
564:
565: (define_insn "addqi3"
566: [(set (match_operand:QI 0 "register_operand" "=d")
567: (plus:QI (match_operand:QI 1 "register_operand" "%0")
568: (match_operand:QI 2 "register_operand" "d")))]
569: ""
570: "add.b %2,%0")
571:
572: ;;- All kinds of subtract instructions.
573:
574: (define_insn "subdf3"
575: [(set (match_operand:DF 0 "register_operand" "=d")
576: (minus:DF (match_operand:DF 1 "register_operand" "0")
577: (match_operand:DF 2 "register_operand" "d")))]
578: ""
579: "sub.d %2,%0")
580:
581: (define_insn "subsf3"
582: [(set (match_operand:SF 0 "register_operand" "=d")
583: (minus:SF (match_operand:SF 1 "register_operand" "0")
584: (match_operand:SF 2 "nonmemory_operand" "dF")))]
585: ""
586: "sub.s %2,%0")
587:
588: (define_insn "subdi3"
589: [(set (match_operand:DI 0 "register_operand" "=d")
590: (minus:DI (match_operand:DI 1 "register_operand" "0")
591: (match_operand:DI 2 "register_operand" "d")))]
592: ""
593: "sub.l %2,%0")
594:
595: (define_insn "subsi3"
596: [(set (match_operand:SI 0 "register_operand" "=d,a")
597: (minus:SI (match_operand:SI 1 "register_operand" "0,0")
598: (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
599: ""
600: "sub.w %2,%0")
601:
602: (define_insn "subhi3"
603: [(set (match_operand:HI 0 "register_operand" "=d,a")
604: (minus:HI (match_operand:HI 1 "register_operand" "0,0")
605: (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
606: ""
607: "sub.h %2,%0")
608:
609: (define_insn "subqi3"
610: [(set (match_operand:QI 0 "register_operand" "=d")
611: (minus:QI (match_operand:QI 1 "register_operand" "0")
612: (match_operand:QI 2 "register_operand" "d")))]
613: ""
614: "sub.b %2,%0")
615:
616: ;;- Multiply instructions.
617:
618: (define_insn "muldf3"
619: [(set (match_operand:DF 0 "register_operand" "=d")
620: (mult:DF (match_operand:DF 1 "register_operand" "%0")
621: (match_operand:DF 2 "register_operand" "d")))]
622: ""
623: "mul.d %2,%0")
624:
625: (define_insn "mulsf3"
626: [(set (match_operand:SF 0 "register_operand" "=d")
627: (mult:SF (match_operand:SF 1 "register_operand" "%0")
628: (match_operand:SF 2 "nonmemory_operand" "dF")))]
629: ""
630: "mul.s %2,%0")
631:
632: (define_insn "muldi3"
633: [(set (match_operand:DI 0 "register_operand" "=d")
634: (mult:DI (match_operand:DI 1 "register_operand" "%0")
635: (match_operand:DI 2 "register_operand" "d")))]
636: ""
637: "mul.l %2,%0")
638:
639: (define_insn "mulsi3"
640: [(set (match_operand:SI 0 "register_operand" "=d,a")
641: (mult:SI (match_operand:SI 1 "register_operand" "%0,0")
642: (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
643: ""
644: "mul.w %2,%0")
645:
646: (define_insn "mulhi3"
647: [(set (match_operand:HI 0 "register_operand" "=d,a")
648: (mult:HI (match_operand:HI 1 "register_operand" "%0,0")
649: (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
650: ""
651: "mul.h %2,%0")
652:
653: (define_insn "mulqi3"
654: [(set (match_operand:QI 0 "register_operand" "=d")
655: (mult:QI (match_operand:QI 1 "register_operand" "%0")
656: (match_operand:QI 2 "register_operand" "d")))]
657: ""
658: "mul.b %2,%0")
659:
660: ;;- Divide instructions.
661:
662: (define_insn "divdf3"
663: [(set (match_operand:DF 0 "register_operand" "=d")
664: (div:DF (match_operand:DF 1 "register_operand" "0")
665: (match_operand:DF 2 "register_operand" "d")))]
666: ""
667: "div.d %2,%0")
668:
669: (define_insn "divsf3"
670: [(set (match_operand:SF 0 "register_operand" "=d")
671: (div:SF (match_operand:SF 1 "register_operand" "0")
672: (match_operand:SF 2 "nonmemory_operand" "dF")))]
673: ""
674: "div.s %2,%0")
675:
676: (define_insn "divdi3"
677: [(set (match_operand:DI 0 "register_operand" "=d")
678: (div:DI (match_operand:DI 1 "register_operand" "0")
679: (match_operand:DI 2 "register_operand" "d")))]
680: ""
681: "div.l %2,%0")
682:
683: (define_insn "udivdi3"
684: [(set (match_operand:DI 0 "register_operand" "=d")
685: (udiv:DI (match_operand:DI 1 "register_operand" "d")
686: (match_operand:DI 2 "register_operand" "d")))]
687: ""
688: "psh.l %2\;psh.l %1\;callq udiv64\;pop.l %0\;add.w #8,sp")
689:
690: (define_insn "divsi3"
691: [(set (match_operand:SI 0 "register_operand" "=d,a")
692: (div:SI (match_operand:SI 1 "register_operand" "0,0")
693: (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
694: ""
695: "div.w %2,%0")
696:
697: (define_insn "divhi3"
698: [(set (match_operand:HI 0 "register_operand" "=d,a")
699: (div:HI (match_operand:HI 1 "register_operand" "0,0")
700: (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
701: ""
702: "div.h %2,%0")
703:
704: (define_insn "divqi3"
705: [(set (match_operand:QI 0 "register_operand" "=d")
706: (div:QI (match_operand:QI 1 "register_operand" "0")
707: (match_operand:QI 2 "register_operand" "d")))]
708: ""
709: "div.b %2,%0")
710:
711: ;; - and, or, xor
712:
713: (define_insn ""
714: [(set (match_operand:DI 0 "register_operand" "=d")
715: (and:DI (match_operand:DI 1 "register_operand" "%0")
716: (match_operand:DI 2 "immediate_operand" "Fn")))]
717: "GET_CODE (operands[2]) == CONST_INT
718: || (GET_CODE (operands[2]) == CONST_DOUBLE
719: && CONST_DOUBLE_HIGH (operands[2]) == -1)"
720: "and %2,%0")
721:
722: (define_insn "anddi3"
723: [(set (match_operand:DI 0 "register_operand" "=d")
724: (and:DI (match_operand:DI 1 "register_operand" "%0")
725: (match_operand:DI 2 "register_operand" "d")))]
726: ""
727: "and %2,%0")
728:
729: (define_insn "andsi3"
730: [(set (match_operand:SI 0 "register_operand" "=d,a")
731: (and:SI (match_operand:SI 1 "register_operand" "%0,0")
732: (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
733: ""
734: "and %2,%0")
735:
736: (define_insn "andhi3"
737: [(set (match_operand:HI 0 "register_operand" "=d,a")
738: (and:HI (match_operand:HI 1 "register_operand" "%0,0")
739: (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
740: ""
741: "and %2,%0")
742:
743: (define_insn "andqi3"
744: [(set (match_operand:QI 0 "register_operand" "=d,a")
745: (and:QI (match_operand:QI 1 "register_operand" "%0,0")
746: (match_operand:QI 2 "nonmemory_operand" "di,ai")))]
747: ""
748: "and %2,%0")
749:
750: ;;- Bit set instructions.
751:
752: (define_insn ""
753: [(set (match_operand:DI 0 "register_operand" "=d")
754: (ior:DI (match_operand:DI 1 "register_operand" "%0")
755: (match_operand:DI 2 "immediate_operand" "Fn")))]
756: "GET_CODE (operands[2]) == CONST_INT
757: || (GET_CODE (operands[2]) == CONST_DOUBLE
758: && CONST_DOUBLE_HIGH (operands[2]) == 0)"
759: "or %2,%0")
760:
761: (define_insn "iordi3"
762: [(set (match_operand:DI 0 "register_operand" "=d")
763: (ior:DI (match_operand:DI 1 "register_operand" "%0")
764: (match_operand:DI 2 "register_operand" "d")))]
765: ""
766: "or %2,%0")
767:
768: (define_insn "iorsi3"
769: [(set (match_operand:SI 0 "register_operand" "=d,a")
770: (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
771: (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
772: ""
773: "or %2,%0")
774:
775: (define_insn "iorhi3"
776: [(set (match_operand:HI 0 "register_operand" "=d,a")
777: (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
778: (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
779: ""
780: "or %2,%0")
781:
782: (define_insn "iorqi3"
783: [(set (match_operand:QI 0 "register_operand" "=d,a")
784: (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
785: (match_operand:QI 2 "nonmemory_operand" "di,ai")))]
786: ""
787: "or %2,%0")
788:
789: ;;- xor instructions.
790:
791: (define_insn ""
792: [(set (match_operand:DI 0 "register_operand" "=d")
793: (xor:DI (match_operand:DI 1 "register_operand" "%0")
794: (match_operand:DI 2 "immediate_operand" "Fn")))]
795: "GET_CODE (operands[2]) == CONST_INT
796: || (GET_CODE (operands[2]) == CONST_DOUBLE
797: && CONST_DOUBLE_HIGH (operands[2]) == 0)"
798: "xor %2,%0")
799:
800: (define_insn "xordi3"
801: [(set (match_operand:DI 0 "register_operand" "=d")
802: (xor:DI (match_operand:DI 1 "register_operand" "%0")
803: (match_operand:DI 2 "register_operand" "d")))]
804: ""
805: "xor %2,%0")
806:
807: (define_insn "xorsi3"
808: [(set (match_operand:SI 0 "register_operand" "=d,a")
809: (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
810: (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
811: ""
812: "xor %2,%0")
813:
814: (define_insn "xorhi3"
815: [(set (match_operand:HI 0 "register_operand" "=d,a")
816: (xor:HI (match_operand:HI 1 "register_operand" "%0,0")
817: (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
818: ""
819: "xor %2,%0")
820:
821: (define_insn "xorqi3"
822: [(set (match_operand:QI 0 "register_operand" "=d,a")
823: (xor:QI (match_operand:QI 1 "register_operand" "%0,0")
824: (match_operand:QI 2 "nonmemory_operand" "di,ai")))]
825: ""
826: "xor %2,%0")
827:
828: (define_insn "negdf2"
829: [(set (match_operand:DF 0 "register_operand" "=d")
830: (neg:DF (match_operand:DF 1 "register_operand" "d")))]
831: ""
832: "neg.d %1,%0")
833:
834: (define_insn "negsf2"
835: [(set (match_operand:SF 0 "register_operand" "=d")
836: (neg:SF (match_operand:SF 1 "register_operand" "d")))]
837: ""
838: "neg.s %1,%0")
839:
840: (define_insn "negdi2"
841: [(set (match_operand:DI 0 "register_operand" "=d")
842: (neg:DI (match_operand:DI 1 "register_operand" "d")))]
843: ""
844: "neg.l %1,%0")
845:
846: (define_insn "negsi2"
847: [(set (match_operand:SI 0 "register_operand" "=d,a")
848: (neg:SI (match_operand:SI 1 "register_operand" "d,a")))]
849: ""
850: "neg.w %1,%0")
851:
852: (define_insn "neghi2"
853: [(set (match_operand:HI 0 "register_operand" "=d,a")
854: (neg:HI (match_operand:HI 1 "register_operand" "d,a")))]
855: ""
856: "neg.h %1,%0")
857:
858: (define_insn "negqi2"
859: [(set (match_operand:QI 0 "register_operand" "=d")
860: (neg:QI (match_operand:QI 1 "register_operand" "d")))]
861: ""
862: "neg.b %1,%0")
863:
864: (define_insn "one_cmpldi2"
865: [(set (match_operand:DI 0 "register_operand" "=d")
866: (not:DI (match_operand:DI 1 "register_operand" "d")))]
867: ""
868: "not %1,%0")
869:
870: (define_insn "one_cmplsi2"
871: [(set (match_operand:SI 0 "register_operand" "=d,a")
872: (not:SI (match_operand:SI 1 "register_operand" "d,a")))]
873: ""
874: "not %1,%0")
875:
876: (define_insn "one_cmplhi2"
877: [(set (match_operand:HI 0 "register_operand" "=d,a")
878: (not:HI (match_operand:HI 1 "register_operand" "d,a")))]
879: ""
880: "not %1,%0")
881:
882: (define_insn "one_cmplqi2"
883: [(set (match_operand:QI 0 "register_operand" "=d,a")
884: (not:QI (match_operand:QI 1 "register_operand" "d,a")))]
885: ""
886: "not %1,%0")
887:
888: ;;- shifts
889: ;;
890: ;; Convex shift instructions are logical shifts.
891: ;; To make signed right shifts:
892: ;; for SImode, sign extend to DImode and shift, works for 0..32
893: ;; for DImode, shift and then extend the sign, works for 0..63 -- but not 64
894:
895: (define_insn "lshlsi3"
896: [(set (match_operand:SI 0 "register_operand" "=d,a")
897: (lshift:SI (match_operand:SI 1 "register_operand" "0,0")
898: (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
899: ""
900: "*
901: {
902: if (operands[2] == const1_rtx)
903: return \"add.w %0,%0\";
904: else if (TARGET_C2 && S_REG_P (operands[0]))
905: return \"shf.w %2,%0\";
906: else
907: return \"shf %2,%0\";
908: }")
909:
910: (define_insn "ashlsi3"
911: [(set (match_operand:SI 0 "register_operand" "=d,a")
912: (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
913: (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
914: ""
915: "*
916: {
917: if (operands[2] == const1_rtx)
918: return \"add.w %0,%0\";
919: else if (TARGET_C2 && S_REG_P (operands[0]))
920: return \"shf.w %2,%0\";
921: else
922: return \"shf %2,%0\";
923: }")
924:
925: (define_expand "lshrsi3"
926: [(set (match_operand:SI 0 "register_operand" "")
927: (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
928: (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))]
929: ""
930: "operands[2] = negate_rtx (SImode, operands[2]);")
931:
932: (define_insn ""
933: [(set
934: (match_operand:SI 0 "register_operand" "=d,a")
935: (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
936: (neg:SI (match_operand:SI 2 "nonmemory_operand" "di,ai"))))]
937: ""
938: "*
939: {
940: if (A_REG_P (operands[0]))
941: return \"shf %2,%0\";
942: else if (TARGET_C2)
943: return \"shf.w %2,%0\";
944: else
945: return \"ld.u #0,%0\;shf %2,%0\";
946: }")
947:
948: (define_insn ""
949: [(set
950: (match_operand:SI 0 "register_operand" "=r")
951: (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
952: (match_operand:SI 2 "immediate_operand" "i")))]
953: ""
954: "*
955: {
956: if (A_REG_P (operands[0]))
957: return \"shf #%n2,%0\";
958: else if (TARGET_C2)
959: return \"shf.w #%n2,%0\";
960: else
961: return \"ld.u #0,%0\;shf #%n2,%0\";
962: }")
963:
964: (define_expand "ashrsi3"
965: [(set (match_operand:SI 0 "register_operand" "=d")
966: (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
967: (neg:SI (match_operand:SI 2 "nonmemory_operand" "di"))))]
968: ""
969: "operands[2] = negate_rtx (SImode, operands[2]);")
970:
971: (define_insn ""
972: [(set (match_operand:SI 0 "register_operand" "=&d")
973: (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
974: (neg:SI (match_operand:SI 2 "nonmemory_operand" "di"))))]
975: ""
976: "cvtw.l %1,%0\;shf %2,%0")
977:
978: (define_insn ""
979: [(set (match_operand:SI 0 "register_operand" "=&d")
980: (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
981: (match_operand:SI 2 "immediate_operand" "i")))]
982: ""
983: "cvtw.l %1,%0\;shf #%n2,%0")
984:
985: (define_insn "lshldi3"
986: [(set (match_operand:DI 0 "register_operand" "=d")
987: (lshift:DI (match_operand:DI 1 "register_operand" "0")
988: (match_operand:SI 2 "nonmemory_operand" "di")))]
989: ""
990: "shf %2,%0")
991:
992: (define_insn "ashldi3"
993: [(set (match_operand:DI 0 "register_operand" "=d")
994: (ashift:DI (match_operand:DI 1 "register_operand" "0")
995: (match_operand:SI 2 "nonmemory_operand" "di")))]
996: ""
997: "shf %2,%0")
998:
999: (define_expand "lshrdi3"
1000: [(set (match_operand:DI 0 "register_operand" "=d")
1001: (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
1002: (neg:SI (match_operand:SI 2 "nonmemory_operand" "di"))))]
1003: ""
1004: "operands[2] = negate_rtx (SImode, operands[2]);")
1005:
1006: (define_insn ""
1007: [(set (match_operand:DI 0 "register_operand" "=d")
1008: (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
1009: (neg:SI (match_operand:SI 2 "nonmemory_operand" "di"))))]
1010: ""
1011: "shf %2,%0")
1012:
1013: (define_insn ""
1014: [(set (match_operand:DI 0 "register_operand" "=d")
1015: (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
1016: (match_operand:SI 2 "immediate_operand" "i")))]
1017: ""
1018: "shf #%n2,%0")
1019:
1020: ;; signed a >> b is
1021: ;; ((a >> b) ^ signbit) - signbit
1022: ;; where signbit is (1 << 63) >> b
1023:
1024: (define_expand "ashrdi3"
1025: [(match_operand:DI 0 "register_operand" "")
1026: (match_operand:DI 1 "register_operand" "")
1027: (match_operand:SI 2 "nonmemory_operand" "")
1028: (match_dup 3)]
1029: ""
1030: "
1031: {
1032: if (GET_CODE (operands[2]) == CONST_INT)
1033: {
1034: int rshift = INTVAL (operands[2]);
1035: operands[3] =
1036: force_reg (DImode, immed_double_const (1 << (63 - rshift),
1037: 1 << (31 - rshift), DImode));
1038: }
1039: else
1040: {
1041: operands[3] =
1042: force_reg (DImode, immed_double_const (0, 1 << 31, DImode));
1043: emit_insn (gen_lshrdi3 (operands[3], operands[3], operands[2]));
1044: }
1045:
1046: emit_insn (gen_lshrdi3 (operands[0], operands[1], operands[2]));
1047: emit_insn (gen_rtx (SET, VOIDmode, operands[0],
1048: gen_rtx (XOR, DImode, operands[0], operands[3])));
1049: emit_insn (gen_rtx (SET, VOIDmode, operands[0],
1050: gen_rtx (MINUS, DImode, operands[0], operands[3])));
1051: DONE;
1052: }")
1053:
1054: ;; __builtin instructions
1055:
1056: (define_insn "sqrtdf2"
1057: [(set (match_operand:DF 0 "register_operand" "=d")
1058: (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
1059: "TARGET_C2"
1060: "sqrt.d %0")
1061:
1062: (define_insn "sqrtsf2"
1063: [(set (match_operand:SF 0 "register_operand" "=d")
1064: (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
1065: "TARGET_C2"
1066: "sqrt.s %0")
1067:
1068: ;(define_insn ""
1069: ; [(set (match_operand:SI 0 "register_operand" "=d")
1070: ; (minus:SI (ffs:SI (match_operand:SI 1 "register_operand" "d"))
1071: ; (const_int 1)))]
1072: ; ""
1073: ; "tzc %1,%0\;le.w #32,%0\;jbrs.f .+6\;ld.w #-1,%0")
1074: ;
1075: ;(define_expand "ffssi2"
1076: ; [(set (match_operand:SI 0 "register_operand" "=d")
1077: ; (minus:SI (ffs:SI (match_operand:SI 1 "register_operand" "d"))
1078: ; (const_int 1)))
1079: ; (set (match_dup 0)
1080: ; (plus:SI (match_dup 0)
1081: ; (const_int 1)))]
1082: ; ""
1083: ; "")
1084:
1085: (define_insn "abssf2"
1086: [(set (match_operand:SF 0 "register_operand" "=d")
1087: (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1088: ""
1089: "and #0x7fffffff,%0")
1090:
1091: (define_expand "absdf2"
1092: [(set (subreg:DI (match_operand:DF 0 "register_operand" "=d") 0)
1093: (and:DI (subreg:DI (match_operand:DF 1 "register_operand" "d") 0)
1094: (match_dup 2)))]
1095: ""
1096: "operands[2] = force_reg (DImode,
1097: immed_double_const (-1, 0x7fffffff, DImode));")
1098:
1099: ;; Jumps
1100:
1101: (define_insn "jump"
1102: [(set (pc)
1103: (label_ref (match_operand 0 "" "")))]
1104: ""
1105: "jbr %l0")
1106:
1107: (define_insn "beq"
1108: [(set (pc)
1109: (if_then_else (eq (cc0)
1110: (const_int 0))
1111: (label_ref (match_operand 0 "" ""))
1112: (pc)))]
1113: ""
1114: "* return gen_cmp (operands[0], \"eq\", 't'); ")
1115:
1116: (define_insn "bne"
1117: [(set (pc)
1118: (if_then_else (ne (cc0)
1119: (const_int 0))
1120: (label_ref (match_operand 0 "" ""))
1121: (pc)))]
1122: ""
1123: "* return gen_cmp (operands[0], \"eq\", 'f'); ")
1124:
1125: (define_insn "bgt"
1126: [(set (pc)
1127: (if_then_else (gt (cc0)
1128: (const_int 0))
1129: (label_ref (match_operand 0 "" ""))
1130: (pc)))]
1131: ""
1132: "* return gen_cmp (operands[0], \"le\", 'f'); ")
1133:
1134: (define_insn "bgtu"
1135: [(set (pc)
1136: (if_then_else (gtu (cc0)
1137: (const_int 0))
1138: (label_ref (match_operand 0 "" ""))
1139: (pc)))]
1140: ""
1141: "* return gen_cmp (operands[0], \"leu\", 'f'); ")
1142:
1143: (define_insn "blt"
1144: [(set (pc)
1145: (if_then_else (lt (cc0)
1146: (const_int 0))
1147: (label_ref (match_operand 0 "" ""))
1148: (pc)))]
1149: ""
1150: "* return gen_cmp (operands[0], \"lt\", 't'); ")
1151:
1152: (define_insn "bltu"
1153: [(set (pc)
1154: (if_then_else (ltu (cc0)
1155: (const_int 0))
1156: (label_ref (match_operand 0 "" ""))
1157: (pc)))]
1158: ""
1159: "* return gen_cmp (operands[0], \"ltu\", 't'); ")
1160:
1161: (define_insn "bge"
1162: [(set (pc)
1163: (if_then_else (ge (cc0)
1164: (const_int 0))
1165: (label_ref (match_operand 0 "" ""))
1166: (pc)))]
1167: ""
1168: "* return gen_cmp (operands[0], \"lt\", 'f'); ")
1169:
1170: (define_insn "bgeu"
1171: [(set (pc)
1172: (if_then_else (geu (cc0)
1173: (const_int 0))
1174: (label_ref (match_operand 0 "" ""))
1175: (pc)))]
1176: ""
1177: "* return gen_cmp (operands[0], \"ltu\", 'f'); ")
1178:
1179: (define_insn "ble"
1180: [(set (pc)
1181: (if_then_else (le (cc0)
1182: (const_int 0))
1183: (label_ref (match_operand 0 "" ""))
1184: (pc)))]
1185: ""
1186: "* return gen_cmp (operands[0], \"le\", 't'); ")
1187:
1188: (define_insn "bleu"
1189: [(set (pc)
1190: (if_then_else (leu (cc0)
1191: (const_int 0))
1192: (label_ref (match_operand 0 "" ""))
1193: (pc)))]
1194: ""
1195: "* return gen_cmp (operands[0], \"leu\", 't'); ")
1196:
1197: (define_insn ""
1198: [(set (pc)
1199: (if_then_else (eq (cc0)
1200: (const_int 0))
1201: (pc)
1202: (label_ref (match_operand 0 "" ""))))]
1203: ""
1204: "* return gen_cmp (operands[0], \"eq\", 'f'); ")
1205:
1206: (define_insn ""
1207: [(set (pc)
1208: (if_then_else (ne (cc0)
1209: (const_int 0))
1210: (pc)
1211: (label_ref (match_operand 0 "" ""))))]
1212: ""
1213: "* return gen_cmp (operands[0], \"eq\", 't'); ")
1214:
1215: (define_insn ""
1216: [(set (pc)
1217: (if_then_else (gt (cc0)
1218: (const_int 0))
1219: (pc)
1220: (label_ref (match_operand 0 "" ""))))]
1221: ""
1222: "* return gen_cmp (operands[0], \"le\", 't'); ")
1223:
1224: (define_insn ""
1225: [(set (pc)
1226: (if_then_else (gtu (cc0)
1227: (const_int 0))
1228: (pc)
1229: (label_ref (match_operand 0 "" ""))))]
1230: ""
1231: "* return gen_cmp (operands[0], \"leu\", 't'); ")
1232:
1233: (define_insn ""
1234: [(set (pc)
1235: (if_then_else (lt (cc0)
1236: (const_int 0))
1237: (pc)
1238: (label_ref (match_operand 0 "" ""))))]
1239: ""
1240: "* return gen_cmp (operands[0], \"lt\", 'f'); ")
1241:
1242: (define_insn ""
1243: [(set (pc)
1244: (if_then_else (ltu (cc0)
1245: (const_int 0))
1246: (pc)
1247: (label_ref (match_operand 0 "" ""))))]
1248: ""
1249: "* return gen_cmp (operands[0], \"ltu\", 'f'); ")
1250:
1251: (define_insn ""
1252: [(set (pc)
1253: (if_then_else (ge (cc0)
1254: (const_int 0))
1255: (pc)
1256: (label_ref (match_operand 0 "" ""))))]
1257: ""
1258: "* return gen_cmp (operands[0], \"lt\", 't'); ")
1259:
1260: (define_insn ""
1261: [(set (pc)
1262: (if_then_else (geu (cc0)
1263: (const_int 0))
1264: (pc)
1265: (label_ref (match_operand 0 "" ""))))]
1266: ""
1267: "* return gen_cmp (operands[0], \"ltu\", 't'); ")
1268:
1269: (define_insn ""
1270: [(set (pc)
1271: (if_then_else (le (cc0)
1272: (const_int 0))
1273: (pc)
1274: (label_ref (match_operand 0 "" ""))))]
1275: ""
1276: "* return gen_cmp (operands[0], \"le\", 'f'); ")
1277:
1278: (define_insn ""
1279: [(set (pc)
1280: (if_then_else (leu (cc0)
1281: (const_int 0))
1282: (pc)
1283: (label_ref (match_operand 0 "" ""))))]
1284: ""
1285: "* return gen_cmp (operands[0], \"leu\", 'f'); ")
1286:
1287: ;; - Calls
1288: ;;
1289: ;; arg count word may be omitted to save a push and let gcc try to
1290: ;; combine the arg list pop. RETURN_POPS_ARGS from tm.h decides this.
1291:
1292: (define_insn "call"
1293: [(call (match_operand:QI 0 "memory_operand" "m")
1294: (match_operand:SI 1 "general_operand" "g"))]
1295: ""
1296: "* return output_call (insn, operands[0], operands[1]);")
1297:
1298: (define_insn "call_value"
1299: [(set (match_operand 0 "" "=g")
1300: (call (match_operand:QI 1 "memory_operand" "m")
1301: (match_operand:SI 2 "general_operand" "g")))]
1302: ""
1303: "* return output_call (insn, operands[1], operands[2]);")
1304:
1305: (define_insn "return"
1306: [(return)]
1307: ""
1308: "rtn")
1309:
1310: (define_insn "nop"
1311: [(const_int 0)]
1312: ""
1313: "nop")
1314:
1315: (define_insn "tablejump"
1316: [(set (pc) (match_operand:SI 0 "address_operand" "p"))
1317: (use (label_ref (match_operand 1 "" "")))]
1318: ""
1319: "jmp %a0")
1320:
1321: (define_insn "indirect_jump"
1322: [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
1323: ""
1324: "jmp %a0")
1325:
1326: ;;- Local variables:
1327: ;;- mode:emacs-lisp
1328: ;;- comment-start: ";;- "
1329: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
1330: ;;- eval: (modify-syntax-entry ?[ "(]")
1331: ;;- eval: (modify-syntax-entry ?] ")[")
1332: ;;- eval: (modify-syntax-entry ?{ "(}")
1333: ;;- eval: (modify-syntax-entry ?} "){")
1334: ;;- End:
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