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1.1 root 1: ;;- Machine description for GNU compiler
2: ;;- Convex Version
3: ;; Copyright (C) 1991 Free Software Foundation, Inc.
4:
5: ;; This file is part of GNU CC.
6:
7: ;; GNU CC is free software; you can redistribute it and/or modify
8: ;; it under the terms of the GNU General Public License as published by
9: ;; the Free Software Foundation; either version 2, or (at your option)
10: ;; any later version.
11:
12: ;; GNU CC is distributed in the hope that it will be useful,
13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: ;; GNU General Public License for more details.
16:
17: ;; You should have received a copy of the GNU General Public License
18: ;; along with GNU CC; see the file COPYING. If not, write to
19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20:
21: ;; Scheduling defs
22: ;;
23: ;; Insn scheduling is not used at present. Scheduling increases
24: ;; register pressure so much that many spills are generated
25: ;; even for very small functions.
26:
27: ;; Compares
28:
29: (define_insn "tstsi"
30: [(set (cc0)
31: (match_operand:SI 0 "register_operand" "r"))]
32: ""
33: "* return set_cmp (operands[0], const0_rtx, 'w');")
34:
35: (define_insn "tsthi"
36: [(set (cc0)
37: (match_operand:HI 0 "register_operand" "r"))]
38: ""
39: "* return set_cmp (operands[0], const0_rtx, 'h');")
40:
41: (define_expand "tstqi"
42: [(set (match_dup 1)
43: (sign_extend:SI (match_operand:QI 0 "register_operand" "r")))
44: (set (cc0)
45: (match_dup 1))]
46: ""
47: "operands[1] = gen_reg_rtx (SImode);")
48:
49: (define_expand "tstdi"
50: [(parallel [(set (cc0) (match_operand:DI 0 "register_operand" "d"))
51: (use (match_dup 1))])]
52: ""
53: "operands[1] = force_reg (DImode, const0_rtx);")
54:
55: (define_insn ""
56: [(set (cc0) (match_operand:DI 0 "register_operand" "d"))
57: (use (match_operand:DI 1 "register_operand" "d"))]
58: ""
59: "* return set_cmp (operands[0], operands[1], 'l');")
60:
61: (define_expand "tstdf"
62: [(set (cc0)
63: (compare (match_operand:DF 0 "register_operand" "d")
64: (match_dup 1)))]
65: ""
66: "operands[1] = force_reg (DFmode, CONST0_RTX (DFmode));")
67:
68: (define_insn "tstsf"
69: [(set (cc0)
70: (match_operand:SF 0 "register_operand" "d"))]
71: ""
72: "* return set_cmp (operands[0], CONST0_RTX (SFmode), 's');")
73:
74: (define_insn "cmpsi"
75: [(set (cc0)
76: (compare (match_operand:SI 0 "register_operand" "d,a,i,r")
77: (match_operand:SI 1 "nonmemory_operand" "d,a,r,i")))]
78: ""
79: "* return set_cmp (operands[0], operands[1], 'w');")
80:
81: (define_insn "cmphi"
82: [(set (cc0)
83: (compare (match_operand:HI 0 "register_operand" "d,a,r,i")
84: (match_operand:HI 1 "nonmemory_operand" "d,a,i,r")))]
85: ""
86: "* return set_cmp (operands[0], operands[1], 'h');")
87:
88: (define_insn "cmpqi"
89: [(set (cc0)
90: (compare (match_operand:QI 0 "register_operand" "d")
91: (match_operand:QI 1 "register_operand" "d")))]
92: ""
93: "* return set_cmp (operands[0], operands[1], 'b');")
94:
95: (define_insn "cmpdi"
96: [(set (cc0)
97: (compare (match_operand:DI 0 "register_operand" "d")
98: (match_operand:DI 1 "register_operand" "d")))]
99: ""
100: "* return set_cmp (operands[0], operands[1], 'l');")
101:
102: (define_insn "cmpdf"
103: [(set (cc0)
104: (compare (match_operand:DF 0 "register_operand" "d")
105: (match_operand:DF 1 "register_operand" "d")))]
106: ""
107: "* return set_cmp (operands[0], operands[1], 'd');")
108:
109: (define_insn "cmpsf"
110: [(set (cc0)
111: (compare (match_operand:SF 0 "nonmemory_operand" "dF,d")
112: (match_operand:SF 1 "nonmemory_operand" "d,F")))]
113: ""
114: "* return set_cmp (operands[0], operands[1], 's');")
115:
116: ;; Moves
117:
118: ;(define_insn "movtf"
119: ; [(set (match_operand:TF 0 "general_operand" "=g,d")
120: ; (match_operand:TF 1 "general_operand" "d,g"))]
121: ; ""
122: ; "*
123: ;{
124: ; rtx opaddr = 0;
125: ; rtx xoperands[4];
126: ; xoperands[0] = operands[0];
127: ; xoperands[2] = operands[1];
128: ;
129: ; if (REG_P (operands[0]))
130: ; xoperands[1] = gen_rtx (REG, TFmode, REGNO (operands[0]) + 1);
131: ; else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
132: ; xoperands[1] = 0;
133: ; else if (offsettable_memref_p (operands[0]))
134: ; xoperands[1] = adj_offsettable_operand (operands[0], 8);
135: ; else
136: ; {
137: ; opaddr = XEXP (operands[0], 0);
138: ; xoperands[0] = gen_rtx (MEM, TFmode, gen_rtx (REG, SImode, 13));
139: ; xoperands[1] = adj_offsettable_operand (xoperands[0], 8);
140: ; }
141: ;
142: ; if (REG_P (operands[1]))
143: ; xoperands[3] = gen_rtx (REG, TFmode, REGNO (operands[1]) + 1);
144: ; else if (offsettable_memref_p (operands[1]))
145: ; xoperands[3] = adj_offsettable_operand (operands[1], 8);
146: ; else
147: ; {
148: ; opaddr = XEXP (operands[1], 0);
149: ; xoperands[2] = gen_rtx (MEM, TFmode, gen_rtx (REG, SImode, 13));
150: ; xoperands[3] = adj_offsettable_operand (xoperands[2], 8);
151: ; }
152: ;
153: ; if (opaddr)
154: ; output_asm_insn (\"psh.w a5\;ld.w %0,a5\", &opaddr);
155: ; if (push_operand (operands[0], TFmode))
156: ; output_asm_insn (\"psh.l %3\;psh.l %2\", xoperands);
157: ; else if (GET_CODE (operands[0]) == MEM)
158: ; output_asm_insn (\"st.l %2,%0\;st.l %3,%1\", xoperands);
159: ; else if (GET_CODE (operands[1]) == REG)
160: ; output_asm_insn (\"mov %2,%0\;mov %3,%1\", xoperands);
161: ; else
162: ; output_asm_insn (\"ld.l %2,%0\;ld.l %3,%1\", xoperands);
163: ; if (opaddr)
164: ; output_asm_insn (\"pop.w a5\");
165: ; return \"\";
166: ;}")
167:
168: (define_insn "movdf"
169: [(set (match_operand:DF 0 "general_operand" "=g,d")
170: (match_operand:DF 1 "general_operand" "d,dmG"))]
171: ""
172: "*
173: {
174: if (push_operand (operands[0], DFmode))
175: return \"psh.l %1\";
176: else if (GET_CODE (operands[0]) == MEM)
177: return \"st.l %1,%0\";
178: else if (GET_CODE (operands[1]) == REG)
179: return \"mov %1,%0\";
180: else if (GET_CODE (operands[1]) == CONST_DOUBLE && LD_D_P (operands[1]))
181: {
182: operands[1] = gen_rtx (CONST_INT, VOIDmode,
183: const_double_high_int (operands[1]));
184: return \"ld.d %1,%0\";
185: }
186: else if (GET_CODE (operands[1]) == CONST_DOUBLE && LD_L_P (operands[1]))
187: {
188: operands[1] = gen_rtx (CONST_INT, VOIDmode,
189: const_double_low_int (operands[1]));
190: return \"ld.l %1,%0\";
191: }
192: else
193: return \"ld.l %1,%0\";
194: }")
195:
196: (define_insn "movsf"
197: [(set (match_operand:SF 0 "general_operand" "=g,d")
198: (match_operand:SF 1 "general_operand" "d,gF"))]
199: ""
200: "*
201: {
202: if (push_operand (operands[0], SFmode))
203: return \"psh.w %1\";
204: else if (GET_CODE (operands[0]) == MEM)
205: return \"st.s %1,%0\";
206: else if (GET_CODE (operands[1]) == REG)
207: return \"mov.s %1,%0\";
208: else
209: return \"ld.s %1,%0\";
210: }")
211:
212: (define_insn "movdi"
213: [(set (match_operand:DI 0 "general_operand" "=g,d")
214: (match_operand:DI 1 "general_operand" "d,dmiG"))]
215: ""
216: "*
217: {
218: if (push_operand (operands[0], DImode))
219: return \"psh.l %1\";
220: else if (GET_CODE (operands[0]) == MEM)
221: return \"st.l %1,%0\";
222: else if (GET_CODE (operands[1]) == REG)
223: return \"mov %1,%0\";
224: else if (GET_CODE (operands[1]) == CONST_DOUBLE && LD_D_P (operands[1]))
225: {
226: operands[1] = gen_rtx (CONST_INT, VOIDmode,
227: const_double_high_int (operands[1]));
228: return \"ld.d %1,%0\";
229: }
230: else
231: return \"ld.l %1,%0\";
232: }")
233:
234: ;; Special case of movsi, needed to express A-reg preference.
235:
236: (define_insn ""
237: [(set (match_operand:SI 0 "push_operand" "=<")
238: (plus:SI (match_operand:SI 1 "register_operand" "a")
239: (match_operand:SI 2 "immediate_operand" "i")))]
240: "operands[1] != stack_pointer_rtx"
241: "pshea %a2(%1)")
242:
243: ;; General movsi. Constraints will be selected based on TARGET_INDIRECTS
244: ;; to avoid indirect addressing on C3, where it is slow.
245:
246: (define_expand "movsi"
247: [(set (match_operand:SI 0 "general_operand" "")
248: (match_operand:SI 1 "general_operand" ""))]
249: ""
250: "")
251:
252: (define_insn ""
1.1.1.2 ! root 253: [(set (match_operand:SI 0 "push_operand" "=<,<")
! 254: (match_operand:SI 1 "general_operand" "Ad,io"))]
! 255: ""
! 256: "@
! 257: psh.w %1
! 258: pshea %a1")
! 259:
! 260: (define_insn ""
1.1 root 261: [(set (match_operand:SI 0 "general_operand" "=g,r,<")
262: (match_operand:SI 1 "general_operand" "r,g,io"))]
263: "TARGET_INDIRECTS"
264: "*
265: {
266: if (push_operand (operands[0], SImode))
267: {
268: if (GET_CODE (operands[1]) == REG)
269: return \"psh.w %1\";
270: else
271: return \"pshea %a1\";
272: }
273: if (GET_CODE (operands[0]) == MEM)
274: return \"st.w %1,%0\";
275: if (GET_CODE (operands[1]) != REG)
276: return \"ld.w %1,%0\";
277: if (S_REG_P (operands[0]) && S_REG_P (operands[1]))
278: return \"mov.w %1,%0\";
279: return \"mov %1,%0\";
280: }")
281:
282: (define_insn ""
283: [(set (match_operand:SI 0 "general_operand" "=g,r,<")
284: (match_operand:SI 1 "general_operand" "r,g,i"))]
285: "! TARGET_INDIRECTS"
286: "*
287: {
288: if (push_operand (operands[0], SImode))
289: {
290: if (GET_CODE (operands[1]) == REG)
291: return \"psh.w %1\";
292: else
293: return \"pshea %a1\";
294: }
295: if (GET_CODE (operands[0]) == MEM)
296: return \"st.w %1,%0\";
297: if (GET_CODE (operands[1]) != REG)
298: return \"ld.w %1,%0\";
299: if (S_REG_P (operands[0]) && S_REG_P (operands[1]))
300: return \"mov.w %1,%0\";
301: return \"mov %1,%0\";
302: }")
303:
304: (define_insn "movstrictsi"
1.1.1.2 ! root 305: [(set (strict_low_part (match_operand:SI 0 "general_operand" "+g,r"))
1.1 root 306: (match_operand:SI 1 "general_operand" "r,g"))]
307: ""
308: "*
309: {
310: if (GET_CODE (operands[0]) == MEM)
311: return \"st.w %1,%0\";
312: if (GET_CODE (operands[1]) != REG)
313: return \"ld.w %1,%0\";
314: if (S_REG_P (operands[0]) && S_REG_P (operands[1]))
315: return \"mov.w %1,%0\";
316: return \"mov %1,%0\";
317: }")
318:
319: (define_insn "movhi"
320: [(set (match_operand:HI 0 "general_operand" "=g,r")
321: (match_operand:HI 1 "general_operand" "r,g"))]
322: ""
323: "*
324: {
325: if (push_operand (operands[0], HImode))
326: abort ();
327: else if (GET_CODE (operands[0]) == MEM)
328: return \"st.h %1,%0\";
329: else if (GET_CODE (operands[1]) == REG)
330: {
331: if (S_REG_P (operands[0]) && S_REG_P (operands[1]))
332: return \"mov.w %1,%0\";
333: else
334: return \"mov %1,%0\";
335: }
336: else if (GET_CODE (operands[1]) == CONST_INT)
337: return \"ld.w %1,%0\";
338: else
339: return \"ld.h %1,%0\";
340: }")
341:
342: (define_insn "movqi"
343: [(set (match_operand:QI 0 "general_operand" "=g,r")
344: (match_operand:QI 1 "general_operand" "r,g"))]
345: ""
346: "*
347: {
348: if (push_operand (operands[0], QImode))
349: abort ();
350: else if (GET_CODE (operands[0]) == MEM)
351: return \"st.b %1,%0\";
352: else if (GET_CODE (operands[1]) == REG)
353: {
354: if (S_REG_P (operands[0]) && S_REG_P (operands[1]))
355: return \"mov.w %1,%0\";
356: else
357: return \"mov %1,%0\";
358: }
359: else if (GET_CODE (operands[1]) == CONST_INT)
360: return \"ld.w %1,%0\";
361: else
362: return \"ld.b %1,%0\";
363: }")
364:
365: ;; Extension and truncation insns.
366: ;; Those for integer source operand
367: ;; are ordered widest source type first.
368:
369: (define_insn "truncsiqi2"
370: [(set (match_operand:QI 0 "register_operand" "=d,a")
371: (truncate:QI (match_operand:SI 1 "register_operand" "d,a")))]
372: ""
373: "cvtw.b %1,%0")
374:
375: (define_insn "truncsihi2"
376: [(set (match_operand:HI 0 "register_operand" "=d,a")
377: (truncate:HI (match_operand:SI 1 "register_operand" "d,a")))]
378: ""
379: "cvtw.h %1,%0")
380:
381: (define_insn "trunchiqi2"
382: [(set (match_operand:QI 0 "register_operand" "=r")
383: (truncate:QI (match_operand:HI 1 "register_operand" "0")))]
384: ""
385: "")
386:
387: (define_insn "truncdisi2"
388: [(set (match_operand:SI 0 "register_operand" "=d")
389: (truncate:SI (match_operand:DI 1 "register_operand" "d")))]
390: ""
391: "cvtl.w %1,%0")
392:
393: (define_insn "extendsidi2"
394: [(set (match_operand:DI 0 "register_operand" "=d")
395: (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))]
396: ""
397: "cvtw.l %1,%0")
398:
399: (define_insn "extendhisi2"
400: [(set (match_operand:SI 0 "register_operand" "=d,a")
401: (sign_extend:SI (match_operand:HI 1 "register_operand" "d,a")))]
402: ""
403: "cvth.w %1,%0")
404:
405: (define_insn "extendqihi2"
406: [(set (match_operand:HI 0 "register_operand" "=d,a")
407: (sign_extend:HI (match_operand:QI 1 "register_operand" "d,a")))]
408: ""
409: "cvtb.w %1,%0")
410:
411: (define_insn "extendqisi2"
412: [(set (match_operand:SI 0 "register_operand" "=d,a")
413: (sign_extend:SI (match_operand:QI 1 "register_operand" "d,a")))]
414: ""
415: "cvtb.w %1,%0")
416:
417: (define_insn "extendsfdf2"
418: [(set (match_operand:DF 0 "register_operand" "=d")
419: (float_extend:DF (match_operand:SF 1 "register_operand" "d")))]
420: ""
421: "cvts.d %1,%0")
422:
423: (define_insn "truncdfsf2"
424: [(set (match_operand:SF 0 "register_operand" "=d")
425: (float_truncate:SF (match_operand:DF 1 "register_operand" "d")))]
426: ""
427: "cvtd.s %1,%0")
428:
429: (define_insn "zero_extendhisi2"
430: [(set (match_operand:SI 0 "register_operand" "=r")
431: (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
432: ""
433: "and #0xffff,%0")
434:
435: (define_insn "zero_extendqihi2"
436: [(set (match_operand:HI 0 "register_operand" "=r")
437: (zero_extend:HI (match_operand:QI 1 "register_operand" "0")))]
438: ""
439: "and #0xff,%0")
440:
441: (define_insn "zero_extendqisi2"
442: [(set (match_operand:SI 0 "register_operand" "=r")
443: (zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]
444: ""
445: "and #0xff,%0")
446:
447: (define_insn "zero_extendsidi2"
448: [(set (match_operand:DI 0 "register_operand" "=d")
449: (zero_extend:DI (match_operand:SI 1 "register_operand" "0")))]
450: ""
451: "ld.u #0,%0")
452:
453: ;; Fix-to-float conversion insns.
454: ;; Note that the ones that start with SImode come first.
455: ;; That is so that an operand that is a CONST_INT
456: ;; (and therefore lacks a specific machine mode).
457: ;; will be recognized as SImode (which is always valid)
458: ;; rather than as QImode or HImode.
459:
460: (define_insn "floatsisf2"
461: [(set (match_operand:SF 0 "register_operand" "=d")
462: (float:SF (match_operand:SI 1 "register_operand" "d")))]
463: ""
464: "cvtw.s %1,%0")
465:
466: (define_insn "floatdisf2"
467: [(set (match_operand:SF 0 "register_operand" "=d")
468: (float:SF (match_operand:DI 1 "register_operand" "d")))]
469: ""
470: "cvtl.s %1,%0")
471:
472: (define_insn "floatsidf2"
473: [(set (match_operand:DF 0 "register_operand" "=d")
474: (float:DF (match_operand:SI 1 "register_operand" "d")))]
475: "TARGET_C2"
476: "cvtw.d %1,%0")
477:
478: (define_insn "floatdidf2"
479: [(set (match_operand:DF 0 "register_operand" "=d")
480: (float:DF (match_operand:DI 1 "register_operand" "d")))]
481: ""
482: "cvtl.d %1,%0")
483:
484: ;; Float-to-fix conversion insns.
485:
486: (define_insn "fix_truncsfsi2"
487: [(set (match_operand:SI 0 "register_operand" "=d")
488: (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "d"))))]
489: ""
490: "cvts.w %1,%0")
491:
492: (define_insn "fix_truncsfdi2"
493: [(set (match_operand:DI 0 "register_operand" "=d")
494: (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "d"))))]
495: ""
496: "cvts.l %1,%0")
497:
498: (define_insn "fix_truncdfsi2"
499: [(set (match_operand:SI 0 "register_operand" "=d")
500: (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
501: ""
502: "*
503: {
504: if (TARGET_C2)
505: return \"cvtd.w %1,%0\";
506: return \"cvtd.l %1,%0\";
507: }")
508:
509: (define_insn "fix_truncdfdi2"
510: [(set (match_operand:DI 0 "register_operand" "=d")
511: (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
512: ""
513: "cvtd.l %1,%0")
514:
515: ;;- All kinds of add instructions.
516:
517: (define_insn "adddf3"
518: [(set (match_operand:DF 0 "register_operand" "=d")
519: (plus:DF (match_operand:DF 1 "register_operand" "%0")
520: (match_operand:DF 2 "register_operand" "d")))]
521: ""
522: "add.d %2,%0")
523:
524: (define_insn "addsf3"
525: [(set (match_operand:SF 0 "register_operand" "=d")
526: (plus:SF (match_operand:SF 1 "register_operand" "%0")
527: (match_operand:SF 2 "nonmemory_operand" "dF")))]
528: ""
529: "add.s %2,%0")
530:
531: (define_insn "adddi3"
532: [(set (match_operand:DI 0 "register_operand" "=d")
533: (plus:DI (match_operand:DI 1 "register_operand" "%0")
534: (match_operand:DI 2 "register_operand" "d")))]
535: ""
536: "add.l %2,%0")
537:
538: ;; special case of addsi3, needed to specify an A reg for the destination
539: ;; when the source is a sum involving FP or AP.
540:
541: (define_insn ""
542: [(set (match_operand:SI 0 "register_operand" "=a")
543: (plus:SI (match_operand:SI 1 "register_operand" "%a")
544: (match_operand:SI 2 "immediate_operand" "i")))]
545: "operands[1] == frame_pointer_rtx || operands[1] == arg_pointer_rtx"
546: "ldea %a2(%1),%0")
547:
548: (define_insn "addsi3"
549: [(set (match_operand:SI 0 "register_operand" "=d,a,a")
550: (plus:SI (match_operand:SI 1 "nonmemory_operand" "%0,0,a")
551: (match_operand:SI 2 "nonmemory_operand" "di,ri,i")))]
552: ""
553: "* switch (which_alternative)
554: {
555: case 0:
556: case 1:
557: return \"add.w %2,%0\";
558: case 2:
559: if ((TARGET_C2 || A_REG_P (operands[0]))
560: && operands[1] != stack_pointer_rtx)
561: return \"ldea %a2(%1),%0\";
562: else
563: return \"mov %1,%0\;add.w %2,%0\";
564: }")
565:
566: (define_insn "addhi3"
567: [(set (match_operand:HI 0 "register_operand" "=d,a")
568: (plus:HI (match_operand:HI 1 "register_operand" "%0,0")
569: (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
570: ""
571: "add.h %2,%0")
572:
573: (define_insn "addqi3"
574: [(set (match_operand:QI 0 "register_operand" "=d")
575: (plus:QI (match_operand:QI 1 "register_operand" "%0")
576: (match_operand:QI 2 "register_operand" "d")))]
577: ""
578: "add.b %2,%0")
579:
580: ;;- All kinds of subtract instructions.
581:
582: (define_insn "subdf3"
583: [(set (match_operand:DF 0 "register_operand" "=d")
584: (minus:DF (match_operand:DF 1 "register_operand" "0")
585: (match_operand:DF 2 "register_operand" "d")))]
586: ""
587: "sub.d %2,%0")
588:
589: (define_insn "subsf3"
590: [(set (match_operand:SF 0 "register_operand" "=d")
591: (minus:SF (match_operand:SF 1 "register_operand" "0")
592: (match_operand:SF 2 "nonmemory_operand" "dF")))]
593: ""
594: "sub.s %2,%0")
595:
596: (define_insn "subdi3"
597: [(set (match_operand:DI 0 "register_operand" "=d")
598: (minus:DI (match_operand:DI 1 "register_operand" "0")
599: (match_operand:DI 2 "register_operand" "d")))]
600: ""
601: "sub.l %2,%0")
602:
603: (define_insn "subsi3"
604: [(set (match_operand:SI 0 "register_operand" "=d,a")
605: (minus:SI (match_operand:SI 1 "register_operand" "0,0")
606: (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
607: ""
608: "sub.w %2,%0")
609:
610: (define_insn "subhi3"
611: [(set (match_operand:HI 0 "register_operand" "=d,a")
612: (minus:HI (match_operand:HI 1 "register_operand" "0,0")
613: (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
614: ""
615: "sub.h %2,%0")
616:
617: (define_insn "subqi3"
618: [(set (match_operand:QI 0 "register_operand" "=d")
619: (minus:QI (match_operand:QI 1 "register_operand" "0")
620: (match_operand:QI 2 "register_operand" "d")))]
621: ""
622: "sub.b %2,%0")
623:
624: ;;- Multiply instructions.
625:
626: (define_insn "muldf3"
627: [(set (match_operand:DF 0 "register_operand" "=d")
628: (mult:DF (match_operand:DF 1 "register_operand" "%0")
629: (match_operand:DF 2 "register_operand" "d")))]
630: ""
631: "mul.d %2,%0")
632:
633: (define_insn "mulsf3"
634: [(set (match_operand:SF 0 "register_operand" "=d")
635: (mult:SF (match_operand:SF 1 "register_operand" "%0")
636: (match_operand:SF 2 "nonmemory_operand" "dF")))]
637: ""
638: "mul.s %2,%0")
639:
640: (define_insn "muldi3"
641: [(set (match_operand:DI 0 "register_operand" "=d")
642: (mult:DI (match_operand:DI 1 "register_operand" "%0")
643: (match_operand:DI 2 "register_operand" "d")))]
644: ""
645: "mul.l %2,%0")
646:
647: (define_insn "mulsi3"
648: [(set (match_operand:SI 0 "register_operand" "=d,a")
649: (mult:SI (match_operand:SI 1 "register_operand" "%0,0")
650: (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
651: ""
652: "mul.w %2,%0")
653:
654: (define_insn "mulhi3"
655: [(set (match_operand:HI 0 "register_operand" "=d,a")
656: (mult:HI (match_operand:HI 1 "register_operand" "%0,0")
657: (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
658: ""
659: "mul.h %2,%0")
660:
661: (define_insn "mulqi3"
662: [(set (match_operand:QI 0 "register_operand" "=d")
663: (mult:QI (match_operand:QI 1 "register_operand" "%0")
664: (match_operand:QI 2 "register_operand" "d")))]
665: ""
666: "mul.b %2,%0")
667:
668: ;;- Divide instructions.
669:
670: (define_insn "divdf3"
671: [(set (match_operand:DF 0 "register_operand" "=d")
672: (div:DF (match_operand:DF 1 "register_operand" "0")
673: (match_operand:DF 2 "register_operand" "d")))]
674: ""
675: "div.d %2,%0")
676:
677: (define_insn "divsf3"
678: [(set (match_operand:SF 0 "register_operand" "=d")
679: (div:SF (match_operand:SF 1 "register_operand" "0")
680: (match_operand:SF 2 "nonmemory_operand" "dF")))]
681: ""
682: "div.s %2,%0")
683:
684: (define_insn "divdi3"
685: [(set (match_operand:DI 0 "register_operand" "=d")
686: (div:DI (match_operand:DI 1 "register_operand" "0")
687: (match_operand:DI 2 "register_operand" "d")))]
688: ""
689: "div.l %2,%0")
690:
691: (define_insn "udivdi3"
692: [(set (match_operand:DI 0 "register_operand" "=d")
693: (udiv:DI (match_operand:DI 1 "register_operand" "d")
694: (match_operand:DI 2 "register_operand" "d")))]
695: ""
696: "psh.l %2\;psh.l %1\;callq udiv64\;pop.l %0\;add.w #8,sp")
697:
698: (define_insn "divsi3"
699: [(set (match_operand:SI 0 "register_operand" "=d,a")
700: (div:SI (match_operand:SI 1 "register_operand" "0,0")
701: (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
702: ""
703: "div.w %2,%0")
704:
705: (define_insn "divhi3"
706: [(set (match_operand:HI 0 "register_operand" "=d,a")
707: (div:HI (match_operand:HI 1 "register_operand" "0,0")
708: (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
709: ""
710: "div.h %2,%0")
711:
712: (define_insn "divqi3"
713: [(set (match_operand:QI 0 "register_operand" "=d")
714: (div:QI (match_operand:QI 1 "register_operand" "0")
715: (match_operand:QI 2 "register_operand" "d")))]
716: ""
717: "div.b %2,%0")
718:
719: ;; - and, or, xor
720:
721: (define_insn ""
722: [(set (match_operand:DI 0 "register_operand" "=d")
723: (and:DI (match_operand:DI 1 "register_operand" "%0")
724: (match_operand:DI 2 "immediate_operand" "Fn")))]
1.1.1.2 ! root 725: "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
1.1 root 726: || (GET_CODE (operands[2]) == CONST_DOUBLE
727: && CONST_DOUBLE_HIGH (operands[2]) == -1)"
728: "and %2,%0")
729:
730: (define_insn "anddi3"
731: [(set (match_operand:DI 0 "register_operand" "=d")
732: (and:DI (match_operand:DI 1 "register_operand" "%0")
733: (match_operand:DI 2 "register_operand" "d")))]
734: ""
735: "and %2,%0")
736:
737: (define_insn "andsi3"
738: [(set (match_operand:SI 0 "register_operand" "=d,a")
739: (and:SI (match_operand:SI 1 "register_operand" "%0,0")
740: (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
741: ""
742: "and %2,%0")
743:
744: (define_insn "andhi3"
745: [(set (match_operand:HI 0 "register_operand" "=d,a")
746: (and:HI (match_operand:HI 1 "register_operand" "%0,0")
747: (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
748: ""
749: "and %2,%0")
750:
751: (define_insn "andqi3"
752: [(set (match_operand:QI 0 "register_operand" "=d,a")
753: (and:QI (match_operand:QI 1 "register_operand" "%0,0")
754: (match_operand:QI 2 "nonmemory_operand" "di,ai")))]
755: ""
756: "and %2,%0")
757:
758: ;;- Bit set instructions.
759:
760: (define_insn ""
761: [(set (match_operand:DI 0 "register_operand" "=d")
762: (ior:DI (match_operand:DI 1 "register_operand" "%0")
763: (match_operand:DI 2 "immediate_operand" "Fn")))]
1.1.1.2 ! root 764: "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0)
1.1 root 765: || (GET_CODE (operands[2]) == CONST_DOUBLE
766: && CONST_DOUBLE_HIGH (operands[2]) == 0)"
767: "or %2,%0")
768:
769: (define_insn "iordi3"
770: [(set (match_operand:DI 0 "register_operand" "=d")
771: (ior:DI (match_operand:DI 1 "register_operand" "%0")
772: (match_operand:DI 2 "register_operand" "d")))]
773: ""
774: "or %2,%0")
775:
776: (define_insn "iorsi3"
777: [(set (match_operand:SI 0 "register_operand" "=d,a")
778: (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
779: (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
780: ""
781: "or %2,%0")
782:
783: (define_insn "iorhi3"
784: [(set (match_operand:HI 0 "register_operand" "=d,a")
785: (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
786: (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
787: ""
788: "or %2,%0")
789:
790: (define_insn "iorqi3"
791: [(set (match_operand:QI 0 "register_operand" "=d,a")
792: (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
793: (match_operand:QI 2 "nonmemory_operand" "di,ai")))]
794: ""
795: "or %2,%0")
796:
797: ;;- xor instructions.
798:
799: (define_insn ""
800: [(set (match_operand:DI 0 "register_operand" "=d")
801: (xor:DI (match_operand:DI 1 "register_operand" "%0")
802: (match_operand:DI 2 "immediate_operand" "Fn")))]
1.1.1.2 ! root 803: "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0)
1.1 root 804: || (GET_CODE (operands[2]) == CONST_DOUBLE
805: && CONST_DOUBLE_HIGH (operands[2]) == 0)"
806: "xor %2,%0")
807:
808: (define_insn "xordi3"
809: [(set (match_operand:DI 0 "register_operand" "=d")
810: (xor:DI (match_operand:DI 1 "register_operand" "%0")
811: (match_operand:DI 2 "register_operand" "d")))]
812: ""
813: "xor %2,%0")
814:
815: (define_insn "xorsi3"
816: [(set (match_operand:SI 0 "register_operand" "=d,a")
817: (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
818: (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
819: ""
820: "xor %2,%0")
821:
822: (define_insn "xorhi3"
823: [(set (match_operand:HI 0 "register_operand" "=d,a")
824: (xor:HI (match_operand:HI 1 "register_operand" "%0,0")
825: (match_operand:HI 2 "nonmemory_operand" "di,ai")))]
826: ""
827: "xor %2,%0")
828:
829: (define_insn "xorqi3"
830: [(set (match_operand:QI 0 "register_operand" "=d,a")
831: (xor:QI (match_operand:QI 1 "register_operand" "%0,0")
832: (match_operand:QI 2 "nonmemory_operand" "di,ai")))]
833: ""
834: "xor %2,%0")
835:
836: (define_insn "negdf2"
837: [(set (match_operand:DF 0 "register_operand" "=d")
838: (neg:DF (match_operand:DF 1 "register_operand" "d")))]
839: ""
840: "neg.d %1,%0")
841:
842: (define_insn "negsf2"
843: [(set (match_operand:SF 0 "register_operand" "=d")
844: (neg:SF (match_operand:SF 1 "register_operand" "d")))]
845: ""
846: "neg.s %1,%0")
847:
848: (define_insn "negdi2"
849: [(set (match_operand:DI 0 "register_operand" "=d")
850: (neg:DI (match_operand:DI 1 "register_operand" "d")))]
851: ""
852: "neg.l %1,%0")
853:
854: (define_insn "negsi2"
855: [(set (match_operand:SI 0 "register_operand" "=d,a")
856: (neg:SI (match_operand:SI 1 "register_operand" "d,a")))]
857: ""
858: "neg.w %1,%0")
859:
860: (define_insn "neghi2"
861: [(set (match_operand:HI 0 "register_operand" "=d,a")
862: (neg:HI (match_operand:HI 1 "register_operand" "d,a")))]
863: ""
864: "neg.h %1,%0")
865:
866: (define_insn "negqi2"
867: [(set (match_operand:QI 0 "register_operand" "=d")
868: (neg:QI (match_operand:QI 1 "register_operand" "d")))]
869: ""
870: "neg.b %1,%0")
871:
872: (define_insn "one_cmpldi2"
873: [(set (match_operand:DI 0 "register_operand" "=d")
874: (not:DI (match_operand:DI 1 "register_operand" "d")))]
875: ""
876: "not %1,%0")
877:
878: (define_insn "one_cmplsi2"
879: [(set (match_operand:SI 0 "register_operand" "=d,a")
880: (not:SI (match_operand:SI 1 "register_operand" "d,a")))]
881: ""
882: "not %1,%0")
883:
884: (define_insn "one_cmplhi2"
885: [(set (match_operand:HI 0 "register_operand" "=d,a")
886: (not:HI (match_operand:HI 1 "register_operand" "d,a")))]
887: ""
888: "not %1,%0")
889:
890: (define_insn "one_cmplqi2"
891: [(set (match_operand:QI 0 "register_operand" "=d,a")
892: (not:QI (match_operand:QI 1 "register_operand" "d,a")))]
893: ""
894: "not %1,%0")
895:
896: ;;- shifts
897: ;;
898: ;; Convex shift instructions are logical shifts.
899: ;; To make signed right shifts:
900: ;; for SImode, sign extend to DImode and shift, works for 0..32
901: ;; for DImode, shift and then extend the sign, works for 0..63 -- but not 64
902:
903: (define_insn "lshlsi3"
904: [(set (match_operand:SI 0 "register_operand" "=d,a")
905: (lshift:SI (match_operand:SI 1 "register_operand" "0,0")
906: (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
907: ""
908: "*
909: {
910: if (operands[2] == const1_rtx)
911: return \"add.w %0,%0\";
912: else if (TARGET_C2 && S_REG_P (operands[0]))
913: return \"shf.w %2,%0\";
914: else
915: return \"shf %2,%0\";
916: }")
917:
918: (define_insn "ashlsi3"
919: [(set (match_operand:SI 0 "register_operand" "=d,a")
920: (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
921: (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
922: ""
923: "*
924: {
925: if (operands[2] == const1_rtx)
926: return \"add.w %0,%0\";
927: else if (TARGET_C2 && S_REG_P (operands[0]))
928: return \"shf.w %2,%0\";
929: else
930: return \"shf %2,%0\";
931: }")
932:
933: (define_expand "lshrsi3"
934: [(set (match_operand:SI 0 "register_operand" "")
935: (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
936: (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))]
937: ""
938: "operands[2] = negate_rtx (SImode, operands[2]);")
939:
940: (define_insn ""
941: [(set
942: (match_operand:SI 0 "register_operand" "=d,a")
943: (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
944: (neg:SI (match_operand:SI 2 "nonmemory_operand" "di,ai"))))]
945: ""
946: "*
947: {
948: if (A_REG_P (operands[0]))
949: return \"shf %2,%0\";
950: else if (TARGET_C2)
951: return \"shf.w %2,%0\";
952: else
953: return \"ld.u #0,%0\;shf %2,%0\";
954: }")
955:
956: (define_insn ""
957: [(set
958: (match_operand:SI 0 "register_operand" "=r")
959: (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
960: (match_operand:SI 2 "immediate_operand" "i")))]
961: ""
962: "*
963: {
964: if (A_REG_P (operands[0]))
965: return \"shf #%n2,%0\";
966: else if (TARGET_C2)
967: return \"shf.w #%n2,%0\";
968: else
969: return \"ld.u #0,%0\;shf #%n2,%0\";
970: }")
971:
972: (define_expand "ashrsi3"
973: [(set (match_operand:SI 0 "register_operand" "=d")
974: (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
975: (neg:SI (match_operand:SI 2 "nonmemory_operand" "di"))))]
976: ""
977: "operands[2] = negate_rtx (SImode, operands[2]);")
978:
979: (define_insn ""
980: [(set (match_operand:SI 0 "register_operand" "=&d")
981: (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
982: (neg:SI (match_operand:SI 2 "nonmemory_operand" "di"))))]
983: ""
984: "cvtw.l %1,%0\;shf %2,%0")
985:
986: (define_insn ""
987: [(set (match_operand:SI 0 "register_operand" "=&d")
988: (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
989: (match_operand:SI 2 "immediate_operand" "i")))]
990: ""
991: "cvtw.l %1,%0\;shf #%n2,%0")
992:
993: (define_insn "lshldi3"
994: [(set (match_operand:DI 0 "register_operand" "=d")
995: (lshift:DI (match_operand:DI 1 "register_operand" "0")
996: (match_operand:SI 2 "nonmemory_operand" "di")))]
997: ""
998: "shf %2,%0")
999:
1000: (define_insn "ashldi3"
1001: [(set (match_operand:DI 0 "register_operand" "=d")
1002: (ashift:DI (match_operand:DI 1 "register_operand" "0")
1003: (match_operand:SI 2 "nonmemory_operand" "di")))]
1004: ""
1005: "shf %2,%0")
1006:
1007: (define_expand "lshrdi3"
1008: [(set (match_operand:DI 0 "register_operand" "=d")
1009: (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
1010: (neg:SI (match_operand:SI 2 "nonmemory_operand" "di"))))]
1011: ""
1012: "operands[2] = negate_rtx (SImode, operands[2]);")
1013:
1014: (define_insn ""
1015: [(set (match_operand:DI 0 "register_operand" "=d")
1016: (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
1017: (neg:SI (match_operand:SI 2 "nonmemory_operand" "di"))))]
1018: ""
1019: "shf %2,%0")
1020:
1021: (define_insn ""
1022: [(set (match_operand:DI 0 "register_operand" "=d")
1023: (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
1024: (match_operand:SI 2 "immediate_operand" "i")))]
1025: ""
1026: "shf #%n2,%0")
1027:
1028: ;; signed a >> b is
1029: ;; ((a >> b) ^ signbit) - signbit
1030: ;; where signbit is (1 << 63) >> b
1031:
1032: (define_expand "ashrdi3"
1033: [(match_operand:DI 0 "register_operand" "")
1034: (match_operand:DI 1 "register_operand" "")
1035: (match_operand:SI 2 "nonmemory_operand" "")
1036: (match_dup 3)]
1037: ""
1038: "
1039: {
1040: if (GET_CODE (operands[2]) == CONST_INT)
1041: {
1042: int rshift = INTVAL (operands[2]);
1.1.1.2 ! root 1043: if (rshift < 0)
! 1044: operands[3] = force_reg (DImode, immed_double_const (0, 0, DImode));
! 1045: else if (rshift < 32)
! 1046: operands[3] =
! 1047: force_reg (DImode,
! 1048: immed_double_const (0, 1 << (31 - rshift), DImode));
! 1049: else if (rshift < 64)
! 1050: operands[3] =
! 1051: force_reg (DImode,
! 1052: immed_double_const (1 << (63 - rshift), 0, DImode));
! 1053: else
! 1054: operands[3] = force_reg (DImode, immed_double_const (0, 0, DImode));
1.1 root 1055: }
1056: else
1057: {
1058: operands[3] =
1059: force_reg (DImode, immed_double_const (0, 1 << 31, DImode));
1060: emit_insn (gen_lshrdi3 (operands[3], operands[3], operands[2]));
1061: }
1062:
1063: emit_insn (gen_lshrdi3 (operands[0], operands[1], operands[2]));
1064: emit_insn (gen_rtx (SET, VOIDmode, operands[0],
1065: gen_rtx (XOR, DImode, operands[0], operands[3])));
1066: emit_insn (gen_rtx (SET, VOIDmode, operands[0],
1067: gen_rtx (MINUS, DImode, operands[0], operands[3])));
1068: DONE;
1069: }")
1070:
1071: ;; __builtin instructions
1072:
1073: (define_insn "sqrtdf2"
1074: [(set (match_operand:DF 0 "register_operand" "=d")
1075: (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
1076: "TARGET_C2"
1077: "sqrt.d %0")
1078:
1079: (define_insn "sqrtsf2"
1080: [(set (match_operand:SF 0 "register_operand" "=d")
1081: (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
1082: "TARGET_C2"
1083: "sqrt.s %0")
1084:
1085: ;(define_insn ""
1086: ; [(set (match_operand:SI 0 "register_operand" "=d")
1087: ; (minus:SI (ffs:SI (match_operand:SI 1 "register_operand" "d"))
1088: ; (const_int 1)))]
1089: ; ""
1090: ; "tzc %1,%0\;le.w #32,%0\;jbrs.f .+6\;ld.w #-1,%0")
1091: ;
1092: ;(define_expand "ffssi2"
1093: ; [(set (match_operand:SI 0 "register_operand" "=d")
1094: ; (minus:SI (ffs:SI (match_operand:SI 1 "register_operand" "d"))
1095: ; (const_int 1)))
1096: ; (set (match_dup 0)
1097: ; (plus:SI (match_dup 0)
1098: ; (const_int 1)))]
1099: ; ""
1100: ; "")
1101:
1102: (define_insn "abssf2"
1103: [(set (match_operand:SF 0 "register_operand" "=d")
1104: (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1105: ""
1106: "and #0x7fffffff,%0")
1107:
1108: (define_expand "absdf2"
1109: [(set (subreg:DI (match_operand:DF 0 "register_operand" "=d") 0)
1110: (and:DI (subreg:DI (match_operand:DF 1 "register_operand" "d") 0)
1111: (match_dup 2)))]
1112: ""
1113: "operands[2] = force_reg (DImode,
1114: immed_double_const (-1, 0x7fffffff, DImode));")
1115:
1116: ;; Jumps
1117:
1118: (define_insn "jump"
1119: [(set (pc)
1120: (label_ref (match_operand 0 "" "")))]
1121: ""
1122: "jbr %l0")
1123:
1124: (define_insn "beq"
1125: [(set (pc)
1126: (if_then_else (eq (cc0)
1127: (const_int 0))
1128: (label_ref (match_operand 0 "" ""))
1129: (pc)))]
1130: ""
1131: "* return gen_cmp (operands[0], \"eq\", 't'); ")
1132:
1133: (define_insn "bne"
1134: [(set (pc)
1135: (if_then_else (ne (cc0)
1136: (const_int 0))
1137: (label_ref (match_operand 0 "" ""))
1138: (pc)))]
1139: ""
1140: "* return gen_cmp (operands[0], \"eq\", 'f'); ")
1141:
1142: (define_insn "bgt"
1143: [(set (pc)
1144: (if_then_else (gt (cc0)
1145: (const_int 0))
1146: (label_ref (match_operand 0 "" ""))
1147: (pc)))]
1148: ""
1149: "* return gen_cmp (operands[0], \"le\", 'f'); ")
1150:
1151: (define_insn "bgtu"
1152: [(set (pc)
1153: (if_then_else (gtu (cc0)
1154: (const_int 0))
1155: (label_ref (match_operand 0 "" ""))
1156: (pc)))]
1157: ""
1158: "* return gen_cmp (operands[0], \"leu\", 'f'); ")
1159:
1160: (define_insn "blt"
1161: [(set (pc)
1162: (if_then_else (lt (cc0)
1163: (const_int 0))
1164: (label_ref (match_operand 0 "" ""))
1165: (pc)))]
1166: ""
1167: "* return gen_cmp (operands[0], \"lt\", 't'); ")
1168:
1169: (define_insn "bltu"
1170: [(set (pc)
1171: (if_then_else (ltu (cc0)
1172: (const_int 0))
1173: (label_ref (match_operand 0 "" ""))
1174: (pc)))]
1175: ""
1176: "* return gen_cmp (operands[0], \"ltu\", 't'); ")
1177:
1178: (define_insn "bge"
1179: [(set (pc)
1180: (if_then_else (ge (cc0)
1181: (const_int 0))
1182: (label_ref (match_operand 0 "" ""))
1183: (pc)))]
1184: ""
1185: "* return gen_cmp (operands[0], \"lt\", 'f'); ")
1186:
1187: (define_insn "bgeu"
1188: [(set (pc)
1189: (if_then_else (geu (cc0)
1190: (const_int 0))
1191: (label_ref (match_operand 0 "" ""))
1192: (pc)))]
1193: ""
1194: "* return gen_cmp (operands[0], \"ltu\", 'f'); ")
1195:
1196: (define_insn "ble"
1197: [(set (pc)
1198: (if_then_else (le (cc0)
1199: (const_int 0))
1200: (label_ref (match_operand 0 "" ""))
1201: (pc)))]
1202: ""
1203: "* return gen_cmp (operands[0], \"le\", 't'); ")
1204:
1205: (define_insn "bleu"
1206: [(set (pc)
1207: (if_then_else (leu (cc0)
1208: (const_int 0))
1209: (label_ref (match_operand 0 "" ""))
1210: (pc)))]
1211: ""
1212: "* return gen_cmp (operands[0], \"leu\", 't'); ")
1213:
1214: (define_insn ""
1215: [(set (pc)
1216: (if_then_else (eq (cc0)
1217: (const_int 0))
1218: (pc)
1219: (label_ref (match_operand 0 "" ""))))]
1220: ""
1221: "* return gen_cmp (operands[0], \"eq\", 'f'); ")
1222:
1223: (define_insn ""
1224: [(set (pc)
1225: (if_then_else (ne (cc0)
1226: (const_int 0))
1227: (pc)
1228: (label_ref (match_operand 0 "" ""))))]
1229: ""
1230: "* return gen_cmp (operands[0], \"eq\", 't'); ")
1231:
1232: (define_insn ""
1233: [(set (pc)
1234: (if_then_else (gt (cc0)
1235: (const_int 0))
1236: (pc)
1237: (label_ref (match_operand 0 "" ""))))]
1238: ""
1239: "* return gen_cmp (operands[0], \"le\", 't'); ")
1240:
1241: (define_insn ""
1242: [(set (pc)
1243: (if_then_else (gtu (cc0)
1244: (const_int 0))
1245: (pc)
1246: (label_ref (match_operand 0 "" ""))))]
1247: ""
1248: "* return gen_cmp (operands[0], \"leu\", 't'); ")
1249:
1250: (define_insn ""
1251: [(set (pc)
1252: (if_then_else (lt (cc0)
1253: (const_int 0))
1254: (pc)
1255: (label_ref (match_operand 0 "" ""))))]
1256: ""
1257: "* return gen_cmp (operands[0], \"lt\", 'f'); ")
1258:
1259: (define_insn ""
1260: [(set (pc)
1261: (if_then_else (ltu (cc0)
1262: (const_int 0))
1263: (pc)
1264: (label_ref (match_operand 0 "" ""))))]
1265: ""
1266: "* return gen_cmp (operands[0], \"ltu\", 'f'); ")
1267:
1268: (define_insn ""
1269: [(set (pc)
1270: (if_then_else (ge (cc0)
1271: (const_int 0))
1272: (pc)
1273: (label_ref (match_operand 0 "" ""))))]
1274: ""
1275: "* return gen_cmp (operands[0], \"lt\", 't'); ")
1276:
1277: (define_insn ""
1278: [(set (pc)
1279: (if_then_else (geu (cc0)
1280: (const_int 0))
1281: (pc)
1282: (label_ref (match_operand 0 "" ""))))]
1283: ""
1284: "* return gen_cmp (operands[0], \"ltu\", 't'); ")
1285:
1286: (define_insn ""
1287: [(set (pc)
1288: (if_then_else (le (cc0)
1289: (const_int 0))
1290: (pc)
1291: (label_ref (match_operand 0 "" ""))))]
1292: ""
1293: "* return gen_cmp (operands[0], \"le\", 'f'); ")
1294:
1295: (define_insn ""
1296: [(set (pc)
1297: (if_then_else (leu (cc0)
1298: (const_int 0))
1299: (pc)
1300: (label_ref (match_operand 0 "" ""))))]
1301: ""
1302: "* return gen_cmp (operands[0], \"leu\", 'f'); ")
1303:
1304: ;; - Calls
1305: ;;
1306: ;; arg count word may be omitted to save a push and let gcc try to
1307: ;; combine the arg list pop. RETURN_POPS_ARGS from tm.h decides this.
1308:
1309: (define_insn "call"
1310: [(call (match_operand:QI 0 "memory_operand" "m")
1.1.1.2 ! root 1311: (match_operand 1 "" "g"))]
1.1 root 1312: ""
1313: "* return output_call (insn, operands[0], operands[1]);")
1314:
1315: (define_insn "call_value"
1316: [(set (match_operand 0 "" "=g")
1317: (call (match_operand:QI 1 "memory_operand" "m")
1.1.1.2 ! root 1318: (match_operand 2 "" "g")))]
1.1 root 1319: ""
1320: "* return output_call (insn, operands[1], operands[2]);")
1321:
1322: (define_insn "return"
1323: [(return)]
1324: ""
1325: "rtn")
1326:
1327: (define_insn "nop"
1328: [(const_int 0)]
1329: ""
1330: "nop")
1331:
1332: (define_insn "tablejump"
1333: [(set (pc) (match_operand:SI 0 "address_operand" "p"))
1334: (use (label_ref (match_operand 1 "" "")))]
1335: ""
1336: "jmp %a0")
1337:
1338: (define_insn "indirect_jump"
1339: [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
1340: ""
1341: "jmp %a0")
1342:
1343: ;;- Local variables:
1344: ;;- mode:emacs-lisp
1345: ;;- comment-start: ";;- "
1346: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
1347: ;;- eval: (modify-syntax-entry ?[ "(]")
1348: ;;- eval: (modify-syntax-entry ?] ")[")
1349: ;;- eval: (modify-syntax-entry ?{ "(}")
1350: ;;- eval: (modify-syntax-entry ?} "){")
1351: ;;- End:
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