--- gcc/config/convex/convex.md	2018/04/24 18:10:25	1.1.1.1
+++ gcc/config/convex/convex.md	2018/04/24 18:21:41	1.1.1.3
@@ -1,6 +1,5 @@
-;;- Machine description for GNU compiler
-;;- Convex Version
-;;   Copyright (C) 1988, 1993 Free Software Foundation, Inc.
+;;- Machine description for GNU compiler, Convex Version
+;;  Copyright (C) 1988, 1994 Free Software Foundation, Inc.
 
 ;; This file is part of GNU CC.
 
@@ -1040,81 +1039,6 @@
 
 ;; SImode
 
-;; Logical left 1, 1 cycle on all machines via add
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(lshift:SI (match_operand:SI 1 "register_operand" "0")
-		   (const_int 1)))]
-  ""
-  "add.w %0,%0")
-
-;; C34 general shift is 1 cycle
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d,a")
-	(lshift:SI (match_operand:SI 1 "register_operand" "0,0")
-		   (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
-  "TARGET_C34"
-  "@
-   shf.w %2,%0
-   shf %2,%0"
-  [(set_attr "type" "shfw,shfw")])
-
-;; else shift left 0..7 is 1 cycle if we use an A register
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=a,?d")
-	(lshift:SI (match_operand:SI 1 "register_operand" "0,0")
-		   (match_operand:SI 2 "immediate_operand" "ai,di")))]
-  "TARGET_C1 && INTVAL (operands[2]) < (unsigned) 8"
-  "@
-   shf %2,%0
-   shf %2,%0"
-  [(set_attr "type" "alu,shfl")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=a,?d")
-	(lshift:SI (match_operand:SI 1 "register_operand" "0,0")
-		   (match_operand:SI 2 "immediate_operand" "ai,di")))]
-  "INTVAL (operands[2]) < (unsigned) 8"
-  "@
-   shf %2,%0
-   shf.w %2,%0"
-  [(set_attr "type" "alu,shfw")])
-
-;; else general left shift
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d,a")
-	(lshift:SI (match_operand:SI 1 "register_operand" "0,0")
-		   (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
-  "TARGET_C1"
-  "@
-   shf %2,%0
-   shf %2,%0"
-  [(set_attr "type" "shfl,shfw")])
-
-;; (but C2 shift left by a constant can is faster via multiply)
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(lshift:SI (match_operand:SI 1 "register_operand" "0")
-		   (match_operand:SI 2 "const_int_operand" "i")))]
-  "TARGET_C2 && INTVAL (operands[2]) < (unsigned) 32"
-  "mul.w %z2,%0"
-  [(set_attr "type" "mulw")])
-
-(define_insn "lshlsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d,a")
-	(lshift:SI (match_operand:SI 1 "register_operand" "0,0")
-		   (match_operand:SI 2 "nonmemory_operand" "di,ai")))]
-  ""
-  "@
-   shf.w %2,%0
-   shf %2,%0"
-  [(set_attr "type" "shfw,shfw")])
-
 ;; Arithmetic left 1, 1 cycle on all machines via add
 
 (define_insn ""
@@ -1170,6 +1094,8 @@
    shf %2,%0"
   [(set_attr "type" "shfl,shfw")])
 
+;; but C2 left shift by a constant is faster via multiply
+
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(ashift:SI (match_operand:SI 1 "register_operand" "0")
@@ -1276,25 +1202,6 @@
   [(set_attr "type" "shfl")])
 
 ;; DImode
-;; Logical left, 1-cycle
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(lshift:DI (match_operand:DI 1 "register_operand" "0")
-		   (const_int 1)))]
-  ""
-  "add.l %0,%0")
-
-;; Logical left, general
-
-(define_insn "lshldi3"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(lshift:DI (match_operand:DI 1 "register_operand" "0")
-		   (match_operand:SI 2 "nonmemory_operand" "di")))]
-  ""
-  "shf %2,%0"
-  [(set_attr "type" "shfl")])
-
 ;; Arithmetic left, 1-cycle
 
 (define_insn ""
@@ -1548,21 +1455,21 @@
   "* return output_cmp (operands[0], operands[1], 'b');")
 
 (define_insn ""
-  [(set (cc0) (match_operand:QI 0 "register_operand" "d,a"))
-   (clobber (match_scratch:QI 1 "=d,a"))]
+  [(set (cc0) (match_operand:QI 0 "register_operand" "d"))
+   (clobber (match_scratch:QI 1 "=d"))]
   "next_insn_tests_no_inequality (insn)"
   "* return output_cmp (operands[0], operands[1], 'B');")
 
 (define_insn ""
-  [(set (cc0) (subreg (match_operand:QI 0 "register_operand" "d,a") 0))
-   (clobber (match_scratch:QI 1 "=d,a"))]
+  [(set (cc0) (subreg (match_operand:QI 0 "register_operand" "d") 0))
+   (clobber (match_scratch:QI 1 "=d"))]
   "next_insn_tests_no_inequality (insn)"
   "* return output_cmp (operands[0], operands[1], 'B');")
 
 (define_insn ""
   [(set (cc0)
-	(zero_extend (subreg (match_operand:QI 0 "register_operand" "d,a") 0)))
-   (clobber (match_scratch:QI 1 "=d,a"))]
+	(zero_extend (subreg (match_operand:QI 0 "register_operand" "d") 0)))
+   (clobber (match_scratch:QI 1 "=d"))]
   "next_insn_tests_no_inequality (insn)"
   "* return output_cmp (operands[0], operands[1], 'B');")
 
@@ -1648,12 +1555,12 @@
 {
   if (which_alternative == 0)
     {
-      output_cmp (operands[0], constm1_rtx, 'W');
-      return \"add.w #-1,%0\";
+      output_cmp (operands[0], constm1_rtx, 'H');
+      return \"add.h #-1,%0\";
     }
   else
     {
-      output_cmp (gen_rtx (REG, HImode, 7), constm1_rtx, 'W');
+      output_cmp (gen_rtx (REG, HImode, 7), constm1_rtx, 'H');
       return \"psh.w s7\;ld.h %0,s7\;add.h #-1,s7\;st.h s7,%0\;pop.w s7\";
     }
 }")
@@ -1670,12 +1577,12 @@
 {
   if (which_alternative == 0)
     {
-      output_cmp (operands[0], const0_rtx, 'W');
-      return \"add.w #-1,%0\";
+      output_cmp (operands[0], const0_rtx, 'H');
+      return \"add.h #-1,%0\";
     }
   else
     {
-      output_cmp (gen_rtx (REG, HImode, 7), const0_rtx, 'W');
+      output_cmp (gen_rtx (REG, HImode, 7), const0_rtx, 'H');
       return \"psh.w s7\;ld.h %0,s7\;add.h #-1,s7\;st.h s7,%0\;pop.w s7\";
     }
 }")
@@ -1908,6 +1815,44 @@
   ""
   "* return output_call (insn, &operands[1]); ")
 
+;; Call subroutine returning any type.
+
+(define_expand "untyped_call"
+  [(parallel [(call (match_operand 0 "" "")
+                  (const_int 0))
+            (match_operand 1 "" "")
+            (match_operand 2 "" "")])]
+  ""
+  "
+{
+  int i;
+
+  emit_call_insn (gen_call_pop (operands[0], const0_rtx,
+				const0_rtx, const0_rtx));
+
+  for (i = 0; i < XVECLEN (operands[2], 0); i++)
+    {
+      rtx set = XVECEXP (operands[2], 0, i);
+      emit_move_insn (SET_DEST (set), SET_SRC (set));
+    }
+
+  /* The optimizer does not know that the call sets the function value
+     registers we stored in the result block.  We avoid problems by
+     claiming that all hard registers are used and clobbered at this
+     point.  */
+  emit_insn (gen_blockage ());
+
+  DONE;
+}")
+
+;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
+;; all of memory.  This blocks insns from being moved across this point.
+
+(define_insn "blockage"
+  [(unspec_volatile [(const_int 0)] 0)]
+  ""
+  "")
+
 (define_expand "return"
   [(return)]
   ""