--- gcc/config/convex/convex.md 2018/04/24 18:15:23 1.1.1.2 +++ gcc/config/convex/convex.md 2018/04/24 18:29:10 1.1.1.4 @@ -1,6 +1,5 @@ -;;- Machine description for GNU compiler -;;- Convex Version -;; Copyright (C) 1988, 1993 Free Software Foundation, Inc. +;;- Machine description for GNU compiler, Convex Version +;; Copyright (C) 1988, 1994, 1995 Free Software Foundation, Inc. ;; This file is part of GNU CC. @@ -16,7 +15,8 @@ ;; You should have received a copy of the GNU General Public License ;; along with GNU CC; see the file COPYING. If not, write to -;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. +;; the Free Software Foundation, 59 Temple Place - Suite 330, +;; Boston, MA 02111-1307, USA. ;; Attribute specifications @@ -1040,81 +1040,6 @@ ;; SImode -;; Logical left 1, 1 cycle on all machines via add - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (lshift:SI (match_operand:SI 1 "register_operand" "0") - (const_int 1)))] - "" - "add.w %0,%0") - -;; C34 general shift is 1 cycle - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=d,a") - (lshift:SI (match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "nonmemory_operand" "di,ai")))] - "TARGET_C34" - "@ - shf.w %2,%0 - shf %2,%0" - [(set_attr "type" "shfw,shfw")]) - -;; else shift left 0..7 is 1 cycle if we use an A register - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=a,?d") - (lshift:SI (match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "immediate_operand" "ai,di")))] - "TARGET_C1 && INTVAL (operands[2]) < (unsigned) 8" - "@ - shf %2,%0 - shf %2,%0" - [(set_attr "type" "alu,shfl")]) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=a,?d") - (lshift:SI (match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "immediate_operand" "ai,di")))] - "INTVAL (operands[2]) < (unsigned) 8" - "@ - shf %2,%0 - shf.w %2,%0" - [(set_attr "type" "alu,shfw")]) - -;; else general left shift - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=d,a") - (lshift:SI (match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "nonmemory_operand" "di,ai")))] - "TARGET_C1" - "@ - shf %2,%0 - shf %2,%0" - [(set_attr "type" "shfl,shfw")]) - -;; (but C2 shift left by a constant can is faster via multiply) - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (lshift:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "const_int_operand" "i")))] - "TARGET_C2 && INTVAL (operands[2]) < (unsigned) 32" - "mul.w %z2,%0" - [(set_attr "type" "mulw")]) - -(define_insn "lshlsi3" - [(set (match_operand:SI 0 "register_operand" "=d,a") - (lshift:SI (match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "nonmemory_operand" "di,ai")))] - "" - "@ - shf.w %2,%0 - shf %2,%0" - [(set_attr "type" "shfw,shfw")]) - ;; Arithmetic left 1, 1 cycle on all machines via add (define_insn "" @@ -1170,6 +1095,8 @@ shf %2,%0" [(set_attr "type" "shfl,shfw")]) +;; but C2 left shift by a constant is faster via multiply + (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (ashift:SI (match_operand:SI 1 "register_operand" "0") @@ -1276,25 +1203,6 @@ [(set_attr "type" "shfl")]) ;; DImode -;; Logical left, 1-cycle - -(define_insn "" - [(set (match_operand:DI 0 "register_operand" "=d") - (lshift:DI (match_operand:DI 1 "register_operand" "0") - (const_int 1)))] - "" - "add.l %0,%0") - -;; Logical left, general - -(define_insn "lshldi3" - [(set (match_operand:DI 0 "register_operand" "=d") - (lshift:DI (match_operand:DI 1 "register_operand" "0") - (match_operand:SI 2 "nonmemory_operand" "di")))] - "" - "shf %2,%0" - [(set_attr "type" "shfl")]) - ;; Arithmetic left, 1-cycle (define_insn "" @@ -1361,7 +1269,7 @@ ;; Use ;; ((a >> b) ^ signbit) - signbit ;; where signbit is (1 << 63) >> b -;; Works for 0..63. Does not work for 64; unfortunate but legal. +;; Works for 0..63. Does not work for 64; unfortunate but valid. (define_expand "ashrdi3" [(set (match_operand:DI 0 "register_operand" "") @@ -1548,21 +1456,21 @@ "* return output_cmp (operands[0], operands[1], 'b');") (define_insn "" - [(set (cc0) (match_operand:QI 0 "register_operand" "d,a")) - (clobber (match_scratch:QI 1 "=d,a"))] + [(set (cc0) (match_operand:QI 0 "register_operand" "d")) + (clobber (match_scratch:QI 1 "=d"))] "next_insn_tests_no_inequality (insn)" "* return output_cmp (operands[0], operands[1], 'B');") (define_insn "" - [(set (cc0) (subreg (match_operand:QI 0 "register_operand" "d,a") 0)) - (clobber (match_scratch:QI 1 "=d,a"))] + [(set (cc0) (subreg (match_operand:QI 0 "register_operand" "d") 0)) + (clobber (match_scratch:QI 1 "=d"))] "next_insn_tests_no_inequality (insn)" "* return output_cmp (operands[0], operands[1], 'B');") (define_insn "" [(set (cc0) - (zero_extend (subreg (match_operand:QI 0 "register_operand" "d,a") 0))) - (clobber (match_scratch:QI 1 "=d,a"))] + (zero_extend (subreg (match_operand:QI 0 "register_operand" "d") 0))) + (clobber (match_scratch:QI 1 "=d"))] "next_insn_tests_no_inequality (insn)" "* return output_cmp (operands[0], operands[1], 'B');") @@ -1648,12 +1556,12 @@ { if (which_alternative == 0) { - output_cmp (operands[0], constm1_rtx, 'W'); - return \"add.w #-1,%0\"; + output_cmp (operands[0], constm1_rtx, 'H'); + return \"add.h #-1,%0\"; } else { - output_cmp (gen_rtx (REG, HImode, 7), constm1_rtx, 'W'); + output_cmp (gen_rtx (REG, HImode, 7), constm1_rtx, 'H'); return \"psh.w s7\;ld.h %0,s7\;add.h #-1,s7\;st.h s7,%0\;pop.w s7\"; } }") @@ -1670,12 +1578,12 @@ { if (which_alternative == 0) { - output_cmp (operands[0], const0_rtx, 'W'); - return \"add.w #-1,%0\"; + output_cmp (operands[0], const0_rtx, 'H'); + return \"add.h #-1,%0\"; } else { - output_cmp (gen_rtx (REG, HImode, 7), const0_rtx, 'W'); + output_cmp (gen_rtx (REG, HImode, 7), const0_rtx, 'H'); return \"psh.w s7\;ld.h %0,s7\;add.h #-1,s7\;st.h s7,%0\;pop.w s7\"; } }")