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1.1.1.3 ! root 1: ;;- Machine description for GNU compiler, Convex Version ! 2: ;; Copyright (C) 1988, 1994 Free Software Foundation, Inc. 1.1 root 3: 4: ;; This file is part of GNU CC. 5: 6: ;; GNU CC is free software; you can redistribute it and/or modify 7: ;; it under the terms of the GNU General Public License as published by 8: ;; the Free Software Foundation; either version 2, or (at your option) 9: ;; any later version. 10: 11: ;; GNU CC is distributed in the hope that it will be useful, 12: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14: ;; GNU General Public License for more details. 15: 16: ;; You should have received a copy of the GNU General Public License 17: ;; along with GNU CC; see the file COPYING. If not, write to 18: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 19: 20: ;; Attribute specifications 21: 22: ; Target CPU 23: (define_attr "cpu" "c1,c32,c34,c38" 24: (const (symbol_ref "(enum attr_cpu) target_cpu"))) 25: 26: ;; Instruction classification 27: 28: (define_attr "type" 29: "alu,xalu,mldw,mldl,mldb,mst,adds,addd,mulw,mull,muls,muld,divw,divl,divs,divd,shfw,shfl,cvts,cvtd" 30: (const_string "alu")) 31: 32: ;; Instruction times 33: 34: (define_function_unit "mem" 1 0 35: (and (eq_attr "cpu" "c1") (eq_attr "type" "mldw")) 2 0) 36: (define_function_unit "mem" 1 0 37: (and (eq_attr "cpu" "c1") (eq_attr "type" "mldl")) 4 0) 38: (define_function_unit "mem" 1 0 39: (and (eq_attr "cpu" "c32") (eq_attr "type" "mldw,mldl")) 2 0) 40: (define_function_unit "mem" 1 0 41: (and (eq_attr "cpu" "c34") (eq_attr "type" "mldw,mldl")) 4 0) 42: (define_function_unit "mem" 1 0 43: (and (eq_attr "cpu" "c38") (eq_attr "type" "mldw,mldl")) 2 0) 44: 45: (define_function_unit "mem" 1 0 46: (and (eq_attr "cpu" "c32") (eq_attr "type" "mldb")) 9 0) 47: (define_function_unit "mem" 1 0 48: (and (eq_attr "cpu" "c34") (eq_attr "type" "mldb")) 36 0) 49: (define_function_unit "mem" 1 0 50: (and (eq_attr "cpu" "c38") (eq_attr "type" "mldb")) 21 0) 51: 52: (define_function_unit "mem" 1 0 53: (and (eq_attr "cpu" "c1") (eq_attr "type" "xalu")) 1 0) 54: (define_function_unit "mem" 1 0 55: (and (eq_attr "cpu" "c32") (eq_attr "type" "xalu")) 1 0) 56: (define_function_unit "mem" 1 0 57: (and (eq_attr "cpu" "c34") (eq_attr "type" "xalu")) 5 0) 58: (define_function_unit "mem" 1 0 59: (and (eq_attr "cpu" "c38") (eq_attr "type" "xalu")) 2 0) 60: 61: (define_function_unit "add" 1 0 62: (and (eq_attr "cpu" "c1") (eq_attr "type" "adds,addd")) 3 2) 63: (define_function_unit "add" 1 0 64: (and (eq_attr "cpu" "c32") (eq_attr "type" "adds,addd")) 2 1) 65: (define_function_unit "add" 1 0 66: (and (eq_attr "cpu" "c34") (eq_attr "type" "adds,addd")) 5 2) 67: (define_function_unit "add" 1 0 68: (and (eq_attr "cpu" "c38") (eq_attr "type" "adds,addd")) 2 1) 69: 70: (define_function_unit "mul" 1 0 71: (and (eq_attr "cpu" "c1") (eq_attr "type" "mulw,muls")) 3 2) 72: (define_function_unit "mul" 1 0 73: (and (eq_attr "cpu" "c32") (eq_attr "type" "mulw,muls")) 4 2) 74: (define_function_unit "mul" 1 0 75: (and (eq_attr "cpu" "c34") (eq_attr "type" "mulw,muls")) 6 2) 76: (define_function_unit "mul" 1 0 77: (and (eq_attr "cpu" "c38") (eq_attr "type" "mulw,muls")) 3 2) 78: 79: (define_function_unit "mul" 1 0 80: (and (eq_attr "cpu" "c1") (eq_attr "type" "mull,muld")) 4 3) 81: (define_function_unit "mul" 1 0 82: (and (eq_attr "cpu" "c32") (eq_attr "type" "mull")) 10 7) 83: (define_function_unit "mul" 1 0 84: (and (eq_attr "cpu" "c32") (eq_attr "type" "muld")) 5 2) 85: (define_function_unit "mul" 1 0 86: (and (eq_attr "cpu" "c34") (eq_attr "type" "mull,muld")) 7 3) 87: (define_function_unit "mul" 1 0 88: (and (eq_attr "cpu" "c38") (eq_attr "type" "mull,muld")) 4 3) 89: 90: (define_function_unit "div" 1 0 91: (and (eq_attr "cpu" "c1") (eq_attr "type" "divw")) 24 24) 92: (define_function_unit "div" 1 0 93: (and (eq_attr "cpu" "c32") (eq_attr "type" "divw")) 44 6) 94: (define_function_unit "div" 1 0 95: (and (eq_attr "cpu" "c34") (eq_attr "type" "divw")) 14 10) 96: (define_function_unit "div" 1 0 97: (and (eq_attr "cpu" "c38") (eq_attr "type" "divw")) 11 10) 98: 99: (define_function_unit "div" 1 0 100: (and (eq_attr "cpu" "c1") (eq_attr "type" "divl")) 41 42) 101: (define_function_unit "div" 1 0 102: (and (eq_attr "cpu" "c32") (eq_attr "type" "divl")) 76 5) 103: (define_function_unit "div" 1 0 104: (and (eq_attr "cpu" "c34") (eq_attr "type" "divl")) 22 18) 105: (define_function_unit "div" 1 0 106: (and (eq_attr "cpu" "c38") (eq_attr "type" "divl")) 19 18) 107: 108: (define_function_unit "div" 1 0 109: (and (eq_attr "cpu" "c1") (eq_attr "type" "divs")) 22 22) 110: (define_function_unit "div" 1 0 111: (and (eq_attr "cpu" "c32") (eq_attr "type" "divs")) 8 6) 112: (define_function_unit "div" 1 0 113: (and (eq_attr "cpu" "c34") (eq_attr "type" "divs")) 13 9) 114: (define_function_unit "div" 1 0 115: (and (eq_attr "cpu" "c38") (eq_attr "type" "divs")) 10 9) 116: 117: (define_function_unit "div" 1 0 118: (and (eq_attr "cpu" "c1") (eq_attr "type" "divd")) 37 38) 119: (define_function_unit "div" 1 0 120: (and (eq_attr "cpu" "c32") (eq_attr "type" "divd")) 12 8) 121: (define_function_unit "div" 1 0 122: (and (eq_attr "cpu" "c34") (eq_attr "type" "divd")) 20 16) 123: (define_function_unit "div" 1 0 124: (and (eq_attr "cpu" "c38") (eq_attr "type" "divd")) 17 16) 125: 126: (define_function_unit "misc" 1 0 127: (and (eq_attr "cpu" "c1") (eq_attr "type" "cvts,cvtd")) 4 3) 128: (define_function_unit "misc" 1 0 129: (and (eq_attr "cpu" "c32") (eq_attr "type" "cvts")) 9 7) 130: (define_function_unit "misc" 1 0 131: (and (eq_attr "cpu" "c32") (eq_attr "type" "cvtd")) 9 6) 132: (define_function_unit "misc" 1 0 133: (and (eq_attr "cpu" "c34") (eq_attr "type" "cvts")) 6 2) 134: (define_function_unit "misc" 1 0 135: (and (eq_attr "cpu" "c34") (eq_attr "type" "cvtd")) 6 1) 136: (define_function_unit "misc" 1 0 137: (and (eq_attr "cpu" "c38") (eq_attr "type" "cvts,cvtd")) 3 1) 138: 139: (define_function_unit "misc" 1 0 140: (and (eq_attr "cpu" "c1") (eq_attr "type" "shfw,shfl")) 3 2) 141: (define_function_unit "misc" 1 0 142: (and (eq_attr "cpu" "c32") (eq_attr "type" "shfw")) 7 5) 143: (define_function_unit "misc" 1 0 144: (and (eq_attr "cpu" "c32") (eq_attr "type" "shfl")) 7 4) 145: (define_function_unit "misc" 1 0 146: (and (eq_attr "cpu" "c38") (eq_attr "type" "shfw,shfl")) 3 1) 147: 148: (define_function_unit "mystery_latch" 1 1 149: (and (eq_attr "type" "!alu,mldw,mldl,adds,addd") (eq_attr "cpu" "c32")) 2 2) 150: 151: ;(define_function_unit "ip" 1 1 152: ; (and (eq_attr "cpu" "c1") 153: ; (eq_attr "type" "divw,divl,divs,divd,xalu")) 2 2) 154: ;(define_function_unit "ip" 1 1 155: ; (and (eq_attr "cpu" "c1") 156: ; (eq_attr "type" "!divw,divl,divs,divd,xalu")) 1 1) 157: ;(define_function_unit "ip" 1 1 158: ; (and (eq_attr "cpu" "c32") 159: ; (eq_attr "type" "mull,muld,divl,divd,shfl,cvtd,xalu")) 2 2) 160: ;(define_function_unit "ip" 1 1 161: ; (and (eq_attr "cpu" "c32") 162: ; (eq_attr "type" "!mull,muld,divl,divd,shfl,cvtd,xalu")) 1 1) 163: ;(define_function_unit "ip" 1 1 164: ; (and (eq_attr "cpu" "c34") 165: ; (eq_attr "type" "addd,mull,muld,divl,divd,cvtd,xalu")) 2 2) 166: ;(define_function_unit "ip" 1 1 167: ; (and (eq_attr "cpu" "c34") 168: ; (eq_attr "type" "!addd,mull,muld,divl,divd,cvtd,xalu")) 1 1) 169: 170: ;; Make the first thing a real insn in case of genattrtab bug 171: 172: (define_insn "nop" 173: [(const_int 0)] 174: "" 175: "nop") 176: 177: ;; Moves 178: 179: (define_expand "movdf" 180: [(set (match_operand:DF 0 "general_operand" "") 181: (match_operand:DF 1 "general_operand" ""))] 182: "" 183: "if (GET_CODE (operands[0]) != REG) 184: operands[1] = force_reg (DFmode, operands[1]);") 185: 186: (define_insn "" 187: [(set (match_operand:DF 0 "general_operand" "=d,d,d,d,d,<,m") 188: (match_operand:DF 1 "general_operand" "d,Q,m,G,H,d,d"))] 189: "register_operand (operands[0], DFmode) 190: || register_operand (operands[1], DFmode)" 191: "@ 192: mov %1,%0 193: ldb.d %1,%0 194: ld.d %1,%0 195: ld.d %u1,%0 196: ld.l %v1,%0 197: psh.l %1 198: st.d %1,%0" 199: [(set_attr "type" "alu,mldb,mldl,alu,alu,alu,mst")]) 200: 201: ;; This is here so we can load any result of RTL constant folding 202: ;; but do not use it on constants that can be loaded from memory. 203: ;; It is never better and can be worse. 204: 205: (define_insn "" 206: [(set (match_operand:DF 0 "register_operand" "=d") 207: (match_operand:DF 1 "const_double_operand" "F"))] 208: "CONST_DOUBLE_MEM (operands[1]) == const0_rtx" 209: "ld.u %u1,%0\;ld.w %v1,%0" 210: [(set_attr "type" "xalu")]) 211: 212: (define_expand "movsf" 213: [(set (match_operand:SF 0 "general_operand" "") 214: (match_operand:SF 1 "general_operand" ""))] 215: "" 216: "if (GET_CODE (operands[0]) != REG) 217: operands[1] = force_reg (SFmode, operands[1]);") 218: 219: (define_insn "" 220: [(set (match_operand:SF 0 "general_operand" "=d,d,d,d,<,m") 221: (match_operand:SF 1 "general_operand" "d,Q,m,F,d,d"))] 222: "register_operand (operands[0], SFmode) 223: || register_operand (operands[1], SFmode)" 224: "@ 225: mov.s %1,%0 226: ldb.s %1,%0 227: ld.s %1,%0 228: ld.s %1,%0 229: psh.w %1 230: st.s %1,%0" 231: [(set_attr "type" "alu,mldb,mldw,alu,alu,mst")]) 232: 233: (define_expand "movdi" 234: [(set (match_operand:DI 0 "general_operand" "") 235: (match_operand:DI 1 "general_operand" ""))] 236: "" 237: "if (GET_CODE (operands[0]) != REG) 238: operands[1] = force_reg (DImode, operands[1]);") 239: 240: (define_insn "" 241: [(set (match_operand:DI 0 "general_operand" "=d,d,d,d,d,<,m") 242: (match_operand:DI 1 "general_operand" "d,Q,m,G,HI,d,d"))] 243: "register_operand (operands[0], DImode) 244: || register_operand (operands[1], DImode)" 245: "@ 246: mov %1,%0 247: ldb.l %1,%0 248: ld.l %1,%0 249: ld.d %u1,%0 250: ld.l %1,%0 251: psh.l %1 252: st.l %1,%0" 253: [(set_attr "type" "alu,mldb,mldl,alu,alu,alu,mst")]) 254: 255: ;; This is here so we can load any result of RTL constant folding 256: ;; but do not use it on constants that can be loaded from memory. 257: ;; It is never better and can be worse. 258: 259: (define_insn "" 260: [(set (match_operand:DI 0 "register_operand" "=d") 261: (match_operand:DI 1 "const_double_operand" "F"))] 262: "CONST_DOUBLE_MEM (operands[1]) == const0_rtx" 263: "ld.u %u1,%0\;ld.w %v1,%0" 264: [(set_attr "type" "xalu")]) 265: 266: (define_expand "movsi" 267: [(set (match_operand:SI 0 "general_operand" "") 268: (match_operand:SI 1 "general_operand" ""))] 269: "" 270: "if (GET_CODE (operands[0]) != REG) 271: operands[1] = force_reg (SImode, operands[1]);") 272: 273: (define_insn "" 274: [(set (match_operand:SI 0 "push_operand" "=<,<") 275: (match_operand:SI 1 "nonmemory_operand" "Ad,i"))] 276: "" 277: "@ 278: psh.w %1 279: pshea %a1") 280: 281: (define_insn "" 282: [(set (match_operand:SI 0 "general_operand" "=d,r,d,r,r,m") 283: (match_operand:SI 1 "general_operand" "d,r,Q,m,i,r"))] 284: "register_operand (operands[0], SImode) 285: || register_operand (operands[1], SImode)" 286: "@ 287: mov.w %1,%0 288: mov %1,%0 289: ldb.w %1,%0 290: ld.w %1,%0 291: ld.w %1,%0 292: st.w %1,%0" 293: [(set_attr "type" "alu,alu,mldb,mldw,alu,mst")]) 294: 295: (define_expand "movstrictsi" 296: [(set (strict_low_part (match_operand:SI 0 "general_operand" "")) 297: (match_operand:SI 1 "general_operand" ""))] 298: "" 299: "if (GET_CODE (operands[0]) != REG) 300: operands[1] = force_reg (SImode, operands[1]);") 301: 302: (define_insn "" 303: [(set (strict_low_part (match_operand:SI 0 "general_operand" "=d,r,d,r,r,m")) 304: (match_operand:SI 1 "general_operand" "d,r,Q,m,i,r"))] 305: "register_operand (operands[0], SImode) 306: || register_operand (operands[1], SImode)" 307: "@ 308: mov.w %1,%0 309: mov %1,%0 310: ldb.w %1,%0 311: ld.w %1,%0 312: ld.w %1,%0 313: st.w %1,%0" 314: [(set_attr "type" "alu,alu,mldb,mldw,alu,mst")]) 315: 316: (define_expand "movhi" 317: [(set (match_operand:HI 0 "general_operand" "") 318: (match_operand:HI 1 "general_operand" ""))] 319: "" 320: "if (GET_CODE (operands[0]) != REG) 321: operands[1] = force_reg (HImode, operands[1]);") 322: 323: (define_insn "" 324: [(set (match_operand:HI 0 "general_operand" "=d,r,d,r,r,<,m") 325: (match_operand:HI 1 "general_operand" "d,r,Q,m,i,Ad,r"))] 326: "register_operand (operands[0], HImode) 327: || register_operand (operands[1], HImode)" 328: "@ 329: mov.w %1,%0 330: mov %1,%0 331: ldb.h %1,%0 332: ld.h %1,%0 333: ld.w %1,%0 334: psh.w %1 335: st.h %1,%0" 336: [(set_attr "type" "alu,alu,mldb,mldw,alu,alu,mst")]) 337: 338: (define_expand "movqi" 339: [(set (match_operand:QI 0 "general_operand" "") 340: (match_operand:QI 1 "general_operand" ""))] 341: "" 342: "if (GET_CODE (operands[0]) != REG) 343: operands[1] = force_reg (QImode, operands[1]);") 344: 345: (define_insn "" 346: [(set (match_operand:QI 0 "general_operand" "=d,r,d,r,r,<,m") 347: (match_operand:QI 1 "general_operand" "d,r,Q,m,i,Ad,r"))] 348: "register_operand (operands[0], QImode) 349: || register_operand (operands[1], QImode)" 350: "@ 351: mov.w %1,%0 352: mov %1,%0 353: ldb.b %1,%0 354: ld.b %1,%0 355: ld.w %1,%0 356: psh.w %1 357: st.b %1,%0" 358: [(set_attr "type" "alu,alu,mldb,mldw,alu,alu,mst")]) 359: 360: ;; Expand block moves manually to get code that pipelines the loads. 361: 362: (define_expand "movstrsi" 363: [(set (match_operand:BLK 0 "memory_operand" "=m") 364: (match_operand:BLK 1 "memory_operand" "m")) 365: (use (match_operand:SI 2 "const_int_operand" "i")) 366: (use (match_operand:SI 3 "const_int_operand" "i"))] 367: "" 368: " expand_movstr (operands); DONE; ") 369: 370: ;; Extension and truncation insns. 371: ;; Those for integer source operand 372: ;; are ordered widest source type first. 373: 374: (define_insn "truncsiqi2" 375: [(set (match_operand:QI 0 "register_operand" "=d,a") 376: (truncate:QI (match_operand:SI 1 "register_operand" "d,a")))] 377: "" 378: "cvtw.b %1,%0") 379: 380: (define_insn "truncsihi2" 381: [(set (match_operand:HI 0 "register_operand" "=d,a") 382: (truncate:HI (match_operand:SI 1 "register_operand" "d,a")))] 383: "" 384: "cvtw.h %1,%0") 385: 386: (define_insn "trunchiqi2" 387: [(set (match_operand:QI 0 "register_operand" "=r") 388: (truncate:QI (match_operand:HI 1 "register_operand" "0")))] 389: "" 390: "") 391: 392: (define_insn "truncdisi2" 393: [(set (match_operand:SI 0 "register_operand" "=d") 394: (truncate:SI (match_operand:DI 1 "register_operand" "d")))] 395: "" 396: "cvtl.w %1,%0") 397: 398: (define_insn "extendsidi2" 399: [(set (match_operand:DI 0 "register_operand" "=d") 400: (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))] 401: "" 402: "cvtw.l %1,%0") 403: 404: (define_insn "extendhisi2" 405: [(set (match_operand:SI 0 "register_operand" "=d,a") 406: (sign_extend:SI (match_operand:HI 1 "register_operand" "d,a")))] 407: "" 408: "cvth.w %1,%0") 409: 410: (define_insn "extendqihi2" 411: [(set (match_operand:HI 0 "register_operand" "=d,a") 412: (sign_extend:HI (match_operand:QI 1 "register_operand" "d,a")))] 413: "" 414: "cvtb.w %1,%0") 415: 416: (define_insn "extendqisi2" 417: [(set (match_operand:SI 0 "register_operand" "=d,a") 418: (sign_extend:SI (match_operand:QI 1 "register_operand" "d,a")))] 419: "" 420: "cvtb.w %1,%0") 421: 422: (define_insn "extendsfdf2" 423: [(set (match_operand:DF 0 "register_operand" "=d") 424: (float_extend:DF (match_operand:SF 1 "register_operand" "d")))] 425: "" 426: "cvts.d %1,%0" 427: [(set_attr "type" "cvts")]) 428: 429: (define_insn "truncdfsf2" 430: [(set (match_operand:SF 0 "register_operand" "=d") 431: (float_truncate:SF (match_operand:DF 1 "register_operand" "d")))] 432: "" 433: "cvtd.s %1,%0" 434: [(set_attr "type" "cvtd")]) 435: 436: (define_insn "zero_extendhisi2" 437: [(set (match_operand:SI 0 "register_operand" "=r") 438: (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))] 439: "" 440: "and #0xffff,%0") 441: 442: (define_insn "zero_extendqihi2" 443: [(set (match_operand:HI 0 "register_operand" "=r") 444: (zero_extend:HI (match_operand:QI 1 "register_operand" "0")))] 445: "" 446: "and #0xff,%0") 447: 448: (define_insn "zero_extendqisi2" 449: [(set (match_operand:SI 0 "register_operand" "=r") 450: (zero_extend:SI (match_operand:QI 1 "register_operand" "0")))] 451: "" 452: "and #0xff,%0") 453: 454: (define_insn "zero_extendsidi2" 455: [(set (match_operand:DI 0 "register_operand" "=d") 456: (zero_extend:DI (match_operand:SI 1 "register_operand" "0")))] 457: "" 458: "ld.u #0,%0") 459: 460: ;; Fix-to-float conversion insns. 461: ;; Note that the ones that start with SImode come first. 462: ;; That is so that an operand that is a CONST_INT 463: ;; (and therefore lacks a specific machine mode). 464: ;; will be recognized as SImode (which is always valid) 465: ;; rather than as QImode or HImode. 466: 467: (define_insn "floatsisf2" 468: [(set (match_operand:SF 0 "register_operand" "=d") 469: (float:SF (match_operand:SI 1 "register_operand" "d")))] 470: "" 471: "cvtw.s %1,%0" 472: [(set_attr "type" "cvts")]) 473: 474: (define_insn "floatdisf2" 475: [(set (match_operand:SF 0 "register_operand" "=d") 476: (float:SF (match_operand:DI 1 "register_operand" "d")))] 477: "" 478: "cvtl.s %1,%0" 479: [(set_attr "type" "cvtd")]) 480: 481: (define_insn "floatsidf2" 482: [(set (match_operand:DF 0 "register_operand" "=d") 483: (float:DF (match_operand:SI 1 "register_operand" "d")))] 484: "! TARGET_C1" 485: "cvtw.d %1,%0" 486: [(set_attr "type" "cvts")]) 487: 488: (define_insn "floatdidf2" 489: [(set (match_operand:DF 0 "register_operand" "=d") 490: (float:DF (match_operand:DI 1 "register_operand" "d")))] 491: "" 492: "cvtl.d %1,%0" 493: [(set_attr "type" "cvtd")]) 494: 495: ;; These are a little slower than gcc's normal way of doing unsigned 496: ;; DI floats (if the DI number is "negative") but they avoid double 497: ;; rounding and they avoid explicit constants. 498: 499: (define_expand "floatunsdidf2" 500: [(set (match_operand:DF 0 "register_operand" "=d") 501: (float:DF (match_operand:DI 1 "register_operand" "d"))) 502: (set (cc0) (compare:DI (match_dup 3) (match_dup 1))) 503: (set (pc) 504: (if_then_else (le (cc0) (const_int 0)) 505: (label_ref (match_dup 4)) 506: (pc))) 507: (set (match_dup 2) (lshiftrt:DI (match_dup 1) (const_int 1))) 508: (set (match_dup 0) (float:DF (match_dup 2))) 509: (set (match_dup 0) (plus:DF (match_dup 0) (match_dup 0))) 510: (match_dup 4) 511: (set (match_dup 0) (match_dup 0))] 512: "" 513: " 514: { 515: operands[2] = gen_reg_rtx (DImode); 516: operands[3] = force_reg (DImode, const0_rtx); 517: operands[4] = gen_label_rtx (); 518: }") 519: 520: (define_expand "floatunsdisf2" 521: [(set (match_operand:SF 0 "register_operand" "=d") 522: (float:SF (match_operand:DI 1 "register_operand" "d"))) 523: (set (cc0) (compare:DI (match_dup 3) (match_dup 1))) 524: (set (pc) 525: (if_then_else (le (cc0) (const_int 0)) 526: (label_ref (match_dup 4)) 527: (pc))) 528: (set (match_dup 2) (lshiftrt:DI (match_dup 1) (const_int 1))) 529: (set (match_dup 0) (float:SF (match_dup 2))) 530: (set (match_dup 0) (plus:SF (match_dup 0) (match_dup 0))) 531: (match_dup 4) 532: (set (match_dup 0) (match_dup 0))] 533: "" 534: " 535: { 536: operands[2] = gen_reg_rtx (DImode); 537: operands[3] = force_reg (DImode, const0_rtx); 538: operands[4] = gen_label_rtx (); 539: }") 540: 541: ;; These patterns are identical to gcc's default action 542: ;; if DI->DF and DI->SF are not present. There are here 543: ;; only to prevent SI->*F from promoting to DI->*F. 544: 545: (define_expand "floatunssidf2" 546: [(set (match_dup 2) 547: (zero_extend:DI (match_operand:SI 1 "register_operand" ""))) 548: (set (match_operand:DF 0 "register_operand" "") 549: (float:DF (match_dup 2)))] 550: "" 551: "operands[2] = gen_reg_rtx (DImode);") 552: 553: (define_expand "floatunssisf2" 554: [(set (match_dup 2) 555: (zero_extend:DI (match_operand:SI 1 "register_operand" ""))) 556: (set (match_operand:SF 0 "register_operand" "") 557: (float:SF (match_dup 2)))] 558: "" 559: "operands[2] = gen_reg_rtx (DImode);") 560: 561: ;; Float-to-fix conversion insns. 562: 563: (define_insn "fix_truncsfsi2" 564: [(set (match_operand:SI 0 "register_operand" "=d") 565: (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "d"))))] 566: "" 567: "cvts.w %1,%0" 568: [(set_attr "type" "cvts")]) 569: 570: (define_insn "fix_truncsfdi2" 571: [(set (match_operand:DI 0 "register_operand" "=d") 572: (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "d"))))] 573: "" 574: "cvts.l %1,%0" 575: [(set_attr "type" "cvts")]) 576: 577: (define_insn "fix_truncdfsi2" 578: [(set (match_operand:SI 0 "register_operand" "=d") 579: (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "d"))))] 580: "" 581: "cvtd.l %1,%0" 582: [(set_attr "type" "cvtd")]) 583: 584: (define_insn "fix_truncdfdi2" 585: [(set (match_operand:DI 0 "register_operand" "=d") 586: (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))] 587: "" 588: "cvtd.l %1,%0" 589: [(set_attr "type" "cvtd")]) 590: 591: ;;- All kinds of add instructions. 592: 593: (define_insn "adddf3" 594: [(set (match_operand:DF 0 "register_operand" "=d") 595: (plus:DF (match_operand:DF 1 "register_operand" "%0") 596: (match_operand:DF 2 "register_operand" "d")))] 597: "" 598: "add.d %2,%0" 599: [(set_attr "type" "addd")]) 600: 601: (define_insn "addsf3" 602: [(set (match_operand:SF 0 "register_operand" "=d") 603: (plus:SF (match_operand:SF 1 "register_operand" "%0") 604: (match_operand:SF 2 "nonmemory_operand" "dF")))] 605: "" 606: "add.s %2,%0" 607: [(set_attr "type" "adds")]) 608: 609: (define_insn "adddi3" 610: [(set (match_operand:DI 0 "register_operand" "=d") 611: (plus:DI (match_operand:DI 1 "register_operand" "%0") 612: (match_operand:DI 2 "register_operand" "d")))] 613: "" 614: "add.l %2,%0") 615: 616: (define_expand "addsi3" 617: [(set (match_operand:SI 0 "register_operand" "") 618: (plus:SI (match_operand:SI 1 "register_operand" "") 619: (match_operand:SI 2 "nonmemory_operand" "")))] 620: "" 621: "") 622: 623: (define_insn "" 624: [(set (match_operand:SI 0 "register_operand" "=a") 625: (plus:SI (match_operand:SI 1 "register_operand" "%A") 626: (match_operand:SI 2 "immediate_operand" "i")))] 627: "operands[1] == frame_pointer_rtx || operands[1] == arg_pointer_rtx" 628: "ldea %a2(%1),%0") 629: 630: (define_insn "" 631: [(set (match_operand:SI 0 "register_operand" "=a") 632: (plus:SI (match_operand:SI 1 "register_operand" "%a") 633: (match_operand:SI 2 "nonmemory_operand" "ri")))] 634: "operands[1] == stack_pointer_rtx && operands[0] != stack_pointer_rtx" 635: "mov %1,%0\;add.w %2,%0") 636: 637: (define_insn "" 638: [(set (match_operand:SI 0 "push_operand" "=<") 639: (plus:SI (match_operand:SI 1 "register_operand" "A") 640: (match_operand:SI 2 "immediate_operand" "i")))] 641: "operands[1] != stack_pointer_rtx" 642: "pshea %a2(%1)" 643: [(set_attr "type" "mst")]) 644: 645: (define_insn "" 646: [(set (match_operand:SI 0 "register_operand" "=d,a,a") 647: (plus:SI (match_operand:SI 1 "register_operand" "%0,0,A") 648: (match_operand:SI 2 "nonmemory_operand" "di,ri,i")))] 649: "TARGET_C1" 650: "@ 651: add.w %2,%0 652: add.w %2,%0 653: ldea %a2(%1),%0") 654: 655: (define_insn "" 656: [(set (match_operand:SI 0 "register_operand" "=d,a,r") 657: (plus:SI (match_operand:SI 1 "register_operand" "%0,0,A") 658: (match_operand:SI 2 "nonmemory_operand" "di,ri,i")))] 659: "" 660: "@ 661: add.w %2,%0 662: add.w %2,%0 663: ldea %a2(%1),%0") 664: 665: (define_insn "addhi3" 666: [(set (match_operand:HI 0 "register_operand" "=d,a") 667: (plus:HI (match_operand:HI 1 "register_operand" "%0,0") 668: (match_operand:HI 2 "nonmemory_operand" "di,ai")))] 669: "" 670: "add.h %2,%0") 671: 672: (define_insn "addqi3" 673: [(set (match_operand:QI 0 "register_operand" "=d,d") 674: (plus:QI (match_operand:QI 1 "register_operand" "%0,0") 675: (match_operand:QI 2 "nonmemory_operand" "d,i")))] 676: "" 677: "@ 678: add.b %2,%0 679: add.w %2,%0") 680: 681: ;;- All kinds of subtract instructions. 682: 683: (define_insn "subdf3" 684: [(set (match_operand:DF 0 "register_operand" "=d") 685: (minus:DF (match_operand:DF 1 "register_operand" "0") 686: (match_operand:DF 2 "register_operand" "d")))] 687: "" 688: "sub.d %2,%0" 689: [(set_attr "type" "addd")]) 690: 691: (define_insn "subsf3" 692: [(set (match_operand:SF 0 "register_operand" "=d") 693: (minus:SF (match_operand:SF 1 "register_operand" "0") 694: (match_operand:SF 2 "nonmemory_operand" "dF")))] 695: "" 696: "sub.s %2,%0" 697: [(set_attr "type" "adds")]) 698: 699: (define_insn "subdi3" 700: [(set (match_operand:DI 0 "register_operand" "=d") 701: (minus:DI (match_operand:DI 1 "register_operand" "0") 702: (match_operand:DI 2 "register_operand" "d")))] 703: "" 704: "sub.l %2,%0") 705: 706: (define_insn "subsi3" 707: [(set (match_operand:SI 0 "register_operand" "=d,a,?d,?a") 708: (minus:SI (match_operand:SI 1 "nonmemory_operand" "0,0,di,ai") 709: (match_operand:SI 2 "nonmemory_operand" "di,ai,0,0")))] 710: "" 711: "@ 712: sub.w %2,%0 713: sub.w %2,%0 714: sub.w %1,%0\;neg.w %0,%0 715: sub.w %1,%0\;neg.w %0,%0") 716: 717: (define_insn "subhi3" 718: [(set (match_operand:HI 0 "register_operand" "=d,a") 719: (minus:HI (match_operand:HI 1 "register_operand" "0,0") 720: (match_operand:HI 2 "nonmemory_operand" "di,ai")))] 721: "" 722: "sub.h %2,%0") 723: 724: (define_insn "subqi3" 725: [(set (match_operand:QI 0 "register_operand" "=d,d") 726: (minus:QI (match_operand:QI 1 "register_operand" "0,0") 727: (match_operand:QI 2 "nonmemory_operand" "d,i")))] 728: "" 729: "@ 730: sub.b %2,%0 731: sub.w %2,%0") 732: 733: ;;- Multiply instructions. 734: 735: (define_insn "muldf3" 736: [(set (match_operand:DF 0 "register_operand" "=d") 737: (mult:DF (match_operand:DF 1 "register_operand" "%0") 738: (match_operand:DF 2 "register_operand" "d")))] 739: "" 740: "mul.d %2,%0" 741: [(set_attr "type" "muld")]) 742: 743: (define_insn "mulsf3" 744: [(set (match_operand:SF 0 "register_operand" "=d") 745: (mult:SF (match_operand:SF 1 "register_operand" "%0") 746: (match_operand:SF 2 "nonmemory_operand" "dF")))] 747: "" 748: "mul.s %2,%0" 749: [(set_attr "type" "muls")]) 750: 751: (define_insn "muldi3" 752: [(set (match_operand:DI 0 "register_operand" "=d") 753: (mult:DI (match_operand:DI 1 "register_operand" "%0") 754: (match_operand:DI 2 "register_operand" "d")))] 755: "" 756: "mul.l %2,%0" 757: [(set_attr "type" "mull")]) 758: 759: (define_insn "mulsi3" 760: [(set (match_operand:SI 0 "register_operand" "=d,a") 761: (mult:SI (match_operand:SI 1 "register_operand" "%0,0") 762: (match_operand:SI 2 "nonmemory_operand" "di,ai")))] 763: "" 764: "mul.w %2,%0" 765: [(set_attr "type" "mulw")]) 766: 767: (define_insn "mulhi3" 768: [(set (match_operand:HI 0 "register_operand" "=d,a") 769: (mult:HI (match_operand:HI 1 "register_operand" "%0,0") 770: (match_operand:HI 2 "nonmemory_operand" "di,ai")))] 771: "" 772: "mul.h %2,%0" 773: [(set_attr "type" "mulw")]) 774: 775: (define_insn "mulqi3" 776: [(set (match_operand:QI 0 "register_operand" "=d,d") 777: (mult:QI (match_operand:QI 1 "register_operand" "%0,0") 778: (match_operand:QI 2 "nonmemory_operand" "d,i")))] 779: "" 780: "@ 781: mul.b %2,%0 782: mul.w %2,%0" 783: [(set_attr "type" "mulw,mulw")]) 784: 785: ;;- Divide instructions. 786: 787: (define_insn "divdf3" 788: [(set (match_operand:DF 0 "register_operand" "=d") 789: (div:DF (match_operand:DF 1 "register_operand" "0") 790: (match_operand:DF 2 "register_operand" "d")))] 791: "" 792: "div.d %2,%0" 793: [(set_attr "type" "divd")]) 794: 795: (define_insn "divsf3" 796: [(set (match_operand:SF 0 "register_operand" "=d") 797: (div:SF (match_operand:SF 1 "register_operand" "0") 798: (match_operand:SF 2 "nonmemory_operand" "dF")))] 799: "" 800: "div.s %2,%0" 801: [(set_attr "type" "divs")]) 802: 803: (define_insn "divdi3" 804: [(set (match_operand:DI 0 "register_operand" "=d") 805: (div:DI (match_operand:DI 1 "register_operand" "0") 806: (match_operand:DI 2 "register_operand" "d")))] 807: "" 808: "div.l %2,%0" 809: [(set_attr "type" "divl")]) 810: 811: (define_expand "udivsi3" 812: [(set (match_dup 3) 813: (zero_extend:DI (match_operand:SI 1 "register_operand" ""))) 814: (set (match_dup 4) 815: (zero_extend:DI (match_operand:SI 2 "register_operand" ""))) 816: (set (match_dup 3) 817: (div:DI (match_dup 3) (match_dup 4))) 818: (set (match_operand:SI 0 "register_operand" "") 819: (subreg:SI (match_dup 3) 0))] 820: "" 821: "operands[3] = gen_reg_rtx (DImode); 822: operands[4] = gen_reg_rtx (DImode); ") 823: 824: (define_insn "udivdi3" 825: [(set (match_operand:DI 0 "register_operand" "=d") 826: (udiv:DI (match_operand:DI 1 "register_operand" "d") 827: (match_operand:DI 2 "register_operand" "d")))] 828: "" 829: "psh.l %2\;psh.l %1\;callq udiv64\;pop.l %0\;add.w #8,sp") 830: 831: (define_insn "divsi3" 832: [(set (match_operand:SI 0 "register_operand" "=d,a") 833: (div:SI (match_operand:SI 1 "register_operand" "0,0") 834: (match_operand:SI 2 "nonmemory_operand" "di,ai")))] 835: "" 836: "div.w %2,%0" 837: [(set_attr "type" "divw")]) 838: 839: (define_insn "divhi3" 840: [(set (match_operand:HI 0 "register_operand" "=d,a") 841: (div:HI (match_operand:HI 1 "register_operand" "0,0") 842: (match_operand:HI 2 "nonmemory_operand" "di,ai")))] 843: "" 844: "div.h %2,%0" 845: [(set_attr "type" "divw")]) 846: 847: (define_insn "divqi3" 848: [(set (match_operand:QI 0 "register_operand" "=d") 849: (div:QI (match_operand:QI 1 "register_operand" "0") 850: (match_operand:QI 2 "register_operand" "d")))] 851: "" 852: "div.b %2,%0" 853: [(set_attr "type" "divw")]) 854: 855: ;;- Bit clear instructions. 856: 857: (define_insn "" 858: [(set (match_operand:DI 0 "register_operand" "=d") 859: (and:DI (match_operand:DI 1 "register_operand" "%0") 860: (match_operand:DI 2 "" "")))] 861: "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) 862: || (GET_CODE (operands[2]) == CONST_DOUBLE 863: && CONST_DOUBLE_HIGH (operands[2]) == -1)" 864: "and %2,%0") 865: 866: (define_insn "anddi3" 867: [(set (match_operand:DI 0 "register_operand" "=d") 868: (and:DI (match_operand:DI 1 "register_operand" "%0") 869: (match_operand:DI 2 "register_operand" "d")))] 870: "" 871: "and %2,%0") 872: 873: (define_insn "andsi3" 874: [(set (match_operand:SI 0 "register_operand" "=d,a") 875: (and:SI (match_operand:SI 1 "register_operand" "%0,0") 876: (match_operand:SI 2 "nonmemory_operand" "di,ai")))] 877: "" 878: "and %2,%0") 879: 880: (define_insn "andhi3" 881: [(set (match_operand:HI 0 "register_operand" "=d,a") 882: (and:HI (match_operand:HI 1 "register_operand" "%0,0") 883: (match_operand:HI 2 "nonmemory_operand" "di,ai")))] 884: "" 885: "and %2,%0") 886: 887: (define_insn "andqi3" 888: [(set (match_operand:QI 0 "register_operand" "=d,a") 889: (and:QI (match_operand:QI 1 "register_operand" "%0,0") 890: (match_operand:QI 2 "nonmemory_operand" "di,ai")))] 891: "" 892: "and %2,%0") 893: 894: ;;- Bit set instructions. 895: 896: (define_insn "" 897: [(set (match_operand:DI 0 "register_operand" "=d") 898: (ior:DI (match_operand:DI 1 "register_operand" "%0") 899: (match_operand:DI 2 "" "")))] 900: "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0) 901: || (GET_CODE (operands[2]) == CONST_DOUBLE 902: && CONST_DOUBLE_HIGH (operands[2]) == 0)" 903: "or %2,%0") 904: 905: (define_insn "iordi3" 906: [(set (match_operand:DI 0 "register_operand" "=d") 907: (ior:DI (match_operand:DI 1 "register_operand" "%0") 908: (match_operand:DI 2 "register_operand" "d")))] 909: "" 910: "or %2,%0") 911: 912: (define_insn "iorsi3" 913: [(set (match_operand:SI 0 "register_operand" "=d,a") 914: (ior:SI (match_operand:SI 1 "register_operand" "%0,0") 915: (match_operand:SI 2 "nonmemory_operand" "di,ai")))] 916: "" 917: "or %2,%0") 918: 919: (define_insn "iorhi3" 920: [(set (match_operand:HI 0 "register_operand" "=d,a") 921: (ior:HI (match_operand:HI 1 "register_operand" "%0,0") 922: (match_operand:HI 2 "nonmemory_operand" "di,ai")))] 923: "" 924: "or %2,%0") 925: 926: (define_insn "iorqi3" 927: [(set (match_operand:QI 0 "register_operand" "=d,a") 928: (ior:QI (match_operand:QI 1 "register_operand" "%0,0") 929: (match_operand:QI 2 "nonmemory_operand" "di,ai")))] 930: "" 931: "or %2,%0") 932: 933: ;;- xor instructions. 934: 935: (define_insn "" 936: [(set (match_operand:DI 0 "register_operand" "=d") 937: (xor:DI (match_operand:DI 1 "register_operand" "%0") 938: (match_operand:DI 2 "" "")))] 939: "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0) 940: || (GET_CODE (operands[2]) == CONST_DOUBLE 941: && CONST_DOUBLE_HIGH (operands[2]) == 0)" 942: "xor %2,%0") 943: 944: (define_insn "xordi3" 945: [(set (match_operand:DI 0 "register_operand" "=d") 946: (xor:DI (match_operand:DI 1 "register_operand" "%0") 947: (match_operand:DI 2 "register_operand" "d")))] 948: "" 949: "xor %2,%0") 950: 951: (define_insn "xorsi3" 952: [(set (match_operand:SI 0 "register_operand" "=d,a") 953: (xor:SI (match_operand:SI 1 "register_operand" "%0,0") 954: (match_operand:SI 2 "nonmemory_operand" "di,ai")))] 955: "" 956: "xor %2,%0") 957: 958: (define_insn "xorhi3" 959: [(set (match_operand:HI 0 "register_operand" "=d,a") 960: (xor:HI (match_operand:HI 1 "register_operand" "%0,0") 961: (match_operand:HI 2 "nonmemory_operand" "di,ai")))] 962: "" 963: "xor %2,%0") 964: 965: (define_insn "xorqi3" 966: [(set (match_operand:QI 0 "register_operand" "=d,a") 967: (xor:QI (match_operand:QI 1 "register_operand" "%0,0") 968: (match_operand:QI 2 "nonmemory_operand" "di,ai")))] 969: "" 970: "xor %2,%0") 971: 972: (define_insn "negdf2" 973: [(set (match_operand:DF 0 "register_operand" "=d") 974: (neg:DF (match_operand:DF 1 "register_operand" "d")))] 975: "" 976: "neg.d %1,%0" 977: [(set_attr "type" "addd")]) 978: 979: (define_insn "negsf2" 980: [(set (match_operand:SF 0 "register_operand" "=d") 981: (neg:SF (match_operand:SF 1 "register_operand" "d")))] 982: "" 983: "neg.s %1,%0" 984: [(set_attr "type" "adds")]) 985: 986: (define_insn "negdi2" 987: [(set (match_operand:DI 0 "register_operand" "=d") 988: (neg:DI (match_operand:DI 1 "register_operand" "d")))] 989: "" 990: "neg.l %1,%0") 991: 992: (define_insn "negsi2" 993: [(set (match_operand:SI 0 "register_operand" "=d,a") 994: (neg:SI (match_operand:SI 1 "register_operand" "d,a")))] 995: "" 996: "neg.w %1,%0") 997: 998: (define_insn "neghi2" 999: [(set (match_operand:HI 0 "register_operand" "=d,a") 1000: (neg:HI (match_operand:HI 1 "register_operand" "d,a")))] 1001: "" 1002: "neg.h %1,%0") 1003: 1004: (define_insn "negqi2" 1005: [(set (match_operand:QI 0 "register_operand" "=d") 1006: (neg:QI (match_operand:QI 1 "register_operand" "d")))] 1007: "" 1008: "neg.b %1,%0") 1009: 1010: (define_insn "one_cmpldi2" 1011: [(set (match_operand:DI 0 "register_operand" "=d") 1012: (not:DI (match_operand:DI 1 "register_operand" "d")))] 1013: "" 1014: "not %1,%0") 1015: 1016: (define_insn "one_cmplsi2" 1017: [(set (match_operand:SI 0 "register_operand" "=d,a") 1018: (not:SI (match_operand:SI 1 "register_operand" "d,a")))] 1019: "" 1020: "not %1,%0") 1021: 1022: (define_insn "one_cmplhi2" 1023: [(set (match_operand:HI 0 "register_operand" "=d,a") 1024: (not:HI (match_operand:HI 1 "register_operand" "d,a")))] 1025: "" 1026: "not %1,%0") 1027: 1028: (define_insn "one_cmplqi2" 1029: [(set (match_operand:QI 0 "register_operand" "=d,a") 1030: (not:QI (match_operand:QI 1 "register_operand" "d,a")))] 1031: "" 1032: "not %1,%0") 1033: 1034: ;;- Shifts 1035: ;; 1036: ;; The extreme profusion of patterns here is due to the different-speed 1037: ;; shifts on different machines, and the C1's lack of word shift S-register 1038: ;; instructions. 1039: 1040: ;; SImode 1041: 1042: ;; Arithmetic left 1, 1 cycle on all machines via add 1043: 1044: (define_insn "" 1045: [(set (match_operand:SI 0 "register_operand" "=r") 1046: (ashift:SI (match_operand:SI 1 "register_operand" "0") 1047: (const_int 1)))] 1048: "" 1049: "add.w %0,%0") 1050: 1051: ;; C34 general shift is 1 cycle 1052: 1053: (define_insn "" 1054: [(set (match_operand:SI 0 "register_operand" "=d,a") 1055: (ashift:SI (match_operand:SI 1 "register_operand" "0,0") 1056: (match_operand:SI 2 "nonmemory_operand" "di,ai")))] 1057: "TARGET_C34" 1058: "@ 1059: shf.w %2,%0 1060: shf %2,%0" 1061: [(set_attr "type" "shfw,shfw")]) 1062: 1063: ;; else shift left 0..7 is 1 cycle if we use an A register 1064: 1065: (define_insn "" 1066: [(set (match_operand:SI 0 "register_operand" "=a,?d") 1067: (ashift:SI (match_operand:SI 1 "register_operand" "0,0") 1068: (match_operand:SI 2 "immediate_operand" "ai,di")))] 1069: "TARGET_C1 && INTVAL (operands[2]) < (unsigned) 8" 1070: "@ 1071: shf %2,%0 1072: shf %2,%0" 1073: [(set_attr "type" "alu,shfl")]) 1074: 1075: (define_insn "" 1076: [(set (match_operand:SI 0 "register_operand" "=a,?d") 1077: (ashift:SI (match_operand:SI 1 "register_operand" "0,0") 1078: (match_operand:SI 2 "immediate_operand" "ai,di")))] 1079: "INTVAL (operands[2]) < (unsigned) 8" 1080: "@ 1081: shf %2,%0 1082: shf.w %2,%0" 1083: [(set_attr "type" "alu,shfw")]) 1084: 1085: ;; else general left shift 1086: 1087: (define_insn "" 1088: [(set (match_operand:SI 0 "register_operand" "=d,a") 1089: (ashift:SI (match_operand:SI 1 "register_operand" "0,0") 1090: (match_operand:SI 2 "nonmemory_operand" "di,ai")))] 1091: "TARGET_C1" 1092: "@ 1093: shf %2,%0 1094: shf %2,%0" 1095: [(set_attr "type" "shfl,shfw")]) 1096: 1.1.1.3 ! root 1097: ;; but C2 left shift by a constant is faster via multiply ! 1098: 1.1 root 1099: (define_insn "" 1100: [(set (match_operand:SI 0 "register_operand" "=r") 1101: (ashift:SI (match_operand:SI 1 "register_operand" "0") 1102: (match_operand:SI 2 "const_int_operand" "i")))] 1103: "TARGET_C2 && INTVAL (operands[2]) < (unsigned) 32" 1104: "mul.w %z2,%0" 1105: [(set_attr "type" "mulw")]) 1106: 1107: (define_insn "ashlsi3" 1108: [(set (match_operand:SI 0 "register_operand" "=d,a") 1109: (ashift:SI (match_operand:SI 1 "register_operand" "0,0") 1110: (match_operand:SI 2 "nonmemory_operand" "di,ai")))] 1111: "" 1112: "@ 1113: shf.w %2,%0 1114: shf %2,%0" 1115: [(set_attr "type" "shfw,shfw")]) 1116: 1117: ;; Logical right, general 1118: ;; The hardware wants the negative of the shift count 1119: 1120: (define_expand "lshrsi3" 1121: [(set (match_operand:SI 0 "register_operand" "") 1122: (lshiftrt:SI (match_operand:SI 1 "register_operand" "") 1123: (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))] 1124: "" 1125: "operands[2] = negate_rtx (SImode, operands[2]);") 1126: 1127: ;; C1 lacks word shift S reg 1128: 1129: (define_insn "" 1130: [(set 1131: (match_operand:SI 0 "register_operand" "=a,?d") 1132: (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0") 1133: (neg:SI (match_operand:SI 2 "nonmemory_operand" "ai,di"))))] 1134: "TARGET_C1" 1135: "@ 1136: shf %2,%0 1137: ld.u #0,%0\;shf %2,%0" 1138: [(set_attr "type" "shfw,shfl")]) 1139: 1140: ;; general case 1141: 1142: (define_insn "" 1143: [(set 1144: (match_operand:SI 0 "register_operand" "=d,a") 1145: (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0") 1146: (neg:SI (match_operand:SI 2 "nonmemory_operand" "di,ai"))))] 1147: "" 1148: "@ 1149: shf.w %2,%0 1150: shf %2,%0" 1151: [(set_attr "type" "shfw,shfw")]) 1152: 1153: ;; Patterns without neg produced by constant folding 1154: 1155: (define_insn "" 1156: [(set 1157: (match_operand:SI 0 "register_operand" "=a,?d") 1158: (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0") 1159: (match_operand:SI 2 "immediate_operand" "i,i")))] 1160: "TARGET_C1" 1161: "@ 1162: shf #%n2,%0 1163: ld.u #0,%0\;shf #%n2,%0" 1164: [(set_attr "type" "shfw,shfl")]) 1165: 1166: (define_insn "" 1167: [(set 1168: (match_operand:SI 0 "register_operand" "=d,a") 1169: (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0") 1170: (match_operand:SI 2 "immediate_operand" "i,i")))] 1171: "" 1172: "@ 1173: shf.w #%n2,%0 1174: shf #%n2,%0" 1175: [(set_attr "type" "shfw,shfw")]) 1176: 1177: ;; Arithmetic right, general 1178: ;; Sign-extend to 64 bits, then shift that. Works for 0..32. 1179: 1180: (define_expand "ashrsi3" 1181: [(set (match_operand:SI 0 "register_operand" "") 1182: (ashiftrt:SI (match_operand:SI 1 "register_operand" "") 1183: (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))] 1184: "" 1185: "operands[2] = negate_rtx (SImode, operands[2]);") 1186: 1187: (define_insn "" 1188: [(set (match_operand:SI 0 "register_operand" "=d,&d") 1189: (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d") 1190: (neg:SI 1191: (match_operand:SI 2 "nonmemory_operand" "di,di"))))] 1192: "" 1193: "cvtw.l %1,%0\;shf %2,%0" 1194: [(set_attr "type" "shfl,shfl")]) 1195: 1196: (define_insn "" 1197: [(set (match_operand:SI 0 "register_operand" "=d") 1198: (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") 1199: (match_operand:SI 2 "immediate_operand" "i")))] 1200: "" 1201: "cvtw.l %1,%0\;shf #%n2,%0" 1202: [(set_attr "type" "shfl")]) 1203: 1204: ;; DImode 1205: ;; Arithmetic left, 1-cycle 1206: 1207: (define_insn "" 1208: [(set (match_operand:DI 0 "register_operand" "=d") 1209: (ashift:DI (match_operand:DI 1 "register_operand" "0") 1210: (const_int 1)))] 1211: "" 1212: "add.l %0,%0") 1213: 1214: ;; Arithmetic left, general 1215: 1216: (define_insn "ashldi3" 1217: [(set (match_operand:DI 0 "register_operand" "=d") 1218: (ashift:DI (match_operand:DI 1 "register_operand" "0") 1219: (match_operand:SI 2 "nonmemory_operand" "di")))] 1220: "" 1221: "shf %2,%0" 1222: [(set_attr "type" "shfl")]) 1223: 1224: ;; Can omit zero- or sign-extend if shift is 32 or more. 1225: 1226: (define_insn "" 1227: [(set (match_operand:DI 0 "register_operand" "=d") 1228: (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0")) 1229: (match_operand:SI 2 "const_int_operand" "i")))] 1230: "INTVAL (operands[2]) >= 32" 1231: "shf %2,%0" 1232: [(set_attr "type" "shfl")]) 1233: 1234: (define_insn "" 1235: [(set (match_operand:DI 0 "register_operand" "=d") 1236: (ashift:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "0")) 1237: (match_operand:SI 2 "const_int_operand" "i")))] 1238: "INTVAL (operands[2]) >= 32" 1239: "shf %2,%0" 1240: [(set_attr "type" "shfl")]) 1241: 1242: ;; Logical right, general 1243: 1244: (define_expand "lshrdi3" 1245: [(set (match_operand:DI 0 "register_operand" "") 1246: (lshiftrt:DI (match_operand:DI 1 "register_operand" "") 1247: (neg:SI (match_operand:SI 2 "nonmemory_operand" ""))))] 1248: "" 1249: "operands[2] = negate_rtx (SImode, operands[2]);") 1250: 1251: (define_insn "" 1252: [(set (match_operand:DI 0 "register_operand" "=d") 1253: (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") 1254: (neg:SI (match_operand:SI 2 "nonmemory_operand" "di"))))] 1255: "" 1256: "shf %2,%0" 1257: [(set_attr "type" "shfl")]) 1258: 1259: (define_insn "" 1260: [(set (match_operand:DI 0 "register_operand" "=d") 1261: (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") 1262: (match_operand:SI 2 "immediate_operand" "i")))] 1263: "" 1264: "shf #%n2,%0" 1265: [(set_attr "type" "shfl")]) 1266: 1267: ;; Arithmetic right, general 1268: ;; Use 1269: ;; ((a >> b) ^ signbit) - signbit 1270: ;; where signbit is (1 << 63) >> b 1271: ;; Works for 0..63. Does not work for 64; unfortunate but legal. 1272: 1273: (define_expand "ashrdi3" 1274: [(set (match_operand:DI 0 "register_operand" "") 1275: (lshiftrt:DI (match_operand:DI 1 "register_operand" "") 1276: (neg:SI (match_operand:SI 2 "nonmemory_operand" "")))) 1277: (set (match_dup 3) (lshiftrt:DI (match_dup 3) (neg:SI (match_dup 2)))) 1278: (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 3))) 1279: (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 3)))] 1280: "" 1281: " 1282: { 1283: if (GET_CODE (operands[2]) == CONST_INT) 1284: switch (INTVAL (operands[2])) 1285: { 1286: case 32: 1287: emit_insn (gen_ashrdi3_32 (operands[0], operands[1])); 1288: DONE; 1289: } 1290: 1291: operands[2] = negate_rtx (SImode, operands[2]); 1292: operands[3] = force_reg (DImode, immed_double_const (0, 1 << 31, DImode)); 1293: }") 1294: 1295: ;; Arithmetic right 32, a common case that can save a couple of insns. 1296: 1297: (define_expand "ashrdi3_32" 1298: [(set (match_operand:DI 0 "register_operand" "") 1299: (lshiftrt:DI (match_operand:DI 1 "register_operand" "") 1300: (const_int 32))) 1301: (set (match_dup 0) 1302: (sign_extend:DI (subreg:SI (match_dup 0) 0)))] 1303: "" 1304: "") 1305: 1306: ;; __builtin instructions 1307: 1308: (define_insn "sqrtdf2" 1309: [(set (match_operand:DF 0 "register_operand" "=d") 1310: (sqrt:DF (match_operand:DF 1 "register_operand" "0")))] 1311: "! TARGET_C1 && flag_fast_math" 1312: "sqrt.d %0" 1313: [(set_attr "type" "divd")]) 1314: 1315: (define_insn "sqrtsf2" 1316: [(set (match_operand:SF 0 "register_operand" "=d") 1317: (sqrt:SF (match_operand:SF 1 "register_operand" "0")))] 1318: "! TARGET_C1 && flag_fast_math" 1319: "sqrt.s %0" 1320: [(set_attr "type" "divs")]) 1321: 1322: (define_insn "sindf2" 1323: [(set (match_operand:DF 0 "register_operand" "=d") 1324: (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))] 1325: "! TARGET_C1 && flag_fast_math" 1326: "sin.d %0") 1327: 1328: (define_insn "sinsf2" 1329: [(set (match_operand:SF 0 "register_operand" "=d") 1330: (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))] 1331: "! TARGET_C1 && flag_fast_math" 1332: "sin.s %0") 1333: 1334: (define_insn "cosdf2" 1335: [(set (match_operand:DF 0 "register_operand" "=d") 1336: (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))] 1337: "! TARGET_C1 && flag_fast_math" 1338: "cos.d %0") 1339: 1340: (define_insn "cossf2" 1341: [(set (match_operand:SF 0 "register_operand" "=d") 1342: (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))] 1343: "! TARGET_C1 && flag_fast_math" 1344: "cos.s %0") 1345: 1346: (define_insn "ftruncdf2" 1347: [(set (match_operand:DF 0 "register_operand" "=d") 1348: (fix:DF (match_operand:DF 1 "register_operand" "d")))] 1349: "! TARGET_C1" 1350: "frint.d %1,%0" 1351: [(set_attr "type" "cvtd")]) 1352: 1353: (define_insn "ftruncsf2" 1354: [(set (match_operand:SF 0 "register_operand" "=d") 1355: (fix:SF (match_operand:SF 1 "register_operand" "d")))] 1356: "! TARGET_C1" 1357: "frint.s %1,%0" 1358: [(set_attr "type" "cvts")]) 1359: 1360: (define_insn "" 1361: [(set (match_operand:SI 0 "register_operand" "=d") 1362: (minus:SI (ffs:SI (match_operand:SI 1 "register_operand" "d")) 1363: (const_int 1)))] 1364: "" 1365: "tzc %1,%0\;le.w #32,%0\;jbrs.f L0%=\;ld.w #-1,%0\\nL0%=:") 1366: 1367: (define_expand "ffssi2" 1368: [(set (match_operand:SI 0 "register_operand" "=d") 1369: (minus:SI (ffs:SI (match_operand:SI 1 "register_operand" "d")) 1370: (const_int 1))) 1371: (set (match_dup 0) 1372: (plus:SI (match_dup 0) 1373: (const_int 1)))] 1374: "" 1375: "") 1376: 1377: (define_insn "abssf2" 1378: [(set (match_operand:SF 0 "register_operand" "=d") 1379: (abs:SF (match_operand:SF 1 "register_operand" "0")))] 1380: "" 1381: "and #0x7fffffff,%0") 1382: 1383: (define_expand "absdf2" 1384: [(set (subreg:DI (match_operand:DF 0 "register_operand" "=d") 0) 1385: (and:DI (subreg:DI (match_operand:DF 1 "register_operand" "d") 0) 1386: (match_dup 2)))] 1387: "" 1388: "operands[2] = force_reg (DImode, 1389: immed_double_const (-1, 0x7fffffff, DImode));") 1390: 1391: ;;- Compares 1392: 1393: (define_insn "cmpdi" 1394: [(set (cc0) 1395: (compare (match_operand:DI 0 "register_operand" "d") 1396: (match_operand:DI 1 "register_operand" "d")))] 1397: "" 1398: "* return output_cmp (operands[0], operands[1], 'l');") 1399: 1400: (define_insn "" 1401: [(set (cc0) (match_operand:DI 0 "register_operand" "d")) 1402: (clobber (match_scratch:DI 1 "=d"))] 1403: "next_insn_tests_no_inequality (insn)" 1404: "* return output_cmp (operands[0], operands[1], 'L');") 1405: 1406: (define_insn "cmpsi" 1407: [(set (cc0) 1408: (compare (match_operand:SI 0 "register_operand" "d,a") 1409: (match_operand:SI 1 "nonmemory_operand" "di,ai")))] 1410: "" 1411: "* return output_cmp (operands[0], operands[1], 'w');") 1412: 1413: (define_insn "cmphi" 1414: [(set (cc0) 1415: (compare (match_operand:HI 0 "register_operand" "d,a") 1416: (match_operand:HI 1 "nonmemory_operand" "di,ai")))] 1417: "" 1418: "* return output_cmp (operands[0], operands[1], 'h');") 1419: 1420: ; cmpqi is intentionally omitted. 1421: ; 1422: ; gcc will sign-extend or zero-extend the operands to the next 1423: ; wider mode, HImode. 1424: ; 1425: ; For reg .cmp. constant, we just go with the halfword immediate 1426: ; instruction. Perhaps the widening insn can be cse'd or combined away. 1427: ; If not, we're still as good as loading a byte constant into a register 1428: ; to do a reg-reg byte compare. 1429: ; 1430: ; The following patterns pick up cases that can use reg .cmp. reg after all. 1431: 1432: (define_insn "" 1433: [(set (cc0) 1434: (compare 1435: (sign_extend:HI (match_operand:QI 0 "register_operand" "d")) 1436: (sign_extend:HI (match_operand:QI 1 "register_operand" "d"))))] 1437: "" 1438: "* return output_cmp (operands[0], operands[1], 'b');") 1439: 1440: (define_insn "" 1441: [(set (cc0) 1442: (compare 1443: (ashift:HI (subreg:HI (match_operand:QI 0 "register_operand" "d") 0) 1444: (const_int 8)) 1445: (ashift:HI (subreg:HI (match_operand:QI 1 "register_operand" "d") 0) 1446: (const_int 8))))] 1447: "" 1448: "* return output_cmp (operands[0], operands[1], 'b');") 1449: 1450: (define_insn "" 1451: [(set (cc0) 1452: (compare (match_operand:QI 0 "register_operand" "d") 1453: (match_operand:QI 1 "register_operand" "d")))] 1454: "" 1455: "* return output_cmp (operands[0], operands[1], 'b');") 1456: 1457: (define_insn "" 1.1.1.3 ! root 1458: [(set (cc0) (match_operand:QI 0 "register_operand" "d")) ! 1459: (clobber (match_scratch:QI 1 "=d"))] 1.1 root 1460: "next_insn_tests_no_inequality (insn)" 1461: "* return output_cmp (operands[0], operands[1], 'B');") 1462: 1463: (define_insn "" 1.1.1.3 ! root 1464: [(set (cc0) (subreg (match_operand:QI 0 "register_operand" "d") 0)) ! 1465: (clobber (match_scratch:QI 1 "=d"))] 1.1 root 1466: "next_insn_tests_no_inequality (insn)" 1467: "* return output_cmp (operands[0], operands[1], 'B');") 1468: 1469: (define_insn "" 1470: [(set (cc0) 1.1.1.3 ! root 1471: (zero_extend (subreg (match_operand:QI 0 "register_operand" "d") 0))) ! 1472: (clobber (match_scratch:QI 1 "=d"))] 1.1 root 1473: "next_insn_tests_no_inequality (insn)" 1474: "* return output_cmp (operands[0], operands[1], 'B');") 1475: 1476: (define_insn "cmpdf" 1477: [(set (cc0) 1478: (compare (match_operand:DF 0 "register_operand" "d") 1479: (match_operand:DF 1 "register_operand" "d")))] 1480: "" 1481: "* return output_cmp (operands[0], operands[1], 'd');") 1482: 1483: (define_insn "cmpsf" 1484: [(set (cc0) 1485: (compare (match_operand:SF 0 "register_operand" "d") 1486: (match_operand:SF 1 "nonmemory_cmpsf_operand" "dF")))] 1487: "" 1488: "* return output_cmp (operands[0], operands[1], 's');") 1489: 1490: ;; decrement-and-set-cc0 insns. 1491: ;; 1492: ;; The most important case where we can use the carry bit from an 1493: ;; arithmetic insn to eliminate a redundant compare is the decrement in 1494: ;; constructs like while (n--) and while (--n >= 0). 1495: ;; 1496: ;; We do it with combine patterns instead of NOTICE_UPDATE_CC because 1497: ;; the decrement needs to be kept at the end of the block during scheduling. 1498: ;; 1499: ;; These patterns must have memory alternatives because reload refuses 1500: ;; to do output reloads for an insn that sets cc0 (since it does not 1501: ;; want to clobber cc0 with its moves). Convex moves do not clobber 1502: ;; cc0, but there is no evident way to get reload to know that. 1503: 1504: (define_insn "" 1505: [(set (cc0) 1506: (match_operand:SI 0 "register_operand" "+r,*m")) 1507: (set (match_dup 0) 1508: (plus:SI (match_dup 0) 1509: (const_int -1)))] 1510: "next_insn_tests_no_inequality (insn)" 1511: "* 1512: { 1513: if (which_alternative == 0) 1514: { 1515: output_cmp (operands[0], constm1_rtx, 'W'); 1516: return \"add.w #-1,%0\"; 1517: } 1518: else 1519: { 1520: output_cmp (gen_rtx (REG, SImode, 7), constm1_rtx, 'W'); 1521: return \"psh.w s7\;ld.w %0,s7\;add.w #-1,s7\;st.w s7,%0\;pop.w s7\"; 1522: } 1523: }") 1524: 1525: (define_insn "" 1526: [(set (cc0) 1527: (plus:SI (match_operand:SI 0 "register_operand" "+r,*m") 1528: (const_int -1))) 1529: (set (match_dup 0) 1530: (plus:SI (match_dup 0) 1531: (const_int -1)))] 1532: "find_reg_note (next_cc0_user (insn), REG_NONNEG, 0)" 1533: "* 1534: { 1535: if (which_alternative == 0) 1536: { 1537: output_cmp (operands[0], const0_rtx, 'W'); 1538: return \"add.w #-1,%0\"; 1539: } 1540: else 1541: { 1542: output_cmp (gen_rtx (REG, SImode, 7), const0_rtx, 'W'); 1543: return \"psh.w s7\;ld.w %0,s7\;add.w #-1,s7\;st.w s7,%0\;pop.w s7\"; 1544: } 1545: }") 1546: 1547: (define_insn "" 1548: [(set (cc0) 1549: (match_operand:HI 0 "register_operand" "+r,*m")) 1550: (set (match_dup 0) 1551: (plus:HI (match_dup 0) 1552: (const_int -1)))] 1553: "next_insn_tests_no_inequality (insn)" 1554: "* 1555: { 1556: if (which_alternative == 0) 1557: { 1.1.1.3 ! root 1558: output_cmp (operands[0], constm1_rtx, 'H'); ! 1559: return \"add.h #-1,%0\"; 1.1 root 1560: } 1561: else 1562: { 1.1.1.3 ! root 1563: output_cmp (gen_rtx (REG, HImode, 7), constm1_rtx, 'H'); 1.1 root 1564: return \"psh.w s7\;ld.h %0,s7\;add.h #-1,s7\;st.h s7,%0\;pop.w s7\"; 1565: } 1566: }") 1567: 1568: (define_insn "" 1569: [(set (cc0) 1570: (plus:HI (match_operand:HI 0 "register_operand" "+r,*m") 1571: (const_int -1))) 1572: (set (match_dup 0) 1573: (plus:HI (match_dup 0) 1574: (const_int -1)))] 1575: "find_reg_note (next_cc0_user (insn), REG_NONNEG, 0)" 1576: "* 1577: { 1578: if (which_alternative == 0) 1579: { 1.1.1.3 ! root 1580: output_cmp (operands[0], const0_rtx, 'H'); ! 1581: return \"add.h #-1,%0\"; 1.1 root 1582: } 1583: else 1584: { 1.1.1.3 ! root 1585: output_cmp (gen_rtx (REG, HImode, 7), const0_rtx, 'H'); 1.1 root 1586: return \"psh.w s7\;ld.h %0,s7\;add.h #-1,s7\;st.h s7,%0\;pop.w s7\"; 1587: } 1588: }") 1589: 1590: ;;- Jumps 1591: 1592: (define_insn "jump" 1593: [(set (pc) 1594: (label_ref (match_operand 0 "" "")))] 1595: "" 1596: "jbr %l0") 1597: 1598: (define_insn "beq" 1599: [(set (pc) 1600: (if_then_else (eq (cc0) 1601: (const_int 0)) 1602: (label_ref (match_operand 0 "" "")) 1603: (pc)))] 1604: "" 1605: "* return output_condjump (operands[0], \"eq\", 't'); ") 1606: 1607: (define_insn "bne" 1608: [(set (pc) 1609: (if_then_else (ne (cc0) 1610: (const_int 0)) 1611: (label_ref (match_operand 0 "" "")) 1612: (pc)))] 1613: "" 1614: "* return output_condjump (operands[0], \"eq\", 'f'); ") 1615: 1616: (define_insn "bgt" 1617: [(set (pc) 1618: (if_then_else (gt (cc0) 1619: (const_int 0)) 1620: (label_ref (match_operand 0 "" "")) 1621: (pc)))] 1622: "" 1623: "* return output_condjump (operands[0], \"le\", 'f'); ") 1624: 1625: (define_insn "bgtu" 1626: [(set (pc) 1627: (if_then_else (gtu (cc0) 1628: (const_int 0)) 1629: (label_ref (match_operand 0 "" "")) 1630: (pc)))] 1631: "" 1632: "* return output_condjump (operands[0], \"leu\", 'f'); ") 1633: 1634: (define_insn "blt" 1635: [(set (pc) 1636: (if_then_else (lt (cc0) 1637: (const_int 0)) 1638: (label_ref (match_operand 0 "" "")) 1639: (pc)))] 1640: "" 1641: "* return output_condjump (operands[0], \"lt\", 't'); ") 1642: 1643: (define_insn "bltu" 1644: [(set (pc) 1645: (if_then_else (ltu (cc0) 1646: (const_int 0)) 1647: (label_ref (match_operand 0 "" "")) 1648: (pc)))] 1649: "" 1650: "* return output_condjump (operands[0], \"ltu\", 't'); ") 1651: 1652: (define_insn "bge" 1653: [(set (pc) 1654: (if_then_else (ge (cc0) 1655: (const_int 0)) 1656: (label_ref (match_operand 0 "" "")) 1657: (pc)))] 1658: "" 1659: "* return output_condjump (operands[0], \"lt\", 'f'); ") 1660: 1661: (define_insn "bgeu" 1662: [(set (pc) 1663: (if_then_else (geu (cc0) 1664: (const_int 0)) 1665: (label_ref (match_operand 0 "" "")) 1666: (pc)))] 1667: "" 1668: "* return output_condjump (operands[0], \"ltu\", 'f'); ") 1669: 1670: (define_insn "ble" 1671: [(set (pc) 1672: (if_then_else (le (cc0) 1673: (const_int 0)) 1674: (label_ref (match_operand 0 "" "")) 1675: (pc)))] 1676: "" 1677: "* return output_condjump (operands[0], \"le\", 't'); ") 1678: 1679: (define_insn "bleu" 1680: [(set (pc) 1681: (if_then_else (leu (cc0) 1682: (const_int 0)) 1683: (label_ref (match_operand 0 "" "")) 1684: (pc)))] 1685: "" 1686: "* return output_condjump (operands[0], \"leu\", 't'); ") 1687: 1688: (define_insn "" 1689: [(set (pc) 1690: (if_then_else (eq (cc0) 1691: (const_int 0)) 1692: (pc) 1693: (label_ref (match_operand 0 "" ""))))] 1694: "" 1695: "* return output_condjump (operands[0], \"eq\", 'f'); ") 1696: 1697: (define_insn "" 1698: [(set (pc) 1699: (if_then_else (ne (cc0) 1700: (const_int 0)) 1701: (pc) 1702: (label_ref (match_operand 0 "" ""))))] 1703: "" 1704: "* return output_condjump (operands[0], \"eq\", 't'); ") 1705: 1706: (define_insn "" 1707: [(set (pc) 1708: (if_then_else (gt (cc0) 1709: (const_int 0)) 1710: (pc) 1711: (label_ref (match_operand 0 "" ""))))] 1712: "" 1713: "* return output_condjump (operands[0], \"le\", 't'); ") 1714: 1715: (define_insn "" 1716: [(set (pc) 1717: (if_then_else (gtu (cc0) 1718: (const_int 0)) 1719: (pc) 1720: (label_ref (match_operand 0 "" ""))))] 1721: "" 1722: "* return output_condjump (operands[0], \"leu\", 't'); ") 1723: 1724: (define_insn "" 1725: [(set (pc) 1726: (if_then_else (lt (cc0) 1727: (const_int 0)) 1728: (pc) 1729: (label_ref (match_operand 0 "" ""))))] 1730: "" 1731: "* return output_condjump (operands[0], \"lt\", 'f'); ") 1732: 1733: (define_insn "" 1734: [(set (pc) 1735: (if_then_else (ltu (cc0) 1736: (const_int 0)) 1737: (pc) 1738: (label_ref (match_operand 0 "" ""))))] 1739: "" 1740: "* return output_condjump (operands[0], \"ltu\", 'f'); ") 1741: 1742: (define_insn "" 1743: [(set (pc) 1744: (if_then_else (ge (cc0) 1745: (const_int 0)) 1746: (pc) 1747: (label_ref (match_operand 0 "" ""))))] 1748: "" 1749: "* return output_condjump (operands[0], \"lt\", 't'); ") 1750: 1751: (define_insn "" 1752: [(set (pc) 1753: (if_then_else (geu (cc0) 1754: (const_int 0)) 1755: (pc) 1756: (label_ref (match_operand 0 "" ""))))] 1757: "" 1758: "* return output_condjump (operands[0], \"ltu\", 't'); ") 1759: 1760: (define_insn "" 1761: [(set (pc) 1762: (if_then_else (le (cc0) 1763: (const_int 0)) 1764: (pc) 1765: (label_ref (match_operand 0 "" ""))))] 1766: "" 1767: "* return output_condjump (operands[0], \"le\", 'f'); ") 1768: 1769: (define_insn "" 1770: [(set (pc) 1771: (if_then_else (leu (cc0) 1772: (const_int 0)) 1773: (pc) 1774: (label_ref (match_operand 0 "" ""))))] 1775: "" 1776: "* return output_condjump (operands[0], \"leu\", 'f'); ") 1777: 1778: ;;- Calls 1779: 1780: (define_expand "call_pop" 1781: [(parallel [(call (match_operand:QI 0 "memory_operand" "m") 1782: (match_operand:SI 1 "const_int_operand" "i")) 1783: (match_operand:SI 2 "const_int_operand" "i") 1784: (match_operand:SI 3 "const_int_operand" "i") 1785: (reg:SI 8)])] 1786: "" 1787: "") 1788: 1789: (define_insn "" 1790: [(call (match_operand:QI 0 "memory_operand" "m") 1791: (match_operand:SI 1 "const_int_operand" "i")) 1792: (match_operand:SI 2 "const_int_operand" "i") 1793: (match_operand:SI 3 "const_int_operand" "i") 1794: (match_operand:SI 4 "" "")] 1795: "" 1796: "* return output_call (insn, &operands[0]);") 1797: 1798: (define_expand "call_value_pop" 1799: [(parallel [(set (match_operand 0 "" "=g") 1800: (call (match_operand:QI 1 "memory_operand" "m") 1801: (match_operand:SI 2 "const_int_operand" "i"))) 1802: (match_operand:SI 3 "const_int_operand" "i") 1803: (match_operand:SI 4 "const_int_operand" "i") 1804: (reg:SI 8)])] 1805: "" 1806: "") 1807: 1808: (define_insn "" 1809: [(set (match_operand 0 "" "=g") 1810: (call (match_operand:QI 1 "memory_operand" "m") 1811: (match_operand:SI 2 "const_int_operand" "i"))) 1812: (match_operand:SI 3 "const_int_operand" "i") 1813: (match_operand:SI 4 "const_int_operand" "i") 1814: (match_operand:SI 5 "" "")] 1815: "" 1816: "* return output_call (insn, &operands[1]); ") 1817: 1.1.1.2 root 1818: ;; Call subroutine returning any type. 1819: 1820: (define_expand "untyped_call" 1821: [(parallel [(call (match_operand 0 "" "") 1822: (const_int 0)) 1823: (match_operand 1 "" "") 1824: (match_operand 2 "" "")])] 1825: "" 1826: " 1827: { 1828: int i; 1829: 1830: emit_call_insn (gen_call_pop (operands[0], const0_rtx, 1831: const0_rtx, const0_rtx)); 1832: 1833: for (i = 0; i < XVECLEN (operands[2], 0); i++) 1834: { 1835: rtx set = XVECEXP (operands[2], 0, i); 1836: emit_move_insn (SET_DEST (set), SET_SRC (set)); 1837: } 1838: 1839: /* The optimizer does not know that the call sets the function value 1840: registers we stored in the result block. We avoid problems by 1841: claiming that all hard registers are used and clobbered at this 1842: point. */ 1843: emit_insn (gen_blockage ()); 1844: 1845: DONE; 1846: }") 1847: 1848: ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 1849: ;; all of memory. This blocks insns from being moved across this point. 1850: 1851: (define_insn "blockage" 1852: [(unspec_volatile [(const_int 0)] 0)] 1853: "" 1854: "") 1855: 1.1 root 1856: (define_expand "return" 1857: [(return)] 1858: "" 1859: " replace_arg_pushes (); ") 1860: 1861: (define_insn "" 1862: [(return)] 1863: "" 1864: "rtn") 1865: 1866: (define_expand "prologue" 1867: [(const_int 0)] 1868: "" 1869: " 1870: { 1871: emit_ap_optimizations (); 1872: DONE; 1873: }") 1874: 1875: (define_insn "tablejump" 1876: [(set (pc) (match_operand:SI 0 "address_operand" "p")) 1877: (use (label_ref (match_operand 1 "" "")))] 1878: "" 1879: "jmp %a0") 1880: 1881: (define_insn "indirect_jump" 1882: [(set (pc) (match_operand:SI 0 "address_operand" "p"))] 1883: "" 1884: "jmp %a0")
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