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1.1 root 1: ;;- Machine description for the AT&T DSP1600 for GNU C compiler 1.1.1.2 ! root 2: ;; Copyright (C) 1994, 1995 Free Software Foundation, Inc. 1.1 root 3: ;; Contributed by Michael Collison ([email protected]). 4: 5: ;; This file is part of GNU CC. 6: 7: ;; GNU CC is free software; you can redistribute it and/or modify 8: ;; it under the terms of the GNU General Public License as published by 9: ;; the Free Software Foundation; either version 2, or (at your option) 10: ;; any later version. 11: 12: ;; GNU CC is distributed in the hope that it will be useful, 13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15: ;; GNU General Public License for more details. 16: 17: ;; You should have received a copy of the GNU General Public License 18: ;; along with GNU CC; see the file COPYING. If not, write to 1.1.1.2 ! root 19: ;; the Free Software Foundation, 59 Temple Place - Suite 330, ! 20: ;; Boston, MA 02111-1307, USA. 1.1 root 21: 22: 23: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 24: 25: ;; Attribute specifications 26: 27: ; Type of each instruction. Default is arithmetic. 28: ; I'd like to write the list as this, but genattrtab won't accept it. 29: ; 30: ; "jump,cond_jump,call, ; flow-control instructions 31: ; load_i,load, store, move ; Y space address arithmetic instructions 32: ; malu,special,f3_alu,f3_alu_i ; data arithmetic unit instructions 33: ; shift_i,shift, bfield_i, bfield ; bit manipulation unit instructions 34: ; arith, ; integer unit instructions 35: ; nop 36: 37: ; Classification of each insn. Some insns of TYPE_BRANCH are multi-word. 38: (define_attr "type" 39: "jump,cond_jump,call,load_i,load,move,store,malu,malu_mul,special,f3_alu,f3_alu_i,shift_i,shift,bfield_i,bfield,nop,ld_short_i" 40: (const_string "malu")) 41: 42: ; Length in # of instructions of each insn. The values are not exact, but 43: ; are safe. 44: (define_attr "length" "" 45: (cond [(eq_attr "type" "cond_jump,f3_alu_i,shift_i,bfield_i,load_i") 46: (const_int 2)] 47: (const_int 1))) 48: 49: 50: ;; .................... 51: ;; 52: ;; Test against 0 instructions 53: ;; 54: ;; .................... 55: 56: (define_expand "tsthi" 57: [(set (cc0) 58: (match_operand:HI 0 "register_operand" ""))] 59: "" 60: " 61: { 62: dsp16xx_compare_gen = gen_tst_reg; 63: dsp16xx_compare_op0 = operands[0]; 64: dsp16xx_compare_op1 = const0_rtx; 65: DONE; 66: }") 67: 68: (define_insn "tsthi_1" 69: [(set (cc0) 70: (match_operand:HI 0 "register_operand" "A"))] 71: "" 72: "%0=%0" 73: [(set_attr "type" "malu")]) 74: 75: (define_expand "tstqi" 76: [(set (cc0) 77: (match_operand:QI 0 "register_operand" ""))] 78: "" 79: " 80: { 81: dsp16xx_compare_gen = gen_tst_reg; 82: dsp16xx_compare_op0 = operands[0]; 83: dsp16xx_compare_op1 = const0_rtx; 84: DONE; 85: }") 86: 87: (define_insn "tstqi_1" 88: [(set (cc0) 89: (match_operand:QI 0 "register_operand" "j,q")) 90: (clobber (match_scratch:QI 1 "=k,u"))] 91: "" 92: "@ 93: %1=0\;%b0-0 94: %1=0\;%b0-0" 95: [(set_attr "type" "malu,malu")]) 96: 97: 98: ;; 99: ;; .................... 100: ;; 101: ;; Bit test instructions 102: ;; 103: ;; .................... 104: 105: (define_insn "" 106: [(set (cc0) 107: (and:HI (match_operand:HI 0 "register_operand" "A,!A,A") 108: (match_operand:HI 1 "nonmemory_operand" "Z,A,I")))] 109: "" 110: "* 111: { 112: switch (which_alternative) 113: { 114: case 0: 115: case 1: 116: return \"%0&%1\"; 117: 118: case 2: 119: return \"%0&%H1\"; 120: } 121: }" 122: [(set_attr "type" "f3_alu,malu,f3_alu_i")]) 123: 124: 125: ;;(define_insn "" 126: ;; [(set (cc0) 127: ;; (and:QI (match_operand:QI 0 "register_operand" "h") 128: ;; (match_operand:QI 1 "const_int_operand" "I")))] 129: ;; "" 130: ;; "%b0&%H1" 131: ;; [(set_attr "type" "f3_alu_i")]) 132: 133: ;; 134: ;; 135: ;; Compare Instructions 136: ;; 137: 138: (define_expand "cmphi" 139: [(parallel [(set (cc0) 140: (compare (match_operand:HI 0 "general_operand" "") 141: (match_operand:HI 1 "general_operand" ""))) 142: (clobber (match_scratch:QI 2 "")) 143: (clobber (match_scratch:QI 3 "")) 144: (clobber (match_scratch:QI 4 "")) 145: (clobber (match_scratch:QI 5 ""))])] 146: "" 147: " 148: { 149: if (GET_CODE (operands[1]) == CONST_INT) 150: operands[1] = force_reg (HImode, operands[1]); 151: 152: if (operands[0]) /* Avoid unused code warning */ 153: { 154: dsp16xx_compare_gen = gen_compare_reg; 155: dsp16xx_compare_op0 = operands[0]; 156: dsp16xx_compare_op1 = operands[1]; 157: DONE; 158: } 159: 160: }") 161: 162: (define_insn "" 163: [(set (cc0) 164: (compare (match_operand:HI 0 "general_operand" "Z*r*m*i") 165: (match_operand:HI 1 "general_operand" "Z*r*m*i"))) 166: (clobber (match_scratch:QI 2 "=&A")) 167: (clobber (match_scratch:QI 3 "=&A")) 168: (clobber (match_scratch:QI 4 "=&A")) 169: (clobber (match_scratch:QI 5 "=&A"))] 170: "(save_next_cc_user_code = next_cc_user_code (insn)) == GTU \ 171: || save_next_cc_user_code == GEU \ 172: || save_next_cc_user_code == LTU \ 173: || save_next_cc_user_code == LEU" 174: "* 175: { 176: if (GET_CODE(operands[0]) == REG) 177: { 178: if (REGNO (operands[0]) == REG_Y || 179: REGNO (operands[0]) == REG_PROD) 180: { 181: output_asm_insn (\"a0=%0\", operands); 182: } 183: else if (IS_YBASE_REGISTER_WINDOW (REGNO(operands[0]))) 184: { 185: output_asm_insn (\"a0=%u0\;a0l=%w0\", operands); 186: } 187: else 1.1.1.2 ! root 188: fatal (\"Invalid register for compare\"); 1.1 root 189: } 190: else if (GET_CODE(operands[0]) == CONST_INT) 191: { 192: output_asm_insn (\"a0=%U0\;a0l=%H0\", operands); 193: } 194: else if (GET_CODE (operands[0]) == MEM) 195: { 196: rtx xoperands[2]; 197: 198: xoperands[0] = gen_rtx (REG, HImode, REG_A0); 199: xoperands[1] = operands[0]; 200: double_reg_from_memory (xoperands); 201: } 202: 203: if (GET_CODE(operands[1]) == REG) 204: { 205: if (REGNO (operands[1]) == REG_Y || 206: REGNO (operands[1]) == REG_PROD) 207: { 208: output_asm_insn (\"a1=%1\", operands); 209: } 210: else if (IS_YBASE_REGISTER_WINDOW (REGNO(operands[1]))) 211: { 212: output_asm_insn (\"a1=%u1\;a1l=%w1\", operands); 213: } 214: else 1.1.1.2 ! root 215: fatal (\"Invalid register for compare\"); 1.1 root 216: } 217: else if (GET_CODE (operands[1]) == MEM) 218: { 219: rtx xoperands[2]; 220: 221: xoperands[0] = gen_rtx (REG, HImode, REG_A1); 222: xoperands[1] = operands[1]; 223: double_reg_from_memory (xoperands); 224: } 225: else if (GET_CODE(operands[1]) == CONST_INT) 226: { 227: output_asm_insn (\"a1=%U1\;a1l=%H1\", operands); 228: } 229: 230: return \"psw = 0\;a0 - a1\"; 231: }") 232: 233: (define_insn "" 234: [(set (cc0) (compare (match_operand:HI 0 "register_operand" "A,!A") 235: (match_operand:HI 1 "register_operand" "Z,*A")))] 236: "" 237: "@ 238: %0-%1 239: %0-%1" 240: [(set_attr "type" "malu,f3_alu")]) 241: 242: (define_expand "cmpqi" 243: [(parallel [(set (cc0) 244: (compare (match_operand:QI 0 "register_operand" "") 245: (match_operand:QI 1 "nonmemory_operand" ""))) 246: (clobber (match_operand:QI 2 "register_operand" "")) 247: (clobber (match_operand:QI 3 "register_operand" ""))])] 248: "" 249: " 250: { 251: if (operands[0]) /* Avoid unused code warning */ 252: { 253: dsp16xx_compare_gen = gen_compare_reg; 254: dsp16xx_compare_op0 = operands[0]; 255: dsp16xx_compare_op1 = operands[1]; 256: DONE; 257: } 258: }") 259: 260: (define_insn "" 261: [(set (cc0) (compare (match_operand:QI 0 "register_operand" "k,k,!k,k,u,u,!u,u") 262: (match_operand:QI 1 "nonmemory_operand" "w,z,u,i,w,z,k,i"))) 263: (clobber (match_scratch:QI 2 "=j,j,j,j,q,q,q,q")) 264: (clobber (match_scratch:QI 3 "=v,y,q,X,v,y,j,X"))] 265: "(save_next_cc_user_code = next_cc_user_code (insn)) == GTU \ 266: || save_next_cc_user_code == GEU \ 267: || save_next_cc_user_code == LTU \ 268: || save_next_cc_user_code == LEU" 269: "@ 270: %2=0\;%3=0\;%2-%3 271: %2=0\;%3=0\;%2-%3 272: %2=0\;%3=0\;%2-%3 273: %2=0\;%0-%H1 274: %2=0\;%3=0\;%2-%3 275: %2=0\;%3=0\;%2-%3 276: %2=0\;%3=0\;%2-%3 277: %2=0\;%0-%H1") 278: 279: 280: (define_insn "" 281: [(set (cc0) (compare (match_operand:QI 0 "register_operand" "j,j,!j,j,q,q,!q,q") 282: (match_operand:QI 1 "nonmemory_operand" "v,y,q,i,v,y,j,i"))) 283: (clobber (match_scratch:QI 2 "=k,k,k,k,u,u,u,u")) 284: (clobber (match_scratch:QI 3 "=w,z,u,X,w,z,k,X"))] 285: "" 286: "@ 287: %2=0\;%3=0\;%0-%1 288: %2=0\;%3=0\;%0-%1 289: %2=0\;%3=0\;%0-%1 290: %2=0\;%b0-%H1 291: %2=0\;%3=0\;%0-%1 292: %2=0\;%3=0\;%0-%1 293: %2=0\;%3=0\;%0-%1 294: %2=0\;%b0-%H1") 295: 296: 297: (define_expand "cmphf" 298: [(set (cc0) 299: (compare (match_operand:HF 0 "register_operand" "") 300: (match_operand:HF 1 "nonmemory_operand" "")))] 301: "" 302: " 303: { 304: if (!dsp16xx_cmphf3_libcall) 305: dsp16xx_cmphf3_libcall = gen_rtx (SYMBOL_REF, Pmode, CMPHF3_LIBCALL); 306: 307: dsp16xx_compare_gen = gen_compare_reg; 308: dsp16xx_compare_op0 = operands[0]; 309: dsp16xx_compare_op1 = operands[1]; 310: emit_library_call (dsp16xx_cmphf3_libcall, 1, HImode, 2, 311: operands[0], HFmode, 312: operands[1], HFmode); 313: emit_insn (gen_tsthi_1 (copy_to_reg(hard_libcall_value (HImode)))); 314: DONE; 315: }") 316: 317: 318: ;; .................... 319: ;; 320: ;; Add instructions 321: ;; 322: ;; .................... 323: 324: 325: (define_insn "addhi3" 326: [(set (match_operand:HI 0 "register_operand" "=A,A,A") 327: (plus:HI (match_operand:HI 1 "register_operand" "%A,A,A") 328: (match_operand:HI 2 "nonmemory_operand" "Z,d,i")))] 329: "" 330: "@ 331: %0=%1+%2 332: %0=%1+%2 333: %0=%w1+%H2\;%0=%b0+%U2" 334: [(set_attr "type" "malu,malu,f3_alu_i")]) 335: 336: (define_insn "" 337: [(set (match_operand:QI 0 "register_operand" "=k,u,!k,!u") 338: (plus:QI (plus:QI (match_operand:QI 1 "register_operand" "uk,uk,uk,uk") 339: (match_operand:QI 2 "register_operand" "wz,wz,uk,uk")) 340: (match_operand:QI 3 "immediate_operand" "i,i,i,i"))) 341: (clobber (match_scratch:QI 4 "=j,q,j,q"))] 342: "" 343: "@ 344: %m0=%m1+%m2\;%m0=%0+%H3 345: %m0=%m1+%m2\;%m0=%0+%H3 346: %m0=%m1+%m2\;%m0=%0+%H3 347: %m0=%m1+%m2\;%m0=%0+%H3") 348: 349: (define_expand "addqi3" 350: [(parallel [(set (match_operand:QI 0 "register_operand" "") 351: (plus:QI (match_operand:QI 1 "register_operand" "") 352: (match_operand:QI 2 "nonmemory_operand" ""))) 353: (clobber (match_scratch:QI 3 ""))])] 354: "" 355: " 356: { 357: if (reload_in_progress) 358: { 359: if (REG_P (operands[1]) && 360: (REGNO(operands[1]) == STACK_POINTER_REGNUM || 361: REGNO(operands[1]) == FRAME_POINTER_REGNUM) && 362: GET_CODE (operands[2]) == CONST_INT) 363: { 364: if (REG_P (operands[0]) && IS_ACCUM_REG(REGNO(operands[0]))) 365: emit_move_insn (operands[0], operands[1]); 366: 367: operands[1] = operands[0]; 368: } 369: } 370: }") 371: 372: 373: (define_insn "match_addqi3" 374: [(set (match_operand:QI 0 "register_operand" "=!a,!a,k,u,!k,!u,h,!a") 375: (plus:QI (match_operand:QI 1 "register_operand" "0,0,uk,uk,uk,uk,h,0") 376: (match_operand:QI 2 "nonmemory_operand" "W,N,wzi,wzi,uk,uk,i,n"))) 377: (clobber (match_scratch:QI 3 "=X,X,j,q,j,q,X,W"))] 378: "" 379: "* 380: { 381: switch (which_alternative) 382: { 383: case 0: 384: return \"*%0++%2\"; 385: 386: case 1: 387: switch (INTVAL (operands[2])) 388: { 389: case -1: 390: return \"*%0--\"; 391: 392: case 1: 393: return \"*%0++\"; 394: 395: case -2: 396: return \"*%0--\;*%0--\"; 397: 398: case 2: 399: return \"*%0++\;*%0++\"; 400: } 401: 402: case 2: 403: case 3: 404: if (!CONSTANT_P(operands[2])) 405: return \"%m0=%m1+%m2\"; 406: else 407: return \"%m0=%1+%H2\"; 408: 409: case 4: 410: case 5: 411: return \"%m0=%m1+%m2\"; 412: 413: case 6: 414: return \"%0=%b1+%H2\"; 415: 416: case 7: 417: return \"%3=%2\;*%0++%3\"; 418: } 419: }") 420: 421: (define_expand "addhf3" 422: [(set (match_operand:HF 0 "register_operand" "") 423: (plus:HF (match_operand:HF 1 "register_operand" "") 424: (match_operand:HF 2 "nonmemory_operand" "")))] 425: "" 426: " 427: { 428: if (!dsp16xx_addhf3_libcall) 429: dsp16xx_addhf3_libcall = gen_rtx (SYMBOL_REF, Pmode, ADDHF3_LIBCALL); 430: 431: emit_library_call (dsp16xx_addhf3_libcall, 1, HFmode, 2, 432: operands[1], HFmode, 433: operands[2], HFmode); 434: emit_move_insn (operands[0], hard_libcall_value(HFmode)); 435: DONE; 436: }") 437: 438: 439: ;; 440: ;; .................... 441: ;; 442: ;; Subtract instructions 443: ;; 444: ;; .................... 445: 446: (define_insn "subhi3" 447: [(set (match_operand:HI 0 "register_operand" "=A,A,A") 448: (minus:HI (match_operand:HI 1 "register_operand" "A,A,A") 449: (match_operand:HI 2 "nonmemory_operand" "Z,d,i")))] 450: "" 451: "@ 452: %0=%1-%2 453: %0=%1-%2 454: %0=%w1-%H2\;%0=%b0-%U2" 455: [(set_attr "type" "malu,malu,f3_alu_i")]) 456: 457: (define_insn "subqi3" 458: [(set (match_operand:QI 0 "register_operand" "=?*a,k,u,!k,!u") 459: (minus:QI (match_operand:QI 1 "register_operand" "0,uk,uk,uk,uk") 460: (match_operand:QI 2 "nonmemory_operand" "n,wzi,wzi,uk,uk"))) 461: (clobber (match_scratch:QI 3 "=W,j,q,j,q"))] 462: "" 463: "* 464: { 465: switch (which_alternative) 466: { 467: case 0: 468: switch (INTVAL (operands[2])) 469: { 470: case 0: 471: return \"\"; 472: 473: case 1: 474: return \"*%0--\"; 475: 476: case -1: 477: return \"*%0++\"; 478: 479: default: 480: operands[2] = GEN_INT (-INTVAL (operands[2])); 481: 482: if (SHORT_IMMEDIATE(operands[2])) 483: return \"set %3=%H2\;*%0++%3\"; 484: else 485: return \"%3=%H2\;*%0++%3\"; 486: } 487: 488: case 1: 489: case 2: 490: if (!CONSTANT_P(operands[2])) 491: return \"%m0=%m1-%m2\"; 492: else 493: return \"%m0=%1-%H2\"; 494: 495: case 3: 496: case 4: 497: return \"%m0=%m1-%m2\"; 498: } 499: }") 500: 501: (define_expand "subhf3" 502: [(set (match_operand:HF 0 "register_operand" "") 503: (minus:HF (match_operand:HF 1 "register_operand" "") 504: (match_operand:HF 2 "nonmemory_operand" "")))] 505: "" 506: " 507: { 508: if (!dsp16xx_subhf3_libcall) 509: dsp16xx_subhf3_libcall = gen_rtx (SYMBOL_REF, Pmode, SUBHF3_LIBCALL); 510: 511: emit_library_call (dsp16xx_subhf3_libcall, 1, HFmode, 2, 512: operands[1], HFmode, 513: operands[2], HFmode); 514: emit_move_insn (operands[0], hard_libcall_value(HFmode)); 515: DONE; 516: }") 517: 518: (define_insn "neghi2" 519: [(set (match_operand:HI 0 "register_operand" "=A") 520: (neg:HI (match_operand:HI 1 "register_operand" "A")))] 521: "" 522: "%0=-%1" 523: [(set_attr "type" "special")]) 524: 525: (define_expand "neghf2" 526: [(set (match_operand:HF 0 "general_operand" "") 527: (neg:HF (match_operand:HF 1 "general_operand" "")))] 528: "" 529: " 530: { 531: if (!dsp16xx_neghf2_libcall) 532: dsp16xx_neghf2_libcall = gen_rtx (SYMBOL_REF, Pmode, NEGHF2_LIBCALL); 533: 534: emit_library_call (dsp16xx_neghf2_libcall, 1, HFmode, 1, 535: operands[1], HFmode); 536: emit_move_insn (operands[0], hard_libcall_value(HFmode)); 537: DONE; 538: }") 539: 540: 541: 542: ;; 543: ;; .................... 544: ;; 545: ;; Multiply instructions 546: ;; 547: 548: (define_expand "mulhi3" 549: [(set (match_operand:HI 0 "register_operand" "") 550: (mult:HI (match_operand:HI 1 "register_operand" "") 551: (match_operand:HI 2 "nonmemory_operand" "")))] 552: "" 553: " 554: { 555: if (!dsp16xx_mulhi3_libcall) 556: dsp16xx_mulhi3_libcall = gen_rtx (SYMBOL_REF, Pmode, MULHI3_LIBCALL); 557: 558: emit_library_call (dsp16xx_mulhi3_libcall, 1, HImode, 2, 559: operands[1], HImode, 560: operands[2], HImode); 561: emit_move_insn (operands[0], hard_libcall_value(HImode)); 562: DONE; 563: }") 564: 565: (define_insn "mulqi3" 566: [(set (match_operand:QI 0 "register_operand" "=w") 567: (mult:QI (match_operand:QI 1 "register_operand" "%x") 568: (match_operand:QI 2 "register_operand" "y"))) 569: (clobber (match_scratch:QI 3 "=v"))] 570: "" 571: "%m0=%1*%2" 572: [(set_attr "type" "malu_mul")]) 573: 574: (define_insn "mulqihi3" 575: [(set (match_operand:HI 0 "register_operand" "=t") 576: (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%x")) 577: (sign_extend:HI (match_operand:QI 2 "register_operand" "y"))))] 578: "" 579: "%0=%1*%2" 580: [(set_attr "type" "malu_mul")]) 581: 582: (define_insn "umulqihi3" 583: [(set (match_operand:HI 0 "register_operand" "=t") 584: (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%x")) 585: (zero_extend:HI (match_operand:QI 2 "register_operand" "y"))))] 586: "" 587: "%0=%1*%2" 588: [(set_attr "type" "malu_mul")]) 589: 590: (define_expand "mulhf3" 591: [(set (match_operand:HF 0 "register_operand" "") 592: (mult:HF (match_operand:HF 1 "register_operand" "") 593: (match_operand:HF 2 "nonmemory_operand" "")))] 594: "" 595: " 596: { 597: if (!dsp16xx_mulhf3_libcall) 598: dsp16xx_mulhf3_libcall = gen_rtx (SYMBOL_REF, Pmode, MULHF3_LIBCALL); 599: 600: emit_library_call (dsp16xx_mulhf3_libcall, 1, HFmode, 2, 601: operands[1], HFmode, 602: operands[2], HFmode); 603: emit_move_insn (operands[0], hard_libcall_value(HFmode)); 604: DONE; 605: }") 606: 607: 608: 609: ;; 610: ;; ******************* 611: ;; 612: ;; Divide Instructions 613: ;; 614: 615: (define_expand "divhi3" 616: [(set (match_operand:HI 0 "register_operand" "") 617: (div:HI (match_operand:HI 1 "register_operand" "") 618: (match_operand:HI 2 "nonmemory_operand" "")))] 619: "" 620: " 621: { 622: if (!dsp16xx_divhi3_libcall) 623: dsp16xx_divhi3_libcall = gen_rtx (SYMBOL_REF, Pmode, DIVHI3_LIBCALL); 624: 625: emit_library_call (dsp16xx_divhi3_libcall, 1, HImode, 2, 626: operands[1], HImode, 627: operands[2], HImode); 628: emit_move_insn (operands[0], hard_libcall_value(HImode)); 629: DONE; 630: }") 631: 632: (define_expand "udivhi3" 633: [(set (match_operand:HI 0 "register_operand" "") 634: (udiv:HI (match_operand:HI 1 "register_operand" "") 635: (match_operand:HI 2 "nonmemory_operand" "")))] 636: "" 637: " 638: { 639: if (!dsp16xx_udivhi3_libcall) 640: dsp16xx_udivhi3_libcall = gen_rtx (SYMBOL_REF, Pmode, UDIVHI3_LIBCALL); 641: 642: emit_library_call (dsp16xx_udivhi3_libcall, 1, HImode, 2, 643: operands[1], HImode, 644: operands[2], HImode); 645: emit_move_insn (operands[0], hard_libcall_value(HImode)); 646: DONE; 647: }") 648: 649: (define_expand "divqi3" 650: [(set (match_operand:QI 0 "register_operand" "") 651: (div:QI (match_operand:QI 1 "register_operand" "") 652: (match_operand:QI 2 "nonmemory_operand" "")))] 653: "" 654: " 655: { 656: if (!dsp16xx_divqi3_libcall) 657: dsp16xx_divqi3_libcall = gen_rtx (SYMBOL_REF, Pmode, DIVQI3_LIBCALL); 658: 659: emit_library_call (dsp16xx_divqi3_libcall, 1, QImode, 2, 660: operands[1], QImode, 661: operands[2], QImode); 662: emit_move_insn (operands[0], hard_libcall_value(QImode)); 663: DONE; 664: }") 665: 666: (define_expand "udivqi3" 667: [(set (match_operand:QI 0 "register_operand" "") 668: (udiv:QI (match_operand:QI 1 "register_operand" "") 669: (match_operand:QI 2 "nonmemory_operand" "")))] 670: "" 671: " 672: { 673: if (!dsp16xx_udivqi3_libcall) 674: dsp16xx_udivqi3_libcall = gen_rtx (SYMBOL_REF, Pmode, UDIVQI3_LIBCALL); 675: 676: emit_library_call (dsp16xx_udivqi3_libcall, 1, QImode, 2, 677: operands[1], QImode, 678: operands[2], QImode); 679: emit_move_insn (operands[0], hard_libcall_value(QImode)); 680: DONE; 681: }") 682: 683: ;; 684: ;; .................... 685: ;; 686: ;; Modulo instructions 687: ;; 688: ;; .................... 689: 690: (define_expand "modhi3" 691: [(set (match_operand:HI 0 "register_operand" "") 692: (mod:HI (match_operand:HI 1 "register_operand" "") 693: (match_operand:HI 2 "nonmemory_operand" "")))] 694: "" 695: " 696: { 697: if (!dsp16xx_modhi3_libcall) 698: dsp16xx_modhi3_libcall = gen_rtx (SYMBOL_REF, Pmode, MODHI3_LIBCALL); 699: 700: emit_library_call (dsp16xx_modhi3_libcall, 1, HImode, 2, 701: operands[1], HImode, 702: operands[2], HImode); 703: emit_move_insn (operands[0], hard_libcall_value(HImode)); 704: DONE; 705: }") 706: 707: (define_expand "umodhi3" 708: [(set (match_operand:HI 0 "register_operand" "") 709: (umod:HI (match_operand:HI 1 "register_operand" "") 710: (match_operand:HI 2 "nonmemory_operand" "")))] 711: "" 712: " 713: { 714: if (!dsp16xx_umodhi3_libcall) 715: dsp16xx_umodhi3_libcall = gen_rtx (SYMBOL_REF, Pmode, UMODHI3_LIBCALL); 716: 717: emit_library_call (dsp16xx_umodhi3_libcall, 1, HImode, 2, 718: operands[1], HImode, 719: operands[2], HImode); 720: emit_move_insn (operands[0], hard_libcall_value(HImode)); 721: DONE; 722: }") 723: 724: (define_expand "modqi3" 725: [(set (match_operand:QI 0 "register_operand" "") 726: (mod:QI (match_operand:QI 1 "register_operand" "") 727: (match_operand:QI 2 "nonmemory_operand" "")))] 728: "" 729: " 730: { 731: if (!dsp16xx_modqi3_libcall) 732: dsp16xx_modqi3_libcall = gen_rtx (SYMBOL_REF, Pmode, MODQI3_LIBCALL); 733: 734: emit_library_call (dsp16xx_modqi3_libcall, 1, QImode, 2, 735: operands[1], QImode, 736: operands[2], QImode); 737: emit_move_insn (operands[0], hard_libcall_value(QImode)); 738: DONE; 739: }") 740: 741: (define_expand "umodqi3" 742: [(set (match_operand:QI 0 "register_operand" "") 743: (umod:QI (match_operand:QI 1 "register_operand" "") 744: (match_operand:QI 2 "nonmemory_operand" "")))] 745: "" 746: " 747: { 748: if (!dsp16xx_umodqi3_libcall) 749: dsp16xx_umodqi3_libcall = gen_rtx (SYMBOL_REF, Pmode, UMODQI3_LIBCALL); 750: 751: emit_library_call (dsp16xx_umodqi3_libcall, 1, QImode, 2, 752: operands[1], QImode, 753: operands[2], QImode); 754: emit_move_insn (operands[0], hard_libcall_value(QImode)); 755: DONE; 756: }") 757: 758: (define_expand "divhf3" 759: [(set (match_operand:HF 0 "register_operand" "") 760: (div:HF (match_operand:HF 1 "register_operand" "") 761: (match_operand:HF 2 "nonmemory_operand" "")))] 762: "" 763: " 764: { 765: if (!dsp16xx_divhf3_libcall) 766: dsp16xx_divhf3_libcall = gen_rtx (SYMBOL_REF, Pmode, DIVHF3_LIBCALL); 767: 768: emit_library_call (dsp16xx_divhf3_libcall, 1, HFmode, 2, 769: operands[1], HFmode, 770: operands[2], HFmode); 771: emit_move_insn (operands[0], hard_libcall_value(HFmode)); 772: DONE; 773: }") 774: 775: 776: 777: ;; 778: ;; ******************** 779: ;; 780: ;; Logical Instructions 781: ;; 782: 783: (define_insn "andhi3" 784: [(set (match_operand:HI 0 "register_operand" "=A,A,?A") 785: (and:HI (match_operand:HI 1 "register_operand" "%A,!A,A") 786: (match_operand:HI 2 "nonmemory_operand" "Z,A,i")))] 787: "" 788: "@ 789: %0=%1&%2 790: %0=%1&%2 791: %0=%w1&%H2\;%0=%b0&%U2" 792: [(set_attr "type" "f3_alu,f3_alu,f3_alu_i")]) 793: 794: (define_insn "andqi3" 795: [(set (match_operand:QI 0 "register_operand" "=k,u,uk,!k,!u,j,q,jq,!j,!q") 796: (and:QI (match_operand:QI 1 "register_operand" "uk,uk,uk,uk,uk,jq,jq,jq,jq,jq") 797: (match_operand:QI 2 "nonmemory_operand" "wz,wz,i,uk,uk,yv,yv,i,jq,jq"))) 798: (clobber (match_scratch:QI 3 "=j,q,X,j,q,k,u,X,k,u"))] 799: "" 800: "@ 801: %m0=%m1&%m2 802: %m0=%m1&%m2 803: %m0=%1&%H2 804: %m0=%m1&%m2 805: %m0=%m1&%m2 806: %m0=%m1&%m2 807: %m0=%m1&%m2 808: %m0=%b1&%H2 809: %m0=%m1&%m2 810: %m0=%m1&%m2") 811: 812: (define_insn "iorhi3" 813: [(set (match_operand:HI 0 "register_operand" "=A,A,A,?A") 814: (ior:HI (match_operand:HI 1 "register_operand" "%A,!A,A,A") 815: (match_operand:HI 2 "nonmemory_operand" "Z,A,I,i")))] 816: "" 817: "@ 818: %0=%u1|%u2 819: %0=%u1|%u2 820: %0=%w1|%H2 821: %0=%w1|%H2\;%0=%b0|%U2" 822: [(set_attr "type" "f3_alu,f3_alu,f3_alu_i,f3_alu_i")]) 823: 824: (define_insn "iorqi3" 825: [(set (match_operand:QI 0 "register_operand" "=k,u,uk,!k,!u,j,q,jq,!j,!q") 826: (ior:QI (match_operand:QI 1 "register_operand" "uk,uk,uk,uk,uk,jq,jq,jq,jq,jq") 827: (match_operand:QI 2 "nonmemory_operand" "wz,wz,i,uk,uk,yv,yv,i,jq,jq"))) 828: (clobber (match_scratch:QI 3 "=j,q,X,j,q,k,u,X,k,u"))] 829: "" 830: "@ 831: %m0=%m1|%m2 832: %m0=%m1|%m2 833: %m0=%1|%H2 834: %m0=%m1|%m2 835: %m0=%m1|%m2 836: %m0=%m1|%m2 837: %m0=%m1|%m2 838: %m0=%b1|%H2 839: %m0=%m1|%m2 840: %m0=%m1|%m2") 841: 842: (define_insn "xorhi3" 843: [(set (match_operand:HI 0 "register_operand" "=A,A,A,?A") 844: (xor:HI (match_operand:HI 1 "register_operand" "%A,!A,A,A") 845: (match_operand:HI 2 "nonmemory_operand" "Z,A,I,i")))] 846: "" 847: "@ 848: %0=%1^%2 849: %0=%1^%2 850: %0=%w1^%H2 851: %0=%w1^%H2\;%0=%b0^%U2" 852: [(set_attr "type" "f3_alu,f3_alu,f3_alu_i,f3_alu_i")]) 853: 854: (define_insn "xorqi3" 855: [(set (match_operand:QI 0 "register_operand" "=k,u,uk,!k,!u,j,q,jq,!j,!q") 856: (xor:QI (match_operand:QI 1 "register_operand" "uk,uk,uk,uk,uk,jq,jq,jq,jq,jq") 857: (match_operand:QI 2 "nonmemory_operand" "wz,wz,i,uk,uk,yv,yv,i,jq,jq"))) 858: (clobber (match_scratch:QI 3 "=j,q,X,j,q,k,u,X,k,u"))] 859: "" 860: "@ 861: %m0=%m1^%m2 862: %m0=%m1^%m2 863: %m0=%1^%H2 864: %m0=%m1^%m2 865: %m0=%m1^%m2 866: %m0=%m1^%m2 867: %m0=%m1^%m2 868: %m0=%b1^%H2 869: %m0=%m1^%m2 870: %m0=%m1^%m2") 871: 872: (define_insn "one_cmplhi2" 873: [(set (match_operand:HI 0 "register_operand" "=A") 874: (not:HI (match_operand:HI 1 "register_operand" "A")))] 875: "" 876: "%0= ~%1" 877: [(set_attr "type" "special")]) 878: 879: (define_insn "one_cmplqi2" 880: [(set (match_operand:QI 0 "register_operand" "=ku,jq") 881: (not:QI (match_operand:QI 1 "register_operand" "ku,jq")))] 882: "" 883: "@ 884: %m0= %1 ^ 0xffff 885: %m0= %b1 ^ 0xffff" 886: [(set_attr "type" "special")]) 887: 888: 889: ;; 890: ;; MOVE INSTRUCTIONS 891: ;; 892: 893: (define_expand "movhi" 894: [(set (match_operand:HI 0 "general_operand" "") 895: (match_operand:HI 1 "general_operand" ""))] 896: "" 897: " 898: { 899: if (emit_move_sequence (operands, HImode)) 900: DONE; 901: }") 902: 903: 904: (define_insn "match_movhi1" 905: [(set (match_operand:HI 0 "nonimmediate_operand" "=A,Z,A,d,d,m,?d,*Y,t,f") 906: (match_operand:HI 1 "general_operand" "d,A,K,i,m,d,*Y,?d,t,f"))] 907: "register_operand(operands[0], HImode) 908: || register_operand(operands[1], HImode)" 909: "* 910: { 911: switch (which_alternative) 912: { 913: /* register to accumulator */ 914: case 0: 915: return \"%0=%1\"; 916: case 1: 917: return \"%u0=%u1\;%w0=%w1\"; 918: case 2: 919: return \"%0=%0^%0\"; 920: case 3: 921: return \"%u0=%U1\;%w0=%H1\"; 922: case 4: 923: double_reg_from_memory(operands); 924: return \"\"; 925: case 5: 926: double_reg_to_memory(operands); 927: return \"\"; 928: case 6: 929: case 7: 930: return \"%u0=%u1\;%w0=%w1\"; 931: case 8: 932: case 9: 933: return \"\"; 934: } 935: }" 936: [(set_attr "type" "move,move,load_i,load_i,load,store,load,store,move,move")]) 937: 938: 939: ;; NOTE: It is cheaper to do 'y = *r0', than 'r0 = *r0'. 940: 941: (define_expand "movqi" 942: [(set (match_operand:QI 0 "nonimmediate_operand" "") 943: (match_operand:QI 1 "general_operand" ""))] 944: "" 945: " 946: { 947: if (emit_move_sequence (operands, QImode)) 948: DONE; 949: }") 950: 951: ;; The movqi pattern with the parallel is used for addqi insns (which have a parallel) 952: ;; that are turned into moveqi insns by the flow phase. This happens when a auto-increment 953: ;; is detected. 954: 955: (define_insn "match_movqi1" 956: [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "=A,r,aW,c,?D,m<>,e,Y,r,xyz,m<>") 957: (match_operand:QI 1 "general_operand" "r,A,J,i,m<>,D,Y,e,0,m<>,xyz")) 958: (clobber (match_scratch:QI 2 "=X,X,X,X,X,X,X,X,X,X,X"))])] 959: "register_operand(operands[0], QImode) 960: || register_operand(operands[1], QImode)" 961: "* 962: { 963: switch (which_alternative) 964: { 965: case 0: 1.1.1.2 ! root 966: /* We have to use the move mnemonic otherwise the 1610 will ! 967: attempt to transfer all 32-bits of 'y', 'p' or an accumulator 1.1 root 968: , which we don't want */ 969: if (REGNO(operands[1]) == REG_Y || REGNO(operands[1]) == REG_PROD 970: || IS_ACCUM_REG(REGNO(operands[1]))) 971: return \"move %0=%1\"; 972: else 973: return \"%0=%1\"; 974: 975: case 1: 976: return \"%0=%1\"; 977: 978: case 2: 979: return \"set %0=%H1\"; 980: 981: case 3: 982: return \"%0=%H1\"; 983: 984: case 4: 985: return \"%0=%1\"; 986: 987: case 5: 988: case 6: 989: return \"%0=%1\"; 990: 991: case 7: 992: return \"%0=%1\"; 993: 994: case 8: 995: return \"\"; 996: 997: case 9: case 10: 998: return \"%0=%1\"; 999: } 1000: }") 1001: 1002: (define_insn "match_movqi2" 1003: [(set (match_operand:QI 0 "nonimmediate_operand" "=A,r,aW,c,?D,m<>,e,Y,r,xyz,m<>") 1004: (match_operand:QI 1 "general_operand" "r,A,J,i,m<>,D,Y,e,0,m<>,xyz"))] 1005: "register_operand(operands[0], QImode) 1006: || register_operand(operands[1], QImode)" 1007: "* 1008: { 1009: switch (which_alternative) 1010: { 1011: case 0: 1.1.1.2 ! root 1012: /* We have to use the move mnemonic otherwise the 1610 will ! 1013: attempt to transfer all 32-bits of 'y', 'p' or an accumulator 1.1 root 1014: , which we don't want */ 1015: if (REGNO(operands[1]) == REG_Y || REGNO(operands[1]) == REG_PROD 1016: || IS_ACCUM_REG(REGNO(operands[1]))) 1017: return \"move %0=%1\"; 1018: else 1019: return \"%0=%1\"; 1020: 1021: case 1: 1022: return \"%0=%1\"; 1023: 1024: case 2: 1025: return \"set %0=%H1\"; 1026: 1027: case 3: 1028: return \"%0=%H1\"; 1029: 1030: case 4: 1031: return \"%0=%1\"; 1032: 1033: case 5: 1034: case 6: 1035: return \"%0=%1\"; 1036: 1037: case 7: 1038: return \"%0=%1\"; 1039: 1040: case 8: 1041: return \"\"; 1042: 1043: case 9: case 10: 1044: return \"%0=%1\"; 1045: } 1046: }") 1047: 1048: (define_expand "reload_inqi" 1049: [(set (match_operand:QI 0 "register_operand" "=u") 1050: (match_operand:QI 1 "sp_operand" "")) 1051: (clobber (match_operand:QI 2 "register_operand" "=&q"))] 1052: "" 1053: " 1054: { 1055: rtx addr_reg = XEXP (operands[1], 0); 1056: rtx offset = XEXP (operands[1], 1); 1057: 1058: /* First, move the frame or stack pointer to the accumulator */ 1059: emit_move_insn (operands[0], addr_reg); 1060: 1061: /* Then generate the add insn */ 1062: emit_insn (gen_rtx (PARALLEL, VOIDmode, 1063: gen_rtvec (2, 1064: gen_rtx (SET, VOIDmode, operands[0], 1065: gen_rtx (PLUS, QImode, operands[0], offset)), 1066: gen_rtx (CLOBBER, VOIDmode, operands[2])))); 1067: DONE; 1068: }") 1069: 1070: (define_expand "reload_inhi" 1071: [(set (match_operand:HI 0 "register_operand" "=r") 1072: (match_operand:HI 1 "register_operand" "r")) 1073: (clobber (match_operand:QI 2 "register_operand" "=&h"))] 1074: "" 1075: " 1076: { 1077: /* Check for an overlap of operand 2 (an accumulator) with 1078: the msw of operand 0. If we have an overlap we must reverse 1079: the order of the moves. */ 1080: 1081: if (REGNO(operands[2]) == REGNO(operands[0])) 1082: { 1083: emit_move_insn (operands[2], operand_subword (operands[1], 1, 0, HImode)); 1084: emit_move_insn (operand_subword (operands[0], 1, 0, HImode), operands[2]); 1085: emit_move_insn (operands[2], operand_subword (operands[1], 0, 0, HImode)); 1086: emit_move_insn (operand_subword (operands[0], 0, 0, HImode), operands[2]); 1087: } 1088: else 1089: { 1090: emit_move_insn (operands[2], operand_subword (operands[1], 0, 0, HImode)); 1091: emit_move_insn (operand_subword (operands[0], 0, 0, HImode), operands[2]); 1092: emit_move_insn (operands[2], operand_subword (operands[1], 1, 0, HImode)); 1093: emit_move_insn (operand_subword (operands[0], 1, 0, HImode), operands[2]); 1094: } 1095: 1096: DONE; 1097: }") 1098: 1099: 1100: (define_expand "reload_outhi" 1101: [(set (match_operand:HI 0 "register_operand" "=r") 1102: (match_operand:HI 1 "register_operand" "r")) 1103: (clobber (match_operand:QI 2 "register_operand" "=&h"))] 1104: "" 1105: " 1106: { 1107: emit_move_insn (operands[2], operand_subword (operands[1], 0, 0, HImode)); 1108: emit_move_insn (operand_subword (operands[0], 0, 0, HImode), operands[2]); 1109: emit_move_insn (operands[2], operand_subword (operands[1], 1, 0, HImode)); 1110: emit_move_insn (operand_subword (operands[0], 1, 0, HImode), operands[2]); 1111: DONE; 1112: }") 1113: 1114: (define_expand "movstrqi" 1115: [(parallel [(set (match_operand:BLK 0 "memory_operand" "") 1116: (match_operand:BLK 1 "memory_operand" "")) 1117: (use (match_operand:QI 2 "const_int_operand" "")) 1118: (use (match_operand:QI 3 "const_int_operand" "")) 1119: (clobber (match_scratch:QI 4 "")) 1120: (clobber (match_dup 5)) 1121: (clobber (match_dup 6))])] 1122: "" 1123: " 1124: { 1125: rtx addr0, addr1; 1126: 1127: if (GET_CODE (operands[2]) != CONST_INT) 1128: FAIL; 1129: 1130: if (INTVAL(operands[2]) > 127) 1131: FAIL; 1132: 1133: addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); 1134: addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); 1135: 1136: operands[5] = addr0; 1137: operands[6] = addr1; 1138: 1139: operands[0] = gen_rtx (MEM, BLKmode, addr0); 1140: operands[1] = gen_rtx (MEM, BLKmode, addr1); 1141: }") 1142: 1143: (define_insn "" 1144: [(set (mem:BLK (match_operand:QI 0 "register_operand" "a")) 1145: (mem:BLK (match_operand:QI 1 "register_operand" "a"))) 1146: (use (match_operand:QI 2 "const_int_operand" "n")) 1147: (use (match_operand:QI 3 "immediate_operand" "i")) 1148: (clobber (match_scratch:QI 4 "=x")) 1149: (clobber (match_dup 0)) 1150: (clobber (match_dup 1))] 1151: "" 1152: "* 1153: { return output_block_move (operands); }") 1154: 1155: 1156: ;; Floating point move insns 1157: 1158: 1159: (define_expand "movhf" 1160: [(set (match_operand:HF 0 "general_operand" "") 1161: (match_operand:HF 1 "general_operand" ""))] 1162: "" 1163: " 1164: { 1165: if (emit_move_sequence (operands, HFmode)) 1166: DONE; 1167: }") 1168: 1169: (define_insn "match_movhf" 1170: [(set (match_operand:HF 0 "nonimmediate_operand" "=A,Z,d,d,m,d,Y") 1171: (match_operand:HF 1 "general_operand" "d,A,F,m,d,Y,d"))] 1172: "" 1173: "* 1174: { 1175: /* NOTE: When loading the register 16 bits at a time we 1176: MUST load the high half FIRST (because the 1610 zeros 1177: the low half) and then load the low half */ 1178: 1179: switch (which_alternative) 1180: { 1181: /* register to accumulator */ 1182: case 0: 1183: return \"%0=%1\"; 1184: case 1: 1185: return \"%u0=%u1\;%w0=%w1\"; 1186: case 2: 1187: output_dsp16xx_float_const(operands); 1188: return \"\"; 1189: case 3: 1190: double_reg_from_memory(operands); 1191: return \"\"; 1192: case 4: 1193: double_reg_to_memory(operands); 1194: return \"\"; 1195: case 5: 1196: case 6: 1197: return \"%u0=%u1\;%w0=%w1\"; 1198: } 1199: }" 1200: [(set_attr "type" "move,move,load_i,load,store,load,store")]) 1201: 1202: 1203: 1204: (define_expand "reload_inhf" 1205: [(set (match_operand:HF 0 "register_operand" "=r") 1206: (match_operand:HF 1 "register_operand" "r")) 1207: (clobber (match_operand:QI 2 "register_operand" "=&h"))] 1208: "" 1209: " 1210: { 1211: /* Check for an overlap of operand 2 (an accumulator) with 1212: the msw of operand 0. If we have an overlap we must reverse 1213: the order of the moves. */ 1214: 1215: if (REGNO(operands[2]) == REGNO(operands[0])) 1216: { 1217: emit_move_insn (operands[2], operand_subword (operands[1], 1, 0, HFmode)); 1218: emit_move_insn (operand_subword (operands[0], 1, 0, HFmode), operands[2]); 1219: emit_move_insn (operands[2], operand_subword (operands[1], 0, 0, HFmode)); 1220: emit_move_insn (operand_subword (operands[0], 0, 0, HFmode), operands[2]); 1221: } 1222: else 1223: { 1224: emit_move_insn (operands[2], operand_subword (operands[1], 0, 0, HFmode)); 1225: emit_move_insn (operand_subword (operands[0], 0, 0, HFmode), operands[2]); 1226: emit_move_insn (operands[2], operand_subword (operands[1], 1, 0, HFmode)); 1227: emit_move_insn (operand_subword (operands[0], 1, 0, HFmode), operands[2]); 1228: } 1229: 1230: DONE; 1231: }") 1232: 1233: (define_expand "reload_outhf" 1234: [(set (match_operand:HF 0 "register_operand" "=r") 1235: (match_operand:HF 1 "register_operand" "r")) 1236: (clobber (match_operand:QI 2 "register_operand" "=&h"))] 1237: "" 1238: " 1239: { 1240: emit_move_insn (operands[2], operand_subword (operands[1], 0, 0, HFmode)); 1241: emit_move_insn (operand_subword (operands[0], 0, 0, HFmode), operands[2]); 1242: emit_move_insn (operands[2], operand_subword (operands[1], 1, 0, HFmode)); 1243: emit_move_insn (operand_subword (operands[0], 1, 0, HFmode), operands[2]); 1244: DONE; 1245: }") 1246: 1247: 1248: ;; 1249: ;; CONVERSION INSTRUCTIONS 1250: ;; 1251: 1252: (define_expand "extendqihi2" 1253: [(clobber (match_dup 2)) 1254: (set (match_dup 3) (match_operand:QI 1 "register_operand" "")) 1255: (set (match_operand:HI 0 "register_operand" "") 1256: (ashift:HI (match_dup 2) 1257: (const_int 16))) 1258: (set (match_dup 0) 1259: (ashiftrt:HI (match_dup 0) (const_int 16)))] 1260: "" 1261: " 1262: { 1263: operands[2] = gen_reg_rtx (HImode); 1264: operands[3] = gen_rtx (SUBREG, QImode, operands[2], 1); 1265: }") 1266: 1267: ;;(define_insn "extendqihi2" 1268: ;; [(set (match_operand:HI 0 "register_operand" "=A") 1269: ;; (sign_extend:HI (match_operand:QI 1 "register_operand" "h")))] 1270: ;; "" 1271: ;; "%0 = %1 >> 16") 1272: 1273: ;;(define_insn "zero_extendqihi2" 1274: ;; [(set (match_operand:HI 0 "register_operand" "=t,f,A,?d,?A") 1275: ;; (zero_extend:HI (match_operand:QI 1 "register_operand" "w,z,ku,A,r")))] 1276: ;; "" 1277: ;; "* 1278: ;; { 1279: ;; switch (which_alternative) 1280: ;; { 1281: ;; case 0: 1282: ;; case 1: 1283: ;; return \"%0=0\"; 1284: ;; 1285: ;; case 2: 1286: ;; if (REGNO(operands[1]) == (REGNO(operands[0]) + 1)) 1287: ;; return \"%0=0\"; 1288: ;; else 1289: ;; return \"%w0=%1\;%0=0\"; 1290: ;; case 3: 1291: ;; return \"%w0=%1\;%0=0\"; 1292: ;; 1293: ;; case 4: 1294: ;; if (REGNO(operands[1]) == REG_Y || REGNO(operands[1]) == REG_PROD 1295: ;; || IS_ACCUM_REG(REGNO(operands[1]))) 1296: ;; return \"move %w0=%1\;%0=0\"; 1297: ;; else 1298: ;; return \"%w0=%1\;%0=0\"; 1299: ;; } 1300: ;; }") 1301: 1302: (define_expand "zero_extendqihi2" 1303: [(clobber (match_dup 2)) 1304: (set (match_dup 3) (match_operand:QI 1 "register_operand" "")) 1305: (set (match_operand:HI 0 "register_operand" "") 1306: (ashift:HI (match_dup 2) 1307: (const_int 16))) 1308: (set (match_dup 0) 1309: (lshiftrt:HI (match_dup 0) (const_int 16)))] 1310: "" 1311: " 1312: { 1313: operands[2] = gen_reg_rtx (HImode); 1314: operands[3] = gen_rtx (SUBREG, QImode, operands[2], 1); 1315: }") 1316: 1317: 1318: (define_expand "floathihf2" 1319: [(set (match_operand:HF 0 "register_operand" "") 1320: (float:HF (match_operand:HI 1 "register_operand" "")))] 1321: "" 1322: " 1323: { 1324: if (!dsp16xx_floathihf2_libcall) 1325: dsp16xx_floathihf2_libcall = gen_rtx (SYMBOL_REF, Pmode, FLOATHIHF2_LIBCALL); 1326: 1327: emit_library_call (dsp16xx_floathihf2_libcall, 1, HFmode, 1, 1328: operands[1], HImode); 1329: emit_move_insn (operands[0], hard_libcall_value(HFmode)); 1330: DONE; 1331: }") 1332: 1333: (define_expand "fix_trunchfhi2" 1334: [(set (match_operand:HI 0 "register_operand" "") 1335: (fix:HI (match_operand:HF 1 "register_operand" "")))] 1336: "" 1337: " 1338: { 1339: if (!dsp16xx_fixhfhi2_libcall) 1340: dsp16xx_fixhfhi2_libcall = gen_rtx (SYMBOL_REF, Pmode, FIXHFHI2_LIBCALL); 1341: 1342: emit_library_call (dsp16xx_fixhfhi2_libcall, 1, HImode, 1, 1343: operands[1], HFmode); 1344: emit_move_insn (operands[0], hard_libcall_value(HImode)); 1345: DONE; 1346: }") 1347: 1348: (define_expand "fixuns_trunchfhi2" 1349: [(set (match_operand:HI 0 "register_operand" "") 1350: (unsigned_fix:HI (match_operand:HF 1 "register_operand" "")))] 1351: "" 1352: " 1353: { 1354: rtx reg1 = gen_reg_rtx (HFmode); 1355: rtx reg2 = gen_reg_rtx (HFmode); 1356: rtx reg3 = gen_reg_rtx (HImode); 1357: rtx label1 = gen_label_rtx (); 1358: rtx label2 = gen_label_rtx (); 1359: REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31); 1360: 1361: if (reg1) /* turn off complaints about unreached code */ 1362: { 1363: emit_move_insn (reg1, immed_real_const_1 (offset, HFmode)); 1364: do_pending_stack_adjust (); 1365: 1366: emit_insn (gen_cmphf (operands[1], reg1)); 1367: emit_jump_insn (gen_bge (label1)); 1368: 1369: emit_insn (gen_fix_trunchfhi2 (operands[0], operands[1])); 1370: emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx, 1371: gen_rtx (LABEL_REF, VOIDmode, label2))); 1372: emit_barrier (); 1373: 1374: emit_label (label1); 1375: emit_insn (gen_subhf3 (reg2, operands[1], reg1)); 1376: emit_move_insn (reg3, GEN_INT (0x80000000));; 1377: 1378: emit_insn (gen_fix_trunchfhi2 (operands[0], reg2)); 1379: emit_insn (gen_iorhi3 (operands[0], operands[0], reg3)); 1380: 1381: emit_label (label2); 1382: 1383: /* allow REG_NOTES to be set on last insn (labels don't have enough 1384: fields, and can't be used for REG_NOTES anyway). */ 1385: emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx)); 1386: DONE; 1387: } 1388: }") 1389: 1390: ;; 1391: ;; SHIFT INSTRUCTIONS 1392: ;; 1393: 1394: (define_insn "" 1395: [(set (match_operand:HI 0 "register_operand" "=A") 1396: (ashiftrt:HI (match_operand:HI 1 "register_operand" "A") 1397: (const_int 1)))] 1398: "" 1399: "%0=%1>>1" 1400: [(set_attr "type" "special")]) 1401: 1402: (define_insn "" 1403: [(set (match_operand:HI 0 "register_operand" "=A") 1404: (ashiftrt:HI (match_operand:HI 1 "register_operand" "A") 1405: (const_int 4)))] 1406: "" 1407: "%0=%1>>4" 1408: [(set_attr "type" "special")]) 1409: 1410: (define_insn "" 1411: [(set (match_operand:HI 0 "register_operand" "=A") 1412: (ashiftrt:HI (match_operand:HI 1 "register_operand" "A") 1413: (const_int 8)))] 1414: "" 1415: "%0=%1>>8" 1416: [(set_attr "type" "special")]) 1417: 1418: (define_insn "" 1419: [(set (match_operand:HI 0 "register_operand" "=A") 1420: (ashiftrt:HI (match_operand:HI 1 "register_operand" "A") 1421: (const_int 16)))] 1422: "" 1423: "%0=%1>>16" 1424: [(set_attr "type" "special")]) 1425: 1426: ;; 1427: ;; Arithmetic Right shift 1428: 1429: (define_expand "ashrhi3" 1430: [(set (match_operand:HI 0 "register_operand" "") 1431: (ashiftrt:HI (match_operand:HI 1 "register_operand" "") 1432: (match_operand:QI 2 "nonmemory_operand" "")))] 1433: "" 1434: " 1435: { 1436: if (!TARGET_BMU) 1437: { 1438: /* If we are shifting by a constant we can do it in 1 or more 1439: 1600 core shift instructions. The core instructions can 1440: shift by 1, 4, 8, or 16. */ 1441: 1442: if (GET_CODE(operands[2]) == CONST_INT) 1443: ; 1444: else 1445: { 1446: rtx label1 = gen_label_rtx (); 1447: rtx label2 = gen_label_rtx (); 1448: 1449: #if 0 1450: if (!dsp16xx_ashrhi3_libcall) 1451: dsp16xx_ashrhi3_libcall = gen_rtx (SYMBOL_REF, Pmode, ASHRHI3_LIBCALL); 1452: 1453: emit_library_call (dsp16xx_ashrhi3_libcall, 1, HImode, 2, 1454: operands[1], HImode, 1455: operands[2], QImode); 1456: emit_move_insn (operands[0], hard_libcall_value(HImode)); 1457: DONE; 1458: #else 1459: do_pending_stack_adjust (); 1460: emit_insn (gen_tstqi (operands[2])); 1461: emit_jump_insn (gen_bne (label1)); 1462: emit_move_insn (operands[0], operands[1]); 1463: emit_jump_insn (gen_jump (label2)); 1464: emit_barrier (); 1465: emit_label (label1); 1466: 1467: if (GET_CODE(operands[2]) != MEM) 1468: { 1469: rtx stack_slot; 1470: 1471: stack_slot = assign_stack_temp (QImode, GET_MODE_SIZE(QImode), 0); 1472: stack_slot = change_address (stack_slot, VOIDmode, XEXP (stack_slot, 0)); 1473: emit_move_insn (stack_slot, operands[2]); 1474: operands[2] = stack_slot; 1475: } 1476: 1477: emit_insn (gen_match_ashrhi3_nobmu (operands[0], operands[1], operands[2])); 1478: emit_label (label2); 1479: DONE; 1480: #endif 1481: } 1482: } 1483: }") 1484: 1485: (define_insn "match_ashrhi3_bmu" 1486: [(set (match_operand:HI 0 "register_operand" "=A,A,A") 1487: (ashiftrt:HI (match_operand:HI 1 "register_operand" "A,A,!A") 1488: (match_operand:QI 2 "nonmemory_operand" "B,I,h")))] 1489: "TARGET_BMU" 1490: "@ 1491: %0=%1>>%2 1492: %0=%1>>%H2 1493: %0=%1>>%2" 1494: [(set_attr "type" "shift,shift_i,shift")]) 1495: 1496: (define_insn "match_ashrhi3_nobmu" 1497: [(set (match_operand:HI 0 "register_operand" "=A,A") 1498: (ashiftrt:HI (match_operand:HI 1 "register_operand" "A,0") 1499: (match_operand:QI 2 "general_operand" "n,m")))] 1500: "!TARGET_BMU" 1501: "* 1502: { 1503: if (which_alternative == 0) 1504: { 1505: emit_1600_core_shift (ASHIFTRT, operands, INTVAL(operands[2])); 1506: return \"\"; 1507: } 1508: else 1509: { 1510: output_asm_insn (\"cloop=%2\", operands); 1511: output_asm_insn (\"do 0 \{\", operands); 1512: output_asm_insn (\"%0=%0>>1\", operands); 1513: return \"\}\"; 1514: } 1515: }") 1516: 1517: 1518: 1519: ;; 1520: ;; Logical Right Shift 1521: 1522: (define_insn "" 1523: [(set (match_operand:HI 0 "register_operand" "=A") 1524: (lshiftrt:HI (match_operand:HI 1 "register_operand" "A") 1525: (const_int 1)))] 1526: "" 1527: "%0=%1>>1\;%0=%b0&0x7fff" 1528: [(set_attr "type" "special")]) 1529: 1530: (define_insn "" 1531: [(set (match_operand:HI 0 "register_operand" "=A") 1532: (lshiftrt:HI (match_operand:HI 1 "register_operand" "A") 1533: (const_int 4)))] 1534: "" 1535: "%0=%1>>4\;%0=%b0&0x0fff" 1536: [(set_attr "type" "special")]) 1537: 1538: (define_insn "" 1539: [(set (match_operand:HI 0 "register_operand" "=A") 1540: (lshiftrt:HI (match_operand:HI 1 "register_operand" "A") 1541: (const_int 8)))] 1542: "" 1543: "%0=%1>>8\;%0=%b0&0x00ff" 1544: [(set_attr "type" "special")]) 1545: 1546: (define_insn "" 1547: [(set (match_operand:HI 0 "register_operand" "=A") 1548: (lshiftrt:HI (match_operand:HI 1 "register_operand" "A") 1549: (const_int 16)))] 1550: "" 1551: "%0=%1>>16\;%0=%b0&0x0000" 1552: [(set_attr "type" "special")]) 1553: 1554: (define_expand "lshrhi3" 1555: [(set (match_operand:HI 0 "register_operand" "") 1556: (lshiftrt:HI (match_operand:HI 1 "register_operand" "") 1557: (match_operand:QI 2 "nonmemory_operand" "")))] 1558: "" 1559: " 1560: { 1561: if (!TARGET_BMU) 1562: { 1563: /* If we are shifting by a constant we can do it in 1 or more 1564: 1600 core shift instructions. The core instructions can 1565: shift by 1, 4, 8, or 16. */ 1566: 1567: if (GET_CODE(operands[2]) == CONST_INT) 1568: emit_insn (gen_match_lshrhi3_nobmu (operands[0], operands[1], operands[2])); 1569: else 1570: { 1571: rtx label1 = gen_label_rtx (); 1572: rtx label2 = gen_label_rtx (); 1573: #if 0 1574: if (!dsp16xx_lshrhi3_libcall) 1575: dsp16xx_lshrhi3_libcall = gen_rtx (SYMBOL_REF, Pmode, LSHRHI3_LIBCALL); 1576: 1577: emit_library_call (dsp16xx_lshrhi3_libcall, 1, HImode, 2, 1578: operands[1], HImode, 1579: operands[2], QImode); 1580: emit_move_insn (operands[0], hard_libcall_value(HImode)); 1581: DONE; 1582: #else 1583: do_pending_stack_adjust (); 1584: emit_insn (gen_tstqi (operands[2])); 1585: emit_jump_insn (gen_bne (label1)); 1586: emit_move_insn (operands[0], operands[1]); 1587: emit_jump_insn (gen_jump (label2)); 1588: emit_barrier (); 1589: emit_label (label1); 1590: 1591: if (GET_CODE(operands[2]) != MEM) 1592: { 1593: rtx stack_slot; 1594: 1595: stack_slot = assign_stack_temp (QImode, GET_MODE_SIZE(QImode), 0); 1596: stack_slot = change_address (stack_slot, VOIDmode, XEXP (stack_slot, 0)); 1597: emit_move_insn (stack_slot, operands[2]); 1598: operands[2] = stack_slot; 1599: } 1600: 1601: emit_insn (gen_match_lshrhi3_nobmu (operands[0], operands[1], operands[2])); 1602: emit_label (label2); 1603: DONE; 1604: #endif 1605: } 1606: } 1607: }") 1608: 1609: (define_insn "match_lshrhi3" 1610: [(set (match_operand:HI 0 "register_operand" "=A,A,A") 1611: (lshiftrt:HI (match_operand:HI 1 "register_operand" "A,A,!A") 1612: (match_operand:QI 2 "nonmemory_operand" "B,I,h")))] 1613: "TARGET_BMU" 1614: "@ 1615: %0=%1>>>%2 1616: %0=%1>>>%H2 1617: %0=%1>>>%2" 1618: [(set_attr "type" "shift,shift_i,shift")]) 1619: 1620: (define_insn "match_lshrhi3_nobmu" 1621: [(set (match_operand:HI 0 "register_operand" "=A,A") 1622: (lshiftrt:HI (match_operand:HI 1 "register_operand" "A,0") 1623: (match_operand:QI 2 "general_operand" "n,m"))) 1624: (clobber (match_scratch:QI 3 "=X,Y"))] 1625: "!TARGET_BMU" 1626: "* 1627: { 1628: if (which_alternative == 0) 1629: { 1630: emit_1600_core_shift (LSHIFTRT, operands, INTVAL(operands[2])); 1631: return \"\"; 1632: } 1633: else 1634: { 1635: output_asm_insn (\"%3=psw\;psw=0\",operands); 1636: output_asm_insn (\"cloop=%2\", operands); 1637: output_asm_insn (\"do 0 \{\", operands); 1638: output_asm_insn (\"%0=%0>>1\", operands); 1639: output_asm_insn (\"\}\", operands); 1640: return \"psw=%3\"; 1641: } 1642: }") 1643: 1644: 1645: ;; 1646: ;; Arithmetic Left shift 1647: 1648: ;; Start off with special case arithmetic left shift by 1,4,8 or 16. 1649: 1650: 1651: (define_insn "" 1652: [(set (match_operand:HI 0 "register_operand" "=A") 1653: (ashift:HI (match_operand:HI 1 "register_operand" "A") 1654: (const_int 1)))] 1655: "" 1656: "%0=%1<<1" 1657: [(set_attr "type" "special")]) 1658: 1659: (define_insn "" 1660: [(set (match_operand:HI 0 "register_operand" "=A") 1661: (ashift:HI (match_operand:HI 1 "register_operand" "A") 1662: (const_int 4)))] 1663: "" 1664: "%0=%1<<4" 1665: [(set_attr "type" "special")]) 1666: 1667: (define_insn "" 1668: [(set (match_operand:HI 0 "register_operand" "=A") 1669: (ashift:HI (match_operand:HI 1 "register_operand" "A") 1670: (const_int 8)))] 1671: "" 1672: "%0=%1<<8" 1673: [(set_attr "type" "special")]) 1674: 1675: (define_insn "" 1676: [(set (match_operand:HI 0 "register_operand" "=A") 1677: (ashift:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "A")) 1678: (const_int 16)))] 1679: "" 1680: "%0=%1<<16" 1681: [(set_attr "type" "special")]) 1682: 1683: (define_insn "" 1684: [(set (match_operand:HI 0 "register_operand" "=A") 1685: (ashift:HI (match_operand:HI 1 "general_operand" "A") 1686: (const_int 16)))] 1687: "" 1688: "%0=%1<<16" 1689: [(set_attr "type" "special")]) 1690: 1691: 1692: 1693: ;; Normal Arithmetic Shift Left 1694: 1695: 1696: (define_expand "ashlhi3" 1697: [(set (match_operand:HI 0 "register_operand" "") 1698: (ashift:HI (match_operand:HI 1 "register_operand" "") 1699: (match_operand:QI 2 "nonmemory_operand" "")))] 1700: "" 1701: " 1702: { 1703: if (!TARGET_BMU) 1704: { 1705: /* If we are shifting by a constant we can do it in 1 or more 1706: 1600 core shift instructions. The core instructions can 1707: shift by 1, 4, 8, or 16. */ 1708: 1709: if (GET_CODE(operands[2]) == CONST_INT) 1710: ; 1711: else 1712: { 1713: rtx label1 = gen_label_rtx (); 1714: rtx label2 = gen_label_rtx (); 1715: #if 0 1716: if (!dsp16xx_ashlhi3_libcall) 1717: dsp16xx_ashlhi3_libcall = gen_rtx (SYMBOL_REF, Pmode, ASHLHI3_LIBCALL); 1718: 1719: emit_library_call (dsp16xx_ashlhi3_libcall, 1, HImode, 2, 1720: operands[1], HImode, 1721: operands[2], QImode); 1722: emit_move_insn (operands[0], hard_libcall_value(HImode)); 1723: DONE; 1724: #else 1725: do_pending_stack_adjust (); 1726: emit_insn (gen_tstqi (operands[2])); 1727: emit_jump_insn (gen_bne (label1)); 1728: emit_move_insn (operands[0], operands[1]); 1729: emit_jump_insn (gen_jump (label2)); 1730: emit_barrier (); 1731: emit_label (label1); 1732: 1733: if (GET_CODE(operands[2]) != MEM) 1734: { 1735: rtx stack_slot; 1736: 1737: stack_slot = assign_stack_temp (QImode, GET_MODE_SIZE(QImode), 0); 1738: stack_slot = change_address (stack_slot, VOIDmode, XEXP (stack_slot, 0)); 1739: emit_move_insn (stack_slot, operands[2]); 1740: operands[2] = stack_slot; 1741: } 1742: emit_insn (gen_match_ashlhi3_nobmu (operands[0], operands[1], operands[2])); 1743: emit_label (label2); 1744: DONE; 1745: #endif 1746: } 1747: } 1748: }") 1749: 1750: (define_insn "match_ashlhi3" 1751: [(set (match_operand:HI 0 "register_operand" "=A,A,A") 1752: (ashift:HI (match_operand:HI 1 "register_operand" "A,A,A") 1753: (match_operand:QI 2 "nonmemory_operand" "B,I,!h")))] 1754: "TARGET_BMU" 1755: "@ 1756: %0=%1<<%2\;move %u0=%u0 1757: %0=%1<<%H2\;move %u0=%u0 1758: %0=%1<<%2\;move %u0=%u0" 1759: [(set_attr "type" "shift,shift_i,shift")]) 1760: 1761: (define_insn "match_ashlhi3_nobmu" 1762: [(set (match_operand:HI 0 "register_operand" "=A,A") 1763: (ashift:HI (match_operand:HI 1 "register_operand" "A,0") 1764: (match_operand:QI 2 "general_operand" "n,m")))] 1765: "!TARGET_BMU" 1766: "* 1767: { 1768: if (which_alternative == 0) 1769: { 1770: emit_1600_core_shift (ASHIFT, operands, INTVAL(operands[2])); 1771: return \"\"; 1772: } 1773: else 1774: { 1775: output_asm_insn (\"cloop=%2\", operands); 1776: output_asm_insn (\"do 0 \{\", operands); 1777: output_asm_insn (\"%0=%0<<1\", operands); 1778: return \"\}\"; 1779: } 1780: }") 1781: 1782: 1783: 1784: ;; 1785: ;; Jump Instructions 1786: ;; 1787: 1788: (define_expand "beq" 1789: [(set (pc) 1790: (if_then_else (eq (match_dup 1) 1791: (const_int 0)) 1792: (label_ref (match_operand 0 "" "")) 1793: (pc)))] 1794: "" 1795: " 1796: { 1797: if (dsp16xx_compare_gen == gen_compare_reg) 1798: operands[1] = (*dsp16xx_compare_gen)(EQ, dsp16xx_compare_op0, dsp16xx_compare_op1); 1799: else 1800: operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 1801: }") 1802: 1803: (define_expand "bne" 1804: [(set (pc) 1805: (if_then_else (ne (match_dup 1) 1806: (const_int 0)) 1807: (label_ref (match_operand 0 "" "")) 1808: (pc)))] 1809: "" 1810: " 1811: { 1812: if (dsp16xx_compare_gen == gen_compare_reg) 1813: operands[1] = (*dsp16xx_compare_gen)(NE, dsp16xx_compare_op0, dsp16xx_compare_op1); 1814: else 1815: operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 1816: }") 1817: 1818: 1819: (define_expand "bgt" 1820: [(set (pc) 1821: (if_then_else (gt (match_dup 1) 1822: (const_int 0)) 1823: (label_ref (match_operand 0 "" "")) 1824: (pc)))] 1825: "" 1826: " 1827: { 1828: if (dsp16xx_compare_gen == gen_compare_reg) 1829: operands[1] = (*dsp16xx_compare_gen)(GT, dsp16xx_compare_op0, dsp16xx_compare_op1); 1830: else 1831: operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 1832: }") 1833: 1834: 1835: (define_expand "bge" 1836: [(set (pc) 1837: (if_then_else (ge (match_dup 1) 1838: (const_int 0)) 1839: (label_ref (match_operand 0 "" "")) 1840: (pc)))] 1841: "" 1842: " 1843: { 1844: if (dsp16xx_compare_gen == gen_compare_reg) 1845: operands[1] = (*dsp16xx_compare_gen)(GE, dsp16xx_compare_op0, dsp16xx_compare_op1); 1846: else 1847: operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 1848: }") 1849: 1850: 1851: (define_expand "blt" 1852: [(set (pc) 1853: (if_then_else (lt (match_dup 1) 1854: (const_int 0)) 1855: (label_ref (match_operand 0 "" "")) 1856: (pc)))] 1857: "" 1858: " 1859: { 1860: if (dsp16xx_compare_gen == gen_compare_reg) 1861: operands[1] = (*dsp16xx_compare_gen)(LT, dsp16xx_compare_op0, dsp16xx_compare_op1); 1862: else 1863: operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 1864: }") 1865: 1866: 1867: (define_expand "ble" 1868: [(set (pc) 1869: (if_then_else (le (match_dup 1) 1870: (const_int 0)) 1871: (label_ref (match_operand 0 "" "")) 1872: (pc)))] 1873: "" 1874: " 1875: { 1876: if (dsp16xx_compare_gen == gen_compare_reg) 1877: operands[1] = (*dsp16xx_compare_gen)(LE, dsp16xx_compare_op0, dsp16xx_compare_op1); 1878: else 1879: operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 1880: }") 1881: 1882: 1883: (define_expand "bgtu" 1884: [(set (pc) 1885: (if_then_else (gtu (match_dup 1) 1886: (const_int 0)) 1887: (label_ref (match_operand 0 "" "")) 1888: (pc)))] 1889: "" 1890: " 1891: { 1892: if (dsp16xx_compare_gen == gen_compare_reg) 1893: operands[1] = (*dsp16xx_compare_gen)(GTU, dsp16xx_compare_op0, dsp16xx_compare_op1); 1894: else 1895: operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 1896: }") 1897: 1898: 1899: (define_expand "bgeu" 1900: [(set (pc) 1901: (if_then_else (geu (match_dup 1) 1902: (const_int 0)) 1903: (label_ref (match_operand 0 "" "")) 1904: (pc)))] 1905: "" 1906: " 1907: { 1908: if (dsp16xx_compare_gen == gen_compare_reg) 1909: operands[1] = (*dsp16xx_compare_gen)(GEU, dsp16xx_compare_op0, dsp16xx_compare_op1); 1910: else 1911: operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 1912: }") 1913: 1914: 1915: (define_expand "bltu" 1916: [(set (pc) 1917: (if_then_else (ltu (match_dup 1) 1918: (const_int 0)) 1919: (label_ref (match_operand 0 "" "")) 1920: (pc)))] 1921: "" 1922: " 1923: { 1924: if (dsp16xx_compare_gen == gen_compare_reg) 1925: operands[1] = (*dsp16xx_compare_gen)(LTU, dsp16xx_compare_op0, dsp16xx_compare_op1); 1926: else 1927: operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 1928: }") 1929: 1930: 1931: (define_expand "bleu" 1932: [(set (pc) 1933: (if_then_else (leu (match_dup 1) 1934: (const_int 0)) 1935: (label_ref (match_operand 0 "" "")) 1936: (pc)))] 1937: "" 1938: " 1939: { 1940: if (dsp16xx_compare_gen == gen_compare_reg) 1941: operands[1] = (*dsp16xx_compare_gen)(LEU, dsp16xx_compare_op0, dsp16xx_compare_op1); 1942: else 1943: operands[1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0); 1944: }") 1945: 1946: 1947: (define_insn "" 1948: [(set (pc) 1949: (if_then_else (match_operator 1 "comparison_operator" 1950: [(cc0) (const_int 0)]) 1951: (label_ref (match_operand 0 "" "")) 1952: (pc)))] 1953: "!TARGET_NEAR_JUMP" 1954: "pt=%l0\;if %C1 goto pt" 1955: [(set_attr "type" "cond_jump")]) 1956: 1957: (define_insn "" 1958: [(set (pc) 1959: (if_then_else (match_operator 1 "comparison_operator" 1960: [(cc0) (const_int 0)]) 1961: (label_ref (match_operand 0 "" "")) 1962: (pc)))] 1963: "TARGET_NEAR_JUMP" 1964: "if %C1 goto %l0" 1965: [(set_attr "type" "cond_jump")]) 1966: 1967: ;; 1968: ;; Negated conditional jump instructions. 1969: ;; These are necessary because jump optimization can turn 1970: ;; direct-conditional branches into reverse-conditional 1971: ;; branches. 1972: 1973: (define_insn "" 1974: [(set (pc) 1975: (if_then_else (match_operator 1 "comparison_operator" 1976: [(cc0) (const_int 0)]) 1977: (pc) 1978: (label_ref (match_operand 0 "" ""))))] 1979: "!TARGET_NEAR_JUMP" 1980: "pt=%l0\;if %I1 goto pt" 1981: [(set_attr "type" "cond_jump")]) 1982: 1983: (define_insn "" 1984: [(set (pc) 1985: (if_then_else (match_operator 1 "comparison_operator" 1986: [(cc0) (const_int 0)]) 1987: (pc) 1988: (label_ref (match_operand 0 "" ""))))] 1989: "TARGET_NEAR_JUMP" 1990: "if %I1 goto %l0" 1991: [(set_attr "type" "cond_jump")]) 1992: 1993: 1994: ;; 1995: ;; JUMPS 1996: ;; 1997: 1998: (define_insn "jump" 1999: [(set (pc) 2000: (label_ref (match_operand 0 "" "")))] 2001: "" 2002: "* 2003: { 2004: if (TARGET_NEAR_JUMP) 2005: return \"goto %l0\"; 2006: else 2007: return \"pt=%l0\;goto pt\"; 2008: }" 2009: [(set_attr "type" "jump")]) 2010: 2011: 2012: (define_insn "indirect_jump" 2013: [(set (pc) (match_operand:QI 0 "register_operand" "A"))] 2014: "" 2015: "pt=%0\;goto pt" 2016: [(set_attr "type" "jump")]) 2017: 2018: (define_insn "tablejump" 2019: [(set (pc) (match_operand:QI 0 "register_operand" "A")) 2020: (use (label_ref (match_operand 1 "" "")))] 2021: "" 2022: "pt=%0\;goto pt" 2023: [(set_attr "type" "jump")]) 2024: 2025: ;; 2026: ;; FUNCTION CALLS 2027: ;; 2028: 2029: ;; Call subroutine with no return value. 2030: 2031: 2032: (define_expand "call" 2033: [(parallel [(call (match_operand:QI 0 "" "") 2034: (match_operand 1 "" "")) 2035: (clobber (reg:QI 24))])] 2036: "" 2037: " 2038: { 2039: if (GET_CODE (operands[0]) == MEM 2040: && ! call_address_operand (XEXP (operands[0], 0), QImode)) 2041: operands[0] = gen_rtx (MEM, GET_MODE (operands[0]), 2042: force_reg (Pmode, XEXP (operands[0], 0))); 2043: }") 2044: 2045: (define_insn "" 2046: [(parallel [(call (mem:QI (match_operand:QI 0 "call_address_operand" "hR")) 2047: (match_operand 1 "" "")) 2048: (clobber (reg:QI 24))])] 2049: "" 2050: "* 2051: { 2052: if (GET_CODE (operands[0]) == REG || 2053: (GET_CODE(operands[0]) == SYMBOL_REF && !TARGET_NEAR_CALL)) 2054: return \"pt=%0\;call pt\"; 2055: else 2056: return \"call %0\"; 2057: }" 2058: [(set_attr "type" "call")]) 2059: 2060: ;; Call subroutine with return value. 2061: 2062: (define_expand "call_value" 2063: [(parallel [(set (match_operand 0 "register_operand" "=f") 2064: (call (match_operand:QI 1 "call_address_operand" "hR") 2065: (match_operand:QI 2 "" ""))) 2066: (clobber (reg:QI 24))])] 2067: "" 2068: " 2069: { 2070: if (GET_CODE (operands[1]) == MEM 2071: && ! call_address_operand (XEXP (operands[1], 0), QImode)) 2072: operands[1] = gen_rtx (MEM, GET_MODE (operands[1]), 2073: force_reg (Pmode, XEXP (operands[1], 0))); 2074: }") 2075: 2076: (define_insn "" 2077: [(parallel [(set (match_operand 0 "register_operand" "=f") 2078: (call (mem:QI (match_operand:QI 1 "call_address_operand" "hR")) 2079: (match_operand:QI 2 "" ""))) 2080: (clobber (reg:QI 24))])] 2081: "" 2082: "* 2083: { 2084: if (GET_CODE (operands[1]) == REG || 2085: (GET_CODE(operands[1]) == SYMBOL_REF && !TARGET_NEAR_CALL)) 2086: return \"pt=%1\;call pt\"; 2087: else 2088: return \"call %1\"; 2089: }" 2090: [(set_attr "type" "call")]) 2091: 2092: 2093: (define_expand "untyped_call" 2094: [(parallel [(call (match_operand 0 "" "") 2095: (const_int 0)) 2096: (match_operand 1 "" "") 2097: (match_operand 2 "" "")])] 2098: "" 2099: " 2100: { 2101: int i; 2102: 2103: emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); 2104: 2105: for (i = 0; i < XVECLEN (operands[2], 0); i++) 2106: { 2107: rtx set = XVECEXP (operands[2], 0, i); 2108: emit_move_insn (SET_DEST (set), SET_SRC (set)); 2109: } 2110: 2111: /* The optimizer does not know that the call sets the function value 2112: registers we stored in the result block. We avoid problems by 2113: claiming that all hard registers are used and clobbered at this 2114: point. */ 2115: emit_insn (gen_blockage ()); 2116: 2117: DONE; 2118: }") 2119: 2120: ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 2121: ;; all of memory. This blocks insns from being moved across this point. 2122: 2123: (define_insn "blockage" 2124: [(unspec_volatile [(const_int 0)] 0)] 2125: "" 2126: "") 2127: 2128: (define_insn "nop" 2129: [(const_int 0)] 2130: "" 2131: "nop" 2132: [(set_attr "type" "nop")]) 2133: 2134: ;; 2135: ;; PEEPHOLE PATTERNS 2136: ;; 2137: 2138: 2139: (define_peephole 2140: [(set (match_operand:QI 0 "register_operand" "=A") 2141: (reg:QI 16)) 2142: (call (mem:QI (match_dup 0)) 2143: (match_operand 1 "" "i"))] 2144: "" 2145: "call pt") 2146: 2147: 2148: (define_peephole 2149: [(set (match_operand:QI 0 "register_operand" "=A") 2150: (reg:QI 16)) 2151: (set (match_operand 1 "" "") 2152: (call (mem:QI (match_dup 0)) 2153: (match_operand 2 "" "i")))] 2154: "" 2155: "call pt") 2156: 2157: (define_peephole 2158: [(set (match_operand:HI 0 "register_operand" "=A") 2159: (ashift:HI (match_operand:HI 1 "register_operand" "A") 2160: (const_int 16))) 2161: (set (match_operand:HI 2 "register_operand" "") 2162: (match_dup 0)) 2163: (set (match_dup 0) 2164: (ashiftrt:HI (match_dup 0) (const_int 16))) 2165: (set (match_dup 2) 2166: (match_dup 0))] 2167: "" 2168: "%0=%1<<16\;%0=%0>>16\;%u2=%u0\;%w2=%w0") 2169: 2170: (define_peephole 2171: [(set (match_operand:HI 0 "register_operand" "=A") 2172: (ashift:HI (match_operand:HI 1 "register_operand" "A") 2173: (const_int 16))) 2174: (set (match_operand:HI 2 "register_operand" "") 2175: (match_dup 0)) 2176: (set (match_dup 0) 2177: (lshiftrt:HI (match_dup 0) (const_int 16))) 2178: (set (match_dup 2) 2179: (match_dup 0))] 2180: "" 2181: "%0=%1<<16\;%0=%0>>16\;%0=%b0&0x0000\;%u2=%u0\;%w2=%w0")
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