![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to elxsi.md CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [GCC 2.x] / gcc / config / elxsi|
Return to elxsi.md CVS log | Up to [GCC 2.x] / gcc / config / elxsi |
1.1.1.2 ! root 1: ;;- Machine description for GNU compiler, Elxsi Version ! 2: ;; Copyright (C) 1987, 1988, 1992, 1994 Free Software Foundation, Inc. ! 3: ;; Contributed by Mike Stump <[email protected]> in 1988, and is the first 1.1 root 4: ;; 64 bit port of GNU CC. 5: ;; Based upon the VAX port. 6: 7: ;; This file is part of GNU CC. 8: 9: ;; GNU CC is free software; you can redistribute it and/or modify 10: ;; it under the terms of the GNU General Public License as published by 11: ;; the Free Software Foundation; either version 1, or (at your option) 12: ;; any later version. 13: 14: ;; GNU CC is distributed in the hope that it will be useful, 15: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 16: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17: ;; GNU General Public License for more details. 18: 19: ;; You should have received a copy of the GNU General Public License 20: ;; along with GNU CC; see the file COPYING. If not, write to 21: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 22: 23: 24: ;;- Instruction patterns. When multiple patterns apply, 25: ;;- the first one in the file is chosen. 26: ;;- 27: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 28: ;;- 29: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code 30: ;;- updates for most instructions. 31: 32: 33: (define_insn "" 34: [(set (reg:SI 15) 35: (plus:SI (reg:SI 15) 36: (match_operand:SI 0 "general_operand" "g")))] 37: "" 38: "add.64\\t.sp,%0") 39: 40: (define_insn "" 41: [(set (reg:SI 15) 42: (plus:SI (match_operand:SI 0 "general_operand" "g") 43: (reg:SI 15)))] 44: "" 45: "add.64\\t.sp,%0") 46: 47: (define_insn "" 48: [(set (match_operand:SI 0 "register_operand" "r") 49: (plus:SI (reg:SI 15) 50: (match_operand:SI 1 "general_operand" "g")))] 51: "" 52: "ld.32\\t%0,.sp\;add.64\\t%0,%1") 53: 54: (define_insn "" 55: [(set (match_operand:SI 0 "register_operand" "r") 56: (plus:SI (match_operand:SI 1 "general_operand" "g") 57: (reg:SI 15)))] 58: "" 59: "ld.32\\t%0,.sp\;add.64\\t%0,%1") 60: 61: (define_insn "" 62: [(set (reg:SI 15) 63: (minus:SI (reg:SI 15) 64: (match_operand:SI 0 "general_operand" "g")))] 65: "" 66: "sub.64\\t.sp,%0") 67: 68: (define_insn "" 69: [(set (reg:SI 15) 70: (match_operand:SI 0 "general_operand" "rm"))] 71: "" 72: "ld.32\\t.sp,%0") 73: 74: (define_insn "" 75: [(set (match_operand:SI 0 "general_operand" "m,r") 76: (reg:SI 15))] 77: "" 78: "* 79: if (which_alternative == 0) 80: return \"st.32\\t.sp,%0\"; 81: return \"ld.32\\t%0,.sp\"; 82: ") 83: 84: ; tstdi is first test insn so that it is the one to match 85: ; a constant argument. 86: 87: (define_insn "tstdi" 88: [(set (cc0) 89: (match_operand:DI 0 "register_operand" "r"))] 90: "" 91: "* 92: extern rtx cmp_op0, cmp_op1; 93: cmp_op0=operands[0]; cmp_op1=0; 94: return \";\\ttstdi\\t%0\"; 95: ") 96: 97: (define_insn "tstdf" 98: [(set (cc0) 99: (match_operand:DF 0 "register_operand" "r"))] 100: "" 101: "* 102: extern rtx cmp_op0, cmp_op1; 103: cmp_op0=operands[0]; cmp_op1=0; 104: return \";\\ttstdf\\t%0\"; 105: ") 106: 107: (define_insn "tstsf" 108: [(set (cc0) 109: (match_operand:SF 0 "register_operand" "r"))] 110: "" 111: "* 112: extern rtx cmp_op0, cmp_op1; 113: cmp_op0=operands[0]; cmp_op1=0; 114: return \";\\ttstsf\\t%0\"; 115: ") 116: 117: (define_insn "cmpdi" 118: [(set (cc0) 119: (compare (match_operand:DI 0 "register_operand" "r") 120: (match_operand:DI 1 "general_operand" "rm")))] 121: "" 122: "* 123: extern rtx cmp_op0, cmp_op1; 124: cmp_op0=operands[0]; cmp_op1=operands[1]; 125: return \";\\tcmpdi\\t%0,%1\"; 126: ") 127: 128: (define_insn "cmpdf" 129: [(set (cc0) 130: (compare (match_operand:DF 0 "register_operand" "r") 131: (match_operand:DF 1 "general_operand" "rm")))] 132: "" 133: "* 134: extern rtx cmp_op0, cmp_op1; 135: cmp_op0=operands[0]; cmp_op1=operands[1]; 136: return \";\\tcmpdf\\t%0,%1\"; 137: ") 138: 139: (define_insn "cmpsf" 140: [(set (cc0) 141: (compare (match_operand:SF 0 "register_operand" "r") 142: (match_operand:SF 1 "general_operand" "rm")))] 143: "" 144: "* 145: extern rtx cmp_op0, cmp_op1; 146: cmp_op0=operands[0]; cmp_op1=operands[1]; 147: return \";\\tcmpsf\\t%0,%1\"; 148: ") 149: 150: (define_insn "" 151: [(set (match_operand:DI 0 "register_operand" "=r") 152: (eq (match_operand:DI 1 "register_operand" "r") 153: (match_operand:DI 2 "general_operand" "g")))] 154: "" 155: "cmp.64\\t%0,%1,%2:eq") 156: 157: (define_insn "" 158: [(set (match_operand:DI 0 "register_operand" "=r") 159: (ne (match_operand:DI 1 "register_operand" "r") 160: (match_operand:DI 2 "general_operand" "g")))] 161: "" 162: "cmp.64\\t%0,%1,%2:ne") 163: 164: (define_insn "" 165: [(set (match_operand:DI 0 "register_operand" "=r") 166: (le (match_operand:DI 1 "register_operand" "r") 167: (match_operand:DI 2 "general_operand" "g")))] 168: "" 169: "cmp.64\\t%0,%1,%2:le") 170: 171: (define_insn "" 172: [(set (match_operand:DI 0 "register_operand" "=r") 173: (leu (match_operand:DI 1 "register_operand" "r") 174: (match_operand:DI 2 "general_operand" "g")))] 175: "" 176: "cmpu.64\\t%0,%1,%2:le") 177: 178: (define_insn "" 179: [(set (match_operand:DI 0 "register_operand" "=r") 180: (lt (match_operand:DI 1 "register_operand" "r") 181: (match_operand:DI 2 "general_operand" "g")))] 182: "" 183: "cmp.64\\t%0,%1,%2:lt") 184: 185: (define_insn "" 186: [(set (match_operand:DI 0 "register_operand" "=r") 187: (ltu (match_operand:DI 1 "register_operand" "r") 188: (match_operand:DI 2 "general_operand" "g")))] 189: "" 190: "cmpu.64\\t%0,%1,%2:lt") 191: 192: (define_insn "" 193: [(set (match_operand:DI 0 "register_operand" "=r") 194: (ge (match_operand:DI 1 "register_operand" "r") 195: (match_operand:DI 2 "general_operand" "g")))] 196: "" 197: "cmp.64\\t%0,%1,%2:ge") 198: 199: (define_insn "" 200: [(set (match_operand:DI 0 "register_operand" "=r") 201: (geu (match_operand:DI 1 "register_operand" "r") 202: (match_operand:DI 2 "general_operand" "g")))] 203: "" 204: "cmpu.64\\t%0,%1,%2:ge") 205: 206: (define_insn "" 207: [(set (match_operand:DI 0 "register_operand" "=r") 208: (gt (match_operand:DI 1 "register_operand" "r") 209: (match_operand:DI 2 "general_operand" "g")))] 210: "" 211: "cmp.64\\t%0,%1,%2:gt") 212: 213: (define_insn "" 214: [(set (match_operand:DI 0 "register_operand" "=r") 215: (gtu (match_operand:DI 1 "register_operand" "r") 216: (match_operand:DI 2 "general_operand" "g")))] 217: "" 218: "cmpu.64\\t%0,%1,%2:gt") 219: 220: (define_insn "seq" 221: [(set (match_operand:DI 0 "register_operand" "=r") 222: (eq (cc0) (const_int 0)))] 223: "" 224: "* return cmp_set(\"\", \"eq\", operands[0]); ") 225: 226: (define_insn "sne" 227: [(set (match_operand:DI 0 "register_operand" "=r") 228: (ne (cc0) (const_int 0)))] 229: "" 230: "* return cmp_set(\"\", \"ne\", operands[0]); ") 231: 232: (define_insn "sle" 233: [(set (match_operand:DI 0 "register_operand" "=r") 234: (le (cc0) (const_int 0)))] 235: "" 236: "* return cmp_set(\"\", \"le\", operands[0]); ") 237: 238: (define_insn "sleu" 239: [(set (match_operand:DI 0 "register_operand" "=r") 240: (leu (cc0) (const_int 0)))] 241: "" 242: "* return cmp_set(\"u\", \"le\", operands[0]); ") 243: 244: (define_insn "slt" 245: [(set (match_operand:DI 0 "register_operand" "=r") 246: (lt (cc0) (const_int 0)))] 247: "" 248: "* return cmp_set(\"\", \"lt\", operands[0]); ") 249: 250: (define_insn "sltu" 251: [(set (match_operand:DI 0 "register_operand" "=r") 252: (ltu (cc0) (const_int 0)))] 253: "" 254: "* return cmp_set(\"u\", \"lt\", operands[0]); ") 255: 256: (define_insn "sge" 257: [(set (match_operand:DI 0 "register_operand" "=r") 258: (ge (cc0) (const_int 0)))] 259: "" 260: "* return cmp_set(\"\", \"ge\", operands[0]); ") 261: 262: (define_insn "sgeu" 263: [(set (match_operand:DI 0 "register_operand" "=r") 264: (geu (cc0) (const_int 0)))] 265: "" 266: "* return cmp_set(\"u\", \"ge\", operands[0]); ") 267: 268: (define_insn "sgt" 269: [(set (match_operand:DI 0 "register_operand" "=r") 270: (gt (cc0) (const_int 0)))] 271: "" 272: "* return cmp_set(\"\", \"gt\", operands[0]); ") 273: 274: (define_insn "sgtu" 275: [(set (match_operand:DI 0 "register_operand" "=r") 276: (gtu (cc0) (const_int 0)))] 277: "" 278: "* return cmp_set(\"u\", \"gt\", operands[0]); ") 279: 280: (define_insn "" 281: [(set (match_operand:SI 0 "register_operand" "=r") 282: (eq (match_operand:SI 1 "register_operand" "r") 283: (match_operand:SI 2 "general_operand" "m")))] 284: "" 285: "cmp.32\\t%0,%1,%2:eq") 286: 287: (define_insn "" 288: [(set (match_operand:SI 0 "register_operand" "=r") 289: (ne (match_operand:SI 1 "register_operand" "r") 290: (match_operand:SI 2 "general_operand" "m")))] 291: "" 292: "cmp.32\\t%0,%1,%2:ne") 293: 294: (define_insn "" 295: [(set (match_operand:SI 0 "register_operand" "=r") 296: (le (match_operand:SI 1 "register_operand" "r") 297: (match_operand:SI 2 "general_operand" "m")))] 298: "" 299: "cmp.32\\t%0,%1,%2:le") 300: 301: (define_insn "" 302: [(set (match_operand:SI 0 "register_operand" "=r") 303: (leu (match_operand:SI 1 "register_operand" "r") 304: (match_operand:SI 2 "general_operand" "m")))] 305: "" 306: "cmpu.32\\t%0,%1,%2:le") 307: 308: (define_insn "" 309: [(set (match_operand:SI 0 "register_operand" "=r") 310: (lt (match_operand:SI 1 "register_operand" "r") 311: (match_operand:SI 2 "general_operand" "m")))] 312: "" 313: "cmp.32\\t%0,%1,%2:lt") 314: 315: (define_insn "" 316: [(set (match_operand:SI 0 "register_operand" "=r") 317: (ltu (match_operand:SI 1 "register_operand" "r") 318: (match_operand:SI 2 "general_operand" "m")))] 319: "" 320: "cmpu.32\\t%0,%1,%2:lt") 321: 322: (define_insn "" 323: [(set (match_operand:SI 0 "register_operand" "=r") 324: (ge (match_operand:SI 1 "register_operand" "r") 325: (match_operand:SI 2 "general_operand" "m")))] 326: "" 327: "cmp.32\\t%0,%1,%2:ge") 328: 329: (define_insn "" 330: [(set (match_operand:SI 0 "register_operand" "=r") 331: (geu (match_operand:SI 1 "register_operand" "r") 332: (match_operand:SI 2 "general_operand" "m")))] 333: "" 334: "cmpu.32\\t%0,%1,%2:ge") 335: 336: (define_insn "" 337: [(set (match_operand:SI 0 "register_operand" "=r") 338: (gt (match_operand:SI 1 "register_operand" "r") 339: (match_operand:SI 2 "general_operand" "m")))] 340: "" 341: "cmp.32\\t%0,%1,%2:gt") 342: 343: (define_insn "" 344: [(set (match_operand:SI 0 "register_operand" "=r") 345: (gtu (match_operand:SI 1 "register_operand" "r") 346: (match_operand:SI 2 "general_operand" "m")))] 347: "" 348: "cmpu.32\\t%0,%1,%2:gt") 349: 350: (define_insn "" 351: [(set (match_operand:HI 0 "register_operand" "=r") 352: (eq (match_operand:HI 1 "register_operand" "r") 353: (match_operand:HI 2 "general_operand" "m")))] 354: "" 355: "cmp.16\\t%0,%1,%2:eq") 356: 357: (define_insn "" 358: [(set (match_operand:HI 0 "register_operand" "=r") 359: (ne (match_operand:HI 1 "register_operand" "r") 360: (match_operand:HI 2 "general_operand" "m")))] 361: "" 362: "cmp.16\\t%0,%1,%2:ne") 363: 364: (define_insn "" 365: [(set (match_operand:HI 0 "register_operand" "=r") 366: (le (match_operand:HI 1 "register_operand" "r") 367: (match_operand:HI 2 "general_operand" "m")))] 368: "" 369: "cmp.16\\t%0,%1,%2:le") 370: 371: (define_insn "" 372: [(set (match_operand:HI 0 "register_operand" "=r") 373: (leu (match_operand:HI 1 "register_operand" "r") 374: (match_operand:HI 2 "general_operand" "m")))] 375: "" 376: "cmpu.16\\t%0,%1,%2:le") 377: 378: (define_insn "" 379: [(set (match_operand:HI 0 "register_operand" "=r") 380: (lt (match_operand:HI 1 "register_operand" "r") 381: (match_operand:HI 2 "general_operand" "m")))] 382: "" 383: "cmp.16\\t%0,%1,%2:lt") 384: 385: (define_insn "" 386: [(set (match_operand:HI 0 "register_operand" "=r") 387: (ltu (match_operand:HI 1 "register_operand" "r") 388: (match_operand:HI 2 "general_operand" "m")))] 389: "" 390: "cmpu.16\\t%0,%1,%2:lt") 391: 392: (define_insn "" 393: [(set (match_operand:HI 0 "register_operand" "=r") 394: (ge (match_operand:HI 1 "register_operand" "r") 395: (match_operand:HI 2 "general_operand" "m")))] 396: "" 397: "cmp.16\\t%0,%1,%2:ge") 398: 399: (define_insn "" 400: [(set (match_operand:HI 0 "register_operand" "=r") 401: (geu (match_operand:HI 1 "register_operand" "r") 402: (match_operand:HI 2 "general_operand" "m")))] 403: "" 404: "cmpu.16\\t%0,%1,%2:ge") 405: 406: (define_insn "" 407: [(set (match_operand:HI 0 "register_operand" "=r") 408: (gt (match_operand:HI 1 "register_operand" "r") 409: (match_operand:HI 2 "general_operand" "m")))] 410: "" 411: "cmp.16\\t%0,%1,%2:gt") 412: 413: (define_insn "" 414: [(set (match_operand:HI 0 "register_operand" "=r") 415: (gtu (match_operand:HI 1 "register_operand" "r") 416: (match_operand:HI 2 "general_operand" "m")))] 417: "" 418: "cmpu.16\\t%0,%1,%2:gt") 419: 420: (define_insn "" 421: [(set (match_operand:QI 0 "register_operand" "=r") 422: (eq (match_operand:QI 1 "register_operand" "r") 423: (match_operand:QI 2 "general_operand" "m")))] 424: "" 425: "cmp.8\\t%0,%1,%2:eq") 426: 427: (define_insn "" 428: [(set (match_operand:QI 0 "register_operand" "=r") 429: (ne (match_operand:QI 1 "register_operand" "r") 430: (match_operand:QI 2 "general_operand" "m")))] 431: "" 432: "cmp.8\\t%0,%1,%2:ne") 433: 434: (define_insn "" 435: [(set (match_operand:QI 0 "register_operand" "=r") 436: (le (match_operand:QI 1 "register_operand" "r") 437: (match_operand:QI 2 "general_operand" "m")))] 438: "" 439: "cmp.8\\t%0,%1,%2:le") 440: 441: (define_insn "" 442: [(set (match_operand:QI 0 "register_operand" "=r") 443: (leu (match_operand:QI 1 "register_operand" "r") 444: (match_operand:QI 2 "general_operand" "m")))] 445: "" 446: "cmpu.8\\t%0,%1,%2:le") 447: 448: (define_insn "" 449: [(set (match_operand:QI 0 "register_operand" "=r") 450: (lt (match_operand:QI 1 "register_operand" "r") 451: (match_operand:QI 2 "general_operand" "m")))] 452: "" 453: "cmp.8\\t%0,%1,%2:lt") 454: 455: (define_insn "" 456: [(set (match_operand:QI 0 "register_operand" "=r") 457: (ltu (match_operand:QI 1 "register_operand" "r") 458: (match_operand:QI 2 "general_operand" "m")))] 459: "" 460: "cmpu.8\\t%0,%1,%2:lt") 461: 462: (define_insn "" 463: [(set (match_operand:QI 0 "register_operand" "=r") 464: (ge (match_operand:QI 1 "register_operand" "r") 465: (match_operand:QI 2 "general_operand" "m")))] 466: "" 467: "cmp.8\\t%0,%1,%2:ge") 468: 469: (define_insn "" 470: [(set (match_operand:QI 0 "register_operand" "=r") 471: (geu (match_operand:QI 1 "register_operand" "r") 472: (match_operand:QI 2 "general_operand" "m")))] 473: "" 474: "cmpu.8\\t%0,%1,%2:ge") 475: 476: (define_insn "" 477: [(set (match_operand:QI 0 "register_operand" "=r") 478: (gt (match_operand:QI 1 "register_operand" "r") 479: (match_operand:QI 2 "general_operand" "m")))] 480: "" 481: "cmp.8\\t%0,%1,%2:gt") 482: 483: (define_insn "" 484: [(set (match_operand:QI 0 "register_operand" "=r") 485: (gtu (match_operand:QI 1 "register_operand" "r") 486: (match_operand:QI 2 "general_operand" "m")))] 487: "" 488: "cmpu.8\\t%0,%1,%2:gt") 489: 490: 491: 492: (define_insn "movdf" [(set (match_operand:DF 0 "general_operand" "=r,m") 493: (match_operand:DF 1 "general_operand" "rm,r"))] 494: "" 495: "* 496: { 497: if (which_alternative == 0) 498: return \"ld.64\\t%0,%1\"; 499: return \"st.64\\t%1,%0\"; 500: }") 501: 502: (define_insn "movsf" 503: [(set (match_operand:SF 0 "general_operand" "=r,m") 504: (match_operand:SF 1 "general_operand" "rm,r"))] 505: "" 506: "* 507: { 508: if (which_alternative == 0) 509: return \"ld.32\\t%0,%1\"; 510: return \"st.32\\t%1,%0\"; 511: }") 512: 513: (define_insn "movdi" 514: [(set (match_operand:DI 0 "general_operand" "=r,m,rm") 515: (match_operand:DI 1 "general_operand" "g,r,I"))] 516: "" 517: "* 518: if (which_alternative == 0) 519: return \"ld.64\\t%0,%1\"; 520: else if (which_alternative == 1) 521: return \"st.64\\t%1,%0\"; 522: else 523: if (GET_CODE(operands[1])==CONST_INT) { 524: if (INTVAL(operands[1]) >= 0) 525: return \"sti.64\\t%c1,%0\"; 526: else 527: return \"stin.64\\t%n1,%0\"; 528: } 529: ") 530: 531: (define_insn "movsi" 532: [(set (match_operand:SI 0 "general_operand" "=r,m,r") 533: (match_operand:SI 1 "general_operand" "rm,rI,i"))] 534: "" 535: "* 536: if (which_alternative == 0) 537: return \"ld.32\\t%0,%1\"; 538: else if (which_alternative == 1) { 539: if (GET_CODE(operands[1])==CONST_INT) { 540: if (INTVAL(operands[1]) >= 0) 541: return \"sti.32\\t%c1,%0\"; 542: else 543: return \"stin.32\\t%n1,%0\"; 544: } 545: return \"st.32\\t%1,%0\"; 546: } else 547: return \"ld.64\\t%0,%1 ; I only want 32\"; 548: ") 549: 550: (define_insn "movhi" 551: [(set (match_operand:HI 0 "general_operand" "=r,m,r") 552: (match_operand:HI 1 "general_operand" "m,rI,ri"))] 553: "" 554: "* 555: { 556: if (which_alternative == 0) 557: return \"ld.16\\t%0,%1\"; 558: if (which_alternative == 2) 559: return \"ld.64\\t%0,%1\\t; I only want 16\"; 560: if (GET_CODE(operands[1])==CONST_INT) { 561: if (INTVAL(operands[1]) >= 0) 562: return \"sti.16\\t%c1,%0\"; 563: else 564: return \"stin.16\\t%n1,%0\"; 565: } 566: return \"st.16\\t%1,%0\"; 567: }") 568: 569: (define_insn "movqi" 570: [(set (match_operand:QI 0 "general_operand" "=r,m,r") 571: (match_operand:QI 1 "general_operand" "m,rI,ri"))] 572: "" 573: "* 574: { 575: if (which_alternative == 0) 576: return \"ld.8\\t%0,%1\"; 577: if (which_alternative == 2) 578: return \"ld.64\\t%0,%1\\t; I only want 8\"; 579: if (GET_CODE(operands[1])==CONST_INT) { 580: if (INTVAL(operands[1]) >= 0) 581: return \"sti.8\\t%c1,%0\"; 582: else 583: return \"stin.8\\t%n1,%0\"; 584: } 585: return \"st.8\\t%1,%0\"; 586: }") 587: 588: ;; Extension and truncation insns. 589: ;; Those for integer source operand 590: ;; are ordered widest source type first. 591: 592: (define_insn "truncdfsf2" 593: [(set (match_operand:SF 0 "register_operand" "=r") 594: (truncate:SF (match_operand:DF 1 "general_operand" "rm")))] 595: "" 596: "cvt.ds\\t%0,%1") 597: 598: (define_insn "truncdiqi2" 599: [(set (match_operand:QI 0 "general_operand" "=r,m,r") 600: (truncate:QI (match_operand:DI 1 "general_operand" "m,r,0")))] 601: "" 602: "* 603: { 604: if (which_alternative == 0) 605: return \"ld.8\\t%0,%1\"; 606: else if (which_alternative == 1) 607: return \"st.8\\t%1,%0\"; 608: return \"\"; 609: }") 610: 611: (define_insn "truncdihi2" 612: [(set (match_operand:HI 0 "general_operand" "=r,m,r") 613: (truncate:HI (match_operand:DI 1 "general_operand" "m,r,0")))] 614: "" 615: "* 616: { 617: if (which_alternative == 0) 618: return \"ld.16\\t%0,%1\"; 619: if (which_alternative == 1) 620: return \"st.16\\t%1,%0\"; 621: return \"\"; 622: }") 623: 624: (define_insn "truncdisi2" 625: [(set (match_operand:SI 0 "general_operand" "=r,m") 626: (truncate:SI (match_operand:DI 1 "general_operand" "rm,r")))] 627: "" 628: "* 629: { 630: if (which_alternative == 0) 631: return \"ld.32\\t%0,%1\"; 632: return \"st.32\\t%1,%0\"; 633: }") 634: 635: (define_insn "truncsiqi2" 636: [(set (match_operand:QI 0 "general_operand" "=r,m,r") 637: (truncate:QI (match_operand:SI 1 "general_operand" "m,r,0")))] 638: "" 639: "* 640: { 641: if (which_alternative == 0) 642: return \"ld.8\\t%0,%1\"; 643: if (which_alternative == 1) 644: return \"st.8\\t%1,%0\"; 645: return \"\"; 646: }") 647: 648: (define_insn "truncsihi2" 649: [(set (match_operand:HI 0 "general_operand" "=r,m,r") 650: (truncate:HI (match_operand:SI 1 "general_operand" "m,r,0")))] 651: "" 652: "* 653: { 654: if (which_alternative == 0) 655: return \"ld.16\\t%0,%1\"; 656: if (which_alternative == 1) 657: return \"st.16\\t%1,%0\"; 658: return \"\"; 659: }") 660: 661: (define_insn "trunchiqi2" 662: [(set (match_operand:QI 0 "general_operand" "=r,m,r") 663: (truncate:QI (match_operand:HI 1 "general_operand" "m,r,0")))] 664: "" 665: "* 666: { 667: if (which_alternative == 0) 668: return \"ld.8\\t%0,%1\"; 669: if (which_alternative == 1) 670: return \"st.8\\t%1,%0\"; 671: return \"\"; 672: }") 673: 674: (define_insn "extendsfdf2" 675: [(set (match_operand:DF 0 "register_operand" "=r") 676: (sign_extend:DF (match_operand:SF 1 "general_operand" "rm")))] 677: "" 678: "cvt.sd\\t%0,%1") 679: 680: (define_insn "extendsidi2" 681: [(set (match_operand:DI 0 "register_operand" "=r") 682: (sign_extend:DI (match_operand:SI 1 "general_operand" "rm")))] 683: "" 684: "ld.32\\t%0,%1") 685: 686: (define_insn "extendhisi2" 687: [(set (match_operand:SI 0 "register_operand" "=r,r") 688: (sign_extend:SI (match_operand:HI 1 "general_operand" "m,r")))] 689: "" 690: "* 691: if (which_alternative==0) 692: return \"ld.16\\t%0,%1\"; 693: return \"extract\\t%0,%1:bit 48,16\"; 694: ") 695: 696: (define_insn "extendhidi2" 697: [(set (match_operand:DI 0 "register_operand" "=r,r") 698: (sign_extend:DI (match_operand:HI 1 "general_operand" "m,r")))] 699: "" 700: "* 701: if (which_alternative==0) 702: return \"ld.16\\t%0,%1\"; 703: return \"extract\\t%0,%1:bit 48,16\"; 704: ") 705: 706: (define_insn "extendqihi2" 707: [(set (match_operand:HI 0 "register_operand" "=r,r") 708: (sign_extend:HI (match_operand:QI 1 "general_operand" "m,r")))] 709: "" 710: "* 711: if (which_alternative==0) 712: return \"ld.8\\t%0,%1\"; 713: return \"extract\\t%0,%1:bit 56,8\"; 714: ") 715: 716: (define_insn "extendqisi2" 717: [(set (match_operand:SI 0 "register_operand" "=r,r") 718: (sign_extend:SI (match_operand:QI 1 "general_operand" "m,r")))] 719: "" 720: "* 721: if (which_alternative==0) 722: return \"ld.8\\t%0,%1\"; 723: return \"extract\\t%0,%1:bit 56,8\"; 724: ") 725: 726: (define_insn "extendqidi2" 727: [(set (match_operand:DI 0 "register_operand" "=r,r") 728: (sign_extend:DI (match_operand:QI 1 "general_operand" "m,r")))] 729: "" 730: "* 731: if (which_alternative==0) 732: return \"ld.8\\t%0,%1\"; 733: return \"extract\\t%0,%1:bit 56,8\"; 734: ") 735: 736: (define_insn "zero_extendsidi2" 737: [(set (match_operand:DI 0 "register_operand" "=r") 738: (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))] 739: "" 740: "ldz.32\\t%0,%1") 741: 742: 743: (define_insn "zero_extendhisi2" 744: [(set (match_operand:SI 0 "register_operand" "=r,r") 745: (zero_extend:SI (match_operand:HI 1 "general_operand" "m,r")))] 746: "" 747: "* 748: if (which_alternative==0) 749: return \"ldz.16\\t%0,%1\"; 750: return \"extractz\\t%0,%1:bit 48,16\"; 751: ") 752: 753: (define_insn "zero_extendhidi2" 754: [(set (match_operand:DI 0 "register_operand" "=r,r") 755: (zero_extend:DI (match_operand:HI 1 "general_operand" "m,r")))] 756: "" 757: "* 758: if (which_alternative==0) 759: return \"ldz.16\\t%0,%1\"; 760: return \"extractz\\t%0,%1:bit 48,16\"; 761: ") 762: 763: (define_insn "zero_extendqihi2" 764: [(set (match_operand:HI 0 "register_operand" "=r,r") 765: (zero_extend:HI (match_operand:QI 1 "general_operand" "m,r")))] 766: "" 767: "* 768: if (which_alternative==0) 769: return \"ldz.8\\t%0,%1\"; 770: return \"extractz\\t%0,%1:bit 56,8\"; 771: ") 772: 773: (define_insn "zero_extendqisi2" 774: [(set (match_operand:SI 0 "register_operand" "=r,r") 775: (zero_extend:SI (match_operand:QI 1 "general_operand" "m,r")))] 776: "" 777: "* 778: if (which_alternative==0) 779: return \"ldz.8\\t%0,%1\"; 780: return \"extractz\\t%0,%1:bit 56,8\"; 781: ") 782: 783: (define_insn "zero_extendqidi2" 784: [(set (match_operand:DI 0 "register_operand" "=r,r") 785: (zero_extend:DI (match_operand:QI 1 "general_operand" "m,r")))] 786: "" 787: "* 788: if (which_alternative==0) 789: return \"ldz.8\\t%0,%1\"; 790: return \"extractz\\t%0,%1:bit 56,8\"; 791: ") 792: 793: 794: (define_insn "ashrdi3" 795: [(set (match_operand:DI 0 "register_operand" "=r") 796: (ashiftrt:DI (match_operand:DI 1 "register_operand" "r") 797: (match_operand:SI 2 "general_operand" "rn")))] 798: "" 799: "sra\\t%0,%1,%2") 800: 801: (define_insn "lshrdi3" 802: [(set (match_operand:DI 0 "register_operand" "=r") 803: (lshiftrt:DI (match_operand:DI 1 "register_operand" "r") 804: (match_operand:SI 2 "general_operand" "rn")))] 805: "" 806: "srl\\t%0,%1,%2") 807: 808: (define_insn "ashldi3" 809: [(set (match_operand:DI 0 "register_operand" "=r") 810: (ashift:DI (match_operand:DI 1 "register_operand" "r") 811: (match_operand:SI 2 "general_operand" "rn")))] 812: "" 813: "sla\\t%0,%1,%2") 814: 815: (define_insn "anddi3" 816: [(set (match_operand:DI 0 "register_operand" "=r,r") 817: (and:DI (match_operand:DI 1 "general_operand" "%0,r") 818: (match_operand:DI 2 "general_operand" "g,g")))] 819: "1 /*which_alternative == 0 || check356(operands[2])*/" 820: "* 821: if (which_alternative == 0) 822: return \"and\\t%0,%2\"; 823: return \"and\\t%0,%1,%2\"; 824: ") 825: 826: (define_insn "iordi3" 827: [(set (match_operand:DI 0 "register_operand" "=r,r") 828: (ior:DI (match_operand:DI 1 "general_operand" "%0,r") 829: (match_operand:DI 2 "general_operand" "g,g")))] 830: "1 /*which_alternative == 0 || check356(operands[2])*/" 831: "* 832: if (which_alternative == 0) 833: return \"or\\t%0,%2\"; 834: return \"or\\t%0,%1,%2\"; 835: ") 836: 837: (define_insn "xordi3" 838: [(set (match_operand:DI 0 "register_operand" "=r,r") 839: (xor:DI (match_operand:DI 1 "general_operand" "%0,r") 840: (match_operand:DI 2 "general_operand" "g,g")))] 841: "1 /*which_alternative == 0 || check356(operands[2])*/" 842: "* 843: if (which_alternative == 0) 844: return \"xor\\t%0,%2\"; 845: return \"xor\\t%0,%1,%2\"; 846: ") 847: 848: (define_insn "one_cmpldi2" 849: [(set (match_operand:DI 0 "register_operand" "=r") 850: (not:DI (match_operand:DI 1 "general_operand" "rm")))] 851: "" 852: "not\\t%0,%1") 853: 854: ;; gcc 2.1 does not widen ~si into ~di. 855: (define_insn "one_cmplsi2" 856: [(set (match_operand:SI 0 "register_operand" "=r") 1.1.1.2 ! root 857: (not:SI (match_operand:SI 1 "register_operand" "r")))] 1.1 root 858: "" 859: "not\\t%0,%1") 860: 861: (define_insn "negdi2" 862: [(set (match_operand:DI 0 "register_operand" "=r") 863: (neg:DI (match_operand:DI 1 "general_operand" "rm")))] 864: "" 865: "neg.64\\t%0,%1") 866: 867: (define_insn "negsi2" 868: [(set (match_operand:SI 0 "register_operand" "=r,r") 869: (neg:SI (match_operand:SI 1 "general_operand" "m,r")))] 870: "" 871: "* 872: if (which_alternative == 0) 873: return \"neg.32\\t%0,%1\"; 874: return \"neg.64\\t%0,%1 ; I only want 32\"; 875: ") 876: 877: (define_insn "neghi2" 878: [(set (match_operand:HI 0 "register_operand" "=r,r") 879: (neg:HI (match_operand:HI 1 "general_operand" "m,r")))] 880: "" 881: "* 882: if (which_alternative == 0) 883: return \"neg.16\\t%0,%1\"; 884: return \"neg.64\\t%0,%1 ; I only want 16\"; 885: ") 886: 887: (define_insn "adddf3" 888: [(set (match_operand:DF 0 "register_operand" "=r") 889: (plus:DF (match_operand:DF 1 "general_operand" "%0") 890: (match_operand:DF 2 "general_operand" "rm")))] 891: "" 892: "fadd.64\\t%0,%2") 893: 894: (define_insn "addsf3" 895: [(set (match_operand:SF 0 "register_operand" "=r") 896: (plus:SF (match_operand:SF 1 "general_operand" "%0") 897: (match_operand:SF 2 "general_operand" "rm")))] 898: "" 899: "fadd.32\\t%0,%2") 900: 901: ;; There is also an addi.64 4,.r0'' optimization 902: (define_insn "adddi3" 903: [(set (match_operand:DI 0 "register_operand" "=r,r") 904: (plus:DI (match_operand:DI 1 "general_operand" "%0,r") 905: (match_operand:DI 2 "general_operand" "g,g")))] 906: "1 /*which_alternative == 0 || check356(operands[2])*/" 907: "* 908: if (which_alternative == 0) 909: return \"add.64\\t%0,%2\"; 910: return \"add.64\\t%0,%1,%2\"; 911: ") 912: 913: (define_insn "addsi3" 914: [(set (match_operand:SI 0 "register_operand" "=r,r,r") 915: (plus:SI (match_operand:SI 1 "general_operand" "%0,r,0") 916: (match_operand:SI 2 "general_operand" "m,m,g")))] 917: "1 /*which_alternative != 1 || check356(operands[2])*/" 918: "* 919: if (which_alternative == 0) 920: return \"add.32\\t%0,%2\"; 921: if (which_alternative == 1) 922: return \"add.32\\t%0,%1,%2\"; 923: return \"add.64\\t%0,%2 ; I only want 32\"; 924: ") 925: 926: (define_insn "addhi3" 927: [(set (match_operand:HI 0 "register_operand" "=r,r,r") 928: (plus:HI (match_operand:HI 1 "general_operand" "%0,r,0") 929: (match_operand:HI 2 "general_operand" "m,m,g")))] 930: "1 /*which_alternative != 1 || check356(operands[2])*/" 931: "* 932: if (which_alternative == 0) 933: return \"add.16\\t%0,%2\"; 934: if (which_alternative == 1) 935: return \"add.16\\t%0,%1,%2\"; 936: return \"add.64\\t%0,%2 ; I only want 16\"; 937: ") 938: 939: (define_insn "subdf3" 940: [(set (match_operand:DF 0 "register_operand" "=r") 941: (minus:DF (match_operand:DF 1 "general_operand" "0") 942: (match_operand:DF 2 "general_operand" "rm")))] 943: "" 944: "fsub.64\\t%0,%2") 945: 946: (define_insn "subsf3" 947: [(set (match_operand:SF 0 "register_operand" "=r") 948: (minus:SF (match_operand:SF 1 "general_operand" "0") 949: (match_operand:SF 2 "general_operand" "rm")))] 950: "" 951: "fsub.32\\t%0,%2") 952: 953: (define_insn "subdi3" 954: [(set (match_operand:DI 0 "register_operand" "=r,r,r") 955: (minus:DI (match_operand:DI 1 "general_operand" "0,g,r") 956: (match_operand:DI 2 "general_operand" "g,r,g")))] 957: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" 958: "* 959: if (which_alternative == 0) 960: return \"sub.64\\t%0,%2\"; 961: else if (which_alternative == 1) 962: return \"subr.64\\t%0,%2,%1\"; 963: else 964: return \"sub.64\\t%0,%1,%2\"; 965: ") 966: 967: (define_insn "subsi3" 968: [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 969: (minus:SI (match_operand:SI 1 "general_operand" "0,m,r,0") 970: (match_operand:SI 2 "general_operand" "m,r,m,g")))] 971: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" 972: "* 973: if (which_alternative == 0) 974: return \"sub.32\\t%0,%2\"; 975: else if (which_alternative == 1) 976: return \"subr.32\\t%0,%2,%1\"; 977: else if (which_alternative == 2) 978: return \"sub.32\\t%0,%1,%2\"; 979: else 980: return \"sub.64\\t%0,%2 ; I only want 32\"; 981: ") 982: 983: (define_insn "subhi3" 984: [(set (match_operand:HI 0 "register_operand" "=r,r,r,r") 985: (minus:HI (match_operand:HI 1 "general_operand" "0,m,r,0") 986: (match_operand:HI 2 "general_operand" "m,r,m,g")))] 987: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" 988: "* 989: if (which_alternative == 0) 990: return \"sub.16\\t%0,%2\"; 991: else if (which_alternative == 1) 992: return \"subr.16\\t%0,%2,%1\"; 993: else if (which_alternative == 2) 994: return \"sub.16\\t%0,%1,%2\"; 995: else 996: return \"sub.64\\t%0,%2 ; I only want 16\"; 997: ") 998: 999: (define_insn "muldf3" 1000: [(set (match_operand:DF 0 "register_operand" "=r") 1001: (mult:DF (match_operand:DF 1 "general_operand" "%0") 1002: (match_operand:DF 2 "general_operand" "rm")))] 1003: "" 1004: "fmul.64\\t%0,%2") 1005: 1006: (define_insn "mulsf3" 1007: [(set (match_operand:SF 0 "register_operand" "=r") 1008: (mult:SF (match_operand:SF 1 "general_operand" "%0") 1009: (match_operand:SF 2 "general_operand" "rm")))] 1010: "" 1011: "fmul.32\\t%0,%2") 1012: 1013: (define_insn "muldi3" 1014: [(set (match_operand:DI 0 "register_operand" "=r,r") 1015: (mult:DI (match_operand:DI 1 "general_operand" "%0,r") 1016: (match_operand:DI 2 "general_operand" "g,g")))] 1017: "1 /*which_alternative == 0 || check356(operands[2])*/" 1018: "* 1019: if (which_alternative == 0) 1020: return \"mul.64\\t%0,%2\"; 1021: return \"mul.64\\t%0,%1,%2\"; 1022: ") 1023: 1024: (define_insn "mulsi3" 1025: [(set (match_operand:SI 0 "register_operand" "=r,r,r") 1026: (mult:SI (match_operand:SI 1 "general_operand" "%0,r,0") 1027: (match_operand:SI 2 "general_operand" "m,m,g")))] 1028: "1 /*which_alternative == 0 || check356(operands[2])*/" 1029: "* 1030: if (which_alternative == 0) 1031: return \"mul.32\\t%0,%2\"; 1032: else if (which_alternative == 1) 1033: return \"mul.32\\t%0,%1,%2\"; 1034: else 1035: return \"mul.64\\t%0,%2 ; I only want 32\"; 1036: ") 1037: 1038: (define_insn "mulhi3" 1039: [(set (match_operand:HI 0 "register_operand" "=r,r,r") 1040: (mult:HI (match_operand:HI 1 "general_operand" "%0,r,0") 1041: (match_operand:HI 2 "general_operand" "m,m,g")))] 1042: "1 /*which_alternative == 0 || check356(operands[2])*/" 1043: "* 1044: if (which_alternative == 0) 1045: return \"mul.16\\t%0,%2\"; 1046: else if (which_alternative == 1) 1047: return \"mul.16\\t%0,%1,%2\"; 1048: else 1049: return \"mul.64\\t%0,%2 ; I only want 16\"; 1050: ") 1051: 1052: (define_insn "divdf3" 1053: [(set (match_operand:DF 0 "register_operand" "=r") 1054: (div:DF (match_operand:DF 1 "general_operand" "0") 1055: (match_operand:DF 2 "general_operand" "rm")))] 1056: "" 1057: "fdiv.64\\t%0,%2") 1058: 1059: (define_insn "divsf3" 1060: [(set (match_operand:SF 0 "register_operand" "=r") 1061: (div:SF (match_operand:SF 1 "general_operand" "0") 1062: (match_operand:SF 2 "general_operand" "rm")))] 1063: "" 1064: "fdiv.32\\t%0,%2") 1065: 1066: (define_insn "divdi3" 1067: [(set (match_operand:DI 0 "register_operand" "=r,r,r") 1068: (div:DI (match_operand:DI 1 "general_operand" "0,g,r") 1069: (match_operand:DI 2 "general_operand" "g,r,g")))] 1070: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" 1071: "* 1072: if (which_alternative == 0) 1073: return \"div.64\\t%0,%2\"; 1074: else if (which_alternative == 1) 1075: return \"divr.64\\t%0,%2,%1\"; 1076: else 1077: return \"div.64\\t%0,%1,%2\"; 1078: ") 1079: 1080: (define_insn "divsi3" 1081: [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 1082: (div:SI (match_operand:SI 1 "general_operand" "0,m,r,0") 1083: (match_operand:SI 2 "general_operand" "m,r,m,g")))] 1084: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" 1085: "* 1086: /* We don't ignore high bits. */ 1087: if (0) { 1088: if (which_alternative == 0) 1089: return \"div.32\\t%0,%2\"; 1090: else if (which_alternative == 1) 1091: return \"divr.32\\t%0,%2,%1\"; 1092: else if (which_alternative == 2) 1093: return \"div.32\\t%0,%1,%2\"; 1094: else 1095: return \"ld.32\\t%0,%0\;div.64\\t%0,%2 ; I only want 32\"; 1096: } else { 1097: if (which_alternative == 0) 1098: return \"ld.32\\t%0,%0\;div.32\\t%0,%2\"; 1099: else if (which_alternative == 1) 1100: return \"ld.32\\t%2,%2\;divr.32\\t%0,%2,%1\"; 1101: else if (which_alternative == 2) 1102: return \"ld.32\\t%1,%1\;div.32\\t%0,%1,%2\"; 1103: else 1104: return \"ld.32\\t%0,%0\;div.64\\t%0,%2 ; I only want 32\"; 1105: } 1106: ") 1107: 1108: (define_insn "divhi3" 1109: [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r") 1110: (div:HI (match_operand:HI 1 "general_operand" "0,m,r,0,0") 1111: (match_operand:HI 2 "general_operand" "m,r,m,r,i")))] 1112: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" 1113: "* 1114: if (which_alternative == 0) 1115: return \"extract\\t%0,%0:bit 48,16\;div.16\\t%0,%2\"; 1116: else if (which_alternative == 1) 1117: return \"extract\\t%2,%2:bit 48,16\;divr.16\\t%0,%2,%1\"; 1118: else if (which_alternative == 2) 1119: return \"extract\\t%1,%1:bit 48,16\;div.16\\t%0,%1,%2\"; 1120: else if (which_alternative == 3) 1121: return \"extract\\t%0,%0:bit 48,16\;extract\\t%2,%2:bit 48,16\;div.64\\t%0,%2 ; I only want 16\"; 1122: else 1123: return \"extract\\t%0,%0:bit 48,16\;div.64\\t%0,%2 ; I only want 16\"; 1124: ") 1125: 1126: (define_insn "modhi3" 1127: [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r") 1128: (mod:HI (match_operand:HI 1 "general_operand" "0,m,r,0,0") 1129: (match_operand:HI 2 "general_operand" "m,r,m,r,i")))] 1130: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" 1131: "* 1132: if (which_alternative == 0) 1133: return \"extract\\t%0,%0:bit 48,16\;rem.16\\t%0,%2\"; 1134: else if (which_alternative == 1) 1135: return \"extract\\t%2,%2:bit 48,16\;remr.16\\t%0,%2,%1\"; 1136: else if (which_alternative == 2) 1137: return \"extract\\t%1,%1:bit 48,16\;rem.16\\t%0,%1,%2\"; 1138: else if (which_alternative == 3) 1139: return \"extract\\t%0,%0:bit 48,16\;extract\\t%2,%2:bit 48,16\;rem.64\\t%0,%2 ; I only want 16\"; 1140: else 1141: return \"extract\\t%0,%0:bit 48,16\;rem.64\\t%0,%2 ; I only want 16\"; 1142: ") 1143: 1144: (define_insn "moddi3" 1145: [(set (match_operand:DI 0 "register_operand" "=r,r,r") 1146: (mod:DI (match_operand:DI 1 "general_operand" "0,g,r") 1147: (match_operand:DI 2 "general_operand" "g,r,g")))] 1148: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" 1149: "* 1150: if (which_alternative == 0) 1151: return \"rem.64\\t%0,%2\"; 1152: else if (which_alternative == 1) 1153: return \"remr.64\\t%0,%2,%1\"; 1154: else 1155: return \"rem.64\\t%0,%1,%2\"; 1156: ") 1157: 1158: (define_insn "modsi3" 1159: [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 1160: (mod:SI (match_operand:SI 1 "general_operand" "0,m,r,0") 1161: (match_operand:SI 2 "general_operand" "m,r,m,g")))] 1162: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/" 1163: "* 1164: /* There is a micro code bug with the below... */ 1165: if (0) { 1166: if (which_alternative == 0) 1167: return \"rem.32\\t%0,%2\"; 1168: else if (which_alternative == 1) 1169: return \"remr.32\\t%0,%2,%1\"; 1170: else if (which_alternative == 2) 1171: return \"rem.32\\t%0,%1,%2\"; 1172: else 1173: return \"ld.32\\t%0,%0\;rem.64\\t%0,%2 ; I only want 32\"; 1174: } else { 1175: if (which_alternative == 0) 1176: return \"ld.32\\t%0,%0\;rem.32\\t%0,%2\"; 1177: else if (which_alternative == 1) 1178: return \"ld.32\\t%2,%2\;remr.32\\t%0,%2,%1\"; 1179: else if (which_alternative == 2) 1180: return \"ld.32\\t%1,%1\;rem.32\\t%0,%1,%2\"; 1181: else 1182: return \"ld.32\\t%0,%0\;rem.64\\t%0,%2 ; I only want 32\"; 1183: } 1184: ") 1185: 1186: 1187: (define_insn "jump" 1188: [(set (pc) 1189: (label_ref (match_operand 0 "" "")))] 1190: "" 1191: "jmp\\t%l0") 1192: 1193: (define_insn "indirect_jump" 1194: [(set (pc) (match_operand:SI 0 "register_operand" "r"))] 1195: "" 1196: ;; Maybe %l0 is better, maybe we can relax register only. 1197: "verify this before use ld.32\\t.r0,%0\;br.reg\\t.r0") 1198: 1199: (define_insn "beq" 1200: [(set (pc) 1201: (if_then_else (eq (cc0) 1202: (const_int 0)) 1203: (label_ref (match_operand 0 "" "")) 1204: (pc)))] 1205: "" 1206: "* return cmp_jmp(\"\", 2, operands[0]); ") 1207: 1208: (define_insn "bne" 1209: [(set (pc) 1210: (if_then_else (ne (cc0) 1211: (const_int 0)) 1212: (label_ref (match_operand 0 "" "")) 1213: (pc)))] 1214: "" 1215: "* return cmp_jmp(\"\", 8, operands[0]); ") 1216: 1217: (define_insn "bgt" 1218: [(set (pc) 1219: (if_then_else (gt (cc0) 1220: (const_int 0)) 1221: (label_ref (match_operand 0 "" "")) 1222: (pc)))] 1223: "" 1224: "* return cmp_jmp(\"\", 0, operands[0]); ") 1225: 1226: (define_insn "bgtu" 1227: [(set (pc) 1228: (if_then_else (gtu (cc0) 1229: (const_int 0)) 1230: (label_ref (match_operand 0 "" "")) 1231: (pc)))] 1232: "" 1233: "* return cmp_jmp(\"u\", 0, operands[0]); ") 1234: 1235: (define_insn "blt" 1236: [(set (pc) 1237: (if_then_else (lt (cc0) 1238: (const_int 0)) 1239: (label_ref (match_operand 0 "" "")) 1240: (pc)))] 1241: "" 1242: "* return cmp_jmp(\"\", 6, operands[0]); ") 1243: 1244: (define_insn "bltu" 1245: [(set (pc) 1246: (if_then_else (ltu (cc0) 1247: (const_int 0)) 1248: (label_ref (match_operand 0 "" "")) 1249: (pc)))] 1250: "" 1251: "* return cmp_jmp(\"u\", 6, operands[0]); ") 1252: 1253: (define_insn "bge" 1254: [(set (pc) 1255: (if_then_else (ge (cc0) 1256: (const_int 0)) 1257: (label_ref (match_operand 0 "" "")) 1258: (pc)))] 1259: "" 1260: "* return cmp_jmp(\"\", 4, operands[0]); ") 1261: 1262: (define_insn "bgeu" 1263: [(set (pc) 1264: (if_then_else (geu (cc0) 1265: (const_int 0)) 1266: (label_ref (match_operand 0 "" "")) 1267: (pc)))] 1268: "" 1269: "* return cmp_jmp(\"u\", 4, operands[0]); ") 1270: 1271: (define_insn "ble" 1272: [(set (pc) 1273: (if_then_else (le (cc0) 1274: (const_int 0)) 1275: (label_ref (match_operand 0 "" "")) 1276: (pc)))] 1277: "" 1278: "* return cmp_jmp(\"\", 10, operands[0]); ") 1279: 1280: (define_insn "bleu" 1281: [(set (pc) 1282: (if_then_else (leu (cc0) 1283: (const_int 0)) 1284: (label_ref (match_operand 0 "" "")) 1285: (pc)))] 1286: "" 1287: "* return cmp_jmp(\"u\", 10, operands[0]); ") 1288: 1289: (define_insn "" 1290: [(set (pc) 1291: (if_then_else (eq (cc0) 1292: (const_int 0)) 1293: (pc) 1294: (label_ref (match_operand 0 "" ""))))] 1295: "" 1296: "* return cmp_jmp(\"\", 8, operands[0]); ") 1297: 1298: (define_insn "" 1299: [(set (pc) 1300: (if_then_else (ne (cc0) 1301: (const_int 0)) 1302: (pc) 1303: (label_ref (match_operand 0 "" ""))))] 1304: "" 1305: "* return cmp_jmp(\"\", 2, operands[0]); ") 1306: 1307: (define_insn "" 1308: [(set (pc) 1309: (if_then_else (gt (cc0) 1310: (const_int 0)) 1311: (pc) 1312: (label_ref (match_operand 0 "" ""))))] 1313: "" 1314: "* return cmp_jmp(\"\", 10, operands[0]); ") 1315: 1316: (define_insn "" 1317: [(set (pc) 1318: (if_then_else (gtu (cc0) 1319: (const_int 0)) 1320: (pc) 1321: (label_ref (match_operand 0 "" ""))))] 1322: "" 1323: "* return cmp_jmp(\"u\", 10, operands[0]); ") 1324: 1325: (define_insn "" 1326: [(set (pc) 1327: (if_then_else (lt (cc0) 1328: (const_int 0)) 1329: (pc) 1330: (label_ref (match_operand 0 "" ""))))] 1331: "" 1332: "* return cmp_jmp(\"\", 4, operands[0]); ") 1333: 1334: (define_insn "" 1335: [(set (pc) 1336: (if_then_else (ltu (cc0) 1337: (const_int 0)) 1338: (pc) 1339: (label_ref (match_operand 0 "" ""))))] 1340: "" 1341: "* return cmp_jmp(\"u\", 4, operands[0]); ") 1342: 1343: (define_insn "" 1344: [(set (pc) 1345: (if_then_else (ge (cc0) 1346: (const_int 0)) 1347: (pc) 1348: (label_ref (match_operand 0 "" ""))))] 1349: "" 1350: "* return cmp_jmp(\"\", 6, operands[0]); ") 1351: 1352: (define_insn "" 1353: [(set (pc) 1354: (if_then_else (geu (cc0) 1355: (const_int 0)) 1356: (pc) 1357: (label_ref (match_operand 0 "" ""))))] 1358: "" 1359: "* return cmp_jmp(\"u\", 6, operands[0]); ") 1360: 1361: (define_insn "" 1362: [(set (pc) 1363: (if_then_else (le (cc0) 1364: (const_int 0)) 1365: (pc) 1366: (label_ref (match_operand 0 "" ""))))] 1367: "" 1368: "* return cmp_jmp(\"\", 0, operands[0]); ") 1369: 1370: (define_insn "" 1371: [(set (pc) 1372: (if_then_else (leu (cc0) 1373: (const_int 0)) 1374: (pc) 1375: (label_ref (match_operand 0 "" ""))))] 1376: "" 1377: "* return cmp_jmp(\"u\", 0, operands[0]); ") 1378: 1379: ;; Note that operand 1 is total size of args, in bytes, 1380: ;; and what the call insn wants is the number of words. 1381: (define_insn "call" 1382: [(call (match_operand:QI 0 "general_operand" "m") 1383: (match_operand:QI 1 "general_operand" "g"))] 1384: "" 1385: "* 1386: if (GET_CODE (operands[0]) == MEM && GET_CODE (XEXP (operands[0], 0)) == REG) 1387: if (REGNO (XEXP (operands[0], 0)) != 0) 1388: return \"add.64\\t.sp,=-4\;ld.64\\t.r0,=.+11\;st.32\\t.r0,[.sp]\;br.reg\\t%r0\;add.64\\t.sp,=4\;add.64\\t.sp,%1\"; 1389: else 1390: return \"add.64\\t.sp,=-4\;ld.64\\t.r1,=.+11\;st.32\\t.r1,[.sp]\;br.reg\\t%r0\;add.64\\t.sp,=4\;add.64\\t.sp,%1\"; 1391: else 1392: return \"add.64\\t.sp,=-4\;call\\t%0\;add.64\\t.sp,=4\;add.64\\t.sp,%1\"; 1393: ") 1394: 1395: (define_insn "call_value" 1396: [(set (match_operand 0 "" "g") 1397: (call (match_operand:QI 1 "general_operand" "m") 1398: (match_operand:QI 2 "general_operand" "g")))] 1399: "" 1400: "* 1401: if (GET_CODE (operands[1]) == MEM && GET_CODE (XEXP (operands[1], 0)) == REG) 1402: if (REGNO (XEXP (operands[1], 0)) != 0) 1403: return \"add.64\\t.sp,=-4\;ld.64\\t.r0,=.+11\;st.32\\t.r0,[.sp]\;br.reg\\t%r1\;add.64\\t.sp,=4\;add.64\\t.sp,%2\"; 1404: else 1405: return \"add.64\\t.sp,=-4\;ld.64\\t.r1,=.+11\;st.32\\t.r1,[.sp]\;br.reg\\t%r1\;add.64\\t.sp,=4\;add.64\\t.sp,%2\"; 1406: else 1407: return \"add.64\\t.sp,=-4\;call\\t%1\;add.64\\t.sp,=4\;add.64\\t.sp,%2\"; 1408: ") 1409: 1410: (define_insn "tablejump" 1411: [(set (pc) (match_operand:SI 0 "register_operand" "r")) 1412: (use (label_ref (match_operand 1 "" "")))] 1413: "" 1414: "br.reg\\t%0") 1415: 1416: (define_insn "nop" 1417: [(const_int 0)] 1418: "" 1419: "nop")
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.