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1.1.1.2 root 1: ;;- Machine description for GNU compiler, Elxsi Version
2: ;; Copyright (C) 1987, 1988, 1992, 1994 Free Software Foundation, Inc.
3: ;; Contributed by Mike Stump <[email protected]> in 1988, and is the first
1.1 root 4: ;; 64 bit port of GNU CC.
5: ;; Based upon the VAX port.
6:
7: ;; This file is part of GNU CC.
8:
9: ;; GNU CC is free software; you can redistribute it and/or modify
10: ;; it under the terms of the GNU General Public License as published by
11: ;; the Free Software Foundation; either version 1, or (at your option)
12: ;; any later version.
13:
14: ;; GNU CC is distributed in the hope that it will be useful,
15: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17: ;; GNU General Public License for more details.
18:
19: ;; You should have received a copy of the GNU General Public License
20: ;; along with GNU CC; see the file COPYING. If not, write to
1.1.1.3 ! root 21: ;; the Free Software Foundation, 59 Temple Place - Suite 330,
! 22: ;; Boston, MA 02111-1307, USA.
1.1 root 23:
24:
25: ;;- Instruction patterns. When multiple patterns apply,
26: ;;- the first one in the file is chosen.
27: ;;-
28: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29: ;;-
30: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
31: ;;- updates for most instructions.
32:
33:
34: (define_insn ""
35: [(set (reg:SI 15)
36: (plus:SI (reg:SI 15)
37: (match_operand:SI 0 "general_operand" "g")))]
38: ""
39: "add.64\\t.sp,%0")
40:
41: (define_insn ""
42: [(set (reg:SI 15)
43: (plus:SI (match_operand:SI 0 "general_operand" "g")
44: (reg:SI 15)))]
45: ""
46: "add.64\\t.sp,%0")
47:
48: (define_insn ""
49: [(set (match_operand:SI 0 "register_operand" "r")
50: (plus:SI (reg:SI 15)
51: (match_operand:SI 1 "general_operand" "g")))]
52: ""
53: "ld.32\\t%0,.sp\;add.64\\t%0,%1")
54:
55: (define_insn ""
56: [(set (match_operand:SI 0 "register_operand" "r")
57: (plus:SI (match_operand:SI 1 "general_operand" "g")
58: (reg:SI 15)))]
59: ""
60: "ld.32\\t%0,.sp\;add.64\\t%0,%1")
61:
62: (define_insn ""
63: [(set (reg:SI 15)
64: (minus:SI (reg:SI 15)
65: (match_operand:SI 0 "general_operand" "g")))]
66: ""
67: "sub.64\\t.sp,%0")
68:
69: (define_insn ""
70: [(set (reg:SI 15)
71: (match_operand:SI 0 "general_operand" "rm"))]
72: ""
73: "ld.32\\t.sp,%0")
74:
75: (define_insn ""
76: [(set (match_operand:SI 0 "general_operand" "m,r")
77: (reg:SI 15))]
78: ""
79: "*
80: if (which_alternative == 0)
81: return \"st.32\\t.sp,%0\";
82: return \"ld.32\\t%0,.sp\";
83: ")
84:
85: ; tstdi is first test insn so that it is the one to match
86: ; a constant argument.
87:
88: (define_insn "tstdi"
89: [(set (cc0)
90: (match_operand:DI 0 "register_operand" "r"))]
91: ""
92: "*
93: extern rtx cmp_op0, cmp_op1;
94: cmp_op0=operands[0]; cmp_op1=0;
95: return \";\\ttstdi\\t%0\";
96: ")
97:
98: (define_insn "tstdf"
99: [(set (cc0)
100: (match_operand:DF 0 "register_operand" "r"))]
101: ""
102: "*
103: extern rtx cmp_op0, cmp_op1;
104: cmp_op0=operands[0]; cmp_op1=0;
105: return \";\\ttstdf\\t%0\";
106: ")
107:
108: (define_insn "tstsf"
109: [(set (cc0)
110: (match_operand:SF 0 "register_operand" "r"))]
111: ""
112: "*
113: extern rtx cmp_op0, cmp_op1;
114: cmp_op0=operands[0]; cmp_op1=0;
115: return \";\\ttstsf\\t%0\";
116: ")
117:
118: (define_insn "cmpdi"
119: [(set (cc0)
120: (compare (match_operand:DI 0 "register_operand" "r")
121: (match_operand:DI 1 "general_operand" "rm")))]
122: ""
123: "*
124: extern rtx cmp_op0, cmp_op1;
125: cmp_op0=operands[0]; cmp_op1=operands[1];
126: return \";\\tcmpdi\\t%0,%1\";
127: ")
128:
129: (define_insn "cmpdf"
130: [(set (cc0)
131: (compare (match_operand:DF 0 "register_operand" "r")
132: (match_operand:DF 1 "general_operand" "rm")))]
133: ""
134: "*
135: extern rtx cmp_op0, cmp_op1;
136: cmp_op0=operands[0]; cmp_op1=operands[1];
137: return \";\\tcmpdf\\t%0,%1\";
138: ")
139:
140: (define_insn "cmpsf"
141: [(set (cc0)
142: (compare (match_operand:SF 0 "register_operand" "r")
143: (match_operand:SF 1 "general_operand" "rm")))]
144: ""
145: "*
146: extern rtx cmp_op0, cmp_op1;
147: cmp_op0=operands[0]; cmp_op1=operands[1];
148: return \";\\tcmpsf\\t%0,%1\";
149: ")
150:
151: (define_insn ""
152: [(set (match_operand:DI 0 "register_operand" "=r")
153: (eq (match_operand:DI 1 "register_operand" "r")
154: (match_operand:DI 2 "general_operand" "g")))]
155: ""
156: "cmp.64\\t%0,%1,%2:eq")
157:
158: (define_insn ""
159: [(set (match_operand:DI 0 "register_operand" "=r")
160: (ne (match_operand:DI 1 "register_operand" "r")
161: (match_operand:DI 2 "general_operand" "g")))]
162: ""
163: "cmp.64\\t%0,%1,%2:ne")
164:
165: (define_insn ""
166: [(set (match_operand:DI 0 "register_operand" "=r")
167: (le (match_operand:DI 1 "register_operand" "r")
168: (match_operand:DI 2 "general_operand" "g")))]
169: ""
170: "cmp.64\\t%0,%1,%2:le")
171:
172: (define_insn ""
173: [(set (match_operand:DI 0 "register_operand" "=r")
174: (leu (match_operand:DI 1 "register_operand" "r")
175: (match_operand:DI 2 "general_operand" "g")))]
176: ""
177: "cmpu.64\\t%0,%1,%2:le")
178:
179: (define_insn ""
180: [(set (match_operand:DI 0 "register_operand" "=r")
181: (lt (match_operand:DI 1 "register_operand" "r")
182: (match_operand:DI 2 "general_operand" "g")))]
183: ""
184: "cmp.64\\t%0,%1,%2:lt")
185:
186: (define_insn ""
187: [(set (match_operand:DI 0 "register_operand" "=r")
188: (ltu (match_operand:DI 1 "register_operand" "r")
189: (match_operand:DI 2 "general_operand" "g")))]
190: ""
191: "cmpu.64\\t%0,%1,%2:lt")
192:
193: (define_insn ""
194: [(set (match_operand:DI 0 "register_operand" "=r")
195: (ge (match_operand:DI 1 "register_operand" "r")
196: (match_operand:DI 2 "general_operand" "g")))]
197: ""
198: "cmp.64\\t%0,%1,%2:ge")
199:
200: (define_insn ""
201: [(set (match_operand:DI 0 "register_operand" "=r")
202: (geu (match_operand:DI 1 "register_operand" "r")
203: (match_operand:DI 2 "general_operand" "g")))]
204: ""
205: "cmpu.64\\t%0,%1,%2:ge")
206:
207: (define_insn ""
208: [(set (match_operand:DI 0 "register_operand" "=r")
209: (gt (match_operand:DI 1 "register_operand" "r")
210: (match_operand:DI 2 "general_operand" "g")))]
211: ""
212: "cmp.64\\t%0,%1,%2:gt")
213:
214: (define_insn ""
215: [(set (match_operand:DI 0 "register_operand" "=r")
216: (gtu (match_operand:DI 1 "register_operand" "r")
217: (match_operand:DI 2 "general_operand" "g")))]
218: ""
219: "cmpu.64\\t%0,%1,%2:gt")
220:
221: (define_insn "seq"
222: [(set (match_operand:DI 0 "register_operand" "=r")
223: (eq (cc0) (const_int 0)))]
224: ""
225: "* return cmp_set(\"\", \"eq\", operands[0]); ")
226:
227: (define_insn "sne"
228: [(set (match_operand:DI 0 "register_operand" "=r")
229: (ne (cc0) (const_int 0)))]
230: ""
231: "* return cmp_set(\"\", \"ne\", operands[0]); ")
232:
233: (define_insn "sle"
234: [(set (match_operand:DI 0 "register_operand" "=r")
235: (le (cc0) (const_int 0)))]
236: ""
237: "* return cmp_set(\"\", \"le\", operands[0]); ")
238:
239: (define_insn "sleu"
240: [(set (match_operand:DI 0 "register_operand" "=r")
241: (leu (cc0) (const_int 0)))]
242: ""
243: "* return cmp_set(\"u\", \"le\", operands[0]); ")
244:
245: (define_insn "slt"
246: [(set (match_operand:DI 0 "register_operand" "=r")
247: (lt (cc0) (const_int 0)))]
248: ""
249: "* return cmp_set(\"\", \"lt\", operands[0]); ")
250:
251: (define_insn "sltu"
252: [(set (match_operand:DI 0 "register_operand" "=r")
253: (ltu (cc0) (const_int 0)))]
254: ""
255: "* return cmp_set(\"u\", \"lt\", operands[0]); ")
256:
257: (define_insn "sge"
258: [(set (match_operand:DI 0 "register_operand" "=r")
259: (ge (cc0) (const_int 0)))]
260: ""
261: "* return cmp_set(\"\", \"ge\", operands[0]); ")
262:
263: (define_insn "sgeu"
264: [(set (match_operand:DI 0 "register_operand" "=r")
265: (geu (cc0) (const_int 0)))]
266: ""
267: "* return cmp_set(\"u\", \"ge\", operands[0]); ")
268:
269: (define_insn "sgt"
270: [(set (match_operand:DI 0 "register_operand" "=r")
271: (gt (cc0) (const_int 0)))]
272: ""
273: "* return cmp_set(\"\", \"gt\", operands[0]); ")
274:
275: (define_insn "sgtu"
276: [(set (match_operand:DI 0 "register_operand" "=r")
277: (gtu (cc0) (const_int 0)))]
278: ""
279: "* return cmp_set(\"u\", \"gt\", operands[0]); ")
280:
281: (define_insn ""
282: [(set (match_operand:SI 0 "register_operand" "=r")
283: (eq (match_operand:SI 1 "register_operand" "r")
284: (match_operand:SI 2 "general_operand" "m")))]
285: ""
286: "cmp.32\\t%0,%1,%2:eq")
287:
288: (define_insn ""
289: [(set (match_operand:SI 0 "register_operand" "=r")
290: (ne (match_operand:SI 1 "register_operand" "r")
291: (match_operand:SI 2 "general_operand" "m")))]
292: ""
293: "cmp.32\\t%0,%1,%2:ne")
294:
295: (define_insn ""
296: [(set (match_operand:SI 0 "register_operand" "=r")
297: (le (match_operand:SI 1 "register_operand" "r")
298: (match_operand:SI 2 "general_operand" "m")))]
299: ""
300: "cmp.32\\t%0,%1,%2:le")
301:
302: (define_insn ""
303: [(set (match_operand:SI 0 "register_operand" "=r")
304: (leu (match_operand:SI 1 "register_operand" "r")
305: (match_operand:SI 2 "general_operand" "m")))]
306: ""
307: "cmpu.32\\t%0,%1,%2:le")
308:
309: (define_insn ""
310: [(set (match_operand:SI 0 "register_operand" "=r")
311: (lt (match_operand:SI 1 "register_operand" "r")
312: (match_operand:SI 2 "general_operand" "m")))]
313: ""
314: "cmp.32\\t%0,%1,%2:lt")
315:
316: (define_insn ""
317: [(set (match_operand:SI 0 "register_operand" "=r")
318: (ltu (match_operand:SI 1 "register_operand" "r")
319: (match_operand:SI 2 "general_operand" "m")))]
320: ""
321: "cmpu.32\\t%0,%1,%2:lt")
322:
323: (define_insn ""
324: [(set (match_operand:SI 0 "register_operand" "=r")
325: (ge (match_operand:SI 1 "register_operand" "r")
326: (match_operand:SI 2 "general_operand" "m")))]
327: ""
328: "cmp.32\\t%0,%1,%2:ge")
329:
330: (define_insn ""
331: [(set (match_operand:SI 0 "register_operand" "=r")
332: (geu (match_operand:SI 1 "register_operand" "r")
333: (match_operand:SI 2 "general_operand" "m")))]
334: ""
335: "cmpu.32\\t%0,%1,%2:ge")
336:
337: (define_insn ""
338: [(set (match_operand:SI 0 "register_operand" "=r")
339: (gt (match_operand:SI 1 "register_operand" "r")
340: (match_operand:SI 2 "general_operand" "m")))]
341: ""
342: "cmp.32\\t%0,%1,%2:gt")
343:
344: (define_insn ""
345: [(set (match_operand:SI 0 "register_operand" "=r")
346: (gtu (match_operand:SI 1 "register_operand" "r")
347: (match_operand:SI 2 "general_operand" "m")))]
348: ""
349: "cmpu.32\\t%0,%1,%2:gt")
350:
351: (define_insn ""
352: [(set (match_operand:HI 0 "register_operand" "=r")
353: (eq (match_operand:HI 1 "register_operand" "r")
354: (match_operand:HI 2 "general_operand" "m")))]
355: ""
356: "cmp.16\\t%0,%1,%2:eq")
357:
358: (define_insn ""
359: [(set (match_operand:HI 0 "register_operand" "=r")
360: (ne (match_operand:HI 1 "register_operand" "r")
361: (match_operand:HI 2 "general_operand" "m")))]
362: ""
363: "cmp.16\\t%0,%1,%2:ne")
364:
365: (define_insn ""
366: [(set (match_operand:HI 0 "register_operand" "=r")
367: (le (match_operand:HI 1 "register_operand" "r")
368: (match_operand:HI 2 "general_operand" "m")))]
369: ""
370: "cmp.16\\t%0,%1,%2:le")
371:
372: (define_insn ""
373: [(set (match_operand:HI 0 "register_operand" "=r")
374: (leu (match_operand:HI 1 "register_operand" "r")
375: (match_operand:HI 2 "general_operand" "m")))]
376: ""
377: "cmpu.16\\t%0,%1,%2:le")
378:
379: (define_insn ""
380: [(set (match_operand:HI 0 "register_operand" "=r")
381: (lt (match_operand:HI 1 "register_operand" "r")
382: (match_operand:HI 2 "general_operand" "m")))]
383: ""
384: "cmp.16\\t%0,%1,%2:lt")
385:
386: (define_insn ""
387: [(set (match_operand:HI 0 "register_operand" "=r")
388: (ltu (match_operand:HI 1 "register_operand" "r")
389: (match_operand:HI 2 "general_operand" "m")))]
390: ""
391: "cmpu.16\\t%0,%1,%2:lt")
392:
393: (define_insn ""
394: [(set (match_operand:HI 0 "register_operand" "=r")
395: (ge (match_operand:HI 1 "register_operand" "r")
396: (match_operand:HI 2 "general_operand" "m")))]
397: ""
398: "cmp.16\\t%0,%1,%2:ge")
399:
400: (define_insn ""
401: [(set (match_operand:HI 0 "register_operand" "=r")
402: (geu (match_operand:HI 1 "register_operand" "r")
403: (match_operand:HI 2 "general_operand" "m")))]
404: ""
405: "cmpu.16\\t%0,%1,%2:ge")
406:
407: (define_insn ""
408: [(set (match_operand:HI 0 "register_operand" "=r")
409: (gt (match_operand:HI 1 "register_operand" "r")
410: (match_operand:HI 2 "general_operand" "m")))]
411: ""
412: "cmp.16\\t%0,%1,%2:gt")
413:
414: (define_insn ""
415: [(set (match_operand:HI 0 "register_operand" "=r")
416: (gtu (match_operand:HI 1 "register_operand" "r")
417: (match_operand:HI 2 "general_operand" "m")))]
418: ""
419: "cmpu.16\\t%0,%1,%2:gt")
420:
421: (define_insn ""
422: [(set (match_operand:QI 0 "register_operand" "=r")
423: (eq (match_operand:QI 1 "register_operand" "r")
424: (match_operand:QI 2 "general_operand" "m")))]
425: ""
426: "cmp.8\\t%0,%1,%2:eq")
427:
428: (define_insn ""
429: [(set (match_operand:QI 0 "register_operand" "=r")
430: (ne (match_operand:QI 1 "register_operand" "r")
431: (match_operand:QI 2 "general_operand" "m")))]
432: ""
433: "cmp.8\\t%0,%1,%2:ne")
434:
435: (define_insn ""
436: [(set (match_operand:QI 0 "register_operand" "=r")
437: (le (match_operand:QI 1 "register_operand" "r")
438: (match_operand:QI 2 "general_operand" "m")))]
439: ""
440: "cmp.8\\t%0,%1,%2:le")
441:
442: (define_insn ""
443: [(set (match_operand:QI 0 "register_operand" "=r")
444: (leu (match_operand:QI 1 "register_operand" "r")
445: (match_operand:QI 2 "general_operand" "m")))]
446: ""
447: "cmpu.8\\t%0,%1,%2:le")
448:
449: (define_insn ""
450: [(set (match_operand:QI 0 "register_operand" "=r")
451: (lt (match_operand:QI 1 "register_operand" "r")
452: (match_operand:QI 2 "general_operand" "m")))]
453: ""
454: "cmp.8\\t%0,%1,%2:lt")
455:
456: (define_insn ""
457: [(set (match_operand:QI 0 "register_operand" "=r")
458: (ltu (match_operand:QI 1 "register_operand" "r")
459: (match_operand:QI 2 "general_operand" "m")))]
460: ""
461: "cmpu.8\\t%0,%1,%2:lt")
462:
463: (define_insn ""
464: [(set (match_operand:QI 0 "register_operand" "=r")
465: (ge (match_operand:QI 1 "register_operand" "r")
466: (match_operand:QI 2 "general_operand" "m")))]
467: ""
468: "cmp.8\\t%0,%1,%2:ge")
469:
470: (define_insn ""
471: [(set (match_operand:QI 0 "register_operand" "=r")
472: (geu (match_operand:QI 1 "register_operand" "r")
473: (match_operand:QI 2 "general_operand" "m")))]
474: ""
475: "cmpu.8\\t%0,%1,%2:ge")
476:
477: (define_insn ""
478: [(set (match_operand:QI 0 "register_operand" "=r")
479: (gt (match_operand:QI 1 "register_operand" "r")
480: (match_operand:QI 2 "general_operand" "m")))]
481: ""
482: "cmp.8\\t%0,%1,%2:gt")
483:
484: (define_insn ""
485: [(set (match_operand:QI 0 "register_operand" "=r")
486: (gtu (match_operand:QI 1 "register_operand" "r")
487: (match_operand:QI 2 "general_operand" "m")))]
488: ""
489: "cmpu.8\\t%0,%1,%2:gt")
490:
491:
492:
493: (define_insn "movdf" [(set (match_operand:DF 0 "general_operand" "=r,m")
494: (match_operand:DF 1 "general_operand" "rm,r"))]
495: ""
496: "*
497: {
498: if (which_alternative == 0)
499: return \"ld.64\\t%0,%1\";
500: return \"st.64\\t%1,%0\";
501: }")
502:
503: (define_insn "movsf"
504: [(set (match_operand:SF 0 "general_operand" "=r,m")
505: (match_operand:SF 1 "general_operand" "rm,r"))]
506: ""
507: "*
508: {
509: if (which_alternative == 0)
510: return \"ld.32\\t%0,%1\";
511: return \"st.32\\t%1,%0\";
512: }")
513:
514: (define_insn "movdi"
515: [(set (match_operand:DI 0 "general_operand" "=r,m,rm")
516: (match_operand:DI 1 "general_operand" "g,r,I"))]
517: ""
518: "*
519: if (which_alternative == 0)
520: return \"ld.64\\t%0,%1\";
521: else if (which_alternative == 1)
522: return \"st.64\\t%1,%0\";
523: else
524: if (GET_CODE(operands[1])==CONST_INT) {
525: if (INTVAL(operands[1]) >= 0)
526: return \"sti.64\\t%c1,%0\";
527: else
528: return \"stin.64\\t%n1,%0\";
529: }
530: ")
531:
532: (define_insn "movsi"
533: [(set (match_operand:SI 0 "general_operand" "=r,m,r")
534: (match_operand:SI 1 "general_operand" "rm,rI,i"))]
535: ""
536: "*
537: if (which_alternative == 0)
538: return \"ld.32\\t%0,%1\";
539: else if (which_alternative == 1) {
540: if (GET_CODE(operands[1])==CONST_INT) {
541: if (INTVAL(operands[1]) >= 0)
542: return \"sti.32\\t%c1,%0\";
543: else
544: return \"stin.32\\t%n1,%0\";
545: }
546: return \"st.32\\t%1,%0\";
547: } else
548: return \"ld.64\\t%0,%1 ; I only want 32\";
549: ")
550:
551: (define_insn "movhi"
552: [(set (match_operand:HI 0 "general_operand" "=r,m,r")
553: (match_operand:HI 1 "general_operand" "m,rI,ri"))]
554: ""
555: "*
556: {
557: if (which_alternative == 0)
558: return \"ld.16\\t%0,%1\";
559: if (which_alternative == 2)
560: return \"ld.64\\t%0,%1\\t; I only want 16\";
561: if (GET_CODE(operands[1])==CONST_INT) {
562: if (INTVAL(operands[1]) >= 0)
563: return \"sti.16\\t%c1,%0\";
564: else
565: return \"stin.16\\t%n1,%0\";
566: }
567: return \"st.16\\t%1,%0\";
568: }")
569:
570: (define_insn "movqi"
571: [(set (match_operand:QI 0 "general_operand" "=r,m,r")
572: (match_operand:QI 1 "general_operand" "m,rI,ri"))]
573: ""
574: "*
575: {
576: if (which_alternative == 0)
577: return \"ld.8\\t%0,%1\";
578: if (which_alternative == 2)
579: return \"ld.64\\t%0,%1\\t; I only want 8\";
580: if (GET_CODE(operands[1])==CONST_INT) {
581: if (INTVAL(operands[1]) >= 0)
582: return \"sti.8\\t%c1,%0\";
583: else
584: return \"stin.8\\t%n1,%0\";
585: }
586: return \"st.8\\t%1,%0\";
587: }")
588:
589: ;; Extension and truncation insns.
590: ;; Those for integer source operand
591: ;; are ordered widest source type first.
592:
593: (define_insn "truncdfsf2"
594: [(set (match_operand:SF 0 "register_operand" "=r")
595: (truncate:SF (match_operand:DF 1 "general_operand" "rm")))]
596: ""
597: "cvt.ds\\t%0,%1")
598:
599: (define_insn "truncdiqi2"
600: [(set (match_operand:QI 0 "general_operand" "=r,m,r")
601: (truncate:QI (match_operand:DI 1 "general_operand" "m,r,0")))]
602: ""
603: "*
604: {
605: if (which_alternative == 0)
606: return \"ld.8\\t%0,%1\";
607: else if (which_alternative == 1)
608: return \"st.8\\t%1,%0\";
609: return \"\";
610: }")
611:
612: (define_insn "truncdihi2"
613: [(set (match_operand:HI 0 "general_operand" "=r,m,r")
614: (truncate:HI (match_operand:DI 1 "general_operand" "m,r,0")))]
615: ""
616: "*
617: {
618: if (which_alternative == 0)
619: return \"ld.16\\t%0,%1\";
620: if (which_alternative == 1)
621: return \"st.16\\t%1,%0\";
622: return \"\";
623: }")
624:
625: (define_insn "truncdisi2"
626: [(set (match_operand:SI 0 "general_operand" "=r,m")
627: (truncate:SI (match_operand:DI 1 "general_operand" "rm,r")))]
628: ""
629: "*
630: {
631: if (which_alternative == 0)
632: return \"ld.32\\t%0,%1\";
633: return \"st.32\\t%1,%0\";
634: }")
635:
636: (define_insn "truncsiqi2"
637: [(set (match_operand:QI 0 "general_operand" "=r,m,r")
638: (truncate:QI (match_operand:SI 1 "general_operand" "m,r,0")))]
639: ""
640: "*
641: {
642: if (which_alternative == 0)
643: return \"ld.8\\t%0,%1\";
644: if (which_alternative == 1)
645: return \"st.8\\t%1,%0\";
646: return \"\";
647: }")
648:
649: (define_insn "truncsihi2"
650: [(set (match_operand:HI 0 "general_operand" "=r,m,r")
651: (truncate:HI (match_operand:SI 1 "general_operand" "m,r,0")))]
652: ""
653: "*
654: {
655: if (which_alternative == 0)
656: return \"ld.16\\t%0,%1\";
657: if (which_alternative == 1)
658: return \"st.16\\t%1,%0\";
659: return \"\";
660: }")
661:
662: (define_insn "trunchiqi2"
663: [(set (match_operand:QI 0 "general_operand" "=r,m,r")
664: (truncate:QI (match_operand:HI 1 "general_operand" "m,r,0")))]
665: ""
666: "*
667: {
668: if (which_alternative == 0)
669: return \"ld.8\\t%0,%1\";
670: if (which_alternative == 1)
671: return \"st.8\\t%1,%0\";
672: return \"\";
673: }")
674:
675: (define_insn "extendsfdf2"
676: [(set (match_operand:DF 0 "register_operand" "=r")
677: (sign_extend:DF (match_operand:SF 1 "general_operand" "rm")))]
678: ""
679: "cvt.sd\\t%0,%1")
680:
681: (define_insn "extendsidi2"
682: [(set (match_operand:DI 0 "register_operand" "=r")
683: (sign_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
684: ""
685: "ld.32\\t%0,%1")
686:
687: (define_insn "extendhisi2"
688: [(set (match_operand:SI 0 "register_operand" "=r,r")
689: (sign_extend:SI (match_operand:HI 1 "general_operand" "m,r")))]
690: ""
691: "*
692: if (which_alternative==0)
693: return \"ld.16\\t%0,%1\";
694: return \"extract\\t%0,%1:bit 48,16\";
695: ")
696:
697: (define_insn "extendhidi2"
698: [(set (match_operand:DI 0 "register_operand" "=r,r")
699: (sign_extend:DI (match_operand:HI 1 "general_operand" "m,r")))]
700: ""
701: "*
702: if (which_alternative==0)
703: return \"ld.16\\t%0,%1\";
704: return \"extract\\t%0,%1:bit 48,16\";
705: ")
706:
707: (define_insn "extendqihi2"
708: [(set (match_operand:HI 0 "register_operand" "=r,r")
709: (sign_extend:HI (match_operand:QI 1 "general_operand" "m,r")))]
710: ""
711: "*
712: if (which_alternative==0)
713: return \"ld.8\\t%0,%1\";
714: return \"extract\\t%0,%1:bit 56,8\";
715: ")
716:
717: (define_insn "extendqisi2"
718: [(set (match_operand:SI 0 "register_operand" "=r,r")
719: (sign_extend:SI (match_operand:QI 1 "general_operand" "m,r")))]
720: ""
721: "*
722: if (which_alternative==0)
723: return \"ld.8\\t%0,%1\";
724: return \"extract\\t%0,%1:bit 56,8\";
725: ")
726:
727: (define_insn "extendqidi2"
728: [(set (match_operand:DI 0 "register_operand" "=r,r")
729: (sign_extend:DI (match_operand:QI 1 "general_operand" "m,r")))]
730: ""
731: "*
732: if (which_alternative==0)
733: return \"ld.8\\t%0,%1\";
734: return \"extract\\t%0,%1:bit 56,8\";
735: ")
736:
737: (define_insn "zero_extendsidi2"
738: [(set (match_operand:DI 0 "register_operand" "=r")
739: (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
740: ""
741: "ldz.32\\t%0,%1")
742:
743:
744: (define_insn "zero_extendhisi2"
745: [(set (match_operand:SI 0 "register_operand" "=r,r")
746: (zero_extend:SI (match_operand:HI 1 "general_operand" "m,r")))]
747: ""
748: "*
749: if (which_alternative==0)
750: return \"ldz.16\\t%0,%1\";
751: return \"extractz\\t%0,%1:bit 48,16\";
752: ")
753:
754: (define_insn "zero_extendhidi2"
755: [(set (match_operand:DI 0 "register_operand" "=r,r")
756: (zero_extend:DI (match_operand:HI 1 "general_operand" "m,r")))]
757: ""
758: "*
759: if (which_alternative==0)
760: return \"ldz.16\\t%0,%1\";
761: return \"extractz\\t%0,%1:bit 48,16\";
762: ")
763:
764: (define_insn "zero_extendqihi2"
765: [(set (match_operand:HI 0 "register_operand" "=r,r")
766: (zero_extend:HI (match_operand:QI 1 "general_operand" "m,r")))]
767: ""
768: "*
769: if (which_alternative==0)
770: return \"ldz.8\\t%0,%1\";
771: return \"extractz\\t%0,%1:bit 56,8\";
772: ")
773:
774: (define_insn "zero_extendqisi2"
775: [(set (match_operand:SI 0 "register_operand" "=r,r")
776: (zero_extend:SI (match_operand:QI 1 "general_operand" "m,r")))]
777: ""
778: "*
779: if (which_alternative==0)
780: return \"ldz.8\\t%0,%1\";
781: return \"extractz\\t%0,%1:bit 56,8\";
782: ")
783:
784: (define_insn "zero_extendqidi2"
785: [(set (match_operand:DI 0 "register_operand" "=r,r")
786: (zero_extend:DI (match_operand:QI 1 "general_operand" "m,r")))]
787: ""
788: "*
789: if (which_alternative==0)
790: return \"ldz.8\\t%0,%1\";
791: return \"extractz\\t%0,%1:bit 56,8\";
792: ")
793:
794:
795: (define_insn "ashrdi3"
796: [(set (match_operand:DI 0 "register_operand" "=r")
797: (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
798: (match_operand:SI 2 "general_operand" "rn")))]
799: ""
800: "sra\\t%0,%1,%2")
801:
802: (define_insn "lshrdi3"
803: [(set (match_operand:DI 0 "register_operand" "=r")
804: (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
805: (match_operand:SI 2 "general_operand" "rn")))]
806: ""
807: "srl\\t%0,%1,%2")
808:
809: (define_insn "ashldi3"
810: [(set (match_operand:DI 0 "register_operand" "=r")
811: (ashift:DI (match_operand:DI 1 "register_operand" "r")
812: (match_operand:SI 2 "general_operand" "rn")))]
813: ""
814: "sla\\t%0,%1,%2")
815:
816: (define_insn "anddi3"
817: [(set (match_operand:DI 0 "register_operand" "=r,r")
818: (and:DI (match_operand:DI 1 "general_operand" "%0,r")
819: (match_operand:DI 2 "general_operand" "g,g")))]
820: "1 /*which_alternative == 0 || check356(operands[2])*/"
821: "*
822: if (which_alternative == 0)
823: return \"and\\t%0,%2\";
824: return \"and\\t%0,%1,%2\";
825: ")
826:
827: (define_insn "iordi3"
828: [(set (match_operand:DI 0 "register_operand" "=r,r")
829: (ior:DI (match_operand:DI 1 "general_operand" "%0,r")
830: (match_operand:DI 2 "general_operand" "g,g")))]
831: "1 /*which_alternative == 0 || check356(operands[2])*/"
832: "*
833: if (which_alternative == 0)
834: return \"or\\t%0,%2\";
835: return \"or\\t%0,%1,%2\";
836: ")
837:
838: (define_insn "xordi3"
839: [(set (match_operand:DI 0 "register_operand" "=r,r")
840: (xor:DI (match_operand:DI 1 "general_operand" "%0,r")
841: (match_operand:DI 2 "general_operand" "g,g")))]
842: "1 /*which_alternative == 0 || check356(operands[2])*/"
843: "*
844: if (which_alternative == 0)
845: return \"xor\\t%0,%2\";
846: return \"xor\\t%0,%1,%2\";
847: ")
848:
849: (define_insn "one_cmpldi2"
850: [(set (match_operand:DI 0 "register_operand" "=r")
851: (not:DI (match_operand:DI 1 "general_operand" "rm")))]
852: ""
853: "not\\t%0,%1")
854:
855: ;; gcc 2.1 does not widen ~si into ~di.
856: (define_insn "one_cmplsi2"
857: [(set (match_operand:SI 0 "register_operand" "=r")
1.1.1.2 root 858: (not:SI (match_operand:SI 1 "register_operand" "r")))]
1.1 root 859: ""
860: "not\\t%0,%1")
861:
862: (define_insn "negdi2"
863: [(set (match_operand:DI 0 "register_operand" "=r")
864: (neg:DI (match_operand:DI 1 "general_operand" "rm")))]
865: ""
866: "neg.64\\t%0,%1")
867:
868: (define_insn "negsi2"
869: [(set (match_operand:SI 0 "register_operand" "=r,r")
870: (neg:SI (match_operand:SI 1 "general_operand" "m,r")))]
871: ""
872: "*
873: if (which_alternative == 0)
874: return \"neg.32\\t%0,%1\";
875: return \"neg.64\\t%0,%1 ; I only want 32\";
876: ")
877:
878: (define_insn "neghi2"
879: [(set (match_operand:HI 0 "register_operand" "=r,r")
880: (neg:HI (match_operand:HI 1 "general_operand" "m,r")))]
881: ""
882: "*
883: if (which_alternative == 0)
884: return \"neg.16\\t%0,%1\";
885: return \"neg.64\\t%0,%1 ; I only want 16\";
886: ")
887:
888: (define_insn "adddf3"
889: [(set (match_operand:DF 0 "register_operand" "=r")
890: (plus:DF (match_operand:DF 1 "general_operand" "%0")
891: (match_operand:DF 2 "general_operand" "rm")))]
892: ""
893: "fadd.64\\t%0,%2")
894:
895: (define_insn "addsf3"
896: [(set (match_operand:SF 0 "register_operand" "=r")
897: (plus:SF (match_operand:SF 1 "general_operand" "%0")
898: (match_operand:SF 2 "general_operand" "rm")))]
899: ""
900: "fadd.32\\t%0,%2")
901:
902: ;; There is also an addi.64 4,.r0'' optimization
903: (define_insn "adddi3"
904: [(set (match_operand:DI 0 "register_operand" "=r,r")
905: (plus:DI (match_operand:DI 1 "general_operand" "%0,r")
906: (match_operand:DI 2 "general_operand" "g,g")))]
907: "1 /*which_alternative == 0 || check356(operands[2])*/"
908: "*
909: if (which_alternative == 0)
910: return \"add.64\\t%0,%2\";
911: return \"add.64\\t%0,%1,%2\";
912: ")
913:
914: (define_insn "addsi3"
915: [(set (match_operand:SI 0 "register_operand" "=r,r,r")
916: (plus:SI (match_operand:SI 1 "general_operand" "%0,r,0")
917: (match_operand:SI 2 "general_operand" "m,m,g")))]
918: "1 /*which_alternative != 1 || check356(operands[2])*/"
919: "*
920: if (which_alternative == 0)
921: return \"add.32\\t%0,%2\";
922: if (which_alternative == 1)
923: return \"add.32\\t%0,%1,%2\";
924: return \"add.64\\t%0,%2 ; I only want 32\";
925: ")
926:
927: (define_insn "addhi3"
928: [(set (match_operand:HI 0 "register_operand" "=r,r,r")
929: (plus:HI (match_operand:HI 1 "general_operand" "%0,r,0")
930: (match_operand:HI 2 "general_operand" "m,m,g")))]
931: "1 /*which_alternative != 1 || check356(operands[2])*/"
932: "*
933: if (which_alternative == 0)
934: return \"add.16\\t%0,%2\";
935: if (which_alternative == 1)
936: return \"add.16\\t%0,%1,%2\";
937: return \"add.64\\t%0,%2 ; I only want 16\";
938: ")
939:
940: (define_insn "subdf3"
941: [(set (match_operand:DF 0 "register_operand" "=r")
942: (minus:DF (match_operand:DF 1 "general_operand" "0")
943: (match_operand:DF 2 "general_operand" "rm")))]
944: ""
945: "fsub.64\\t%0,%2")
946:
947: (define_insn "subsf3"
948: [(set (match_operand:SF 0 "register_operand" "=r")
949: (minus:SF (match_operand:SF 1 "general_operand" "0")
950: (match_operand:SF 2 "general_operand" "rm")))]
951: ""
952: "fsub.32\\t%0,%2")
953:
954: (define_insn "subdi3"
955: [(set (match_operand:DI 0 "register_operand" "=r,r,r")
956: (minus:DI (match_operand:DI 1 "general_operand" "0,g,r")
957: (match_operand:DI 2 "general_operand" "g,r,g")))]
958: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
959: "*
960: if (which_alternative == 0)
961: return \"sub.64\\t%0,%2\";
962: else if (which_alternative == 1)
963: return \"subr.64\\t%0,%2,%1\";
964: else
965: return \"sub.64\\t%0,%1,%2\";
966: ")
967:
968: (define_insn "subsi3"
969: [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
970: (minus:SI (match_operand:SI 1 "general_operand" "0,m,r,0")
971: (match_operand:SI 2 "general_operand" "m,r,m,g")))]
972: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
973: "*
974: if (which_alternative == 0)
975: return \"sub.32\\t%0,%2\";
976: else if (which_alternative == 1)
977: return \"subr.32\\t%0,%2,%1\";
978: else if (which_alternative == 2)
979: return \"sub.32\\t%0,%1,%2\";
980: else
981: return \"sub.64\\t%0,%2 ; I only want 32\";
982: ")
983:
984: (define_insn "subhi3"
985: [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
986: (minus:HI (match_operand:HI 1 "general_operand" "0,m,r,0")
987: (match_operand:HI 2 "general_operand" "m,r,m,g")))]
988: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
989: "*
990: if (which_alternative == 0)
991: return \"sub.16\\t%0,%2\";
992: else if (which_alternative == 1)
993: return \"subr.16\\t%0,%2,%1\";
994: else if (which_alternative == 2)
995: return \"sub.16\\t%0,%1,%2\";
996: else
997: return \"sub.64\\t%0,%2 ; I only want 16\";
998: ")
999:
1000: (define_insn "muldf3"
1001: [(set (match_operand:DF 0 "register_operand" "=r")
1002: (mult:DF (match_operand:DF 1 "general_operand" "%0")
1003: (match_operand:DF 2 "general_operand" "rm")))]
1004: ""
1005: "fmul.64\\t%0,%2")
1006:
1007: (define_insn "mulsf3"
1008: [(set (match_operand:SF 0 "register_operand" "=r")
1009: (mult:SF (match_operand:SF 1 "general_operand" "%0")
1010: (match_operand:SF 2 "general_operand" "rm")))]
1011: ""
1012: "fmul.32\\t%0,%2")
1013:
1014: (define_insn "muldi3"
1015: [(set (match_operand:DI 0 "register_operand" "=r,r")
1016: (mult:DI (match_operand:DI 1 "general_operand" "%0,r")
1017: (match_operand:DI 2 "general_operand" "g,g")))]
1018: "1 /*which_alternative == 0 || check356(operands[2])*/"
1019: "*
1020: if (which_alternative == 0)
1021: return \"mul.64\\t%0,%2\";
1022: return \"mul.64\\t%0,%1,%2\";
1023: ")
1024:
1025: (define_insn "mulsi3"
1026: [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1027: (mult:SI (match_operand:SI 1 "general_operand" "%0,r,0")
1028: (match_operand:SI 2 "general_operand" "m,m,g")))]
1029: "1 /*which_alternative == 0 || check356(operands[2])*/"
1030: "*
1031: if (which_alternative == 0)
1032: return \"mul.32\\t%0,%2\";
1033: else if (which_alternative == 1)
1034: return \"mul.32\\t%0,%1,%2\";
1035: else
1036: return \"mul.64\\t%0,%2 ; I only want 32\";
1037: ")
1038:
1039: (define_insn "mulhi3"
1040: [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1041: (mult:HI (match_operand:HI 1 "general_operand" "%0,r,0")
1042: (match_operand:HI 2 "general_operand" "m,m,g")))]
1043: "1 /*which_alternative == 0 || check356(operands[2])*/"
1044: "*
1045: if (which_alternative == 0)
1046: return \"mul.16\\t%0,%2\";
1047: else if (which_alternative == 1)
1048: return \"mul.16\\t%0,%1,%2\";
1049: else
1050: return \"mul.64\\t%0,%2 ; I only want 16\";
1051: ")
1052:
1053: (define_insn "divdf3"
1054: [(set (match_operand:DF 0 "register_operand" "=r")
1055: (div:DF (match_operand:DF 1 "general_operand" "0")
1056: (match_operand:DF 2 "general_operand" "rm")))]
1057: ""
1058: "fdiv.64\\t%0,%2")
1059:
1060: (define_insn "divsf3"
1061: [(set (match_operand:SF 0 "register_operand" "=r")
1062: (div:SF (match_operand:SF 1 "general_operand" "0")
1063: (match_operand:SF 2 "general_operand" "rm")))]
1064: ""
1065: "fdiv.32\\t%0,%2")
1066:
1067: (define_insn "divdi3"
1068: [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1069: (div:DI (match_operand:DI 1 "general_operand" "0,g,r")
1070: (match_operand:DI 2 "general_operand" "g,r,g")))]
1071: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
1072: "*
1073: if (which_alternative == 0)
1074: return \"div.64\\t%0,%2\";
1075: else if (which_alternative == 1)
1076: return \"divr.64\\t%0,%2,%1\";
1077: else
1078: return \"div.64\\t%0,%1,%2\";
1079: ")
1080:
1081: (define_insn "divsi3"
1082: [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1083: (div:SI (match_operand:SI 1 "general_operand" "0,m,r,0")
1084: (match_operand:SI 2 "general_operand" "m,r,m,g")))]
1085: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
1086: "*
1087: /* We don't ignore high bits. */
1088: if (0) {
1089: if (which_alternative == 0)
1090: return \"div.32\\t%0,%2\";
1091: else if (which_alternative == 1)
1092: return \"divr.32\\t%0,%2,%1\";
1093: else if (which_alternative == 2)
1094: return \"div.32\\t%0,%1,%2\";
1095: else
1096: return \"ld.32\\t%0,%0\;div.64\\t%0,%2 ; I only want 32\";
1097: } else {
1098: if (which_alternative == 0)
1099: return \"ld.32\\t%0,%0\;div.32\\t%0,%2\";
1100: else if (which_alternative == 1)
1101: return \"ld.32\\t%2,%2\;divr.32\\t%0,%2,%1\";
1102: else if (which_alternative == 2)
1103: return \"ld.32\\t%1,%1\;div.32\\t%0,%1,%2\";
1104: else
1105: return \"ld.32\\t%0,%0\;div.64\\t%0,%2 ; I only want 32\";
1106: }
1107: ")
1108:
1109: (define_insn "divhi3"
1110: [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1111: (div:HI (match_operand:HI 1 "general_operand" "0,m,r,0,0")
1112: (match_operand:HI 2 "general_operand" "m,r,m,r,i")))]
1113: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
1114: "*
1115: if (which_alternative == 0)
1116: return \"extract\\t%0,%0:bit 48,16\;div.16\\t%0,%2\";
1117: else if (which_alternative == 1)
1118: return \"extract\\t%2,%2:bit 48,16\;divr.16\\t%0,%2,%1\";
1119: else if (which_alternative == 2)
1120: return \"extract\\t%1,%1:bit 48,16\;div.16\\t%0,%1,%2\";
1121: else if (which_alternative == 3)
1122: return \"extract\\t%0,%0:bit 48,16\;extract\\t%2,%2:bit 48,16\;div.64\\t%0,%2 ; I only want 16\";
1123: else
1124: return \"extract\\t%0,%0:bit 48,16\;div.64\\t%0,%2 ; I only want 16\";
1125: ")
1126:
1127: (define_insn "modhi3"
1128: [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1129: (mod:HI (match_operand:HI 1 "general_operand" "0,m,r,0,0")
1130: (match_operand:HI 2 "general_operand" "m,r,m,r,i")))]
1131: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
1132: "*
1133: if (which_alternative == 0)
1134: return \"extract\\t%0,%0:bit 48,16\;rem.16\\t%0,%2\";
1135: else if (which_alternative == 1)
1136: return \"extract\\t%2,%2:bit 48,16\;remr.16\\t%0,%2,%1\";
1137: else if (which_alternative == 2)
1138: return \"extract\\t%1,%1:bit 48,16\;rem.16\\t%0,%1,%2\";
1139: else if (which_alternative == 3)
1140: return \"extract\\t%0,%0:bit 48,16\;extract\\t%2,%2:bit 48,16\;rem.64\\t%0,%2 ; I only want 16\";
1141: else
1142: return \"extract\\t%0,%0:bit 48,16\;rem.64\\t%0,%2 ; I only want 16\";
1143: ")
1144:
1145: (define_insn "moddi3"
1146: [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1147: (mod:DI (match_operand:DI 1 "general_operand" "0,g,r")
1148: (match_operand:DI 2 "general_operand" "g,r,g")))]
1149: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
1150: "*
1151: if (which_alternative == 0)
1152: return \"rem.64\\t%0,%2\";
1153: else if (which_alternative == 1)
1154: return \"remr.64\\t%0,%2,%1\";
1155: else
1156: return \"rem.64\\t%0,%1,%2\";
1157: ")
1158:
1159: (define_insn "modsi3"
1160: [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1161: (mod:SI (match_operand:SI 1 "general_operand" "0,m,r,0")
1162: (match_operand:SI 2 "general_operand" "m,r,m,g")))]
1163: "1 /*which_alternative == 0 || check356(operands[which_alternative])*/"
1164: "*
1165: /* There is a micro code bug with the below... */
1166: if (0) {
1167: if (which_alternative == 0)
1168: return \"rem.32\\t%0,%2\";
1169: else if (which_alternative == 1)
1170: return \"remr.32\\t%0,%2,%1\";
1171: else if (which_alternative == 2)
1172: return \"rem.32\\t%0,%1,%2\";
1173: else
1174: return \"ld.32\\t%0,%0\;rem.64\\t%0,%2 ; I only want 32\";
1175: } else {
1176: if (which_alternative == 0)
1177: return \"ld.32\\t%0,%0\;rem.32\\t%0,%2\";
1178: else if (which_alternative == 1)
1179: return \"ld.32\\t%2,%2\;remr.32\\t%0,%2,%1\";
1180: else if (which_alternative == 2)
1181: return \"ld.32\\t%1,%1\;rem.32\\t%0,%1,%2\";
1182: else
1183: return \"ld.32\\t%0,%0\;rem.64\\t%0,%2 ; I only want 32\";
1184: }
1185: ")
1186:
1187:
1188: (define_insn "jump"
1189: [(set (pc)
1190: (label_ref (match_operand 0 "" "")))]
1191: ""
1192: "jmp\\t%l0")
1193:
1194: (define_insn "indirect_jump"
1195: [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
1196: ""
1197: ;; Maybe %l0 is better, maybe we can relax register only.
1198: "verify this before use ld.32\\t.r0,%0\;br.reg\\t.r0")
1199:
1200: (define_insn "beq"
1201: [(set (pc)
1202: (if_then_else (eq (cc0)
1203: (const_int 0))
1204: (label_ref (match_operand 0 "" ""))
1205: (pc)))]
1206: ""
1207: "* return cmp_jmp(\"\", 2, operands[0]); ")
1208:
1209: (define_insn "bne"
1210: [(set (pc)
1211: (if_then_else (ne (cc0)
1212: (const_int 0))
1213: (label_ref (match_operand 0 "" ""))
1214: (pc)))]
1215: ""
1216: "* return cmp_jmp(\"\", 8, operands[0]); ")
1217:
1218: (define_insn "bgt"
1219: [(set (pc)
1220: (if_then_else (gt (cc0)
1221: (const_int 0))
1222: (label_ref (match_operand 0 "" ""))
1223: (pc)))]
1224: ""
1225: "* return cmp_jmp(\"\", 0, operands[0]); ")
1226:
1227: (define_insn "bgtu"
1228: [(set (pc)
1229: (if_then_else (gtu (cc0)
1230: (const_int 0))
1231: (label_ref (match_operand 0 "" ""))
1232: (pc)))]
1233: ""
1234: "* return cmp_jmp(\"u\", 0, operands[0]); ")
1235:
1236: (define_insn "blt"
1237: [(set (pc)
1238: (if_then_else (lt (cc0)
1239: (const_int 0))
1240: (label_ref (match_operand 0 "" ""))
1241: (pc)))]
1242: ""
1243: "* return cmp_jmp(\"\", 6, operands[0]); ")
1244:
1245: (define_insn "bltu"
1246: [(set (pc)
1247: (if_then_else (ltu (cc0)
1248: (const_int 0))
1249: (label_ref (match_operand 0 "" ""))
1250: (pc)))]
1251: ""
1252: "* return cmp_jmp(\"u\", 6, operands[0]); ")
1253:
1254: (define_insn "bge"
1255: [(set (pc)
1256: (if_then_else (ge (cc0)
1257: (const_int 0))
1258: (label_ref (match_operand 0 "" ""))
1259: (pc)))]
1260: ""
1261: "* return cmp_jmp(\"\", 4, operands[0]); ")
1262:
1263: (define_insn "bgeu"
1264: [(set (pc)
1265: (if_then_else (geu (cc0)
1266: (const_int 0))
1267: (label_ref (match_operand 0 "" ""))
1268: (pc)))]
1269: ""
1270: "* return cmp_jmp(\"u\", 4, operands[0]); ")
1271:
1272: (define_insn "ble"
1273: [(set (pc)
1274: (if_then_else (le (cc0)
1275: (const_int 0))
1276: (label_ref (match_operand 0 "" ""))
1277: (pc)))]
1278: ""
1279: "* return cmp_jmp(\"\", 10, operands[0]); ")
1280:
1281: (define_insn "bleu"
1282: [(set (pc)
1283: (if_then_else (leu (cc0)
1284: (const_int 0))
1285: (label_ref (match_operand 0 "" ""))
1286: (pc)))]
1287: ""
1288: "* return cmp_jmp(\"u\", 10, operands[0]); ")
1289:
1290: (define_insn ""
1291: [(set (pc)
1292: (if_then_else (eq (cc0)
1293: (const_int 0))
1294: (pc)
1295: (label_ref (match_operand 0 "" ""))))]
1296: ""
1297: "* return cmp_jmp(\"\", 8, operands[0]); ")
1298:
1299: (define_insn ""
1300: [(set (pc)
1301: (if_then_else (ne (cc0)
1302: (const_int 0))
1303: (pc)
1304: (label_ref (match_operand 0 "" ""))))]
1305: ""
1306: "* return cmp_jmp(\"\", 2, operands[0]); ")
1307:
1308: (define_insn ""
1309: [(set (pc)
1310: (if_then_else (gt (cc0)
1311: (const_int 0))
1312: (pc)
1313: (label_ref (match_operand 0 "" ""))))]
1314: ""
1315: "* return cmp_jmp(\"\", 10, operands[0]); ")
1316:
1317: (define_insn ""
1318: [(set (pc)
1319: (if_then_else (gtu (cc0)
1320: (const_int 0))
1321: (pc)
1322: (label_ref (match_operand 0 "" ""))))]
1323: ""
1324: "* return cmp_jmp(\"u\", 10, operands[0]); ")
1325:
1326: (define_insn ""
1327: [(set (pc)
1328: (if_then_else (lt (cc0)
1329: (const_int 0))
1330: (pc)
1331: (label_ref (match_operand 0 "" ""))))]
1332: ""
1333: "* return cmp_jmp(\"\", 4, operands[0]); ")
1334:
1335: (define_insn ""
1336: [(set (pc)
1337: (if_then_else (ltu (cc0)
1338: (const_int 0))
1339: (pc)
1340: (label_ref (match_operand 0 "" ""))))]
1341: ""
1342: "* return cmp_jmp(\"u\", 4, operands[0]); ")
1343:
1344: (define_insn ""
1345: [(set (pc)
1346: (if_then_else (ge (cc0)
1347: (const_int 0))
1348: (pc)
1349: (label_ref (match_operand 0 "" ""))))]
1350: ""
1351: "* return cmp_jmp(\"\", 6, operands[0]); ")
1352:
1353: (define_insn ""
1354: [(set (pc)
1355: (if_then_else (geu (cc0)
1356: (const_int 0))
1357: (pc)
1358: (label_ref (match_operand 0 "" ""))))]
1359: ""
1360: "* return cmp_jmp(\"u\", 6, operands[0]); ")
1361:
1362: (define_insn ""
1363: [(set (pc)
1364: (if_then_else (le (cc0)
1365: (const_int 0))
1366: (pc)
1367: (label_ref (match_operand 0 "" ""))))]
1368: ""
1369: "* return cmp_jmp(\"\", 0, operands[0]); ")
1370:
1371: (define_insn ""
1372: [(set (pc)
1373: (if_then_else (leu (cc0)
1374: (const_int 0))
1375: (pc)
1376: (label_ref (match_operand 0 "" ""))))]
1377: ""
1378: "* return cmp_jmp(\"u\", 0, operands[0]); ")
1379:
1380: ;; Note that operand 1 is total size of args, in bytes,
1381: ;; and what the call insn wants is the number of words.
1382: (define_insn "call"
1383: [(call (match_operand:QI 0 "general_operand" "m")
1384: (match_operand:QI 1 "general_operand" "g"))]
1385: ""
1386: "*
1387: if (GET_CODE (operands[0]) == MEM && GET_CODE (XEXP (operands[0], 0)) == REG)
1388: if (REGNO (XEXP (operands[0], 0)) != 0)
1389: return \"add.64\\t.sp,=-4\;ld.64\\t.r0,=.+11\;st.32\\t.r0,[.sp]\;br.reg\\t%r0\;add.64\\t.sp,=4\;add.64\\t.sp,%1\";
1390: else
1391: return \"add.64\\t.sp,=-4\;ld.64\\t.r1,=.+11\;st.32\\t.r1,[.sp]\;br.reg\\t%r0\;add.64\\t.sp,=4\;add.64\\t.sp,%1\";
1392: else
1393: return \"add.64\\t.sp,=-4\;call\\t%0\;add.64\\t.sp,=4\;add.64\\t.sp,%1\";
1394: ")
1395:
1396: (define_insn "call_value"
1397: [(set (match_operand 0 "" "g")
1398: (call (match_operand:QI 1 "general_operand" "m")
1399: (match_operand:QI 2 "general_operand" "g")))]
1400: ""
1401: "*
1402: if (GET_CODE (operands[1]) == MEM && GET_CODE (XEXP (operands[1], 0)) == REG)
1403: if (REGNO (XEXP (operands[1], 0)) != 0)
1404: return \"add.64\\t.sp,=-4\;ld.64\\t.r0,=.+11\;st.32\\t.r0,[.sp]\;br.reg\\t%r1\;add.64\\t.sp,=4\;add.64\\t.sp,%2\";
1405: else
1406: return \"add.64\\t.sp,=-4\;ld.64\\t.r1,=.+11\;st.32\\t.r1,[.sp]\;br.reg\\t%r1\;add.64\\t.sp,=4\;add.64\\t.sp,%2\";
1407: else
1408: return \"add.64\\t.sp,=-4\;call\\t%1\;add.64\\t.sp,=4\;add.64\\t.sp,%2\";
1409: ")
1410:
1411: (define_insn "tablejump"
1412: [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1413: (use (label_ref (match_operand 1 "" "")))]
1414: ""
1415: "br.reg\\t%0")
1416:
1417: (define_insn "nop"
1418: [(const_int 0)]
1419: ""
1420: "nop")
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