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1.1 root 1: /* Definitions of target machine for GNU compiler. Alliant FX version. 1.1.1.4 ! root 2: Copyright (C) 1989, 1993, 1994, 1995 Free Software Foundation, Inc. 1.1 root 3: Adapted from m68k.h by Paul Petersen ([email protected]) 4: and Joe Weening ([email protected]). 5: 6: This file is part of GNU CC. 7: 8: GNU CC is free software; you can redistribute it and/or modify 9: it under the terms of the GNU General Public License as published by 10: the Free Software Foundation; either version 2, or (at your option) 11: any later version. 12: 13: GNU CC is distributed in the hope that it will be useful, 14: but WITHOUT ANY WARRANTY; without even the implied warranty of 15: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16: GNU General Public License for more details. 17: 18: You should have received a copy of the GNU General Public License 19: along with GNU CC; see the file COPYING. If not, write to 1.1.1.4 ! root 20: the Free Software Foundation, 59 Temple Place - Suite 330, ! 21: Boston, MA 02111-1307, USA. */ 1.1 root 22: 23: 24: /* This file is based on m68k.h, simplified by removing support for 25: the Sun FPA and other things not applicable to the Alliant. Some 26: remnants of these features remain. */ 27: 28: /* Names to predefine in the preprocessor for this target machine. */ 29: 1.1.1.2 root 30: #define CPP_PREDEFINES "-Dmc68000 -Dalliant -Dunix -Asystem(unix) -Acpu(m68k) -Amachine(m68k)" 1.1 root 31: 32: /* Print subsidiary information on the compiler version in use. */ 33: 34: #define TARGET_VERSION fprintf (stderr, " (Alliant)"); 35: 36: /* Run-time compilation parameters selecting different hardware 37: subsets. The Alliant IP is an mc68020. (Older mc68010-based IPs 38: are no longer supported.) The Alliant CE is 68020-compatible, and 39: also has floating point, vector and concurrency instructions. 40: 41: Although the IP doesn't have floating point, it emulates it in the 42: operating system. Using this generally is faster than running code 43: compiled with -msoft-float, because the soft-float code still uses 44: (simulated) FP registers and ends up emulating several fmove{s,d} 45: instructions per call. So I don't recommend using soft-float for 46: any Alliant code. -- JSW 47: */ 48: 49: extern int target_flags; 50: 51: /* Macros used in the machine description to test the flags. */ 52: 53: /* Compile for a 68020 (not a 68000 or 68010). */ 54: #define TARGET_68020 (target_flags & 1) 55: /* Compile CE insns for floating point (not library calls). */ 56: #define TARGET_CE (target_flags & 2) 57: /* Compile using 68020 bitfield insns. */ 58: #define TARGET_BITFIELD (target_flags & 4) 59: /* Compile with 16-bit `int'. */ 60: #define TARGET_SHORT (target_flags & 040) 61: 62: /* Default 3 means compile 68020 and CE instructions. We don't use 63: bitfield instructions because there appears to be a bug in the 64: implementation of bfins on the CE. */ 65: 66: #define TARGET_DEFAULT 3 67: 68: /* Define __HAVE_CE__ in preprocessor according to the -m flags. 69: This will control the use of inline FP insns in certain macros. 70: Also inform the program which CPU this is for. */ 71: 72: #if TARGET_DEFAULT & 02 73: 74: /* -mce is the default */ 75: #define CPP_SPEC \ 76: "%{!msoft-float:-D__HAVE_CE__ }\ 77: %{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}" 78: 79: #else 80: 81: /* -msoft-float is the default */ 82: #define CPP_SPEC \ 83: "%{mce:-D__HAVE_CE__ }\ 84: %{m68000:-Dmc68010}%{mc68000:-Dmc68010}%{!mc68000:%{!m68000:-Dmc68020}}" 85: 86: #endif 87: 88: /* Link with libg.a when debugging, for dbx's sake. */ 89: 90: #define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} " 91: 92: /* Make the linker remove temporary labels, since the Alliant assembler 93: doesn't. */ 94: 95: #define LINK_SPEC "-X" 96: 97: /* Every structure or union's size must be a multiple of 2 bytes. */ 98: 99: #define STRUCTURE_SIZE_BOUNDARY 16 100: 101: /* This is BSD, so it wants DBX format. */ 102: 103: #define DBX_DEBUGGING_INFO 104: 105: /* Macro to define tables used to set the flags. 106: This is a list in braces of pairs in braces, 107: each pair being { "NAME", VALUE } 108: where VALUE is the bits to set or minus the bits to clear. 109: An empty string NAME is used to identify the default VALUE. */ 110: 111: #define TARGET_SWITCHES \ 112: { { "68020", 5}, \ 113: { "c68020", 5}, \ 114: { "bitfield", 4}, \ 115: { "68000", -7}, \ 116: { "c68000", -7}, \ 117: { "soft-float", -2}, \ 118: { "nobitfield", -4}, \ 119: { "short", 040}, \ 120: { "noshort", -040}, \ 121: { "", TARGET_DEFAULT}} 122: 123: /* target machine storage layout */ 124: 125: /* Define this if most significant bit is lowest numbered 126: in instructions that operate on numbered bit-fields. 127: This is true for 68020 insns such as bfins and bfexts. 128: We make it true always by avoiding using the single-bit insns 129: except in special cases with constant bit numbers. */ 130: #define BITS_BIG_ENDIAN 1 131: 132: /* Define this if most significant byte of a word is the lowest numbered. */ 133: /* That is true on the 68000. */ 134: #define BYTES_BIG_ENDIAN 1 135: 136: /* Define this if most significant word of a multiword number is the lowest 137: numbered. */ 138: /* For 68000 we can decide arbitrarily 139: since there are no machine instructions for them. */ 140: #define WORDS_BIG_ENDIAN 0 141: 142: /* number of bits in an addressable storage unit */ 143: #define BITS_PER_UNIT 8 144: 145: /* Width in bits of a "word", which is the contents of a machine register. 146: Note that this is not necessarily the width of data type `int'; 147: if using 16-bit ints on a 68000, this would still be 32. 148: But on a machine with 16-bit registers, this would be 16. */ 149: #define BITS_PER_WORD 32 150: 151: /* Width of a word, in units (bytes). */ 152: #define UNITS_PER_WORD 4 153: 154: /* Width in bits of a pointer. 155: See also the macro `Pmode' defined below. */ 156: #define POINTER_SIZE 32 157: 158: /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 159: #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32) 160: 161: /* Boundary (in *bits*) on which stack pointer should be aligned. */ 162: #define STACK_BOUNDARY 16 163: 164: /* Allocation boundary (in *bits*) for the code of a function. */ 165: #define FUNCTION_BOUNDARY 16 166: 167: /* Alignment of field after `int : 0' in a structure. */ 168: #define EMPTY_FIELD_BOUNDARY 16 169: 170: /* No data type wants to be aligned rounder than this. */ 171: #define BIGGEST_ALIGNMENT 16 172: 173: /* Set this non-zero if move instructions will actually fail to work 174: when given unaligned data. */ 175: #define STRICT_ALIGNMENT 1 176: 177: /* Define number of bits in most basic integer type. 178: (If undefined, default is BITS_PER_WORD). */ 179: 180: #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32) 181: 182: /* Define these to avoid dependence on meaning of `int'. 183: Note that WCHAR_TYPE_SIZE is used in cexp.y, 184: where TARGET_SHORT is not available. */ 185: 186: #define WCHAR_TYPE "long int" 187: #define WCHAR_TYPE_SIZE 32 188: 189: /* Standard register usage. */ 190: 191: /* Number of actual hardware registers. 192: The hardware registers are assigned numbers for the compiler 193: from 0 to just below FIRST_PSEUDO_REGISTER. 194: All registers that the compiler knows about must be given numbers, 195: even those that are not normally considered general registers. 196: For the Alliant, we give the data registers numbers 0-7, 197: the address registers numbers 010-017, 198: and the floating point registers numbers 020-027. */ 199: #define FIRST_PSEUDO_REGISTER 24 200: 201: /* 1 for registers that have pervasive standard uses 202: and are not available for the register allocator. 203: On the Alliant, these are a0 (argument pointer), 204: a6 (frame pointer) and a7 (stack pointer). */ 205: #define FIXED_REGISTERS \ 206: {0, 0, 0, 0, 0, 0, 0, 0, \ 207: 1, 0, 0, 0, 0, 0, 1, 1, \ 208: 0, 0, 0, 0, 0, 0, 0, 0 } 209: 210: /* 1 for registers not available across function calls. 211: These must include the FIXED_REGISTERS and also any 212: registers that can be used without being saved. 213: The latter must include the registers where values are returned 214: and the register where structure-value addresses are passed. 215: Aside from that, you can include as many other registers as you like. 216: The Alliant calling sequence allows a function to use any register, 217: so we include them all here. */ 218: 219: #define CALL_USED_REGISTERS \ 220: {1, 1, 1, 1, 1, 1, 1, 1, \ 221: 1, 1, 1, 1, 1, 1, 1, 1, \ 222: 1, 1, 1, 1, 1, 1, 1, 1 } 223: 224: /* Return number of consecutive hard regs needed starting at reg REGNO 225: to hold something of mode MODE. 226: This is ordinarily the length in words of a value of mode MODE 227: but can be less for certain modes in special long registers. 228: 229: On the Alliant, ordinary registers hold 32 bits worth; 230: for the FP registers, a single register is always enough for 231: any floating-point value. */ 232: #define HARD_REGNO_NREGS(REGNO, MODE) \ 233: ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \ 234: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 235: 236: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 237: On the Alliant, the cpu registers can hold any mode but the FP registers 238: can hold only floating point. */ 239: #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 240: ((REGNO) < 16 || GET_MODE_CLASS (MODE) == MODE_FLOAT \ 241: || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) 242: 243: /* Value is 1 if it is a good idea to tie two pseudo registers 244: when one has mode MODE1 and one has mode MODE2. 245: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 246: for any hard reg, then this must be 0 for correct output. */ 247: #define MODES_TIEABLE_P(MODE1, MODE2) \ 248: (((MODE1) == SFmode || (MODE1) == DFmode \ 249: || (MODE1) == SCmode || (MODE1) == DCmode) \ 250: == ((MODE2) == SFmode || (MODE2) == DFmode \ 251: || (MODE2) == SCmode || (MODE2) == DCmode)) 252: 253: /* Specify the registers used for certain standard purposes. 254: The values of these macros are register numbers. */ 255: 256: /* m68000 pc isn't overloaded on a register. */ 257: /* #define PC_REGNUM */ 258: 259: /* Register to use for pushing function arguments. */ 260: #define STACK_POINTER_REGNUM 15 261: 262: /* Base register for access to local variables of the function. */ 263: #define FRAME_POINTER_REGNUM 14 264: 265: /* Value should be nonzero if functions must have frame pointers. 266: Zero means the frame pointer need not be set up (and parms 267: may be accessed via the stack pointer) in functions that seem suitable. 268: This is computed in `reload', in reload1.c. */ 269: /* Set for now on Alliant until we find a way to make this work with 270: their calling sequence. */ 271: #define FRAME_POINTER_REQUIRED 1 272: 273: /* Base register for access to arguments of the function. */ 274: #define ARG_POINTER_REGNUM 8 275: 276: /* Register in which static-chain is passed to a function. */ 277: #define STATIC_CHAIN_REGNUM 10 278: 279: /* Register in which address to store a structure value 280: is passed to a function. */ 281: #define STRUCT_VALUE_REGNUM 9 282: 283: /* Define the classes of registers for register constraints in the 284: machine description. Also define ranges of constants. 285: 286: One of the classes must always be named ALL_REGS and include all hard regs. 287: If there is more than one class, another class must be named NO_REGS 288: and contain no registers. 289: 290: The name GENERAL_REGS must be the name of a class (or an alias for 291: another name such as ALL_REGS). This is the class of registers 292: that is allowed by "g" or "r" in a register constraint. 293: Also, registers outside this class are allocated only when 294: instructions express preferences for them. 295: 296: The classes must be numbered in nondecreasing order; that is, 297: a larger-numbered class must never be contained completely 298: in a smaller-numbered class. 299: 300: For any two classes, it is very desirable that there be another 301: class that represents their union. */ 302: 303: /* The Alliant has three kinds of registers, so eight classes would be 304: a complete set. One of them is not needed. */ 305: 306: enum reg_class { NO_REGS, FP_REGS, DATA_REGS, DATA_OR_FP_REGS, 307: ADDR_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES }; 308: 309: #define N_REG_CLASSES (int) LIM_REG_CLASSES 310: 311: /* Give names of register classes as strings for dump file. */ 312: 313: #define REG_CLASS_NAMES \ 314: { "NO_REGS", "FP_REGS", "DATA_REGS", "DATA_OR_FP_REGS", \ 315: "ADDR_REGS", "GENERAL_REGS", "ALL_REGS" } 316: 317: /* Define which registers fit in which classes. 318: This is an initializer for a vector of HARD_REG_SET 319: of length N_REG_CLASSES. */ 320: 321: #define REG_CLASS_CONTENTS \ 322: { \ 323: 0, /* NO_REGS */ \ 324: 0x00ff0000, /* FP_REGS */ \ 325: 0x000000ff, /* DATA_REGS */ \ 326: 0x00ff00ff, /* DATA_OR_FP_REGS */ \ 327: 0x0000ff00, /* ADDR_REGS */ \ 328: 0x0000ffff, /* GENERAL_REGS */ \ 329: 0x00ffffff /* ALL_REGS */ \ 330: } 331: 332: /* The same information, inverted: 333: Return the class number of the smallest class containing 334: reg number REGNO. This could be a conditional expression 335: or could index an array. */ 336: 337: extern enum reg_class regno_reg_class[]; 338: #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3]) 339: 340: /* The class value for index registers, and the one for base regs. */ 341: 342: #define INDEX_REG_CLASS GENERAL_REGS 343: #define BASE_REG_CLASS ADDR_REGS 344: 345: /* Get reg_class from a letter such as appears in the machine description. */ 346: 347: #define REG_CLASS_FROM_LETTER(C) \ 348: ((C) == 'a' ? ADDR_REGS : \ 349: ((C) == 'd' ? DATA_REGS : \ 350: ((C) == 'f' ? FP_REGS : \ 351: NO_REGS))) 352: 353: /* The letters I, J, K, L and M in a register constraint string 354: can be used to stand for particular ranges of immediate operands. 355: This macro defines what the ranges are. 356: C is the letter, and VALUE is a constant value. 357: Return 1 if VALUE is in the range specified by C. 358: 359: For the 68000, `I' is used for the range 1 to 8 360: allowed as immediate shift counts and in addq. 361: `J' is used for the range of signed numbers that fit in 16 bits. 362: `K' is for numbers that moveq can't handle. 363: `L' is for range -8 to -1, range of values that can be added with subq. */ 364: 365: #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 366: ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \ 367: (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \ 368: (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \ 369: (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : 0) 370: 371: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0 372: 373: /* Given an rtx X being reloaded into a reg required to be 374: in class CLASS, return the class of reg to actually use. 375: In general this is just CLASS; but on some machines 376: in some cases it is preferable to use a more restrictive class. 377: On the 68000 series, use a data reg if possible when the 378: value is a constant in the range where moveq could be used 379: and we ensure that QImodes are reloaded into data regs. */ 380: 381: #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 382: ((GET_CODE (X) == CONST_INT \ 383: && (unsigned) (INTVAL (X) + 0x80) < 0x100 \ 384: && (CLASS) != ADDR_REGS) \ 385: ? DATA_REGS \ 386: : GET_MODE (X) == QImode \ 387: ? DATA_REGS \ 388: : (CLASS)) 389: 390: /* Return the maximum number of consecutive registers 391: needed to represent mode MODE in a register of class CLASS. */ 392: /* On the 68000, this is the size of MODE in words, 393: except in the FP regs, where a single reg is always enough. */ 394: #define CLASS_MAX_NREGS(CLASS, MODE) \ 395: ((CLASS) == FP_REGS ? 1 \ 396: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 397: 398: /* Moves between fp regs and other regs are two insns. */ 399: #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ 400: ((((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \ 401: || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS)) \ 402: ? 4 : 2) 403: 404: /* Stack layout; function entry, exit and calling. */ 405: 406: /* Define this if pushing a word on the stack 407: makes the stack pointer a smaller address. */ 408: #define STACK_GROWS_DOWNWARD 409: 410: /* Define this if the nominal address of the stack frame 411: is at the high-address end of the local variables; 412: that is, each additional local variable allocated 413: goes at a more negative offset in the frame. */ 414: #define FRAME_GROWS_DOWNWARD 415: 416: /* The Alliant uses -fcaller-saves by default. */ 417: #define DEFAULT_CALLER_SAVES 418: 419: /* Offset within stack frame to start allocating local variables at. 420: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 421: first local allocated. Otherwise, it is the offset to the BEGINNING 422: of the first local allocated. */ 423: #define STARTING_FRAME_OFFSET -4 424: 425: /* If we generate an insn to push BYTES bytes, 426: this says how many the stack pointer really advances by. 427: On the 68000, sp@- in a byte insn really pushes a word. */ 428: #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1) 429: 430: /* Offset of first parameter from the argument pointer register value. */ 431: #define FIRST_PARM_OFFSET(FNDECL) 0 432: 433: /* Value is the number of bytes of arguments automatically 434: popped when returning from a subroutine call. 1.1.1.4 ! root 435: FUNDECL is the declaration node of the function (as a tree), 1.1 root 436: FUNTYPE is the data type of the function (as a tree), 437: or for a library call it is an identifier node for the subroutine name. 438: SIZE is the number of bytes of arguments passed on the stack. 439: 440: On the Alliant we define this as SIZE and make the calling sequence 441: (in alliant.md) pop the args. This wouldn't be necessary if we 442: could add to the pending stack adjustment the size of the argument 443: descriptors that are pushed after the arguments. */ 444: 1.1.1.4 ! root 445: #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) (SIZE) 1.1 root 446: 447: /* Define how to find the value returned by a function. 448: VALTYPE is the data type of the value (as a tree). 449: If the precise function being called is known, FUNC is its FUNCTION_DECL; 450: otherwise, FUNC is 0. */ 451: 452: /* On the Alliant the return value is in FP0 if real, else D0. */ 453: 454: #define FUNCTION_VALUE(VALTYPE, FUNC) \ 455: (TREE_CODE (VALTYPE) == REAL_TYPE \ 456: ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \ 457: : gen_rtx (REG, TYPE_MODE (VALTYPE), 0)) 458: 459: /* Define how to find the value returned by a library function 460: assuming the value has mode MODE. */ 461: 462: /* On the Alliant the return value is in FP0 if real, else D0. The 463: Alliant library functions for floating-point emulation return their 464: values both in FP0 and in D0/D1. But since not all libgcc functions 465: return the results of these directly, we cannot assume that D0/D1 466: contain the values we expect on return from a libgcc function. */ 467: 468: #define LIBCALL_VALUE(MODE) \ 469: (((MODE) == DFmode || (MODE) == SFmode) \ 470: ? gen_rtx (REG, MODE, 16) \ 471: : gen_rtx (REG, MODE, 0)) 472: 473: /* 1 if N is a possible register number for a function value. 474: On the Alliant, D0 and FP0 are the only registers thus used. 475: (No need to mention D1 when used as a pair with D0.) */ 476: 477: #define FUNCTION_VALUE_REGNO_P(N) (((N) & ~16) == 0) 478: 479: /* Define this if PCC uses the nonreentrant convention for returning 480: structure and union values. */ 481: 482: #define PCC_STATIC_STRUCT_RETURN 483: 484: /* 1 if N is a possible register number for function argument passing. 485: On the Alliant, no registers are used in this way. */ 486: 487: #define FUNCTION_ARG_REGNO_P(N) 0 488: 489: /* Define a data type for recording info about an argument list 490: during the scan of that argument list. This data type should 491: hold all necessary information about the function itself 492: and about the args processed so far, enough to enable macros 493: such as FUNCTION_ARG to determine where the next arg should go. 494: 495: On the Alliant, this is a single integer, which is a number of bytes 496: of arguments scanned so far. */ 497: 498: #define CUMULATIVE_ARGS int 499: 500: /* Initialize a variable CUM of type CUMULATIVE_ARGS 501: for a call to a function whose data type is FNTYPE. 502: For a library call, FNTYPE is 0. 503: 504: On the Alliant, the offset starts at 0. */ 505: 506: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ 507: ((CUM) = 0) 508: 509: /* Update the data in CUM to advance over an argument 510: of mode MODE and data type TYPE. 511: (TYPE is null for libcalls where that information may not be available.) */ 512: 513: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 514: ((CUM) += ((MODE) != BLKmode \ 515: ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ 516: : (int_size_in_bytes (TYPE) + 3) & ~3)) 517: 518: /* Define where to put the arguments to a function. 519: Value is zero to push the argument on the stack, 520: or a hard register in which to store the argument. 521: 522: MODE is the argument's machine mode. 523: TYPE is the data type of the argument (as a tree). 524: This is null for libcalls where that information may 525: not be available. 526: CUM is a variable of type CUMULATIVE_ARGS which gives info about 527: the preceding args and about the function being called. 528: NAMED is nonzero if this argument is a named parameter 529: (otherwise it is an extra parameter matching an ellipsis). */ 530: 531: /* On the Alliant all args are pushed. */ 532: 533: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0 534: 535: /* For an arg passed partly in registers and partly in memory, 536: this is the number of registers used. 537: For args passed entirely in registers or entirely in memory, zero. */ 538: 539: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 540: 541: /* This macro generates the assembly code for function entry. 542: FILE is a stdio stream to output the code to. 543: SIZE is an int: how many units of temporary storage to allocate. 544: Refer to the array `regs_ever_live' to determine which registers 545: to save; `regs_ever_live[I]' is nonzero if register number I 546: is ever used in the function. This macro is responsible for 547: knowing which registers should not be saved even if used. 548: The Alliant uses caller-saves, so this macro is very simple. */ 549: 550: #define FUNCTION_PROLOGUE(FILE, SIZE) \ 551: { int fsize = ((SIZE) - STARTING_FRAME_OFFSET + 3) & -4; \ 552: if (frame_pointer_needed) \ 553: { \ 554: if (fsize < 0x8000) \ 555: fprintf(FILE,"\tlinkw a6,#%d\n", -fsize); \ 556: else if (TARGET_68020) \ 557: fprintf(FILE,"\tlinkl a6,#%d\n", -fsize); \ 558: else \ 559: fprintf(FILE,"\tlinkw a6,#0\n\tsubl #%d,sp\n", fsize); \ 560: fprintf(FILE, "\tmovl a0,a6@(-4)\n" ); }} 561: 562: /* Output assembler code to FILE to increment profiler label # LABELNO 563: for profiling a function entry. */ 564: 565: #define FUNCTION_PROFILER(FILE, LABELNO) \ 566: fprintf (FILE, "\tjbsr __mcount_\n") 567: 568: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 569: the stack pointer does not matter. The value is tested only in 570: functions that have frame pointers. 571: No definition is equivalent to always zero. */ 572: 573: #define EXIT_IGNORE_STACK 1 574: 575: /* This macro generates the assembly code for function exit, 576: on machines that need it. If FUNCTION_EPILOGUE is not defined 577: then individual return instructions are generated for each 578: return statement. Args are same as for FUNCTION_PROLOGUE. 579: 580: The function epilogue should not depend on the current stack pointer! 581: It should use the frame pointer only. This is mandatory because 582: of alloca; we also take advantage of it to omit stack adjustments 583: before returning. */ 584: 585: #define FUNCTION_EPILOGUE(FILE, SIZE) \ 586: { if (frame_pointer_needed) \ 587: fprintf (FILE, "\tunlk a6\n"); \ 588: fprintf (FILE, "\trts\n"); } 589: 590: /* Store in the variable DEPTH the initial difference between the 591: frame pointer reg contents and the stack pointer reg contents, 592: as of the start of the function body. This depends on the layout 593: of the fixed parts of the stack frame and on how registers are saved. */ 594: 595: #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \ 596: { \ 597: int regno; \ 598: int offset = -4; \ 599: for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \ 600: if (regs_ever_live[regno] && ! call_used_regs[regno]) \ 601: offset += 12; \ 602: for (regno = 0; regno < 16; regno++) \ 603: if (regs_ever_live[regno] && ! call_used_regs[regno]) \ 604: offset += 4; \ 605: (DEPTH) = offset - ((get_frame_size () + 3) & -4); \ 606: } 607: 608: /* Addressing modes, and classification of registers for them. */ 609: 610: #define HAVE_POST_INCREMENT 611: /* #define HAVE_POST_DECREMENT */ 612: 613: #define HAVE_PRE_DECREMENT 614: /* #define HAVE_PRE_INCREMENT */ 615: 616: /* Macros to check register numbers against specific register classes. */ 617: 618: /* These assume that REGNO is a hard or pseudo reg number. 619: They give nonzero only if REGNO is a hard reg of the suitable class 620: or a pseudo reg currently allocated to a suitable hard reg. 621: Since they use reg_renumber, they are safe only once reg_renumber 622: has been allocated, which happens in local-alloc.c. */ 623: 624: #define REGNO_OK_FOR_INDEX_P(REGNO) \ 625: ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16) 626: #define REGNO_OK_FOR_BASE_P(REGNO) \ 627: (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8) 628: #define REGNO_OK_FOR_DATA_P(REGNO) \ 629: ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8) 630: #define REGNO_OK_FOR_FP_P(REGNO) \ 631: (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8) 632: 633: /* Now macros that check whether X is a register and also, 634: strictly, whether it is in a specified class. 635: 636: These macros are specific to the 68000, and may be used only 637: in code for printing assembler insns and in conditions for 638: define_optimization. */ 639: 640: /* 1 if X is a data register. */ 641: 642: #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X))) 643: 644: /* 1 if X is an fp register. */ 645: 646: #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) 647: 648: /* 1 if X is an address register */ 649: 650: #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X))) 651: 652: /* Maximum number of registers that can appear in a valid memory address. */ 653: 654: #define MAX_REGS_PER_ADDRESS 2 655: 656: /* Recognize any constant value that is a valid address. */ 657: 658: #define CONSTANT_ADDRESS_P(X) \ 659: (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 660: || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ 661: || GET_CODE (X) == HIGH) 662: 663: /* Nonzero if the constant value X is a legitimate general operand. 664: It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 665: 666: /* Alliant FP instructions don't take immediate operands, so this 667: forces them into memory. */ 668: #define LEGITIMATE_CONSTANT_P(X) (GET_CODE (X) != CONST_DOUBLE) 669: 670: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 671: and check its validity for a certain class. 672: We have two alternate definitions for each of them. 673: The usual definition accepts all pseudo regs; the other rejects 674: them unless they have been allocated suitable hard regs. 675: The symbol REG_OK_STRICT causes the latter definition to be used. 676: 677: Most source files want to accept pseudo regs in the hope that 678: they will get allocated to the class that the insn wants them to be in. 679: Source files for reload pass need to be strict. 680: After reload, it makes no difference, since pseudo regs have 681: been eliminated by then. */ 682: 683: #ifndef REG_OK_STRICT 684: 685: /* Nonzero if X is a hard reg that can be used as an index 686: or if it is a pseudo reg. */ 687: #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8) 688: /* Nonzero if X is a hard reg that can be used as a base reg 689: or if it is a pseudo reg. */ 690: #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0) 691: 692: #else 693: 694: /* Nonzero if X is a hard reg that can be used as an index. */ 695: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 696: /* Nonzero if X is a hard reg that can be used as a base reg. */ 697: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 698: 699: #endif 700: 701: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 702: that is a valid memory address for an instruction. 703: The MODE argument is the machine mode for the MEM expression 704: that wants to use this address. 705: 706: The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ 707: 708: #define INDIRECTABLE_1_ADDRESS_P(X) \ 709: (CONSTANT_ADDRESS_P (X) \ 710: || (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ 711: || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \ 712: && REG_P (XEXP (X, 0)) \ 713: && REG_OK_FOR_BASE_P (XEXP (X, 0))) \ 714: || (GET_CODE (X) == PLUS \ 715: && REG_P (XEXP (X, 0)) && REG_OK_FOR_BASE_P (XEXP (X, 0)) \ 716: && GET_CODE (XEXP (X, 1)) == CONST_INT \ 717: && ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) 718: 719: #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \ 720: { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; } 721: 722: #define GO_IF_INDEXABLE_BASE(X, ADDR) \ 723: { if (GET_CODE (X) == LABEL_REF) goto ADDR; \ 724: if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) goto ADDR; } 725: 726: #define GO_IF_INDEXING(X, ADDR) \ 727: { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \ 728: { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \ 729: if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \ 730: { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } } 731: 732: #define GO_IF_INDEXED_ADDRESS(X, ADDR) \ 733: { GO_IF_INDEXING (X, ADDR); \ 734: if (GET_CODE (X) == PLUS) \ 735: { if (GET_CODE (XEXP (X, 1)) == CONST_INT \ 736: && (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100) \ 737: { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \ 738: if (GET_CODE (XEXP (X, 0)) == CONST_INT \ 739: && (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100) \ 740: { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } } 741: 742: #define LEGITIMATE_INDEX_REG_P(X) \ 743: ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ 744: || (GET_CODE (X) == SIGN_EXTEND \ 745: && GET_CODE (XEXP (X, 0)) == REG \ 746: && GET_MODE (XEXP (X, 0)) == HImode \ 747: && REG_OK_FOR_INDEX_P (XEXP (X, 0)))) 748: 749: #define LEGITIMATE_INDEX_P(X) \ 750: (LEGITIMATE_INDEX_REG_P (X) \ 751: || (TARGET_68020 && GET_CODE (X) == MULT \ 752: && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \ 753: && GET_CODE (XEXP (X, 1)) == CONST_INT \ 754: && (INTVAL (XEXP (X, 1)) == 2 \ 755: || INTVAL (XEXP (X, 1)) == 4 \ 756: || INTVAL (XEXP (X, 1)) == 8))) 757: 758: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 759: { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \ 760: GO_IF_INDEXED_ADDRESS (X, ADDR); } 761: 762: /* Try machine-dependent ways of modifying an illegitimate address 763: to be legitimate. If we find one, return the new, valid address. 764: This macro is used in only one place: `memory_address' in explow.c. 765: 766: OLDX is the address as it was before break_out_memory_refs was called. 767: In some cases it is useful to look at this to decide what needs to be done. 768: 769: MODE and WIN are passed so that this macro can use 770: GO_IF_LEGITIMATE_ADDRESS. 771: 772: It is always safe for this macro to do nothing. It exists to recognize 773: opportunities to optimize the output. 774: 775: For the 68000, we handle X+REG by loading X into a register R and 776: using R+REG. R will go in an address reg and indexing will be used. 777: However, if REG is a broken-out memory address or multiplication, 778: nothing needs to be done because REG can certainly go in an address reg. */ 779: 780: #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 781: { register int ch = (X) != (OLDX); \ 782: if (GET_CODE (X) == PLUS) \ 783: { if (GET_CODE (XEXP (X, 0)) == MULT) \ 784: ch = 1, XEXP (X, 0) = force_operand (XEXP (X, 0), 0); \ 785: if (GET_CODE (XEXP (X, 1)) == MULT) \ 786: ch = 1, XEXP (X, 1) = force_operand (XEXP (X, 1), 0); \ 787: if (ch && GET_CODE (XEXP (X, 1)) == REG \ 788: && GET_CODE (XEXP (X, 0)) == REG) \ 789: goto WIN; \ 790: if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \ 791: if (GET_CODE (XEXP (X, 0)) == REG \ 792: || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \ 793: && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ 794: && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \ 795: { register rtx temp = gen_reg_rtx (Pmode); \ 796: register rtx val = force_operand (XEXP (X, 1), 0); \ 797: emit_move_insn (temp, val); \ 798: XEXP (X, 1) = temp; \ 799: goto WIN; } \ 800: else if (GET_CODE (XEXP (X, 1)) == REG \ 801: || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \ 802: && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \ 803: && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \ 804: { register rtx temp = gen_reg_rtx (Pmode); \ 805: register rtx val = force_operand (XEXP (X, 0), 0); \ 806: emit_move_insn (temp, val); \ 807: XEXP (X, 0) = temp; \ 808: goto WIN; }}} 809: 810: /* Go to LABEL if ADDR (a legitimate address expression) 811: has an effect that depends on the machine mode it is used for. 812: On the 68000, only predecrement and postincrement address depend thus 813: (the amount of decrement or increment being the length of the operand). */ 814: 815: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 816: if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL 817: 818: /* Specify the machine mode that this machine uses 819: for the index in the tablejump instruction. */ 820: #define CASE_VECTOR_MODE HImode 821: 822: /* Define this if the tablejump instruction expects the table 823: to contain offsets from the address of the table. 824: Do not define this if the table should contain absolute addresses. */ 825: #define CASE_VECTOR_PC_RELATIVE 826: 827: /* Specify the tree operation to be used to convert reals to integers. */ 828: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR 829: 830: /* This is the kind of divide that is easiest to do in the general case. */ 831: #define EASY_DIV_EXPR TRUNC_DIV_EXPR 832: 833: /* Define this as 1 if `char' should by default be signed; else as 0. */ 834: #define DEFAULT_SIGNED_CHAR 1 835: 836: /* Max number of bytes we can move from memory to memory 837: in one reasonably fast instruction. */ 838: #define MOVE_MAX 4 839: 840: /* Define this if zero-extension is slow (more than one real instruction). */ 841: #define SLOW_ZERO_EXTEND 842: 843: /* Nonzero if access to memory by bytes is slow and undesirable. */ 844: #define SLOW_BYTE_ACCESS 0 845: 1.1.1.2 root 846: /* Define this to be nonzero if shift instructions ignore all but the low-order 847: few bits. */ 848: #define SHIFT_COUNT_TRUNCATED 1 1.1 root 849: 850: /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 851: is done just by pretending it is already truncated. */ 852: #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 853: 854: /* We assume that the store-condition-codes instructions store 0 for false 855: and some other value for true. This is the value stored for true. */ 856: 857: #define STORE_FLAG_VALUE -1 858: 859: /* When a prototype says `char' or `short', really pass an `int'. */ 860: #define PROMOTE_PROTOTYPES 861: 862: /* Specify the machine mode that pointers have. 863: After generation of rtl, the compiler makes no further distinction 864: between pointers and any other objects of this machine mode. */ 865: #define Pmode SImode 866: 867: /* A function address in a call instruction 868: is a byte address (for indexing purposes) 869: so give the MEM rtx a byte's mode. */ 870: #define FUNCTION_MODE QImode 871: 872: /* Compute the cost of computing a constant rtl expression RTX 873: whose rtx-code is CODE. The body of this macro is a portion 874: of a switch statement. If the code is computed here, 875: return it with a return statement. Otherwise, break from the switch. */ 876: 877: #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ 878: case CONST_INT: \ 879: /* Constant zero is super cheap due to clr instruction. */ \ 880: if (RTX == const0_rtx) return 0; \ 881: if ((unsigned) INTVAL (RTX) < 077) return 1; \ 882: case CONST: \ 883: case LABEL_REF: \ 884: case SYMBOL_REF: \ 885: return 3; \ 886: case CONST_DOUBLE: \ 887: return 5; 888: 889: /* Check a `double' value for validity for a particular machine mode. 890: This is defined to avoid crashes outputting certain constants. */ 891: 1.1.1.3 root 892: #define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \ 893: if (OVERFLOW) \ 894: (D) = 3.4028234663852890e+38; \ 895: else if ((MODE) == SFmode) \ 1.1 root 896: { \ 897: if ((d) > 3.4028234663852890e+38) \ 1.1.1.3 root 898: (OVERFLOW) = 1, (D) = 3.4028234663852890e+38; \ 899: else if ((D) < -3.4028234663852890e+38) \ 900: (OVERFLOW) = 1, (D) = -3.4028234663852890e+38; \ 901: else if (((D) > 0) && ((D) < 1.1754943508222873e-38)) \ 902: (OVERFLOW) = 1, (D) = 0.0; \ 1.1 root 903: else if (((d) < 0) && ((d) > -1.1754943508222873e-38)) \ 1.1.1.4 ! root 904: (OVERFLOW) = 1, (D) = 0.0; \ 1.1 root 905: } 906: 907: /* Tell final.c how to eliminate redundant test instructions. */ 908: 909: /* Here we define machine-dependent flags and fields in cc_status 910: (see `conditions.h'). */ 911: 912: /* On the Alliant, floating-point instructions do not modify the 913: ordinary CC register. Only fcmp and ftest instructions modify the 914: floating-point CC register. We should actually keep track of what 915: both kinds of CC registers contain, but for now we only consider 916: the most recent instruction that has set either register. */ 917: 918: /* Set if the cc value came from a floating point test, so a floating 919: point conditional branch must be output. */ 920: #define CC_IN_FP 04000 921: 922: /* Store in cc_status the expressions 923: that the condition codes will describe 924: after execution of an instruction whose pattern is EXP. 925: Do not alter them if the instruction would not alter the cc's. */ 926: 927: /* On the 68000, all the insns to store in an address register 928: fail to set the cc's. However, in some cases these instructions 929: can make it possibly invalid to use the saved cc's. In those 930: cases we clear out some or all of the saved cc's so they won't be used. */ 931: 932: #define NOTICE_UPDATE_CC(EXP, INSN) \ 933: { \ 934: if (GET_CODE (EXP) == SET) \ 935: { if (ADDRESS_REG_P (SET_DEST (EXP)) || FP_REG_P (SET_DEST (EXP))) \ 936: { if (cc_status.value1 \ 937: && reg_overlap_mentioned_p (SET_DEST (EXP), cc_status.value1)) \ 938: cc_status.value1 = 0; \ 939: if (cc_status.value2 \ 940: && reg_overlap_mentioned_p (SET_DEST (EXP), cc_status.value2)) \ 941: cc_status.value2 = 0; } \ 942: else if (GET_CODE (SET_SRC (EXP)) == MOD \ 943: || GET_CODE (SET_SRC (EXP)) == UMOD \ 944: || (GET_CODE (SET_SRC (EXP)) == TRUNCATE \ 945: && (GET_CODE (XEXP (SET_SRC (EXP))) == MOD \ 946: || GET_CODE (XEXP (SET_SRC (EXP))) == UMOD))) \ 947: /* The swap insn produces cc's that don't correspond to the \ 948: result. */ \ 949: CC_STATUS_INIT; \ 950: else if (SET_DEST (EXP) != cc0_rtx \ 951: && (FP_REG_P (SET_SRC (EXP)) \ 952: || GET_CODE (SET_SRC (EXP)) == FIX \ 953: || GET_CODE (SET_SRC (EXP)) == FLOAT_TRUNCATE \ 954: || GET_CODE (SET_SRC (EXP)) == FLOAT_EXTEND)) \ 955: { CC_STATUS_INIT; } \ 956: /* A pair of move insns doesn't produce a useful overall cc. */ \ 957: else if (!FP_REG_P (SET_DEST (EXP)) \ 958: && !FP_REG_P (SET_SRC (EXP)) \ 959: && GET_MODE_SIZE (GET_MODE (SET_SRC (EXP))) > 4 \ 960: && (GET_CODE (SET_SRC (EXP)) == REG \ 961: || GET_CODE (SET_SRC (EXP)) == MEM \ 962: || GET_CODE (SET_SRC (EXP)) == CONST_DOUBLE))\ 963: { CC_STATUS_INIT; } \ 964: else if (GET_CODE (SET_SRC (EXP)) == CALL) \ 965: { CC_STATUS_INIT; } \ 966: else if (XEXP (EXP, 0) != pc_rtx) \ 967: { cc_status.flags = 0; \ 968: cc_status.value1 = XEXP (EXP, 0); \ 969: cc_status.value2 = XEXP (EXP, 1); } } \ 970: else if (GET_CODE (EXP) == PARALLEL \ 971: && GET_CODE (XVECEXP (EXP, 0, 0)) == SET) \ 972: { \ 973: if (ADDRESS_REG_P (XEXP (XVECEXP (EXP, 0, 0), 0))) \ 974: CC_STATUS_INIT; \ 975: else if (XEXP (XVECEXP (EXP, 0, 0), 0) != pc_rtx) \ 976: { cc_status.flags = 0; \ 977: cc_status.value1 = XEXP (XVECEXP (EXP, 0, 0), 0); \ 978: cc_status.value2 = XEXP (XVECEXP (EXP, 0, 0), 1); } } \ 979: else CC_STATUS_INIT; \ 980: if (cc_status.value2 != 0 \ 981: && ADDRESS_REG_P (cc_status.value2) \ 982: && GET_MODE (cc_status.value2) == QImode) \ 983: CC_STATUS_INIT; \ 984: if (cc_status.value2 != 0) \ 985: switch (GET_CODE (cc_status.value2)) \ 986: { case PLUS: case MINUS: case MULT: \ 987: case DIV: case UDIV: case MOD: case UMOD: case NEG: \ 1.1.1.3 root 988: case ASHIFT: case ASHIFTRT: case LSHIFTRT: \ 1.1 root 989: case ROTATE: case ROTATERT: \ 990: if (GET_MODE (cc_status.value2) != VOIDmode) \ 991: cc_status.flags |= CC_NO_OVERFLOW; \ 992: break; \ 993: case ZERO_EXTEND: \ 994: /* (SET r1 (ZERO_EXTEND r2)) on this machine 995: ends with a move insn moving r2 in r2's mode. 996: Thus, the cc's are set for r2. 997: This can set N bit spuriously. */ \ 998: cc_status.flags |= CC_NOT_NEGATIVE; } \ 999: if (cc_status.value1 && GET_CODE (cc_status.value1) == REG \ 1000: && cc_status.value2 \ 1001: && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) \ 1002: cc_status.value2 = 0; \ 1003: if ((cc_status.value1 && FP_REG_P (cc_status.value1)) \ 1004: || (cc_status.value2 && FP_REG_P (cc_status.value2))) \ 1005: cc_status.flags = CC_IN_FP; } 1006: 1007: #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ 1008: { if (cc_prev_status.flags & CC_IN_FP) \ 1009: return FLOAT; \ 1010: if (cc_prev_status.flags & CC_NO_OVERFLOW) \ 1011: return NO_OV; \ 1012: return NORMAL; } 1013: 1014: /* Control the assembler format that we output. */ 1015: 1016: /* Output at beginning of assembler file. */ 1017: 1018: #define ASM_FILE_START(FILE) \ 1019: fprintf (FILE, "#NO_APP\n"); 1020: 1021: /* Output to assembler file text saying following lines 1022: may contain character constants, extra white space, comments, etc. */ 1023: 1024: #define ASM_APP_ON "#APP\n" 1025: 1026: /* Output to assembler file text saying following lines 1027: no longer contain unusual constructs. */ 1028: 1029: #define ASM_APP_OFF "#NO_APP\n" 1030: 1031: /* Output before read-only data. */ 1032: 1033: #define TEXT_SECTION_ASM_OP ".text" 1034: 1035: /* Output before writable data. */ 1036: 1037: #define DATA_SECTION_ASM_OP ".data" 1038: 1039: /* How to refer to registers in assembler output. 1040: This sequence is indexed by compiler's hard-register-number (see above). */ 1041: 1042: #define REGISTER_NAMES \ 1043: {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ 1044: "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ 1045: "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" } 1046: 1047: /* How to renumber registers for dbx and gdb. 1048: On the Sun-3, the floating point registers have numbers 1049: 18 to 25, not 16 to 23 as they do in the compiler. */ 1050: /* (On the Alliant, dbx isn't working yet at all. */ 1051: 1052: #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2) 1053: 1054: /* This is how to output the definition of a user-level label named NAME, 1055: such as the label on a static function or variable NAME. */ 1056: 1057: #define ASM_OUTPUT_LABEL(FILE,NAME) \ 1058: do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) 1059: 1060: /* This is how to output a command to make the user-level label named NAME 1061: defined for reference from other files. */ 1062: 1063: #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ 1064: do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) 1065: 1066: /* This is how to output a reference to a user-level label named NAME. 1067: `assemble_name' uses this. */ 1068: 1069: #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 1070: fprintf (FILE, "_%s", NAME) 1071: 1072: /* This is how to output an internal numbered label where 1073: PREFIX is the class of label and NUM is the number within the class. */ 1074: 1075: #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ 1076: fprintf (FILE, "%s%d:\n", PREFIX, NUM) 1077: 1078: /* This is how to store into the string LABEL 1079: the symbol_ref name of an internal numbered label where 1080: PREFIX is the class of label and NUM is the number within the class. 1081: This is suitable for output with `assemble_name'. */ 1082: 1083: #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 1084: sprintf (LABEL, "*%s%d", PREFIX, NUM) 1085: 1086: /* This is how to output an assembler line defining a `double' constant. */ 1087: 1088: #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ 1089: do { union { double d; long v[2];} tem; \ 1090: tem.d = (VALUE); \ 1091: fprintf (FILE, "\t.long 0x%x,0x%x\n", tem.v[0], tem.v[1]); \ 1092: } while (0) 1093: 1094: /* This is how to output an assembler line defining a `float' constant. */ 1095: 1096: #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ 1097: do { union { float f; long l;} tem; \ 1098: tem.f = (VALUE); \ 1099: fprintf (FILE, "\t.long 0x%x\n", tem.l); \ 1100: } while (0) 1101: 1102: /* This is how to output an assembler line defining an `int' constant. */ 1103: 1104: #define ASM_OUTPUT_INT(FILE,VALUE) \ 1105: ( fprintf (FILE, "\t.long "), \ 1106: output_addr_const (FILE, (VALUE)), \ 1107: fprintf (FILE, "\n")) 1108: 1109: /* Likewise for `char' and `short' constants. */ 1110: 1111: #define ASM_OUTPUT_SHORT(FILE,VALUE) \ 1112: ( fprintf (FILE, "\t.word "), \ 1113: output_addr_const (FILE, (VALUE)), \ 1114: fprintf (FILE, "\n")) 1115: 1116: #define ASM_OUTPUT_CHAR(FILE,VALUE) \ 1117: ( fprintf (FILE, "\t.byte "), \ 1118: output_addr_const (FILE, (VALUE)), \ 1119: fprintf (FILE, "\n")) 1120: 1121: #define ASM_OUTPUT_ASCII(FILE,PTR,SIZE) \ 1.1.1.3 root 1122: do { int i; unsigned char *pp = (unsigned char *) (PTR); \ 1.1 root 1123: fprintf((FILE), "\t.byte %d", (unsigned int)*pp++); \ 1124: for (i = 1; i < (SIZE); ++i, ++pp) { \ 1125: if ((i % 8) == 0) \ 1126: fprintf((FILE), "\n\t.byte %d", (unsigned int) *pp); \ 1127: else \ 1128: fprintf((FILE), ",%d", (unsigned int) *pp); } \ 1.1.1.3 root 1129: fprintf ((FILE), "\n"); } while (0) 1.1 root 1130: 1131: /* This is how to output an assembler line for a numeric constant byte. */ 1132: 1133: #define ASM_OUTPUT_BYTE(FILE,VALUE) \ 1134: fprintf (FILE, "\t.byte 0x%x\n", (VALUE)) 1135: 1136: /* This is how to output an insn to push a register on the stack. 1137: It need not be very fast code. */ 1138: 1139: #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ 1140: fprintf (FILE, "\tmovl %s,sp@-\n", reg_names[REGNO]) 1141: 1142: /* This is how to output an insn to pop a register from the stack. 1143: It need not be very fast code. */ 1144: 1145: #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ 1146: fprintf (FILE, "\tmovl sp@+,%s\n", reg_names[REGNO]) 1147: 1148: /* This is how to output an element of a case-vector that is absolute. 1149: (The 68000 does not use such vectors, 1150: but we must define this macro anyway.) */ 1151: 1152: #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1153: fprintf (FILE, "\t.long L%d\n", VALUE) 1154: 1155: /* This is how to output an element of a case-vector that is relative. */ 1156: 1157: #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ 1158: fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL) 1159: 1160: /* This is how to output an assembler line 1161: that says to advance the location counter 1162: to a multiple of 2**LOG bytes. */ 1163: 1164: #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1165: if ((LOG) == 1) \ 1166: fprintf (FILE, "\t.even\n"); \ 1167: else if ((LOG) != 0) \ 1168: fprintf (FILE, "\t.align %dn", (LOG)); 1169: 1170: #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1171: fprintf (FILE, "\t. = . + %u\n", (SIZE)) 1172: 1173: /* This says how to output an assembler line 1174: to define a global common symbol. */ 1175: 1176: #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1177: ( fputs ("\t.comm ", (FILE)), \ 1178: assemble_name ((FILE), (NAME)), \ 1179: fprintf ((FILE), ",%u\n", (ROUNDED))) 1180: 1181: /* This says how to output an assembler line 1182: to define a local common symbol. */ 1183: 1184: #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 1185: ( fputs ("\t.lcomm ", (FILE)), \ 1186: assemble_name ((FILE), (NAME)), \ 1187: fprintf ((FILE), ",%u\n", (ROUNDED))) 1188: 1189: /* Store in OUTPUT a string (made with alloca) containing 1190: an assembler-name for a local static variable named NAME. 1191: LABELNO is an integer which is different for each call. */ 1192: 1193: #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ 1194: ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ 1195: sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) 1196: 1197: /* Define the parentheses used to group arithmetic operations 1198: in assembler code. */ 1199: 1200: #define ASM_OPEN_PAREN "(" 1201: #define ASM_CLOSE_PAREN ")" 1202: 1203: /* Define results of standard character escape sequences. */ 1204: #define TARGET_BELL 007 1205: #define TARGET_BS 010 1206: #define TARGET_TAB 011 1207: #define TARGET_NEWLINE 012 1208: #define TARGET_VT 013 1209: #define TARGET_FF 014 1210: #define TARGET_CR 015 1211: 1212: /* Print operand X (an rtx) in assembler syntax to file FILE. 1213: CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 1214: For `%' followed by punctuation, CODE is the punctuation and X is null. 1215: 1216: On the Alliant, we use several CODE characters: 1217: '.' for dot needed in Motorola-style opcode names. 1218: '-' for an operand pushing on the stack: 1219: sp@-, -(sp) or -(%sp) depending on the style of syntax. 1220: '+' for an operand pushing on the stack: 1221: sp@+, (sp)+ or (%sp)+ depending on the style of syntax. 1222: '@' for a reference to the top word on the stack: 1223: sp@, (sp) or (%sp) depending on the style of syntax. 1224: '#' for an immediate operand prefix (# in MIT and Motorola syntax 1225: but & in SGS syntax). 1226: '!' for the cc register (used in an `and to cc' insn). 1227: 1228: 'b' for byte insn (no effect, on the Sun; this is for the ISI). 1229: 'd' to force memory addressing to be absolute, not relative. 1230: 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) 1231: 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), 1232: or print pair of registers as rx:ry. */ 1233: 1234: #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 1235: ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \ 1236: || (CODE) == '+' || (CODE) == '@' || (CODE) == '!') 1237: 1238: #define PRINT_OPERAND(FILE, X, CODE) \ 1239: { int i; \ 1240: if (CODE == '.') ; \ 1241: else if (CODE == '#') fprintf (FILE, "#"); \ 1242: else if (CODE == '-') fprintf (FILE, "sp@-"); \ 1243: else if (CODE == '+') fprintf (FILE, "sp@+"); \ 1244: else if (CODE == '@') fprintf (FILE, "sp@"); \ 1245: else if (CODE == '!') fprintf (FILE, "cc"); \ 1246: else if ((X) == 0 ) ; \ 1247: else if (GET_CODE (X) == REG) \ 1248: { if (REGNO (X) < 16 && (CODE == 'y' || CODE == 'x') && GET_MODE (X) == DFmode) \ 1249: fprintf (FILE, "%s,%s", reg_names[REGNO (X)], reg_names[REGNO (X)+1]); \ 1250: else \ 1251: fprintf (FILE, "%s", reg_names[REGNO (X)]); \ 1252: } \ 1253: else if (GET_CODE (X) == MEM) \ 1254: { \ 1255: output_address (XEXP (X, 0)); \ 1256: if (CODE == 'd' && ! TARGET_68020 \ 1257: && CONSTANT_ADDRESS_P (XEXP (X, 0)) \ 1258: && !(GET_CODE (XEXP (X, 0)) == CONST_INT \ 1259: && INTVAL (XEXP (X, 0)) < 0x8000 \ 1260: && INTVAL (XEXP (X, 0)) >= -0x8000)) \ 1261: fprintf (FILE, ":l"); \ 1262: } \ 1263: else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode) \ 1264: { union { double d; int i[2]; } u; \ 1265: union { float f; int i; } u1; \ 1266: u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \ 1267: u1.f = u.d; \ 1268: if (CODE == 'f') \ 1269: fprintf (FILE, "#0r%.9g", u1.f); \ 1270: else \ 1271: fprintf (FILE, "#0x%x", u1.i); } \ 1.1.1.3 root 1272: else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode) \ 1.1 root 1273: { union { double d; int i[2]; } u; \ 1274: u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \ 1275: fprintf (FILE, "#0r%.20g", u.d); } \ 1276: else { putc ('#', FILE); output_addr_const (FILE, X); }} 1277: 1278: /* Note that this contains a kludge that knows that the only reason 1279: we have an address (plus (label_ref...) (reg...)) 1280: is in the insn before a tablejump, and we know that m68k.md 1281: generates a label LInnn: on such an insn. */ 1282: #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 1283: { register rtx reg1, reg2, breg, ireg; \ 1284: register rtx addr = ADDR; \ 1285: static char *sz = ".BW.L...D"; \ 1286: rtx offset; \ 1287: switch (GET_CODE (addr)) \ 1288: { \ 1289: case REG: \ 1290: fprintf (FILE, "%s@", reg_names[REGNO (addr)]); \ 1291: break; \ 1292: case PRE_DEC: \ 1293: fprintf (FILE, "%s@-", reg_names[REGNO (XEXP (addr, 0))]); \ 1294: break; \ 1295: case POST_INC: \ 1296: fprintf (FILE, "%s@+", reg_names[REGNO (XEXP (addr, 0))]); \ 1297: break; \ 1298: case PLUS: \ 1299: reg1 = 0; reg2 = 0; \ 1300: ireg = 0; breg = 0; \ 1301: offset = 0; \ 1302: if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) \ 1303: { \ 1304: offset = XEXP (addr, 0); \ 1305: addr = XEXP (addr, 1); \ 1306: } \ 1307: else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) \ 1308: { \ 1309: offset = XEXP (addr, 1); \ 1310: addr = XEXP (addr, 0); \ 1311: } \ 1312: if (GET_CODE (addr) != PLUS) ; \ 1313: else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND) \ 1314: { \ 1315: reg1 = XEXP (addr, 0); \ 1316: addr = XEXP (addr, 1); \ 1317: } \ 1318: else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND) \ 1319: { \ 1320: reg1 = XEXP (addr, 1); \ 1321: addr = XEXP (addr, 0); \ 1322: } \ 1323: else if (GET_CODE (XEXP (addr, 0)) == MULT) \ 1324: { \ 1325: reg1 = XEXP (addr, 0); \ 1326: addr = XEXP (addr, 1); \ 1327: } \ 1328: else if (GET_CODE (XEXP (addr, 1)) == MULT) \ 1329: { \ 1330: reg1 = XEXP (addr, 1); \ 1331: addr = XEXP (addr, 0); \ 1332: } \ 1333: else if (GET_CODE (XEXP (addr, 0)) == REG) \ 1334: { \ 1335: reg1 = XEXP (addr, 0); \ 1336: addr = XEXP (addr, 1); \ 1337: } \ 1338: else if (GET_CODE (XEXP (addr, 1)) == REG) \ 1339: { \ 1340: reg1 = XEXP (addr, 1); \ 1341: addr = XEXP (addr, 0); \ 1342: } \ 1343: if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT \ 1344: || GET_CODE (addr) == SIGN_EXTEND) \ 1345: { if (reg1 == 0) reg1 = addr; else reg2 = addr; addr = 0; } \ 1346: /* for OLD_INDEXING \ 1347: else if (GET_CODE (addr) == PLUS) \ 1348: { \ 1349: if (GET_CODE (XEXP (addr, 0)) == REG) \ 1350: { \ 1351: reg2 = XEXP (addr, 0); \ 1352: addr = XEXP (addr, 1); \ 1353: } \ 1354: else if (GET_CODE (XEXP (addr, 1)) == REG) \ 1355: { \ 1356: reg2 = XEXP (addr, 1); \ 1357: addr = XEXP (addr, 0); \ 1358: } \ 1359: } \ 1360: */ \ 1361: if (offset != 0) { if (addr != 0) abort (); addr = offset; } \ 1362: if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND \ 1363: || GET_CODE (reg1) == MULT)) \ 1364: || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) \ 1365: { breg = reg2; ireg = reg1; } \ 1366: else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) \ 1367: { breg = reg1; ireg = reg2; } \ 1368: if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF) \ 1369: { int scale = 1; \ 1370: if (GET_CODE (ireg) == MULT) \ 1371: { scale = INTVAL (XEXP (ireg, 1)); \ 1372: ireg = XEXP (ireg, 0); } \ 1373: if (GET_CODE (ireg) == SIGN_EXTEND) \ 1374: fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:W", \ 1375: CODE_LABEL_NUMBER (XEXP (addr, 0)), \ 1376: CODE_LABEL_NUMBER (XEXP (addr, 0)), \ 1377: reg_names[REGNO (XEXP (ireg, 0))]); \ 1378: else \ 1379: fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L", \ 1380: CODE_LABEL_NUMBER (XEXP (addr, 0)), \ 1381: CODE_LABEL_NUMBER (XEXP (addr, 0)), \ 1382: reg_names[REGNO (ireg)]); \ 1383: fprintf (FILE, ":%c", sz[scale]); \ 1384: putc (']', FILE); \ 1385: break; } \ 1386: if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF) \ 1387: { fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L:B]", \ 1388: CODE_LABEL_NUMBER (XEXP (addr, 0)), \ 1389: CODE_LABEL_NUMBER (XEXP (addr, 0)), \ 1390: reg_names[REGNO (breg)]); \ 1391: break; } \ 1392: if (ireg != 0 || breg != 0) \ 1393: { int scale = 1; \ 1394: if (breg == 0) \ 1395: abort (); \ 1396: if (addr && GET_CODE (addr) == LABEL_REF) abort (); \ 1397: fprintf (FILE, "%s@", reg_names[REGNO (breg)]); \ 1398: if (addr != 0) { \ 1399: putc( '(', FILE ); \ 1400: output_addr_const (FILE, addr); \ 1401: if (ireg != 0) { \ 1402: if (GET_CODE(addr) == CONST_INT) { \ 1403: int size_of = 1, val = INTVAL(addr); \ 1404: if (val < -0x8000 || val >= 0x8000) \ 1405: size_of = 4; \ 1406: else if (val < -0x80 || val >= 0x80) \ 1407: size_of = 2; \ 1408: fprintf(FILE, ":%c", sz[size_of]); \ 1409: } \ 1410: else \ 1411: fprintf(FILE, ":L"); } \ 1412: putc( ')', FILE ); } \ 1413: if (ireg != 0) { \ 1414: putc ('[', FILE); \ 1415: if (ireg != 0 && GET_CODE (ireg) == MULT) \ 1416: { scale = INTVAL (XEXP (ireg, 1)); \ 1417: ireg = XEXP (ireg, 0); } \ 1418: if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND) \ 1419: fprintf (FILE, "%s:W", reg_names[REGNO (XEXP (ireg, 0))]); \ 1420: else if (ireg != 0) \ 1421: fprintf (FILE, "%s:L", reg_names[REGNO (ireg)]); \ 1422: fprintf (FILE, ":%c", sz[scale]); \ 1423: putc (']', FILE); \ 1424: } \ 1425: break; \ 1426: } \ 1427: else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF) \ 1428: { fprintf (FILE, "pc@(L%d-LI%d-2:B)[%s:L:B]", \ 1429: CODE_LABEL_NUMBER (XEXP (addr, 0)), \ 1430: CODE_LABEL_NUMBER (XEXP (addr, 0)), \ 1431: reg_names[REGNO (reg1)]); \ 1432: break; } \ 1433: default: \ 1434: if (GET_CODE (addr) == CONST_INT \ 1435: && INTVAL (addr) < 0x8000 \ 1436: && INTVAL (addr) >= -0x8000) \ 1437: fprintf (FILE, "%d:W", INTVAL (addr)); \ 1438: else \ 1439: output_addr_const (FILE, addr); \ 1440: }} 1441: 1442: /* 1443: Local variables: 1444: version-control: t 1445: End: 1446: */ 1447:
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