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1.1 root 1: /* Definitions of target machine for GNU compiler. Gmicro (TRON) version.
2: Ported by Masanobu Yuhara, Fujitsu Laboratories LTD.
3: ([email protected])
4:
5: Copyright (C) 1987, 1988, 1989 Free Software Foundation, Inc.
6:
7: This file is part of GNU CC.
8:
9: GNU CC is free software; you can redistribute it and/or modify
10: it under the terms of the GNU General Public License as published by
11: the Free Software Foundation; either version 2, or (at your option)
12: any later version.
13:
14: GNU CC is distributed in the hope that it will be useful,
15: but WITHOUT ANY WARRANTY; without even the implied warranty of
16: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17: GNU General Public License for more details.
18:
19: Among other things, the copyright
20: notice and this notice must be preserved on all copies.
21:
22: You should have received a copy of the GNU General Public License
23: along with GNU CC; see the file COPYING. If not, write to
24: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25: */
26:
27:
28: /* Note that some other tm.h files include this one and then override
29: many of the definitions that relate to assembler syntax. */
30:
31:
32: /* Names to predefine in the preprocessor for this target machine. */
33:
34: #define CPP_PREDEFINES "-Dgmicro"
35:
36: /* #define CPP_SPEC ** currently not defined **/
37:
38: /* #define CC1_SPEC ** currently not defined **/
39:
40:
41: /* Print subsidiary information on the compiler version in use. */
42: /*
43: #define TARGET_VERSION fprintf (stderr, " (Gmicro syntax)");
44: */
45:
46: /* Run-time compilation parameters selecting different hardware subsets. */
47:
48: extern int target_flags;
49:
50: /* Macros used in the machine description to test the flags. */
51:
52: /* Compile for a Gmicro/300. */
53: #define TARGET_G300 (target_flags & 1)
54: /* Compile for a Gmicro/200. */
55: #define TARGET_G200 (target_flags & 2)
56: /* Compile for a Gmicro/100. */
57: #define TARGET_G100 (target_flags & 4)
58:
59: /* Compile FPU insns for floating point (not library calls). */
60: #define TARGET_FPU (target_flags & 8)
61:
62: /* Pop up arguments by called function. */
63: #define TARGET_RTD (target_flags & 0x10)
64:
65: /* Compile passing first args in regs 0 and 1.
66: This exists only to test compiler features that will be needed for
67: RISC chips. It is not usable and is not intended to be usable on
68: this cpu ;-< */
69: #define TARGET_REGPARM (target_flags & 0x20)
70:
71: #define TARGET_BITFIELD (target_flags & 0x40)
72:
73: #define TARGET_NEWRETURN (target_flags & 0x80)
74:
75: /* Do not expand __builtin_smov (strcpy) to multiple movs.
76: Use the smov instruction. */
77: #define TARGET_FORCE_SMOV (target_flags & 0x100)
78:
79: /* default options are -m300, -mFPU,
80: with bitfield instructions added because it won't always work otherwise.
81: If there are versions of the gmicro that don't support bitfield instructions
82: then it will take some thinking to figure out how to make them work. */
83: #define TARGET_DEFAULT 0x49
84:
85: /* Macro to define tables used to set the flags.
86: This is a list in braces of pairs in braces,
87: each pair being { "NAME", VALUE }
88: where VALUE is the bits to set or minus the bits to clear.
89: An empty string NAME is used to identify the default VALUE. */
90:
91: #define TARGET_SWITCHES \
92: { { "g300", 1}, \
93: { "g200", 2}, \
94: { "g100", 4}, \
95: { "fpu", 8}, \
96: { "soft-float", -8}, \
97: { "rtd", 0x10}, \
98: { "no-rtd", -0x10}, \
99: { "regparm", 0x20}, \
100: { "no-regparm", -0x20}, \
101: #if 0 /* Since we don't define PCC_BITFIELD_TYPE_MATTERS or use a large
102: STRUCTURE_SIZE_BOUNDARY, we must have bitfield instructions. */
103: { "bitfield", 0x40}, \
104: { "no-bitfield", -0x40}, \
105: #endif
106: { "newreturn", 0x80}, \
107: { "no-newreturn", -0x80}, \
108: { "force-smov", 0x100}, \
109: { "no-force-smov", -0x100}, \
110: { "", TARGET_DEFAULT}}
111:
112:
113: /* Blow away G100 flag silently off TARGET_fpu (since we can't clear
114: any bits in TARGET_SWITCHES above) */
115: #define OVERRIDE_OPTIONS \
116: { \
117: if (TARGET_G100) target_flags &= ~8; \
118: }
119:
120: /* target machine storage layout */
121:
122: /* Define this if most significant bit is lowest numbered
123: in instructions that operate on numbered bit-fields.
124: This is true for Gmicro insns.
125: We make it true always by avoiding using the single-bit insns
126: except in special cases with constant bit numbers. */
127: #define BITS_BIG_ENDIAN 1
128:
129: /* Define this if most significant byte of a word is the lowest numbered. */
130: /* That is true on the Gmicro. */
131: #define BYTES_BIG_ENDIAN 1
132:
133: /* Define this if most significant word of a multiword number is the lowest
134: numbered. */
135: /* For Gmicro we can decide arbitrarily
136: since there are no machine instructions for them. ????? */
137: #define WORDS_BIG_ENDIAN 0
138:
139: /* number of bits in an addressible storage unit */
140: #define BITS_PER_UNIT 8
141:
142: /* Width in bits of a "word", which is the contents of a machine register. */
143: #define BITS_PER_WORD 32
144:
145: /* Width of a word, in units (bytes). */
146: #define UNITS_PER_WORD 4
147:
148: /* Width in bits of a pointer.
149: See also the macro `Pmode' defined below. */
150: #define POINTER_SIZE 32
151:
152: /* Allocation boundary (in *bits*) for storing arguments in argument list. */
153: #define PARM_BOUNDARY 32
154:
155: /* Boundary (in *bits*) on which stack pointer should be aligned. */
156: #define STACK_BOUNDARY 32
157:
158: /* Allocation boundary (in *bits*) for the code of a function. */
159: /* Instructions of the Gmicro should be on half-word boundary */
160: /* But word boundary gets better performance */
161: #define FUNCTION_BOUNDARY 32
162:
163: /* Alignment of field after `int : 0' in a structure. */
164: #define EMPTY_FIELD_BOUNDARY 32
165:
166: /* No data type wants to be aligned rounder than this. */
167: /* This is not necessarily 32 on the Gmicro */
168: #define BIGGEST_ALIGNMENT 32
169:
170: /* Define this if move instructions will actually fail to work
171: when given unaligned data. */
172: /* Unaligned data is allowed on Gmicro, though the access is slow. */
173: /* But now STRICT is defined */
174: #define STRICT_ALIGNMENT
175:
176: /* Make strings word-aligned so strcpy from constants will be faster. */
177: #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
178: (TREE_CODE (EXP) == STRING_CST \
179: && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
180:
181: /* Make arrays of chars word-aligned for the same reasons. */
182: #define DATA_ALIGNMENT(TYPE, ALIGN) \
183: (TREE_CODE (TYPE) == ARRAY_TYPE \
184: && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
185: && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
186:
187: /* Define number of bits in most basic integer type.
188: (If undefined, default is BITS_PER_WORD). */
189: #define INT_TYPE_SIZE 32
190:
191: /* #define PCC_BITFIELD_TYPE_MATTERS 1 ????? */
192:
193: /* #define CHECK_FLOAT_VALUE (MODE, VALUE) ????? */
194:
195:
196: /* Standard register usage. */
197:
198: /* Number of actual hardware registers.
199: The hardware registers are assigned numbers for the compiler
200: from 0 to just below FIRST_PSEUDO_REGISTER.
201: All registers that the compiler knows about must be given numbers,
202: even those that are not normally considered general registers.
203: For the Gmicro, we give the general registers numbers 0-15,
204: and the FPU floating point registers numbers 16-31. */
205: #define FIRST_PSEUDO_REGISTER 32
206:
207: /* 1 for registers that have pervasive standard uses
208: and are not available for the register allocator.
209: On the Gmicro, the stack pointer and the frame pointer are
210: such registers. */
211: /* frame pointer is not indicated as fixed, because fp may be used freely
212: when a frame is not built. */
213: #define FIXED_REGISTERS \
214: {0, 0, 0, 0, 0, 0, 0, 0, \
215: 0, 0, 0, 0, 0, 0, 0, 1, \
216: /* FPU registers. */ \
217: 0, 0, 0, 0, 0, 0, 0, 0, \
218: 0, 0, 0, 0, 0, 0, 0, 0, }
219:
220: /* 1 for registers not available across function calls.
221: These must include the FIXED_REGISTERS and also any
222: registers that can be used without being saved.
223: The latter must include the registers where values are returned
224: and the register where structure-value addresses are passed.
225: Aside from that, you can include as many other registers as you like. */
226: #define CALL_USED_REGISTERS \
227: {1, 1, 1, 1, 0, 0, 0, 0, \
228: 0, 0, 0, 0, 0, 0, 0, 1, \
229: /* FPU registers. */ \
230: 1, 1, 1, 1, 0, 0, 0, 0, \
231: 0, 0, 0, 0, 0, 0, 0, 0, }
232:
233:
234: /* Make sure everything's fine if we *don't* have a given processor.
235: This assumes that putting a register in fixed_regs will keep the
236: compilers mitt's completely off it. We don't bother to zero it out
237: of register classes. If TARGET_FPU is not set,
238: the compiler won't touch since no instructions that use these
239: registers will be valid. */
240: /* This Macro is not defined now.
241: #define CONDITIONAL_REGISTER_USAGE */
242:
243: /* The Gmicro has no overlapping register */
244: /* #define OVERLAPPING_REGNO_P(REGNO) */
245:
246: /* #define INSN_CLOBBERS_REGNO_P(INSN,REGNO) */
247: /* #define PRESERVE_DEATH_INFO_REGNO_P(REGNO) */
248:
249: /* Return number of consecutive hard regs needed starting at reg REGNO
250: to hold something of mode MODE.
251: This is ordinarily the length in words of a value of mode MODE
252: but can be less for certain modes in special long registers.
253:
254: On the Gmicro, ordinary registers hold 32 bits worth;
255: for the Gmicro/FPU registers, a single register is always enough for
256: anything that can be stored in them at all. */
257: #define HARD_REGNO_NREGS(REGNO, MODE) \
258: ((REGNO) >= 16 ? 1 \
259: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
260:
261: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
262: On the Gmicro, the cpu registers can hold any mode but the FPU registers
263: can hold only SFmode or DFmode. And the FPU registers can't hold anything
264: if FPU use is disabled. */
265: #define HARD_REGNO_MODE_OK(REGNO, MODE) \
266: ((REGNO) < 16 \
267: || ((REGNO) < 32 \
268: ? TARGET_FPU && (GET_MODE_CLASS (MODE) == MODE_FLOAT || \
269: GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
270: : 0 ))
271:
272: /* Value is 1 if it is a good idea to tie two pseudo registers
273: when one has mode MODE1 and one has mode MODE2.
274: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
275: for any hard reg, then this must be 0 for correct output. */
276: #define MODES_TIEABLE_P(MODE1, MODE2) \
277: (! TARGET_FPU \
278: || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
279: GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
280: == ((MODE2) == SFmode || (MODE2) == DFmode)))
281:
282: /* Specify the registers used for certain standard purposes.
283: The values of these macros are register numbers. */
284:
285: /* Gmicro pc isn't overloaded on a register. */
286: /* #define PC_REGNUM */
287:
288: /* Register to use for pushing function arguments. */
289: #define STACK_POINTER_REGNUM 15
290:
291: /* Base register for access to local variables of the function. */
292: #define FRAME_POINTER_REGNUM 14
293:
294: /* Value should be nonzero if functions must have frame pointers.
295: Zero means the frame pointer need not be set up (and parms
296: may be accessed via the stack pointer) in functions that seem suitable.
297: This is computed in `reload', in reload1.c. */
298: #define FRAME_POINTER_REQUIRED 0
299:
300: /* Base register for access to arguments of the function. */
301: /* The Gmicro does not have hardware ap. Fp is treated as ap */
302: #define ARG_POINTER_REGNUM 14
303:
304: /* Register in which static-chain is passed to a function. */
305: #define STATIC_CHAIN_REGNUM 0
306:
307: /* Register in which address to store a structure value
308: is passed to a function. */
309: #define STRUCT_VALUE_REGNUM 1
310:
311: /* Define the classes of registers for register constraints in the
312: machine description. Also define ranges of constants.
313:
314: One of the classes must always be named ALL_REGS and include all hard regs.
315: If there is more than one class, another class must be named NO_REGS
316: and contain no registers.
317:
318: The name GENERAL_REGS must be the name of a class (or an alias for
319: another name such as ALL_REGS). This is the class of registers
320: that is allowed by "g" or "r" in a register constraint.
321: Also, registers outside this class are allocated only when
322: instructions express preferences for them.
323:
324: The classes must be numbered in nondecreasing order; that is,
325: a larger-numbered class must never be contained completely
326: in a smaller-numbered class.
327:
328: For any two classes, it is very desirable that there be another
329: class that represents their union. */
330:
331: /* The Gmicro has two kinds of registers, so four classes would be
332: a complete set. */
333:
334: enum reg_class { NO_REGS, FPU_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES };
335:
336: #define N_REG_CLASSES (int) LIM_REG_CLASSES
337:
338: /* Give names of register classes as strings for dump file. */
339:
340: #define REG_CLASS_NAMES \
341: { "NO_REGS", "FPU_REGS", "GENERAL_REGS", "ALL_REGS" }
342:
343: /* Define which registers fit in which classes.
344: This is an initializer for a vector of HARD_REG_SET
345: of length N_REG_CLASSES. */
346:
347: #define REG_CLASS_CONTENTS \
348: { \
349: 0, /* NO_REGS */ \
350: 0xffff0000, /* FPU_REGS */ \
351: 0x0000ffff, /* GENERAL_REGS */ \
352: 0xffffffff /* ALL_REGS */ \
353: }
354:
355: /* The same information, inverted:
356: Return the class number of the smallest class containing
357: reg number REGNO. This could be a conditional expression
358: or could index an array. */
359:
360: extern enum reg_class regno_reg_class[];
361: #define REGNO_REG_CLASS(REGNO) ( (REGNO < 16) ? GENERAL_REGS : FPU_REGS )
362:
363: /* The class value for index registers, and the one for base regs. */
364:
365: #define INDEX_REG_CLASS GENERAL_REGS
366: #define BASE_REG_CLASS GENERAL_REGS
367:
368: /* Get reg_class from a letter such as appears in the machine description.
369: We do a trick here to modify the effective constraints on the
370: machine description; we zorch the constraint letters that aren't
371: appropriate for a specific target. This allows us to guarantee
372: that a specific kind of register will not be used for a given taget
373: without fiddling with the register classes above. */
374:
375: #define REG_CLASS_FROM_LETTER(C) \
376: ((C) == 'r' ? GENERAL_REGS : \
377: ((C) == 'f' ? (TARGET_FPU ? FPU_REGS : NO_REGS) : \
378: NO_REGS))
379:
380: /* The letters I, J, K, L and M in a register constraint string
381: can be used to stand for particular ranges of immediate operands.
382: This macro defines what the ranges are.
383: C is the letter, and VALUE is a constant value.
384: Return 1 if VALUE is in the range specified by C.
385:
386: For the Gmicro, all immediate value optimizations are done
387: by assember, so no machine dependent definition is necessary ??? */
388:
389: /* #define CONST_OK_FOR_LETTER_P(VALUE, C) ((C) == 'I') */
390: #define CONST_OK_FOR_LETTER_P(VALUE, C) 0
391:
392: /*
393: * The letters G defines all of the floating constants tha are *NOT*
394: * Gmicro-FPU constant.
395: */
396:
397: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
398: ((C) == 'F' || \
399: (C) == 'G' && !(TARGET_FPU && standard_fpu_constant_p (VALUE)))
400:
401: /* Given an rtx X being reloaded into a reg required to be
402: in class CLASS, return the class of reg to actually use.
403: In general this is just CLASS; but on some machines
404: in some cases it is preferable to use a more restrictive class. */
405: /* On the Gmicro series, there is no restricton on GENERAL_REGS,
406: so CLASS is returned. I do not know whether I should treat FPU_REGS
407: specially or not (at least, m68k does not). */
408:
409: #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
410:
411: /* Return the maximum number of consecutive registers
412: needed to represent mode MODE in a register of class CLASS. */
413: /* On the Gmicro, this is the size of MODE in words,
414: except in the FPU regs, where a single reg is always enough. */
415: #define CLASS_MAX_NREGS(CLASS, MODE) \
416: ((CLASS) == FPU_REGS ? \
417: 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
418:
419: /* Stack layout; function entry, exit and calling. */
420:
421: /* Define this if pushing a word on the stack
422: makes the stack pointer a smaller address. */
423: #define STACK_GROWS_DOWNWARD
424:
425: /* Define this if the nominal address of the stack frame
426: is at the high-address end of the local variables;
427: that is, each additional local variable allocated
428: goes at a more negative offset in the frame. */
429: #define FRAME_GROWS_DOWNWARD
430:
431: /* Offset within stack frame to start allocating local variables at.
432: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
433: first local allocated. Otherwise, it is the offset to the BEGINNING
434: of the first local allocated. */
435: /* On the Gmicro, FP points to the old FP and the first local variables are
436: at (FP - 4). */
437: #define STARTING_FRAME_OFFSET 0
438:
439: /* If we generate an insn to push BYTES bytes,
440: this says how many the stack pointer really advances by. */
441: /* On the Gmicro, sp is decrimented by the exact size of the operand */
442: #define PUSH_ROUNDING(BYTES) (BYTES)
443:
444: /* Offset of first parameter from the argument pointer register value. */
445: /* On the Gmicro, the first argument is found at (ap + 8) where ap is fp. */
446: #define FIRST_PARM_OFFSET(FNDECL) 8
447:
448: /* Value is the number of byte of arguments automatically
449: popped when returning from a subroutine call.
450: FUNTYPE is the data type of the function (as a tree),
451: or for a library call it is an identifier node for the subroutine name.
452: SIZE is the number of bytes of arguments passed on the stack.
453:
454: On the Gmicro, the EXITD insn may be used to pop them if the number
455: of args is fixed, but if the number is variable then the caller must pop
456: them all. The adjsp operand of the EXITD insn can't be used for library
457: calls now because the library is compiled with the standard compiler.
458: Use of adjsp operand is a selectable option, since it is incompatible with
459: standard Unix calling sequences. If the option is not selected,
460: the caller must always pop the args.
461: On the m68k this is an RTD option, so I use the same name
462: for the Gmicro. The option name may be changed in the future. */
463:
464: #define RETURN_POPS_ARGS(FUNTYPE,SIZE) \
465: ((TARGET_RTD && TREE_CODE (FUNTYPE) != IDENTIFIER_NODE \
466: && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
467: || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
468: = void_type_node))) \
469: ? (SIZE) : 0)
470:
471: /* Define how to find the value returned by a function.
472: VALTYPE is the data type of the value (as a tree).
473: If the precise function being called is known, FUNC is its FUNCTION_DECL;
474: otherwise, FUNC is 0. */
475:
476: /* On the Gmicro the floating return value is in fr0 not r0. */
477:
478: #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
479:
480: /* Define how to find the value returned by a library function
481: assuming the value has mode MODE. */
482:
483: #define LIBCALL_VALUE(MODE) \
484: (gen_rtx (REG, (MODE), \
485: ((TARGET_FPU && ((MODE) == SFmode || (MODE) == DFmode)) ? 16 : 0)))
486:
487:
488: /* 1 if N is a possible register number for a function value.
489: On the Gmicro, r0 and fp0 are the possible registers. */
490:
491: #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N) == 16)
492:
493: /* Define this if PCC uses the nonreentrant convention for returning
494: structure and union values. */
495:
496: #define PCC_STATIC_STRUCT_RETURN
497:
498: /* 1 if N is a possible register number for function argument passing.
499: On the Gmicro, no registers are used in this way. */
500: /* Really? For the performance improvement, registers should be used !! */
501:
502: #define FUNCTION_ARG_REGNO_P(N) 0
503:
504: /* Define a data type for recording info about an argument list
505: during the scan of that argument list. This data type should
506: hold all necessary information about the function itself
507: and about the args processed so far, enough to enable macros
508: such as FUNCTION_ARG to determine where the next arg should go.
509:
510: On the Gmicro, this is a single integer, which is a number of bytes
511: of arguments scanned so far. */
512:
513: #define CUMULATIVE_ARGS int
514:
515: /* Initialize a variable CUM of type CUMULATIVE_ARGS
516: for a call to a function whose data type is FNTYPE.
517: For a library call, FNTYPE is 0.
518:
519: On the Gmicro, the offset starts at 0. */
520:
521: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \
522: ((CUM) = 0)
523:
524: /* Update the data in CUM to advance over an argument
525: of mode MODE and data type TYPE.
526: (TYPE is null for libcalls where that information may not be available.) */
527:
528: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
529: ((CUM) += ((MODE) != BLKmode \
530: ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
531: : (int_size_in_bytes (TYPE) + 3) & ~3))
532:
533: /* Define where to put the arguments to a function.
534: Value is zero to push the argument on the stack,
535: or a hard register in which to store the argument.
536:
537: MODE is the argument's machine mode.
538: TYPE is the data type of the argument (as a tree).
539: This is null for libcalls where that information may
540: not be available.
541: CUM is a variable of type CUMULATIVE_ARGS which gives info about
542: the preceding args and about the function being called.
543: NAMED is nonzero if this argument is a named parameter
544: (otherwise it is an extra parameter matching an ellipsis). */
545:
546: /* On the Gmicro all args are pushed, except if -mregparm is specified
547: then the first two words of arguments are passed in d0, d1.
548: *NOTE* -mregparm does not work.
549: It exists only to test register calling conventions. */
550:
551: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
552: ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx (REG, (MODE), (CUM) / 4) : 0)
553:
554: /* For an arg passed partly in registers and partly in memory,
555: this is the number of registers used.
556: For args passed entirely in registers or entirely in memory, zero. */
557:
558: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
559: ((TARGET_REGPARM && (CUM) < 8 \
560: && 8 < ((CUM) + ((MODE) == BLKmode \
561: ? int_size_in_bytes (TYPE) \
562: : GET_MODE_SIZE (MODE)))) \
563: ? 2 - (CUM) / 4 : 0)
564:
565: /* The following macro is defined to output register list.
566: The LSB of Mask is the lowest number register.
567: Regoff is MY_GREG_OFF or MY_FREG_OFF.
568: Do NOT use <i> in File, Mask, Regoff !!
569: Should be changed from macros to functions. M.Yuhara */
570:
571: #define MY_GREG_OFF 0
572: #define MY_FREG_OFF 16
573:
574: #define MY_PRINT_MASK(File, Mask, Regoff) \
575: { \
576: int i, first = -1; \
577: if ((Mask) == 0) { \
578: fprintf(File, "#0"); \
579: } else { \
580: fprintf(File, "("); \
581: for (i = 0; i < 16; i++) { \
582: if ( (Mask) & (1 << i) ) { \
583: if (first < 0) { \
584: if (first == -2) { \
585: fprintf(File, ","); \
586: } \
587: first = i; \
588: fprintf(File, "%s", reg_names[Regoff + i]); \
589: } \
590: } else if (first >= 0) { \
591: if (i > first + 1) { \
592: fprintf(File, "-%s", reg_names[Regoff + i - 1]); \
593: } \
594: first = -2; \
595: } \
596: } \
597: if ( (first >= 0) && (first != 15) ) \
598: fprintf(File, "-%s", reg_names[Regoff + 15]);\
599: fprintf(File, ")"); \
600: } \
601: }
602:
603:
604: #define MY_PRINT_ONEREG_L(FILE,MASK) \
605: { register int i; \
606: for (i = 0; i < 16; i++) \
607: if ( (1 << i) & (MASK)) { \
608: fprintf(FILE, "%s", reg_names[i]); \
609: (MASK) &= ~(1 << i); \
610: break; \
611: } \
612: }
613:
614:
615: #define MY_PRINT_ONEREG_H(FILE,MASK) \
616: { register int i; \
617: for (i = 15; i >= 0; i--) \
618: if ( (1 << i) & (MASK)) { \
619: fprintf(FILE, "%s", reg_names[i]); \
620: (MASK) &= ~(1 << i); \
621: break; \
622: } \
623: }
624:
625: /* This macro generates the assembly code for function entry.
626: FILE is a stdio stream to output the code to.
627: SIZE is an int: how many units of temporary storage to allocate.
628: Refer to the array `regs_ever_live' to determine which registers
629: to save; `regs_ever_live[I]' is nonzero if register number I
630: is ever used in the function. This macro is responsible for
631: knowing which registers should not be saved even if used. */
632:
633: /* The next macro needs much optimization !!
634: M.Yuhara */
635:
636: #define FUNCTION_PROLOGUE(FILE, SIZE) \
637: { register int regno; \
638: register int mask = 0; \
639: register int nregs = 0; \
640: static char *reg_names[] = REGISTER_NAMES; \
641: extern char call_used_regs[]; \
642: int fsize = ((SIZE) + 3) & -4; \
643: for (regno = 0; regno < 16; regno++) \
644: if (regs_ever_live[regno] && !call_used_regs[regno]) { \
645: mask |= (1 << regno); \
646: nregs++; \
647: } \
648: if (frame_pointer_needed) { \
649: mask &= ~(1 << FRAME_POINTER_REGNUM); \
650: if (nregs > 4) { \
651: fprintf(FILE, "\tenter.w #%d,", fsize); \
652: MY_PRINT_MASK(FILE, mask, MY_GREG_OFF); \
653: fprintf(FILE,"\n"); \
654: } else { \
655: fprintf(FILE, "\tmov.w fp,@-sp\n"); \
656: fprintf(FILE, "\tmov.w sp,fp\n"); \
657: if (fsize > 0) \
658: myoutput_sp_adjust(FILE, "sub", fsize); \
659: while (nregs--) { \
660: fprintf(FILE, "\tmov.w "); \
661: MY_PRINT_ONEREG_H(FILE, mask); \
662: fprintf(FILE, ",@-sp\n"); \
663: } \
664: } \
665: } else { \
666: if (fsize > 0) \
667: myoutput_sp_adjust(FILE, "sub", fsize); \
668: if (mask != 0) { \
669: if (nregs > 4) { \
670: fprintf(FILE, "\tstm.w "); \
671: MY_PRINT_MASK(FILE, mask, MY_GREG_OFF); \
672: fprintf(FILE, ",@-sp\n"); \
673: } else { \
674: while (nregs--) { \
675: fprintf(FILE, "\tmov.w "); \
676: MY_PRINT_ONEREG_H(FILE, mask); \
677: fprintf(FILE, ",@-sp\n"); \
678: } \
679: } \
680: } \
681: } \
682: mask = 0; \
683: for (regno = 16; regno < 32; regno++) \
684: if (regs_ever_live[regno] && !call_used_regs[regno]) \
685: mask |= 1 << (regno - 16); \
686: if (mask != 0) { \
687: fprintf(FILE, "\tfstm.w "); \
688: MY_PRINT_MASK(FILE, mask, MY_FREG_OFF); \
689: fprintf(FILE, ",@-sp\n", mask); \
690: } \
691: }
692:
693:
694: /* Output assembler code to FILE to increment profiler label # LABELNO
695: for profiling a function entry. */
696: /* ??? M.Yuhara */
697:
698: #define FUNCTION_PROFILER(FILE, LABELNO) \
699: fprintf (FILE, "\tmova @LP%d,r0\n\tjsr mcount\n", (LABELNO))
700:
701: /* Output assembler code to FILE to initialize this source file's
702: basic block profiling info, if that has not already been done. */
703:
704: #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
705: fprintf (FILE, "\tcmp #0,@LPBX0\n\tbne LPI%d\n\tpusha @LPBX0\n\tjsr ___bb_init_func\n\tadd #4,sp\nLPI%d:\n", \
706: LABELNO, LABELNO);
707:
708: /* Output assembler code to FILE to increment the entry-count for
709: the BLOCKNO'th basic block in this source file. */
710:
711: #define BLOCK_PROFILER(FILE, BLOCKNO) \
712: fprintf (FILE, "\tadd #1,@(LPBX2+%d)\n", 4 * BLOCKNO)
713:
714: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
715: the stack pointer does not matter. The value is tested only in
716: functions that have frame pointers.
717: No definition is equivalent to always zero. */
718:
719: #define EXIT_IGNORE_STACK 1
720:
721: /* This macro generates the assembly code for function exit,
722: on machines that need it. If FUNCTION_EPILOGUE is not defined
723: then individual return instructions are generated for each
724: return statement. Args are same as for FUNCTION_PROLOGUE.
725:
726: The function epilogue should not depend on the current stack pointer (when
727: frame_pinter_needed) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
728: It should use the frame pointer only. This is mandatory because
729: of alloca; we also take advantage of it to omit stack adjustments
730: before returning. */
731:
732: /* The Gmicro FPU seems to be unable to fldm/fstm double or single
733: floating. It only allows extended !! */
734: /* Optimization is not enough, especially FREGs load !! M.Yuhara */
735:
736: #define FUNCTION_EPILOGUE(FILE, SIZE) \
737: { register int regno; \
738: register int mask, fmask; \
739: register int nregs, nfregs; \
740: int offset, foffset; \
741: extern char call_used_regs[]; \
742: static char *reg_names[] = REGISTER_NAMES; \
743: int fsize = ((SIZE) + 3) & -4; \
744: FUNCTION_EXTRA_EPILOGUE (FILE, SIZE); \
745: nfregs = 0; fmask = 0; \
746: for (regno = 16; regno < 31; regno++) \
747: if (regs_ever_live[regno] && ! call_used_regs[regno]) \
748: { nfregs++; fmask |= 1 << (regno - 16); } \
749: foffset = nfregs * 12; \
750: nregs = 0; mask = 0; \
751: if (frame_pointer_needed) regs_ever_live[FRAME_POINTER_REGNUM] = 0; \
752: for (regno = 0; regno < 16; regno++) \
753: if (regs_ever_live[regno] && ! call_used_regs[regno]) \
754: { nregs++; mask |= 1 << regno; } \
755: if (frame_pointer_needed) { \
756: offset = nregs * 4 + fsize; \
757: if (nfregs > 0) { \
758: fprintf(FILE, "\tfldm.x @(%d,fp),", -(foffset + offset));\
759: MY_PRINT_MASK(FILE, fmask, MY_FREG_OFF); \
760: fprintf(FILE, "\n"); \
761: } \
762: if (nregs > 4 \
763: || current_function_pops_args) { \
764: fprintf(FILE, "\tmova @(%d,fp),sp\n", -offset); \
765: fprintf(FILE, "\texitd "); \
766: MY_PRINT_MASK(FILE, mask, MY_GREG_OFF); \
767: fprintf(FILE, ",#%d\n", current_function_pops_args); \
768: } else { \
769: while (nregs--) { \
770: fprintf(FILE, "\tmov:l.w @(%d,fp),", -offset); \
771: MY_PRINT_ONEREG_L(FILE, mask); \
772: fprintf(FILE, "\n"); \
773: offset -= 4; \
774: } \
775: if (TARGET_NEWRETURN) { \
776: fprintf(FILE, "\tmova.w @(4,fp),sp\n"); \
777: fprintf(FILE, "\tmov:l.w @fp,fp\n"); \
778: } else { \
779: fprintf(FILE, "\tmov.w fp,sp\n"); \
780: fprintf(FILE, "\tmov.w @sp+,fp\n"); \
781: } \
782: fprintf(FILE, "\trts\n"); \
783: } \
784: } else { \
785: if (nfregs > 0) { \
786: fprintf(FILE, "\tfldm.w @sp+,"); \
787: MY_PRINT_MASK(FILE, fmask, MY_FREG_OFF); \
788: fprintf(FILE, "\n"); \
789: } \
790: if (nregs > 4) { \
791: fprintf(FILE, "\tldm.w @sp+,"); \
792: MY_PRINT_MASK(FILE, mask, MY_GREG_OFF); \
793: fprintf(FILE, "\n"); \
794: } else { \
795: while (nregs--) { \
796: fprintf(FILE, "\tmov.w @sp+,"); \
797: MY_PRINT_ONEREG_L(FILE,mask); \
798: fprintf(FILE, "\n"); \
799: } \
800: } \
801: if (current_function_pops_args) { \
802: myoutput_sp_adjust(FILE, "add", \
803: (fsize + 4 + current_function_pops_args)); \
804: fprintf(FILE, "\tjmp @(%d,sp)\n", current_function_pops_args);\
805: } else { \
806: if (fsize > 0) \
807: myoutput_sp_adjust(FILE, "add", fsize); \
808: fprintf(FILE, "\trts\n"); \
809: } \
810: } \
811: }
812:
813: /* This is a hook for other tm files to change. */
814: #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE)
815:
816: /* If the memory address ADDR is relative to the frame pointer,
817: correct it to be relative to the stack pointer instead.
818: This is for when we don't use a frame pointer.
819: ADDR should be a variable name. */
820:
821: /* You have to change the next macro if you want to use more complex
822: addressing modes (such as double indirection and more than one
823: chain-addressing stages). */
824:
825: #define FIX_FRAME_POINTER_ADDRESS(ADDR,DEPTH) \
826: { int offset = -1; \
827: rtx regs = stack_pointer_rtx; \
828: if (ADDR == frame_pointer_rtx) \
829: offset = 0; \
830: else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx \
831: && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \
832: offset = INTVAL (XEXP (ADDR, 1)); \
833: else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx) \
834: { rtx other_reg = XEXP (ADDR, 1); \
835: offset = 0; \
836: regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
837: else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 1) == frame_pointer_rtx) \
838: { rtx other_reg = XEXP (ADDR, 0); \
839: offset = 0; \
840: regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
841: else if (GET_CODE (ADDR) == PLUS \
842: && GET_CODE (XEXP (ADDR, 0)) == PLUS \
843: && XEXP (XEXP (ADDR, 0), 0) == frame_pointer_rtx \
844: && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \
845: { rtx other_reg = XEXP (XEXP (ADDR, 0), 1); \
846: offset = INTVAL (XEXP (ADDR, 1)); \
847: regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
848: else if (GET_CODE (ADDR) == PLUS \
849: && GET_CODE (XEXP (ADDR, 0)) == PLUS \
850: && XEXP (XEXP (ADDR, 0), 1) == frame_pointer_rtx \
851: && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \
852: { rtx other_reg = XEXP (XEXP (ADDR, 0), 0); \
853: offset = INTVAL (XEXP (ADDR, 1)); \
854: regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
855: if (offset >= 0) \
856: { int regno; \
857: extern char call_used_regs[]; \
858: for (regno = 16; regno < 32; regno++) \
859: if (regs_ever_live[regno] && ! call_used_regs[regno]) \
860: offset += 12; \
861: for (regno = 0; regno < 16; regno++) \
862: if (regs_ever_live[regno] && ! call_used_regs[regno]) \
863: offset += 4; \
864: offset -= 4; \
865: ADDR = plus_constant (regs, offset + (DEPTH)); } }
866:
867: /* Addressing modes, and classification of registers for them. */
868:
869: /* #define HAVE_POST_INCREMENT */
870: /* #define HAVE_POST_DECREMENT */
871:
872: /* #define HAVE_PRE_DECREMENT */
873: /* #define HAVE_PRE_INCREMENT */
874:
875: /* Macros to check register numbers against specific register classes. */
876:
877: /* These assume that REGNO is a hard or pseudo reg number.
878: They give nonzero only if REGNO is a hard reg of the suitable class
879: or a pseudo reg currently allocated to a suitable hard reg.
880: Since they use reg_renumber, they are safe only once reg_renumber
881: has been allocated, which happens in local-alloc.c. */
882:
883: /* Gmicro */
884: #define REGNO_OK_FOR_GREG_P(REGNO) \
885: ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
886: #define REGNO_OK_FOR_FPU_P(REGNO) \
887: (((REGNO) ^ 0x10) < 16 || (unsigned) (reg_renumber[REGNO] ^ 0x10) < 16)
888:
889: #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_GREG_P(REGNO)
890: #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_GREG_P(REGNO)
891:
892: /* Now macros that check whether X is a register and also,
893: strictly, whether it is in a specified class.
894:
895: These macros are specific to the Gmicro, and may be used only
896: in code for printing assembler insns and in conditions for
897: define_optimization. */
898:
899: /* 1 if X is an fpu register. */
900:
901: #define FPU_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FPU_P (REGNO (X)))
902:
903: /* I used GREG_P in the gmicro.md file. */
904:
905: #ifdef REG_OK_STRICT
906: #define GREG_P(X) (REG_P (X) && REGNO_OK_FOR_GREG_P (REGNO(X)))
907: #else
908: #define GREG_P(X) (REG_P (X) && ((REGNO (X) & ~0xf) != 0x10))
909: #endif
910:
911: /* Maximum number of registers that can appear in a valid memory address. */
912:
913: /* The Gmicro allows more registers in the chained addressing mode.
914: But I do not know gcc supports such an architecture. */
915:
916: #define MAX_REGS_PER_ADDRESS 2
917:
918: /* Recognize any constant value that is a valid address. */
919:
920: #define CONSTANT_ADDRESS_P(X) CONSTANT_P (X)
921:
922: /* Nonzero if the constant value X is a legitimate general operand.
923: It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
924:
925: #define LEGITIMATE_CONSTANT_P(X) 1
926:
927: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
928: and check its validity for a certain class.
929: We have two alternate definitions for each of them.
930: The usual definition accepts all pseudo regs; the other rejects
931: them unless they have been allocated suitable hard regs.
932: The symbol REG_OK_STRICT causes the latter definition to be used.
933:
934: Most source files want to accept pseudo regs in the hope that
935: they will get allocated to the class that the insn wants them to be in.
936: Source files for reload pass need to be strict.
937: After reload, it makes no difference, since pseudo regs have
938: been eliminated by then. */
939:
940: #ifndef REG_OK_STRICT
941:
942: /* Nonzero if X is a hard reg that can be used as an index
943: or if it is a pseudo reg. */
944: #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) & ~0xf) != 0x10)
945: /* Nonzero if X is a hard reg that can be used as a base reg
946: or if it is a pseudo reg. */
947: #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~0xf) != 0x10)
948:
949: #else
950:
951: /* Nonzero if X is a hard reg that can be used as an index. */
952: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
953: /* Nonzero if X is a hard reg that can be used as a base reg. */
954: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
955:
956: #endif
957:
958: /* The gcc uses the following effective address of the Gmicro.
959: (without using PC!!).
960: {@} ( {Rbase} + {Disp} + {Rindex * [1,2,4,8]} )
961: where
962: @: memory indirection.
963: Rbase: Base Register = General Register.
964: Disp: Displacement (up to 32bits)
965: Rindex: Index Register = General Register.
966: [1,2,4,8]: Scale of Index. 1 or 2 or 4 or 8.
967: The inside of { } can be omitted.
968: This restricts the chained addressing up to 1 stage. */
969:
970:
971:
972: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
973: that is a valid memory address for an instruction.
974: The MODE argument is the machine mode for the MEM expression
975: that wants to use this address.
976:
977: The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
978: except for CONSTANT_ADDRESS_P which is actually machine-independent. */
979:
980: #define REG_CODE_BASE_P(X) \
981: (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
982:
983: #define REG_CODE_INDEX_P(X) \
984: (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
985:
986: /* GET_CODE(X) must be PLUS. This macro does not check for PLUS! */
987: #define BASE_PLUS_DISP_P(X) \
988: ( REG_CODE_BASE_P (XEXP (X, 0)) \
989: && CONSTANT_ADDRESS_P (XEXP (X, 1)) \
990: || \
991: REG_CODE_BASE_P (XEXP (X, 1)) \
992: && CONSTANT_ADDRESS_P (XEXP (X, 0)) )
993:
994: /* 1 if X is {0,Rbase} + {0,disp}. */
995: #define BASED_ADDRESS_P(X) \
996: (CONSTANT_ADDRESS_P (X) \
997: || REG_CODE_BASE_P (X) \
998: || (GET_CODE (X) == PLUS) \
999: && BASE_PLUS_DISP_P (X))
1000:
1001: /* 1 if X is 1 or 2 or 4 or 8. GET_CODE(X) must be CONST_INT. */
1002: #define SCALE_OF_INDEX_P(X) \
1003: ( INTVAL(X) == 4 \
1004: || INTVAL(X) == 2 \
1005: || INTVAL(X) == 8 \
1006: || INTVAL(X) == 1 )
1007:
1008: /* #define INDEX_TERM_P(X,MODE) */
1009: #define INDEX_TERM_P(X) \
1010: ( REG_CODE_INDEX_P(X) \
1011: || (GET_CODE (X) == MULT \
1012: && ( (xfoo0 = XEXP (X, 0)), (xfoo1 = XEXP(X, 1)), \
1013: ( ( (GET_CODE (xfoo0) == CONST_INT) \
1014: && SCALE_OF_INDEX_P (xfoo0) \
1015: && REG_CODE_INDEX_P (xfoo1) ) \
1016: || \
1017: ( (GET_CODE (xfoo1) == CONST_INT) \
1018: && SCALE_OF_INDEX_P (xfoo1) \
1019: && REG_CODE_INDEX_P (xfoo0) ) ))))
1020:
1021: /* Assumes there are no cases such that X = (Ireg + Disp) + Disp */
1022: #define BASE_DISP_INDEX_P(X) \
1023: ( BASED_ADDRESS_P (X) \
1024: || ( (GET_CODE (X) == PLUS) \
1025: && ( ( (xboo0 = XEXP (X, 0)), (xboo1 = XEXP (X, 1)), \
1026: (REG_CODE_BASE_P (xboo0) \
1027: && (GET_CODE (xboo1) == PLUS) \
1028: && ( ( CONSTANT_ADDRESS_P (XEXP (xboo1, 0)) \
1029: && INDEX_TERM_P (XEXP (xboo1, 1)) ) \
1030: || ( CONSTANT_ADDRESS_P (XEXP (xboo1, 1)) \
1031: && INDEX_TERM_P (XEXP (xboo1, 0))) ))) \
1032: || \
1033: (CONSTANT_ADDRESS_P (xboo0) \
1034: && (GET_CODE (xboo1) == PLUS) \
1035: && ( ( REG_CODE_BASE_P (XEXP (xboo1, 0)) \
1036: && INDEX_TERM_P (XEXP (xboo1, 1)) ) \
1037: || ( REG_CODE_BASE_P (XEXP (xboo1, 1)) \
1038: && INDEX_TERM_P (XEXP (xboo1, 0))) )) \
1039: || \
1040: (INDEX_TERM_P (xboo0) \
1041: && ( ( (GET_CODE (xboo1) == PLUS) \
1042: && ( ( REG_CODE_BASE_P (XEXP (xboo1, 0)) \
1043: && CONSTANT_ADDRESS_P (XEXP (xboo1, 1)) ) \
1044: || ( REG_CODE_BASE_P (XEXP (xboo1, 1)) \
1045: && CONSTANT_ADDRESS_P (XEXP (xboo1, 0))) )) \
1046: || \
1047: (CONSTANT_ADDRESS_P (xboo1)) \
1048: || \
1049: (REG_CODE_BASE_P (xboo1)) )))))
1050:
1051: /*
1052: If you want to allow double-indirection,
1053: you have to change the <fp-relative> => <sp-relative> conversion
1054: routine. M.Yuhara
1055:
1056: #ifdef REG_OK_STRICT
1057: #define DOUBLE_INDIRECTION(X,ADDR) {\
1058: if (BASE_DISP_INDEX_P (XEXP (XEXP (X, 0), 0) )) goto ADDR; \
1059: }
1060: #else
1061: #define DOUBLE_INDIRECTION(X,ADDR) { }
1062: #endif
1063: */
1064:
1065:
1066: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) {\
1067: register rtx xboo0, xboo1, xfoo0, xfoo1; \
1068: if (GET_CODE (X) == MEM) { \
1069: /* \
1070: if (GET_CODE (XEXP (X,0)) == MEM) { \
1071: DOUBLE_INDIRECTION(X,ADDR); \
1072: } else { \
1073: if (BASE_DISP_INDEX_P (XEXP (X, 0))) goto ADDR; \
1074: } \
1075: */ \
1076: } else { \
1077: if (BASE_DISP_INDEX_P (X)) goto ADDR; \
1078: if ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
1079: && REG_P (XEXP (X, 0)) \
1080: && (REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM)) \
1081: goto ADDR; \
1082: } \
1083: }
1084:
1085:
1086: /* Try machine-dependent ways of modifying an illegitimate address
1087: to be legitimate. If we find one, return the new, valid address.
1088: This macro is used in only one place: `memory_address' in explow.c.
1089:
1090: OLDX is the address as it was before break_out_memory_refs was called.
1091: In some cases it is useful to look at this to decide what needs to be done.
1092:
1093: MODE and WIN are passed so that this macro can use
1094: GO_IF_LEGITIMATE_ADDRESS.
1095:
1096: It is always safe for this macro to do nothing. It exists to recognize
1097: opportunities to optimize the output.
1098:
1099: For the Gmicro, nothing is done now. */
1100:
1101: #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {}
1102:
1103: /* Go to LABEL if ADDR (a legitimate address expression)
1104: has an effect that depends on the machine mode it is used for.
1105: On the VAX, the predecrement and postincrement address depend thus
1106: (the amount of decrement or increment being the length of the operand)
1107: and all indexed address depend thus (because the index scale factor
1108: is the length of the operand).
1109: The Gmicro mimics the VAX now. Since ADDE is legitimate, it cannot
1110: include auto-inc/dec. */
1111:
1112: /* Unnecessary ??? */
1113: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1114: { if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) \
1115: goto LABEL; }
1116:
1117:
1118: /* Specify the machine mode that this machine uses
1119: for the index in the tablejump instruction. */
1120: /* #define CASE_VECTOR_MODE HImode */
1121: #define CASE_VECTOR_MODE SImode
1122:
1123: /* Define this if the tablejump instruction expects the table
1124: to contain offsets from the address of the table.
1125: Do not define this if the table should contain absolute addresses. */
1126: #define CASE_VECTOR_PC_RELATIVE
1127:
1128: /* Specify the tree operation to be used to convert reals to integers. */
1129: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1130:
1131: /* This is the kind of divide that is easiest to do in the general case. */
1132: #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1133:
1134: /* Define this as 1 if `char' should by default be signed; else as 0. */
1135: #define DEFAULT_SIGNED_CHAR 1
1136:
1137: /* Max number of bytes we can move from memory to memory
1138: in one reasonably fast instruction. */
1139: #define MOVE_MAX 4
1140:
1141: /* Define this if zero-extension is slow (more than one real instruction). */
1142: /* #define SLOW_ZERO_EXTEND */
1143:
1144: /* Nonzero if access to memory by bytes is slow and undesirable. */
1145: #define SLOW_BYTE_ACCESS 0
1146:
1147: /* Define if shifts truncate the shift count
1148: which implies one can omit a sign-extension or zero-extension
1149: of a shift count. */
1150: /* #define SHIFT_COUNT_TRUNCATED */
1151:
1152: /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1153: is done just by pretending it is already truncated. */
1154: #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1155:
1156: /* We assume that the store-condition-codes instructions store 0 for false
1157: and some other value for true. This is the value stored for true. */
1158:
1159: /* #define STORE_FLAG_VALUE -1 */
1160:
1161: /* When a prototype says `char' or `short', really pass an `int'. */
1162: #define PROMOTE_PROTOTYPES
1163:
1164: /* Specify the machine mode that pointers have.
1165: After generation of rtl, the compiler makes no further distinction
1166: between pointers and any other objects of this machine mode. */
1167: #define Pmode SImode
1168:
1169: /* A function address in a call instruction
1170: is a byte address (for indexing purposes)
1171: so give the MEM rtx a byte's mode. */
1172: #define FUNCTION_MODE QImode
1173:
1174: /* Compute the cost of computing a constant rtl expression RTX
1175: whose rtx-code is CODE. The body of this macro is a portion
1176: of a switch statement. If the code is computed here,
1177: return it with a return statement. Otherwise, break from the switch. */
1178:
1179: #define CONST_COSTS(RTX,CODE) \
1180: case CONST_INT: \
1181: if ((unsigned) INTVAL (RTX) < 8) return 0; \
1182: if ((unsigned) (INTVAL (RTX) + 0x80) < 0x100) return 1; \
1183: if ((unsigned) (INTVAL (RTX) + 0x8000) < 0x10000) return 2; \
1184: case CONST: \
1185: case LABEL_REF: \
1186: case SYMBOL_REF: \
1187: return 3; \
1188: case CONST_DOUBLE: \
1189: return 5;
1190:
1191: /* Define subroutines to call to handle multiply and divide.
1192: The `*' prevents an underscore from being prepended by the compiler. */
1193: /* Use libgcc on Gmicro */
1194: /* #define UDIVSI3_LIBCALL "*udiv" */
1195: /* #define UMODSI3_LIBCALL "*urem" */
1196:
1197:
1198: /* Tell final.c how to eliminate redundant test instructions. */
1199:
1200: /* Here we define machine-dependent flags and fields in cc_status
1201: (see `conditions.h'). */
1202:
1203: /* Set if the cc value is actually in the FPU, so a floating point
1204: conditional branch must be output. */
1205: #define CC_IN_FPU 04000
1206:
1207: /* Store in cc_status the expressions
1208: that the condition codes will describe
1209: after execution of an instruction whose pattern is EXP.
1210: Do not alter them if the instruction would not alter the cc's. */
1211:
1212: /* Since Gmicro's compare instructions depend on the branch condition,
1213: all branch should be kept.
1214: More work must be done to optimize condition code !! M.Yuhara */
1215:
1216: #define NOTICE_UPDATE_CC(EXP, INSN) {CC_STATUS_INIT;}
1217:
1218: /* The skelton of the next macro is taken from "vax.h".
1219: FPU-reg manipulation is added. M.Yuhara */
1220: /* Now comment out.
1221: #define NOTICE_UPDATE_CC(EXP, INSN) { \
1222: if (GET_CODE (EXP) == SET) { \
1223: if ( !FPU_REG_P (XEXP (EXP, 0)) \
1224: && (XEXP (EXP, 0) != cc0_rtx) \
1225: && (FPU_REG_P (XEXP (EXP, 1)) \
1226: || GET_CODE (XEXP (EXP, 1)) == FIX \
1227: || GET_CODE (XEXP (EXP, 1)) == FLOAT_TRUNCATE \
1228: || GET_CODE (XEXP (EXP, 1)) == FLOAT_EXTEND)) { \
1229: CC_STATUS_INIT; \
1230: } else if (GET_CODE (SET_SRC (EXP)) == CALL) { \
1231: CC_STATUS_INIT; \
1232: } else if (GET_CODE (SET_DEST (EXP)) != PC) { \
1233: cc_status.flags = 0; \
1234: cc_status.value1 = SET_DEST (EXP); \
1235: cc_status.value2 = SET_SRC (EXP); \
1236: } \
1237: } else if (GET_CODE (EXP) == PARALLEL \
1238: && GET_CODE (XVECEXP (EXP, 0, 0)) == SET \
1239: && GET_CODE (SET_DEST (XVECEXP (EXP, 0, 0))) != PC) {\
1240: cc_status.flags = 0; \
1241: cc_status.value1 = SET_DEST (XVECEXP (EXP, 0, 0)); \
1242: cc_status.value2 = SET_SRC (XVECEXP (EXP, 0, 0)); \
1243: /* PARALLELs whose first element sets the PC are aob, sob VAX insns. \
1244: They do change the cc's. So drop through and forget the cc's. * / \
1245: } else CC_STATUS_INIT; \
1246: if (cc_status.value1 && GET_CODE (cc_status.value1) == REG \
1247: && cc_status.value2 \
1248: && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) \
1249: cc_status.value2 = 0; \
1250: if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM \
1251: && cc_status.value2 \
1252: && GET_CODE (cc_status.value2) == MEM) \
1253: cc_status.value2 = 0; \
1254: if ( (cc_status.value1 && FPU_REG_P (cc_status.value1)) \
1255: || (cc_status.value2 && FPU_REG_P (cc_status.value2))) \
1256: cc_status.flags = CC_IN_FPU; \
1257: }
1258: */
1259:
1260: #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1261: { if (cc_prev_status.flags & CC_IN_FPU) \
1262: return FLOAT; \
1263: if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1264: return NO_OV; \
1265: return NORMAL; }
1266:
1267: /* Control the assembler format that we output. */
1268:
1269: /* Output before read-only data. */
1270:
1271: #define TEXT_SECTION_ASM_OP "\t.section text,code,align=4"
1272:
1273: /* Output before writable data. */
1274:
1275: #define DATA_SECTION_ASM_OP "\t.section data,data,align=4"
1276:
1277: /* Output before uninitialized data. */
1278:
1279: #define BSS_SECTION_ASM_OP "\t.section bss,data,align=4"
1280:
1281: #define EXTRA_SECTIONS in_bss
1282:
1283: #define EXTRA_SECTION_FUNCTIONS \
1284: void \
1285: bss_section () \
1286: { \
1287: if (in_section != in_bss) { \
1288: fprintf (asm_out_file, "%s\n", BSS_SECTION_ASM_OP); \
1289: in_section = in_bss; \
1290: } \
1291: }
1292:
1293: /* Output at beginning of assembler file.
1294: It is not appropriate for this to print a list of the options used,
1295: since that's not the convention that we use. */
1296:
1297: #define ASM_FILE_START(FILE)
1298:
1299: /* Output at the end of assembler file. */
1300:
1301: #define ASM_FILE_END(FILE) fprintf (FILE, "\t.end\n");
1302:
1303:
1304: /* Don't try to define `gcc_compiled.' since the assembler do not
1305: accept symbols with periods and GDB doesn't run on this machine anyway. */
1306: #define ASM_IDENTIFY_GCC(FILE)
1307:
1308:
1309: /* Output to assembler file text saying following lines
1310: may contain character constants, extra white space, comments, etc. */
1311:
1312: #define ASM_APP_ON ""
1313: /* #define ASM_APP_ON "#APP\n" */
1314:
1315: /* Output to assembler file text saying following lines
1316: no longer contain unusual constructs. */
1317:
1318: #define ASM_APP_OFF ""
1319: /* #define ASM_APP_OFF ";#NO_APP\n" */
1320:
1321: /* How to refer to registers in assembler output.
1322: This sequence is indexed by compiler's hard-register-number (see above). */
1323:
1324: #define REGISTER_NAMES \
1325: {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1326: "r8", "r9", "r10", "r11", "r12", "r13", "fp", "sp", \
1327: "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
1328: "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15"}
1329:
1330: /* How to renumber registers for dbx and gdb. */
1331:
1332: #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1333:
1334: /* Define this if gcc should produce debugging output for dbx in response
1335: to the -g flag. This does not work for the Gmicro now */
1336:
1337: #define DBX_DEBUGGING_INFO
1338:
1339: /* This is how to output the definition of a user-level label named NAME,
1340: such as the label on a static function or variable NAME. */
1341:
1342: #define ASM_OUTPUT_LABEL(FILE,NAME) { \
1343: assemble_name (FILE, NAME); \
1344: fputs (":\n", FILE); \
1345: }
1346:
1347: /* This is how to output a command to make the user-level label named NAME
1348: defined for reference from other files. */
1349:
1350: #define ASM_GLOBALIZE_LABEL(FILE,NAME) {\
1351: fputs ("\t.global ", FILE); \
1352: assemble_name (FILE, NAME); \
1353: fputs ("\n", FILE); \
1354: }
1355:
1356: /* This is how to output a command to make the external label named NAME
1357: which are not defined in the file to be referable */
1358: /* ".import" does not work ??? */
1359:
1360: #define ASM_OUTPUT_EXTERNAL(FILE,DECL,NAME) { \
1361: fputs ("\t.global ", FILE); \
1362: assemble_name (FILE, NAME); \
1363: fputs ("\n", FILE); \
1364: }
1365:
1366:
1367: /* This is how to output a reference to a user-level label named NAME.
1368: `assemble_name' uses this. */
1369:
1370: #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1371: fprintf (FILE, "_%s", NAME)
1372:
1373: /* This is how to output an internal numbered label where
1374: PREFIX is the class of label and NUM is the number within the class. */
1375:
1376: #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1377: fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1378:
1379: /* This is how to store into the string LABEL
1380: the symbol_ref name of an internal numbered label where
1381: PREFIX is the class of label and NUM is the number within the class.
1382: This is suitable for output with `assemble_name'. */
1383:
1384: #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1385: sprintf (LABEL, "*%s%d", PREFIX, NUM)
1386:
1387: /* This is how to output an assembler line defining a `double' constant. */
1388:
1389: /* do {...} while(0) is necessary, because these macros are used as
1390: if (xxx) MACRO; else ....
1391: ^
1392: */
1393:
1394:
1395: #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1396: do { union { double d; long l[2];} tem; \
1397: tem.d = (VALUE); \
1398: fprintf (FILE, "\t.fdata.d h'%x%08x.d\n", tem.l[0], tem.l[1]); \
1399: } while(0)
1400:
1401:
1402: /* This is how to output an assembler line defining a `float' constant. */
1403:
1404: #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1405: do { union { float f; long l;} tem; \
1406: tem.f = (VALUE); \
1407: fprintf (FILE, "\t.fdata.s h'%x.s\n", tem.l); \
1408: } while(0)
1409:
1410: /* This is how to output an assembler line defining an `int' constant. */
1411:
1412: #define ASM_OUTPUT_INT(FILE,VALUE) \
1413: ( fprintf (FILE, "\t.data.w "), \
1414: output_addr_const (FILE, (VALUE)), \
1415: fprintf (FILE, "\n"))
1416:
1417: /* Likewise for `char' and `short' constants. */
1418:
1419: #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1420: ( fprintf (FILE, "\t.data.h "), \
1421: output_addr_const (FILE, (VALUE)), \
1422: fprintf (FILE, "\n"))
1423:
1424: #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1425: ( fprintf (FILE, "\t.data.b "), \
1426: output_addr_const (FILE, (VALUE)), \
1427: fprintf (FILE, "\n"))
1428:
1429: /* This is how to output an assembler line for a numeric constant byte. */
1430:
1431: #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1432: fprintf (FILE, "\t.data.b h'%x\n", (VALUE))
1433:
1434: #define ASM_OUTPUT_ASCII(FILE,P,SIZE) \
1435: output_ascii ((FILE), (P), (SIZE))
1436:
1437: /* This is how to output an insn to push a register on the stack.
1438: It need not be very fast code. */
1439:
1440: #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1441: fprintf (FILE, "\tmov %s,@-sp\n", reg_names[REGNO])
1442:
1443: /* This is how to output an insn to pop a register from the stack.
1444: It need not be very fast code. */
1445:
1446: #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1447: fprintf (FILE, "\tmov @sp+,%s\n", reg_names[REGNO])
1448:
1449: /* This is how to output an element of a case-vector that is absolute.
1450: (The Gmicro does not use such vectors,
1451: but we must define this macro anyway.) */
1452:
1453: #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1454: fprintf (FILE, "\t.data.w L%d\n", VALUE)
1455:
1456:
1457: /* This is how to output an element of a case-vector that is relative. */
1458:
1459: #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1460: fprintf (FILE, "\t.data.w L%d-L%d\n", VALUE, REL)
1461:
1462:
1463: /* This is how to output an assembler line
1464: that says to advance the location counter
1465: to a multiple of 2**LOG bytes. */
1466:
1467: #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1468: fprintf (FILE, "\t.align %d\n", (1 << (LOG)));
1469:
1470: #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1471: fprintf (FILE, "\t.res.b %d\n", (SIZE))
1472:
1473: /* This says how to output an assembler line
1474: to define a global common symbol. */
1475:
1476: #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1477: ( bss_section (), \
1478: assemble_name ((FILE), (NAME)), \
1479: fprintf ((FILE), ":\t.res.b %d\n", (ROUNDED)),\
1480: fprintf ((FILE), "\t.export "), \
1481: assemble_name ((FILE), (NAME)), \
1482: fprintf ((FILE), "\n") )
1483:
1484: /* This says how to output an assembler line
1485: to define a local common symbol. */
1486:
1487: #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1488: ( bss_section (), \
1489: assemble_name ((FILE), (NAME)), \
1490: fprintf ((FILE), ":\t.res.b %d\n", (ROUNDED)))
1491:
1492: /* Store in OUTPUT a string (made with alloca) containing
1493: an assembler-name for a local static variable named NAME.
1494: LABELNO is an integer which is different for each call. */
1495:
1496: /* $__ is unique ????? M.Yuhara */
1497: #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1498: ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 12), \
1499: sprintf ((OUTPUT), "$__%s%d", (NAME), (LABELNO)))
1500:
1501: /* Define the parentheses used to group arithmetic operations
1502: in assembler code. */
1503:
1504: #define ASM_OPEN_PAREN "("
1505: #define ASM_CLOSE_PAREN ")"
1506:
1507: /* Define results of standard character escape sequences. */
1508: #define TARGET_BELL 007
1509: #define TARGET_BS 010
1510: #define TARGET_TAB 011
1511: #define TARGET_NEWLINE 012
1512: #define TARGET_VT 013
1513: #define TARGET_FF 014
1514: #define TARGET_CR 015
1515:
1516: /* Output a float value (represented as a C double) as an immediate operand.
1517: This macro is a Gmicro/68k-specific macro. */
1518:
1519: #define ASM_OUTPUT_FLOAT_OPERAND(FILE,VALUE) \
1520: do { union { float f; long l;} tem; \
1521: tem.f = (VALUE); \
1522: fprintf (FILE, "#h'%x.s", tem.l); \
1523: } while(0)
1524:
1525:
1526: /* Output a double value (represented as a C double) as an immediate operand.
1527: This macro is a 68k-specific macro. */
1528: #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
1529: do { union { double d; long l[2];} tem; \
1530: tem.d = (VALUE); \
1531: fprintf (FILE, "#h'%x%08x.d", tem.l[0], tem.l[1]); \
1532: } while(0)
1533:
1534: /* Print operand X (an rtx) in assembler syntax to file FILE.
1535: CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1536: For `%' followed by punctuation, CODE is the punctuation and X is null.
1537:
1538: On the Gmicro, we use several CODE characters:
1539: 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1540: 'b' for branch target label.
1541: '-' for an operand pushing on the stack.
1542: '+' for an operand pushing on the stack.
1543: '#' for an immediate operand prefix
1544: */
1545:
1546: #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1547: ( (CODE) == '#' || (CODE) == '-' \
1548: || (CODE) == '+' || (CODE) == '@' || (CODE) == '!')
1549:
1550:
1551: #define PRINT_OPERAND(FILE, X, CODE) \
1552: { int i; \
1553: static char *reg_name[] = REGISTER_NAMES; \
1554: /* fprintf (stderr, "PRINT_OPERAND CODE=%c(0x%x), ", CODE, CODE);\
1555: myprcode(GET_CODE(X)); */ \
1556: if (CODE == '#') fprintf (FILE, "#"); \
1557: else if (CODE == '-') fprintf (FILE, "@-sp"); \
1558: else if (CODE == '+') fprintf (FILE, "@sp+"); \
1559: else if (CODE == 's') fprintf (stderr, "err: PRINT_OPERAND <s>\n"); \
1560: else if (CODE == '!') fprintf (stderr, "err: PRINT_OPERAND <!>\n"); \
1561: else if (CODE == '.') fprintf (stderr, "err: PRINT_OPERAND <.>\n"); \
1562: else if (CODE == 'b') { \
1563: if (GET_CODE (X) == MEM) \
1564: output_addr_const (FILE, XEXP (X, 0)); /* for bsr */ \
1565: else \
1566: output_addr_const (FILE, X); /* for bcc */ \
1567: } \
1568: else if (CODE == 'p') \
1569: print_operand_address (FILE, X); \
1570: else if (GET_CODE (X) == REG) \
1571: fprintf (FILE, "%s", reg_name[REGNO (X)]); \
1572: else if (GET_CODE (X) == MEM) \
1573: output_address (XEXP (X, 0)); \
1574: else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode) \
1575: { union { double d; int i[2]; } u; \
1576: union { float f; int i; } u1; \
1577: u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \
1578: u1.f = u.d; \
1579: if (CODE == 'f') \
1580: ASM_OUTPUT_FLOAT_OPERAND (FILE, u1.f); \
1581: else \
1582: fprintf (FILE, "#h'%x", u1.i); } \
1583: else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != DImode) \
1584: { union { double d; int i[2]; } u; \
1585: u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \
1586: ASM_OUTPUT_DOUBLE_OPERAND (FILE, u.d); } \
1587: else { putc ('#', FILE); \
1588: output_addr_const (FILE, X); }}
1589:
1590: /* Note that this contains a kludge that knows that the only reason
1591: we have an address (plus (label_ref...) (reg...))
1592: is in the insn before a tablejump, and we know that m68k.md
1593: generates a label LInnn: on such an insn. */
1594: #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1595: { print_operand_address (FILE, ADDR); }
1596:
1597: /*
1598: Local variables:
1599: version-control: t
1600: End:
1601: */
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