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1.1.1.2 ! root 1: ;;- Machine description for GNU compiler, Fujitsu Gmicro Version ! 2: ;; Copyright (C) 1990, 1994 Free Software Foundation, Inc. ! 3: ;; Contributed by M.Yuhara, Fujitsu Laboratories LTD. 1.1 root 4: 5: ;; This file is part of GNU CC. 6: 7: ;; GNU CC is free software; you can redistribute it and/or modify 8: ;; it under the terms of the GNU General Public License as published by 9: ;; the Free Software Foundation; either version 2, or (at your option) 10: ;; any later version. 11: 12: ;; GNU CC is distributed in the hope that it will be useful, 13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15: ;; GNU General Public License for more details. 16: ;; Among other things, the copyright 17: ;; notice and this notice must be preserved on all copies. 18: 19: 20: ;; You should have received a copy of the GNU General Public License 21: ;; along with GNU CC; see the file COPYING. If not, write to 22: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 23: 24: 25: ;;- instruction definitions 26: 27: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 28: 29: ;;- When naming insn's (operand 0 of define_insn) be careful about using 30: ;;- names from other targets machine descriptions. 31: 32: ;;- cpp macro #define NOTICE_UPDATE_CC is essentially a no-op for the 33: ;;- gmicro; no compares are eliminated. 34: 35: ;;- The original structure of this file is m68k.md. 36: 37: ;; ??? Work to be done: 38: ;; Add patterns for ACB and SCB instructions. 39: ;; Add define_insn patterns to recognize the insns that extend a byte 40: ;; to a word and add it into a word, etc. 41: 42: ;;- Some of these insn's are composites of several Gmicro op codes. 43: ;;- The assembler (or final @@??) insures that the appropriate one is 44: ;;- selected. 45: 46: (define_insn "" 47: [(set (match_operand:DF 0 "push_operand" "=m") 48: (match_operand:DF 1 "general_operand" "rmfF"))] 49: "" 50: "* 51: { 52: if (FPU_REG_P (operands[1])) 53: return \"fmov.d %f1,%0\"; 54: return output_move_double (operands); 55: }") 56: 57: (define_insn "" 58: [(set (match_operand:DI 0 "push_operand" "=m") 59: (match_operand:DF 1 "general_operand" "rmF"))] 60: "" 61: "* 62: { 63: return output_move_double (operands); 64: }") 65: 66: ;; We don't want to allow a constant operand for test insns because 67: ;; (set (cc0) (const_int foo)) has no mode information. Such insns will 68: ;; be folded while optimizing anyway. 69: 70: (define_insn "tstsi" 71: [(set (cc0) 72: (match_operand:SI 0 "nonimmediate_operand" "rm"))] 73: "" 74: "cmp:z.w #0,%0") 75: 76: (define_insn "tsthi" 77: [(set (cc0) 78: (match_operand:HI 0 "nonimmediate_operand" "rm"))] 79: "" 80: "cmp:z.h #0,%0") 81: 82: (define_insn "tstqi" 83: [(set (cc0) 84: (match_operand:QI 0 "nonimmediate_operand" "rm"))] 85: "" 86: "cmp:z.b #0,%0") 87: 88: 89: (define_insn "tstsf" 90: [(set (cc0) 91: (match_operand:SF 0 "general_operand" "fmF"))] 92: "TARGET_FPU" 93: "* 94: { 95: cc_status.flags = CC_IN_FPU; 96: return \"ftst.s %0\"; 97: }") 98: 99: 100: (define_insn "tstdf" 101: [(set (cc0) 102: (match_operand:DF 0 "general_operand" "fmF"))] 103: "TARGET_FPU" 104: "* 105: { 106: cc_status.flags = CC_IN_FPU; 107: return \"ftst.d %0\"; 108: }") 109: 110: ;; compare instructions. 111: 112: ;; (operand0 - operand1) 113: (define_insn "cmpsi" 114: [(set (cc0) 115: (compare (match_operand:SI 0 "nonimmediate_operand" "ri,rm") 116: (match_operand:SI 1 "general_operand" "rm,rmi")))] 117: "" 118: "* 119: { 120: int signed_flag = my_signed_comp (insn); 121: 122: if (which_alternative == 0) 123: { 124: cc_status.flags |= CC_REVERSED; 125: if (signed_flag && GET_CODE (operands[0]) == CONST_INT) 126: { 127: register rtx xfoo; 128: xfoo = operands[1]; 129: operands[0] = operands[1]; 130: operands[1] = xfoo; 131: return cmp_imm_word (INTVAL (operands[1]), operands[0]); 132: } 133: if (signed_flag) 134: return \"cmp.w %0,%1\"; 135: return \"cmpu.w %0,%1\"; 136: } 137: if (signed_flag) 138: { 139: if (GET_CODE (operands[1]) == CONST_INT) 140: return cmp_imm_word (INTVAL (operands[1]), operands[0]); 141: return \"cmp.w %1,%0\"; 142: } 143: else 144: return \"cmpu.w %1,%0\"; 145: }") 146: 147: (define_insn "cmphi" 148: [(set (cc0) 149: (compare (match_operand:HI 0 "nonimmediate_operand" "ri,rm") 150: (match_operand:HI 1 "general_operand" "rm,rmi")))] 151: "" 152: "* 153: { 154: int signed_flag = my_signed_comp (insn); 155: 156: if (which_alternative == 0) 157: { 158: cc_status.flags |= CC_REVERSED; 159: if (signed_flag) 160: return \"cmp.h %0,%1\"; 161: return \"cmpu.h %0,%1\"; 162: } 163: if (signed_flag) 164: return \"cmp.h %1,%0\"; 165: return \"cmpu.h %1,%0\"; 166: }") 167: 168: (define_insn "cmpqi" 169: [(set (cc0) 170: (compare (match_operand:QI 0 "nonimmediate_operand" "ri,rm") 171: (match_operand:QI 1 "general_operand" "rm,rmi")))] 172: "" 173: "* 174: { 175: int signed_flag = my_signed_comp (insn); 176: 177: if (which_alternative == 0) 178: { 179: cc_status.flags |= CC_REVERSED; 180: if (signed_flag) 181: return \"cmp.b %0,%1\"; 182: return \"cmpu.b %0,%1\"; 183: } 184: if (signed_flag) 185: return \"cmp.b %1,%0\"; 186: return \"cmpu.b %1,%0\"; 187: }") 188: 189: 190: (define_insn "cmpdf" 191: [(set (cc0) 192: (compare (match_operand:DF 0 "general_operand" "f,mG") 193: (match_operand:DF 1 "general_operand" "fmG,f")))] 194: "TARGET_FPU" 195: "* 196: { 197: cc_status.flags = CC_IN_FPU; 198: 199: if (FPU_REG_P (operands[0])) 200: return \"fcmp.d %f1,%f0\"; 201: cc_status.flags |= CC_REVERSED; 202: return \"fcmp.d %f0,%f1\"; 203: }") 204: 205: 206: (define_insn "cmpsf" 207: [(set (cc0) 208: (compare (match_operand:SF 0 "general_operand" "f,mG") 209: (match_operand:SF 1 "general_operand" "fmG,f")))] 210: "TARGET_FPU" 211: "* 212: { 213: cc_status.flags = CC_IN_FPU; 214: if (FPU_REG_P (operands[0])) 215: return \"fcmp.s %f1,%0\"; 216: cc_status.flags |= CC_REVERSED; 217: return \"fcmp.s %f0,%1\"; 218: }") 219: 220: ;; Recognizers for btst instructions. 221: 222: (define_insn "" 223: [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "rm") 224: (const_int 1) 225: (match_operand:SI 1 "general_operand" "rmi")))] 226: "" 227: "btst %1.w,%0.b") 228: 229: (define_insn "" 230: [(set (cc0) (zero_extract (match_operand:HI 0 "nonimmediate_operand" "rm") 231: (const_int 1) 232: (match_operand:SI 1 "general_operand" "rmi")))] 233: "" 234: "btst %1.w,%0.h") 235: 236: (define_insn "" 237: [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "rm") 238: (const_int 1) 239: (match_operand:SI 1 "general_operand" "rmi")))] 240: "" 241: "btst %1.w,%0.w") 242: 243: ;; The following two patterns are like the previous two 244: ;; except that they use the fact that bit-number operands (offset) 245: ;; are automatically masked to 3 or 5 bits when the base is a register. 246: 247: (define_insn "" 248: [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "r") 249: (const_int 1) 250: (and:SI 251: (match_operand:SI 1 "general_operand" "rmi") 252: (const_int 7))))] 253: "" 254: "btst %1.w,%0.b") 255: 256: (define_insn "" 257: [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "r") 258: (const_int 1) 259: (and:SI 260: (match_operand:SI 1 "general_operand" "rmi") 261: (const_int 31))))] 262: "" 263: "btst %1.w,%0.w") 264: 265: ; More various size-patterns are allowed for btst, but not 266: ; included yet. M.Yuhara 267: 268: 269: (define_insn "" 270: [(set (cc0) (and:SI (sign_extend:SI (sign_extend:HI (match_operand:QI 0 "nonimmediate_operand" "rm"))) 271: (match_operand:SI 1 "general_operand" "i")))] 272: "(GET_CODE (operands[1]) == CONST_INT 273: && (unsigned) INTVAL (operands[1]) < 0x100 274: && exact_log2 (INTVAL (operands[1])) >= 0)" 275: "* 276: { 277: register int log = exact_log2 (INTVAL (operands[1])); 278: operands[1] = gen_rtx (CONST_INT, VOIDmode, log); 279: return \"btst %1,%0.b\"; 280: }") 281: 282: ; I can add more patterns like above. But not yet. M.Yuhara 283: 284: 285: ; mtst is supported only by G/300. 286: 287: (define_insn "" 288: [(set (cc0) 289: (and:SI (match_operand:SI 0 "general_operand" "%rmi") 290: (match_operand:SI 1 "general_operand" "rm")))] 291: "TARGET_G300" 292: "* 293: { 294: if (GET_CODE (operands[0]) == CONST_INT) 295: return \"mtst.w %0,%1\"; 296: return \"mtst.w %1,%0\"; 297: }") 298: 299: (define_insn "" 300: [(set (cc0) 301: (and:HI (match_operand:HI 0 "general_operand" "%rmi") 302: (match_operand:HI 1 "general_operand" "rm")))] 303: "TARGET_G300" 304: "* 305: { 306: if (GET_CODE (operands[0]) == CONST_INT) 307: return \"mtst.h %0,%1\"; 308: return \"mtst.h %1,%0\"; 309: }") 310: 311: (define_insn "" 312: [(set (cc0) 313: (and:QI (match_operand:QI 0 "general_operand" "%rmi") 314: (match_operand:QI 1 "general_operand" "rm")))] 315: "TARGET_G300" 316: "* 317: { 318: if (GET_CODE (operands[0]) == CONST_INT) 319: return \"mtst.b %0,%1\"; 320: return \"mtst.b %1,%0\"; 321: }") 322: 323: 324: 325: ;; move instructions 326: 327: /* added by M.Yuhara */ 328: ;; 1.35.04 89.08.28 modification start 329: ;; register_operand -> general_operand 330: ;; ashift -> mult 331: 332: (define_insn "" 333: [(set (mem:SI (plus:SI 334: (match_operand:SI 0 "general_operand" "r") 335: (ashift:SI 336: (match_operand:SI 1 "general_operand" "r") 337: (const_int 2)))) 338: (match_operand:SI 2 "general_operand" "rmi"))] 339: "" 340: "* 341: { 342: return \"mov.w %2,@(%0:b,%1*4)\"; 343: }") 344: 345: (define_insn "" 346: [(set (mem:SI (plus:SI 347: (ashift:SI 348: (match_operand:SI 0 "general_operand" "r") 349: (const_int 2)) 350: (match_operand:SI 1 "general_operand" "r"))) 351: (match_operand:SI 2 "general_operand" "rmi"))] 352: "" 353: "* 354: { 355: return \"mov.w %2,@(%1:b,%0*4)\"; 356: }") 357: 358: 359: (define_insn "" 360: [(set (mem:SI (plus:SI 361: (match_operand:SI 0 "register_operand" "r") 362: (mult:SI 363: (match_operand:SI 1 "register_operand" "r") 364: (const_int 4)))) 365: (match_operand:SI 2 "general_operand" "rmi"))] 366: "" 367: "* 368: { 369: return \"mov.w %2,@(%0:b,%1*4)\"; 370: }") 371: 372: (define_insn "" 373: [(set (mem:SI (plus:SI 374: (mult:SI 375: (match_operand:SI 0 "register_operand" "r") 376: (const_int 4)) 377: (match_operand:SI 1 "register_operand" "r"))) 378: (match_operand:SI 2 "general_operand" "rmi"))] 379: "" 380: "* 381: { 382: return \"mov.w %2,@(%1:b,%0*4)\"; 383: }") 384: 385: 386: (define_insn "" 387: [(set (mem:SI (plus:SI 388: (match_operand:SI 0 "general_operand" "r") 389: (plus:SI 390: (match_operand:SI 1 "register_operand" "r") 391: (match_operand:SI 2 "register_operand" "i")))) 392: (match_operand:SI 3 "general_operand" "rmi"))] 393: "" 394: "* 395: { 396: return \"mov.w %3,@(%c2,%0,%1)\"; 397: }") 398: 399: (define_insn "" 400: [(set (mem:SI (plus:SI 401: (plus:SI 402: (match_operand:SI 0 "register_operand" "r") 403: (match_operand:SI 1 "register_operand" "r")) 404: (match_operand:SI 2 "general_operand" "i"))) 405: (match_operand:SI 3 "general_operand" "rmi"))] 406: "" 407: "* 408: { 409: return \"mov.w %3,@(%c2,%0,%1)\"; 410: }") 411: 412: 413: (define_insn "" 414: [(set (mem:SI (plus:SI 415: (match_operand:SI 0 "general_operand" "i") 416: (plus:SI 417: (match_operand:SI 1 "register_operand" "r") 418: (mult:SI 419: (match_operand:SI 2 "register_operand" "r") 420: (const_int 4))))) 421: (match_operand:SI 3 "general_operand" "rmi"))] 422: "" 423: "* 424: { 425: return \"mov.w %3,@(%1:b,%0,%2*4)\"; 426: }") 427: 428: ;; 89.08.28 1.35.04 modification end 429: 430: ;; Should add "!" to op2 ?? 431: 432: ;; General move-address-to-operand should handle these. 433: ;; If that does not work, please figure out why. 434: 435: ;(define_insn "" 436: ; [(set (match_operand:SI 0 "push_operand" "=m") 437: ; (plus:SI 438: ; (match_operand:SI 1 "immediate_operand" "i") 439: ; (match_operand:SI 2 "general_operand" "r")))] 440: ; "" 441: ; "mova.w @(%c1,%2),%-") 442: 443: ;(define_insn "" 444: ; [(set (match_operand:SI 0 "push_operand" "=m") 445: ; (plus:SI 446: ; (match_operand:SI 1 "general_operand" "r") 447: ; (match_operand:SI 2 "immediate_operand" "i")))] 448: ; "" 449: ; "mova.w @(%c2,%1),%-") 450: 451: 452: (define_insn "" 453: [(set (match_operand:SI 0 "push_operand" "=m") 454: (minus:SI 455: (match_operand:SI 1 "general_operand" "r") 456: (match_operand:SI 2 "immediate_operand" "i")))] 457: "" 458: "mova.w @(%n2,%1),%-") 459: 460: 461: 462: ;; General case of fullword move. 463: 464: (define_insn "movsi" 465: [(set (match_operand:SI 0 "general_operand" "=rm") 466: (match_operand:SI 1 "general_operand" "rmi"))] 467: "" 468: "* 469: { 470: if (GET_CODE (operands[1]) == CONST_INT) 471: return mov_imm_word (INTVAL (operands[1]), operands[0]); 472: /* if (address_operand (operands[1], SImode)) 473: return \"mova.w %1,%0\"; */ 474: if (push_operand (operands[0], SImode)) 475: return \"mov.w %1,%-\"; 476: return \"mov.w %1,%0\"; 477: }") 478: 479: /* pushsi 89.08.10 for test M.Yuhara */ 480: /* 481: (define_insn "" 482: [(set (match_operand:SI 0 "push_operand" "=m") 483: (match_operand:SI 1 "general_operand" "rmi"))] 484: "" 485: "* 486: { 487: if (GET_CODE (operands[1]) == CONST_INT) 488: return mov_imm_word (INTVAL (operands[1]), operands[0]); 489: if (push_operand (operands[0], SImode)) 490: return \"mov.w %1,%-\"; 491: return \"mov.w %1,%0\"; 492: }") 493: */ 494: 495: 496: (define_insn "movhi" 497: [(set (match_operand:HI 0 "general_operand" "=rm") 498: (match_operand:HI 1 "general_operand" "rmi"))] 499: "" 500: "* 501: { 502: if (push_operand (operands[0], SImode)) 503: return \"mov.h %1,%-\"; 504: return \"mov.h %1,%0\"; 505: }") 506: 507: ;; Is the operand constraint "+" necessary ???? 508: ;; Should I check push_operand ???? 509: 510: (define_insn "movstricthi" 511: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+rm")) 512: (match_operand:HI 1 "general_operand" "rmi"))] 513: "" 514: "mov.h %1,%0"); 515: 516: (define_insn "movqi" 517: [(set (match_operand:QI 0 "general_operand" "=rm") 518: (match_operand:QI 1 "general_operand" "rmi"))] 519: "" 520: "* 521: { 522: if (GREG_P (operands[0])) 523: { 524: if (CONSTANT_P (operands[1])) 525: return \"mov:l %1,%0.w\"; 526: else 527: return \"mov:l %1.b,%0.w\"; 528: } 529: if (GREG_P (operands[1])) 530: return \"mov:s %1.w,%0.b\"; 531: return \"mov.b %1,%0\"; 532: }") 533: 534: (define_insn "movstrictqi" 535: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+rm")) 536: (match_operand:QI 1 "general_operand" "rmi"))] 537: "" 538: "mov.b %1,%0") 539: 540: 541: (define_insn "movsf" 542: [(set (match_operand:SF 0 "general_operand" "=f,mf,rm,fr") 543: (match_operand:SF 1 "general_operand" "mfF,f,rmF,fr"))] 544: "" 545: "* 546: { 547: switch (which_alternative) 548: { 549: case 0: 550: if (GET_CODE (operands[1]) == CONST_DOUBLE) 551: return output_move_const_single (operands); 552: return \"fmov.s %1,%0\"; 553: case 1: 554: return \"fmov.s %1,%0\"; 555: case 2: 556: if (GET_CODE (operands[1]) == CONST_DOUBLE) 557: return output_move_const_single (operands); 558: return \"mov.w %1,%0\"; 559: case 3: 560: if (FPU_REG_P (operands[0])) 561: return \"mov.w %1,%-\\n\\tfmov.s %+,%0\"; 562: return \"fmov.s %1,%-\\n\\tmov.w %+,%0\"; 563: } 564: }") 565: 566: (define_insn "movdf" 567: [(set (match_operand:DF 0 "general_operand" "=f,mf,rm,fr") 568: (match_operand:DF 1 "general_operand" "mfF,f,rmF,fr"))] 569: "" 570: "* 571: { 572: switch (which_alternative) 573: { 574: case 0: 575: if (GET_CODE (operands[1]) == CONST_DOUBLE) 576: return output_move_const_double (operands); 577: return \"fmov.d %1,%0\"; 578: case 1: 579: return \"fmov.d %1,%0\"; 580: case 2: 581: if (GET_CODE (operands[1]) == CONST_DOUBLE) 582: return output_move_const_double (operands); 583: return output_move_double (operands); 584: case 3: 585: if (FPU_REG_P (operands[0])) 586: { 587: rtx xoperands[2]; 588: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 589: output_asm_insn (\"mov.w %1,%-\", xoperands); 590: output_asm_insn (\"mov.w %1,%-\", operands); 591: return \"fmov.d %+,%0\"; 592: } 593: else 594: { 595: output_asm_insn (\"fmov.d %f1,%-\", operands); 596: output_asm_insn (\"mov.w %+,%0\", operands); 597: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 598: return \"mov.w %+,%0\"; 599: } 600: } 601: }") 602: 603: 604: ;; movdi can apply to fp regs in some cases 605: ;; Must check again. you can use fsti/fldi, etc. 606: ;; FPU reg should be included ?? 607: ;; 89.12.13 for test 608: 609: (define_insn "movdi" 610: ;; Let's see if it really still needs to handle fp regs, and, if so, why. 611: [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro") 612: (match_operand:DI 1 "general_operand" "rF,m,roiF"))] 613: "" 614: "* 615: { 616: if (FPU_REG_P (operands[0])) 617: { 618: if (FPU_REG_P (operands[1])) 619: return \"fmov.d %1,%0\"; 620: if (REG_P (operands[1])) 621: { 622: rtx xoperands[2]; 623: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 624: output_asm_insn (\"mov.w %1,%-\", xoperands); 625: output_asm_insn (\"mov.w %1,%-\", operands); 626: return \"fmov.d %+,%0\"; 627: } 628: if (GET_CODE (operands[1]) == CONST_DOUBLE) 629: return output_move_const_double (operands); 630: return \"fmov.d %f1,%0\"; 631: } 632: else if (FPU_REG_P (operands[1])) 633: { 634: if (REG_P (operands[0])) 635: { 636: output_asm_insn (\"fmov.d %f1,%-\;mov.w %+,%0\", operands); 637: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 638: return \"mov.w %+,%0\"; 639: } 640: else 641: return \"fmov.d %f1,%0\"; 642: } 643: return output_move_double (operands); 644: } 645: ") 646: 647: 648: ;; The definition of this insn does not really explain what it does, 649: ;; but it should suffice 650: ;; that anything generated as this insn will be recognized as one 651: ;; and that it won't successfully combine with anything. 652: 653: ;; This is dangerous when %0 and %1 overlapped !!!!! 654: ;; Ugly code... 655: 656: (define_insn "movstrhi" 657: [(set (match_operand:BLK 0 "general_operand" "=m") 658: (match_operand:BLK 1 "general_operand" "m")) 659: (use (match_operand:HI 2 "general_operand" "rmi")) 660: (clobber (reg:SI 0)) 661: (clobber (reg:SI 1)) 662: (clobber (reg:SI 2))] 663: "" 664: "* 665: { 666: int op2const; 667: rtx tmpx; 668: 669: if (CONSTANT_P (operands[1])) 670: { 671: fprintf (stderr, \"smov 1 const err \"); 672: abort (); 673: } 674: else if (GET_CODE (operands[1]) == REG) 675: { 676: fprintf (stderr, \"smov 1 reg err \"); 677: abort (); 678: } 679: else if (GET_CODE (operands[1]) == MEM) 680: { 681: tmpx = XEXP (operands[1], 0); 682: if (CONSTANT_ADDRESS_P (tmpx) || GREG_P (tmpx)) 683: { 684: operands[1] = tmpx; 685: output_asm_insn (\"mov.w %1,r0\", operands); 686: } 687: else 688: { 689: output_asm_insn (\"mova %1,r0\", operands); 690: } 691: } 692: else 693: { 694: fprintf (stderr, \"smov 1 else err \"); 695: abort (); 696: output_asm_insn (\"mova.w %p1,r0\", operands); 697: } 698: 699: if (CONSTANT_P (operands[0])) 700: { 701: fprintf (stderr, \"smov 0 const err \"); 702: abort (); 703: } 704: else if (GET_CODE (operands[0]) == REG) 705: { 706: fprintf (stderr, \"smov 0 reg err \"); 707: abort (); 708: } 709: else if (GET_CODE (operands[0]) == MEM) 710: { 711: tmpx = XEXP (operands[0], 0); 712: if (CONSTANT_ADDRESS_P (tmpx) || GREG_P (tmpx)) 713: { 714: operands[0] = tmpx; 715: output_asm_insn (\"mov.w %0,r1\", operands); 716: } 717: else 718: { 719: output_asm_insn (\"mova %0,r1\", operands); 720: } 721: } 722: else 723: { 724: fprintf (stderr, \"smov 0 else err \"); 725: abort (); 726: } 727: 728: if (GET_CODE (operands[2]) == CONST_INT) 729: { 730: op2const = INTVAL (operands[2]); 731: if (op2const % 4 != 0) 732: { 733: output_asm_insn (\"mov.w %2,r2\", operands); 734: return \"smov/n/f.b\"; 735: } 736: op2const = op2const / 4; 737: if (op2const <= 4) 738: { 739: if (op2const == 0) 740: abort (0); 741: if (op2const == 1) 742: return \"mov.w @r0,@r1\"; 743: output_asm_insn (\"mov.w @r0,@r1\", operands); 744: if (op2const == 2) 745: return \"mov.w @(4,r0),@(4,r1)\"; 746: output_asm_insn (\"mov.w @(4,r0),@(4,r1)\", operands); 747: if (op2const == 3) 748: return \"mov.w @(8,r0),@(8,r1)\"; 749: output_asm_insn (\"mov.w @(8,r0),@(8,r1)\", operands); 750: return \"mov.w @(12,r0),@(12,r1)\"; 751: } 752: 753: operands[2] = 754: gen_rtx (CONST_INT, VOIDmode, op2const); 755: output_asm_insn (\"mov.w %2,r2\", operands); 756: return \"smov/n/f.w\"; 757: } 758: else 759: { 760: fprintf (stderr, \"smov 0 else err \"); 761: abort (); 762: output_asm_insn (\"mov %2.h,r2.w\", operands); 763: return \"smov/n/f.b\"; 764: } 765: 766: }") 767: 768: ;; M.Yuhara 89.08.24 769: ;; experiment on the built-in strcpy (__builtin_smov) 770: ;; 771: ;; len = 0 means unknown string length. 772: ;; 773: ;; mem:SI is dummy. Necessary so as not to be deleted by optimization. 774: ;; Use of BLKmode would be better... 775: ;; 776: ;; 777: (define_insn "smovsi" 778: [(set (mem:SI (match_operand:SI 0 "general_operand" "=rm")) 779: (mem:SI (match_operand:SI 1 "general_operand" "rm"))) 780: (use (match_operand:SI 2 "general_operand" "i")) 781: (clobber (reg:SI 0)) 782: (clobber (reg:SI 1)) 783: (clobber (reg:SI 2)) 784: (clobber (reg:SI 3))] 785: "" 786: "* 787: { 788: int len, wlen, blen, offset; 789: char tmpstr[128]; 790: rtx xoperands[1]; 791: 792: len = INTVAL (operands[2]); 793: output_asm_insn (\"mov.w %1,r0\\t; begin built-in strcpy\", operands); 794: output_asm_insn (\"mov.w %0,r1\", operands); 795: 796: if (len == 0) 797: { 798: output_asm_insn (\"mov:z.w #0,r2\", operands); 799: output_asm_insn (\"mov:z.w #0,r3\", operands); 800: return \"smov/eq/f.b\\t; end built-in strcpy\"; 801: } 802: 803: wlen = len / 4; 804: blen = len - wlen * 4; 805: 806: if (wlen > 0) 807: { 808: if (len <= 40 && !TARGET_FORCE_SMOV) 809: { 810: output_asm_insn (\"mov.w @r0,@r1\", operands); 811: offset = 4; 812: while ( (blen = len - offset) > 0) 813: { 814: if (blen >= 4) 815: { 816: sprintf (tmpstr, \"mov.w @(%d,r0),@(%d,r1)\", 817: offset, offset); 818: output_asm_insn (tmpstr, operands); 819: offset += 4; 820: } 821: else if (blen >= 2) 822: { 823: sprintf (tmpstr, \"mov.h @(%d,r0),@(%d,r1)\", 824: offset, offset); 825: output_asm_insn (tmpstr, operands); 826: offset += 2; 827: } 828: else 829: { 830: sprintf (tmpstr, \"mov.b @(%d,r0),@(%d,r1)\", 831: offset, offset); 832: output_asm_insn (tmpstr, operands); 833: offset++; 834: } 835: } 836: return \"\\t\\t; end built-in strcpy\"; 837: } 838: else 839: { 840: xoperands[0] = gen_rtx (CONST_INT, VOIDmode, wlen); 841: output_asm_insn (\"mov.w %0,r2\", xoperands); 842: output_asm_insn (\"smov/n/f.w\", operands); 843: } 844: } 845: 846: if (blen >= 2) 847: { 848: output_asm_insn (\"mov.h @r0,@r1\", operands); 849: if (blen == 3) 850: output_asm_insn (\"mov.b @(2,r0),@(2,r1)\", operands); 851: } 852: else if (blen == 1) 853: { 854: output_asm_insn (\"mov.b @r0,@r1\", operands); 855: } 856: 857: return \"\\t\\t; end built-in strcpy\"; 858: }") 859: 860: ;; truncation instructions 861: (define_insn "truncsiqi2" 862: [(set (match_operand:QI 0 "general_operand" "=rm") 863: (truncate:QI 864: (match_operand:SI 1 "general_operand" "rmi")))] 865: "" 866: "mov %1.w,%0.b") 867: ; "* 868: ;{ 869: ; if (GET_CODE (operands[0]) == REG) 870: ; return \"mov.w %1,%0\"; 871: ; if (GET_CODE (operands[1]) == MEM) 872: ; operands[1] = adj_offsettable_operand (operands[1], 3); 873: ; return \"mov.b %1,%0\"; 874: ;}") 875: 876: (define_insn "trunchiqi2" 877: [(set (match_operand:QI 0 "general_operand" "=rm") 878: (truncate:QI 879: (match_operand:HI 1 "general_operand" "rmi")))] 880: "" 881: "mov %1.h,%0.b") 882: ; "* 883: ;{ 884: ; if (GET_CODE (operands[0]) == REG) 885: ; return \"mov.h %1,%0\"; 886: ; if (GET_CODE (operands[1]) == MEM) 887: ; operands[1] = adj_offsettable_operand (operands[1], 1); 888: ; return \"mov.b %1,%0\"; 889: ;}") 890: 891: (define_insn "truncsihi2" 892: [(set (match_operand:HI 0 "general_operand" "=rm") 893: (truncate:HI 894: (match_operand:SI 1 "general_operand" "rmi")))] 895: "" 896: "mov %1.w,%0.h") 897: ; "* 898: ;{ 899: ; if (GET_CODE (operands[0]) == REG) 900: ; return \"mov.w %1,%0\"; 901: ; if (GET_CODE (operands[1]) == MEM) 902: ; operands[1] = adj_offsettable_operand (operands[1], 2); 903: ; return \"mov.h %1,%0\"; 904: ;}") 905: 906: ;; zero extension instructions 907: ;; define_expand (68k) -> define_insn (Gmicro) 908: 909: (define_insn "zero_extendhisi2" 910: [(set (match_operand:SI 0 "general_operand" "=rm") 911: (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))] 912: "" 913: "movu %1.h,%0.w") 914: 915: 916: (define_insn "zero_extendqihi2" 917: [(set (match_operand:HI 0 "general_operand" "=rm") 918: (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))] 919: "" 920: "movu %1.b,%0.h") 921: 922: (define_insn "zero_extendqisi2" 923: [(set (match_operand:SI 0 "general_operand" "=rm") 924: (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))] 925: "" 926: "movu %1.b,%0.w") 927: 928: 929: ;; sign extension instructions 930: 931: (define_insn "extendhisi2" 932: [(set (match_operand:SI 0 "general_operand" "=rm") 933: (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))] 934: "" 935: "mov %1.h,%0.w") 936: 937: 938: (define_insn "extendqihi2" 939: [(set (match_operand:HI 0 "general_operand" "=rm") 940: (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))] 941: "" 942: "mov %1.b,%0.h") 943: 944: (define_insn "extendqisi2" 945: [(set (match_operand:SI 0 "general_operand" "=rm") 946: (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))] 947: "" 948: "mov %1.b,%0.w") 949: 950: 951: 952: ;; Conversions between float and double. 953: 954: (define_insn "extendsfdf2" 955: [(set (match_operand:DF 0 "general_operand" "=*frm,f") 956: (float_extend:DF 957: (match_operand:SF 1 "general_operand" "f,rmF")))] 958: "TARGET_FPU" 959: "* 960: { 961: if (FPU_REG_P (operands[0])) 962: { 963: if (GET_CODE (operands[1]) == CONST_DOUBLE) 964: return output_move_const_double (operands); 965: if (GREG_P (operands[1])) 966: { 967: output_asm_insn (\"mov.w %1,%-\", operands); 968: return \"fmov %+.s,%0.d\"; 969: } 970: return \"fmov %1.s,%0.d\"; 971: } 972: else 973: { 974: if (GREG_P (operands[0])) 975: { 976: output_asm_insn (\"fmov %1.s,%-.d\", operands); 977: output_asm_insn (\"mov.w %+,%0\", operands); 978: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 979: return \"mov.w %+,%0\"; 980: } 981: return \"fmov %1.s,%0.d\"; 982: } 983: }") 984: 985: 986: (define_insn "truncdfsf2" 987: [(set (match_operand:SF 0 "general_operand" "=rfm") 988: (float_truncate:SF 989: (match_operand:DF 1 "general_operand" "f")))] 990: "TARGET_FPU" 991: "* 992: { 993: if (GREG_P (operands[0])) 994: { 995: output_asm_insn (\"fmov %1.d,%-.s\", operands); 996: return \"mov.w %+,%0\"; 997: } 998: return \"fmov %1.d,%0.s\"; 999: }") 1000: 1001: ;; Conversion between fixed point and floating point. 1002: ;; Note that among the fix-to-float insns 1003: ;; the ones that start with SImode come first. 1004: ;; That is so that an operand that is a CONST_INT 1005: ;; (and therefore lacks a specific machine mode). 1006: ;; will be recognized as SImode (which is always valid) 1007: ;; rather than as QImode or HImode. 1008: 1009: 1010: (define_insn "floatsisf2" 1011: [(set (match_operand:SF 0 "general_operand" "=f") 1012: (float:SF (match_operand:SI 1 "general_operand" "rmi")))] 1013: "TARGET_FPU" 1014: "fldi %1.w,%0.s") 1015: 1016: (define_insn "floatsidf2" 1017: [(set (match_operand:DF 0 "general_operand" "=f") 1018: (float:DF (match_operand:SI 1 "general_operand" "rmi")))] 1019: "TARGET_FPU" 1020: "fldi %1.w,%0.d") 1021: 1022: (define_insn "floathisf2" 1023: [(set (match_operand:SF 0 "general_operand" "=f") 1024: (float:SF (match_operand:HI 1 "general_operand" "rmi")))] 1025: "TARGET_FPU" 1026: "fldi %1.h,%0.s") 1027: 1028: (define_insn "floathidf2" 1029: [(set (match_operand:DF 0 "general_operand" "=f") 1030: (float:DF (match_operand:HI 1 "general_operand" "rmi")))] 1031: "TARGET_FPU" 1032: "fldi %1.h,%0.d") 1033: 1034: (define_insn "floatqisf2" 1035: [(set (match_operand:SF 0 "general_operand" "=f") 1036: (float:SF (match_operand:QI 1 "general_operand" "rmi")))] 1037: "TARGET_FPU" 1038: "fldi %1.b,%0.s") 1039: 1040: (define_insn "floatqidf2" 1041: [(set (match_operand:DF 0 "general_operand" "=f") 1042: (float:DF (match_operand:QI 1 "general_operand" "rmi")))] 1043: "TARGET_FPU" 1044: "fldi %1.b,%0.d") 1045: 1046: ;;; Convert a float to a float whose value is an integer. 1047: ;;; This is the first stage of converting it to an integer type. 1048: ; 1049: ;(define_insn "ftruncdf2" 1050: ; [(set (match_operand:DF 0 "general_operand" "=f") 1051: ; (fix:DF (match_operand:DF 1 "general_operand" "fFm")))] 1052: ; "TARGET_FPU" 1053: ; "* 1054: ;{ 1055: ; return \"fintrz.d %f1,%0\"; 1056: ;}") 1057: ; 1058: ;(define_insn "ftruncsf2" 1059: ; [(set (match_operand:SF 0 "general_operand" "=f") 1060: ; (fix:SF (match_operand:SF 1 "general_operand" "fFm")))] 1061: ; "TARGET_FPU" 1062: ; "* 1063: ;{ 1064: ; return \"fintrz.s %f1,%0\"; 1065: ;}") 1066: 1067: ;; Convert a float to an integer. 1068: 1069: (define_insn "fix_truncsfqi2" 1070: [(set (match_operand:QI 0 "general_operand" "=rm") 1071: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "f"))))] 1072: "TARGET_FPU" 1073: "fsti %1.s,%0.b") 1074: 1075: (define_insn "fix_truncsfhi2" 1076: [(set (match_operand:HI 0 "general_operand" "=rm") 1077: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "f"))))] 1078: "TARGET_FPU" 1079: "fsti %1.s,%0.h") 1080: 1081: (define_insn "fix_truncsfsi2" 1082: [(set (match_operand:SI 0 "general_operand" "=rm") 1083: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "f"))))] 1084: "TARGET_FPU" 1085: "fsti %1.s,%0.w") 1086: 1087: (define_insn "fix_truncdfqi2" 1088: [(set (match_operand:QI 0 "general_operand" "=rm") 1089: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "f"))))] 1090: "TARGET_FPU" 1091: "fsti %1.d,%0.b") 1092: 1093: (define_insn "fix_truncdfhi2" 1094: [(set (match_operand:HI 0 "general_operand" "=rm") 1095: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "f"))))] 1096: "TARGET_FPU" 1097: "fsti %1.d,%0.h") 1098: 1099: (define_insn "fix_truncdfsi2" 1100: [(set (match_operand:SI 0 "general_operand" "=rm") 1101: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "f"))))] 1102: "TARGET_FPU" 1103: "fsti %1.d,%0.w") 1104: 1105: 1106: ;;; Special add patterns 1107: ;;; 89.09.28 1108: 1109: ;; This should be redundant; please find out why regular addsi3 1110: ;; fails to match this case. 1111: 1112: ;(define_insn "" 1113: ; [(set (mem:SI (plus:SI 1114: ; (plus:SI (match_operand 0 "general_operand" "r") 1115: ; (match_operand 1 "general_operand" "r")) 1116: ; (match_operand 2 "general_operand" "i"))) 1117: ; (plus:SI 1118: ; (mem:SI (plus:SI 1119: ; (plus:SI (match_dup 0) 1120: ; (match_dup 1)) 1121: ; (match_dup 2))) 1122: ; (match_operand 3 "general_operand" "rmi")))] 1123: ; "" 1124: ; "add.w %3,@(%c2,%0,%1)") 1125: 1126: 1127: ;; add instructions 1128: 1129: ;; Note that the last two alternatives are near-duplicates 1130: ;; in order to handle insns generated by reload. 1131: ;; This is needed since they are not themselves reloaded, 1132: ;; so commutativity won't apply to them. 1133: 1134: (define_insn "addsi3" 1135: [(set (match_operand:SI 0 "general_operand" "=rm,!r,!r") 1136: (plus:SI (match_operand:SI 1 "general_operand" "%0,r,ri") 1137: (match_operand:SI 2 "general_operand" "rmi,ri,r")))] 1138: "" 1139: "* 1140: { 1141: if (which_alternative == 0) 1142: { 1143: if (GET_CODE (operands[2]) == CONST_INT) 1144: { 1145: operands[1] = operands[2]; 1146: return add_imm_word (INTVAL (operands[1]), operands[0], &operands[1]); 1147: } 1148: else 1149: return \"add.w %2,%0\"; 1150: } 1151: else 1152: { 1153: if (GET_CODE (operands[1]) == REG 1154: && REGNO (operands[0]) == REGNO (operands[1])) 1155: return \"add.w %2,%0\"; 1156: if (GET_CODE (operands[2]) == REG 1157: && REGNO (operands[0]) == REGNO (operands[2])) 1158: return \"add.w %1,%0\"; 1159: 1160: if (GET_CODE (operands[1]) == REG) 1161: { 1162: if (GET_CODE (operands[2]) == REG) 1163: return \"mova.w @(%1,%2),%0\"; 1164: else 1165: return \"mova.w @(%c2,%1),%0\"; 1166: } 1167: else 1168: return \"mova.w @(%c1,%2),%0\"; 1169: } 1170: }") 1171: 1172: (define_insn "" 1173: [(set (match_operand:SI 0 "general_operand" "=rm") 1174: (plus:SI (match_operand:SI 1 "general_operand" "0") 1175: (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rmi"))))] 1176: "" 1177: "* 1178: { 1179: if (CONSTANT_P (operands[2])) 1180: { 1181: operands[1] = operands[2]; 1182: return add_imm_word (INTVAL (operands[1]), operands[0], &operands[1]); 1183: } 1184: else 1185: return \"add %2.h,%0.w\"; 1186: }") 1187: 1188: (define_insn "addhi3" 1189: [(set (match_operand:HI 0 "general_operand" "=rm") 1190: (plus:HI (match_operand:HI 1 "general_operand" "%0") 1191: (match_operand:HI 2 "general_operand" "rmi")))] 1192: "" 1193: "* 1194: { 1195: if (GET_CODE (operands[2]) == CONST_INT 1196: && INTVAL (operands[2]) < 0) 1197: return \"sub.h #%n2,%0\"; 1198: if (GREG_P (operands[0])) 1199: { 1200: if (CONSTANT_P (operands[2])) 1201: return \"add:l %2,%0.w\"; 1202: else 1203: return \"add:l %2.h,%0.w\"; 1204: } 1205: return \"add.h %2,%0\"; 1206: }") 1207: 1208: (define_insn "" 1209: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+rm")) 1210: (plus:HI (match_dup 0) 1211: (match_operand:HI 1 "general_operand" "rmi")))] 1212: "" 1213: "add.h %1,%0") 1214: 1215: (define_insn "addqi3" 1216: [(set (match_operand:QI 0 "general_operand" "=rm") 1217: (plus:QI (match_operand:QI 1 "general_operand" "%0") 1218: (match_operand:QI 2 "general_operand" "rmi")))] 1219: "" 1220: "* 1221: { 1222: if (GET_CODE (operands[2]) == CONST_INT 1223: && INTVAL (operands[2]) < 0) 1224: return \"sub.b #%n2,%0\"; 1225: if (GREG_P (operands[0])) 1226: { 1227: if (CONSTANT_P (operands[2])) 1228: return \"add:l %2,%0.w\"; 1229: else 1230: return \"add:l %2.b,%0.w\"; 1231: } 1232: return \"add.b %2,%0\"; 1233: }") 1234: 1235: (define_insn "" 1236: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+rm")) 1237: (plus:QI (match_dup 0) 1238: (match_operand:QI 1 "general_operand" "rmi")))] 1239: "" 1240: "add.b %1,%0") 1241: 1242: (define_insn "adddf3" 1243: [(set (match_operand:DF 0 "general_operand" "=f") 1244: (plus:DF (match_operand:DF 1 "general_operand" "%0") 1245: (match_operand:DF 2 "general_operand" "fmG")))] 1246: "TARGET_FPU" 1247: "fadd.d %f2,%0") 1248: 1249: (define_insn "addsf3" 1250: [(set (match_operand:SF 0 "general_operand" "=f") 1251: (plus:SF (match_operand:SF 1 "general_operand" "%0") 1252: (match_operand:SF 2 "general_operand" "fmG")))] 1253: "TARGET_FPU" 1254: "fadd.s %f2,%0") 1255: 1256: ;; subtract instructions 1257: 1258: (define_insn "subsi3" 1259: [(set (match_operand:SI 0 "general_operand" "=rm,!r") 1260: (minus:SI (match_operand:SI 1 "general_operand" "0,r") 1261: (match_operand:SI 2 "general_operand" "rmi,i")))] 1262: "" 1263: "* 1264: { 1265: if (which_alternative == 0 1266: || (GET_CODE (operands[1]) == REG 1267: && REGNO (operands[0]) == REGNO (operands[1]))) 1268: { 1269: if (GET_CODE (operands[2]) == CONST_INT) 1270: { 1271: operands[1] = operands[2]; 1272: return sub_imm_word (INTVAL (operands[1]), 1273: operands[0], &operands[1]); 1274: } 1275: else 1276: return \"sub.w %2,%0\"; 1277: } 1278: else 1279: return \"mova.w @(%n2,%1),%0\"; 1280: }") 1281: 1282: (define_insn "" 1283: [(set (match_operand:SI 0 "general_operand" "=rm") 1284: (minus:SI (match_operand:SI 1 "general_operand" "0") 1285: (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rmi"))))] 1286: "" 1287: "sub %2.h,%0.w") 1288: 1289: (define_insn "subhi3" 1290: [(set (match_operand:HI 0 "general_operand" "=rm") 1291: (minus:HI (match_operand:HI 1 "general_operand" "0") 1292: (match_operand:HI 2 "general_operand" "rmi")))] 1293: "" 1294: "* 1295: { 1296: if (GET_CODE (operands[2]) == CONST_INT 1297: && INTVAL (operands[2]) < 0 1298: && INTVAL (operands[2]) != 0x8000) 1299: return \"add.h #%n2,%0\"; 1300: return \"sub.h %2,%0\"; 1301: }") 1302: 1303: (define_insn "" 1304: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+rm")) 1305: (minus:HI (match_dup 0) 1306: (match_operand:HI 1 "general_operand" "rmi")))] 1307: "" 1308: "sub.h %1,%0") 1309: 1310: (define_insn "subqi3" 1311: [(set (match_operand:QI 0 "general_operand" "=rm") 1312: (minus:QI (match_operand:QI 1 "general_operand" "0") 1313: (match_operand:QI 2 "general_operand" "rmi")))] 1314: "" 1315: "* 1316: { 1317: if (GET_CODE (operands[2]) == CONST_INT 1318: && INTVAL (operands[2]) < 0 1319: && INTVAL (operands[2]) != 0x80) 1320: return \"add.b #%n2,%0\"; 1321: return \"sub.b %2,%0\"; 1322: }") 1323: 1324: (define_insn "" 1325: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+rm")) 1326: (minus:QI (match_dup 0) 1327: (match_operand:QI 1 "general_operand" "rmi")))] 1328: "" 1329: "sub.b %1,%0") 1330: 1331: (define_insn "subdf3" 1332: [(set (match_operand:DF 0 "general_operand" "=f") 1333: (minus:DF (match_operand:DF 1 "general_operand" "0") 1334: (match_operand:DF 2 "general_operand" "fmG")))] 1335: "TARGET_FPU" 1336: "fsub.d %f2,%0") 1337: 1338: (define_insn "subsf3" 1339: [(set (match_operand:SF 0 "general_operand" "=f") 1340: (minus:SF (match_operand:SF 1 "general_operand" "0") 1341: (match_operand:SF 2 "general_operand" "fmG")))] 1342: "TARGET_FPU" 1343: "fsub.s %f2,%0") 1344: 1345: 1346: ;; multiply instructions 1347: 1348: (define_insn "mulqi3" 1349: [(set (match_operand:QI 0 "general_operand" "=rm") 1350: (mult:QI (match_operand:QI 1 "general_operand" "%0") 1351: (match_operand:QI 2 "general_operand" "rmi")))] 1352: "" 1353: "mul.b %2,%0") 1354: 1355: 1356: (define_insn "mulhi3" 1357: [(set (match_operand:HI 0 "general_operand" "=rm") 1358: (mult:HI (match_operand:HI 1 "general_operand" "%0") 1359: (match_operand:HI 2 "general_operand" "rmi")))] 1360: "" 1361: "mul.h %2,%0") 1362: 1363: ;; define_insn "mulhisi3" 1364: 1365: (define_insn "mulsi3" 1366: [(set (match_operand:SI 0 "general_operand" "=rm") 1367: (mult:SI (match_operand:SI 1 "general_operand" "%0") 1368: (match_operand:SI 2 "general_operand" "rmi")))] 1369: "" 1370: "mul.w %2,%0") 1371: 1372: (define_insn "muldf3" 1373: [(set (match_operand:DF 0 "general_operand" "=f") 1374: (mult:DF (match_operand:DF 1 "general_operand" "%0") 1375: (match_operand:DF 2 "general_operand" "fmG")))] 1376: "TARGET_FPU" 1377: "fmul.d %f2,%0") 1378: 1379: (define_insn "mulsf3" 1380: [(set (match_operand:SF 0 "general_operand" "=f") 1381: (mult:SF (match_operand:SF 1 "general_operand" "%0") 1382: (match_operand:SF 2 "general_operand" "fmG")))] 1383: "TARGET_FPU" 1384: "fmul.s %f2,%0") 1385: 1386: 1387: ;; divide instructions 1388: 1389: (define_insn "divqi3" 1390: [(set (match_operand:QI 0 "general_operand" "=rm") 1391: (div:QI (match_operand:QI 1 "general_operand" "0") 1392: (match_operand:QI 2 "general_operand" "rmi")))] 1393: "" 1394: "div.b %2,%0") 1395: 1396: (define_insn "divhi3" 1397: [(set (match_operand:HI 0 "general_operand" "=rm") 1398: (div:HI (match_operand:HI 1 "general_operand" "0") 1399: (match_operand:HI 2 "general_operand" "rmi")))] 1400: "" 1401: "div.h %2,%0") 1402: 1403: (define_insn "divhisi3" 1404: [(set (match_operand:HI 0 "general_operand" "=r") 1405: (div:HI (match_operand:SI 1 "general_operand" "0") 1406: (match_operand:HI 2 "general_operand" "rmi")))] 1407: "" 1408: "div %2.h,%0.w") 1409: 1410: (define_insn "divsi3" 1411: [(set (match_operand:SI 0 "general_operand" "=rm") 1412: (div:SI (match_operand:SI 1 "general_operand" "0") 1413: (match_operand:SI 2 "general_operand" "rmi")))] 1414: "" 1415: "div.w %2,%0") 1416: 1417: (define_insn "udivqi3" 1418: [(set (match_operand:QI 0 "general_operand" "=rm") 1419: (udiv:QI (match_operand:QI 1 "general_operand" "0") 1420: (match_operand:QI 2 "general_operand" "rmi")))] 1421: "" 1422: "divu.b %2,%0") 1423: 1424: (define_insn "udivhi3" 1425: [(set (match_operand:HI 0 "general_operand" "=rm") 1426: (udiv:HI (match_operand:HI 1 "general_operand" "0") 1427: (match_operand:HI 2 "general_operand" "rmi")))] 1428: "" 1429: "divu.h %2,%0") 1430: 1431: (define_insn "udivhisi3" 1432: [(set (match_operand:HI 0 "general_operand" "=r") 1433: (udiv:HI (match_operand:SI 1 "general_operand" "0") 1434: (match_operand:HI 2 "general_operand" "rmi")))] 1435: "" 1436: "divu %2.h,%0.w") 1437: 1438: (define_insn "udivsi3" 1439: [(set (match_operand:SI 0 "general_operand" "=rm") 1440: (udiv:SI (match_operand:SI 1 "general_operand" "0") 1441: (match_operand:SI 2 "general_operand" "rmi")))] 1442: "" 1443: "divu.w %2,%0") 1444: 1445: (define_insn "divdf3" 1446: [(set (match_operand:DF 0 "general_operand" "=f") 1447: (div:DF (match_operand:DF 1 "general_operand" "0") 1448: (match_operand:DF 2 "general_operand" "fmG")))] 1449: "TARGET_FPU" 1450: "fdiv.d %f2,%0") 1451: 1452: (define_insn "divsf3" 1453: [(set (match_operand:SF 0 "general_operand" "=f") 1454: (div:SF (match_operand:SF 1 "general_operand" "0") 1455: (match_operand:SF 2 "general_operand" "fmG")))] 1456: "TARGET_FPU" 1457: "fdiv.s %f2,%0") 1458: 1459: ;; Remainder instructions. 1460: 1461: (define_insn "modqi3" 1462: [(set (match_operand:QI 0 "general_operand" "=rm") 1463: (mod:QI (match_operand:QI 1 "general_operand" "0") 1464: (match_operand:QI 2 "general_operand" "rmi")))] 1465: "" 1466: "rem.b %2,%0") 1467: 1468: (define_insn "modhisi3" 1469: [(set (match_operand:HI 0 "general_operand" "=r") 1470: (mod:HI (match_operand:SI 1 "general_operand" "0") 1471: (match_operand:HI 2 "general_operand" "rmi")))] 1472: "" 1473: "rem.h %2,%0") 1474: 1475: (define_insn "umodqi3" 1476: [(set (match_operand:QI 0 "general_operand" "=rm") 1477: (umod:QI (match_operand:QI 1 "general_operand" "0") 1478: (match_operand:QI 2 "general_operand" "rmi")))] 1479: "" 1480: "remu.b %2,%0") 1481: 1482: (define_insn "umodhi3" 1483: [(set (match_operand:HI 0 "general_operand" "=rm") 1484: (umod:HI (match_operand:HI 1 "general_operand" "0") 1485: (match_operand:HI 2 "general_operand" "rmi")))] 1486: "" 1487: "remu.h %2,%0") 1488: 1489: (define_insn "umodhisi3" 1490: [(set (match_operand:HI 0 "general_operand" "=r") 1491: (umod:HI (match_operand:SI 1 "general_operand" "0") 1492: (match_operand:HI 2 "general_operand" "rmi")))] 1493: "" 1494: "remu %2.h,%0.w") 1495: 1496: ;; define_insn "divmodsi4" 1497: 1498: (define_insn "udivmodsi4" 1499: [(set (match_operand:SI 0 "general_operand" "=rm") 1500: (udiv:SI (match_operand:SI 1 "general_operand" "0") 1501: (match_operand:SI 2 "general_operand" "rmi"))) 1502: (set (match_operand:SI 3 "general_operand" "=r") 1503: (umod:SI (match_dup 1) (match_dup 2)))] 1504: "" 1505: "mov.w #0,%3;divx.w %2,%0,%3") 1506: 1507: ;; logical-and instructions 1508: 1509: (define_insn "andsi3" 1510: [(set (match_operand:SI 0 "general_operand" "=rm") 1511: (and:SI (match_operand:SI 1 "general_operand" "%0") 1512: (match_operand:SI 2 "general_operand" "rmi")))] 1513: "" 1514: "* 1515: { 1516: if (GET_CODE (operands[2]) == CONST_INT 1517: && (INTVAL (operands[2]) | 0xffff) == 0xffffffff 1518: && (GREG_P (operands[0]) 1519: || offsettable_memref_p (operands[0]))) 1520: 1521: { 1522: if (GET_CODE (operands[0]) != REG) 1523: operands[0] = adj_offsettable_operand (operands[0], 2); 1524: operands[2] = gen_rtx (CONST_INT, VOIDmode, 1525: INTVAL (operands[2]) & 0xffff); 1526: /* Do not delete a following tstl %0 insn; that would be incorrect. */ 1527: CC_STATUS_INIT; 1528: return \"and.h %2,%0\"; 1529: } 1530: return \"and.w %2,%0\"; 1531: }") 1532: 1533: (define_insn "andhi3" 1534: [(set (match_operand:HI 0 "general_operand" "=rm") 1535: (and:HI (match_operand:HI 1 "general_operand" "%0") 1536: (match_operand:HI 2 "general_operand" "rmi")))] 1537: "" 1538: "and.h %2,%0") 1539: 1540: (define_insn "andqi3" 1541: [(set (match_operand:QI 0 "general_operand" "=rm") 1542: (and:QI (match_operand:QI 1 "general_operand" "%0") 1543: (match_operand:QI 2 "general_operand" "rmi")))] 1544: "" 1545: "and.b %2,%0") 1546: 1547: (define_insn "" 1548: [(set (match_operand:SI 0 "general_operand" "=r") 1549: (and:SI (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")) 1550: (match_operand:SI 2 "general_operand" "0")))] 1551: "" 1552: "* 1553: { 1554: if (GET_CODE (operands[1]) == CONST_INT) 1555: return \"and %1,%0.w\"; 1556: return \"and %1.h,%0.w\"; 1557: }") 1558: 1559: 1560: (define_insn "" 1561: [(set (match_operand:SI 0 "general_operand" "=r") 1562: (and:SI (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")) 1563: (match_operand:SI 2 "general_operand" "0")))] 1564: "" 1565: "* 1566: { 1567: if (GET_CODE (operands[1]) == CONST_INT) 1568: return \"and %1,%0.w\"; 1569: return \"and %1.b,%0.w\"; 1570: }") 1571: 1572: ;; inclusive-or instructions 1573: 1574: (define_insn "iorsi3" 1575: [(set (match_operand:SI 0 "general_operand" "=rm") 1576: (ior:SI (match_operand:SI 1 "general_operand" "%0") 1577: (match_operand:SI 2 "general_operand" "rmi")))] 1578: "" 1579: "* 1580: { 1581: register int logval; 1582: if (GET_CODE (operands[2]) == CONST_INT 1583: && INTVAL (operands[2]) >> 16 == 0 1584: && (GREG_P (operands[0]) 1585: || offsettable_memref_p (operands[0]))) 1586: { 1587: if (GET_CODE (operands[0]) != REG) 1588: operands[0] = adj_offsettable_operand (operands[0], 2); 1589: /* Do not delete a following tstl %0 insn; that would be incorrect. */ 1590: CC_STATUS_INIT; 1591: return \"or.h %2,%0\"; 1592: } 1593: if (GET_CODE (operands[2]) == CONST_INT 1594: && (logval = exact_log2 (INTVAL (operands[2]))) >= 0 1595: && (GREG_P (operands[0]) 1596: || offsettable_memref_p (operands[0]))) 1597: { 1598: if (GREG_P (operands[0])) 1599: { 1600: if (logval < 7) 1601: { 1602: operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - logval); 1603: return \"bset.b %1,%0\"; 1604: } 1605: operands[1] = gen_rtx (CONST_INT, VOIDmode, 31 - logval); 1606: return \"bset.w %1,%0\"; 1607: } 1608: else 1609: { 1610: operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8)); 1611: operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - (logval % 8)); 1612: } 1613: return \"bset.b %1,%0\"; 1614: } 1615: return \"or.w %2,%0\"; 1616: }") 1617: 1618: (define_insn "iorhi3" 1619: [(set (match_operand:HI 0 "general_operand" "=rm") 1620: (ior:HI (match_operand:HI 1 "general_operand" "%0") 1621: (match_operand:HI 2 "general_operand" "rmi")))] 1622: "" 1623: "or.h %2,%0") 1624: 1625: (define_insn "iorqi3" 1626: [(set (match_operand:QI 0 "general_operand" "=rm") 1627: (ior:QI (match_operand:QI 1 "general_operand" "%0") 1628: (match_operand:QI 2 "general_operand" "rmi")))] 1629: "" 1630: "or.b %2,%0") 1631: 1632: ;; xor instructions 1633: 1634: (define_insn "xorsi3" 1635: [(set (match_operand:SI 0 "general_operand" "=rm") 1636: (xor:SI (match_operand:SI 1 "general_operand" "%0") 1637: (match_operand:SI 2 "general_operand" "rmi")))] 1638: "" 1639: "* 1640: { 1641: if (GET_CODE (operands[2]) == CONST_INT 1642: && INTVAL (operands[2]) >> 16 == 0 1643: && (offsettable_memref_p (operands[0]) || GREG_P (operands[0]))) 1644: { 1645: if (! GREG_P (operands[0])) 1646: operands[0] = adj_offsettable_operand (operands[0], 2); 1647: /* Do not delete a following tstl %0 insn; that would be incorrect. */ 1648: CC_STATUS_INIT; 1649: return \"xor.h %2,%0\"; 1650: } 1651: return \"xor.w %2,%0\"; 1652: }") 1653: 1654: (define_insn "xorhi3" 1655: [(set (match_operand:HI 0 "general_operand" "=rm") 1656: (xor:HI (match_operand:HI 1 "general_operand" "%0") 1657: (match_operand:HI 2 "general_operand" "rmi")))] 1658: "" 1659: "xor.h %2,%0") 1660: 1661: (define_insn "xorqi3" 1662: [(set (match_operand:QI 0 "general_operand" "=rm") 1663: (xor:QI (match_operand:QI 1 "general_operand" "%0") 1664: (match_operand:QI 2 "general_operand" "rmi")))] 1665: "" 1666: "xor.b %2,%0") 1667: 1668: ;; negation instructions 1669: 1670: (define_insn "negsi2" 1671: [(set (match_operand:SI 0 "general_operand" "=rm") 1672: (neg:SI (match_operand:SI 1 "general_operand" "0")))] 1673: "" 1674: "neg.w %0") 1675: 1676: (define_insn "neghi2" 1677: [(set (match_operand:HI 0 "general_operand" "=rm") 1678: (neg:HI (match_operand:HI 1 "general_operand" "0")))] 1679: "" 1680: "neg.h %0") 1681: 1682: (define_insn "negqi2" 1683: [(set (match_operand:QI 0 "general_operand" "=rm") 1684: (neg:QI (match_operand:QI 1 "general_operand" "0")))] 1685: "" 1686: "neg.b %0") 1687: 1688: (define_insn "negsf2" 1689: [(set (match_operand:SF 0 "general_operand" "=f") 1690: (neg:SF (match_operand:SF 1 "general_operand" "fmF")))] 1691: "TARGET_FPU" 1692: "fneg.s %f1,%0") 1693: 1694: 1695: (define_insn "negdf2" 1696: [(set (match_operand:DF 0 "general_operand" "=f") 1697: (neg:DF (match_operand:DF 1 "general_operand" "fmF")))] 1698: "TARGET_FPU" 1699: "fneg.d %f1,%0") 1700: 1701: 1702: ;; Absolute value instructions 1703: 1704: (define_insn "abssf2" 1705: [(set (match_operand:SF 0 "general_operand" "=f") 1706: (abs:SF (match_operand:SF 1 "general_operand" "fmF")))] 1707: "TARGET_FPU" 1708: "fabs.s %f1,%0") 1709: 1710: (define_insn "absdf2" 1711: [(set (match_operand:DF 0 "general_operand" "=f") 1712: (abs:DF (match_operand:DF 1 "general_operand" "fmF")))] 1713: "TARGET_FPU" 1714: "fabs.d %f1,%0") 1715: 1716: 1717: ;; one complement instructions 1718: 1719: (define_insn "one_cmplsi2" 1720: [(set (match_operand:SI 0 "general_operand" "=rm") 1721: (not:SI (match_operand:SI 1 "general_operand" "0")))] 1722: "" 1723: "not.w %0") 1724: 1725: (define_insn "one_cmplhi2" 1726: [(set (match_operand:HI 0 "general_operand" "=rm") 1727: (not:HI (match_operand:HI 1 "general_operand" "0")))] 1728: "" 1729: "not.h %0") 1730: 1731: (define_insn "one_cmplqi2" 1732: [(set (match_operand:QI 0 "general_operand" "=rm") 1733: (not:QI (match_operand:QI 1 "general_operand" "0")))] 1734: "" 1735: "not.b %0") 1736: 1737: ;; Optimized special case of shifting. 1738: ;; Must precede the general case. 1739: 1740: (define_insn "" 1741: [(set (match_operand:SI 0 "general_operand" "=r") 1742: (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m") 1743: (const_int 24)))] 1744: "GET_CODE (XEXP (operands[1], 0)) != POST_INC 1745: && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC" 1746: "mov:l %1.b,%0.w") 1747: 1748: (define_insn "" 1749: [(set (match_operand:SI 0 "general_operand" "=r") 1750: (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m") 1751: (const_int 24)))] 1752: "GET_CODE (XEXP (operands[1], 0)) != POST_INC 1753: && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC" 1754: "movu %1.b,%0.w") 1755: 1756: (define_insn "" 1757: [(set (cc0) (compare (match_operand:QI 0 "general_operand" "i") 1758: (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m") 1759: (const_int 24))))] 1760: "(GET_CODE (operands[0]) == CONST_INT 1761: && (INTVAL (operands[0]) & ~0xff) == 0)" 1762: "* 1763: { 1764: cc_status.flags |= CC_REVERSED; 1765: if (my_signed_comp (insn)) 1766: return \"cmp.b %0,%1\"; 1767: return \"cmpu.b %0,%1\"; 1768: }") 1769: 1770: (define_insn "" 1771: [(set (cc0) (compare (lshiftrt:SI (match_operand:SI 0 "memory_operand" "m") 1772: (const_int 24)) 1773: (match_operand:QI 1 "general_operand" "i")))] 1774: "(GET_CODE (operands[1]) == CONST_INT 1775: && (INTVAL (operands[1]) & ~0xff) == 0)" 1776: "* 1777: if (my_signed_comp (insn)) 1778: return \"cmp.b %1,%0\"; 1779: return \"cmpu.b %1,%0\"; 1780: ") 1781: 1782: (define_insn "" 1783: [(set (cc0) (compare (match_operand:QI 0 "general_operand" "i") 1784: (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m") 1785: (const_int 24))))] 1786: "(GET_CODE (operands[0]) == CONST_INT 1787: && ((INTVAL (operands[0]) + 0x80) & ~0xff) == 0)" 1788: "* 1789: cc_status.flags |= CC_REVERSED; 1790: if (my_signed_comp (insn)) 1791: return \"cmp.b %0,%1\"; 1792: return \"cmpu.b %0,%1\"; 1793: ") 1794: 1795: (define_insn "" 1796: [(set (cc0) (compare (ashiftrt:SI (match_operand:SI 0 "memory_operand" "m") 1797: (const_int 24)) 1798: (match_operand:QI 1 "general_operand" "i")))] 1799: "(GET_CODE (operands[1]) == CONST_INT 1800: && ((INTVAL (operands[1]) + 0x80) & ~0xff) == 0)" 1801: "* 1802: if (my_signed_comp (insn)) 1803: return \"cmp.b %1,%0\"; 1804: return \"cmpu.b %1,%0\"; 1805: ") 1806: 1807: ;; arithmetic shift instructions 1808: ;; We don't need the shift memory by 1 bit instruction 1809: 1810: (define_insn "ashlsi3" 1811: [(set (match_operand:SI 0 "general_operand" "=rm") 1812: (ashift:SI (match_operand:SI 1 "general_operand" "0") 1813: (match_operand:SI 2 "general_operand" "rmi")))] 1814: "" 1815: "sha.w %2,%0") 1816: 1817: (define_insn "ashlhi3" 1818: [(set (match_operand:HI 0 "general_operand" "=rm") 1819: (ashift:HI (match_operand:HI 1 "general_operand" "0") 1820: (match_operand:HI 2 "general_operand" "rmi")))] 1821: "" 1822: "sha.h %2,%0") 1823: 1824: (define_insn "ashlqi3" 1825: [(set (match_operand:QI 0 "general_operand" "=rm") 1826: (ashift:QI (match_operand:QI 1 "general_operand" "0") 1827: (match_operand:QI 2 "general_operand" "rmi")))] 1828: "" 1829: "sha.b %2,%0") 1830: 1831: ;; Arithmetic right shift on the Gmicro works by negating the shift count 1832: 1833: ;; ashiftrt -> ashift 1834: (define_expand "ashrsi3" 1835: [(set (match_operand:SI 0 "general_operand" "=rm") 1836: (ashift:SI (match_operand:SI 1 "general_operand" "0") 1837: (match_operand:SI 2 "general_operand" "rmi")))] 1838: "" 1839: "{ operands[2] = negate_rtx (SImode, operands[2]); }") 1840: 1841: ;; ashiftrt -> ashift 1842: (define_expand "ashrhi3" 1843: [(set (match_operand:HI 0 "general_operand" "=rm") 1844: (ashift:HI (match_operand:HI 1 "general_operand" "0") 1845: (match_operand:HI 2 "general_operand" "rmi")))] 1846: "" 1847: " { operands[2] = negate_rtx (HImode, operands[2]); }") 1848: 1849: ;; ashiftrt -> ashift 1850: (define_expand "ashrqi3" 1851: [(set (match_operand:QI 0 "general_operand" "=rm") 1852: (ashift:QI (match_operand:QI 1 "general_operand" "0") 1853: (match_operand:QI 2 "general_operand" "rmi")))] 1854: "" 1855: " { operands[2] = negate_rtx (QImode, operands[2]); }") 1856: 1857: ;; logical shift instructions 1858: 1.1.1.2 ! root 1859: ;; Logical right shift on the gmicro works by negating the shift count, ! 1860: ;; then emitting a right shift with the shift count negated. This means ! 1861: ;; that all actual shift counts in the RTL will be positive. This ! 1862: ;; prevents converting shifts to ZERO_EXTRACTs with negative positions, ! 1863: ;; which isn't valid. 1.1 root 1864: 1.1.1.2 ! root 1865: (define_expand "lshrsi3" ! 1866: [(set (match_operand:SI 0 "general_operand" "=g") ! 1867: (lshiftrt:SI (match_operand:SI 1 "general_operand" "g") ! 1868: (match_operand:SI 2 "general_operand" "g")))] 1.1 root 1869: "" 1.1.1.2 ! root 1870: " ! 1871: { ! 1872: if (GET_CODE (operands[2]) != CONST_INT) ! 1873: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); ! 1874: }") 1.1 root 1875: 1.1.1.2 ! root 1876: (define_insn "" ! 1877: [(set (match_operand:SI 0 "general_operand" "=rm") ! 1878: (lshiftrt:SI (match_operand:SI 1 "general_operand" "0") ! 1879: (match_operand:SI 2 "const_int_operand" "n")))] 1.1 root 1880: "" 1.1.1.2 ! root 1881: "shl.w %n2,%0") 1.1 root 1882: 1.1.1.2 ! root 1883: (define_insn "" 1.1 root 1884: [(set (match_operand:SI 0 "general_operand" "=rm") 1.1.1.2 ! root 1885: (lshiftrt:SI (match_operand:SI 1 "general_operand" "0") ! 1886: (neg:SI (match_operand:SI 2 "general_operand" "rm"))))] 1.1 root 1887: "" 1.1.1.2 ! root 1888: "shl.w %2,%0") 1.1 root 1889: 1890: (define_expand "lshrhi3" 1.1.1.2 ! root 1891: [(set (match_operand:HI 0 "general_operand" "=g") ! 1892: (lshiftrt:HI (match_operand:HI 1 "general_operand" "g") ! 1893: (match_operand:HI 2 "general_operand" "g")))] ! 1894: "" ! 1895: " ! 1896: { ! 1897: if (GET_CODE (operands[2]) != CONST_INT) ! 1898: operands[2] = gen_rtx (NEG, HImode, negate_rtx (HImode, operands[2])); ! 1899: }") ! 1900: ! 1901: (define_insn "" 1.1 root 1902: [(set (match_operand:HI 0 "general_operand" "=rm") 1.1.1.2 ! root 1903: (lshiftrt:HI (match_operand:HI 1 "general_operand" "0") ! 1904: (match_operand:HI 2 "const_int_operand" "n")))] 1.1 root 1905: "" 1.1.1.2 ! root 1906: "shl.h %n2,%0") ! 1907: ! 1908: (define_insn "" ! 1909: [(set (match_operand:HI 0 "general_operand" "=rm") ! 1910: (lshiftrt:HI (match_operand:HI 1 "general_operand" "0") ! 1911: (neg:HI (match_operand:HI 2 "general_operand" "rm"))))] ! 1912: "" ! 1913: "shl.h %2,%0") 1.1 root 1914: 1915: (define_expand "lshrqi3" 1.1.1.2 ! root 1916: [(set (match_operand:QI 0 "general_operand" "=g") ! 1917: (lshiftrt:QI (match_operand:QI 1 "general_operand" "g") ! 1918: (match_operand:QI 2 "general_operand" "g")))] ! 1919: "" ! 1920: " ! 1921: { ! 1922: if (GET_CODE (operands[2]) != CONST_INT) ! 1923: operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2])); ! 1924: }") ! 1925: ! 1926: (define_insn "" 1.1 root 1927: [(set (match_operand:QI 0 "general_operand" "=rm") 1.1.1.2 ! root 1928: (lshiftrt:QI (match_operand:QI 1 "general_operand" "0") ! 1929: (match_operand:QI 2 "const_int_operand" "n")))] 1.1 root 1930: "" 1.1.1.2 ! root 1931: "shl.b %n2,%0") ! 1932: ! 1933: (define_insn "" ! 1934: [(set (match_operand:QI 0 "general_operand" "=rm") ! 1935: (lshiftrt:QI (match_operand:QI 1 "general_operand" "0") ! 1936: (neg:QI (match_operand:QI 2 "general_operand" "rm"))))] ! 1937: "" ! 1938: "shl.b %2,%0") 1.1 root 1939: 1940: ;; rotate instructions 1941: 1942: (define_insn "rotlsi3" 1943: [(set (match_operand:SI 0 "general_operand" "=rm") 1944: (rotate:SI (match_operand:SI 1 "general_operand" "0") 1945: (match_operand:SI 2 "general_operand" "rmi")))] 1946: "" 1947: "rol.w %2,%0") 1948: 1949: (define_insn "rotlhi3" 1950: [(set (match_operand:HI 0 "general_operand" "=rm") 1951: (rotate:HI (match_operand:HI 1 "general_operand" "0") 1952: (match_operand:HI 2 "general_operand" "rmi")))] 1953: "" 1954: "rol.h %2,%0") 1955: 1956: (define_insn "rotlqi3" 1957: [(set (match_operand:QI 0 "general_operand" "=rm") 1958: (rotate:QI (match_operand:QI 1 "general_operand" "0") 1959: (match_operand:QI 2 "general_operand" "rmi")))] 1960: "" 1961: "rol.b %2,%0") 1962: 1963: (define_expand "rotrsi3" 1964: [(set (match_operand:SI 0 "general_operand" "=rm") 1965: (rotatert:SI (match_operand:SI 1 "general_operand" "0") 1966: (match_operand:SI 2 "general_operand" "rmi")))] 1967: "" 1968: " { operands[2] = negate_rtx (SImode, operands[2]); }") 1969: 1970: (define_expand "rotrhi3" 1971: [(set (match_operand:HI 0 "general_operand" "=rm") 1972: (rotatert:HI (match_operand:HI 1 "general_operand" "0") 1973: (match_operand:HI 2 "general_operand" "rmi")))] 1974: "" 1975: " { operands[2] = negate_rtx (HImode, operands[2]); }") 1976: 1977: (define_expand "rotrqi3" 1978: [(set (match_operand:QI 0 "general_operand" "=rm") 1979: (rotatert:QI (match_operand:QI 1 "general_operand" "0") 1980: (match_operand:QI 2 "general_operand" "rmi")))] 1981: "" 1982: " { operands[2] = negate_rtx (QImode, operands[2]); }") 1983: 1984: ;; Special cases of bit-field insns which we should 1985: ;; recognize in preference to the general case. 1986: ;; These handle aligned 8-bit and 16-bit fields, 1987: ;; which can usually be done with move instructions. 1988: 1989: ;; Should I add mode_dependent_address_p ???? 1990: 1991: (define_insn "" 1992: [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+rm") 1993: (match_operand:SI 1 "immediate_operand" "i") 1994: (match_operand:SI 2 "immediate_operand" "i")) 1995: (match_operand:SI 3 "general_operand" "rm"))] 1996: "TARGET_BITFIELD 1997: && GET_CODE (operands[1]) == CONST_INT 1998: && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16) 1999: && GET_CODE (operands[2]) == CONST_INT 2000: && INTVAL (operands[2]) % INTVAL (operands[1]) == 0 2001: && (GET_CODE (operands[0]) != REG 2002: || ( INTVAL (operands[1]) + INTVAL (operands[2]) == 32))" 2003: "* 2004: { 2005: if (GET_CODE (operands[3]) == MEM) 2006: operands[3] = adj_offsettable_operand (operands[3], 2007: (32 - INTVAL (operands[1])) / 8); 2008: 2009: if (GET_CODE (operands[0]) == REG) 2010: { 2011: if (INTVAL (operands[1]) == 8) 2012: return \"movu %3.b,%0.w\"; 2013: return \"movu %3.h,%0.w\"; 2014: } 2015: else 2016: { 2017: operands[0] 2018: = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8); 2019: if (INTVAL (operands[1]) == 8) 2020: return \"mov.b %3,%0\"; 2021: return \"mov.h %3,%0\"; 2022: } 2023: }") 2024: 2025: (define_insn "" 2026: [(set (match_operand:SI 0 "general_operand" "=&r") 2027: (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "rm") 2028: (match_operand:SI 2 "immediate_operand" "i") 2029: (match_operand:SI 3 "immediate_operand" "i")))] 2030: "TARGET_BITFIELD 2031: && GET_CODE (operands[2]) == CONST_INT 2032: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 2033: && GET_CODE (operands[3]) == CONST_INT 2034: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0" 2035: "* 2036: { 2037: if (!REG_P (operands[1])) 2038: operands[1] 2039: = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); 2040: 2041: if (REG_P (operands[0])) 2042: { 2043: if (REG_P (operands[1])) 2044: { 2045: if (INTVAL (operands[2]) == 8) 2046: { /* width == 8 */ 2047: switch (INTVAL (operands[3])) 2048: { 2049: case 0: 2050: return \"mov.w %1,%0;shl.w #-24,%0\"; 2051: break; 2052: case 8: 2053: return \"mov.w %1,%0;shl.w #8,%0;shl.w #-24,%0\"; 2054: break; 2055: case 16: 2056: return \"mov.w %1,%0;shl.w #16,%0;shl.w #-24,%0\"; 2057: break; 2058: case 24: 2059: return \"movu %1.b,%0.w\"; 2060: break; 2061: default: 2062: myabort (2); 2063: } 2064: } 2065: else 2066: { 2067: switch (INTVAL (operands[3])) 2068: { 2069: case 0: 2070: return \"mov.w %1,%0;shl.w #-16,%0\"; 2071: break; 2072: case 16: 2073: return \"movu %1.h,%0.w\"; 2074: break; 2075: default: 2076: myabort (3); 2077: } 2078: } 2079: } 2080: else 2081: { 2082: if (INTVAL (operands[2]) == 8) 2083: return \"movu %1.h,%0.w\"; 2084: else 2085: return \"movu %1.b,%0.w\"; 2086: } 2087: } 2088: else 2089: { /* op[0] == MEM */ 2090: if (INTVAL (operands[2]) == 8) 2091: return \"movu %1.b,%0.w\"; 2092: return \"movu %1.h,%0.w\"; 2093: } 2094: }") 2095: 2096: (define_insn "" 2097: [(set (match_operand:SI 0 "general_operand" "=r") 2098: (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro") 2099: (match_operand:SI 2 "immediate_operand" "i") 2100: (match_operand:SI 3 "immediate_operand" "i")))] 2101: "TARGET_BITFIELD 2102: && GET_CODE (operands[2]) == CONST_INT 2103: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 2104: && GET_CODE (operands[3]) == CONST_INT 2105: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0" 2106: "* 2107: { 2108: if (!REG_P (operands[1])) 2109: operands[1] 2110: = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); 2111: 2112: if (REG_P (operands[0])) 2113: { 2114: if (REG_P (operands[1])) 2115: { 2116: if (INTVAL (operands[2]) == 8) 2117: { /* width == 8 */ 2118: switch (INTVAL (operands[3])) 2119: { 2120: case 0: 2121: return \"mov.w %1,%0;sha.w #-24,%0\"; 2122: break; 2123: case 8: 2124: return \"mov.w %1,%0;shl.w #8,%0;sha.w #-24,%0\"; 2125: break; 2126: case 16: 2127: return \"mov.w %1,%0;shl.w #16,%0;sha.w #-24,%0\"; 2128: break; 2129: case 24: 2130: return \"mov %1.b,%0.w\"; 2131: break; 2132: default: 2133: myabort (4); 2134: } 2135: } 2136: else 2137: { 2138: switch (INTVAL (operands[3])) 2139: { 2140: case 0: 2141: return \"mov.w %1,%0;sha.w #-16,%0\"; 2142: break; 2143: case 16: 2144: return \"mov %1.h,%0.w\"; 2145: break; 2146: default: 2147: myabort (5); 2148: } 2149: } 2150: } 2151: else 2152: { 2153: if (INTVAL (operands[2]) == 8) 2154: return \"mov %1.h,%0.w\"; 2155: else 2156: return \"mov %1.b,%0.w\"; 2157: } 2158: } 2159: else 2160: { /* op[0] == MEM */ 2161: if (INTVAL (operands[2]) == 8) 2162: return \"mov %1.b,%0.w\"; 2163: return \"mov %1.h,%0.w\"; 2164: } 2165: }") 2166: 2167: ;; Bit field instructions, general cases. 2168: ;; "o,d" constraint causes a nonoffsettable memref to match the "o" 2169: ;; so that its address is reloaded. 2170: 2171: ;; extv dest:SI src(:QI/:SI) width:SI pos:SI 2172: ;; r.w m r.w/# rmi 2173: ;; %0 %1 %2 %3 2174: 2175: (define_insn "extv" 2176: [(set (match_operand:SI 0 "general_operand" "=r") 2177: (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "m") 2178: (match_operand:SI 2 "general_operand" "ri") 2179: (match_operand:SI 3 "general_operand" "rmi")))] 2180: "TARGET_BITFIELD" 2181: "bfext %3,%2,%1,%0") 2182: 2183: 2184: (define_insn "extzv" 2185: [(set (match_operand:SI 0 "general_operand" "=r") 2186: (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "m") 2187: (match_operand:SI 2 "general_operand" "ri") 2188: (match_operand:SI 3 "general_operand" "rmi")))] 2189: "TARGET_BITFIELD" 2190: "bfextu %3,%2,%1,%0") 2191: 2192: ;; There is no insn on the Gmicro to NOT/SET/CLR bitfield. 2193: 2194: 2195: ;; insv dest(BF):QI/SI width:SI pos:SI src:SI 2196: ;; m r.w rmi r.w/i 2197: ;; 0 1 2 3 2198: 2199: 2200: (define_insn "insv" 2201: [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+m,m") 2202: (match_operand:SI 1 "general_operand" "r,i") 2203: (match_operand:SI 2 "general_operand" "rmi,i")) 2204: (match_operand:SI 3 "general_operand" "ri,ri"))] 2205: "TARGET_BITFIELD" 2206: "bfinsu %3,%2,%1,%0") 2207: ;;; bfins/bfinsu ???????? 2208: 2209: ;; == == == == == == == == == == == == == 2210: 2211: ;; Now recognize bit field insns that operate on registers 2212: ;; (or at least were intended to do so). 2213: 2214: ;; On the Gmicro/300, 2215: ;; bitfield instructions are not applicable to registers ;-< 2216: ;; But I write the register cases, because without them the gcc 2217: ;; seems to use "and" instruction with some other instructions 2218: ;; instead of using a shift instruction. 2219: ;; It is because on many processors shift instructions are slower. 2220: ;; On the Gmicro/300 which has a barrel shifter, 2221: ;; it is faster to use a shift instruction. 2222: ;; 2223: ;; Restricts width and offset to be immediates. 2224: ;; 2225: (define_insn "" 2226: [(set (match_operand:SI 0 "general_operand" "=r") 2227: (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "r") 2228: (match_operand:SI 2 "immediate_operand" "i") 2229: (match_operand:SI 3 "immediate_operand" "i")))] 2230: "TARGET_BITFIELD" 2231: "* 2232: { 2233: if (REGNO (operands[0]) != REGNO (operands[1])) 2234: output_asm_insn (\"mov.w %1,%0\", operands); 2235: if (INTVAL (operands[3]) != 0) 2236: output_asm_insn (\"shl.w %3,%0\", operands); 2237: operands[2] = gen_rtx (CONST_INT, VOIDmode, -(32 - INTVAL (operands[2]))); 2238: return \"sha.w %3,%0\"; 2239: }") 2240: 2241: 2242: (define_insn "" 2243: [(set (match_operand:SI 0 "general_operand" "=r") 2244: (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "r") 2245: (match_operand:SI 2 "immediate_operand" "i") 2246: (match_operand:SI 3 "immediate_operand" "i")))] 2247: "TARGET_BITFIELD" 2248: "* 2249: { 2250: if (REGNO (operands[0]) != REGNO (operands[1])) 2251: output_asm_insn (\"mov.w %1,%0\", operands); 2252: if (INTVAL (operands[3]) != 0) 2253: output_asm_insn (\"shl.w %3,%0\", operands); 2254: operands[2] = gen_rtx (CONST_INT, VOIDmode, -(32 - INTVAL (operands[2]))); 2255: return \"shl.w %3,%0\"; 2256: }") 2257: 2258: 2259: ;; There are more descriptions for m68k, but not yet for the Gmicro. 2260: ;; 2261: 2262: ;; Basic conditional jump instructions. 2263: 2264: 2265: (define_insn "beq" 2266: [(set (pc) 2267: (if_then_else (eq (cc0) 2268: (const_int 0)) 2269: (label_ref (match_operand 0 "" "")) 2270: (pc)))] 2271: "" 2272: "* 2273: { 2274: OUTPUT_JUMP (\"beq %b0\", \"fbeq %b0\", \"beq %b0\"); 2275: }") 2276: 2277: (define_insn "bne" 2278: [(set (pc) 2279: (if_then_else (ne (cc0) 2280: (const_int 0)) 2281: (label_ref (match_operand 0 "" "")) 2282: (pc)))] 2283: "" 2284: "* 2285: { 2286: OUTPUT_JUMP (\"bne %b0\", \"fbne %b0\", \"bne %b0\"); 2287: }") 2288: 2289: (define_insn "bgt" 2290: [(set (pc) 2291: (if_then_else (gt (cc0) 2292: (const_int 0)) 2293: (label_ref (match_operand 0 "" "")) 2294: (pc)))] 2295: "" 2296: "* 2297: OUTPUT_JUMP (\"bgt %b0\", \"fbgt %b0\", 0); 2298: ") 2299: 2300: (define_insn "bgtu" 2301: [(set (pc) 2302: (if_then_else (gtu (cc0) 2303: (const_int 0)) 2304: (label_ref (match_operand 0 "" "")) 2305: (pc)))] 2306: "" 2307: "bgt %b0") 2308: 2309: (define_insn "blt" 2310: [(set (pc) 2311: (if_then_else (lt (cc0) 2312: (const_int 0)) 2313: (label_ref (match_operand 0 "" "")) 2314: (pc)))] 2315: "" 2316: "* 2317: OUTPUT_JUMP (\"blt %b0\", \"fblt %b0\", \"bms %b0\"); 2318: ") 2319: 2320: ;; bms ????? 2321: ;; 2322: 2323: (define_insn "bltu" 2324: [(set (pc) 2325: (if_then_else (ltu (cc0) 2326: (const_int 0)) 2327: (label_ref (match_operand 0 "" "")) 2328: (pc)))] 2329: "" 2330: "blt %b0") 2331: 2332: (define_insn "bge" 2333: [(set (pc) 2334: (if_then_else (ge (cc0) 2335: (const_int 0)) 2336: (label_ref (match_operand 0 "" "")) 2337: (pc)))] 2338: "" 2339: "* 2340: OUTPUT_JUMP (\"bge %b0\", \"fbge %b0\", \"bmc %b0\"); 2341: ") 2342: 2343: ;; bmc ?? 2344: 2345: (define_insn "bgeu" 2346: [(set (pc) 2347: (if_then_else (geu (cc0) 2348: (const_int 0)) 2349: (label_ref (match_operand 0 "" "")) 2350: (pc)))] 2351: "" 2352: "bge %b0") 2353: 2354: (define_insn "ble" 2355: [(set (pc) 2356: (if_then_else (le (cc0) 2357: (const_int 0)) 2358: (label_ref (match_operand 0 "" "")) 2359: (pc)))] 2360: "" 2361: "ble %b0") 2362: 2363: (define_insn "bleu" 2364: [(set (pc) 2365: (if_then_else (leu (cc0) 2366: (const_int 0)) 2367: (label_ref (match_operand 0 "" "")) 2368: (pc)))] 2369: "" 2370: "ble %b0") 2371: 2372: ;; Negated conditional jump instructions. 2373: 2374: (define_insn "" 2375: [(set (pc) 2376: (if_then_else (eq (cc0) 2377: (const_int 0)) 2378: (pc) 2379: (label_ref (match_operand 0 "" ""))))] 2380: "" 2381: "* 2382: { 2383: OUTPUT_JUMP (\"bne %b0\", \"fbne %b0\", \"bne %b0\"); 2384: }") 2385: 2386: (define_insn "" 2387: [(set (pc) 2388: (if_then_else (ne (cc0) 2389: (const_int 0)) 2390: (pc) 2391: (label_ref (match_operand 0 "" ""))))] 2392: "" 2393: "* 2394: { 2395: OUTPUT_JUMP (\"beq %b0\", \"fbeq %b0\", \"beq %b0\"); 2396: }") 2397: 2398: (define_insn "" 2399: [(set (pc) 2400: (if_then_else (gt (cc0) 2401: (const_int 0)) 2402: (pc) 2403: (label_ref (match_operand 0 "" ""))))] 2404: "" 2405: "* 2406: OUTPUT_JUMP (\"ble %b0\", \"fbngt %b0\", 0); 2407: ") 2408: ;; fbngt ??? 2409: 2410: (define_insn "" 2411: [(set (pc) 2412: (if_then_else (gtu (cc0) 2413: (const_int 0)) 2414: (pc) 2415: (label_ref (match_operand 0 "" ""))))] 2416: "" 2417: "ble %b0") 2418: 2419: (define_insn "" 2420: [(set (pc) 2421: (if_then_else (lt (cc0) 2422: (const_int 0)) 2423: (pc) 2424: (label_ref (match_operand 0 "" ""))))] 2425: "" 2426: "* 2427: OUTPUT_JUMP (\"bge %b0\", \"fbnlt %b0\", \"jbmc %b0\"); 2428: ") 2429: 2430: (define_insn "" 2431: [(set (pc) 2432: (if_then_else (ltu (cc0) 2433: (const_int 0)) 2434: (pc) 2435: (label_ref (match_operand 0 "" ""))))] 2436: "" 2437: "blt %b0") 2438: 2439: (define_insn "" 2440: [(set (pc) 2441: (if_then_else (ge (cc0) 2442: (const_int 0)) 2443: (pc) 2444: (label_ref (match_operand 0 "" ""))))] 2445: "" 2446: "* 2447: OUTPUT_JUMP (\"blt %b0\", \"fbnge %b0\", \"jbms %b0\"); 2448: ") 2449: 2450: (define_insn "" 2451: [(set (pc) 2452: (if_then_else (geu (cc0) 2453: (const_int 0)) 2454: (pc) 2455: (label_ref (match_operand 0 "" ""))))] 2456: "" 2457: "blt %b0") 2458: ;; ???? 2459: 2460: (define_insn "" 2461: [(set (pc) 2462: (if_then_else (le (cc0) 2463: (const_int 0)) 2464: (pc) 2465: (label_ref (match_operand 0 "" ""))))] 2466: "" 2467: "* 2468: OUTPUT_JUMP (\"bgt %b0\", \"fbnle %b0\", 0); 2469: ") 2470: 2471: (define_insn "" 2472: [(set (pc) 2473: (if_then_else (leu (cc0) 2474: (const_int 0)) 2475: (pc) 2476: (label_ref (match_operand 0 "" ""))))] 2477: "" 2478: "bgt %b0") 2479: 2480: ;; Unconditional and other jump instructions 2481: (define_insn "jump" 2482: [(set (pc) 2483: (label_ref (match_operand 0 "" "")))] 2484: "" 2485: "bra %b0") 2486: 2487: (define_insn "tablejump" 2488: [(set (pc) 2489: (plus:SI (pc) (match_operand:SI 0 "general_operand" "r"))) 2490: (use (label_ref (match_operand 1 "" "")))] 2491: "" 2492: "jmp @(pc:b,4:4,%0)") 2493: 2494: ;; 2495: ;; Should Add code for "ACB", "SCB". !!! ???? 2496: ;; See m68k.h (dbra) 2497: ;; 2498: 2499: ;; Call subroutine with no return value. 2500: (define_insn "call" 2501: [(call (match_operand:QI 0 "general_operand" "m") 2502: (match_operand:SI 1 "general_operand" "rmi"))] 2503: ;; Operand 1 not really used on the Gmicro. 2504: 2505: "" 2506: "* 2507: { 2508: if (GET_CODE (operands[0]) == MEM 2509: && GET_CODE (XEXP (operands[0],0)) == SYMBOL_REF) 2510: return \"bsr %b0\"; 2511: return \"jsr %0\"; 2512: }") 2513: 2514: ;; Call subroutine, returning value in operand 0 2515: ;; (which must be a hard register). 2516: (define_insn "call_value" 2517: [(set (match_operand 0 "" "=rf") 2518: (call (match_operand:QI 1 "general_operand" "m") 2519: (match_operand:SI 2 "general_operand" "rmi")))] 2520: ;; Operand 2 not really used on the Gmicro. 2521: "" 2522: "* 2523: { 2524: if (GET_CODE (operands[1]) == MEM 2525: && GET_CODE (XEXP (operands[1],0)) == SYMBOL_REF) 2526: return \"bsr %b1\"; 2527: return \"jsr %1\"; 2528: }") 2529: 2530: ;; Call subroutine returning any type. 2531: 2532: (define_expand "untyped_call" 2533: [(parallel [(call (match_operand 0 "" "") 2534: (const_int 0)) 2535: (match_operand 1 "" "") 2536: (match_operand 2 "" "")])] 2537: "" 2538: " 2539: { 2540: int i; 2541: 2542: emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); 2543: 2544: for (i = 0; i < XVECLEN (operands[2], 0); i++) 2545: { 2546: rtx set = XVECEXP (operands[2], 0, i); 2547: emit_move_insn (SET_DEST (set), SET_SRC (set)); 2548: } 2549: 2550: /* The optimizer does not know that the call sets the function value 2551: registers we stored in the result block. We avoid problems by 2552: claiming that all hard registers are used and clobbered at this 2553: point. */ 2554: emit_insn (gen_blockage ()); 2555: 2556: DONE; 2557: }") 2558: 2559: ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 2560: ;; all of memory. This blocks insns from being moved across this point. 2561: 2562: (define_insn "blockage" 2563: [(unspec_volatile [(const_int 0)] 0)] 2564: "" 2565: "") 2566: 2567: (define_insn "nop" 2568: [(const_int 0)] 2569: "" 2570: "nop") 2571: 2572: ;; Turned off because the general move-an-address pattern handles it. 2573: ;; 2574: ;; Thus goes after the move instructions 2575: ;; because the move instructions are better (require no spilling) 2576: ;; when they can apply. 2577: ;; After add/sub now !! 2578: 2579: ;(define_insn "pushasi" 2580: ; [(set (match_operand:SI 0 "push_operand" "=m") 2581: ; (match_operand:SI 1 "address_operand" "p"))] 2582: ; "" 2583: ; "* 2584: ;{ 2585: ; if (GET_CODE (operands[1]) == CONST_INT) 2586: ; return push_imm_word (INTVAL (operands[1]), operands[0]); 2587: ; if (CONSTANT_P (operands[1])) 2588: ; return \"mov.w %1,%-\"; 2589: ; if (GET_CODE (operands[1]) == REG) 2590: ; return \"mov.w %1,%-\"; 2591: ; else if (GET_CODE (operands[1]) == MEM) 2592: ; { 2593: ; return \"mov.w %1,%-\"; 2594: ; } 2595: ; else 2596: ; return \"mova.w %p1,%-\"; 2597: ;}") 2598: 2599: ;; This should not be used unless the add/sub insns can't be. 2600: 2601: /* mova.[whq] 89.08.11 for test M.Yuhara */ 2602: ;(define_insn "" 2603: ; [(set (match_operand:SI 0 "general_operand" "=rm") 2604: ; (address (match_operand:SI 1 "address_operand" "p")))] 2605: ; "" 2606: ; "* 2607: ;{ 2608: ; if (GET_CODE (operands[1]) == CONST_INT) 2609: ; return mov_imm_word (INTVAL (operands[1]), operands[0]); 2610: ; if (CONSTANT_P (operands[1])) 2611: ; return \"mov.w %1,%0\"; 2612: ; if (GET_CODE (operands[1]) == REG) 2613: ; return \"mov.w %1,%0\"; 2614: ; else if (GET_CODE (operands[1]) == MEM) { 2615: ; operands[1] = XEXP (operands[1],0); 2616: ; return \"mov.w %1,%0\"; 2617: ; } 2618: ; else 2619: ; return \"mova.w %p1,%0\"; 2620: ;}") 2621: 2622: 2623: (define_insn "" 2624: [(set (match_operand:SI 0 "general_operand" "=rm") 2625: (address (match_operand:HI 1 "address_operand" "")))] 2626: "" 2627: "* 2628: { 2629: if (GET_CODE (operands[1]) == CONST_INT) 2630: return mov_imm_word (INTVAL (operands[1]), operands[0]); 2631: if (CONSTANT_P (operands[1])) 2632: return \"mov.w %1,%0\"; 2633: if (GET_CODE (operands[1]) == REG) 2634: return \"mov.w %1,%0\"; 2635: else if (GET_CODE (operands[1]) == MEM) 2636: { 2637: operands[1] = XEXP (operands[1],0); 2638: return \"mov.w %1,%0\"; /* OK ? */ 2639: } 2640: else 2641: return \"mova.w %p1,%0\"; 2642: }") 2643: 2644: ;(define_insn "" 2645: ; [(set (match_operand:SI 0 "general_operand" "=rm") 2646: ; (match_operand:QI 1 "address_operand" "p"))] 2647: ; "" 2648: ; "* 2649: ;{ 2650: ; if (push_operand (operands[0], SImode)) 2651: ; return \"mova %1,%-\"; 2652: ; return \"mova %1,%0\"; 2653: ;}") 2654: 2655: ;(define_insn "" 2656: ; [(set (match_operand:SI 0 "general_operand" "=rm") 2657: ; (match_operand:QI 1 "address_operand" "p"))] 2658: ; "" 2659: ; "* 2660: ;{ 2661: ; if (CONSTANT_P (operands[1])) 2662: ; return \"mov.w %1,%0\"; 2663: ; else if (GET_CODE (operands[1]) == REG) 2664: ; return \"mov.w %1,%0\"; 2665: ; else if (GET_CODE (operands[1]) == MEM) 2666: ; { 2667: ; operands[1] = XEXP (operands[1],0); 2668: ; return \"mov.w %1,%0 ; OK?\"; 2669: ; } 2670: ; else if (GET_CODE (operands[0]) == REG 2671: ; && GET_CODE (operands[1]) == PLUS) 2672: ; { 2673: ; rtx xreg, xdisp; 2674: ; 2675: ; if (GET_CODE (XEXP (operands[1], 0)) == REG 2676: ; && REGNO (XEXP (operands[1], 0)) == REGNO (operands[0])) 2677: ; { 2678: ; xreg = XEXP (operands[1], 0); 2679: ; xdisp = XEXP (operands[1],1); 2680: ; } 2681: ; else 2682: ; { 2683: ; xreg = XEXP (operands[1], 1); 2684: ; xdisp = XEXP (operands[1],0); 2685: ; } 2686: ; 2687: ; if (GET_CODE (xreg) == REG 2688: ; && REGNO (xreg) == REGNO (operands[0]) 2689: ; && (CONSTANT_P (xdisp) || GET_CODE (xdisp) == REG)) 2690: ; { 2691: ; operands[1] = xdisp; 2692: ; if (CONSTANT_P (xdisp)) 2693: ; return add_imm_word (INTVAL (xdisp), xreg, &operands[1]); 2694: ; else 2695: ; return \"add.w %1,%0\"; 2696: ; } 2697: ; } 2698: ; return \"mova.w %p1,%0\"; 2699: ;}") 2700: 2701: ;; This is the first machine-dependent peephole optimization. 2702: ;; It is useful when a floating value is returned from a function call 2703: ;; and then is moved into an FP register. 2704: ;; But it is mainly intended to test the support for these optimizations. 2705: 2706: (define_peephole 2707: [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4))) 2708: (set (match_operand:DF 0 "register_operand" "=f") 2709: (match_operand:DF 1 "register_operand" "r"))] 2710: "FPU_REG_P (operands[0]) && ! FPU_REG_P (operands[1])" 2711: "* 2712: { 2713: rtx xoperands[2]; 2714: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 2715: output_asm_insn (\"mov.w %1,@sp\", xoperands); 2716: output_asm_insn (\"mov.w %1,%-\", operands); 2717: return \"fmov.d %+,%0\"; 2718: } 2719: ")
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