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1.1.1.2 root 1: ;;- Machine description for GNU compiler, Fujitsu Gmicro Version
2: ;; Copyright (C) 1990, 1994 Free Software Foundation, Inc.
3: ;; Contributed by M.Yuhara, Fujitsu Laboratories LTD.
1.1 root 4:
5: ;; This file is part of GNU CC.
6:
7: ;; GNU CC is free software; you can redistribute it and/or modify
8: ;; it under the terms of the GNU General Public License as published by
9: ;; the Free Software Foundation; either version 2, or (at your option)
10: ;; any later version.
11:
12: ;; GNU CC is distributed in the hope that it will be useful,
13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: ;; GNU General Public License for more details.
16: ;; Among other things, the copyright
17: ;; notice and this notice must be preserved on all copies.
18:
19:
20: ;; You should have received a copy of the GNU General Public License
21: ;; along with GNU CC; see the file COPYING. If not, write to
1.1.1.3 ! root 22: ;; the Free Software Foundation, 59 Temple Place - Suite 330,
! 23: ;; Boston, MA 02111-1307, USA.
1.1 root 24:
25:
26: ;;- instruction definitions
27:
28: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29:
30: ;;- When naming insn's (operand 0 of define_insn) be careful about using
31: ;;- names from other targets machine descriptions.
32:
33: ;;- cpp macro #define NOTICE_UPDATE_CC is essentially a no-op for the
34: ;;- gmicro; no compares are eliminated.
35:
36: ;;- The original structure of this file is m68k.md.
37:
38: ;; ??? Work to be done:
39: ;; Add patterns for ACB and SCB instructions.
40: ;; Add define_insn patterns to recognize the insns that extend a byte
41: ;; to a word and add it into a word, etc.
42:
43: ;;- Some of these insn's are composites of several Gmicro op codes.
44: ;;- The assembler (or final @@??) insures that the appropriate one is
45: ;;- selected.
46:
47: (define_insn ""
48: [(set (match_operand:DF 0 "push_operand" "=m")
49: (match_operand:DF 1 "general_operand" "rmfF"))]
50: ""
51: "*
52: {
53: if (FPU_REG_P (operands[1]))
54: return \"fmov.d %f1,%0\";
55: return output_move_double (operands);
56: }")
57:
58: (define_insn ""
59: [(set (match_operand:DI 0 "push_operand" "=m")
60: (match_operand:DF 1 "general_operand" "rmF"))]
61: ""
62: "*
63: {
64: return output_move_double (operands);
65: }")
66:
67: ;; We don't want to allow a constant operand for test insns because
68: ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
69: ;; be folded while optimizing anyway.
70:
71: (define_insn "tstsi"
72: [(set (cc0)
73: (match_operand:SI 0 "nonimmediate_operand" "rm"))]
74: ""
75: "cmp:z.w #0,%0")
76:
77: (define_insn "tsthi"
78: [(set (cc0)
79: (match_operand:HI 0 "nonimmediate_operand" "rm"))]
80: ""
81: "cmp:z.h #0,%0")
82:
83: (define_insn "tstqi"
84: [(set (cc0)
85: (match_operand:QI 0 "nonimmediate_operand" "rm"))]
86: ""
87: "cmp:z.b #0,%0")
88:
89:
90: (define_insn "tstsf"
91: [(set (cc0)
92: (match_operand:SF 0 "general_operand" "fmF"))]
93: "TARGET_FPU"
94: "*
95: {
96: cc_status.flags = CC_IN_FPU;
97: return \"ftst.s %0\";
98: }")
99:
100:
101: (define_insn "tstdf"
102: [(set (cc0)
103: (match_operand:DF 0 "general_operand" "fmF"))]
104: "TARGET_FPU"
105: "*
106: {
107: cc_status.flags = CC_IN_FPU;
108: return \"ftst.d %0\";
109: }")
110:
111: ;; compare instructions.
112:
113: ;; (operand0 - operand1)
114: (define_insn "cmpsi"
115: [(set (cc0)
116: (compare (match_operand:SI 0 "nonimmediate_operand" "ri,rm")
117: (match_operand:SI 1 "general_operand" "rm,rmi")))]
118: ""
119: "*
120: {
121: int signed_flag = my_signed_comp (insn);
122:
123: if (which_alternative == 0)
124: {
125: cc_status.flags |= CC_REVERSED;
126: if (signed_flag && GET_CODE (operands[0]) == CONST_INT)
127: {
128: register rtx xfoo;
129: xfoo = operands[1];
130: operands[0] = operands[1];
131: operands[1] = xfoo;
132: return cmp_imm_word (INTVAL (operands[1]), operands[0]);
133: }
134: if (signed_flag)
135: return \"cmp.w %0,%1\";
136: return \"cmpu.w %0,%1\";
137: }
138: if (signed_flag)
139: {
140: if (GET_CODE (operands[1]) == CONST_INT)
141: return cmp_imm_word (INTVAL (operands[1]), operands[0]);
142: return \"cmp.w %1,%0\";
143: }
144: else
145: return \"cmpu.w %1,%0\";
146: }")
147:
148: (define_insn "cmphi"
149: [(set (cc0)
150: (compare (match_operand:HI 0 "nonimmediate_operand" "ri,rm")
151: (match_operand:HI 1 "general_operand" "rm,rmi")))]
152: ""
153: "*
154: {
155: int signed_flag = my_signed_comp (insn);
156:
157: if (which_alternative == 0)
158: {
159: cc_status.flags |= CC_REVERSED;
160: if (signed_flag)
161: return \"cmp.h %0,%1\";
162: return \"cmpu.h %0,%1\";
163: }
164: if (signed_flag)
165: return \"cmp.h %1,%0\";
166: return \"cmpu.h %1,%0\";
167: }")
168:
169: (define_insn "cmpqi"
170: [(set (cc0)
171: (compare (match_operand:QI 0 "nonimmediate_operand" "ri,rm")
172: (match_operand:QI 1 "general_operand" "rm,rmi")))]
173: ""
174: "*
175: {
176: int signed_flag = my_signed_comp (insn);
177:
178: if (which_alternative == 0)
179: {
180: cc_status.flags |= CC_REVERSED;
181: if (signed_flag)
182: return \"cmp.b %0,%1\";
183: return \"cmpu.b %0,%1\";
184: }
185: if (signed_flag)
186: return \"cmp.b %1,%0\";
187: return \"cmpu.b %1,%0\";
188: }")
189:
190:
191: (define_insn "cmpdf"
192: [(set (cc0)
193: (compare (match_operand:DF 0 "general_operand" "f,mG")
194: (match_operand:DF 1 "general_operand" "fmG,f")))]
195: "TARGET_FPU"
196: "*
197: {
198: cc_status.flags = CC_IN_FPU;
199:
200: if (FPU_REG_P (operands[0]))
201: return \"fcmp.d %f1,%f0\";
202: cc_status.flags |= CC_REVERSED;
203: return \"fcmp.d %f0,%f1\";
204: }")
205:
206:
207: (define_insn "cmpsf"
208: [(set (cc0)
209: (compare (match_operand:SF 0 "general_operand" "f,mG")
210: (match_operand:SF 1 "general_operand" "fmG,f")))]
211: "TARGET_FPU"
212: "*
213: {
214: cc_status.flags = CC_IN_FPU;
215: if (FPU_REG_P (operands[0]))
216: return \"fcmp.s %f1,%0\";
217: cc_status.flags |= CC_REVERSED;
218: return \"fcmp.s %f0,%1\";
219: }")
220:
221: ;; Recognizers for btst instructions.
222:
223: (define_insn ""
224: [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "rm")
225: (const_int 1)
226: (match_operand:SI 1 "general_operand" "rmi")))]
227: ""
228: "btst %1.w,%0.b")
229:
230: (define_insn ""
231: [(set (cc0) (zero_extract (match_operand:HI 0 "nonimmediate_operand" "rm")
232: (const_int 1)
233: (match_operand:SI 1 "general_operand" "rmi")))]
234: ""
235: "btst %1.w,%0.h")
236:
237: (define_insn ""
238: [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "rm")
239: (const_int 1)
240: (match_operand:SI 1 "general_operand" "rmi")))]
241: ""
242: "btst %1.w,%0.w")
243:
244: ;; The following two patterns are like the previous two
245: ;; except that they use the fact that bit-number operands (offset)
246: ;; are automatically masked to 3 or 5 bits when the base is a register.
247:
248: (define_insn ""
249: [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "r")
250: (const_int 1)
251: (and:SI
252: (match_operand:SI 1 "general_operand" "rmi")
253: (const_int 7))))]
254: ""
255: "btst %1.w,%0.b")
256:
257: (define_insn ""
258: [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "r")
259: (const_int 1)
260: (and:SI
261: (match_operand:SI 1 "general_operand" "rmi")
262: (const_int 31))))]
263: ""
264: "btst %1.w,%0.w")
265:
266: ; More various size-patterns are allowed for btst, but not
267: ; included yet. M.Yuhara
268:
269:
270: (define_insn ""
271: [(set (cc0) (and:SI (sign_extend:SI (sign_extend:HI (match_operand:QI 0 "nonimmediate_operand" "rm")))
272: (match_operand:SI 1 "general_operand" "i")))]
273: "(GET_CODE (operands[1]) == CONST_INT
274: && (unsigned) INTVAL (operands[1]) < 0x100
275: && exact_log2 (INTVAL (operands[1])) >= 0)"
276: "*
277: {
278: register int log = exact_log2 (INTVAL (operands[1]));
279: operands[1] = gen_rtx (CONST_INT, VOIDmode, log);
280: return \"btst %1,%0.b\";
281: }")
282:
283: ; I can add more patterns like above. But not yet. M.Yuhara
284:
285:
286: ; mtst is supported only by G/300.
287:
288: (define_insn ""
289: [(set (cc0)
290: (and:SI (match_operand:SI 0 "general_operand" "%rmi")
291: (match_operand:SI 1 "general_operand" "rm")))]
292: "TARGET_G300"
293: "*
294: {
295: if (GET_CODE (operands[0]) == CONST_INT)
296: return \"mtst.w %0,%1\";
297: return \"mtst.w %1,%0\";
298: }")
299:
300: (define_insn ""
301: [(set (cc0)
302: (and:HI (match_operand:HI 0 "general_operand" "%rmi")
303: (match_operand:HI 1 "general_operand" "rm")))]
304: "TARGET_G300"
305: "*
306: {
307: if (GET_CODE (operands[0]) == CONST_INT)
308: return \"mtst.h %0,%1\";
309: return \"mtst.h %1,%0\";
310: }")
311:
312: (define_insn ""
313: [(set (cc0)
314: (and:QI (match_operand:QI 0 "general_operand" "%rmi")
315: (match_operand:QI 1 "general_operand" "rm")))]
316: "TARGET_G300"
317: "*
318: {
319: if (GET_CODE (operands[0]) == CONST_INT)
320: return \"mtst.b %0,%1\";
321: return \"mtst.b %1,%0\";
322: }")
323:
324:
325:
326: ;; move instructions
327:
328: /* added by M.Yuhara */
329: ;; 1.35.04 89.08.28 modification start
330: ;; register_operand -> general_operand
331: ;; ashift -> mult
332:
333: (define_insn ""
334: [(set (mem:SI (plus:SI
335: (match_operand:SI 0 "general_operand" "r")
336: (ashift:SI
337: (match_operand:SI 1 "general_operand" "r")
338: (const_int 2))))
339: (match_operand:SI 2 "general_operand" "rmi"))]
340: ""
341: "*
342: {
343: return \"mov.w %2,@(%0:b,%1*4)\";
344: }")
345:
346: (define_insn ""
347: [(set (mem:SI (plus:SI
348: (ashift:SI
349: (match_operand:SI 0 "general_operand" "r")
350: (const_int 2))
351: (match_operand:SI 1 "general_operand" "r")))
352: (match_operand:SI 2 "general_operand" "rmi"))]
353: ""
354: "*
355: {
356: return \"mov.w %2,@(%1:b,%0*4)\";
357: }")
358:
359:
360: (define_insn ""
361: [(set (mem:SI (plus:SI
362: (match_operand:SI 0 "register_operand" "r")
363: (mult:SI
364: (match_operand:SI 1 "register_operand" "r")
365: (const_int 4))))
366: (match_operand:SI 2 "general_operand" "rmi"))]
367: ""
368: "*
369: {
370: return \"mov.w %2,@(%0:b,%1*4)\";
371: }")
372:
373: (define_insn ""
374: [(set (mem:SI (plus:SI
375: (mult:SI
376: (match_operand:SI 0 "register_operand" "r")
377: (const_int 4))
378: (match_operand:SI 1 "register_operand" "r")))
379: (match_operand:SI 2 "general_operand" "rmi"))]
380: ""
381: "*
382: {
383: return \"mov.w %2,@(%1:b,%0*4)\";
384: }")
385:
386:
387: (define_insn ""
388: [(set (mem:SI (plus:SI
389: (match_operand:SI 0 "general_operand" "r")
390: (plus:SI
391: (match_operand:SI 1 "register_operand" "r")
392: (match_operand:SI 2 "register_operand" "i"))))
393: (match_operand:SI 3 "general_operand" "rmi"))]
394: ""
395: "*
396: {
397: return \"mov.w %3,@(%c2,%0,%1)\";
398: }")
399:
400: (define_insn ""
401: [(set (mem:SI (plus:SI
402: (plus:SI
403: (match_operand:SI 0 "register_operand" "r")
404: (match_operand:SI 1 "register_operand" "r"))
405: (match_operand:SI 2 "general_operand" "i")))
406: (match_operand:SI 3 "general_operand" "rmi"))]
407: ""
408: "*
409: {
410: return \"mov.w %3,@(%c2,%0,%1)\";
411: }")
412:
413:
414: (define_insn ""
415: [(set (mem:SI (plus:SI
416: (match_operand:SI 0 "general_operand" "i")
417: (plus:SI
418: (match_operand:SI 1 "register_operand" "r")
419: (mult:SI
420: (match_operand:SI 2 "register_operand" "r")
421: (const_int 4)))))
422: (match_operand:SI 3 "general_operand" "rmi"))]
423: ""
424: "*
425: {
426: return \"mov.w %3,@(%1:b,%0,%2*4)\";
427: }")
428:
429: ;; 89.08.28 1.35.04 modification end
430:
431: ;; Should add "!" to op2 ??
432:
433: ;; General move-address-to-operand should handle these.
434: ;; If that does not work, please figure out why.
435:
436: ;(define_insn ""
437: ; [(set (match_operand:SI 0 "push_operand" "=m")
438: ; (plus:SI
439: ; (match_operand:SI 1 "immediate_operand" "i")
440: ; (match_operand:SI 2 "general_operand" "r")))]
441: ; ""
442: ; "mova.w @(%c1,%2),%-")
443:
444: ;(define_insn ""
445: ; [(set (match_operand:SI 0 "push_operand" "=m")
446: ; (plus:SI
447: ; (match_operand:SI 1 "general_operand" "r")
448: ; (match_operand:SI 2 "immediate_operand" "i")))]
449: ; ""
450: ; "mova.w @(%c2,%1),%-")
451:
452:
453: (define_insn ""
454: [(set (match_operand:SI 0 "push_operand" "=m")
455: (minus:SI
456: (match_operand:SI 1 "general_operand" "r")
457: (match_operand:SI 2 "immediate_operand" "i")))]
458: ""
459: "mova.w @(%n2,%1),%-")
460:
461:
462:
463: ;; General case of fullword move.
464:
465: (define_insn "movsi"
466: [(set (match_operand:SI 0 "general_operand" "=rm")
467: (match_operand:SI 1 "general_operand" "rmi"))]
468: ""
469: "*
470: {
471: if (GET_CODE (operands[1]) == CONST_INT)
472: return mov_imm_word (INTVAL (operands[1]), operands[0]);
473: /* if (address_operand (operands[1], SImode))
474: return \"mova.w %1,%0\"; */
475: if (push_operand (operands[0], SImode))
476: return \"mov.w %1,%-\";
477: return \"mov.w %1,%0\";
478: }")
479:
480: /* pushsi 89.08.10 for test M.Yuhara */
481: /*
482: (define_insn ""
483: [(set (match_operand:SI 0 "push_operand" "=m")
484: (match_operand:SI 1 "general_operand" "rmi"))]
485: ""
486: "*
487: {
488: if (GET_CODE (operands[1]) == CONST_INT)
489: return mov_imm_word (INTVAL (operands[1]), operands[0]);
490: if (push_operand (operands[0], SImode))
491: return \"mov.w %1,%-\";
492: return \"mov.w %1,%0\";
493: }")
494: */
495:
496:
497: (define_insn "movhi"
498: [(set (match_operand:HI 0 "general_operand" "=rm")
499: (match_operand:HI 1 "general_operand" "rmi"))]
500: ""
501: "*
502: {
503: if (push_operand (operands[0], SImode))
504: return \"mov.h %1,%-\";
505: return \"mov.h %1,%0\";
506: }")
507:
508: ;; Is the operand constraint "+" necessary ????
509: ;; Should I check push_operand ????
510:
511: (define_insn "movstricthi"
512: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+rm"))
513: (match_operand:HI 1 "general_operand" "rmi"))]
514: ""
515: "mov.h %1,%0");
516:
517: (define_insn "movqi"
518: [(set (match_operand:QI 0 "general_operand" "=rm")
519: (match_operand:QI 1 "general_operand" "rmi"))]
520: ""
521: "*
522: {
523: if (GREG_P (operands[0]))
524: {
525: if (CONSTANT_P (operands[1]))
526: return \"mov:l %1,%0.w\";
527: else
528: return \"mov:l %1.b,%0.w\";
529: }
530: if (GREG_P (operands[1]))
531: return \"mov:s %1.w,%0.b\";
532: return \"mov.b %1,%0\";
533: }")
534:
535: (define_insn "movstrictqi"
536: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+rm"))
537: (match_operand:QI 1 "general_operand" "rmi"))]
538: ""
539: "mov.b %1,%0")
540:
541:
542: (define_insn "movsf"
543: [(set (match_operand:SF 0 "general_operand" "=f,mf,rm,fr")
544: (match_operand:SF 1 "general_operand" "mfF,f,rmF,fr"))]
545: ""
546: "*
547: {
548: switch (which_alternative)
549: {
550: case 0:
551: if (GET_CODE (operands[1]) == CONST_DOUBLE)
552: return output_move_const_single (operands);
553: return \"fmov.s %1,%0\";
554: case 1:
555: return \"fmov.s %1,%0\";
556: case 2:
557: if (GET_CODE (operands[1]) == CONST_DOUBLE)
558: return output_move_const_single (operands);
559: return \"mov.w %1,%0\";
560: case 3:
561: if (FPU_REG_P (operands[0]))
562: return \"mov.w %1,%-\\n\\tfmov.s %+,%0\";
563: return \"fmov.s %1,%-\\n\\tmov.w %+,%0\";
564: }
565: }")
566:
567: (define_insn "movdf"
568: [(set (match_operand:DF 0 "general_operand" "=f,mf,rm,fr")
569: (match_operand:DF 1 "general_operand" "mfF,f,rmF,fr"))]
570: ""
571: "*
572: {
573: switch (which_alternative)
574: {
575: case 0:
576: if (GET_CODE (operands[1]) == CONST_DOUBLE)
577: return output_move_const_double (operands);
578: return \"fmov.d %1,%0\";
579: case 1:
580: return \"fmov.d %1,%0\";
581: case 2:
582: if (GET_CODE (operands[1]) == CONST_DOUBLE)
583: return output_move_const_double (operands);
584: return output_move_double (operands);
585: case 3:
586: if (FPU_REG_P (operands[0]))
587: {
588: rtx xoperands[2];
589: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
590: output_asm_insn (\"mov.w %1,%-\", xoperands);
591: output_asm_insn (\"mov.w %1,%-\", operands);
592: return \"fmov.d %+,%0\";
593: }
594: else
595: {
596: output_asm_insn (\"fmov.d %f1,%-\", operands);
597: output_asm_insn (\"mov.w %+,%0\", operands);
598: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
599: return \"mov.w %+,%0\";
600: }
601: }
602: }")
603:
604:
605: ;; movdi can apply to fp regs in some cases
606: ;; Must check again. you can use fsti/fldi, etc.
607: ;; FPU reg should be included ??
608: ;; 89.12.13 for test
609:
610: (define_insn "movdi"
611: ;; Let's see if it really still needs to handle fp regs, and, if so, why.
612: [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro")
613: (match_operand:DI 1 "general_operand" "rF,m,roiF"))]
614: ""
615: "*
616: {
617: if (FPU_REG_P (operands[0]))
618: {
619: if (FPU_REG_P (operands[1]))
620: return \"fmov.d %1,%0\";
621: if (REG_P (operands[1]))
622: {
623: rtx xoperands[2];
624: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
625: output_asm_insn (\"mov.w %1,%-\", xoperands);
626: output_asm_insn (\"mov.w %1,%-\", operands);
627: return \"fmov.d %+,%0\";
628: }
629: if (GET_CODE (operands[1]) == CONST_DOUBLE)
630: return output_move_const_double (operands);
631: return \"fmov.d %f1,%0\";
632: }
633: else if (FPU_REG_P (operands[1]))
634: {
635: if (REG_P (operands[0]))
636: {
637: output_asm_insn (\"fmov.d %f1,%-\;mov.w %+,%0\", operands);
638: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
639: return \"mov.w %+,%0\";
640: }
641: else
642: return \"fmov.d %f1,%0\";
643: }
644: return output_move_double (operands);
645: }
646: ")
647:
648:
649: ;; The definition of this insn does not really explain what it does,
650: ;; but it should suffice
651: ;; that anything generated as this insn will be recognized as one
652: ;; and that it won't successfully combine with anything.
653:
654: ;; This is dangerous when %0 and %1 overlapped !!!!!
655: ;; Ugly code...
656:
657: (define_insn "movstrhi"
658: [(set (match_operand:BLK 0 "general_operand" "=m")
659: (match_operand:BLK 1 "general_operand" "m"))
660: (use (match_operand:HI 2 "general_operand" "rmi"))
661: (clobber (reg:SI 0))
662: (clobber (reg:SI 1))
663: (clobber (reg:SI 2))]
664: ""
665: "*
666: {
667: int op2const;
668: rtx tmpx;
669:
670: if (CONSTANT_P (operands[1]))
671: {
672: fprintf (stderr, \"smov 1 const err \");
673: abort ();
674: }
675: else if (GET_CODE (operands[1]) == REG)
676: {
677: fprintf (stderr, \"smov 1 reg err \");
678: abort ();
679: }
680: else if (GET_CODE (operands[1]) == MEM)
681: {
682: tmpx = XEXP (operands[1], 0);
683: if (CONSTANT_ADDRESS_P (tmpx) || GREG_P (tmpx))
684: {
685: operands[1] = tmpx;
686: output_asm_insn (\"mov.w %1,r0\", operands);
687: }
688: else
689: {
690: output_asm_insn (\"mova %1,r0\", operands);
691: }
692: }
693: else
694: {
695: fprintf (stderr, \"smov 1 else err \");
696: abort ();
697: output_asm_insn (\"mova.w %p1,r0\", operands);
698: }
699:
700: if (CONSTANT_P (operands[0]))
701: {
702: fprintf (stderr, \"smov 0 const err \");
703: abort ();
704: }
705: else if (GET_CODE (operands[0]) == REG)
706: {
707: fprintf (stderr, \"smov 0 reg err \");
708: abort ();
709: }
710: else if (GET_CODE (operands[0]) == MEM)
711: {
712: tmpx = XEXP (operands[0], 0);
713: if (CONSTANT_ADDRESS_P (tmpx) || GREG_P (tmpx))
714: {
715: operands[0] = tmpx;
716: output_asm_insn (\"mov.w %0,r1\", operands);
717: }
718: else
719: {
720: output_asm_insn (\"mova %0,r1\", operands);
721: }
722: }
723: else
724: {
725: fprintf (stderr, \"smov 0 else err \");
726: abort ();
727: }
728:
729: if (GET_CODE (operands[2]) == CONST_INT)
730: {
731: op2const = INTVAL (operands[2]);
732: if (op2const % 4 != 0)
733: {
734: output_asm_insn (\"mov.w %2,r2\", operands);
735: return \"smov/n/f.b\";
736: }
737: op2const = op2const / 4;
738: if (op2const <= 4)
739: {
740: if (op2const == 0)
741: abort (0);
742: if (op2const == 1)
743: return \"mov.w @r0,@r1\";
744: output_asm_insn (\"mov.w @r0,@r1\", operands);
745: if (op2const == 2)
746: return \"mov.w @(4,r0),@(4,r1)\";
747: output_asm_insn (\"mov.w @(4,r0),@(4,r1)\", operands);
748: if (op2const == 3)
749: return \"mov.w @(8,r0),@(8,r1)\";
750: output_asm_insn (\"mov.w @(8,r0),@(8,r1)\", operands);
751: return \"mov.w @(12,r0),@(12,r1)\";
752: }
753:
754: operands[2] =
755: gen_rtx (CONST_INT, VOIDmode, op2const);
756: output_asm_insn (\"mov.w %2,r2\", operands);
757: return \"smov/n/f.w\";
758: }
759: else
760: {
761: fprintf (stderr, \"smov 0 else err \");
762: abort ();
763: output_asm_insn (\"mov %2.h,r2.w\", operands);
764: return \"smov/n/f.b\";
765: }
766:
767: }")
768:
769: ;; M.Yuhara 89.08.24
770: ;; experiment on the built-in strcpy (__builtin_smov)
771: ;;
772: ;; len = 0 means unknown string length.
773: ;;
774: ;; mem:SI is dummy. Necessary so as not to be deleted by optimization.
775: ;; Use of BLKmode would be better...
776: ;;
777: ;;
778: (define_insn "smovsi"
779: [(set (mem:SI (match_operand:SI 0 "general_operand" "=rm"))
780: (mem:SI (match_operand:SI 1 "general_operand" "rm")))
781: (use (match_operand:SI 2 "general_operand" "i"))
782: (clobber (reg:SI 0))
783: (clobber (reg:SI 1))
784: (clobber (reg:SI 2))
785: (clobber (reg:SI 3))]
786: ""
787: "*
788: {
789: int len, wlen, blen, offset;
790: char tmpstr[128];
791: rtx xoperands[1];
792:
793: len = INTVAL (operands[2]);
794: output_asm_insn (\"mov.w %1,r0\\t; begin built-in strcpy\", operands);
795: output_asm_insn (\"mov.w %0,r1\", operands);
796:
797: if (len == 0)
798: {
799: output_asm_insn (\"mov:z.w #0,r2\", operands);
800: output_asm_insn (\"mov:z.w #0,r3\", operands);
801: return \"smov/eq/f.b\\t; end built-in strcpy\";
802: }
803:
804: wlen = len / 4;
805: blen = len - wlen * 4;
806:
807: if (wlen > 0)
808: {
809: if (len <= 40 && !TARGET_FORCE_SMOV)
810: {
811: output_asm_insn (\"mov.w @r0,@r1\", operands);
812: offset = 4;
813: while ( (blen = len - offset) > 0)
814: {
815: if (blen >= 4)
816: {
817: sprintf (tmpstr, \"mov.w @(%d,r0),@(%d,r1)\",
818: offset, offset);
819: output_asm_insn (tmpstr, operands);
820: offset += 4;
821: }
822: else if (blen >= 2)
823: {
824: sprintf (tmpstr, \"mov.h @(%d,r0),@(%d,r1)\",
825: offset, offset);
826: output_asm_insn (tmpstr, operands);
827: offset += 2;
828: }
829: else
830: {
831: sprintf (tmpstr, \"mov.b @(%d,r0),@(%d,r1)\",
832: offset, offset);
833: output_asm_insn (tmpstr, operands);
834: offset++;
835: }
836: }
837: return \"\\t\\t; end built-in strcpy\";
838: }
839: else
840: {
841: xoperands[0] = gen_rtx (CONST_INT, VOIDmode, wlen);
842: output_asm_insn (\"mov.w %0,r2\", xoperands);
843: output_asm_insn (\"smov/n/f.w\", operands);
844: }
845: }
846:
847: if (blen >= 2)
848: {
849: output_asm_insn (\"mov.h @r0,@r1\", operands);
850: if (blen == 3)
851: output_asm_insn (\"mov.b @(2,r0),@(2,r1)\", operands);
852: }
853: else if (blen == 1)
854: {
855: output_asm_insn (\"mov.b @r0,@r1\", operands);
856: }
857:
858: return \"\\t\\t; end built-in strcpy\";
859: }")
860:
861: ;; truncation instructions
862: (define_insn "truncsiqi2"
863: [(set (match_operand:QI 0 "general_operand" "=rm")
864: (truncate:QI
865: (match_operand:SI 1 "general_operand" "rmi")))]
866: ""
867: "mov %1.w,%0.b")
868: ; "*
869: ;{
870: ; if (GET_CODE (operands[0]) == REG)
871: ; return \"mov.w %1,%0\";
872: ; if (GET_CODE (operands[1]) == MEM)
873: ; operands[1] = adj_offsettable_operand (operands[1], 3);
874: ; return \"mov.b %1,%0\";
875: ;}")
876:
877: (define_insn "trunchiqi2"
878: [(set (match_operand:QI 0 "general_operand" "=rm")
879: (truncate:QI
880: (match_operand:HI 1 "general_operand" "rmi")))]
881: ""
882: "mov %1.h,%0.b")
883: ; "*
884: ;{
885: ; if (GET_CODE (operands[0]) == REG)
886: ; return \"mov.h %1,%0\";
887: ; if (GET_CODE (operands[1]) == MEM)
888: ; operands[1] = adj_offsettable_operand (operands[1], 1);
889: ; return \"mov.b %1,%0\";
890: ;}")
891:
892: (define_insn "truncsihi2"
893: [(set (match_operand:HI 0 "general_operand" "=rm")
894: (truncate:HI
895: (match_operand:SI 1 "general_operand" "rmi")))]
896: ""
897: "mov %1.w,%0.h")
898: ; "*
899: ;{
900: ; if (GET_CODE (operands[0]) == REG)
901: ; return \"mov.w %1,%0\";
902: ; if (GET_CODE (operands[1]) == MEM)
903: ; operands[1] = adj_offsettable_operand (operands[1], 2);
904: ; return \"mov.h %1,%0\";
905: ;}")
906:
907: ;; zero extension instructions
908: ;; define_expand (68k) -> define_insn (Gmicro)
909:
910: (define_insn "zero_extendhisi2"
911: [(set (match_operand:SI 0 "general_operand" "=rm")
912: (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
913: ""
914: "movu %1.h,%0.w")
915:
916:
917: (define_insn "zero_extendqihi2"
918: [(set (match_operand:HI 0 "general_operand" "=rm")
919: (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
920: ""
921: "movu %1.b,%0.h")
922:
923: (define_insn "zero_extendqisi2"
924: [(set (match_operand:SI 0 "general_operand" "=rm")
925: (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
926: ""
927: "movu %1.b,%0.w")
928:
929:
930: ;; sign extension instructions
931:
932: (define_insn "extendhisi2"
933: [(set (match_operand:SI 0 "general_operand" "=rm")
934: (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
935: ""
936: "mov %1.h,%0.w")
937:
938:
939: (define_insn "extendqihi2"
940: [(set (match_operand:HI 0 "general_operand" "=rm")
941: (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
942: ""
943: "mov %1.b,%0.h")
944:
945: (define_insn "extendqisi2"
946: [(set (match_operand:SI 0 "general_operand" "=rm")
947: (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
948: ""
949: "mov %1.b,%0.w")
950:
951:
952:
953: ;; Conversions between float and double.
954:
955: (define_insn "extendsfdf2"
956: [(set (match_operand:DF 0 "general_operand" "=*frm,f")
957: (float_extend:DF
958: (match_operand:SF 1 "general_operand" "f,rmF")))]
959: "TARGET_FPU"
960: "*
961: {
962: if (FPU_REG_P (operands[0]))
963: {
964: if (GET_CODE (operands[1]) == CONST_DOUBLE)
965: return output_move_const_double (operands);
966: if (GREG_P (operands[1]))
967: {
968: output_asm_insn (\"mov.w %1,%-\", operands);
969: return \"fmov %+.s,%0.d\";
970: }
971: return \"fmov %1.s,%0.d\";
972: }
973: else
974: {
975: if (GREG_P (operands[0]))
976: {
977: output_asm_insn (\"fmov %1.s,%-.d\", operands);
978: output_asm_insn (\"mov.w %+,%0\", operands);
979: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
980: return \"mov.w %+,%0\";
981: }
982: return \"fmov %1.s,%0.d\";
983: }
984: }")
985:
986:
987: (define_insn "truncdfsf2"
988: [(set (match_operand:SF 0 "general_operand" "=rfm")
989: (float_truncate:SF
990: (match_operand:DF 1 "general_operand" "f")))]
991: "TARGET_FPU"
992: "*
993: {
994: if (GREG_P (operands[0]))
995: {
996: output_asm_insn (\"fmov %1.d,%-.s\", operands);
997: return \"mov.w %+,%0\";
998: }
999: return \"fmov %1.d,%0.s\";
1000: }")
1001:
1002: ;; Conversion between fixed point and floating point.
1003: ;; Note that among the fix-to-float insns
1004: ;; the ones that start with SImode come first.
1005: ;; That is so that an operand that is a CONST_INT
1006: ;; (and therefore lacks a specific machine mode).
1007: ;; will be recognized as SImode (which is always valid)
1008: ;; rather than as QImode or HImode.
1009:
1010:
1011: (define_insn "floatsisf2"
1012: [(set (match_operand:SF 0 "general_operand" "=f")
1013: (float:SF (match_operand:SI 1 "general_operand" "rmi")))]
1014: "TARGET_FPU"
1015: "fldi %1.w,%0.s")
1016:
1017: (define_insn "floatsidf2"
1018: [(set (match_operand:DF 0 "general_operand" "=f")
1019: (float:DF (match_operand:SI 1 "general_operand" "rmi")))]
1020: "TARGET_FPU"
1021: "fldi %1.w,%0.d")
1022:
1023: (define_insn "floathisf2"
1024: [(set (match_operand:SF 0 "general_operand" "=f")
1025: (float:SF (match_operand:HI 1 "general_operand" "rmi")))]
1026: "TARGET_FPU"
1027: "fldi %1.h,%0.s")
1028:
1029: (define_insn "floathidf2"
1030: [(set (match_operand:DF 0 "general_operand" "=f")
1031: (float:DF (match_operand:HI 1 "general_operand" "rmi")))]
1032: "TARGET_FPU"
1033: "fldi %1.h,%0.d")
1034:
1035: (define_insn "floatqisf2"
1036: [(set (match_operand:SF 0 "general_operand" "=f")
1037: (float:SF (match_operand:QI 1 "general_operand" "rmi")))]
1038: "TARGET_FPU"
1039: "fldi %1.b,%0.s")
1040:
1041: (define_insn "floatqidf2"
1042: [(set (match_operand:DF 0 "general_operand" "=f")
1043: (float:DF (match_operand:QI 1 "general_operand" "rmi")))]
1044: "TARGET_FPU"
1045: "fldi %1.b,%0.d")
1046:
1047: ;;; Convert a float to a float whose value is an integer.
1048: ;;; This is the first stage of converting it to an integer type.
1049: ;
1050: ;(define_insn "ftruncdf2"
1051: ; [(set (match_operand:DF 0 "general_operand" "=f")
1052: ; (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1053: ; "TARGET_FPU"
1054: ; "*
1055: ;{
1056: ; return \"fintrz.d %f1,%0\";
1057: ;}")
1058: ;
1059: ;(define_insn "ftruncsf2"
1060: ; [(set (match_operand:SF 0 "general_operand" "=f")
1061: ; (fix:SF (match_operand:SF 1 "general_operand" "fFm")))]
1062: ; "TARGET_FPU"
1063: ; "*
1064: ;{
1065: ; return \"fintrz.s %f1,%0\";
1066: ;}")
1067:
1068: ;; Convert a float to an integer.
1069:
1070: (define_insn "fix_truncsfqi2"
1071: [(set (match_operand:QI 0 "general_operand" "=rm")
1072: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "f"))))]
1073: "TARGET_FPU"
1074: "fsti %1.s,%0.b")
1075:
1076: (define_insn "fix_truncsfhi2"
1077: [(set (match_operand:HI 0 "general_operand" "=rm")
1078: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "f"))))]
1079: "TARGET_FPU"
1080: "fsti %1.s,%0.h")
1081:
1082: (define_insn "fix_truncsfsi2"
1083: [(set (match_operand:SI 0 "general_operand" "=rm")
1084: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "f"))))]
1085: "TARGET_FPU"
1086: "fsti %1.s,%0.w")
1087:
1088: (define_insn "fix_truncdfqi2"
1089: [(set (match_operand:QI 0 "general_operand" "=rm")
1090: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "f"))))]
1091: "TARGET_FPU"
1092: "fsti %1.d,%0.b")
1093:
1094: (define_insn "fix_truncdfhi2"
1095: [(set (match_operand:HI 0 "general_operand" "=rm")
1096: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "f"))))]
1097: "TARGET_FPU"
1098: "fsti %1.d,%0.h")
1099:
1100: (define_insn "fix_truncdfsi2"
1101: [(set (match_operand:SI 0 "general_operand" "=rm")
1102: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "f"))))]
1103: "TARGET_FPU"
1104: "fsti %1.d,%0.w")
1105:
1106:
1107: ;;; Special add patterns
1108: ;;; 89.09.28
1109:
1110: ;; This should be redundant; please find out why regular addsi3
1111: ;; fails to match this case.
1112:
1113: ;(define_insn ""
1114: ; [(set (mem:SI (plus:SI
1115: ; (plus:SI (match_operand 0 "general_operand" "r")
1116: ; (match_operand 1 "general_operand" "r"))
1117: ; (match_operand 2 "general_operand" "i")))
1118: ; (plus:SI
1119: ; (mem:SI (plus:SI
1120: ; (plus:SI (match_dup 0)
1121: ; (match_dup 1))
1122: ; (match_dup 2)))
1123: ; (match_operand 3 "general_operand" "rmi")))]
1124: ; ""
1125: ; "add.w %3,@(%c2,%0,%1)")
1126:
1127:
1128: ;; add instructions
1129:
1130: ;; Note that the last two alternatives are near-duplicates
1131: ;; in order to handle insns generated by reload.
1132: ;; This is needed since they are not themselves reloaded,
1133: ;; so commutativity won't apply to them.
1134:
1135: (define_insn "addsi3"
1136: [(set (match_operand:SI 0 "general_operand" "=rm,!r,!r")
1137: (plus:SI (match_operand:SI 1 "general_operand" "%0,r,ri")
1138: (match_operand:SI 2 "general_operand" "rmi,ri,r")))]
1139: ""
1140: "*
1141: {
1142: if (which_alternative == 0)
1143: {
1144: if (GET_CODE (operands[2]) == CONST_INT)
1145: {
1146: operands[1] = operands[2];
1147: return add_imm_word (INTVAL (operands[1]), operands[0], &operands[1]);
1148: }
1149: else
1150: return \"add.w %2,%0\";
1151: }
1152: else
1153: {
1154: if (GET_CODE (operands[1]) == REG
1155: && REGNO (operands[0]) == REGNO (operands[1]))
1156: return \"add.w %2,%0\";
1157: if (GET_CODE (operands[2]) == REG
1158: && REGNO (operands[0]) == REGNO (operands[2]))
1159: return \"add.w %1,%0\";
1160:
1161: if (GET_CODE (operands[1]) == REG)
1162: {
1163: if (GET_CODE (operands[2]) == REG)
1164: return \"mova.w @(%1,%2),%0\";
1165: else
1166: return \"mova.w @(%c2,%1),%0\";
1167: }
1168: else
1169: return \"mova.w @(%c1,%2),%0\";
1170: }
1171: }")
1172:
1173: (define_insn ""
1174: [(set (match_operand:SI 0 "general_operand" "=rm")
1175: (plus:SI (match_operand:SI 1 "general_operand" "0")
1176: (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rmi"))))]
1177: ""
1178: "*
1179: {
1180: if (CONSTANT_P (operands[2]))
1181: {
1182: operands[1] = operands[2];
1183: return add_imm_word (INTVAL (operands[1]), operands[0], &operands[1]);
1184: }
1185: else
1186: return \"add %2.h,%0.w\";
1187: }")
1188:
1189: (define_insn "addhi3"
1190: [(set (match_operand:HI 0 "general_operand" "=rm")
1191: (plus:HI (match_operand:HI 1 "general_operand" "%0")
1192: (match_operand:HI 2 "general_operand" "rmi")))]
1193: ""
1194: "*
1195: {
1196: if (GET_CODE (operands[2]) == CONST_INT
1197: && INTVAL (operands[2]) < 0)
1198: return \"sub.h #%n2,%0\";
1199: if (GREG_P (operands[0]))
1200: {
1201: if (CONSTANT_P (operands[2]))
1202: return \"add:l %2,%0.w\";
1203: else
1204: return \"add:l %2.h,%0.w\";
1205: }
1206: return \"add.h %2,%0\";
1207: }")
1208:
1209: (define_insn ""
1210: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+rm"))
1211: (plus:HI (match_dup 0)
1212: (match_operand:HI 1 "general_operand" "rmi")))]
1213: ""
1214: "add.h %1,%0")
1215:
1216: (define_insn "addqi3"
1217: [(set (match_operand:QI 0 "general_operand" "=rm")
1218: (plus:QI (match_operand:QI 1 "general_operand" "%0")
1219: (match_operand:QI 2 "general_operand" "rmi")))]
1220: ""
1221: "*
1222: {
1223: if (GET_CODE (operands[2]) == CONST_INT
1224: && INTVAL (operands[2]) < 0)
1225: return \"sub.b #%n2,%0\";
1226: if (GREG_P (operands[0]))
1227: {
1228: if (CONSTANT_P (operands[2]))
1229: return \"add:l %2,%0.w\";
1230: else
1231: return \"add:l %2.b,%0.w\";
1232: }
1233: return \"add.b %2,%0\";
1234: }")
1235:
1236: (define_insn ""
1237: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+rm"))
1238: (plus:QI (match_dup 0)
1239: (match_operand:QI 1 "general_operand" "rmi")))]
1240: ""
1241: "add.b %1,%0")
1242:
1243: (define_insn "adddf3"
1244: [(set (match_operand:DF 0 "general_operand" "=f")
1245: (plus:DF (match_operand:DF 1 "general_operand" "%0")
1246: (match_operand:DF 2 "general_operand" "fmG")))]
1247: "TARGET_FPU"
1248: "fadd.d %f2,%0")
1249:
1250: (define_insn "addsf3"
1251: [(set (match_operand:SF 0 "general_operand" "=f")
1252: (plus:SF (match_operand:SF 1 "general_operand" "%0")
1253: (match_operand:SF 2 "general_operand" "fmG")))]
1254: "TARGET_FPU"
1255: "fadd.s %f2,%0")
1256:
1257: ;; subtract instructions
1258:
1259: (define_insn "subsi3"
1260: [(set (match_operand:SI 0 "general_operand" "=rm,!r")
1261: (minus:SI (match_operand:SI 1 "general_operand" "0,r")
1262: (match_operand:SI 2 "general_operand" "rmi,i")))]
1263: ""
1264: "*
1265: {
1266: if (which_alternative == 0
1267: || (GET_CODE (operands[1]) == REG
1268: && REGNO (operands[0]) == REGNO (operands[1])))
1269: {
1270: if (GET_CODE (operands[2]) == CONST_INT)
1271: {
1272: operands[1] = operands[2];
1273: return sub_imm_word (INTVAL (operands[1]),
1274: operands[0], &operands[1]);
1275: }
1276: else
1277: return \"sub.w %2,%0\";
1278: }
1279: else
1280: return \"mova.w @(%n2,%1),%0\";
1281: }")
1282:
1283: (define_insn ""
1284: [(set (match_operand:SI 0 "general_operand" "=rm")
1285: (minus:SI (match_operand:SI 1 "general_operand" "0")
1286: (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "rmi"))))]
1287: ""
1288: "sub %2.h,%0.w")
1289:
1290: (define_insn "subhi3"
1291: [(set (match_operand:HI 0 "general_operand" "=rm")
1292: (minus:HI (match_operand:HI 1 "general_operand" "0")
1293: (match_operand:HI 2 "general_operand" "rmi")))]
1294: ""
1295: "*
1296: {
1297: if (GET_CODE (operands[2]) == CONST_INT
1298: && INTVAL (operands[2]) < 0
1299: && INTVAL (operands[2]) != 0x8000)
1300: return \"add.h #%n2,%0\";
1301: return \"sub.h %2,%0\";
1302: }")
1303:
1304: (define_insn ""
1305: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+rm"))
1306: (minus:HI (match_dup 0)
1307: (match_operand:HI 1 "general_operand" "rmi")))]
1308: ""
1309: "sub.h %1,%0")
1310:
1311: (define_insn "subqi3"
1312: [(set (match_operand:QI 0 "general_operand" "=rm")
1313: (minus:QI (match_operand:QI 1 "general_operand" "0")
1314: (match_operand:QI 2 "general_operand" "rmi")))]
1315: ""
1316: "*
1317: {
1318: if (GET_CODE (operands[2]) == CONST_INT
1319: && INTVAL (operands[2]) < 0
1320: && INTVAL (operands[2]) != 0x80)
1321: return \"add.b #%n2,%0\";
1322: return \"sub.b %2,%0\";
1323: }")
1324:
1325: (define_insn ""
1326: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+rm"))
1327: (minus:QI (match_dup 0)
1328: (match_operand:QI 1 "general_operand" "rmi")))]
1329: ""
1330: "sub.b %1,%0")
1331:
1332: (define_insn "subdf3"
1333: [(set (match_operand:DF 0 "general_operand" "=f")
1334: (minus:DF (match_operand:DF 1 "general_operand" "0")
1335: (match_operand:DF 2 "general_operand" "fmG")))]
1336: "TARGET_FPU"
1337: "fsub.d %f2,%0")
1338:
1339: (define_insn "subsf3"
1340: [(set (match_operand:SF 0 "general_operand" "=f")
1341: (minus:SF (match_operand:SF 1 "general_operand" "0")
1342: (match_operand:SF 2 "general_operand" "fmG")))]
1343: "TARGET_FPU"
1344: "fsub.s %f2,%0")
1345:
1346:
1347: ;; multiply instructions
1348:
1349: (define_insn "mulqi3"
1350: [(set (match_operand:QI 0 "general_operand" "=rm")
1351: (mult:QI (match_operand:QI 1 "general_operand" "%0")
1352: (match_operand:QI 2 "general_operand" "rmi")))]
1353: ""
1354: "mul.b %2,%0")
1355:
1356:
1357: (define_insn "mulhi3"
1358: [(set (match_operand:HI 0 "general_operand" "=rm")
1359: (mult:HI (match_operand:HI 1 "general_operand" "%0")
1360: (match_operand:HI 2 "general_operand" "rmi")))]
1361: ""
1362: "mul.h %2,%0")
1363:
1364: ;; define_insn "mulhisi3"
1365:
1366: (define_insn "mulsi3"
1367: [(set (match_operand:SI 0 "general_operand" "=rm")
1368: (mult:SI (match_operand:SI 1 "general_operand" "%0")
1369: (match_operand:SI 2 "general_operand" "rmi")))]
1370: ""
1371: "mul.w %2,%0")
1372:
1373: (define_insn "muldf3"
1374: [(set (match_operand:DF 0 "general_operand" "=f")
1375: (mult:DF (match_operand:DF 1 "general_operand" "%0")
1376: (match_operand:DF 2 "general_operand" "fmG")))]
1377: "TARGET_FPU"
1378: "fmul.d %f2,%0")
1379:
1380: (define_insn "mulsf3"
1381: [(set (match_operand:SF 0 "general_operand" "=f")
1382: (mult:SF (match_operand:SF 1 "general_operand" "%0")
1383: (match_operand:SF 2 "general_operand" "fmG")))]
1384: "TARGET_FPU"
1385: "fmul.s %f2,%0")
1386:
1387:
1388: ;; divide instructions
1389:
1390: (define_insn "divqi3"
1391: [(set (match_operand:QI 0 "general_operand" "=rm")
1392: (div:QI (match_operand:QI 1 "general_operand" "0")
1393: (match_operand:QI 2 "general_operand" "rmi")))]
1394: ""
1395: "div.b %2,%0")
1396:
1397: (define_insn "divhi3"
1398: [(set (match_operand:HI 0 "general_operand" "=rm")
1399: (div:HI (match_operand:HI 1 "general_operand" "0")
1400: (match_operand:HI 2 "general_operand" "rmi")))]
1401: ""
1402: "div.h %2,%0")
1403:
1404: (define_insn "divhisi3"
1405: [(set (match_operand:HI 0 "general_operand" "=r")
1406: (div:HI (match_operand:SI 1 "general_operand" "0")
1407: (match_operand:HI 2 "general_operand" "rmi")))]
1408: ""
1409: "div %2.h,%0.w")
1410:
1411: (define_insn "divsi3"
1412: [(set (match_operand:SI 0 "general_operand" "=rm")
1413: (div:SI (match_operand:SI 1 "general_operand" "0")
1414: (match_operand:SI 2 "general_operand" "rmi")))]
1415: ""
1416: "div.w %2,%0")
1417:
1418: (define_insn "udivqi3"
1419: [(set (match_operand:QI 0 "general_operand" "=rm")
1420: (udiv:QI (match_operand:QI 1 "general_operand" "0")
1421: (match_operand:QI 2 "general_operand" "rmi")))]
1422: ""
1423: "divu.b %2,%0")
1424:
1425: (define_insn "udivhi3"
1426: [(set (match_operand:HI 0 "general_operand" "=rm")
1427: (udiv:HI (match_operand:HI 1 "general_operand" "0")
1428: (match_operand:HI 2 "general_operand" "rmi")))]
1429: ""
1430: "divu.h %2,%0")
1431:
1432: (define_insn "udivhisi3"
1433: [(set (match_operand:HI 0 "general_operand" "=r")
1434: (udiv:HI (match_operand:SI 1 "general_operand" "0")
1435: (match_operand:HI 2 "general_operand" "rmi")))]
1436: ""
1437: "divu %2.h,%0.w")
1438:
1439: (define_insn "udivsi3"
1440: [(set (match_operand:SI 0 "general_operand" "=rm")
1441: (udiv:SI (match_operand:SI 1 "general_operand" "0")
1442: (match_operand:SI 2 "general_operand" "rmi")))]
1443: ""
1444: "divu.w %2,%0")
1445:
1446: (define_insn "divdf3"
1447: [(set (match_operand:DF 0 "general_operand" "=f")
1448: (div:DF (match_operand:DF 1 "general_operand" "0")
1449: (match_operand:DF 2 "general_operand" "fmG")))]
1450: "TARGET_FPU"
1451: "fdiv.d %f2,%0")
1452:
1453: (define_insn "divsf3"
1454: [(set (match_operand:SF 0 "general_operand" "=f")
1455: (div:SF (match_operand:SF 1 "general_operand" "0")
1456: (match_operand:SF 2 "general_operand" "fmG")))]
1457: "TARGET_FPU"
1458: "fdiv.s %f2,%0")
1459:
1460: ;; Remainder instructions.
1461:
1462: (define_insn "modqi3"
1463: [(set (match_operand:QI 0 "general_operand" "=rm")
1464: (mod:QI (match_operand:QI 1 "general_operand" "0")
1465: (match_operand:QI 2 "general_operand" "rmi")))]
1466: ""
1467: "rem.b %2,%0")
1468:
1469: (define_insn "modhisi3"
1470: [(set (match_operand:HI 0 "general_operand" "=r")
1471: (mod:HI (match_operand:SI 1 "general_operand" "0")
1472: (match_operand:HI 2 "general_operand" "rmi")))]
1473: ""
1474: "rem.h %2,%0")
1475:
1476: (define_insn "umodqi3"
1477: [(set (match_operand:QI 0 "general_operand" "=rm")
1478: (umod:QI (match_operand:QI 1 "general_operand" "0")
1479: (match_operand:QI 2 "general_operand" "rmi")))]
1480: ""
1481: "remu.b %2,%0")
1482:
1483: (define_insn "umodhi3"
1484: [(set (match_operand:HI 0 "general_operand" "=rm")
1485: (umod:HI (match_operand:HI 1 "general_operand" "0")
1486: (match_operand:HI 2 "general_operand" "rmi")))]
1487: ""
1488: "remu.h %2,%0")
1489:
1490: (define_insn "umodhisi3"
1491: [(set (match_operand:HI 0 "general_operand" "=r")
1492: (umod:HI (match_operand:SI 1 "general_operand" "0")
1493: (match_operand:HI 2 "general_operand" "rmi")))]
1494: ""
1495: "remu %2.h,%0.w")
1496:
1497: ;; define_insn "divmodsi4"
1498:
1499: (define_insn "udivmodsi4"
1500: [(set (match_operand:SI 0 "general_operand" "=rm")
1501: (udiv:SI (match_operand:SI 1 "general_operand" "0")
1502: (match_operand:SI 2 "general_operand" "rmi")))
1503: (set (match_operand:SI 3 "general_operand" "=r")
1504: (umod:SI (match_dup 1) (match_dup 2)))]
1505: ""
1506: "mov.w #0,%3;divx.w %2,%0,%3")
1507:
1508: ;; logical-and instructions
1509:
1510: (define_insn "andsi3"
1511: [(set (match_operand:SI 0 "general_operand" "=rm")
1512: (and:SI (match_operand:SI 1 "general_operand" "%0")
1513: (match_operand:SI 2 "general_operand" "rmi")))]
1514: ""
1515: "*
1516: {
1517: if (GET_CODE (operands[2]) == CONST_INT
1518: && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
1519: && (GREG_P (operands[0])
1520: || offsettable_memref_p (operands[0])))
1521:
1522: {
1523: if (GET_CODE (operands[0]) != REG)
1524: operands[0] = adj_offsettable_operand (operands[0], 2);
1525: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1526: INTVAL (operands[2]) & 0xffff);
1527: /* Do not delete a following tstl %0 insn; that would be incorrect. */
1528: CC_STATUS_INIT;
1529: return \"and.h %2,%0\";
1530: }
1531: return \"and.w %2,%0\";
1532: }")
1533:
1534: (define_insn "andhi3"
1535: [(set (match_operand:HI 0 "general_operand" "=rm")
1536: (and:HI (match_operand:HI 1 "general_operand" "%0")
1537: (match_operand:HI 2 "general_operand" "rmi")))]
1538: ""
1539: "and.h %2,%0")
1540:
1541: (define_insn "andqi3"
1542: [(set (match_operand:QI 0 "general_operand" "=rm")
1543: (and:QI (match_operand:QI 1 "general_operand" "%0")
1544: (match_operand:QI 2 "general_operand" "rmi")))]
1545: ""
1546: "and.b %2,%0")
1547:
1548: (define_insn ""
1549: [(set (match_operand:SI 0 "general_operand" "=r")
1550: (and:SI (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm"))
1551: (match_operand:SI 2 "general_operand" "0")))]
1552: ""
1553: "*
1554: {
1555: if (GET_CODE (operands[1]) == CONST_INT)
1556: return \"and %1,%0.w\";
1557: return \"and %1.h,%0.w\";
1558: }")
1559:
1560:
1561: (define_insn ""
1562: [(set (match_operand:SI 0 "general_operand" "=r")
1563: (and:SI (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm"))
1564: (match_operand:SI 2 "general_operand" "0")))]
1565: ""
1566: "*
1567: {
1568: if (GET_CODE (operands[1]) == CONST_INT)
1569: return \"and %1,%0.w\";
1570: return \"and %1.b,%0.w\";
1571: }")
1572:
1573: ;; inclusive-or instructions
1574:
1575: (define_insn "iorsi3"
1576: [(set (match_operand:SI 0 "general_operand" "=rm")
1577: (ior:SI (match_operand:SI 1 "general_operand" "%0")
1578: (match_operand:SI 2 "general_operand" "rmi")))]
1579: ""
1580: "*
1581: {
1582: register int logval;
1583: if (GET_CODE (operands[2]) == CONST_INT
1584: && INTVAL (operands[2]) >> 16 == 0
1585: && (GREG_P (operands[0])
1586: || offsettable_memref_p (operands[0])))
1587: {
1588: if (GET_CODE (operands[0]) != REG)
1589: operands[0] = adj_offsettable_operand (operands[0], 2);
1590: /* Do not delete a following tstl %0 insn; that would be incorrect. */
1591: CC_STATUS_INIT;
1592: return \"or.h %2,%0\";
1593: }
1594: if (GET_CODE (operands[2]) == CONST_INT
1595: && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
1596: && (GREG_P (operands[0])
1597: || offsettable_memref_p (operands[0])))
1598: {
1599: if (GREG_P (operands[0]))
1600: {
1601: if (logval < 7)
1602: {
1603: operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - logval);
1604: return \"bset.b %1,%0\";
1605: }
1606: operands[1] = gen_rtx (CONST_INT, VOIDmode, 31 - logval);
1607: return \"bset.w %1,%0\";
1608: }
1609: else
1610: {
1611: operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
1612: operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - (logval % 8));
1613: }
1614: return \"bset.b %1,%0\";
1615: }
1616: return \"or.w %2,%0\";
1617: }")
1618:
1619: (define_insn "iorhi3"
1620: [(set (match_operand:HI 0 "general_operand" "=rm")
1621: (ior:HI (match_operand:HI 1 "general_operand" "%0")
1622: (match_operand:HI 2 "general_operand" "rmi")))]
1623: ""
1624: "or.h %2,%0")
1625:
1626: (define_insn "iorqi3"
1627: [(set (match_operand:QI 0 "general_operand" "=rm")
1628: (ior:QI (match_operand:QI 1 "general_operand" "%0")
1629: (match_operand:QI 2 "general_operand" "rmi")))]
1630: ""
1631: "or.b %2,%0")
1632:
1633: ;; xor instructions
1634:
1635: (define_insn "xorsi3"
1636: [(set (match_operand:SI 0 "general_operand" "=rm")
1637: (xor:SI (match_operand:SI 1 "general_operand" "%0")
1638: (match_operand:SI 2 "general_operand" "rmi")))]
1639: ""
1640: "*
1641: {
1642: if (GET_CODE (operands[2]) == CONST_INT
1643: && INTVAL (operands[2]) >> 16 == 0
1644: && (offsettable_memref_p (operands[0]) || GREG_P (operands[0])))
1645: {
1646: if (! GREG_P (operands[0]))
1647: operands[0] = adj_offsettable_operand (operands[0], 2);
1648: /* Do not delete a following tstl %0 insn; that would be incorrect. */
1649: CC_STATUS_INIT;
1650: return \"xor.h %2,%0\";
1651: }
1652: return \"xor.w %2,%0\";
1653: }")
1654:
1655: (define_insn "xorhi3"
1656: [(set (match_operand:HI 0 "general_operand" "=rm")
1657: (xor:HI (match_operand:HI 1 "general_operand" "%0")
1658: (match_operand:HI 2 "general_operand" "rmi")))]
1659: ""
1660: "xor.h %2,%0")
1661:
1662: (define_insn "xorqi3"
1663: [(set (match_operand:QI 0 "general_operand" "=rm")
1664: (xor:QI (match_operand:QI 1 "general_operand" "%0")
1665: (match_operand:QI 2 "general_operand" "rmi")))]
1666: ""
1667: "xor.b %2,%0")
1668:
1669: ;; negation instructions
1670:
1671: (define_insn "negsi2"
1672: [(set (match_operand:SI 0 "general_operand" "=rm")
1673: (neg:SI (match_operand:SI 1 "general_operand" "0")))]
1674: ""
1675: "neg.w %0")
1676:
1677: (define_insn "neghi2"
1678: [(set (match_operand:HI 0 "general_operand" "=rm")
1679: (neg:HI (match_operand:HI 1 "general_operand" "0")))]
1680: ""
1681: "neg.h %0")
1682:
1683: (define_insn "negqi2"
1684: [(set (match_operand:QI 0 "general_operand" "=rm")
1685: (neg:QI (match_operand:QI 1 "general_operand" "0")))]
1686: ""
1687: "neg.b %0")
1688:
1689: (define_insn "negsf2"
1690: [(set (match_operand:SF 0 "general_operand" "=f")
1691: (neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
1692: "TARGET_FPU"
1693: "fneg.s %f1,%0")
1694:
1695:
1696: (define_insn "negdf2"
1697: [(set (match_operand:DF 0 "general_operand" "=f")
1698: (neg:DF (match_operand:DF 1 "general_operand" "fmF")))]
1699: "TARGET_FPU"
1700: "fneg.d %f1,%0")
1701:
1702:
1703: ;; Absolute value instructions
1704:
1705: (define_insn "abssf2"
1706: [(set (match_operand:SF 0 "general_operand" "=f")
1707: (abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
1708: "TARGET_FPU"
1709: "fabs.s %f1,%0")
1710:
1711: (define_insn "absdf2"
1712: [(set (match_operand:DF 0 "general_operand" "=f")
1713: (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
1714: "TARGET_FPU"
1715: "fabs.d %f1,%0")
1716:
1717:
1718: ;; one complement instructions
1719:
1720: (define_insn "one_cmplsi2"
1721: [(set (match_operand:SI 0 "general_operand" "=rm")
1722: (not:SI (match_operand:SI 1 "general_operand" "0")))]
1723: ""
1724: "not.w %0")
1725:
1726: (define_insn "one_cmplhi2"
1727: [(set (match_operand:HI 0 "general_operand" "=rm")
1728: (not:HI (match_operand:HI 1 "general_operand" "0")))]
1729: ""
1730: "not.h %0")
1731:
1732: (define_insn "one_cmplqi2"
1733: [(set (match_operand:QI 0 "general_operand" "=rm")
1734: (not:QI (match_operand:QI 1 "general_operand" "0")))]
1735: ""
1736: "not.b %0")
1737:
1738: ;; Optimized special case of shifting.
1739: ;; Must precede the general case.
1740:
1741: (define_insn ""
1742: [(set (match_operand:SI 0 "general_operand" "=r")
1743: (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
1744: (const_int 24)))]
1745: "GET_CODE (XEXP (operands[1], 0)) != POST_INC
1746: && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC"
1747: "mov:l %1.b,%0.w")
1748:
1749: (define_insn ""
1750: [(set (match_operand:SI 0 "general_operand" "=r")
1751: (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
1752: (const_int 24)))]
1753: "GET_CODE (XEXP (operands[1], 0)) != POST_INC
1754: && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC"
1755: "movu %1.b,%0.w")
1756:
1757: (define_insn ""
1758: [(set (cc0) (compare (match_operand:QI 0 "general_operand" "i")
1759: (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
1760: (const_int 24))))]
1761: "(GET_CODE (operands[0]) == CONST_INT
1762: && (INTVAL (operands[0]) & ~0xff) == 0)"
1763: "*
1764: {
1765: cc_status.flags |= CC_REVERSED;
1766: if (my_signed_comp (insn))
1767: return \"cmp.b %0,%1\";
1768: return \"cmpu.b %0,%1\";
1769: }")
1770:
1771: (define_insn ""
1772: [(set (cc0) (compare (lshiftrt:SI (match_operand:SI 0 "memory_operand" "m")
1773: (const_int 24))
1774: (match_operand:QI 1 "general_operand" "i")))]
1775: "(GET_CODE (operands[1]) == CONST_INT
1776: && (INTVAL (operands[1]) & ~0xff) == 0)"
1777: "*
1778: if (my_signed_comp (insn))
1779: return \"cmp.b %1,%0\";
1780: return \"cmpu.b %1,%0\";
1781: ")
1782:
1783: (define_insn ""
1784: [(set (cc0) (compare (match_operand:QI 0 "general_operand" "i")
1785: (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
1786: (const_int 24))))]
1787: "(GET_CODE (operands[0]) == CONST_INT
1788: && ((INTVAL (operands[0]) + 0x80) & ~0xff) == 0)"
1789: "*
1790: cc_status.flags |= CC_REVERSED;
1791: if (my_signed_comp (insn))
1792: return \"cmp.b %0,%1\";
1793: return \"cmpu.b %0,%1\";
1794: ")
1795:
1796: (define_insn ""
1797: [(set (cc0) (compare (ashiftrt:SI (match_operand:SI 0 "memory_operand" "m")
1798: (const_int 24))
1799: (match_operand:QI 1 "general_operand" "i")))]
1800: "(GET_CODE (operands[1]) == CONST_INT
1801: && ((INTVAL (operands[1]) + 0x80) & ~0xff) == 0)"
1802: "*
1803: if (my_signed_comp (insn))
1804: return \"cmp.b %1,%0\";
1805: return \"cmpu.b %1,%0\";
1806: ")
1807:
1808: ;; arithmetic shift instructions
1809: ;; We don't need the shift memory by 1 bit instruction
1810:
1811: (define_insn "ashlsi3"
1812: [(set (match_operand:SI 0 "general_operand" "=rm")
1813: (ashift:SI (match_operand:SI 1 "general_operand" "0")
1814: (match_operand:SI 2 "general_operand" "rmi")))]
1815: ""
1816: "sha.w %2,%0")
1817:
1818: (define_insn "ashlhi3"
1819: [(set (match_operand:HI 0 "general_operand" "=rm")
1820: (ashift:HI (match_operand:HI 1 "general_operand" "0")
1821: (match_operand:HI 2 "general_operand" "rmi")))]
1822: ""
1823: "sha.h %2,%0")
1824:
1825: (define_insn "ashlqi3"
1826: [(set (match_operand:QI 0 "general_operand" "=rm")
1827: (ashift:QI (match_operand:QI 1 "general_operand" "0")
1828: (match_operand:QI 2 "general_operand" "rmi")))]
1829: ""
1830: "sha.b %2,%0")
1831:
1832: ;; Arithmetic right shift on the Gmicro works by negating the shift count
1833:
1834: ;; ashiftrt -> ashift
1835: (define_expand "ashrsi3"
1836: [(set (match_operand:SI 0 "general_operand" "=rm")
1837: (ashift:SI (match_operand:SI 1 "general_operand" "0")
1838: (match_operand:SI 2 "general_operand" "rmi")))]
1839: ""
1840: "{ operands[2] = negate_rtx (SImode, operands[2]); }")
1841:
1842: ;; ashiftrt -> ashift
1843: (define_expand "ashrhi3"
1844: [(set (match_operand:HI 0 "general_operand" "=rm")
1845: (ashift:HI (match_operand:HI 1 "general_operand" "0")
1846: (match_operand:HI 2 "general_operand" "rmi")))]
1847: ""
1848: " { operands[2] = negate_rtx (HImode, operands[2]); }")
1849:
1850: ;; ashiftrt -> ashift
1851: (define_expand "ashrqi3"
1852: [(set (match_operand:QI 0 "general_operand" "=rm")
1853: (ashift:QI (match_operand:QI 1 "general_operand" "0")
1854: (match_operand:QI 2 "general_operand" "rmi")))]
1855: ""
1856: " { operands[2] = negate_rtx (QImode, operands[2]); }")
1857:
1858: ;; logical shift instructions
1859:
1.1.1.2 root 1860: ;; Logical right shift on the gmicro works by negating the shift count,
1861: ;; then emitting a right shift with the shift count negated. This means
1862: ;; that all actual shift counts in the RTL will be positive. This
1863: ;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
1864: ;; which isn't valid.
1.1 root 1865:
1.1.1.2 root 1866: (define_expand "lshrsi3"
1867: [(set (match_operand:SI 0 "general_operand" "=g")
1868: (lshiftrt:SI (match_operand:SI 1 "general_operand" "g")
1869: (match_operand:SI 2 "general_operand" "g")))]
1.1 root 1870: ""
1.1.1.2 root 1871: "
1872: {
1873: if (GET_CODE (operands[2]) != CONST_INT)
1874: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1875: }")
1.1 root 1876:
1.1.1.2 root 1877: (define_insn ""
1878: [(set (match_operand:SI 0 "general_operand" "=rm")
1879: (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1880: (match_operand:SI 2 "const_int_operand" "n")))]
1.1 root 1881: ""
1.1.1.2 root 1882: "shl.w %n2,%0")
1.1 root 1883:
1.1.1.2 root 1884: (define_insn ""
1.1 root 1885: [(set (match_operand:SI 0 "general_operand" "=rm")
1.1.1.2 root 1886: (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1887: (neg:SI (match_operand:SI 2 "general_operand" "rm"))))]
1.1 root 1888: ""
1.1.1.2 root 1889: "shl.w %2,%0")
1.1 root 1890:
1891: (define_expand "lshrhi3"
1.1.1.2 root 1892: [(set (match_operand:HI 0 "general_operand" "=g")
1893: (lshiftrt:HI (match_operand:HI 1 "general_operand" "g")
1894: (match_operand:HI 2 "general_operand" "g")))]
1895: ""
1896: "
1897: {
1898: if (GET_CODE (operands[2]) != CONST_INT)
1899: operands[2] = gen_rtx (NEG, HImode, negate_rtx (HImode, operands[2]));
1900: }")
1901:
1902: (define_insn ""
1.1 root 1903: [(set (match_operand:HI 0 "general_operand" "=rm")
1.1.1.2 root 1904: (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1905: (match_operand:HI 2 "const_int_operand" "n")))]
1.1 root 1906: ""
1.1.1.2 root 1907: "shl.h %n2,%0")
1908:
1909: (define_insn ""
1910: [(set (match_operand:HI 0 "general_operand" "=rm")
1911: (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1912: (neg:HI (match_operand:HI 2 "general_operand" "rm"))))]
1913: ""
1914: "shl.h %2,%0")
1.1 root 1915:
1916: (define_expand "lshrqi3"
1.1.1.2 root 1917: [(set (match_operand:QI 0 "general_operand" "=g")
1918: (lshiftrt:QI (match_operand:QI 1 "general_operand" "g")
1919: (match_operand:QI 2 "general_operand" "g")))]
1920: ""
1921: "
1922: {
1923: if (GET_CODE (operands[2]) != CONST_INT)
1924: operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
1925: }")
1926:
1927: (define_insn ""
1.1 root 1928: [(set (match_operand:QI 0 "general_operand" "=rm")
1.1.1.2 root 1929: (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
1930: (match_operand:QI 2 "const_int_operand" "n")))]
1.1 root 1931: ""
1.1.1.2 root 1932: "shl.b %n2,%0")
1933:
1934: (define_insn ""
1935: [(set (match_operand:QI 0 "general_operand" "=rm")
1936: (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
1937: (neg:QI (match_operand:QI 2 "general_operand" "rm"))))]
1938: ""
1939: "shl.b %2,%0")
1.1 root 1940:
1941: ;; rotate instructions
1942:
1943: (define_insn "rotlsi3"
1944: [(set (match_operand:SI 0 "general_operand" "=rm")
1945: (rotate:SI (match_operand:SI 1 "general_operand" "0")
1946: (match_operand:SI 2 "general_operand" "rmi")))]
1947: ""
1948: "rol.w %2,%0")
1949:
1950: (define_insn "rotlhi3"
1951: [(set (match_operand:HI 0 "general_operand" "=rm")
1952: (rotate:HI (match_operand:HI 1 "general_operand" "0")
1953: (match_operand:HI 2 "general_operand" "rmi")))]
1954: ""
1955: "rol.h %2,%0")
1956:
1957: (define_insn "rotlqi3"
1958: [(set (match_operand:QI 0 "general_operand" "=rm")
1959: (rotate:QI (match_operand:QI 1 "general_operand" "0")
1960: (match_operand:QI 2 "general_operand" "rmi")))]
1961: ""
1962: "rol.b %2,%0")
1963:
1964: (define_expand "rotrsi3"
1965: [(set (match_operand:SI 0 "general_operand" "=rm")
1966: (rotatert:SI (match_operand:SI 1 "general_operand" "0")
1967: (match_operand:SI 2 "general_operand" "rmi")))]
1968: ""
1969: " { operands[2] = negate_rtx (SImode, operands[2]); }")
1970:
1971: (define_expand "rotrhi3"
1972: [(set (match_operand:HI 0 "general_operand" "=rm")
1973: (rotatert:HI (match_operand:HI 1 "general_operand" "0")
1974: (match_operand:HI 2 "general_operand" "rmi")))]
1975: ""
1976: " { operands[2] = negate_rtx (HImode, operands[2]); }")
1977:
1978: (define_expand "rotrqi3"
1979: [(set (match_operand:QI 0 "general_operand" "=rm")
1980: (rotatert:QI (match_operand:QI 1 "general_operand" "0")
1981: (match_operand:QI 2 "general_operand" "rmi")))]
1982: ""
1983: " { operands[2] = negate_rtx (QImode, operands[2]); }")
1984:
1985: ;; Special cases of bit-field insns which we should
1986: ;; recognize in preference to the general case.
1987: ;; These handle aligned 8-bit and 16-bit fields,
1988: ;; which can usually be done with move instructions.
1989:
1990: ;; Should I add mode_dependent_address_p ????
1991:
1992: (define_insn ""
1993: [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+rm")
1994: (match_operand:SI 1 "immediate_operand" "i")
1995: (match_operand:SI 2 "immediate_operand" "i"))
1996: (match_operand:SI 3 "general_operand" "rm"))]
1997: "TARGET_BITFIELD
1998: && GET_CODE (operands[1]) == CONST_INT
1999: && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
2000: && GET_CODE (operands[2]) == CONST_INT
2001: && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
2002: && (GET_CODE (operands[0]) != REG
2003: || ( INTVAL (operands[1]) + INTVAL (operands[2]) == 32))"
2004: "*
2005: {
2006: if (GET_CODE (operands[3]) == MEM)
2007: operands[3] = adj_offsettable_operand (operands[3],
2008: (32 - INTVAL (operands[1])) / 8);
2009:
2010: if (GET_CODE (operands[0]) == REG)
2011: {
2012: if (INTVAL (operands[1]) == 8)
2013: return \"movu %3.b,%0.w\";
2014: return \"movu %3.h,%0.w\";
2015: }
2016: else
2017: {
2018: operands[0]
2019: = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
2020: if (INTVAL (operands[1]) == 8)
2021: return \"mov.b %3,%0\";
2022: return \"mov.h %3,%0\";
2023: }
2024: }")
2025:
2026: (define_insn ""
2027: [(set (match_operand:SI 0 "general_operand" "=&r")
2028: (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "rm")
2029: (match_operand:SI 2 "immediate_operand" "i")
2030: (match_operand:SI 3 "immediate_operand" "i")))]
2031: "TARGET_BITFIELD
2032: && GET_CODE (operands[2]) == CONST_INT
2033: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
2034: && GET_CODE (operands[3]) == CONST_INT
2035: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0"
2036: "*
2037: {
2038: if (!REG_P (operands[1]))
2039: operands[1]
2040: = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
2041:
2042: if (REG_P (operands[0]))
2043: {
2044: if (REG_P (operands[1]))
2045: {
2046: if (INTVAL (operands[2]) == 8)
2047: { /* width == 8 */
2048: switch (INTVAL (operands[3]))
2049: {
2050: case 0:
2051: return \"mov.w %1,%0;shl.w #-24,%0\";
2052: break;
2053: case 8:
2054: return \"mov.w %1,%0;shl.w #8,%0;shl.w #-24,%0\";
2055: break;
2056: case 16:
2057: return \"mov.w %1,%0;shl.w #16,%0;shl.w #-24,%0\";
2058: break;
2059: case 24:
2060: return \"movu %1.b,%0.w\";
2061: break;
2062: default:
2063: myabort (2);
2064: }
2065: }
2066: else
2067: {
2068: switch (INTVAL (operands[3]))
2069: {
2070: case 0:
2071: return \"mov.w %1,%0;shl.w #-16,%0\";
2072: break;
2073: case 16:
2074: return \"movu %1.h,%0.w\";
2075: break;
2076: default:
2077: myabort (3);
2078: }
2079: }
2080: }
2081: else
2082: {
2083: if (INTVAL (operands[2]) == 8)
2084: return \"movu %1.h,%0.w\";
2085: else
2086: return \"movu %1.b,%0.w\";
2087: }
2088: }
2089: else
2090: { /* op[0] == MEM */
2091: if (INTVAL (operands[2]) == 8)
2092: return \"movu %1.b,%0.w\";
2093: return \"movu %1.h,%0.w\";
2094: }
2095: }")
2096:
2097: (define_insn ""
2098: [(set (match_operand:SI 0 "general_operand" "=r")
2099: (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
2100: (match_operand:SI 2 "immediate_operand" "i")
2101: (match_operand:SI 3 "immediate_operand" "i")))]
2102: "TARGET_BITFIELD
2103: && GET_CODE (operands[2]) == CONST_INT
2104: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
2105: && GET_CODE (operands[3]) == CONST_INT
2106: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0"
2107: "*
2108: {
2109: if (!REG_P (operands[1]))
2110: operands[1]
2111: = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
2112:
2113: if (REG_P (operands[0]))
2114: {
2115: if (REG_P (operands[1]))
2116: {
2117: if (INTVAL (operands[2]) == 8)
2118: { /* width == 8 */
2119: switch (INTVAL (operands[3]))
2120: {
2121: case 0:
2122: return \"mov.w %1,%0;sha.w #-24,%0\";
2123: break;
2124: case 8:
2125: return \"mov.w %1,%0;shl.w #8,%0;sha.w #-24,%0\";
2126: break;
2127: case 16:
2128: return \"mov.w %1,%0;shl.w #16,%0;sha.w #-24,%0\";
2129: break;
2130: case 24:
2131: return \"mov %1.b,%0.w\";
2132: break;
2133: default:
2134: myabort (4);
2135: }
2136: }
2137: else
2138: {
2139: switch (INTVAL (operands[3]))
2140: {
2141: case 0:
2142: return \"mov.w %1,%0;sha.w #-16,%0\";
2143: break;
2144: case 16:
2145: return \"mov %1.h,%0.w\";
2146: break;
2147: default:
2148: myabort (5);
2149: }
2150: }
2151: }
2152: else
2153: {
2154: if (INTVAL (operands[2]) == 8)
2155: return \"mov %1.h,%0.w\";
2156: else
2157: return \"mov %1.b,%0.w\";
2158: }
2159: }
2160: else
2161: { /* op[0] == MEM */
2162: if (INTVAL (operands[2]) == 8)
2163: return \"mov %1.b,%0.w\";
2164: return \"mov %1.h,%0.w\";
2165: }
2166: }")
2167:
2168: ;; Bit field instructions, general cases.
2169: ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
2170: ;; so that its address is reloaded.
2171:
2172: ;; extv dest:SI src(:QI/:SI) width:SI pos:SI
2173: ;; r.w m r.w/# rmi
2174: ;; %0 %1 %2 %3
2175:
2176: (define_insn "extv"
2177: [(set (match_operand:SI 0 "general_operand" "=r")
2178: (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "m")
2179: (match_operand:SI 2 "general_operand" "ri")
2180: (match_operand:SI 3 "general_operand" "rmi")))]
2181: "TARGET_BITFIELD"
2182: "bfext %3,%2,%1,%0")
2183:
2184:
2185: (define_insn "extzv"
2186: [(set (match_operand:SI 0 "general_operand" "=r")
2187: (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "m")
2188: (match_operand:SI 2 "general_operand" "ri")
2189: (match_operand:SI 3 "general_operand" "rmi")))]
2190: "TARGET_BITFIELD"
2191: "bfextu %3,%2,%1,%0")
2192:
2193: ;; There is no insn on the Gmicro to NOT/SET/CLR bitfield.
2194:
2195:
2196: ;; insv dest(BF):QI/SI width:SI pos:SI src:SI
2197: ;; m r.w rmi r.w/i
2198: ;; 0 1 2 3
2199:
2200:
2201: (define_insn "insv"
2202: [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+m,m")
2203: (match_operand:SI 1 "general_operand" "r,i")
2204: (match_operand:SI 2 "general_operand" "rmi,i"))
2205: (match_operand:SI 3 "general_operand" "ri,ri"))]
2206: "TARGET_BITFIELD"
2207: "bfinsu %3,%2,%1,%0")
2208: ;;; bfins/bfinsu ????????
2209:
2210: ;; == == == == == == == == == == == == ==
2211:
2212: ;; Now recognize bit field insns that operate on registers
2213: ;; (or at least were intended to do so).
2214:
2215: ;; On the Gmicro/300,
2216: ;; bitfield instructions are not applicable to registers ;-<
2217: ;; But I write the register cases, because without them the gcc
2218: ;; seems to use "and" instruction with some other instructions
2219: ;; instead of using a shift instruction.
2220: ;; It is because on many processors shift instructions are slower.
2221: ;; On the Gmicro/300 which has a barrel shifter,
2222: ;; it is faster to use a shift instruction.
2223: ;;
2224: ;; Restricts width and offset to be immediates.
2225: ;;
2226: (define_insn ""
2227: [(set (match_operand:SI 0 "general_operand" "=r")
2228: (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "r")
2229: (match_operand:SI 2 "immediate_operand" "i")
2230: (match_operand:SI 3 "immediate_operand" "i")))]
2231: "TARGET_BITFIELD"
2232: "*
2233: {
2234: if (REGNO (operands[0]) != REGNO (operands[1]))
2235: output_asm_insn (\"mov.w %1,%0\", operands);
2236: if (INTVAL (operands[3]) != 0)
2237: output_asm_insn (\"shl.w %3,%0\", operands);
2238: operands[2] = gen_rtx (CONST_INT, VOIDmode, -(32 - INTVAL (operands[2])));
2239: return \"sha.w %3,%0\";
2240: }")
2241:
2242:
2243: (define_insn ""
2244: [(set (match_operand:SI 0 "general_operand" "=r")
2245: (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "r")
2246: (match_operand:SI 2 "immediate_operand" "i")
2247: (match_operand:SI 3 "immediate_operand" "i")))]
2248: "TARGET_BITFIELD"
2249: "*
2250: {
2251: if (REGNO (operands[0]) != REGNO (operands[1]))
2252: output_asm_insn (\"mov.w %1,%0\", operands);
2253: if (INTVAL (operands[3]) != 0)
2254: output_asm_insn (\"shl.w %3,%0\", operands);
2255: operands[2] = gen_rtx (CONST_INT, VOIDmode, -(32 - INTVAL (operands[2])));
2256: return \"shl.w %3,%0\";
2257: }")
2258:
2259:
2260: ;; There are more descriptions for m68k, but not yet for the Gmicro.
2261: ;;
2262:
2263: ;; Basic conditional jump instructions.
2264:
2265:
2266: (define_insn "beq"
2267: [(set (pc)
2268: (if_then_else (eq (cc0)
2269: (const_int 0))
2270: (label_ref (match_operand 0 "" ""))
2271: (pc)))]
2272: ""
2273: "*
2274: {
2275: OUTPUT_JUMP (\"beq %b0\", \"fbeq %b0\", \"beq %b0\");
2276: }")
2277:
2278: (define_insn "bne"
2279: [(set (pc)
2280: (if_then_else (ne (cc0)
2281: (const_int 0))
2282: (label_ref (match_operand 0 "" ""))
2283: (pc)))]
2284: ""
2285: "*
2286: {
2287: OUTPUT_JUMP (\"bne %b0\", \"fbne %b0\", \"bne %b0\");
2288: }")
2289:
2290: (define_insn "bgt"
2291: [(set (pc)
2292: (if_then_else (gt (cc0)
2293: (const_int 0))
2294: (label_ref (match_operand 0 "" ""))
2295: (pc)))]
2296: ""
2297: "*
2298: OUTPUT_JUMP (\"bgt %b0\", \"fbgt %b0\", 0);
2299: ")
2300:
2301: (define_insn "bgtu"
2302: [(set (pc)
2303: (if_then_else (gtu (cc0)
2304: (const_int 0))
2305: (label_ref (match_operand 0 "" ""))
2306: (pc)))]
2307: ""
2308: "bgt %b0")
2309:
2310: (define_insn "blt"
2311: [(set (pc)
2312: (if_then_else (lt (cc0)
2313: (const_int 0))
2314: (label_ref (match_operand 0 "" ""))
2315: (pc)))]
2316: ""
2317: "*
2318: OUTPUT_JUMP (\"blt %b0\", \"fblt %b0\", \"bms %b0\");
2319: ")
2320:
2321: ;; bms ?????
2322: ;;
2323:
2324: (define_insn "bltu"
2325: [(set (pc)
2326: (if_then_else (ltu (cc0)
2327: (const_int 0))
2328: (label_ref (match_operand 0 "" ""))
2329: (pc)))]
2330: ""
2331: "blt %b0")
2332:
2333: (define_insn "bge"
2334: [(set (pc)
2335: (if_then_else (ge (cc0)
2336: (const_int 0))
2337: (label_ref (match_operand 0 "" ""))
2338: (pc)))]
2339: ""
2340: "*
2341: OUTPUT_JUMP (\"bge %b0\", \"fbge %b0\", \"bmc %b0\");
2342: ")
2343:
2344: ;; bmc ??
2345:
2346: (define_insn "bgeu"
2347: [(set (pc)
2348: (if_then_else (geu (cc0)
2349: (const_int 0))
2350: (label_ref (match_operand 0 "" ""))
2351: (pc)))]
2352: ""
2353: "bge %b0")
2354:
2355: (define_insn "ble"
2356: [(set (pc)
2357: (if_then_else (le (cc0)
2358: (const_int 0))
2359: (label_ref (match_operand 0 "" ""))
2360: (pc)))]
2361: ""
2362: "ble %b0")
2363:
2364: (define_insn "bleu"
2365: [(set (pc)
2366: (if_then_else (leu (cc0)
2367: (const_int 0))
2368: (label_ref (match_operand 0 "" ""))
2369: (pc)))]
2370: ""
2371: "ble %b0")
2372:
2373: ;; Negated conditional jump instructions.
2374:
2375: (define_insn ""
2376: [(set (pc)
2377: (if_then_else (eq (cc0)
2378: (const_int 0))
2379: (pc)
2380: (label_ref (match_operand 0 "" ""))))]
2381: ""
2382: "*
2383: {
2384: OUTPUT_JUMP (\"bne %b0\", \"fbne %b0\", \"bne %b0\");
2385: }")
2386:
2387: (define_insn ""
2388: [(set (pc)
2389: (if_then_else (ne (cc0)
2390: (const_int 0))
2391: (pc)
2392: (label_ref (match_operand 0 "" ""))))]
2393: ""
2394: "*
2395: {
2396: OUTPUT_JUMP (\"beq %b0\", \"fbeq %b0\", \"beq %b0\");
2397: }")
2398:
2399: (define_insn ""
2400: [(set (pc)
2401: (if_then_else (gt (cc0)
2402: (const_int 0))
2403: (pc)
2404: (label_ref (match_operand 0 "" ""))))]
2405: ""
2406: "*
2407: OUTPUT_JUMP (\"ble %b0\", \"fbngt %b0\", 0);
2408: ")
2409: ;; fbngt ???
2410:
2411: (define_insn ""
2412: [(set (pc)
2413: (if_then_else (gtu (cc0)
2414: (const_int 0))
2415: (pc)
2416: (label_ref (match_operand 0 "" ""))))]
2417: ""
2418: "ble %b0")
2419:
2420: (define_insn ""
2421: [(set (pc)
2422: (if_then_else (lt (cc0)
2423: (const_int 0))
2424: (pc)
2425: (label_ref (match_operand 0 "" ""))))]
2426: ""
2427: "*
2428: OUTPUT_JUMP (\"bge %b0\", \"fbnlt %b0\", \"jbmc %b0\");
2429: ")
2430:
2431: (define_insn ""
2432: [(set (pc)
2433: (if_then_else (ltu (cc0)
2434: (const_int 0))
2435: (pc)
2436: (label_ref (match_operand 0 "" ""))))]
2437: ""
2438: "blt %b0")
2439:
2440: (define_insn ""
2441: [(set (pc)
2442: (if_then_else (ge (cc0)
2443: (const_int 0))
2444: (pc)
2445: (label_ref (match_operand 0 "" ""))))]
2446: ""
2447: "*
2448: OUTPUT_JUMP (\"blt %b0\", \"fbnge %b0\", \"jbms %b0\");
2449: ")
2450:
2451: (define_insn ""
2452: [(set (pc)
2453: (if_then_else (geu (cc0)
2454: (const_int 0))
2455: (pc)
2456: (label_ref (match_operand 0 "" ""))))]
2457: ""
2458: "blt %b0")
2459: ;; ????
2460:
2461: (define_insn ""
2462: [(set (pc)
2463: (if_then_else (le (cc0)
2464: (const_int 0))
2465: (pc)
2466: (label_ref (match_operand 0 "" ""))))]
2467: ""
2468: "*
2469: OUTPUT_JUMP (\"bgt %b0\", \"fbnle %b0\", 0);
2470: ")
2471:
2472: (define_insn ""
2473: [(set (pc)
2474: (if_then_else (leu (cc0)
2475: (const_int 0))
2476: (pc)
2477: (label_ref (match_operand 0 "" ""))))]
2478: ""
2479: "bgt %b0")
2480:
2481: ;; Unconditional and other jump instructions
2482: (define_insn "jump"
2483: [(set (pc)
2484: (label_ref (match_operand 0 "" "")))]
2485: ""
2486: "bra %b0")
2487:
2488: (define_insn "tablejump"
2489: [(set (pc)
2490: (plus:SI (pc) (match_operand:SI 0 "general_operand" "r")))
2491: (use (label_ref (match_operand 1 "" "")))]
2492: ""
2493: "jmp @(pc:b,4:4,%0)")
2494:
2495: ;;
2496: ;; Should Add code for "ACB", "SCB". !!! ????
2497: ;; See m68k.h (dbra)
2498: ;;
2499:
2500: ;; Call subroutine with no return value.
2501: (define_insn "call"
2502: [(call (match_operand:QI 0 "general_operand" "m")
2503: (match_operand:SI 1 "general_operand" "rmi"))]
2504: ;; Operand 1 not really used on the Gmicro.
2505:
2506: ""
2507: "*
2508: {
2509: if (GET_CODE (operands[0]) == MEM
2510: && GET_CODE (XEXP (operands[0],0)) == SYMBOL_REF)
2511: return \"bsr %b0\";
2512: return \"jsr %0\";
2513: }")
2514:
2515: ;; Call subroutine, returning value in operand 0
2516: ;; (which must be a hard register).
2517: (define_insn "call_value"
2518: [(set (match_operand 0 "" "=rf")
2519: (call (match_operand:QI 1 "general_operand" "m")
2520: (match_operand:SI 2 "general_operand" "rmi")))]
2521: ;; Operand 2 not really used on the Gmicro.
2522: ""
2523: "*
2524: {
2525: if (GET_CODE (operands[1]) == MEM
2526: && GET_CODE (XEXP (operands[1],0)) == SYMBOL_REF)
2527: return \"bsr %b1\";
2528: return \"jsr %1\";
2529: }")
2530:
2531: ;; Call subroutine returning any type.
2532:
2533: (define_expand "untyped_call"
2534: [(parallel [(call (match_operand 0 "" "")
2535: (const_int 0))
2536: (match_operand 1 "" "")
2537: (match_operand 2 "" "")])]
2538: ""
2539: "
2540: {
2541: int i;
2542:
2543: emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
2544:
2545: for (i = 0; i < XVECLEN (operands[2], 0); i++)
2546: {
2547: rtx set = XVECEXP (operands[2], 0, i);
2548: emit_move_insn (SET_DEST (set), SET_SRC (set));
2549: }
2550:
2551: /* The optimizer does not know that the call sets the function value
2552: registers we stored in the result block. We avoid problems by
2553: claiming that all hard registers are used and clobbered at this
2554: point. */
2555: emit_insn (gen_blockage ());
2556:
2557: DONE;
2558: }")
2559:
2560: ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
2561: ;; all of memory. This blocks insns from being moved across this point.
2562:
2563: (define_insn "blockage"
2564: [(unspec_volatile [(const_int 0)] 0)]
2565: ""
2566: "")
2567:
2568: (define_insn "nop"
2569: [(const_int 0)]
2570: ""
2571: "nop")
2572:
2573: ;; Turned off because the general move-an-address pattern handles it.
2574: ;;
2575: ;; Thus goes after the move instructions
2576: ;; because the move instructions are better (require no spilling)
2577: ;; when they can apply.
2578: ;; After add/sub now !!
2579:
2580: ;(define_insn "pushasi"
2581: ; [(set (match_operand:SI 0 "push_operand" "=m")
2582: ; (match_operand:SI 1 "address_operand" "p"))]
2583: ; ""
2584: ; "*
2585: ;{
2586: ; if (GET_CODE (operands[1]) == CONST_INT)
2587: ; return push_imm_word (INTVAL (operands[1]), operands[0]);
2588: ; if (CONSTANT_P (operands[1]))
2589: ; return \"mov.w %1,%-\";
2590: ; if (GET_CODE (operands[1]) == REG)
2591: ; return \"mov.w %1,%-\";
2592: ; else if (GET_CODE (operands[1]) == MEM)
2593: ; {
2594: ; return \"mov.w %1,%-\";
2595: ; }
2596: ; else
2597: ; return \"mova.w %p1,%-\";
2598: ;}")
2599:
2600: ;; This should not be used unless the add/sub insns can't be.
2601:
2602: /* mova.[whq] 89.08.11 for test M.Yuhara */
2603: ;(define_insn ""
2604: ; [(set (match_operand:SI 0 "general_operand" "=rm")
2605: ; (address (match_operand:SI 1 "address_operand" "p")))]
2606: ; ""
2607: ; "*
2608: ;{
2609: ; if (GET_CODE (operands[1]) == CONST_INT)
2610: ; return mov_imm_word (INTVAL (operands[1]), operands[0]);
2611: ; if (CONSTANT_P (operands[1]))
2612: ; return \"mov.w %1,%0\";
2613: ; if (GET_CODE (operands[1]) == REG)
2614: ; return \"mov.w %1,%0\";
2615: ; else if (GET_CODE (operands[1]) == MEM) {
2616: ; operands[1] = XEXP (operands[1],0);
2617: ; return \"mov.w %1,%0\";
2618: ; }
2619: ; else
2620: ; return \"mova.w %p1,%0\";
2621: ;}")
2622:
2623:
2624: (define_insn ""
2625: [(set (match_operand:SI 0 "general_operand" "=rm")
2626: (address (match_operand:HI 1 "address_operand" "")))]
2627: ""
2628: "*
2629: {
2630: if (GET_CODE (operands[1]) == CONST_INT)
2631: return mov_imm_word (INTVAL (operands[1]), operands[0]);
2632: if (CONSTANT_P (operands[1]))
2633: return \"mov.w %1,%0\";
2634: if (GET_CODE (operands[1]) == REG)
2635: return \"mov.w %1,%0\";
2636: else if (GET_CODE (operands[1]) == MEM)
2637: {
2638: operands[1] = XEXP (operands[1],0);
2639: return \"mov.w %1,%0\"; /* OK ? */
2640: }
2641: else
2642: return \"mova.w %p1,%0\";
2643: }")
2644:
2645: ;(define_insn ""
2646: ; [(set (match_operand:SI 0 "general_operand" "=rm")
2647: ; (match_operand:QI 1 "address_operand" "p"))]
2648: ; ""
2649: ; "*
2650: ;{
2651: ; if (push_operand (operands[0], SImode))
2652: ; return \"mova %1,%-\";
2653: ; return \"mova %1,%0\";
2654: ;}")
2655:
2656: ;(define_insn ""
2657: ; [(set (match_operand:SI 0 "general_operand" "=rm")
2658: ; (match_operand:QI 1 "address_operand" "p"))]
2659: ; ""
2660: ; "*
2661: ;{
2662: ; if (CONSTANT_P (operands[1]))
2663: ; return \"mov.w %1,%0\";
2664: ; else if (GET_CODE (operands[1]) == REG)
2665: ; return \"mov.w %1,%0\";
2666: ; else if (GET_CODE (operands[1]) == MEM)
2667: ; {
2668: ; operands[1] = XEXP (operands[1],0);
2669: ; return \"mov.w %1,%0 ; OK?\";
2670: ; }
2671: ; else if (GET_CODE (operands[0]) == REG
2672: ; && GET_CODE (operands[1]) == PLUS)
2673: ; {
2674: ; rtx xreg, xdisp;
2675: ;
2676: ; if (GET_CODE (XEXP (operands[1], 0)) == REG
2677: ; && REGNO (XEXP (operands[1], 0)) == REGNO (operands[0]))
2678: ; {
2679: ; xreg = XEXP (operands[1], 0);
2680: ; xdisp = XEXP (operands[1],1);
2681: ; }
2682: ; else
2683: ; {
2684: ; xreg = XEXP (operands[1], 1);
2685: ; xdisp = XEXP (operands[1],0);
2686: ; }
2687: ;
2688: ; if (GET_CODE (xreg) == REG
2689: ; && REGNO (xreg) == REGNO (operands[0])
2690: ; && (CONSTANT_P (xdisp) || GET_CODE (xdisp) == REG))
2691: ; {
2692: ; operands[1] = xdisp;
2693: ; if (CONSTANT_P (xdisp))
2694: ; return add_imm_word (INTVAL (xdisp), xreg, &operands[1]);
2695: ; else
2696: ; return \"add.w %1,%0\";
2697: ; }
2698: ; }
2699: ; return \"mova.w %p1,%0\";
2700: ;}")
2701:
2702: ;; This is the first machine-dependent peephole optimization.
2703: ;; It is useful when a floating value is returned from a function call
2704: ;; and then is moved into an FP register.
2705: ;; But it is mainly intended to test the support for these optimizations.
2706:
2707: (define_peephole
2708: [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
2709: (set (match_operand:DF 0 "register_operand" "=f")
2710: (match_operand:DF 1 "register_operand" "r"))]
2711: "FPU_REG_P (operands[0]) && ! FPU_REG_P (operands[1])"
2712: "*
2713: {
2714: rtx xoperands[2];
2715: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2716: output_asm_insn (\"mov.w %1,@sp\", xoperands);
2717: output_asm_insn (\"mov.w %1,%-\", operands);
2718: return \"fmov.d %+,%0\";
2719: }
2720: ")
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