--- gcc/config/h8300/h8300.md	2018/04/24 18:21:42	1.1.1.2
+++ gcc/config/h8300/h8300.md	2018/04/24 18:29:13	1.1.1.3
@@ -1,5 +1,5 @@
 ;; GCC machine description for Hitachi H8/300
-;; Copyright (C) 1992, 1993, 1994 Free Software Foundation, Inc.
+;; Copyright (C) 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
 
 ;;   Contributed by Steve Chamberlain (sac@cygnus.com),
 ;;   Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
@@ -18,7 +18,8 @@
 
 ;; You should have received a copy of the GNU General Public License
 ;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
 
 
 ;; The original PO technology requires these to be ordered by speed,
@@ -382,8 +383,8 @@
    (set_attr "cc" "set")])
 
 (define_insn "movsf_h8300h"
-  [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<")
-	(match_operand:SF 1 "general_operand_src" "I,r,ion,r,r"))]
+  [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
+	(match_operand:SF 1 "general_operand_src" "I,r,ion,r,r,>"))]
   "TARGET_H8300H
    && (register_operand (operands[0], SFmode)
        || register_operand (operands[1], SFmode))"
@@ -392,9 +393,10 @@
    mov.l	%S1,%S0
    mov.l	%S1,%S0
    mov.l	%S1,%S0
+   mov.l	%S1,%S0
    mov.l	%S1,%S0"
   [(set_attr "type" "move")
-   (set_attr "length" "2,2,8,8,4")
+   (set_attr "length" "2,2,8,8,4,4")
    (set_attr "cc" "set")])
 
 ;; ----------------------------------------------------------------------
@@ -1269,7 +1271,7 @@
   "")
 
 (define_insn "tablejump_h8300"
-  [(set (pc) (match_operand:HI 0 "register_operand" ""))
+  [(set (pc) (match_operand:HI 0 "register_operand" "r"))
    (use (label_ref (match_operand 1 "" "")))]
   "TARGET_H8300"
   "jmp	@%0"
@@ -1278,7 +1280,7 @@
    (set_attr "length" "2")])
 
 (define_insn "tablejump_h8300h"
-  [(set (pc) (match_operand:SI 0 "register_operand" ""))
+  [(set (pc) (match_operand:SI 0 "register_operand" "r"))
    (use (label_ref (match_operand 1 "" "")))]
   "TARGET_H8300H"
   "jmp	@%0"
@@ -1629,7 +1631,7 @@
 ;; BIT FIELDS
 ;; -----------------------------------------------------------------
 ;; The H8/300 has given 1/8th of its opcode space to bitfield
-;; instuctions so let's use them as well as we can
+;; instructions so let's use them as well as we can
 
 ;; BCC and BCS patterns.
 
@@ -1851,7 +1853,7 @@
   if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) >= 8)
     FAIL;
 
-  /* The bit_operand predicate accepts any memory durint RTL generation, but
+  /* The bit_operand predicate accepts any memory during RTL generation, but
      only 'U' memory afterwards, so if this is a MEM operand, we must force
      it to be valid for 'U' by reloading the address.  */
 
@@ -1895,7 +1897,7 @@
   if (INTVAL (operands[2]) != 1)
     FAIL;
 
-  /* The bit_operand predicate accepts any memory durint RTL generation, but
+  /* The bit_operand predicate accepts any memory during RTL generation, but
      only 'U' memory afterwards, so if this is a MEM operand, we must force
      it to be valid for 'U' by reloading the address.  */
 
@@ -2165,42 +2167,42 @@
 
 (define_insn "fancy_btst"
   [(set (pc)
-	(if_then_else (eq (zero_extract:HI (zero_extend:HI (match_operand:QI 0 "general_operand" "Ur"))
+	(if_then_else (eq (zero_extract:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "Ur"))
 					   (const_int 1)
-					   (match_operand:HI 1 "nonmemory_operand" "rn"))
+					   (match_operand:HI 2 "nonmemory_operand" "rn"))
 			  (const_int 0))
-		      (label_ref (match_operand 2 "" ""))
+		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
   "*
 {
   if (get_attr_length (insn) == 2)
-    return \"btst	%X1,%X0\;beq	%l2\";
+    return \"btst	%X2,%X1\;beq	%l0\";
   else if (get_attr_length (insn) == 4)
-    return \"btst	%X1,%X0\;beq	%l2:16\";
+    return \"btst	%X2,%X1\;beq	%l0:16\";
   else
-    return \"btst	%X1,%X0\;bne	%L0\;jmp	@%l2\;%L0:\";
+    return \"btst	%X2,%X1\;bne	%L1\;jmp	@%l0\;%L1:\";
 }"
   [(set_attr "type" "branch")
    (set_attr "cc" "clobber")])
 
 (define_insn "fancy_btst1"
   [(set (pc)
-	(if_then_else (ne (zero_extract:HI (zero_extend:HI (match_operand:QI 0 "general_operand" "Ur"))
+	(if_then_else (ne (zero_extract:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "Ur"))
 					   (const_int 1)
-					   (match_operand:HI 1 "nonmemory_operand" "rn"))
+					   (match_operand:HI 2 "nonmemory_operand" "rn"))
 			  (const_int 0))
-		      (label_ref (match_operand 2 "" ""))
+		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
   "*
 {
   if (get_attr_length (insn) == 2)
-    return \"btst	%X1,%X0\;bne	%l2\";
+    return \"btst	%X2,%X1\;bne	%l0\";
   else if (get_attr_length (insn) == 4)
-    return \"btst	%X1,%X0\;bne	%l2:16\";
+    return \"btst	%X2,%X1\;bne	%l0:16\";
   else
-    return \"btst	%X1,%X0\;beq	%L0\;jmp	@%l2\;%L0:\";
+    return \"btst	%X2,%X1\;beq	%L1\;jmp	@%l0\;%L1:\";
 }"
   [(set_attr "type" "branch")
    (set_attr "cc" "clobber")])