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1.1.1.2 ! root 1: ;; GCC machine description for Hitachi H8/300 ! 2: ;; Copyright (C) 1992, 1993, 1994 Free Software Foundation, Inc. ! 3: ! 4: ;; Contributed by Steve Chamberlain ([email protected]), ! 5: ;; Jim Wilson ([email protected]), and Doug Evans ([email protected]). 1.1 root 6: 7: ;; This file is part of GNU CC. 8: 9: ;; GNU CC is free software; you can redistribute it and/or modify 10: ;; it under the terms of the GNU General Public License as published by 11: ;; the Free Software Foundation; either version 2, or (at your option) 12: ;; any later version. 13: 14: ;; GNU CC is distributed in the hope that it will be useful, 15: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 16: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17: ;; GNU General Public License for more details. 18: 19: ;; You should have received a copy of the GNU General Public License 20: ;; along with GNU CC; see the file COPYING. If not, write to 21: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 22: 23: 24: ;; The original PO technology requires these to be ordered by speed, 25: ;; so that assigner will pick the fastest. 26: 27: ;; See file "rtl.def" for documentation on define_insn, match_*, et. al. 28: 1.1.1.2 ! root 29: (define_attr "cpu" "h8300,h8300h" ! 30: (const (symbol_ref "cpu_type"))) ! 31: ! 32: ;; ??? If we can remove the operand type on all the insns, do it. ! 33: ;; ??? Otherwise, try to have the operand type on all the insns. ! 34: 1.1 root 35: (define_attr "type" "branch,return,call,arith,move,float,multi" 36: (const_string "arith")) 37: 38: ;; The size of instructions in bytes. 39: 40: (define_attr "length" "" 41: (cond [(eq_attr "type" "branch") 42: (if_then_else (and (ge (minus (pc) (match_dup 0)) 1.1.1.2 ! root 43: (const_int -120)) 1.1 root 44: (le (minus (pc) (match_dup 0)) 1.1.1.2 ! root 45: (const_int 120))) 1.1 root 46: (const_int 2) 1.1.1.2 ! root 47: (if_then_else (and (eq_attr "cpu" "h8300h") ! 48: (and (ge (minus (pc) (match_dup 0)) ! 49: (const_int -32000)) ! 50: (le (minus (pc) (match_dup 0)) ! 51: (const_int 32000)))) ! 52: (const_int 4) ! 53: (const_int 6))) 1.1 root 54: (eq_attr "type" "move") (const_int 4) 55: (eq_attr "type" "return") (const_int 2) 56: (eq_attr "type" "float") (const_int 12) 57: (eq_attr "type" "call") (const_int 4)] 58: (const_int 200))) 59: 1.1.1.2 ! root 60: (define_attr "cc" "none,clobber,none_0hit,set,compare,whoops,cbit" 1.1 root 61: (const_string "whoops")) 1.1.1.2 ! root 62: 1.1 root 63: ;; ---------------------------------------------------------------------- 1.1.1.2 ! root 64: ;; MOVE INSTRUCTIONS 1.1 root 65: ;; ---------------------------------------------------------------------- 66: 1.1.1.2 ! root 67: ;; movqi 1.1 root 68: 1.1.1.2 ! root 69: (define_insn "movqi_push" ! 70: [(set (match_operand:QI 0 "push_operand" "=<") ! 71: (match_operand:QI 1 "register_operand" "r"))] 1.1 root 72: "" 1.1.1.2 ! root 73: "* ! 74: { ! 75: if (TARGET_H8300) ! 76: return \"push.w %T1\"; ! 77: else ! 78: return \"push.l %S1\"; ! 79: }" 1.1 root 80: [(set_attr "type" "move") 1.1.1.2 ! root 81: (set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4))) 1.1 root 82: (set_attr "cc" "set")]) 83: 1.1.1.2 ! root 84: (define_insn "movqi_internal" ! 85: [(set (match_operand:QI 0 "general_operand_dst" "=r,r,r,o,<,r") ! 86: (match_operand:QI 1 "general_operand_src" "I,r>,io,r,r,c"))] ! 87: "register_operand (operands[0],QImode) || register_operand (operands[1], QImode)" ! 88: "@ ! 89: sub.b %X0,%X0 ! 90: mov.b %X1,%X0 ! 91: mov.b %X1,%X0 ! 92: mov.b %X1,%X0 ! 93: mov.b %X1,%X0 ! 94: xor %X0,%X0\;bst #0,%X0" ! 95: [(set_attr "type" "move") ! 96: (set_attr_alternative "length" ! 97: [(const_int 2) (const_int 2) ! 98: (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8)) ! 99: (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8)) ! 100: (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4)) ! 101: (const_int 4)]) ! 102: (set_attr "cc" "set,set,set,set,set,none")]) ! 103: ! 104: (define_expand "movqi" ! 105: [(set (match_operand:QI 0 "general_operand_dst" "") ! 106: (match_operand:QI 1 "general_operand_src" ""))] ! 107: "" ! 108: " ! 109: { ! 110: /* One of the ops has to be in a register */ ! 111: if (!register_operand(operand0, QImode) ! 112: && !register_operand(operand1, QImode)) ! 113: { ! 114: operands[1] = copy_to_mode_reg(QImode, operand1); ! 115: } ! 116: }") ! 117: ! 118: (define_insn "movstrictqi" ! 119: [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "=r,r,r,o,<")) ! 120: (match_operand:QI 1 "general_operand_src" "I,r,io,r,r"))] 1.1 root 121: "" 122: "@ 1.1.1.2 ! root 123: sub.b %X0,%X0 ! 124: mov.b %X1,%X0 ! 125: mov.b %X1,%X0 ! 126: mov.b %X1,%X0 ! 127: mov.b %X1,%X0" 1.1 root 128: [(set_attr "type" "move") 1.1.1.2 ! root 129: (set_attr_alternative "length" ! 130: [(const_int 2) (const_int 2) ! 131: (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8)) ! 132: (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8)) ! 133: (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4))]) ! 134: (set_attr "cc" "set")]) ! 135: ! 136: ;; movhi ! 137: ! 138: (define_insn "movhi_push" ! 139: [(set (match_operand:HI 0 "push_operand" "=<") ! 140: (match_operand:HI 1 "register_operand" "ra"))] ! 141: "" ! 142: "* ! 143: { ! 144: if (TARGET_H8300) ! 145: return \"push.w %T1\"; ! 146: else ! 147: return \"push.l %S1\"; ! 148: }" ! 149: [(set_attr "type" "move") ! 150: (set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4))) 1.1 root 151: (set_attr "cc" "set")]) 152: 1.1.1.2 ! root 153: (define_insn "movhi_internal" 1.1 root 154: [(set (match_operand:HI 0 "general_operand_dst" "=ra,ra,ra,o,<") 1.1.1.2 ! root 155: (match_operand:HI 1 "general_operand_src" "I,ra>,ion,ra,ra"))] 1.1 root 156: "" 157: "@ 158: sub.w %T0,%T0 159: mov.w %T1,%T0 160: mov.w %T1,%T0 161: mov.w %T1,%T0 162: mov.w %T1,%T0" 163: [(set_attr "type" "move") 1.1.1.2 ! root 164: (set_attr_alternative "length" ! 165: [(const_int 2) (const_int 2) ! 166: (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8)) ! 167: (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8)) ! 168: (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4))]) 1.1 root 169: (set_attr "cc" "set")]) 170: 171: (define_expand "movhi" 172: [(set (match_operand:HI 0 "general_operand_dst" "") 173: (match_operand:HI 1 "general_operand_src" ""))] 174: "" 175: " 176: { 1.1.1.2 ! root 177: /* One of the ops has to be in a register */ ! 178: if (!register_operand(operand1, HImode) ! 179: && !register_operand(operand0, HImode)) ! 180: { ! 181: operands[1] = copy_to_mode_reg(HImode, operand1); ! 182: } 1.1 root 183: }") 184: 1.1.1.2 ! root 185: (define_insn "movstricthi" ! 186: [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "=r,r,r,o,<")) ! 187: (match_operand:HI 1 "general_operand_src" "I,r,io,r,r"))] 1.1 root 188: "" 189: "@ 1.1.1.2 ! root 190: sub.w %T0,%T0 ! 191: mov.w %T1,%T0 ! 192: mov.w %T1,%T0 ! 193: mov.w %T1,%T0 ! 194: mov.w %T1,%T0" 1.1 root 195: [(set_attr "type" "move") 1.1.1.2 ! root 196: (set_attr_alternative "length" ! 197: [(const_int 2) (const_int 2) ! 198: (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8)) ! 199: (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8)) ! 200: (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4))]) 1.1 root 201: (set_attr "cc" "set")]) 202: 1.1.1.2 ! root 203: ;; movsi 1.1 root 204: 1.1.1.2 ! root 205: (define_expand "movsi" ! 206: [(set (match_operand:SI 0 "general_operand_dst" "") ! 207: (match_operand:SI 1 "general_operand_src" ""))] 1.1 root 208: "" 209: " 210: { 1.1.1.2 ! root 211: if (TARGET_H8300) ! 212: { ! 213: if (do_movsi (operands)) ! 214: DONE; ! 215: } ! 216: else /* TARGET_H8300H */ ! 217: { ! 218: /* One of the ops has to be in a register. */ ! 219: if (!register_operand (operand1, SImode) ! 220: && !register_operand (operand0, SImode)) ! 221: { ! 222: operands[1] = copy_to_mode_reg (SImode, operand1); ! 223: } ! 224: } 1.1 root 225: }") 226: 1.1.1.2 ! root 227: (define_expand "movsf" ! 228: [(set (match_operand:SF 0 "general_operand_dst" "") ! 229: (match_operand:SF 1 "general_operand_src" ""))] 1.1 root 230: "" 1.1.1.2 ! root 231: " ! 232: { ! 233: if (TARGET_H8300) ! 234: { ! 235: if (do_movsi (operands)) ! 236: DONE; ! 237: } ! 238: else /* TARGET_H8300H */ ! 239: { ! 240: /* One of the ops has to be in a register. */ ! 241: if (!register_operand (operand1, SFmode) ! 242: && !register_operand (operand0, SFmode)) ! 243: { ! 244: operands[1] = copy_to_mode_reg (SFmode, operand1); ! 245: } ! 246: } ! 247: }") ! 248: ! 249: (define_insn "movsi_h8300" ! 250: [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r") ! 251: (match_operand:SI 1 "general_operand_src" "I,r,ion,r,r,>"))] ! 252: "TARGET_H8300 ! 253: && (register_operand (operands[0], SImode) ! 254: || register_operand (operands[1], SImode))" 1.1 root 255: "* 256: { 257: int rn = -1; 258: switch (which_alternative) 259: { 260: case 0: 261: return \"sub.w %e0,%e0\;sub.w %f0,%f0\"; 262: case 1: 1.1.1.2 ! root 263: if (REGNO(operands[0]) < REGNO(operands[1])) ! 264: return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; ! 265: else ! 266: return \"mov.w %f1,%f0\;mov.w %e1,%e0\"; 1.1 root 267: case 2: 268: /* Make sure we don't trample the register we index with. */ 269: 1.1.1.2 ! root 270: if (GET_CODE(operands[1]) == MEM) 1.1 root 271: { 1.1.1.2 ! root 272: rtx inside = XEXP (operands[1],0); ! 273: if (REG_P (inside)) ! 274: { ! 275: rn = REGNO(inside); ! 276: } 1.1 root 277: else if (GET_CODE (inside) == PLUS) 278: { 1.1.1.2 ! root 279: rtx lhs = XEXP (inside,0); ! 280: rtx rhs = XEXP (inside,1); ! 281: if (REG_P (lhs)) rn = REGNO (lhs); ! 282: if (REG_P (rhs)) rn = REGNO (rhs); 1.1 root 283: } 284: } 1.1.1.2 ! root 285: if (rn == REGNO (operands[0])) ! 286: { ! 287: /* Move the second word first. */ ! 288: return \"mov.w %f1,%f0\;mov.w %e1,%e0\"; ! 289: } 1.1 root 290: else 1.1.1.2 ! root 291: { ! 292: return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; ! 293: } 1.1 root 294: 295: case 3: 296: return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; 297: case 4: 298: return \"mov.w %f1,%T0\;mov.w %e1,%T0\"; 1.1.1.2 ! root 299: case 5: ! 300: return \"mov.w %T1,%e0\;mov.w %T1,%f0\"; 1.1 root 301: } 302: }" 303: [(set_attr "type" "move") 1.1.1.2 ! root 304: (set_attr "length" "4,4,8,8,4,4") 1.1 root 305: (set_attr "cc" "clobber")]) 306: 1.1.1.2 ! root 307: (define_insn "movsf_h8300" ! 308: [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r") ! 309: (match_operand:SF 1 "general_operand_src" "I,r,ion,r,r,>"))] ! 310: "TARGET_H8300 ! 311: && (register_operand (operands[0], SFmode) ! 312: || register_operand (operands[1], SFmode))" 1.1 root 313: "* 314: { 1.1.1.2 ! root 315: /* Copy of the movsi stuff */ 1.1 root 316: int rn = -1; 317: switch (which_alternative) 318: { 319: case 0: 320: return \"sub.w %e0,%e0\;sub.w %f0,%f0\"; 321: case 1: 1.1.1.2 ! root 322: if (REGNO(operands[0]) < REGNO(operands[1])) ! 323: return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; ! 324: else ! 325: return \"mov.w %f1,%f0\;mov.w %e1,%e0\"; 1.1 root 326: case 2: 327: /* Make sure we don't trample the register we index with. */ 328: 329: if (GET_CODE (operands[1]) == MEM) 330: { 1.1.1.2 ! root 331: rtx inside = XEXP (operands[1],0); 1.1 root 332: if (REG_P (inside)) 1.1.1.2 ! root 333: { ! 334: rn = REGNO (inside); ! 335: } 1.1 root 336: else if (GET_CODE (inside) == PLUS) 337: { 1.1.1.2 ! root 338: rtx lhs = XEXP (inside,0); ! 339: rtx rhs = XEXP (inside,1); ! 340: if (REG_P (lhs)) rn = REGNO (lhs); ! 341: if (REG_P (rhs)) rn = REGNO (rhs); 1.1 root 342: } 343: } 344: if (rn == REGNO (operands[0])) 1.1.1.2 ! root 345: { ! 346: /* move the second word first */ ! 347: return \"mov.w %f1,%f0\;mov.w %e1,%e0\"; ! 348: } 1.1 root 349: else 1.1.1.2 ! root 350: { ! 351: return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; ! 352: } 1.1 root 353: 354: case 3: 355: return \"mov.w %e1,%e0\;mov.w %f1,%f0\"; 356: case 4: 357: return \"mov.w %f1,%T0\;mov.w %e1,%T0\"; 1.1.1.2 ! root 358: case 5: ! 359: return \"mov.w %T1,%e0\;mov.w %T1,%f0\"; ! 360: ! 361: } 1.1 root 362: }" 363: [(set_attr "type" "move") 1.1.1.2 ! root 364: (set_attr "length" "4,4,8,8,4,4") 1.1 root 365: (set_attr "cc" "clobber")]) 366: 1.1.1.2 ! root 367: (define_insn "movsi_h8300h" ! 368: [(set (match_operand:SI 0 "general_operand_dst" "=ra,ra,ra,o,<,ra") ! 369: (match_operand:SI 1 "general_operand_src" "I,ra,ion,ra,ra,>"))] ! 370: "TARGET_H8300H ! 371: && (register_operand (operands[0], SImode) ! 372: || register_operand (operands[1], SImode))" ! 373: "@ ! 374: sub.l %S0,%S0 ! 375: mov.l %S1,%S0 ! 376: mov.l %S1,%S0 ! 377: mov.l %S1,%S0 ! 378: mov.l %S1,%S0 ! 379: mov.l %S1,%S0" 1.1 root 380: [(set_attr "type" "move") 1.1.1.2 ! root 381: (set_attr "length" "2,2,8,8,4,4") ! 382: (set_attr "cc" "set")]) 1.1 root 383: 1.1.1.2 ! root 384: (define_insn "movsf_h8300h" ! 385: [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<") ! 386: (match_operand:SF 1 "general_operand_src" "I,r,ion,r,r"))] ! 387: "TARGET_H8300H ! 388: && (register_operand (operands[0], SFmode) ! 389: || register_operand (operands[1], SFmode))" ! 390: "@ ! 391: sub.l %S0,%S0 ! 392: mov.l %S1,%S0 ! 393: mov.l %S1,%S0 ! 394: mov.l %S1,%S0 ! 395: mov.l %S1,%S0" ! 396: [(set_attr "type" "move") ! 397: (set_attr "length" "2,2,8,8,4") ! 398: (set_attr "cc" "set")]) 1.1 root 399: 400: ;; ---------------------------------------------------------------------- 1.1.1.2 ! root 401: ;; TEST INSTRUCTIONS 1.1 root 402: ;; ---------------------------------------------------------------------- 403: 404: (define_insn "tstqi" 1.1.1.2 ! root 405: [(set (cc0) (match_operand:QI 0 "register_operand" "ra"))] 1.1 root 406: "" 1.1.1.2 ! root 407: "* ! 408: { ! 409: /* ??? I don't think this is right. --Jim */ ! 410: if (cc_prev_status.flags & CC_DONE_CBIT) ! 411: return \"btst #0,%X0\"; ! 412: else ! 413: return \"cmp.b #0,%X0\"; ! 414: }" 1.1 root 415: [(set_attr "type" "arith") 1.1.1.2 ! root 416: (set_attr "length" "4") 1.1 root 417: (set_attr "cc" "set")]) 418: 419: (define_insn "tsthi" 1.1.1.2 ! root 420: [(set (cc0) (match_operand:HI 0 "general_operand" "ra"))] ! 421: "" ! 422: "* ! 423: { ! 424: /* ??? I don't think this is right. --Jim */ ! 425: if (cc_prev_status.flags & CC_DONE_CBIT) ! 426: return \"btst #0,%0l\"; ! 427: else ! 428: return \"mov.w %T0,%T0\"; ! 429: }" ! 430: [(set_attr "type" "arith") ! 431: (set_attr "length" "4") ! 432: (set_attr "cc" "set")]) ! 433: ! 434: (define_insn "tstsi" ! 435: [(set (cc0) (match_operand:SI 0 "general_operand" "ra"))] ! 436: "TARGET_H8300H" ! 437: "* ! 438: { ! 439: /* ??? I don't think this is right. --Jim */ ! 440: if (cc_prev_status.flags & CC_DONE_CBIT) ! 441: return \"btst #0,%0l\"; ! 442: else ! 443: return \"mov.l %S0,%S0\"; ! 444: }" ! 445: [(set_attr "type" "arith") ! 446: (set_attr "length" "4") ! 447: (set_attr "cc" "set")]) ! 448: ! 449: (define_insn "cmpqi" 1.1 root 450: [(set (cc0) 1.1.1.2 ! root 451: (compare:QI (match_operand:QI 0 "register_operand" "ra") ! 452: (match_operand:QI 1 "nonmemory_operand" "rai")))] 1.1 root 453: "" 1.1.1.2 ! root 454: "cmp.b %X1,%X0" 1.1 root 455: [(set_attr "type" "arith") 456: (set_attr "length" "2") 1.1.1.2 ! root 457: (set_attr "cc" "compare")]) ! 458: ! 459: ;; ??? 300h can have an immediate operand here. 1.1 root 460: 461: (define_insn "cmphi" 462: [(set (cc0) 463: (compare:HI (match_operand:HI 0 "register_operand" "ra") 464: (match_operand:HI 1 "register_operand" "ra")))] 465: "" 466: "cmp.w %T1,%T0" 467: [(set_attr "type" "arith") 468: (set_attr "length" "2") 469: (set_attr "cc" "compare")]) 470: 1.1.1.2 ! root 471: ;; ??? 300h can have an immediate operand here. ! 472: ! 473: (define_insn "cmpsi" 1.1 root 474: [(set (cc0) 1.1.1.2 ! root 475: (compare:SI (match_operand:SI 0 "register_operand" "ra") ! 476: (match_operand:SI 1 "register_operand" "ra")))] ! 477: "TARGET_H8300H" ! 478: "cmp.l %S1,%S0" 1.1 root 479: [(set_attr "type" "arith") 480: (set_attr "length" "2") 481: (set_attr "cc" "compare")]) 1.1.1.2 ! root 482: 1.1 root 483: ;; ---------------------------------------------------------------------- 1.1.1.2 ! root 484: ;; ADD INSTRUCTIONS 1.1 root 485: ;; ---------------------------------------------------------------------- 486: 1.1.1.2 ! root 487: (define_insn "addqi3" ! 488: [(set (match_operand:QI 0 "register_operand" "=r") ! 489: (plus:QI (match_operand:QI 1 "register_operand" "%0") ! 490: (match_operand:QI 2 "nonmemory_operand" "ri")))] ! 491: "" ! 492: "add.b %X2,%X0" ! 493: [(set_attr "type" "arith") ! 494: (set_attr "length" "2") ! 495: (set_attr "cc" "set")]) ! 496: ! 497: ;; ??? adds operates on the 32bit register. We can use it because we don't ! 498: ;; use the e0-7 registers. ! 499: ;; ??? 4 can be handled in one insn on the 300h. ! 500: ! 501: (define_insn "addhi3_internal" 1.1 root 502: [(set (match_operand:HI 0 "register_operand" "=ra,ra,ra,ra,r,ra") 503: (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0") 504: (match_operand:HI 2 "nonmemory_operand" "K,M,L,N,n,ra")))] 505: "" 506: "@ 1.1.1.2 ! root 507: adds %T2,%A0 ! 508: adds #2,%A0\;adds %C2,%A0 ! 509: subs %M2,%A0 ! 510: subs #2,%A0\;subs %M2,%A0 1.1 root 511: add.b %s2,%s0\;addx %t2,%t0 512: add.w %T2,%T0" 1.1.1.2 ! root 513: [(set_attr "type" "arith,multi,arith,multi,multi,arith") 1.1 root 514: (set_attr "length" "2,4,2,4,4,2") 515: (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,clobber,set")]) 516: 1.1.1.2 ! root 517: ;; ??? Why is this here? 1.1 root 518: (define_expand "addhi3" 519: [(set (match_operand:HI 0 "register_operand" "") 520: (plus:HI (match_operand:HI 1 "register_operand" "") 521: (match_operand:HI 2 "nonmemory_operand" "")))] 522: "" 1.1.1.2 ! root 523: "") 1.1 root 524: 1.1.1.2 ! root 525: (define_expand "addsi3" ! 526: [(set (match_operand:SI 0 "register_operand" "") ! 527: (plus:SI (match_operand:SI 1 "register_operand" "") ! 528: (match_operand:SI 2 "nonmemory_operand" "")))] 1.1 root 529: "" 1.1.1.2 ! root 530: "") 1.1 root 531: 1.1.1.2 ! root 532: (define_insn "addsi_h8300" ! 533: [(set (match_operand:SI 0 "register_operand" "=r,r,&r") ! 534: (plus:SI (match_operand:SI 1 "register_operand" "%0,0,r") ! 535: (match_operand:SI 2 "nonmemory_operand" "n,r,r")))] ! 536: "TARGET_H8300" 1.1 root 537: "@ 1.1.1.2 ! root 538: add %w2,%w0\;addx %x2,%x0\;addx %y2,%y0\;addx %z2,%z0 ! 539: add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0 ! 540: mov %f1,%f0\;mov %e1,%e0\;add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0" ! 541: [(set_attr "type" "arith") ! 542: (set_attr "length" "8,6,20") 1.1 root 543: (set_attr "cc" "clobber")]) 544: 1.1.1.2 ! root 545: ;; ??? 4 can be handled in one insn on the 300h. ! 546: ;; ??? Should the 'n' constraint be 'i' here? ! 547: ;; ??? We don't handle (reg + symbol_ref) which the 300h can handle. ! 548: ! 549: (define_insn "addsi_h8300h" ! 550: [(set (match_operand:SI 0 "register_operand" "=ra,ra,ra,ra,r,ra") ! 551: (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0") ! 552: (match_operand:SI 2 "nonmemory_operand" "K,M,L,N,n,ra")))] ! 553: "TARGET_H8300H" ! 554: "@ ! 555: adds %S2,%S0 ! 556: adds #2,%S0\;adds %C2,%S0 ! 557: subs %M2,%S0 ! 558: subs #2,%S0\;subs %M2,%S0 ! 559: add.l %S2,%S0 ! 560: add.l %S2,%S0" ! 561: [(set_attr "type" "multi,multi,multi,multi,arith,arith") ! 562: (set_attr "length" "2,4,2,4,6,2") ! 563: (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,clobber,clobber")]) ! 564: ! 565: ;; ---------------------------------------------------------------------- ! 566: ;; SUBTRACT INSTRUCTIONS ! 567: ;; ---------------------------------------------------------------------- ! 568: ! 569: (define_insn "subqi3" ! 570: [(set (match_operand:QI 0 "register_operand" "=r,r") ! 571: (minus:QI (match_operand:QI 1 "register_operand" "0,0") ! 572: (match_operand:QI 2 "nonmemory_operand" "r,i")))] 1.1 root 573: "" 574: "@ 1.1.1.2 ! root 575: sub.b %X2,%X0 ! 576: add.b %G2,%X0" 1.1 root 577: [(set_attr "type" "arith") 1.1.1.2 ! root 578: (set_attr "length" "2") ! 579: (set_attr "cc" "set")]) 1.1 root 580: 1.1.1.2 ! root 581: ;; ??? subs operates on the 32bit register. We can use it because we don't ! 582: ;; use the e0-7 registers. ! 583: ;; ??? 4 can be handled in one insn on the 300h. ! 584: ;; ??? The fourth alternative can use sub.w on the 300h. ! 585: ;; ??? Should the 'n' constraint be an 'i' here? 1.1 root 586: 1.1.1.2 ! root 587: (define_insn "subhi3_internal" 1.1 root 588: [(set (match_operand:HI 0 "register_operand" "=ra,ra,ra,r") 589: (minus:HI (match_operand:HI 1 "general_operand" "0,0,0,0") 590: (match_operand:HI 2 "nonmemory_operand" "K,M,ra,n")))] 591: "" 592: "@ 593: subs %T2,%T0 1.1.1.2 ! root 594: subs #2,%T0\;subs %M2,%T0 1.1 root 595: sub.w %T2,%T0 596: add.b %E2,%s0\;addx %F2,%t0 ; -%0" 597: [(set_attr "type" "multi") 598: (set_attr "length" "2,4,2,4") 599: (set_attr "cc" "none_0hit,none_0hit,set,clobber")]) 600: 1.1.1.2 ! root 601: ;; ??? Why is this here? 1.1 root 602: (define_expand "subhi3" 603: [(set (match_operand:HI 0 "register_operand" "") 604: (minus:HI (match_operand:HI 1 "register_operand" "") 605: (match_operand:HI 2 "nonmemory_operand" "")))] 606: "" 1.1.1.2 ! root 607: "") 1.1 root 608: 1.1.1.2 ! root 609: (define_expand "subsi3" ! 610: [(set (match_operand:SI 0 "register_operand" "") ! 611: (minus:SI (match_operand:SI 1 "register_operand" "") ! 612: (match_operand:SI 2 "nonmemory_operand" "")))] 1.1 root 613: "" 1.1.1.2 ! root 614: "") ! 615: ! 616: (define_insn "subsi3_h8300" ! 617: [(set (match_operand:SI 0 "register_operand" "=r") ! 618: (minus:SI (match_operand:SI 1 "register_operand" "0") ! 619: (match_operand:SI 2 "register_operand" "r")))] ! 620: "TARGET_H8300" 1.1 root 621: "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0" 622: [(set_attr "type" "arith") 623: (set_attr "length" "6") 624: (set_attr "cc" "clobber")]) 625: 1.1.1.2 ! root 626: ;; ??? 4 can be handled in one insn on the 300h. ! 627: ! 628: (define_insn "subsi3_h8300h" ! 629: [(set (match_operand:SI 0 "register_operand" "=ra,ra,ra,r") ! 630: (minus:SI (match_operand:SI 1 "general_operand" "0,0,0,0") ! 631: (match_operand:SI 2 "nonmemory_operand" "K,M,ra,n")))] ! 632: "TARGET_H8300H" ! 633: "@ ! 634: subs %T2,%T0 ! 635: subs #2,%T0\;subs %E2,%T0 ! 636: sub.l %S2,%S0 ! 637: sub.l %S2,%S0" ! 638: [(set_attr "type" "multi") ! 639: (set_attr "length" "2,4,2,6") ! 640: (set_attr "cc" "none_0hit,none_0hit,set,set")]) 1.1 root 641: 642: ;; ---------------------------------------------------------------------- 1.1.1.2 ! root 643: ;; MULTIPLY INSTRUCTIONS 1.1 root 644: ;; ---------------------------------------------------------------------- 645: 1.1.1.2 ! root 646: ;; Note that the h8/300 can only handle umulqihi3. ! 647: ! 648: (define_insn "mulqihi3" ! 649: [(set (match_operand:HI 0 "register_operand" "=r") ! 650: (mult:HI (sign_extend:HI (match_operand:QI 1 "general_operand" "%0")) ! 651: (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))] ! 652: "TARGET_H8300H" ! 653: "mulxs.b %X2,%T0" ! 654: [(set_attr "type" "multi") ! 655: (set_attr "length" "4") ! 656: (set_attr "cc" "set")]) ! 657: ! 658: (define_insn "mulhisi3" ! 659: [(set (match_operand:SI 0 "register_operand" "=r") ! 660: (mult:SI (sign_extend:SI (match_operand:HI 1 "general_operand" "%0")) ! 661: (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))] ! 662: "TARGET_H8300H" ! 663: "mulxs.w %T2,%S0" ! 664: [(set_attr "type" "multi") ! 665: (set_attr "length" "4") ! 666: (set_attr "cc" "set")]) ! 667: 1.1 root 668: (define_insn "umulqihi3" 669: [(set (match_operand:HI 0 "register_operand" "=r") 1.1.1.2 ! root 670: (mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%0")) ! 671: (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))] 1.1 root 672: "" 673: "mulxu %X2,%T0" 674: [(set_attr "type" "multi") 675: (set_attr "length" "2") 676: (set_attr "cc" "none_0hit")]) 677: 1.1.1.2 ! root 678: (define_insn "umulhisi3" ! 679: [(set (match_operand:SI 0 "register_operand" "=r") ! 680: (mult:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "%0")) ! 681: (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))] ! 682: "TARGET_H8300H" ! 683: "mulxu.w %T2,%S0" ! 684: [(set_attr "type" "multi") ! 685: (set_attr "length" "2") ! 686: (set_attr "cc" "none_0hit")]) ! 687: 1.1 root 688: ;; ---------------------------------------------------------------------- 1.1.1.2 ! root 689: ;; DIVIDE INSTRUCTIONS 1.1 root 690: ;; ---------------------------------------------------------------------- 691: 692: (define_insn "udivqi3" 693: [(set (match_operand:QI 0 "register_operand" "=r") 694: (udiv:QI (match_operand:HI 1 "general_operand" "0") 695: (match_operand:QI 2 "register_operand" "r")))] 696: "" 697: "divxu %X2,%T0" 698: [(set_attr "type" "multi") 699: (set_attr "length" "2") 700: (set_attr "cc" "clobber")]) 701: 1.1.1.2 ! root 702: ;; ??? Will divxu always work here? ! 703: 1.1 root 704: (define_insn "divqi3" 705: [(set (match_operand:QI 0 "register_operand" "=r") 706: (div:QI (match_operand:HI 1 "general_operand" "0") 707: (match_operand:QI 2 "register_operand" "r")))] 708: "" 709: "divxu %X2,%T0" 710: [(set_attr "type" "multi") 711: (set_attr "length" "2") 712: (set_attr "cc" "clobber")]) 1.1.1.2 ! root 713: ! 714: (define_insn "udivhi3" ! 715: [(set (match_operand:HI 0 "register_operand" "=r") ! 716: (udiv:HI (match_operand:SI 1 "general_operand" "0") ! 717: (match_operand:HI 2 "register_operand" "r")))] ! 718: "TARGET_H8300H" ! 719: "divxu.w %T2,%S0" ! 720: [(set_attr "type" "multi") ! 721: (set_attr "length" "2") ! 722: (set_attr "cc" "clobber")]) ! 723: ! 724: (define_insn "divhi3" ! 725: [(set (match_operand:HI 0 "register_operand" "=r") ! 726: (div:HI (match_operand:SI 1 "general_operand" "0") ! 727: (match_operand:HI 2 "register_operand" "r")))] ! 728: "TARGET_H8300H" ! 729: "divxs.w %T2,%S0" ! 730: [(set_attr "type" "multi") ! 731: (set_attr "length" "4") ! 732: (set_attr "cc" "clobber")]) ! 733: 1.1 root 734: ;; ---------------------------------------------------------------------- 1.1.1.2 ! root 735: ;; MOD INSTRUCTIONS 1.1 root 736: ;; ---------------------------------------------------------------------- 737: 1.1.1.2 ! root 738: (define_insn "umodqi3" ! 739: [(set (match_operand:QI 0 "register_operand" "=r") ! 740: (umod:QI (match_operand:HI 1 "general_operand" "0") ! 741: (match_operand:QI 2 "register_operand" "r")))] 1.1 root 742: "" 1.1.1.2 ! root 743: "divxu %X2,%T0\;mov %t0,%s0" ! 744: [(set_attr "type" "multi") ! 745: (set_attr "length" "4") ! 746: (set_attr "cc" "clobber")]) ! 747: ! 748: (define_insn "modqi3" ! 749: [(set (match_operand:QI 0 "register_operand" "=r") ! 750: (mod:QI (match_operand:HI 1 "general_operand" "0") ! 751: (match_operand:QI 2 "register_operand" "r")))] ! 752: "TARGET_H8300H" ! 753: "divxs.b %X2,%T0\;mov %t0,%s0" ! 754: [(set_attr "type" "multi") ! 755: (set_attr "length" "6") ! 756: (set_attr "cc" "clobber")]) ! 757: ! 758: (define_insn "umodhi3" ! 759: [(set (match_operand:HI 0 "register_operand" "=r") ! 760: (umod:HI (match_operand:SI 1 "general_operand" "0") ! 761: (match_operand:HI 2 "register_operand" "r")))] ! 762: "TARGET_H8300H" ! 763: "divxu.w %T2,%S0\;mov %e0,%f0" ! 764: [(set_attr "type" "multi") ! 765: (set_attr "length" "4") ! 766: (set_attr "cc" "clobber")]) ! 767: ! 768: (define_insn "modhi3" ! 769: [(set (match_operand:HI 0 "register_operand" "=r") ! 770: (mod:HI (match_operand:SI 1 "general_operand" "0") ! 771: (match_operand:HI 2 "register_operand" "r")))] ! 772: "TARGET_H8300H" ! 773: "divxs.w %T2,%S0\;mov %e0,%f0" ! 774: [(set_attr "type" "multi") ! 775: (set_attr "length" "6") ! 776: (set_attr "cc" "clobber")]) ! 777: ! 778: ;; ---------------------------------------------------------------------- ! 779: ;; AND INSTRUCTIONS ! 780: ;; ---------------------------------------------------------------------- ! 781: ! 782: (define_insn "andqi3_internal" ! 783: [(set (match_operand:QI 0 "bit_operand" "=r,U") ! 784: (and:QI (match_operand:QI 1 "bit_operand" "%0,0") ! 785: (match_operand:QI 2 "nonmemory_operand" "rn,O")))] ! 786: "register_operand (operands[0], QImode) || o_operand (operands[2], QImode)" ! 787: "@ ! 788: and %X2,%X0 ! 789: bclr %W2,%X0" 1.1 root 790: [(set_attr "type" "arith") 1.1.1.2 ! root 791: (set_attr "length" "2,4") ! 792: (set_attr "cc" "set,none_0hit")]) ! 793: ! 794: (define_expand "andqi3" ! 795: [(set (match_operand:QI 0 "bit_operand" "=r,U") ! 796: (and:QI (match_operand:QI 1 "bit_operand" "%0,0") ! 797: (match_operand:QI 2 "nonmemory_operand" "rn,O")))] ! 798: "" ! 799: " ! 800: { ! 801: if (fix_bit_operand (operands, 'O', AND)) ! 802: DONE; ! 803: }") ! 804: ! 805: ;; ??? Should have a bclr case here also. 1.1 root 806: 807: (define_insn "andhi3" 808: [(set (match_operand:HI 0 "register_operand" "=r") 809: (and:HI (match_operand:HI 1 "register_operand" "%0") 1.1.1.2 ! root 810: (match_operand:HI 2 "nonmemory_operand" "rn")))] 1.1 root 811: "" 1.1.1.2 ! root 812: "* ! 813: { ! 814: if (GET_CODE (operands[2]) == CONST_INT) ! 815: { ! 816: int i = INTVAL (operands[2]); ! 817: if ((i & 0x00ff) != 0x00ff) ! 818: output_asm_insn (\"and %s2,%s0\", operands); ! 819: if ((i & 0xff00) != 0xff00) ! 820: output_asm_insn (\"and %t2,%t0\", operands); ! 821: return \"\"; ! 822: } ! 823: return \"and %s2,%s0\;and %t2,%t0;\"; ! 824: }" 1.1 root 825: [(set_attr "type" "multi") 826: (set_attr "length" "4") 827: (set_attr "cc" "clobber")]) 1.1.1.2 ! root 828: ! 829: ;; ??? There is an iorsi3 for TARGET_H8300. Should we have andsi3? ! 830: ! 831: (define_insn "andsi3" ! 832: [(set (match_operand:SI 0 "register_operand" "=r,r") ! 833: (and:SI (match_operand:SI 1 "register_operand" "%0,0") ! 834: (match_operand:SI 2 "nonmemory_operand" "r,i")))] ! 835: "TARGET_H8300H" ! 836: "@ ! 837: and %S2,%S0 ! 838: and %S2,%S0" ! 839: [(set_attr "type" "arith") ! 840: (set_attr "length" "4,6") ! 841: (set_attr "cc" "clobber")]) ! 842: 1.1 root 843: ;; ---------------------------------------------------------------------- 1.1.1.2 ! root 844: ;; OR INSTRUCTIONS 1.1 root 845: ;; ---------------------------------------------------------------------- 846: 1.1.1.2 ! root 847: (define_insn "iorqi3_internal" ! 848: [(set (match_operand:QI 0 "bit_operand" "=U,r") ! 849: (ior:QI (match_operand:QI 1 "bit_operand" "%0,0") ! 850: (match_operand:QI 2 "nonmemory_operand" "P,rn")))] ! 851: "register_operand (operands[0], QImode) || p_operand (operands[2], QImode)" 1.1 root 852: "@ 1.1.1.2 ! root 853: bset %V2,%X0 ! 854: or %X2,%X0" 1.1 root 855: [(set_attr "type" "arith") 1.1.1.2 ! root 856: (set_attr "length" "4,2") ! 857: (set_attr "cc" "none_0hit,set")]) ! 858: ! 859: (define_expand "iorqi3" ! 860: [(set (match_operand:QI 0 "bit_operand" "=r,U") ! 861: (ior:QI (match_operand:QI 1 "bit_operand" "%0,0") ! 862: (match_operand:QI 2 "nonmemory_operand" "rn,P")))] ! 863: "" ! 864: " ! 865: { ! 866: if (fix_bit_operand (operands, 'P', IOR)) ! 867: DONE; ! 868: }") ! 869: ! 870: ;; ??? Should have a bset case here also. 1.1 root 871: 872: (define_insn "iorhi3" 873: [(set (match_operand:HI 0 "general_operand" "=r,r") 874: (ior:HI (match_operand:HI 1 "general_operand" "%0,0") 1.1.1.2 ! root 875: (match_operand:HI 2 "general_operand" "J,rn")))] 1.1 root 876: "" 1.1.1.2 ! root 877: "* ! 878: { ! 879: if (TARGET_H8300) ! 880: { ! 881: if (GET_CODE (operands[2]) == CONST_INT) ! 882: { ! 883: int i = INTVAL (operands[2]); ! 884: if ((i & 0x00ff) != 0) ! 885: output_asm_insn (\"or %s2,%s0\", operands); ! 886: if ((i & 0xff00) != 0) ! 887: output_asm_insn (\"or %t2,%t0\", operands); ! 888: return \"\"; ! 889: } ! 890: return \"or %s2,%s0\;or %t2,%t0; %2 or2\"; ! 891: } ! 892: else ! 893: { ! 894: return \"or %S2,%S0\"; ! 895: } ! 896: }" 1.1 root 897: [(set_attr "type" "multi") 898: (set_attr "length" "2,4") 899: (set_attr "cc" "clobber,clobber")]) 1.1.1.2 ! root 900: ! 901: (define_insn "iorsi3" ! 902: [(set (match_operand:SI 0 "register_operand" "=r") ! 903: (ior:SI (match_operand:SI 1 "register_operand" "%0") ! 904: (match_operand:SI 2 "nonmemory_operand" "ri")))] ! 905: "" ! 906: "* ! 907: { ! 908: if (TARGET_H8300) ! 909: { ! 910: if (GET_CODE (operands[2]) == CONST_INT) ! 911: { ! 912: int i = INTVAL (operands[2]); ! 913: if ((i & 0x000000ff) != 0) ! 914: output_asm_insn (\"or %w2,%w0\", operands); ! 915: if ((i & 0x0000ff00) != 0) ! 916: output_asm_insn (\"or %x2,%x0\", operands); ! 917: if ((i & 0x00ff0000) != 0) ! 918: output_asm_insn (\"or %y2,%y0\", operands); ! 919: if ((i & 0xff000000) != 0) ! 920: output_asm_insn (\"or %z2,%z0\", operands); ! 921: return \"\"; ! 922: } ! 923: return \"or %w2,%w0\;or %x2,%x0\;or %y2,%y0\;or %z2,%z0\;\"; ! 924: } ! 925: else ! 926: { ! 927: return \"or %S2,%S0\"; ! 928: } ! 929: }" ! 930: [(set_attr "type" "multi") ! 931: (set_attr "length" "8") ! 932: (set_attr "cc" "clobber")]) ! 933: 1.1 root 934: ;; ---------------------------------------------------------------------- 1.1.1.2 ! root 935: ;; XOR INSTRUCTIONS 1.1 root 936: ;; ---------------------------------------------------------------------- 937: 1.1.1.2 ! root 938: (define_insn "xorqi3_internal" ! 939: [(set (match_operand:QI 0 "bit_operand" "=r,U") ! 940: (xor:QI (match_operand:QI 1 "bit_operand" "%0,0") ! 941: (match_operand:QI 2 "nonmemory_operand" "rn,P")))] ! 942: "register_operand (operands[0], QImode) || p_operand (operands[2], QImode)" ! 943: "@ ! 944: xor %X2,%X0 ! 945: bnot %V2,%X0" 1.1 root 946: [(set_attr "type" "arith") 1.1.1.2 ! root 947: (set_attr "length" "2,4") ! 948: (set_attr "cc" "set,none_0hit")]) ! 949: ! 950: (define_expand "xorqi3" ! 951: [(set (match_operand:QI 0 "bit_operand" "=r,U") ! 952: (xor:QI (match_operand:QI 1 "bit_operand" "%0,0") ! 953: (match_operand:QI 2 "nonmemory_operand" "rn,O")))] ! 954: "" ! 955: " ! 956: { ! 957: if (fix_bit_operand (operands, 'O', XOR)) ! 958: DONE; ! 959: }") 1.1 root 960: 961: (define_insn "xorhi3" 1.1.1.2 ! root 962: [(set (match_operand:HI 0 "register_operand" "=r") 1.1 root 963: (xor:HI (match_operand:HI 1 "general_operand" "%0") 1.1.1.2 ! root 964: (match_operand:HI 2 "nonmemory_operand" "rn")))] 1.1 root 965: "" 1.1.1.2 ! root 966: "* ! 967: { ! 968: if (TARGET_H8300) ! 969: return \"xor %s2,%s0\;xor %t2,%t0\"; ! 970: else ! 971: return \"xor %S2,%S0\"; ! 972: }" 1.1 root 973: [(set_attr "type" "multi") 974: (set_attr "length" "4") 975: (set_attr "cc" "clobber")]) 1.1.1.2 ! root 976: ! 977: ;; ??? There is an iorsi3 for TARGET_H8300. Should we have xorsi3? ! 978: ! 979: (define_insn "xorsi3" ! 980: [(set (match_operand:SI 0 "register_operand" "=r,r") ! 981: (xor:SI (match_operand:SI 1 "register_operand" "%0,0") ! 982: (match_operand:SI 2 "nonmemory_operand" "r,i")))] ! 983: "TARGET_H8300H" ! 984: "@ ! 985: xor %S2,%S0 ! 986: xor %S2,%S0" ! 987: [(set_attr "type" "arith") ! 988: (set_attr "length" "4,6") ! 989: (set_attr "cc" "clobber")]) ! 990: 1.1 root 991: ;; ---------------------------------------------------------------------- 1.1.1.2 ! root 992: ;; NEGATION INSTRUCTIONS 1.1 root 993: ;; ---------------------------------------------------------------------- 994: 995: (define_insn "negqi2" 996: [(set (match_operand:QI 0 "register_operand" "=r") 997: (neg:QI (match_operand:QI 1 "general_operand" "0")))] 998: "" 999: "neg %X0" 1000: [(set_attr "type" "arith") 1001: (set_attr "length" "2") 1.1.1.2 ! root 1002: (set_attr "cc" "clobber")]) 1.1 root 1003: 1004: (define_expand "neghi2" 1.1.1.2 ! root 1005: [(set (match_operand:HI 0 "register_operand" "=r") ! 1006: (neg:HI (match_operand:HI 1 "general_operand" "0")))] ! 1007: "" ! 1008: " ! 1009: { ! 1010: if (TARGET_H8300) ! 1011: { ! 1012: emit_insn (gen_neghi2_h8300 (operands[0], operands[1])); ! 1013: DONE; ! 1014: } ! 1015: }") ! 1016: ! 1017: (define_expand "neghi2_h8300" 1.1 root 1018: [(set (match_dup 2) 1019: (not:HI (match_operand:HI 1 "register_operand" "r"))) 1020: (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1))) 1021: (set (match_operand:HI 0 "register_operand" "=r") 1022: (match_dup 2))] 1023: "" 1.1.1.2 ! root 1024: "{ operands[2] = gen_reg_rtx (HImode); }") ! 1025: ! 1026: (define_insn "neghi2_h8300h" ! 1027: [(set (match_operand:HI 0 "register_operand" "=r") ! 1028: (neg:HI (match_operand:HI 1 "general_operand" "0")))] ! 1029: "TARGET_H8300H" ! 1030: "neg %T0" ! 1031: [(set_attr "type" "arith") ! 1032: (set_attr "length" "2") ! 1033: (set_attr "cc" "clobber")]) 1.1 root 1034: 1035: (define_expand "negsi2" 1.1.1.2 ! root 1036: [(set (match_operand:SI 0 "register_operand" "=r") ! 1037: (neg:SI (match_operand:SI 1 "general_operand" "0")))] ! 1038: "" ! 1039: " ! 1040: { ! 1041: if (TARGET_H8300) ! 1042: { ! 1043: emit_insn (gen_negsi2_h8300 (operands[0], operands[1])); ! 1044: DONE; ! 1045: } ! 1046: }") ! 1047: ! 1048: (define_expand "negsi2_h8300" 1.1 root 1049: [(set (match_dup 2) 1050: (not:SI (match_operand:SI 1 "register_operand" "r"))) 1051: (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1))) 1052: (set (match_operand:SI 0 "register_operand" "=r") 1053: (match_dup 2))] 1054: "" 1.1.1.2 ! root 1055: "{ operands[2] = gen_reg_rtx(SImode); }") ! 1056: ! 1057: (define_insn "negsi2_h8300h" ! 1058: [(set (match_operand:SI 0 "register_operand" "=r") ! 1059: (neg:SI (match_operand:SI 1 "general_operand" "0")))] ! 1060: "TARGET_H8300H" ! 1061: "neg %S0" ! 1062: [(set_attr "type" "arith") ! 1063: (set_attr "length" "2") ! 1064: (set_attr "cc" "clobber")]) ! 1065: 1.1 root 1066: ;; ---------------------------------------------------------------------- 1.1.1.2 ! root 1067: ;; NOT INSTRUCTIONS 1.1 root 1068: ;; ---------------------------------------------------------------------- 1069: 1070: (define_insn "one_cmplqi2" 1071: [(set (match_operand:QI 0 "register_operand" "=r") 1072: (not:QI (match_operand:QI 1 "general_operand" "0")))] 1073: "" 1074: "not %X0" 1075: [(set_attr "type" "arith") 1076: (set_attr "length" "2") 1077: (set_attr "cc" "set")]) 1078: 1079: (define_insn "one_cmplhi2" 1080: [(set (match_operand:HI 0 "register_operand" "=r") 1081: (not:HI (match_operand:HI 1 "general_operand" "0")))] 1082: "" 1.1.1.2 ! root 1083: "* ! 1084: { ! 1085: if (TARGET_H8300) ! 1086: return \"not %s0\;not %t0\"; ! 1087: else ! 1088: return \"not %T0\"; ! 1089: }" 1.1 root 1090: [(set_attr "type" "arith") 1091: (set_attr "length" "4") 1092: (set_attr "cc" "clobber")]) 1093: 1094: (define_insn "one_cmplsi2" 1095: [(set (match_operand:SI 0 "register_operand" "=r") 1096: (not:SI (match_operand:SI 1 "general_operand" "0")))] 1097: "" 1.1.1.2 ! root 1098: "* ! 1099: { ! 1100: if (TARGET_H8300) ! 1101: return \"not %w0\;not %x0\;not %y0\;not %z0\"; ! 1102: else ! 1103: return \"not %S0\"; ! 1104: }" 1.1 root 1105: [(set_attr "type" "arith") 1.1.1.2 ! root 1106: ;; ??? length is wrong for 300h 1.1 root 1107: (set_attr "length" "8") 1108: (set_attr "cc" "clobber")]) 1.1.1.2 ! root 1109: 1.1 root 1110: ;; ---------------------------------------------------------------------- 1.1.1.2 ! root 1111: ;; JUMP INSTRUCTIONS 1.1 root 1112: ;; ---------------------------------------------------------------------- 1113: 1.1.1.2 ! root 1114: ;; Conditional jump instructions ! 1115: 1.1 root 1116: (define_expand "ble" 1117: [(set (pc) 1118: (if_then_else (le (cc0) 1119: (const_int 0)) 1120: (label_ref (match_operand 0 "" "")) 1121: (pc)))] 1122: "" 1123: "") 1124: 1125: (define_expand "bleu" 1126: [(set (pc) 1127: (if_then_else (leu (cc0) 1128: (const_int 0)) 1129: (label_ref (match_operand 0 "" "")) 1130: (pc)))] 1131: "" 1132: "") 1133: 1134: (define_expand "bge" 1135: [(set (pc) 1136: (if_then_else (ge (cc0) 1137: (const_int 0)) 1138: (label_ref (match_operand 0 "" "")) 1139: (pc)))] 1140: "" 1141: "") 1142: 1143: (define_expand "bgeu" 1144: [(set (pc) 1145: (if_then_else (geu (cc0) 1146: (const_int 0)) 1147: (label_ref (match_operand 0 "" "")) 1148: (pc)))] 1149: "" 1150: "") 1151: 1152: (define_expand "blt" 1153: [(set (pc) 1154: (if_then_else (lt (cc0) 1155: (const_int 0)) 1156: (label_ref (match_operand 0 "" "")) 1157: (pc)))] 1158: "" 1159: "") 1160: 1161: (define_expand "bltu" 1162: [(set (pc) 1163: (if_then_else (ltu (cc0) 1164: (const_int 0)) 1165: (label_ref (match_operand 0 "" "")) 1166: (pc)))] 1167: "" 1168: "") 1169: 1170: (define_expand "bgt" 1171: [(set (pc) 1172: (if_then_else (gt (cc0) 1173: (const_int 0)) 1174: (label_ref (match_operand 0 "" "")) 1175: (pc)))] 1176: "" 1177: "") 1178: 1179: (define_expand "bgtu" 1180: [(set (pc) 1181: (if_then_else (gtu (cc0) 1182: (const_int 0)) 1183: (label_ref (match_operand 0 "" "")) 1184: (pc)))] 1185: "" 1186: "") 1187: 1188: (define_expand "beq" 1189: [(set (pc) 1190: (if_then_else (eq (cc0) 1191: (const_int 0)) 1192: (label_ref (match_operand 0 "" "")) 1193: (pc)))] 1194: "" 1195: "") 1196: 1197: (define_expand "bne" 1198: [(set (pc) 1199: (if_then_else (ne (cc0) 1200: (const_int 0)) 1201: (label_ref (match_operand 0 "" "")) 1202: (pc)))] 1203: "" 1204: "") 1205: 1.1.1.2 ! root 1206: (define_insn "branch_true" 1.1 root 1207: [(set (pc) 1.1.1.2 ! root 1208: (if_then_else (match_operator 1 "comparison_operator" ! 1209: [(cc0) (const_int 0)]) ! 1210: (label_ref (match_operand 0 "" "")) ! 1211: (pc)))] 1.1 root 1212: "" 1213: "* 1214: { 1215: if (get_attr_length (insn) == 2) 1.1.1.2 ! root 1216: return \"b%j1 %l0\"; ! 1217: else if (get_attr_length (insn) == 4) ! 1218: return \"b%j1 %l0:16\"; 1.1 root 1219: else 1.1.1.2 ! root 1220: return \"b%k1 %L0\;jmp @%l0\;%L0:\"; 1.1 root 1221: }" 1.1.1.2 ! root 1222: [(set_attr "type" "branch") 1.1 root 1223: (set_attr "cc" "none")]) 1224: 1.1.1.2 ! root 1225: (define_insn "branch_false" 1.1 root 1226: [(set (pc) 1.1.1.2 ! root 1227: (if_then_else (match_operator 1 "comparison_operator" ! 1228: [(cc0) (const_int 0)]) ! 1229: (pc) ! 1230: (label_ref (match_operand 0 "" ""))))] 1.1 root 1231: "" 1.1.1.2 ! root 1232: ;; ??? We don't take advantage of 16 bit relative jumps in the 300h. 1.1 root 1233: "* 1234: { 1235: if (get_attr_length (insn) == 2) 1.1.1.2 ! root 1236: return \"b%k1 %l0\"; ! 1237: else if (get_attr_length (insn) == 4) ! 1238: return \"b%k1 %l0:16\"; 1.1 root 1239: else 1.1.1.2 ! root 1240: return \"b%j1 %L0\;jmp @%l0\;%L0:\"; 1.1 root 1241: }" 1242: [(set_attr "type" "branch") 1243: (set_attr "cc" "none")]) 1.1.1.2 ! root 1244: ! 1245: ;; Unconditional and other jump instructions. 1.1 root 1246: 1247: (define_insn "jump" 1248: [(set (pc) 1249: (label_ref (match_operand 0 "" "")))] 1250: "" 1251: "* 1252: { 1.1.1.2 ! root 1253: if (get_attr_length (insn) == 2) ! 1254: return \"bra %l0\"; ! 1255: else if (get_attr_length (insn) == 4) ! 1256: return \"bra %l0:16\"; 1.1 root 1257: else 1.1.1.2 ! root 1258: return \"jmp @%l0\"; 1.1 root 1259: }" 1260: [(set_attr "type" "branch") 1261: (set_attr "cc" "none")]) 1262: 1.1.1.2 ! root 1263: ;; This is a define expand, because pointers may be either 16 or 32 bits. ! 1264: ! 1265: (define_expand "tablejump" ! 1266: [(parallel [(set (pc) (match_operand 0 "register_operand" "r")) ! 1267: (use (label_ref (match_operand 1 "" "")))])] ! 1268: "" ! 1269: "") ! 1270: ! 1271: (define_insn "tablejump_h8300" 1.1 root 1272: [(set (pc) (match_operand:HI 0 "register_operand" "")) 1273: (use (label_ref (match_operand 1 "" "")))] 1.1.1.2 ! root 1274: "TARGET_H8300" 1.1 root 1275: "jmp @%0" 1276: [(set_attr "type" "branch") 1277: (set_attr "cc" "none") 1278: (set_attr "length" "2")]) 1279: 1.1.1.2 ! root 1280: (define_insn "tablejump_h8300h" ! 1281: [(set (pc) (match_operand:SI 0 "register_operand" "")) ! 1282: (use (label_ref (match_operand 1 "" "")))] ! 1283: "TARGET_H8300H" ! 1284: "jmp @%0" ! 1285: [(set_attr "type" "branch") ! 1286: (set_attr "cc" "none") ! 1287: (set_attr "length" "2")]) 1.1 root 1288: 1.1.1.2 ! root 1289: ;; This is a define expand, because pointers may be either 16 or 32 bits. ! 1290: ! 1291: ;(define_insn "indirect_jump" ! 1292: ; [(set (pc) (match_operand:HI 0 "register_operand" "r"))] ! 1293: ; "" ! 1294: ; "jmp @%0" ! 1295: ; [(set_attr "type" "branch") ! 1296: ; (set_attr "cc" "none") ! 1297: ; (set_attr "length" "2")]) ! 1298: ! 1299: (define_expand "indirect_jump" ! 1300: [(set (pc) (match_operand 0 "jump_address_operand" "Vr"))] 1.1 root 1301: "" 1.1.1.2 ! root 1302: "") ! 1303: ! 1304: (define_insn "indirect_jump_h8300" ! 1305: [(set (pc) (match_operand:HI 0 "jump_address_operand" "V,r"))] ! 1306: "TARGET_H8300" ! 1307: "@ ! 1308: jmp @%0 ! 1309: jmp @%0" ! 1310: [(set_attr "type" "branch") ! 1311: (set_attr "cc" "none") ! 1312: (set_attr "length" "2")]) ! 1313: ! 1314: (define_insn "indirect_jump_h8300h" ! 1315: [(set (pc) (match_operand:SI 0 "jump_address_operand" "V,r"))] ! 1316: "TARGET_H8300H" ! 1317: "@ ! 1318: jmp @%0 ! 1319: jmp @%0" ! 1320: [(set_attr "type" "branch") ! 1321: (set_attr "cc" "none") ! 1322: (set_attr "length" "2")]) ! 1323: ! 1324: ;; Call subroutine with no return value. ! 1325: ! 1326: ;; ??? Even though we use HImode here, this works for the 300h. ! 1327: ! 1328: (define_insn "call" ! 1329: [(call (match_operand:QI 0 "call_insn_operand" "or") ! 1330: (match_operand:HI 1 "general_operand" "g"))] ! 1331: "" ! 1332: "jsr %0" 1.1 root 1333: [(set_attr "type" "call") 1334: (set_attr "cc" "clobber") 1335: (set_attr "length" "4")]) 1336: 1337: ;; Call subroutine, returning value in operand 0 1338: ;; (which must be a hard register). 1339: 1.1.1.2 ! root 1340: ;; ??? Even though we use HImode here, this works on the 300h. ! 1341: 1.1 root 1342: (define_insn "call_value" 1343: [(set (match_operand 0 "" "=r") 1.1.1.2 ! root 1344: (call (match_operand:QI 1 "call_insn_operand" "or") 1.1 root 1345: (match_operand:HI 2 "general_operand" "g")))] 1346: "" 1347: "jsr %1" 1348: [(set_attr "type" "call") 1349: (set_attr "cc" "clobber") 1350: (set_attr "length" "4")]) 1351: 1352: (define_insn "nop" 1353: [(const_int 0)] 1354: "" 1355: "nop" 1356: [(set_attr "type" "multi") 1357: (set_attr "cc" "none") 1358: (set_attr "length" "2")]) 1359: 1.1.1.2 ! root 1360: ;; ---------------------------------------------------------------------- ! 1361: ;; EXTEND INSTRUCTIONS ! 1362: ;; ---------------------------------------------------------------------- 1.1 root 1363: 1.1.1.2 ! root 1364: (define_insn "zero_extendqihi2" ! 1365: [(set (match_operand:HI 0 "register_operand" "=r,r") ! 1366: (zero_extend:HI (match_operand:QI 1 "general_operand" "0,g")))] 1.1 root 1367: "" 1.1.1.2 ! root 1368: "* ! 1369: { ! 1370: if (which_alternative==0) ! 1371: return \"mov.b #0,%t0\"; 1.1 root 1372: 1.1.1.2 ! root 1373: if (TARGET_H8300) ! 1374: return \"mov.b %X1,%s0\;mov.b #0,%t0\"; ! 1375: else ! 1376: { ! 1377: /* ??? See how often this gets optimized. */ ! 1378: if (REG_P (operands[1]) && (REGNO (operands[1]) == REGNO (operands[0]))) ! 1379: return \"extu.w %T0\"; ! 1380: else ! 1381: return \"mov.b %X1,%s0\;extu.w %T0\"; ! 1382: } ! 1383: }" ! 1384: [(set_attr "type" "multi") ! 1385: ;; ??? This length is wrong for one case. ! 1386: (set_attr "length" "4") ! 1387: (set_attr "cc" "clobber")]) 1.1 root 1388: 1.1.1.2 ! root 1389: (define_insn "zero_extendhisi2" ! 1390: [(set (match_operand:SI 0 "register_operand" "=r") ! 1391: (zero_extend:SI (match_operand:HI 1 "general_operand" "g")))] ! 1392: "TARGET_H8300H" ! 1393: "* 1.1 root 1394: { 1.1.1.2 ! root 1395: /* ??? See how often this gets optimized. */ ! 1396: if (REG_P (operands[1]) && (REGNO (operands[1]) == REGNO (operands[0]))) ! 1397: return \"extu.l %S0\"; 1.1 root 1398: else 1.1.1.2 ! root 1399: return \"mov.w %T1,%T0\;extu.l %S0\"; ! 1400: }" ! 1401: [(set_attr "type" "multi") ! 1402: ;; ??? This length is wrong for one case. ! 1403: (set_attr "length" "4") ! 1404: (set_attr "cc" "clobber")]) 1.1 root 1405: 1.1.1.2 ! root 1406: (define_insn "extendqihi2" ! 1407: [(set (match_operand:HI 0 "register_operand" "=r") ! 1408: (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))] 1.1 root 1409: "" 1.1.1.2 ! root 1410: "* 1.1 root 1411: { 1.1.1.2 ! root 1412: if (TARGET_H8300) ! 1413: { ! 1414: /* ??? See how often this gets optimized. */ ! 1415: if (REG_P (operands[1]) && (REGNO (operands[1]) == REGNO (operands[0]))) ! 1416: return \"bld #7,%s0\;subx %t0,%t0\"; ! 1417: else ! 1418: return \"mov.b %X1,%s0\;bld #7,%s0\;subx %t0,%t0\"; ! 1419: } 1.1 root 1420: else 1.1.1.2 ! root 1421: { ! 1422: /* ??? See how often this gets optimized. */ ! 1423: if (REG_P (operands[1]) && (REGNO (operands[1]) == REGNO (operands[0]))) ! 1424: return \"exts.w %T0\"; ! 1425: else ! 1426: return \"mov.b %X1,%s0\;exts.w %T0\"; ! 1427: } ! 1428: }" ! 1429: [(set_attr "type" "multi") ! 1430: ;; ??? Length is wrong in some cases. ! 1431: (set_attr "length" "6") ! 1432: (set_attr "cc" "clobber")]) 1.1 root 1433: 1.1.1.2 ! root 1434: (define_expand "extendhisi2" ! 1435: [(set (match_operand:SI 0 "register_operand" "") ! 1436: (sign_extend:SI (match_operand:HI 1 "general_operand" "")))] 1.1 root 1437: "" 1438: " 1439: { 1.1.1.2 ! root 1440: if (TARGET_H8300) ! 1441: emit_insn (gen_extendhisi2_h8300 (operands[0], operands[1])); 1.1 root 1442: else 1.1.1.2 ! root 1443: emit_insn (gen_extendhisi2_h8300h (operands[0], operands[1])); ! 1444: DONE; 1.1 root 1445: }") 1446: 1.1.1.2 ! root 1447: (define_expand "extendhisi2_h8300" ! 1448: [(set (reg:HI 1) (match_operand:HI 1 "general_operand" "")) ! 1449: (set (reg:SI 0) (sign_extend:SI (reg:HI 1))) ! 1450: (set (match_operand:SI 0 "general_operand" "" ) (reg:SI 0))] ! 1451: "TARGET_H8300" ! 1452: "") 1.1 root 1453: 1.1.1.2 ! root 1454: (define_expand "extendhisi2_h8300h" ! 1455: [(set (match_operand:SI 0 "register_operand" "") ! 1456: (sign_extend:SI (match_operand:HI 1 "general_operand" "")))] ! 1457: "TARGET_H8300H" ! 1458: "") 1.1 root 1459: 1.1.1.2 ! root 1460: (define_insn "extendhisi2_h8300_internal" ! 1461: [(set (match_operand:SI 0 "register_operand" "=r") ! 1462: (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))] ! 1463: "TARGET_H8300" ! 1464: "mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0" ! 1465: [(set_attr "length" "10") 1.1 root 1466: (set_attr "cc" "clobber")]) 1467: 1.1.1.2 ! root 1468: (define_insn "extendhisi2_h8300h_internal" ! 1469: [(set (match_operand:SI 0 "register_operand" "=r") ! 1470: (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))] ! 1471: "TARGET_H8300H" ! 1472: "* 1.1 root 1473: { 1.1.1.2 ! root 1474: /* ??? See how often this gets optimized. */ ! 1475: if (REG_P (operands[1]) && (REGNO (operands[1]) == REGNO (operands[0]))) ! 1476: return \"exts.l %S0\"; 1.1 root 1477: else 1.1.1.2 ! root 1478: return \"mov.w %T1,%T0\;exts.l %S0\"; ! 1479: }" ! 1480: [(set_attr "length" "10") ! 1481: (set_attr "cc" "clobber")]) 1.1 root 1482: 1.1.1.2 ! root 1483: ;; ---------------------------------------------------------------------- ! 1484: ;; SHIFTS ! 1485: ;; ---------------------------------------------------------------------- ! 1486: ;; ! 1487: ;; We make some attempt to provide real efficient shifting. One example is ! 1488: ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other ! 1489: ;; reg and moving 0 into the former reg. ! 1490: ;; ! 1491: ;; We also try to achieve this in a uniform way. IE: We don't try to achieve ! 1492: ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would ! 1493: ;; give the optimizer more cracks at the code. However, we wish to do things ! 1494: ;; like optimizing shifting the sign bit to bit 0 by rotating the other way. ! 1495: ;; There is rtl to handle this (rotate + and), but the h8/300 doesn't handle ! 1496: ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able ! 1497: ;; to detect cases it can optimize. ! 1498: ;; ! 1499: ;; For these and other fuzzy reasons, I've decided to go the less pretty but ! 1500: ;; easier "do it at insn emit time" route. ! 1501: ! 1502: ;; QI BIT SHIFTS ! 1503: ! 1504: (define_expand "ashlqi3" ! 1505: [(set (match_operand:QI 0 "register_operand" "") ! 1506: (ashift:QI (match_operand:QI 1 "register_operand" "") ! 1507: (match_operand:QI 2 "nonmemory_operand" "")))] 1.1 root 1508: "" 1.1.1.2 ! root 1509: "if (expand_a_shift (QImode, ASHIFT, operands)) DONE;else FAIL;") 1.1 root 1510: 1.1.1.2 ! root 1511: (define_expand "ashrqi3" ! 1512: [(set (match_operand:QI 0 "register_operand" "") ! 1513: (ashiftrt:QI (match_operand:QI 1 "register_operand" "") ! 1514: (match_operand:QI 2 "nonmemory_operand" "")))] 1.1 root 1515: "" 1.1.1.2 ! root 1516: "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE;else FAIL;") 1.1 root 1517: 1.1.1.2 ! root 1518: (define_expand "lshrqi3" ! 1519: [(set (match_operand:QI 0 "register_operand" "") ! 1520: (lshiftrt:QI (match_operand:QI 1 "register_operand" "") ! 1521: (match_operand:QI 2 "nonmemory_operand" "")))] 1.1 root 1522: "" 1.1.1.2 ! root 1523: "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE;else FAIL;") 1.1 root 1524: 1.1.1.2 ! root 1525: ;; WARNING: The constraints on the scratch register say one is not needed ! 1526: ;; for constant shifts of 1,2,3,4. Emit_a_shift() must know this. ! 1527: ! 1528: (define_insn "shiftbyn_QI" ! 1529: [(set (match_operand:QI 0 "register_operand" "=r,r") ! 1530: (match_operator:QI 3 "nshift_operator" ! 1531: [ (match_operand:QI 1 "register_operand" "0,0") ! 1532: (match_operand:QI 2 "nonmemory_operand" "IKM,rn")])) ! 1533: (clobber (match_scratch:QI 4 "=X,&r"))] 1.1 root 1534: "" 1.1.1.2 ! root 1535: "* return emit_a_shift (insn, operands);" ! 1536: [(set_attr "type" "arith") ! 1537: (set_attr "length" "20") ! 1538: ;; ??? We'd like to indicate that cc is set here, and it is for simple shifts. ! 1539: ;; However, for cases that loop or are done in pieces, cc does not contain ! 1540: ;; what we want. Emit_a_shift is free to tweak cc_status as desired. 1.1 root 1541: (set_attr "cc" "clobber")]) 1542: 1.1.1.2 ! root 1543: ;; HI BIT SHIFTS 1.1 root 1544: 1.1.1.2 ! root 1545: (define_expand "ashlhi3" ! 1546: [(set (match_operand:HI 0 "register_operand" "") ! 1547: (ashift:HI (match_operand:HI 1 "nonmemory_operand" "") ! 1548: (match_operand:QI 2 "nonmemory_operand" "")))] 1.1 root 1549: "" 1.1.1.2 ! root 1550: "if (expand_a_shift (HImode, ASHIFT, operands)) DONE;else FAIL;") ! 1551: ! 1552: (define_expand "lshrhi3" ! 1553: [(set (match_operand:HI 0 "register_operand" "") ! 1554: (lshiftrt:HI (match_operand:HI 1 "general_operand_src" "") ! 1555: (match_operand:QI 2 "nonmemory_operand" "")))] ! 1556: "" ! 1557: "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE;else FAIL;") 1.1 root 1558: 1559: (define_expand "ashrhi3" 1560: [(set (match_operand:HI 0 "register_operand" "") 1.1.1.2 ! root 1561: (ashiftrt:HI (match_operand:HI 1 "register_operand" "") ! 1562: (match_operand:QI 2 "nonmemory_operand" "")))] 1.1 root 1563: "" 1.1.1.2 ! root 1564: "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE;else FAIL;") 1.1 root 1565: 1.1.1.2 ! root 1566: ;; WARNING: The constraints on the scratch register say one is not needed ! 1567: ;; for constant shifts of 1,2,3,4. Emit_a_shift() must know this. 1.1 root 1568: 1.1.1.2 ! root 1569: (define_insn "shiftbyn_HI" ! 1570: [(set (match_operand:HI 0 "register_operand" "=r,r") ! 1571: (match_operator:HI 3 "nshift_operator" ! 1572: [ (match_operand:HI 1 "register_operand" "0,0") ! 1573: (match_operand:QI 2 "nonmemory_operand" "IKM,rn")])) ! 1574: (clobber (match_scratch:QI 4 "=X,&r"))] 1.1 root 1575: "" 1.1.1.2 ! root 1576: "* return emit_a_shift (insn, operands);" ! 1577: [(set_attr "type" "arith") ! 1578: (set_attr "length" "20") ! 1579: ;; ??? We'd like to indicate that cc is set here, and it is for simple shifts. ! 1580: ;; However, for cases that loop or are done in pieces, cc does not contain ! 1581: ;; what we want. Emit_a_shift is free to tweak cc_status as desired. 1.1 root 1582: (set_attr "cc" "clobber")]) 1583: 1.1.1.2 ! root 1584: ;; SI BIT SHIFTS ! 1585: 1.1 root 1586: (define_expand "ashlsi3" 1587: [(set (match_operand:SI 0 "register_operand" "") 1588: (ashift:SI 1589: (match_operand:SI 1 "general_operand_src" "") 1.1.1.2 ! root 1590: (match_operand:QI 2 "nonmemory_operand" "")))] 1.1 root 1591: "" 1.1.1.2 ! root 1592: "if (expand_a_shift (SImode, ASHIFT, operands)) DONE;else FAIL;") 1.1 root 1593: 1594: (define_expand "lshrsi3" 1595: [(set (match_operand:SI 0 "register_operand" "") 1596: (lshiftrt:SI 1597: (match_operand:SI 1 "general_operand_src" "") 1.1.1.2 ! root 1598: (match_operand:QI 2 "nonmemory_operand" "")))] 1.1 root 1599: "" 1.1.1.2 ! root 1600: "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE;else FAIL;") 1.1 root 1601: 1602: (define_expand "ashrsi3" 1603: [(set (match_operand:SI 0 "register_operand" "") 1604: (ashiftrt:SI 1605: (match_operand:SI 1 "general_operand_src" "") 1.1.1.2 ! root 1606: (match_operand:QI 2 "nonmemory_operand" "")))] 1.1 root 1607: "" 1.1.1.2 ! root 1608: "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE;else FAIL;") 1.1 root 1609: 1.1.1.2 ! root 1610: ;; WARNING: The constraints on the scratch register say one is not needed ! 1611: ;; for constant shifts of 1,2. Emit_a_shift() must know this. 1.1 root 1612: 1.1.1.2 ! root 1613: (define_insn "shiftbyn_SI" ! 1614: [(set (match_operand:SI 0 "register_operand" "=r,r") ! 1615: (match_operator:SI 3 "nshift_operator" ! 1616: [ (match_operand:SI 1 "register_operand" "0,0") ! 1617: (match_operand:QI 2 "nonmemory_operand" "IK,rn")])) ! 1618: (clobber (match_scratch:QI 4 "=X,&r"))] 1.1 root 1619: "" 1.1.1.2 ! root 1620: "* return emit_a_shift (insn, operands);" ! 1621: [(set_attr "type" "arith") ! 1622: (set_attr "length" "20") ! 1623: ;; ??? We'd like to indicate that cc is set here, and it is for simple shifts. ! 1624: ;; However, for cases that loop or are done in pieces, cc does not contain ! 1625: ;; what we want. Emit_a_shift is free to tweak cc_status as desired. 1.1 root 1626: (set_attr "cc" "clobber")]) 1627: 1.1.1.2 ! root 1628: ;; ----------------------------------------------------------------- ! 1629: ;; BIT FIELDS ! 1630: ;; ----------------------------------------------------------------- ! 1631: ;; The H8/300 has given 1/8th of its opcode space to bitfield ! 1632: ;; instuctions so let's use them as well as we can 1.1 root 1633: 1.1.1.2 ! root 1634: ;; BCC and BCS patterns. ! 1635: ! 1636: (define_insn "bcs_qiqi" ! 1637: [(set (pc) ! 1638: (if_then_else ! 1639: (match_operator 1 "eq_operator" ! 1640: [(zero_extract:QI (match_operand:QI 2 "bit_operand" "Ur") ! 1641: (const_int 1) ! 1642: (match_operand:HI 3 "immediate_operand" "i")) ! 1643: (const_int 0)]) ! 1644: (label_ref (match_operand 0 "" "")) ! 1645: (pc)))] 1.1 root 1646: "" 1.1.1.2 ! root 1647: "* ! 1648: { ! 1649: output_asm_insn(\"bld %Z3,%Y2\", operands); ! 1650: if (get_attr_length (insn) == 2) ! 1651: return \"b%d1 %l0\"; ! 1652: else if (get_attr_length (insn) == 4) ! 1653: return \"b%d1 %l0:16\"; ! 1654: else ! 1655: return \"b%g1 %L0\;jmp @%l0\;%L0:\"; ! 1656: }" ! 1657: [(set_attr "type" "branch") 1.1 root 1658: (set_attr "cc" "clobber")]) 1659: 1.1.1.2 ! root 1660: (define_insn "bcs_hihi" ! 1661: [(set (pc) ! 1662: (if_then_else ! 1663: (match_operator 1 "eq_operator" ! 1664: [(zero_extract:HI (match_operand:HI 2 "bit_operand" "Ur") ! 1665: (const_int 1) ! 1666: (match_operand:HI 3 "immediate_operand" "i")) ! 1667: (const_int 0)]) ! 1668: (label_ref (match_operand 0 "" "")) ! 1669: (pc)))] 1.1 root 1670: "" 1.1.1.2 ! root 1671: "* ! 1672: { ! 1673: output_asm_insn(\"bld %Z3,%Y2\", operands); ! 1674: if (get_attr_length (insn) == 2) ! 1675: return \"%d1 %l0\"; ! 1676: else if (get_attr_length (insn) == 4) ! 1677: return \"%d1 %l0:16\"; ! 1678: else ! 1679: return \"%g1 %L0\;jmp @%l0\;%L0:\"; ! 1680: }" ! 1681: [(set_attr "type" "branch") 1.1 root 1682: (set_attr "cc" "clobber")]) 1683: 1.1.1.2 ! root 1684: (define_insn "bcs_hiqi" ! 1685: [(set (pc) ! 1686: (if_then_else ! 1687: (match_operator 1 "eq_operator" ! 1688: [(zero_extract:HI (match_operand:QI 2 "bit_operand" "Ur") ! 1689: (const_int 1) ! 1690: (match_operand:HI 3 "immediate_operand" "i")) ! 1691: (const_int 0)]) ! 1692: (label_ref (match_operand 0 "" "")) ! 1693: (pc)))] 1.1 root 1694: "" 1.1.1.2 ! root 1695: "* ! 1696: { ! 1697: output_asm_insn(\"bld %Z3,%Y2\", operands); ! 1698: if (get_attr_length (insn) == 2) ! 1699: return \"%d1 %l0\"; ! 1700: else if (get_attr_length (insn) == 4) ! 1701: return \"%d1 %l0:16\"; ! 1702: else ! 1703: return \"%g1 %L0\;jmp @%l0\;%L0:\"; ! 1704: }" ! 1705: [(set_attr "type" "branch") ! 1706: (set_attr "cc" "clobber")]) 1.1 root 1707: 1.1.1.2 ! root 1708: ;; BLD and BST patterns ! 1709: ! 1710: (define_insn "extract_1" ! 1711: [(set (match_operand:HI 0 "register_operand" "=&r") ! 1712: (zero_extract:HI (match_operand:QI 1 "bit_operand" "Ur") ! 1713: (const_int 1) ! 1714: (match_operand:HI 2 "immediate_operand" "i")))] 1.1 root 1715: "" 1.1.1.2 ! root 1716: "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0") 1.1 root 1717: 1.1.1.2 ! root 1718: (define_insn "extract_1_hi" ! 1719: [(set (match_operand:HI 0 "register_operand" "=&r") ! 1720: (zero_extract:HI (match_operand:HI 1 "bit_operand" "Ur") ! 1721: (const_int 1) ! 1722: (match_operand:HI 2 "immediate_operand" "i")))] 1.1 root 1723: "" 1.1.1.2 ! root 1724: "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0") 1.1 root 1725: 1.1.1.2 ! root 1726: (define_insn "insert_1" ! 1727: [(set (zero_extract:HI (match_operand:QI 0 "bit_operand" "+Ur") ! 1728: (const_int 1) ! 1729: (match_operand:HI 1 "immediate_operand" "i")) ! 1730: (zero_extract:HI (match_operand:QI 2 "bit_operand" "Ur") ! 1731: (const_int 1) ! 1732: (const_int 0)))] 1.1 root 1733: "" 1.1.1.2 ! root 1734: "bld #0,%X2\;bst %Z1,%Y0 ; i1") ! 1735: ! 1736: ;; This is how combine canonicalizes this pattern. This is perhaps a bug ! 1737: ;; in combine.c, but there is no problem with writing it this way so we do. ! 1738: (define_insn "extract_insert_1" ! 1739: [(set (zero_extract:QI (match_operand:QI 0 "bit_operand" "+Ur") ! 1740: (const_int 1) ! 1741: (match_operand:HI 1 "immediate_operand" "i")) ! 1742: (lshiftrt:QI (match_operand:QI 2 "bit_operand" "Ur") ! 1743: (match_operand:HI 3 "immediate_operand" "i")))] ! 1744: "" ! 1745: "bld %Z3,%Y2\;bst %Z1,%Y0; ei1") ! 1746: ! 1747: ;; BAND, BOR, and BXOR patterns ! 1748: ! 1749: (define_insn "bitlogical_1" ! 1750: [(set (match_operand:HI 0 "bit_operand" "=Ur") ! 1751: (match_operator:HI 4 "bit_operator" ! 1752: [(zero_extract:HI (match_operand:QI 1 "bit_operand" "Ur") ! 1753: (const_int 1) ! 1754: (match_operand:HI 2 "immediate_operand" "i")) ! 1755: (match_operand:HI 3 "bit_operand" "0")]))] ! 1756: "" ! 1757: "bld %Z2,%Y1\;%b4 #0,%X0\;bst #0,%X0; bl1") ! 1758: ! 1759: (define_insn "bitlogical_1_hi" ! 1760: [(set (match_operand:HI 0 "bit_operand" "=Ur") ! 1761: (match_operator:HI 4 "bit_operator" ! 1762: [(zero_extract:HI (match_operand:HI 1 "bit_operand" "Ur") ! 1763: (const_int 1) ! 1764: (match_operand:HI 2 "immediate_operand" "i")) ! 1765: (match_operand:HI 3 "bit_operand" "0")]))] ! 1766: "" ! 1767: "bld %Z2,%Y1\;%b4 #0,%X0\;bst #0,%X0; bl2") ! 1768: ! 1769: (define_insn "bitlogical_2" ! 1770: [(set (match_operand:HI 0 "bit_operand" "=Ur") ! 1771: (match_operator:HI 5 "bit_operator" ! 1772: [(zero_extract:HI (match_operand:QI 1 "bit_operand" "Ur") ! 1773: (const_int 1) ! 1774: (match_operand:HI 2 "immediate_operand" "i")) ! 1775: (zero_extract:HI (match_operand:QI 3 "bit_operand" "Ur") ! 1776: (const_int 1) ! 1777: (match_operand:HI 4 "immediate_operand" "i"))]))] ! 1778: "" ! 1779: "bld %Z2,%Y1\;%b5 %Z4,%Y3\;bst #0,%X0; bl3") ! 1780: ! 1781: (define_insn "bitlogical_2_hi" ! 1782: [(set (match_operand:HI 0 "bit_operand" "=Ur") ! 1783: (match_operator:HI 5 "bit_operator" ! 1784: [(zero_extract:HI (match_operand:HI 1 "bit_operand" "Ur") ! 1785: (const_int 1) ! 1786: (match_operand:HI 2 "immediate_operand" "i")) ! 1787: (zero_extract:HI (match_operand:HI 3 "bit_operand" "Ur") ! 1788: (const_int 1) ! 1789: (match_operand:HI 4 "immediate_operand" "i"))]))] ! 1790: "" ! 1791: "bld %Z2,%Y1\;%b5 %Z4,%Y3\;bst #0,%X0; bl3") ! 1792: ! 1793: ;; This is how combine canonicalizes this pattern. This is perhaps a bug ! 1794: ;; in combine.c, but there is no problem with writing it this way so we do. ! 1795: (define_insn "bitlogical_3" ! 1796: [(set (zero_extract:QI (match_operand:QI 0 "bit_operand" "+Ur") ! 1797: (const_int 1) ! 1798: (match_operand:HI 1 "immediate_operand" "i")) ! 1799: (match_operator:QI 6 "bit_operator" ! 1800: [(lshiftrt:QI (match_operand:QI 2 "bit_operand" "Ur") ! 1801: (match_operand:HI 3 "immediate_operand" "i")) ! 1802: (lshiftrt:QI (match_operand:QI 4 "bit_operand" "Ur") ! 1803: (match_operand:HI 5 "immediate_operand" "i"))]))] ! 1804: "" ! 1805: "bld %Z3,%Y2\;%b6 %Z5,%Y4\;bst %Z1,%Y0; bl5") ! 1806: ! 1807: ;; This is how combine canonicalizes this pattern. This is perhaps a bug ! 1808: ;; in combine.c, but there is no problem with writing it this way so we do. ! 1809: (define_insn "bitnot_1" ! 1810: [(set (zero_extract:QI (match_operand:QI 0 "bit_operand" "=Ur") ! 1811: (const_int 1) ! 1812: (match_operand:HI 1 "immediate_operand" "i")) ! 1813: (lshiftrt:QI (xor:QI (match_operand:QI 2 "bit_operand" "0") ! 1814: (match_operand:HI 3 "immediate_operand" "i")) ! 1815: (match_operand:HI 4 "immediate_operand" "1")))] ! 1816: "GET_CODE (operands[3]) == CONST_INT && GET_CODE (operands[1]) == CONST_INT ! 1817: && exact_log2 (INTVAL (operands[3])) == INTVAL (operands[1])" ! 1818: "bnot %Z1,%Y0") ! 1819: ! 1820: ;; ??? Implement BIAND, BIOR, BIXOR ! 1821: ! 1822: ;; ??? Implement BILD, BIST ! 1823: ! 1824: ;; ??? Apparently general_operand for the 1st and 2nd operands is useful, ! 1825: ;; but I don't know why. --Jim ! 1826: ! 1827: (define_expand "insv" ! 1828: [(set (zero_extract:HI (match_operand:QI 0 "bit_operand" "Ur") ! 1829: (match_operand:HI 1 "general_operand" "g") ! 1830: (match_operand:HI 2 "general_operand" "g")) ! 1831: (zero_extract:HI (match_operand:QI 3 "bit_operand" "Ur") ! 1832: (const_int 1) ! 1833: (const_int 0)))] ! 1834: ;; ??? This should have word mode which is SImode for the h8/300h. ! 1835: "TARGET_H8300" ! 1836: " 1.1 root 1837: { 1.1.1.2 ! root 1838: if (INTVAL (operands[1]) != 1) ! 1839: FAIL; ! 1840: ! 1841: /* ??? HACK ??? ! 1842: This INSV pattern is wrong. It should use HImode for operand 3. ! 1843: Also, the zero_extract around operand 3 is superfluous and should be ! 1844: deleted. Fixing this is more work than we care to do for the moment, ! 1845: because it means most of the above patterns would need to be rewritten, ! 1846: and we also need more combine.c patches to make this work. ! 1847: ! 1848: So, for now, we work around this bug by simply not accepting any bitfield ! 1849: inserts that have a position greater than fits in QImode. */ ! 1850: ! 1851: if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) >= 8) ! 1852: FAIL; ! 1853: ! 1854: /* The bit_operand predicate accepts any memory durint RTL generation, but ! 1855: only 'U' memory afterwards, so if this is a MEM operand, we must force ! 1856: it to be valid for 'U' by reloading the address. */ ! 1857: ! 1858: if (GET_CODE (operands[0]) == MEM && ! EXTRA_CONSTRAINT (operands[0], 'U')) ! 1859: { ! 1860: rtx mem; ! 1861: mem = gen_rtx (MEM, GET_MODE (operands[0]), ! 1862: copy_to_mode_reg (Pmode, XEXP (operands[0], 0))); ! 1863: RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (operands[0]); ! 1864: MEM_IN_STRUCT_P (mem) = MEM_IN_STRUCT_P (operands[0]); ! 1865: MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (operands[0]); ! 1866: operands[0] = mem; ! 1867: } ! 1868: ! 1869: /* Likewise for operands[3]. */ ! 1870: ! 1871: if (GET_CODE (operands[3]) == MEM && ! EXTRA_CONSTRAINT (operands[3], 'U')) ! 1872: { ! 1873: rtx mem; ! 1874: mem = gen_rtx (MEM, GET_MODE (operands[3]), ! 1875: copy_to_mode_reg (Pmode, XEXP (operands[3], 0))); ! 1876: RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (operands[3]); ! 1877: MEM_IN_STRUCT_P (mem) = MEM_IN_STRUCT_P (operands[3]); ! 1878: MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (operands[3]); ! 1879: operands[3] = mem; ! 1880: } ! 1881: }") ! 1882: ! 1883: ;; ??? Apparently general_operand for the 2nd and 3rd operands is useful, ! 1884: ;; but I don't know why. --Jim ! 1885: ! 1886: (define_expand "extzv" ! 1887: [(set (match_operand:HI 0 "register_operand" "") ! 1888: (zero_extract:HI (match_operand:QI 1 "bit_operand" "") ! 1889: (match_operand:HI 2 "general_operand" "g") ! 1890: (match_operand:HI 3 "general_operand" "g")))] ! 1891: ;; ??? This should have word mode which is SImode for the h8/300h. ! 1892: "TARGET_H8300" ! 1893: " ! 1894: { ! 1895: if (INTVAL (operands[2]) != 1) ! 1896: FAIL; ! 1897: ! 1898: /* The bit_operand predicate accepts any memory durint RTL generation, but ! 1899: only 'U' memory afterwards, so if this is a MEM operand, we must force ! 1900: it to be valid for 'U' by reloading the address. */ ! 1901: ! 1902: if (GET_CODE (operands[1]) == MEM && ! EXTRA_CONSTRAINT (operands[1], 'U')) ! 1903: { ! 1904: rtx mem; ! 1905: mem = gen_rtx (MEM, GET_MODE (operands[1]), ! 1906: copy_to_mode_reg (Pmode, XEXP (operands[1], 0))); ! 1907: RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (operands[1]); ! 1908: MEM_IN_STRUCT_P (mem) = MEM_IN_STRUCT_P (operands[1]); ! 1909: MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (operands[1]); ! 1910: operands[1] = mem; ! 1911: } ! 1912: }") ! 1913: ! 1914: ;; ----------------------------------------------------------------- ! 1915: ;; STACK POINTER MANIPULATIONS ! 1916: ;; ----------------------------------------------------------------- ! 1917: ! 1918: ;; This pattern is needed because there is no way on the H8/300 ! 1919: ;; to add a 16 bit immediate value to the stack pointer in one ! 1920: ;; instruction, which could leave an invalid instruction if interrupted ! 1921: ;; half way through. Here we add to the stack pointer from a ! 1922: ;; register. ! 1923: ! 1924: (define_insn "stack_pointer_manip" ! 1925: [(set (match_operand:HI 0 "register_operand" "=&ra") ! 1926: (plus:HI (match_operand:HI 1 "general_operand_src" "g") ! 1927: (match_operand:HI 2 "register_operand" "ra")))] ! 1928: "TARGET_H8300" ! 1929: "mov.w %T1,%T0\;add.w %T2,%T0" ! 1930: [(set_attr "type" "arith") 1.1 root 1931: (set_attr "length" "6") 1.1.1.2 ! root 1932: (set_attr "cc" "set")]) 1.1 root 1933: 1934: 1.1.1.2 ! root 1935: ;; ------------------------------------------- ! 1936: ;; BLK moves ! 1937: ;; ------------------------------------------- ! 1938: ! 1939: (define_expand "movstrhi" ! 1940: [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" "")) ! 1941: (mem:BLK (match_operand:BLK 1 "general_operand" ""))) ! 1942: (use (match_operand:HI 2 "general_operand" "")) ! 1943: (use (match_operand:HI 3 "immediate_operand" "")) ! 1944: (clobber (match_dup 3)) ! 1945: ])] 1.1 root 1946: "" 1.1.1.2 ! root 1947: " ! 1948: { ! 1949: rtx src_ptr = copy_to_mode_reg (Pmode, XEXP(operands[1], 0)); ! 1950: rtx dst_ptr = copy_to_mode_reg (Pmode, XEXP(operands[0], 0)); ! 1951: ! 1952: int max = GET_CODE (operands[2]) == CONST_INT ! 1953: ? MIN (INTVAL (operands[2]), INTVAL (operands[3])) : 1; ! 1954: enum machine_mode mode = max >= 2 ? HImode : QImode; ! 1955: rtx tmpreg = gen_reg_rtx (mode); ! 1956: rtx increment = mode == QImode ? const1_rtx : const2_rtx; ! 1957: rtx length = operands[2]; ! 1958: rtx label = gen_label_rtx (); ! 1959: rtx end_src_ptr = gen_reg_rtx (Pmode); ! 1960: ! 1961: /* emit_move_insn (length, gen_rtx(MINUS, HImode, length, increment));*/ ! 1962: FAIL; ! 1963: if (Pmode == HImode) ! 1964: emit_insn (gen_addhi3 (end_src_ptr, src_ptr, length)); ! 1965: else ! 1966: emit_insn (gen_addsi3 (end_src_ptr, src_ptr, length)); ! 1967: ! 1968: emit_label (label); ! 1969: emit_move_insn (tmpreg, gen_rtx (MEM, mode, src_ptr)); ! 1970: emit_move_insn (gen_rtx (MEM, mode, dst_ptr), tmpreg); ! 1971: emit_insn (gen_rtx (SET, VOIDmode, src_ptr, ! 1972: gen_rtx (PLUS, Pmode, src_ptr, increment))); ! 1973: emit_insn (gen_rtx (SET, VOIDmode, dst_ptr, ! 1974: gen_rtx (PLUS, Pmode, dst_ptr, increment))); ! 1975: ! 1976: emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx, ! 1977: gen_rtx (COMPARE, Pmode, src_ptr, end_src_ptr))); ! 1978: emit_jump_insn (gen_bne (label)); 1.1 root 1979: 1.1.1.2 ! root 1980: DONE; ! 1981: }") 1.1 root 1982: 1.1.1.2 ! root 1983: ;; ---------------------------------------------- ! 1984: ;; Peepholes go at the end. ! 1985: ;; ---------------------------------------------- ! 1986: ! 1987: ;; Notice when two byte moves in a row could be a word move. ! 1988: ! 1989: (define_peephole ! 1990: [(set (match_operand:QI 0 "register_operand" "=r") ! 1991: (mem:QI (plus:HI (match_operand:HI 1 "register_operand" "ra") ! 1992: (match_operand:HI 2 "immediate_operand" "n")))) ! 1993: (set (match_operand:QI 3 "register_operand" "=r") ! 1994: (mem:QI (plus:HI (match_dup 1) ! 1995: (match_operand:HI 4 "immediate_operand" "n"))))] ! 1996: "(INTVAL(operands[2]) == INTVAL(operands[4])+1) && REGNO(operands[0]) +1 == REGNO(operands[3])" ! 1997: "mov.w @(%u4,%T1),%T0" ! 1998: [(set_attr "length" "6") 1.1 root 1999: (set_attr "cc" "set")]) 2000: 1.1.1.2 ! root 2001: (define_peephole ! 2002: [(set (mem:QI (plus:HI (match_operand:HI 1 "register_operand" "ra") ! 2003: (match_operand:HI 2 "immediate_operand" "n"))) ! 2004: (match_operand:QI 0 "register_operand" "r")) ! 2005: (set (mem:QI (plus:HI (match_dup 1) ! 2006: (match_operand:HI 4 "immediate_operand" "n"))) ! 2007: (match_operand:QI 3 "register_operand" "r"))] ! 2008: "(INTVAL(operands[2]) == INTVAL(operands[4])+1) && REGNO(operands[0]) +1 == REGNO(operands[3])" ! 2009: "mov.w %T0,@(%u4,%T1)" ! 2010: [(set_attr "length" "6") ! 2011: (set_attr "cc" "set")]) ! 2012: ! 2013: ;; Notice a move which could be post incremented. ! 2014: 1.1 root 2015: (define_peephole 1.1.1.2 ! root 2016: [(set (match_operand:QI 0 "register_operand" "") ! 2017: (mem:QI (match_operand:HI 1 "register_operand" ""))) ! 2018: (set (match_dup 1) (plus:HI (match_dup 1) (const_int 1)))] ! 2019: "REGNO(operands[1]) != REGNO(operands[0])" ! 2020: "mov.b @%T1+,%X0" 1.1 root 2021: [(set_attr "length" "2") 2022: (set_attr "cc" "set")]) 2023: 2024: (define_peephole 2025: [(set (match_operand:HI 0 "register_operand" "") 2026: (mem:HI (match_operand:HI 1 "register_operand" ""))) 2027: (set (match_dup 1) (plus:HI (match_dup 1) (const_int 2)))] 1.1.1.2 ! root 2028: "REGNO(operands[1]) != REGNO(operands[0])" 1.1 root 2029: "mov.w @%T1+,%T0" 2030: [(set_attr "length" "2") 2031: (set_attr "cc" "set")]) 2032: 1.1.1.2 ! root 2033: ;; Notice a move which could be predecremented. ! 2034: 1.1 root 2035: (define_peephole 1.1.1.2 ! root 2036: [(set (match_operand:HI 1 "register_operand" "") ! 2037: (plus:HI (match_dup 1) (const_int -1))) ! 2038: (set (mem:QI (match_dup 1)) ! 2039: (match_operand:QI 0 "register_operand" ""))] ! 2040: "REGNO(operands[1]) != REGNO(operands[0])" ! 2041: "mov.b %X0,@-%T1" 1.1 root 2042: [(set_attr "length" "2") 2043: (set_attr "cc" "set")]) 2044: 1.1.1.2 ! root 2045: (define_peephole ! 2046: [(set (match_operand:HI 1 "register_operand" "") ! 2047: (plus:HI (match_dup 1) (const_int -1))) ! 2048: (set (mem:HI (match_dup 1)) ! 2049: (match_operand:HI 0 "register_operand" ""))] ! 2050: "REGNO(operands[1]) != REGNO(operands[0])" ! 2051: "mov.w %T0,@-%T1" ! 2052: [(set_attr "length" "2") 1.1 root 2053: (set_attr "cc" "set")]) 2054: 1.1.1.2 ! root 2055: ;(define_insn "" ! 2056: ; [(set (match_operand:HI 0 "register_operand" "=r") ! 2057: ; (MEM:HI (match_operand:HI 1 "register_operand" "r"))) ! 2058: ; (set (match_operand:HI 3 "register_operand" "=r") ! 2059: ; (zero_extract:HI (match_dup 0) ! 2060: ; (const_int 1) ! 2061: ; (match_operand:HI 2 "general_operand" "g"))) ! 2062: ; (set (MEM:HI (match_dup 1) (match_dup 3)))] ! 2063: ; "" ! 2064: ; "bld #0,%3l\;bst %Z2,%0%Y1" ! 2065: ; [(set_attr "type" "multi") ! 2066: ; (set_attr "length" "4") ! 2067: ; (set_attr "cc" "clobber")]) ! 2068: ! 2069: (define_insn "fancybset1" ! 2070: [(set (match_operand:QI 0 "bit_operand" "=Ur") ! 2071: (ior:QI (subreg:QI ! 2072: (ashift:HI (const_int 1) ! 2073: (subreg:QI (match_operand:HI 1 "register_operand" "ri") 0)) 0) ! 2074: (match_dup 0)))] ! 2075: "" ! 2076: "bset %X1,%X0") ! 2077: ! 2078: (define_insn "fancybset" ! 2079: [(set (match_operand:QI 0 "bit_operand" "=Ur") ! 2080: (ior:QI (subreg:QI ! 2081: (ashift:HI (const_int 1) ! 2082: (match_operand:HI 1 "nonmemory_operand" "ri") ) 0) ! 2083: (match_operand:QI 2 "general_operand" "Ur")))] ! 2084: "" ! 2085: "mov.b %X2,%X0\;bset %X1,%X0") ! 2086: ! 2087: ! 2088: (define_insn "fancybclr4" ! 2089: [(set (match_operand:QI 0 "general_operand" "=Ur,Ur") ! 2090: (and:QI ! 2091: (subreg:QI ! 2092: (rotate:HI (const_int -2) ! 2093: (match_operand:HI 2 "nonmemory_operand" "ri,ri") ) 0) ! 2094: (match_operand:QI 1 "general_operand" "0,Ur"))) ! 2095: (clobber (match_scratch:HI 3 "=X,&r"))] ! 2096: "" ! 2097: "@ ! 2098: bclr %X2,%X0; l1 ! 2099: mov.b %X1,%X3\;mov.b %3,%0\;bclr %X2,%X0; l3") ! 2100: ! 2101: (define_insn "fancybclr5" ! 2102: [(set (match_operand:QI 0 "general_operand" "=Ur,Ur") ! 2103: (and:QI ! 2104: (subreg:QI ! 2105: (rotate:HI (const_int -2) ! 2106: (match_operand:QI 2 "nonmemory_operand" "ri,ri")) 0) ! 2107: (match_operand:QI 1 "general_operand" "0,Ur"))) ! 2108: (clobber (match_scratch:HI 3 "=X,&r"))] ! 2109: "" ! 2110: "@ ! 2111: bclr %X2,%X0; l1 ! 2112: mov.b %X1,%X3\;mov.b %3,%0\;bclr %X2,%X0;l2") ! 2113: ! 2114: (define_insn "fancybclr2" ! 2115: [(set (match_operand:QI 0 "general_operand" "=U,r") ! 2116: (and:QI ! 2117: (subreg:QI ! 2118: (rotate:HI (const_int -2) ! 2119: (match_operand:HI 2 "nonmemory_operand" "ri,ri") ) 0) ! 2120: (match_operand:QI 1 "general_operand" "0,0")))] ! 2121: "" ! 2122: "bclr %X2,%X0") ! 2123: ! 2124: (define_insn "fancybclr3" ! 2125: [(set (match_operand:QI 0 "general_operand" "=U,r") ! 2126: (and:QI ! 2127: (subreg:QI ! 2128: (rotate:HI (const_int -2) ! 2129: (match_operand:QI 2 "nonmemory_operand" "ri,ri")) 0) ! 2130: (match_operand:QI 1 "general_operand" "0,0")))] ! 2131: "" ! 2132: "bclr %X2,%X0") ! 2133: ! 2134: (define_insn "fancybclr" ! 2135: [(set (match_operand:QI 0 "general_operand" "=r") ! 2136: (and:QI (not:QI (match_operand:QI 1 "general_operand" "0")) ! 2137: (match_operand:QI 2 "general_operand" "r")))] ! 2138: "" ! 2139: "not %X0\;and %X2,%X0") ! 2140: ! 2141: (define_insn "fancybsetp3" ! 2142: [(set (match_operand:QI 0 "bit_operand" "=Ur") ! 2143: (ior:QI (subreg:QI (ashift:HI (const_int 1) ! 2144: (match_operand:QI 1 "register_operand" "r")) 0) ! 2145: (match_operand:QI 2 "bit_operand" "0")))] ! 2146: "" ! 2147: "bset %X1,%X0") ! 2148: ! 2149: (define_insn "fancybsetp2" ! 2150: [(set (match_operand:QI 0 "general_operand" "=r,U") ! 2151: (ior:QI (subreg:QI (ashift:HI (const_int 1) ! 2152: (match_operand:QI 1 "register_operand" "r,r")) 0) ! 2153: (match_operand:QI 2 "general_operand" "U,r")))] ! 2154: "" ! 2155: "mov.b %X2,%X0\;bset %X1,%X0") ! 2156: ! 2157: (define_insn "fancybnot" ! 2158: [(set (match_operand:QI 0 "bit_operand" "=Ur") ! 2159: (xor:QI (subreg:QI (ashift:HI (const_int 1) ! 2160: (match_operand:QI 1 "register_operand" "r")) 0) ! 2161: (match_operand:QI 2 "bit_operand" "0")))] ! 2162: ! 2163: "" ! 2164: "bnot %X1,%X0") ! 2165: ! 2166: (define_insn "fancy_btst" ! 2167: [(set (pc) ! 2168: (if_then_else (eq (zero_extract:HI (zero_extend:HI (match_operand:QI 0 "general_operand" "Ur")) ! 2169: (const_int 1) ! 2170: (match_operand:HI 1 "nonmemory_operand" "rn")) ! 2171: (const_int 0)) ! 2172: (label_ref (match_operand 2 "" "")) ! 2173: (pc)))] ! 2174: "" ! 2175: "* ! 2176: { ! 2177: if (get_attr_length (insn) == 2) ! 2178: return \"btst %X1,%X0\;beq %l2\"; ! 2179: else if (get_attr_length (insn) == 4) ! 2180: return \"btst %X1,%X0\;beq %l2:16\"; ! 2181: else ! 2182: return \"btst %X1,%X0\;bne %L0\;jmp @%l2\;%L0:\"; ! 2183: }" ! 2184: [(set_attr "type" "branch") ! 2185: (set_attr "cc" "clobber")]) ! 2186: ! 2187: (define_insn "fancy_btst1" ! 2188: [(set (pc) ! 2189: (if_then_else (ne (zero_extract:HI (zero_extend:HI (match_operand:QI 0 "general_operand" "Ur")) ! 2190: (const_int 1) ! 2191: (match_operand:HI 1 "nonmemory_operand" "rn")) ! 2192: (const_int 0)) ! 2193: (label_ref (match_operand 2 "" "")) ! 2194: (pc)))] ! 2195: "" ! 2196: "* ! 2197: { ! 2198: if (get_attr_length (insn) == 2) ! 2199: return \"btst %X1,%X0\;bne %l2\"; ! 2200: else if (get_attr_length (insn) == 4) ! 2201: return \"btst %X1,%X0\;bne %l2:16\"; ! 2202: else ! 2203: return \"btst %X1,%X0\;beq %L0\;jmp @%l2\;%L0:\"; ! 2204: }" ! 2205: [(set_attr "type" "branch") ! 2206: (set_attr "cc" "clobber")]) ! 2207: ! 2208: (define_insn "pxor" ! 2209: [(set (zero_extract:QI (match_operand:QI 0 "bit_operand" "=r,U") ! 2210: (const_int 1) ! 2211: (match_operand 1 "immediate_operand" "n,n")) ! 2212: (and:QI (not:QI (match_operand:QI 2 "bit_operand" "r,U")) ! 2213: (const_int 1)))] ! 2214: "" ! 2215: "bld #0,%X2\;bist %1,%0" ! 2216: [(set_attr "type" "arith") ! 2217: (set_attr "length" "4") ! 2218: (set_attr "cc" "clobber")])
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