--- gcc/config/hp800.md 2018/04/24 17:51:30 1.1 +++ gcc/config/hp800.md 2018/04/24 17:53:43 1.1.1.2 @@ -406,7 +406,7 @@ [(set (match_operand:SI 0 "register_operand" "=r,r") (match_operator:CC 3 "comparison_operator" [(match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "arith_operand" "r,J")]))] + (match_operand:SI 2 "arith11_operand" "r,I")]))] "" "* { @@ -798,7 +798,7 @@ ;;; Experimental (define_insn "" - [(set (match_operand:SI 0 "fp_reg_operand" "fxy") + [(set (match_operand:SI 0 "fp_reg_operand" "*f*x*y") (match_operand:SI 1 "short_memory_operand" "T"))] "" "fldws%F1 %1,%0" @@ -807,7 +807,7 @@ (define_insn "" [(set (match_operand:SI 0 "short_memory_operand" "T") - (match_operand:SI 1 "fp_reg_operand" "fxy"))] + (match_operand:SI 1 "fp_reg_operand" "*f*x*y"))] "" "fstws%F0 %1,%0" [(set_attr "type" "fpstore") @@ -901,33 +901,45 @@ (define_expand "movstrsi" [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" "")) (mem:BLK (match_operand:BLK 1 "general_operand" ""))) - (use (match_operand:SI 2 "arith_operand" "")) - (use (match_operand:SI 3 "immediate_operand" "")) (clobber (match_dup 0)) (clobber (match_dup 1)) (clobber (match_scratch:SI 4 "")) - (clobber (reg:SI 0)) - (clobber (match_scratch:SI 5 ""))])] + (clobber (match_scratch:SI 5 "")) + (use (match_operand:SI 2 "arith_operand" "")) + (use (match_operand:SI 3 "const_int_operand" ""))])] "" " { + /* If the blocks are not word-aligned and rather big (>16 items), + or the size is indeterminate, don't inline the copy code. A + procedure call is better since it can check the alignment at + runtime and make the optimal decisions. */ + if (INTVAL (operands[3]) != 4 + && (GET_CODE (operands[2]) != CONST_INT + || (INTVAL (operands[2]) / INTVAL (operands[3]) > 16))) + FAIL; + operands[0] = copy_to_mode_reg (SImode, XEXP (operands[0], 0)); operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); operands[2] = force_not_mem (operands[2]); }") +;; The operand constraints are written like this to support both compile-time +;; and run-time determined byte count. If the count is run-time determined, +;; the register with the byte count is clobbered by the copying code, and +;; therefore it is forced to operand 2. If the count is compile-time +;; determined, we need two scratch registers for the unrolled code. (define_insn "" - [(set (mem:BLK (match_operand:SI 0 "register_operand" "r")) - (mem:BLK (match_operand:SI 1 "register_operand" "r"))) - (use (match_operand:SI 2 "arith_operand" "rn")) - (use (match_operand:SI 3 "immediate_operand" "i")) + [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r")) + (mem:BLK (match_operand:SI 1 "register_operand" "r,r"))) (clobber (match_dup 0)) (clobber (match_dup 1)) - (clobber (match_scratch:SI 4 "=&r")) - (clobber (reg:SI 0)) - (clobber (match_scratch:SI 5 "=&a"))] + (clobber (match_scratch:SI 2 "=r,r")) ;loop cnt/item tmp + (clobber (match_scratch:SI 3 "=r,r")) ;item tmp + (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count + (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment "" - "* return output_block_move (operands);" + "* return output_block_move (operands, !which_alternative);" [(set_attr "type" "multi")]) ;; Floating point move insns @@ -992,7 +1004,8 @@ (define_insn "" [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "=r,Q,&r,&r,*f*x*y,*f*x*y,*f*x*y,r,Q") - (match_operand:DI 1 "general_operand" "r,r,Q,i,r,*f*x*y,Q,*f*x*y,*f*x*y"))] + (match_operand:DI 1 "general_operand" + "r,r,Q,i,r,*f*x*y,Q,*f*x*y,*f*x*y"))] "" "* { @@ -1219,18 +1232,26 @@ ;; Truncation is performed as part of the conversion. (define_insn "fix_truncsfsi2" - [(set (match_operand:SI 0 "register_operand" "=fxy") - (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "fxy"))))] + [(set (match_operand:SI 0 "register_operand" "=r,fxy") + (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "fxy,fxy")))) + (clobber (match_scratch:SI 2 "=&fxy,X"))] "" - "fcnvfxt,sgl,sgl %1,%0" - [(set_attr "type" "fpalu")]) + "@ + fcnvfxt,sgl,sgl %1,%2\;fstws %2,-16(30)\;ldw -16(30),%0 + fcnvfxt,sgl,sgl %1,%0" + [(set_attr "type" "fpalu,fpalu") + (set_attr "length" "3,1")]) (define_insn "fix_truncdfsi2" - [(set (match_operand:SI 0 "register_operand" "=fxy") - (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "fxy"))))] + [(set (match_operand:SI 0 "register_operand" "=r,fxy") + (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "fxy,fxy")))) + (clobber (match_scratch:SI 2 "=&fxy,X"))] "" - "fcnvfxt,dbl,sgl %1,%0" - [(set_attr "type" "fpalu")]) + "@ + fcnvfxt,dbl,sgl %1,%2\;fstws %2,-16(30)\;ldw -16(30),%0 + fcnvfxt,dbl,sgl %1,%0" + [(set_attr "type" "fpalu,fpalu") + (set_attr "length" "3,1")]) ;;- arithmetic instructions @@ -1246,7 +1267,7 @@ (define_insn "addsi3" [(set (match_operand:SI 0 "register_operand" "=r,r") - (plus:SI (match_operand:SI 1 "arith_operand" "%r,r") + (plus:SI (match_operand:SI 1 "register_operand" "%r,r") (match_operand:SI 2 "arith_operand" "r,J")))] "" "@ @@ -1261,21 +1282,26 @@ "sub %R1,%R2,%R0\;subb %1,%2,%0" [(set_attr "length" "2")]) +;(define_insn "subsi3" +; [(set (match_operand:SI 0 "register_operand" "=r,r,r") +; (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,r") +; (match_operand:SI 2 "arith_operand" "r,r,J")))] +; "" +; "@ +; sub %1,%2,%0 +; subi %1,%2,%0 +; ldo %n2(%1),%0") + (define_insn "subsi3" [(set (match_operand:SI 0 "register_operand" "=r,r") - (minus:SI (match_operand:SI 1 "arith_operand" "r,r") - (match_operand:SI 2 "arith_operand" "r,J")))] + (minus:SI (match_operand:SI 1 "arith11_operand" "r,I") + (match_operand:SI 2 "register_operand" "r,r")))] "" "@ sub %1,%2,%0 - ldo %n2(%1),%0") + subi %1,%2,%0") -;; The mulsi3 insns set up registers for the millicode call. However, -;; if the multiplication involves constants, all that is -;; short-circuited. -;; -;; The algorithm used by output_mul_by_constant requires the source -;; and destination to be in different registers. +;; The mulsi3 insns set up registers for the millicode call. (define_expand "mulsi3" [(set (reg:SI 26) (match_operand:SI 1 "general_operand" "")) @@ -1287,38 +1313,7 @@ (clobber (reg:SI 31))]) (set (match_operand:SI 0 "register_operand" "") (reg:SI 29))] "" - " -{ - if (GET_CODE (operands[1]) == CONST_INT) - { - if (GET_CODE (operands[2]) == CONST_INT) - emit_move_insn (operands[0], - gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]) * INTVAL (operands[2]))); - else - { - rtx temp; - - if (GET_CODE (operands[2]) == REG) - temp = make_safe_from (operands[2], operands[0]); - else - temp = copy_to_reg (operands[2]); - operands[2] = operands[1]; - operands[1] = temp; - emit_mul_by_constant (operands, 0); - } - DONE; - } - else if (GET_CODE (operands[2]) == CONST_INT) - { - if (GET_CODE (operands[1]) == REG) - operands[1] = make_safe_from (operands[1], operands[0]); - else - operands[1] = copy_to_reg (operands[1]); - emit_mul_by_constant (operands, 0); - DONE; - } -}") + "") (define_insn "" [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25))) @@ -1340,8 +1335,7 @@ (clobber (reg:SI 26)) (clobber (reg:SI 25)) (clobber (reg:SI 31))]) - (set (match_operand:SI 0 "general_operand" "") (reg:SI 29)) - ] + (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))] "" " { @@ -1365,7 +1359,6 @@ DONE; }") - (define_insn "" [(set (reg:SI 29) (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" ""))) @@ -1386,8 +1379,7 @@ (clobber (reg:SI 26)) (clobber (reg:SI 25)) (clobber (reg:SI 31))]) - (set (match_operand:SI 0 "general_operand" "") (reg:SI 29)) - ] + (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))] "" " { @@ -1756,12 +1748,9 @@ "fsqrt,sgl %1,%0" [(set_attr "type" "fpsqrtsgl")]) -;;- arithmetic shift instructions - -;; A safe subtraction insn for values going into the shift register. +;;- Shift instructions ;; Optimized special case of shifting. -;; Must precede the general case. ? (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1772,25 +1761,25 @@ (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") - (plus:SI (match_operand:SI 1 "register_operand" "r") - (mult:SI (match_operand:SI 2 "register_operand" "r") - (const_int 2))))] + (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r") + (const_int 2)) + (match_operand:SI 1 "register_operand" "r")))] "" "sh1add %2,%1,%0") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") - (plus:SI (match_operand:SI 1 "register_operand" "r") - (mult:SI (match_operand:SI 2 "register_operand" "r") - (const_int 4))))] + (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r") + (const_int 4)) + (match_operand:SI 1 "register_operand" "r")))] "" "sh2add %2,%1,%0") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") - (plus:SI (match_operand:SI 1 "register_operand" "r") - (mult:SI (match_operand:SI 2 "register_operand" "r") - (const_int 8))))] + (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r") + (const_int 8)) + (match_operand:SI 1 "register_operand" "r")))] "" "sh3add %2,%1,%0")