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1.1 root 1: ;;- Machine description for HP PA-RISC architecture for GNU C compiler
2: ;; Copyright (C) 1992 Free Software Foundation, Inc.
3: ;; Contributed by the Center for Software Science at the University
4: ;; of Utah.
5:
6: ;; This file is part of GNU CC.
7:
8: ;; GNU CC is free software; you can redistribute it and/or modify
9: ;; it under the terms of the GNU General Public License as published by
10: ;; the Free Software Foundation; either version 2, or (at your option)
11: ;; any later version.
12:
13: ;; GNU CC is distributed in the hope that it will be useful,
14: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16: ;; GNU General Public License for more details.
17:
18: ;; You should have received a copy of the GNU General Public License
19: ;; along with GNU CC; see the file COPYING. If not, write to
20: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21:
22: ;; This gcc Version 2 machine description is inspired by sparc.md and
23: ;; mips.md.
24:
25: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
26:
27: ;; Insn type. Used to default other attribute values.
28:
29: ;; type "unary" insns have one input operand (1) and one output operand (0)
30: ;; type "binary" insns have two input operands (1,2) and one output (0)
31:
32: (define_attr "type"
33: "move,unary,binary,compare,load,store,branch,cbranch,call,dyncall,address,fpload,fpstore,fpalu,fpcc,fpmul,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,misc,milli"
34: (const_string "binary"))
35:
36: ;; Set true if insn uses call-clobbered intermediate register.
37: (define_attr "use_clobbered" "false,true"
38: (if_then_else (and (eq_attr "type" "address")
39: (match_operand 0 "clobbered_register" ""))
40: (const_string "true")
41: (const_string "false")))
42:
43: ;; Length (in # of insns).
44: (define_attr "length" ""
45: (cond [(eq_attr "type" "load,fpload")
46: (if_then_else (match_operand 1 "symbolic_memory_operand" "")
47: (const_int 2) (const_int 1))
48:
49: (eq_attr "type" "store,fpstore")
50: (if_then_else (match_operand 0 "symbolic_memory_operand" "")
51: (const_int 2) (const_int 1))
52:
53: (eq_attr "type" "address") (const_int 2)
54:
55: (eq_attr "type" "binary")
56: (if_then_else (match_operand 2 "arith_operand" "")
57: (const_int 1) (const_int 3))
58:
59: (eq_attr "type" "move,unary")
60: (if_then_else (match_operand 1 "arith_operand" "")
61: (const_int 1) (const_int 2))]
62:
63: (const_int 1)))
64:
65: (define_asm_attributes
66: [(set_attr "length" "1")
67: (set_attr "type" "multi")])
68:
69: ;; Attributes for instruction and branch scheduling
70:
71: (define_attr "in_call_delay" "false,true"
72: (cond [(eq_attr "type" "branch,cbranch,call,dyncall,multi,milli")
73: (const_string "false")
74:
75: (eq_attr "type" "load,fpload,store,fpstore")
76: (if_then_else (eq_attr "length" "1")
77: (const_string "true")
78: (const_string "false"))
79:
80: (eq_attr "type" "address")
81: (if_then_else (eq_attr "use_clobbered" "false")
82: (const_string "true")
83: (const_string "false"))]
84:
85: (if_then_else (eq_attr "length" "1")
86: (const_string "true")
87: (const_string "false"))))
88:
89: (define_attr "in_milli_delay" "false,true"
90: (cond [(eq_attr "length" "!1")
91: (const_string "false")
92:
93: (eq_attr "type" "branch,cbranch,call,dyncall,milli")
94: (const_string "false")
95:
96: (ne (symbol_ref "use_milli_regs (insn)") (const_int 0))
97: (const_string "false")]
98: (const_string "true")))
99:
100: (define_delay (eq_attr "type" "call")
101: [(eq_attr "in_call_delay" "true") (nil) (nil)])
102:
103: (define_attr "in_branch_delay" "false,true"
104: (if_then_else (and (eq_attr "type" "!branch,cbranch,call,multi,milli")
105: (eq_attr "length" "1"))
106: (const_string "true")
107: (const_string "false")))
108:
109: (define_delay (eq_attr "type" "branch")
110: [(eq_attr "in_branch_delay" "true")
111: (eq_attr "in_branch_delay" "true") (nil)])
112:
113: (define_delay (eq_attr "type" "cbranch")
114: [(eq_attr "in_branch_delay" "true") (nil) (nil)])
115:
116: (define_delay (eq_attr "type" "milli")
117: [(eq_attr "in_milli_delay" "true") (nil) (nil)])
118:
119: ;; Function units of the HPPA. The following data is for the "Snake"
120: ;; (Mustang CPU + Timex FPU) because that's what I have the docs for.
121: ;; Scheduling instructions for PA-83 machines according to the Snake
122: ;; constraints shouldn't hurt.
123:
124: ;; (define_function_unit {name} {num-units} {n-users} {test}
125: ;; {ready-delay} {busy-delay} [{conflict-list}])
126:
127: ;; The integer ALU.
128: ;; (Noted only for documentation; units that take one cycle do not need to
129: ;; be specified.)
130:
131: ;; (define_function_unit "alu" 1 0
132: ;; (eq_attr "type" "unary,binary,move,address") 1 0)
133:
134:
135: ;; Memory. Disregarding Cache misses, the Mustang memory times are:
136: ;; load: 1
137: ;; store, fpstore: 3, no D-cache operations should be scheduled.
138: ;; fpload: 3 (really 2 for flops, but I don't think we can specify that).
139:
140: (define_function_unit "memory" 1 1 (eq_attr "type" "load") 1 0)
141: (define_function_unit "memory" 1 1 (eq_attr "type" "store,fpstore") 3 0)
142: (define_function_unit "memory" 1 1 (eq_attr "type" "fpload") 3 0)
143:
144: ;; The Timex has two floating-point units: ALU, and MUL/DIV/SQRT unit.
145: ;; Timings:
146: ;; Instruction Time Unit Minimum Distance (unit contention)
147: ;; fcpy 3 ALU 2
148: ;; fabs 3 ALU 2
149: ;; fadd 3 ALU 2
150: ;; fsub 3 ALU 2
151: ;; fcmp 3 ALU 2
152: ;; fcnv 3 ALU 2
153: ;; fmpyadd 3 ALU,MPY 2
154: ;; fmpysub 3 ALU,MPY 2
155: ;; fmpycfxt 3 ALU,MPY 2
156: ;; fmpy 3 MPY 2
157: ;; fmpyi 3 MPY 2
158: ;; fdiv,sgl 10 MPY 10
159: ;; fdiv,dbl 12 MPY 12
160: ;; fsqrt,sgl 14 MPY 14
161: ;; fsqrt,dbl 18 MPY 18
162:
163: (define_function_unit "fp_alu" 1 0 (eq_attr "type" "fpalu") 3 2)
164: (define_function_unit "fp_mpy" 1 0 (eq_attr "type" "fpmul") 3 2)
165: (define_function_unit "fp_mpy" 1 0 (eq_attr "type" "fpdivsgl") 10 10)
166: (define_function_unit "fp_mpy" 1 0 (eq_attr "type" "fpdivdbl") 12 12)
167: (define_function_unit "fp_mpy" 1 0 (eq_attr "type" "fpsqrtsgl") 14 14)
168: (define_function_unit "fp_mpy" 1 0 (eq_attr "type" "fpsqrtdbl") 18 18)
169:
170: ;; Compare instructions.
171: ;; This controls RTL generation and register allocation.
172:
173: ;; We generate RTL for comparisons and branches by having the cmpxx
174: ;; patterns store away the operands. Then, the scc and bcc patterns
175: ;; emit RTL for both the compare and the branch.
176: ;;
177:
178: (define_expand "cmpsi"
179: [(set (reg:CC 0)
180: (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
181: (match_operand:SI 1 "arith5_operand" "")))]
182: ""
183: "
184: {
185: hppa_compare_op0 = operands[0];
186: hppa_compare_op1 = operands[1];
187: hppa_branch_type = CMP_SI;
188: DONE;
189: }")
190:
191: (define_expand "cmpsf"
192: [(set (reg:CCFP 0)
193: (compare:CCFP (match_operand:SF 0 "register_operand" "")
194: (match_operand:SF 1 "register_operand" "")))]
195: ""
196: "
197: {
198: hppa_compare_op0 = operands[0];
199: hppa_compare_op1 = operands[1];
200: hppa_branch_type = CMP_SF;
201: DONE;
202: }")
203:
204: (define_expand "cmpdf"
205: [(set (reg:CCFP 0)
206: (compare:CCFP (match_operand:DF 0 "register_operand" "")
207: (match_operand:DF 1 "register_operand" "")))]
208: ""
209: "
210: {
211: hppa_compare_op0 = operands[0];
212: hppa_compare_op1 = operands[1];
213: hppa_branch_type = CMP_DF;
214: DONE;
215: }")
216:
217: (define_insn ""
218: [(set (reg:CCFP 0)
219: (match_operator:CCFP 2 "comparison_operator"
220: [(match_operand:SF 0 "register_operand" "fxy")
221: (match_operand:SF 1 "register_operand" "fxy")]))]
222: ""
223: "fcmp,sgl,%Y2 %0,%1"
224: [(set_attr "type" "fpcc")])
225:
226: (define_insn ""
227: [(set (reg:CCFP 0)
228: (match_operator:CCFP 2 "comparison_operator"
229: [(match_operand:DF 0 "register_operand" "fxy")
230: (match_operand:DF 1 "register_operand" "fxy")]))]
231: ""
232: "fcmp,dbl,%Y2 %0,%1"
233: [(set_attr "type" "fpcc")])
234:
235: ;; scc insns.
236:
237: (define_insn ""
238: [(set (match_operand:SI 0 "register_operand" "=r")
239: (match_operator:CCFP 1 "comparison_operator" [(reg:CCFP 0)
240: (const_int 0)]))]
241: ""
242: "copy 0,%0\;ftest\;ldi 1,%0"
243: [(set_attr "type" "unary")
244: (set_attr "length" "3")])
245:
246: (define_expand "seq"
247: [(set (match_operand:SI 0 "register_operand" "")
248: (eq:CC (match_dup 1)
249: (match_dup 2)))]
250: ""
251: "
252: {
253: if (hppa_branch_type != CMP_SI)
254: {
255: emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
256: emit_insn (gen_scond_fp (EQ, operands[0]));
257: DONE;
258: }
259: /* set up operands from compare. */
260: operands[1] = hppa_compare_op0;
261: operands[2] = hppa_compare_op1;
262: /* fall through and generate default code */
263: }")
264:
265: (define_expand "sne"
266: [(set (match_operand:SI 0 "register_operand" "=r")
267: (ne:CC (match_dup 1)
268: (match_dup 2)))]
269: ""
270: "
271: {
272: if (hppa_branch_type != CMP_SI)
273: {
274: emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
275: emit_insn (gen_scond_fp (NE, operands[0]));
276: DONE;
277: }
278: operands[1] = hppa_compare_op0;
279: operands[2] = hppa_compare_op1;
280: }")
281:
282: (define_expand "slt"
283: [(set (match_operand:SI 0 "register_operand" "=r")
284: (lt:CC (match_dup 1)
285: (match_dup 2)))]
286: ""
287: "
288: {
289: if (hppa_branch_type != CMP_SI)
290: {
291: emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
292: emit_insn (gen_scond_fp (LT, operands[0]));
293: DONE;
294: }
295: operands[1] = hppa_compare_op0;
296: operands[2] = hppa_compare_op1;
297: }")
298:
299: (define_expand "sgt"
300: [(set (match_operand:SI 0 "register_operand" "=r")
301: (gt:CC (match_dup 1)
302: (match_dup 2)))]
303: ""
304: "
305: {
306: if (hppa_branch_type != CMP_SI)
307: {
308: emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
309: emit_insn (gen_scond_fp (GT, operands[0]));
310: DONE;
311: }
312: operands[1] = hppa_compare_op0;
313: operands[2] = hppa_compare_op1;
314: }")
315:
316: (define_expand "sle"
317: [(set (match_operand:SI 0 "register_operand" "=r")
318: (le:CC (match_dup 1)
319: (match_dup 2)))]
320: ""
321: "
322: {
323: if (hppa_branch_type != CMP_SI)
324: {
325: emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
326: emit_insn (gen_scond_fp (LE, operands[0]));
327: DONE;
328: }
329: operands[1] = hppa_compare_op0;
330: operands[2] = hppa_compare_op1;
331: }")
332:
333: (define_expand "sge"
334: [(set (match_operand:SI 0 "register_operand" "=r")
335: (ge:CC (match_dup 1)
336: (match_dup 2)))]
337: ""
338: "
339: {
340: if (hppa_branch_type != CMP_SI)
341: {
342: emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
343: emit_insn (gen_scond_fp (GE, operands[0]));
344: DONE;
345: }
346: operands[1] = hppa_compare_op0;
347: operands[2] = hppa_compare_op1;
348: }")
349:
350: (define_expand "sltu"
351: [(set (match_operand:SI 0 "register_operand" "=r")
352: (ltu:CC (match_dup 1)
353: (match_dup 2)))]
354: ""
355: "
356: {
357: if (hppa_branch_type != CMP_SI)
358: FAIL;
359: operands[1] = hppa_compare_op0;
360: operands[2] = hppa_compare_op1;
361: }")
362:
363: (define_expand "sgtu"
364: [(set (match_operand:SI 0 "register_operand" "=r")
365: (gtu:CC (match_dup 1)
366: (match_dup 2)))]
367: ""
368: "
369: {
370: if (hppa_branch_type != CMP_SI)
371: FAIL;
372: operands[1] = hppa_compare_op0;
373: operands[2] = hppa_compare_op1;
374: }")
375:
376: (define_expand "sleu"
377: [(set (match_operand:SI 0 "register_operand" "=r")
378: (leu:CC (match_dup 1)
379: (match_dup 2)))]
380: ""
381: "
382: {
383: if (hppa_branch_type != CMP_SI)
384: FAIL;
385: operands[1] = hppa_compare_op0;
386: operands[2] = hppa_compare_op1;
387: }")
388:
389: (define_expand "sgeu"
390: [(set (match_operand:SI 0 "register_operand" "=r")
391: (geu:CC (match_dup 1)
392: (match_dup 2)))]
393: ""
394: "
395: {
396: if (hppa_branch_type != CMP_SI)
397: FAIL;
398: operands[1] = hppa_compare_op0;
399: operands[2] = hppa_compare_op1;
400: }")
401:
402: ;; Instruction canonicalization puts immediate operands second, which
403: ;; is the reverse of what we want.
404:
405: (define_insn ""
406: [(set (match_operand:SI 0 "register_operand" "=r,r")
407: (match_operator:CC 3 "comparison_operator"
408: [(match_operand:SI 1 "register_operand" "r,r")
409: (match_operand:SI 2 "arith_operand" "r,J")]))]
410: ""
411: "*
412: {
413: if (which_alternative == 0)
414: return \"comclr,%N3 %1,%2,%0\;ldi 1,%0\";
415: else
416: {
417: if (!(GET_CODE (operands[3]) == EQ || GET_CODE (operands[3]) == NE))
418: PUT_CODE (operands[3], reverse_relop (GET_CODE (operands[3])));
419: output_asm_insn (\"comiclr,%N3 %2,%1,%0\;ldi 1,%0\", operands);
420: return \"\";
421: }
422: }"
423: [(set_attr "type" "binary")
424: (set_attr "length" "2")])
425:
426: ;; Conditionals
427:
428: (define_expand "beq"
429: [(set (pc)
430: (if_then_else (eq (match_dup 1) (match_dup 2))
431: (label_ref (match_operand 0 "" ""))
432: (pc)))]
433: ""
434: "
435: {
436: if (hppa_branch_type != CMP_SI)
437: {
438: emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
439: emit_bcond_fp (NE, operands[0]);
440: DONE;
441: }
442: /* set up operands from compare. */
443: operands[1] = hppa_compare_op0;
444: operands[2] = hppa_compare_op1;
445: /* fall through and generate default code */
446: }")
447:
448: (define_expand "bne"
449: [(set (pc)
450: (if_then_else (ne (match_dup 1) (match_dup 2))
451: (label_ref (match_operand 0 "" ""))
452: (pc)))]
453: ""
454: "
455: {
456: if (hppa_branch_type != CMP_SI)
457: {
458: emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
459: emit_bcond_fp (NE, operands[0]);
460: DONE;
461: }
462: operands[1] = hppa_compare_op0;
463: operands[2] = hppa_compare_op1;
464: }")
465:
466: (define_expand "bgt"
467: [(set (pc)
468: (if_then_else (gt (match_dup 1) (match_dup 2))
469: (label_ref (match_operand 0 "" ""))
470: (pc)))]
471: ""
472: "
473: {
474: if (hppa_branch_type != CMP_SI)
475: {
476: emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
477: emit_bcond_fp (NE, operands[0]);
478: DONE;
479: }
480: operands[1] = hppa_compare_op0;
481: operands[2] = hppa_compare_op1;
482: }")
483:
484: (define_expand "blt"
485: [(set (pc)
486: (if_then_else (lt (match_dup 1) (match_dup 2))
487: (label_ref (match_operand 0 "" ""))
488: (pc)))]
489: ""
490: "
491: {
492: if (hppa_branch_type != CMP_SI)
493: {
494: emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
495: emit_bcond_fp (NE, operands[0]);
496: DONE;
497: }
498: operands[1] = hppa_compare_op0;
499: operands[2] = hppa_compare_op1;
500: }")
501:
502: (define_expand "bge"
503: [(set (pc)
504: (if_then_else (ge (match_dup 1) (match_dup 2))
505: (label_ref (match_operand 0 "" ""))
506: (pc)))]
507: ""
508: "
509: {
510: if (hppa_branch_type != CMP_SI)
511: {
512: emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
513: emit_bcond_fp (NE, operands[0]);
514: DONE;
515: }
516: operands[1] = hppa_compare_op0;
517: operands[2] = hppa_compare_op1;
518: }")
519:
520: (define_expand "ble"
521: [(set (pc)
522: (if_then_else (le (match_dup 1) (match_dup 2))
523: (label_ref (match_operand 0 "" ""))
524: (pc)))]
525: ""
526: "
527: {
528: if (hppa_branch_type != CMP_SI)
529: {
530: emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
531: emit_bcond_fp (NE, operands[0]);
532: DONE;
533: }
534: operands[1] = hppa_compare_op0;
535: operands[2] = hppa_compare_op1;
536: }")
537:
538: (define_expand "bgtu"
539: [(set (pc)
540: (if_then_else (gtu (match_dup 1) (match_dup 2))
541: (label_ref (match_operand 0 "" ""))
542: (pc)))]
543: ""
544: "
545: {
546: if (hppa_branch_type != CMP_SI)
547: FAIL;
548: operands[1] = hppa_compare_op0;
549: operands[2] = hppa_compare_op1;
550: }")
551:
552: (define_expand "bltu"
553: [(set (pc)
554: (if_then_else (ltu (match_dup 1) (match_dup 2))
555: (label_ref (match_operand 0 "" ""))
556: (pc)))]
557: ""
558: "
559: {
560: if (hppa_branch_type != CMP_SI)
561: FAIL;
562: operands[1] = hppa_compare_op0;
563: operands[2] = hppa_compare_op1;
564: }")
565:
566: (define_expand "bgeu"
567: [(set (pc)
568: (if_then_else (geu (match_dup 1) (match_dup 2))
569: (label_ref (match_operand 0 "" ""))
570: (pc)))]
571: ""
572: "
573: {
574: if (hppa_branch_type != CMP_SI)
575: FAIL;
576: operands[1] = hppa_compare_op0;
577: operands[2] = hppa_compare_op1;
578: }")
579:
580: (define_expand "bleu"
581: [(set (pc)
582: (if_then_else (leu (match_dup 1) (match_dup 2))
583: (label_ref (match_operand 0 "" ""))
584: (pc)))]
585: ""
586: "
587: {
588: if (hppa_branch_type != CMP_SI)
589: FAIL;
590: operands[1] = hppa_compare_op0;
591: operands[2] = hppa_compare_op1;
592: }")
593:
594: ;; Match the branch patterns.
595:
596: (define_insn ""
597: [(set (pc)
598: (if_then_else
599: (match_operator 3 "comparison_operator"
600: [(match_operand:SI 1 "register_operand" "r,r")
601: (match_operand:SI 2 "arith5_operand" "r,L")])
602: (label_ref (match_operand 0 "" ""))
603: (pc)))]
604: ""
605: "*
606: {
607: if (which_alternative == 0)
608: return (get_attr_length (insn) == 1
609: ? \"comb,%C3 %1,%2,%0%#\" : \"comclr,%N3 %1,%2,0\;bl %0,0%#\");
610: {
611: enum rtx_code comp_code = GET_CODE (operands[3]);
612: if (!(comp_code == EQ || comp_code == NE))
613: PUT_CODE (operands[3], reverse_relop (comp_code));
614: if (get_attr_length (insn) == 1)
615: output_asm_insn (\"comib,%C3 %2,%1,%0%#\", operands);
616: else
617: output_asm_insn (\"comiclr,%N3 %2,%1,0\;bl %0,0%#\", operands);
618: return \"\";
619: }
620: }"
621: [(set_attr "type" "cbranch")
622: (set (attr "length") (if_then_else (lt (abs (minus (match_dup 0)
623: (plus (pc) (const_int 2))))
624: (const_int 1023))
625: (const_int 1)
626: (const_int 2)))])
627:
628: ;; Match the negated branch.
629:
630: (define_insn ""
631: [(set (pc)
632: (if_then_else
633: (match_operator 3 "comparison_operator"
634: [(match_operand:SI 1 "register_operand" "r,r")
635: (match_operand:SI 2 "arith5_operand" "r,L")])
636: (pc)
637: (label_ref (match_operand 0 "" ""))))]
638: ""
639: "*
640: {
641: if (which_alternative == 0)
642: return (get_attr_length (insn) == 1
643: ? \"comb,%N3 %1,%2,%0%#\" : \"comclr,%C3 %1,%2,0\;bl %0,0%#\");
644: {
645: enum rtx_code comp_code = GET_CODE (operands[3]);
646: if (!(comp_code == EQ || comp_code == NE))
647: PUT_CODE (operands[3], reverse_relop (comp_code));
648: if (get_attr_length (insn) == 1)
649: output_asm_insn (\"comib,%N3 %2,%1,%0%#\", operands);
650: else
651: output_asm_insn (\"comiclr,%C3 %2,%1,0%#\;bl %0,0%#\", operands);
652: return \"\";
653: }
654: }"
655: [(set_attr "type" "cbranch")
656: (set (attr "length") (if_then_else (lt (abs (minus (match_dup 0)
657: (plus (pc) (const_int 2))))
658: (const_int 1023))
659: (const_int 1)
660: (const_int 2)))])
661:
662: ;; Floating point branches
663:
664: (define_insn ""
665: [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
666: (label_ref (match_operand 0 "" ""))
667: (pc)))]
668: ""
669: "ftest\;bl%* %0,0"
670: [(set_attr "type" "cbranch")
671: (set_attr "length" "2")])
672:
673: (define_insn ""
674: [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
675: (pc)
676: (label_ref (match_operand 0 "" ""))))]
677: ""
678: "ftest\;add,tr 0,0,0\;bl%* %0,0"
679: [(set_attr "type" "cbranch")
680: (set_attr "length" "3")])
681:
682: ;; Move instructions
683:
684: (define_expand "movsi"
685: [(set (match_operand:SI 0 "general_operand" "")
686: (match_operand:SI 1 "general_operand" ""))]
687: ""
688: "
689: {
690: if (emit_move_sequence (operands, SImode))
691: DONE;
692: }")
693:
694: ;; Moves to and from the shift register.
695:
696: (define_insn ""
697: [(set (reg:SI 112)
698: (match_operand:SI 0 "register_operand" "r"))]
699: ""
700: "mtsar %0"
701: [(set_attr "type" "move")])
702:
703: (define_insn ""
704: [(set (match_operand:SI 0 "register_operand" "=r")
705: (reg:SI 112))]
706: ""
707: "mfctl 11,%0"
708: [(set_attr "type" "move")])
709:
710: (define_insn ""
711: [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand" "=r,r,Q,!r,!*f*x*y,!*f")
712: (match_operand:SI 1 "move_operand" "rM,Q,rM,!*f*x*y,!r,!*f"))]
713: ""
714: "@
715: copy %r1,%0
716: ldw%M1 %1,%0
717: stw%M0 %r1,%0
718: fstws %1,-16(30)\;ldw -16(30),%0
719: stw %1,-16(30)\;fldws -16(30),%0
720: fcpy,sgl %1,%0"
721: [(set_attr "type" "move,load,store,move,move,fpalu")
722: (set_attr "length" "1,1,1,2,2,1")])
723:
724: ;; For pic
725: (define_insn ""
726: [(set (match_operand:SI 0 "register_operand" "=r")
727: (match_operand:SI 1 "pic_operand" "i"))
728: (clobber (match_scratch:SI 2 "=a"))]
729: ""
730: "*
731: {
732: rtx label_rtx = gen_label_rtx ();
733: rtx xoperands[3];
734: extern FILE *asm_out_file;
735:
736: xoperands[0] = operands[0];
737: xoperands[1] = operands[1];
738: xoperands[2] = label_rtx;
739: output_asm_insn (\"bl .+8,%0\;addil L'%1-%2,%0\", xoperands);
740: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", CODE_LABEL_NUMBER (label_rtx));
741: output_asm_insn (\"ldo R'%1(1),%0\", xoperands);
742: return \"\";
743: }
744: "
745: [(set_attr "type" "multi")
746: (set_attr "length" "3")])
747:
748: (define_insn ""
749: [(set (match_operand:SI 0 "register_operand" "=r")
750: (match_operand:SI 1 "immediate_operand" "n"))]
751: "(GET_CODE (operands[1]) == CONST_INT) &&
752: (INT_14_BITS (operands[1]) || !(INTVAL (operands[1]) & 0x7ff))"
753: "*
754: {
755: if (INT_14_BITS (operands[1]))
756: return \"ldo %1(0),%0\";
757: else
758: return \"ldil L'%1,%0\";
759: }"
760: [(set_attr "type" "move")
761: (set_attr "length" "1")])
762:
763: (define_insn ""
764: [(set (match_operand:SI 0 "register_operand" "=a")
765: (plus:SI (match_operand:SI 1 "register_operand" "r")
766: (high:SI (match_operand 2 "" ""))))]
767: ""
768: "addil L'%G2,%1"
769: [(set_attr "type" "binary")
770: (set_attr "length" "1")])
771:
772: (define_insn ""
773: [(set (match_operand:SI 0 "register_operand" "=r")
774: (high:SI (match_operand 1 "" "")))]
775: "check_pic (1)"
776: "ldil L'%G1,%0"
777: [(set_attr "type" "move")
778: (set_attr "length" "1")])
779:
780: (define_insn ""
781: [(set (match_operand:HI 0 "register_operand" "=r")
782: (high:HI (match_operand 1 "" "")))]
783: "check_pic (1)"
784: "ldil L'%G1,%0"
785: [(set_attr "type" "move")
786: (set_attr "length" "1")])
787:
788: (define_insn ""
789: [(set (match_operand:SI 0 "register_operand" "=r")
790: (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
791: (match_operand:SI 2 "immediate_operand" "in")))]
792: ""
793: "ldo R'%G2(%1),%0"
794: ;; Need to set length for this arith insn because operand2
795: ;; is not an "arith_operand".
796: [(set_attr "length" "1")])
797:
798: ;;; Experimental
799:
800: (define_insn ""
801: [(set (match_operand:SI 0 "fp_reg_operand" "fxy")
802: (match_operand:SI 1 "short_memory_operand" "T"))]
803: ""
804: "fldws%F1 %1,%0"
805: [(set_attr "type" "fpload")
806: (set_attr "length" "1")])
807:
808: (define_insn ""
809: [(set (match_operand:SI 0 "short_memory_operand" "T")
810: (match_operand:SI 1 "fp_reg_operand" "fxy"))]
811: ""
812: "fstws%F0 %1,%0"
813: [(set_attr "type" "fpstore")
814: (set_attr "length" "1")])
815:
816: (define_expand "movhi"
817: [(set (match_operand:HI 0 "general_operand" "")
818: (match_operand:HI 1 "general_operand" ""))]
819: ""
820: "
821: {
822: if (emit_move_sequence (operands, HImode))
823: DONE;
824: }")
825:
826: (define_insn ""
827: [(set (match_operand:HI 0 "reg_or_nonsymb_mem_operand" "=r,r,Q")
828: (match_operand:HI 1 "move_operand" "rM,Q,rM"))]
829: ""
830: "@
831: copy %r1,%0
832: ldh%M1 %1,%0
833: sth%M0 %r1,%0"
834: [(set_attr "type" "move,load,store")
835: (set_attr "length" "1,1,1")])
836:
837: (define_insn ""
838: [(set (match_operand:HI 0 "register_operand" "=r")
839: (match_operand:HI 1 "immediate_operand" "n"))]
840: "(GET_CODE (operands[1]) == CONST_INT) &&
841: (INT_14_BITS (operands[1]) || !(INTVAL (operands[1]) & 0x7ff))"
842: "*
843: {
844: if (INT_14_BITS (operands[1]))
845: return \"ldo %1(0),%0\";
846: else
847: return \"ldil L'%1,%0\";
848: }"
849: [(set_attr "type" "move")
850: (set_attr "length" "1")])
851:
852: (define_insn ""
853: [(set (match_operand:HI 0 "register_operand" "=r")
854: (lo_sum:HI (match_operand:HI 1 "register_operand" "r")
855: (match_operand 2 "immediate_operand" "in")))]
856: ""
857: "ldo R'%G2(%1),%0"
858: [(set_attr "length" "1")])
859:
860: (define_expand "movqi"
861: [(set (match_operand:QI 0 "general_operand" "")
862: (match_operand:QI 1 "general_operand" ""))]
863: ""
864: "
865: {
866: if (emit_move_sequence (operands, QImode))
867: DONE;
868: }")
869:
870: (define_insn ""
871: [(set (match_operand:QI 0 "reg_or_nonsymb_mem_operand" "=r,r,Q")
872: (match_operand:QI 1 "move_operand" "rM,Q,rM"))]
873: ""
874: "@
875: copy %r1,%0
876: ldb%M1 %1,%0
877: stb%M0 %r1,%0"
878: [(set_attr "type" "move,load,store")
879: (set_attr "length" "1,1,1")])
880:
881: (define_insn ""
882: [(set (match_operand:QI 0 "register_operand" "=r")
883: (match_operand:QI 1 "immediate_operand" "J"))]
884: ""
885: "ldo %1(0),%0"
886: [(set_attr "type" "move")
887: (set_attr "length" "1")])
888:
889: (define_insn ""
890: [(set (match_operand:QI 0 "register_operand" "=r")
891: (subreg:QI (lo_sum:SI (match_operand:QI 1 "register_operand" "r")
892: (match_operand 2 "immediate_operand" "in")) 0))]
893: ""
894: "ldo R'%G2(%1),%0"
895: [(set_attr "length" "1")])
896:
897: ;; The definition of this insn does not really explain what it does,
898: ;; but it should suffice
899: ;; that anything generated as this insn will be recognized as one
900: ;; and that it will not successfully combine with anything.
901: (define_expand "movstrsi"
902: [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" ""))
903: (mem:BLK (match_operand:BLK 1 "general_operand" "")))
904: (use (match_operand:SI 2 "arith_operand" ""))
905: (use (match_operand:SI 3 "immediate_operand" ""))
906: (clobber (match_dup 0))
907: (clobber (match_dup 1))
908: (clobber (match_scratch:SI 4 ""))
909: (clobber (reg:SI 0))
910: (clobber (match_scratch:SI 5 ""))])]
911: ""
912: "
913: {
914: operands[0] = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
915: operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
916: operands[2] = force_not_mem (operands[2]);
917: }")
918:
919: (define_insn ""
920: [(set (mem:BLK (match_operand:SI 0 "register_operand" "r"))
921: (mem:BLK (match_operand:SI 1 "register_operand" "r")))
922: (use (match_operand:SI 2 "arith_operand" "rn"))
923: (use (match_operand:SI 3 "immediate_operand" "i"))
924: (clobber (match_dup 0))
925: (clobber (match_dup 1))
926: (clobber (match_scratch:SI 4 "=&r"))
927: (clobber (reg:SI 0))
928: (clobber (match_scratch:SI 5 "=&a"))]
929: ""
930: "* return output_block_move (operands);"
931: [(set_attr "type" "multi")])
932:
933: ;; Floating point move insns
934:
935: ;; This pattern forces (set (reg:DF ...) (const_double ...))
936: ;; to be reloaded by putting the constant into memory.
937: ;; It must come before the more general movdf pattern.
938: (define_insn ""
939: [(set (match_operand:DF 0 "general_operand" "=?r,r,f")
940: (match_operand:DF 1 "" "?E,G,m"))]
941: "GET_CODE (operands[1]) == CONST_DOUBLE"
942: "*
943: {
944: switch (which_alternative)
945: {
946: case 0:
947: return output_move_double (operands);
948: case 1:
949: return \"copy 0,%0\;copy 0,%R0\";
950: case 2:
951: return output_fp_move_double (operands);
952: }
953: }"
954: [(set_attr "type" "load,move,fpload")
955: (set_attr "length" "3,2,3")])
956:
957: (define_expand "movdf"
958: [(set (match_operand:DF 0 "general_operand" "")
959: (match_operand:DF 1 "general_operand" ""))]
960: ""
961: "
962: {
963: if (emit_move_sequence (operands, DFmode))
964: DONE;
965: }")
966:
967: (define_insn ""
968: [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
969: "=fxy,r,Q,Q,fxy,&r,?fxy,?r")
970: (match_operand:DF 1 "reg_or_nonsymb_mem_operand"
971: "fxy,r,fxy,r,Q,Q,r,fxy"))]
972: ""
973: "*
974: {
975: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
976: return output_fp_move_double (operands);
977: return output_move_double (operands);
978: }"
979: [(set_attr "type" "fpalu,move,fpstore,store,fpload,load,multi,multi")
980: (set_attr "length" "1,2,1,2,1,2,3,3")])
981:
982: (define_expand "movdi"
983: [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
984: (match_operand:DI 1 "general_operand" ""))]
985: ""
986: "
987: {
988: if (emit_move_sequence (operands, DImode))
989: DONE;
990: }")
991:
992: (define_insn ""
993: [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
994: "=r,Q,&r,&r,*f*x*y,*f*x*y,*f*x*y,r,Q")
995: (match_operand:DI 1 "general_operand" "r,r,Q,i,r,*f*x*y,Q,*f*x*y,*f*x*y"))]
996: ""
997: "*
998: {
999: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
1000: return output_fp_move_double (operands);
1001: return output_move_double (operands);
1002: }"
1003: [(set_attr "type" "move,store,load,misc,multi,fpalu,fpload,multi,fpstore")
1004: (set_attr "length" "2,3,3,3,3,2,3,3,3")])
1005:
1006: (define_expand "movsf"
1007: [(set (match_operand:SF 0 "general_operand" "")
1008: (match_operand:SF 1 "general_operand" ""))]
1009: ""
1010: "
1011: {
1012: if (emit_move_sequence (operands, SFmode))
1013: DONE;
1014: }")
1015:
1016: (define_insn ""
1017: [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand"
1018: "=fxy,r,r,fxy,fxy,r,Q,Q")
1019: (match_operand:SF 1 "reg_or_nonsymb_mem_operand"
1020: "fxy,r,!fxy,!r,Q,Q,fxy,r"))]
1021: ""
1022: "@
1023: fcpy %1,%0
1024: copy %1,%0
1025: fstws %1,-16(0,30)\;ldw -16(0,30),%0
1026: stw %r1,-16(0,30)\;fldws -16(0,30),%0
1027: fldws%F1 %1,%0
1028: ldw%M1 %1,%0
1029: fstws%F0 %r1,%0
1030: stw%M0 %r1,%0"
1031: [(set_attr "type" "fpalu,move,multi,multi,fpload,load,fpstore,store")
1032: (set_attr "length" "1,1,2,2,1,1,1,1")])
1033:
1034:
1035: ;;- zero extension instructions
1036:
1037: ;; Note that the one starting from HImode comes before those for QImode
1038: ;; so that a constant operand will match HImode, not QImode.
1039:
1040: (define_expand "zero_extendhisi2"
1041: [(set (match_operand:SI 0 "register_operand" "")
1042: (zero_extend:SI
1043: (match_operand:HI 1 "general_operand" "")))]
1044: ""
1045: "
1046: {
1047: if (GET_CODE (operand1) == MEM
1048: && symbolic_operand (XEXP (operand1, 0), Pmode))
1049: {
1050: rtx temp = copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode,
1051: XEXP (operand1, 0)));
1052: operands[1] = gen_rtx (MEM, HImode,
1053: gen_rtx (LO_SUM, Pmode,
1054: temp, XEXP (operand1, 0)));
1055: }
1056: }")
1057:
1058: (define_insn ""
1059: [(set (match_operand:SI 0 "register_operand" "=r,r")
1060: (zero_extend:SI
1061: (match_operand:HI 1 "reg_or_nonsymb_mem_operand" "r,Q")))]
1062: ""
1063: "@
1064: extru %1,31,16,%0
1065: ldh%M1 %1,%0"
1066: [(set_attr "type" "unary,load")])
1067:
1068: (define_expand "zero_extendqihi2"
1069: [(set (match_operand:HI 0 "register_operand" "")
1070: (zero_extend:HI
1071: (match_operand:QI 1 "general_operand" "")))]
1072: ""
1073: "
1074: {
1075: if (GET_CODE (operand1) == MEM
1076: && symbolic_operand (XEXP (operand1, 0), Pmode))
1077: {
1078: rtx temp = copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode,
1079: XEXP (operand1, 0)));
1080: operands[1] = gen_rtx (MEM, QImode,
1081: gen_rtx (LO_SUM, Pmode,
1082: temp, XEXP (operand1, 0)));
1083: }
1084: }")
1085:
1086: (define_insn ""
1087: [(set (match_operand:HI 0 "register_operand" "=r,r")
1088: (zero_extend:HI
1089: (match_operand:QI 1 "reg_or_nonsymb_mem_operand" "r,Q")))]
1090: ""
1091: "@
1092: extru %1,31,8,%0
1093: ldb%M1 %1,%0"
1094: [(set_attr "type" "unary,load")
1095: (set_attr "length" "1")])
1096:
1097: (define_expand "zero_extendqisi2"
1098: [(set (match_operand:SI 0 "register_operand" "")
1099: (zero_extend:SI
1100: (match_operand:QI 1 "general_operand" "")))]
1101: ""
1102: "
1103: {
1104: if (GET_CODE (operand1) == MEM
1105: && symbolic_operand (XEXP (operand1, 0), Pmode))
1106: {
1107: rtx temp = copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode,
1108: XEXP (operand1, 0)));
1109: operand1 = gen_rtx (MEM, QImode,
1110: gen_rtx (LO_SUM, Pmode,
1111: temp, XEXP (operand1, 0)));
1112: emit_insn (gen_rtx (SET, VOIDmode, operand0,
1113: gen_rtx (ZERO_EXTEND, SImode, operand1)));
1114: DONE;
1115: }
1116: }")
1117:
1118: (define_insn ""
1119: [(set (match_operand:SI 0 "register_operand" "=r,r")
1120: (zero_extend:SI
1121: (match_operand:QI 1 "reg_or_nonsymb_mem_operand" "r,Q")))]
1122: ""
1123: "@
1124: extru %1,31,8,%0
1125: ldb%M1 %1,%0"
1126: [(set_attr "type" "unary,load")
1127: (set_attr "length" "1")])
1128:
1129: ;;- sign extension instructions
1130: ;; Note that the one starting from HImode comes before those for QImode
1131: ;; so that a constant operand will match HImode, not QImode.
1132:
1133: (define_insn "extendhisi2"
1134: [(set (match_operand:SI 0 "register_operand" "=r")
1135: (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1136: ""
1137: "extrs %1,31,16,%0"
1138: [(set_attr "type" "unary")])
1139:
1140: (define_insn "extendqihi2"
1141: [(set (match_operand:HI 0 "register_operand" "=r")
1142: (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1143: ""
1144: "extrs %1,31,8,%0"
1145: [(set_attr "type" "unary")])
1146:
1147: (define_insn "extendqisi2"
1148: [(set (match_operand:SI 0 "register_operand" "=r")
1149: (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1150: ""
1151: "extrs %1,31,8,%0"
1152: [(set_attr "type" "unary")])
1153:
1154: ;; Conversions between float and double.
1155:
1156: (define_insn "extendsfdf2"
1157: [(set (match_operand:DF 0 "register_operand" "=fxy")
1158: (float_extend:DF
1159: (match_operand:SF 1 "register_operand" "fxy")))]
1160: ""
1161: "fcnvff,sgl,dbl %1,%0"
1162: [(set_attr "type" "fpalu")])
1163:
1164: (define_insn "truncdfsf2"
1165: [(set (match_operand:SF 0 "register_operand" "=fxy")
1166: (float_truncate:SF
1167: (match_operand:DF 1 "register_operand" "fxy")))]
1168: ""
1169: "fcnvff,dbl,sgl %1,%0"
1170: [(set_attr "type" "fpalu")])
1171:
1172: ;; Conversion between fixed point and floating point.
1173: ;; Note that among the fix-to-float insns
1174: ;; the ones that start with SImode come first.
1175: ;; That is so that an operand that is a CONST_INT
1176: ;; (and therefore lacks a specific machine mode).
1177: ;; will be recognized as SImode (which is always valid)
1178: ;; rather than as QImode or HImode.
1179:
1180: ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
1181: ;; to be reloaded by putting the constant into memory.
1182: ;; It must come before the more general floatsisf2 pattern.
1183: (define_insn ""
1184: [(set (match_operand:SF 0 "general_operand" "=fxy")
1185: (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
1186: ""
1187: "* return output_floatsisf2 (operands);"
1188: [(set_attr "type" "fpalu")
1189: (set_attr "length" "3")])
1190:
1191: (define_insn "floatsisf2"
1192: [(set (match_operand:SF 0 "general_operand" "=fxy")
1193: (float:SF (match_operand:SI 1 "register_operand" "fxyr")))]
1194: ""
1195: "* return output_floatsisf2 (operands);"
1196: [(set_attr "type" "fpalu")
1197: (set_attr "length" "3")])
1198:
1199: ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
1200: ;; to be reloaded by putting the constant into memory.
1201: ;; It must come before the more general floatsidf2 pattern.
1202: (define_insn ""
1203: [(set (match_operand:DF 0 "general_operand" "=fxy")
1204: (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
1205: ""
1206: "* return output_floatsidf2 (operands);"
1207: [(set_attr "type" "fpalu")
1208: (set_attr "length" "3")])
1209:
1210: (define_insn "floatsidf2"
1211: [(set (match_operand:DF 0 "general_operand" "=fxy")
1212: (float:DF (match_operand:SI 1 "register_operand" "fxyr")))]
1213: ""
1214: "* return output_floatsidf2 (operands);"
1215: [(set_attr "type" "fpalu")
1216: (set_attr "length" "3")])
1217:
1218: ;; Convert a float to an actual integer.
1219: ;; Truncation is performed as part of the conversion.
1220:
1221: (define_insn "fix_truncsfsi2"
1222: [(set (match_operand:SI 0 "register_operand" "=fxy")
1223: (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "fxy"))))]
1224: ""
1225: "fcnvfxt,sgl,sgl %1,%0"
1226: [(set_attr "type" "fpalu")])
1227:
1228: (define_insn "fix_truncdfsi2"
1229: [(set (match_operand:SI 0 "register_operand" "=fxy")
1230: (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "fxy"))))]
1231: ""
1232: "fcnvfxt,dbl,sgl %1,%0"
1233: [(set_attr "type" "fpalu")])
1234:
1235:
1236: ;;- arithmetic instructions
1237:
1238: (define_insn "adddi3"
1239: [(set (match_operand:DI 0 "register_operand" "=r")
1240: (plus:DI (match_operand:DI 1 "register_operand" "%r")
1241: (match_operand:DI 2 "register_operand" "r")))]
1242: ""
1243: "add %R1,%R2,%R0\;addc %1,%2,%0"
1244: [(set_attr "type" "binary")
1245: (set_attr "length" "2")])
1246:
1247: (define_insn "addsi3"
1248: [(set (match_operand:SI 0 "register_operand" "=r,r")
1249: (plus:SI (match_operand:SI 1 "arith_operand" "%r,r")
1250: (match_operand:SI 2 "arith_operand" "r,J")))]
1251: ""
1252: "@
1253: add %1,%2,%0
1254: ldo %2(%1),%0")
1255:
1256: (define_insn "subdi3"
1257: [(set (match_operand:DI 0 "register_operand" "=r")
1258: (minus:DI (match_operand:DI 1 "register_operand" "r")
1259: (match_operand:DI 2 "register_operand" "r")))]
1260: ""
1261: "sub %R1,%R2,%R0\;subb %1,%2,%0"
1262: [(set_attr "length" "2")])
1263:
1264: (define_insn "subsi3"
1265: [(set (match_operand:SI 0 "register_operand" "=r,r")
1266: (minus:SI (match_operand:SI 1 "arith_operand" "r,r")
1267: (match_operand:SI 2 "arith_operand" "r,J")))]
1268: ""
1269: "@
1270: sub %1,%2,%0
1271: ldo %n2(%1),%0")
1272:
1273: ;; The mulsi3 insns set up registers for the millicode call. However,
1274: ;; if the multiplication involves constants, all that is
1275: ;; short-circuited.
1276: ;;
1277: ;; The algorithm used by output_mul_by_constant requires the source
1278: ;; and destination to be in different registers.
1279:
1280: (define_expand "mulsi3"
1281: [(set (reg:SI 26) (match_operand:SI 1 "general_operand" ""))
1282: (set (reg:SI 25) (match_operand:SI 2 "general_operand" ""))
1283: (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
1284: (clobber (match_scratch:SI 3 ""))
1285: (clobber (reg:SI 26))
1286: (clobber (reg:SI 25))
1287: (clobber (reg:SI 31))])
1288: (set (match_operand:SI 0 "register_operand" "") (reg:SI 29))]
1289: ""
1290: "
1291: {
1292: if (GET_CODE (operands[1]) == CONST_INT)
1293: {
1294: if (GET_CODE (operands[2]) == CONST_INT)
1295: emit_move_insn (operands[0],
1296: gen_rtx (CONST_INT, VOIDmode,
1297: INTVAL (operands[1]) * INTVAL (operands[2])));
1298: else
1299: {
1300: rtx temp;
1301:
1302: if (GET_CODE (operands[2]) == REG)
1303: temp = make_safe_from (operands[2], operands[0]);
1304: else
1305: temp = copy_to_reg (operands[2]);
1306: operands[2] = operands[1];
1307: operands[1] = temp;
1308: emit_mul_by_constant (operands, 0);
1309: }
1310: DONE;
1311: }
1312: else if (GET_CODE (operands[2]) == CONST_INT)
1313: {
1314: if (GET_CODE (operands[1]) == REG)
1315: operands[1] = make_safe_from (operands[1], operands[0]);
1316: else
1317: operands[1] = copy_to_reg (operands[1]);
1318: emit_mul_by_constant (operands, 0);
1319: DONE;
1320: }
1321: }")
1322:
1323: (define_insn ""
1324: [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
1325: (clobber (match_scratch:SI 0 "=a"))
1326: (clobber (reg:SI 26))
1327: (clobber (reg:SI 25))
1328: (clobber (reg:SI 31))]
1329: ""
1330: "* return output_mul_insn (0);"
1331: [(set_attr "type" "milli")])
1332:
1333: ;;; Division and mod.
1334:
1335: (define_expand "divsi3"
1336: [(set (reg:SI 26) (match_operand:SI 1 "general_operand" ""))
1337: (set (reg:SI 25) (match_operand:SI 2 "general_operand" ""))
1338: (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
1339: (clobber (match_scratch:SI 3 ""))
1340: (clobber (reg:SI 26))
1341: (clobber (reg:SI 25))
1342: (clobber (reg:SI 31))])
1343: (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))
1344: ]
1345: ""
1346: "
1347: {
1348: if (!(GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const(operands, 0)))
1349: {
1350: emit_move_insn (gen_rtx (REG, SImode, 26), operands[1]);
1351: emit_move_insn (gen_rtx (REG, SImode, 25), operands[2]);
1352: emit
1353: (gen_rtx
1354: (PARALLEL, VOIDmode,
1355: gen_rtvec (5, gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 29),
1356: gen_rtx (DIV, SImode,
1357: gen_rtx (REG, SImode, 26),
1358: gen_rtx (REG, SImode, 25))),
1359: gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)),
1360: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 26)),
1361: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 25)),
1362: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 31)))));
1363: emit_move_insn (operands[0], gen_rtx (REG, SImode, 29));
1364: }
1365: DONE;
1366: }")
1367:
1368:
1369: (define_insn ""
1370: [(set (reg:SI 29)
1371: (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
1372: (clobber (match_scratch:SI 1 "=a"))
1373: (clobber (reg:SI 26))
1374: (clobber (reg:SI 25))
1375: (clobber (reg:SI 31))]
1376: ""
1377: "*
1378: return output_div_insn (operands, 0);"
1379: [(set_attr "type" "milli")])
1380:
1381: (define_expand "udivsi3"
1382: [(set (reg:SI 26) (match_operand:SI 1 "general_operand" ""))
1383: (set (reg:SI 25) (match_operand:SI 2 "general_operand" ""))
1384: (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
1385: (clobber (match_scratch:SI 3 ""))
1386: (clobber (reg:SI 26))
1387: (clobber (reg:SI 25))
1388: (clobber (reg:SI 31))])
1389: (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))
1390: ]
1391: ""
1392: "
1393: {
1394: if (!(GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const(operands, 1)))
1395: {
1396: emit_move_insn (gen_rtx (REG, SImode, 26), operands[1]);
1397: emit_move_insn (gen_rtx (REG, SImode, 25), operands[2]);
1398: emit
1399: (gen_rtx
1400: (PARALLEL, VOIDmode,
1401: gen_rtvec (5, gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 29),
1402: gen_rtx (UDIV, SImode,
1403: gen_rtx (REG, SImode, 26),
1404: gen_rtx (REG, SImode, 25))),
1405: gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)),
1406: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 26)),
1407: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 25)),
1408: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 31)))));
1409: emit_move_insn (operands[0], gen_rtx (REG, SImode, 29));
1410: }
1411: DONE;
1412: }")
1413:
1414: (define_insn ""
1415: [(set (reg:SI 29)
1416: (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
1417: (clobber (match_scratch:SI 1 "=a"))
1418: (clobber (reg:SI 26))
1419: (clobber (reg:SI 25))
1420: (clobber (reg:SI 31))]
1421: ""
1422: "*
1423: return output_div_insn (operands, 1);"
1424: [(set_attr "type" "milli")])
1425:
1426: (define_expand "modsi3"
1427: [(set (reg:SI 26) (match_operand:SI 1 "general_operand" ""))
1428: (set (reg:SI 25) (match_operand:SI 2 "general_operand" ""))
1429: (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
1430: (clobber (match_scratch:SI 3 ""))
1431: (clobber (reg:SI 26))
1432: (clobber (reg:SI 25))
1433: (clobber (reg:SI 31))])
1434: (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
1435: ""
1436: "
1437: {
1438: emit_move_insn (gen_rtx (REG, SImode, 26), operands[1]);
1439: emit_move_insn (gen_rtx (REG, SImode, 25), operands[2]);
1440: emit
1441: (gen_rtx
1442: (PARALLEL, VOIDmode,
1443: gen_rtvec (5, gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 29),
1444: gen_rtx (MOD, SImode,
1445: gen_rtx (REG, SImode, 26),
1446: gen_rtx (REG, SImode, 25))),
1447: gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)),
1448: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 26)),
1449: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 25)),
1450: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 31)))));
1451: emit_move_insn (operands[0], gen_rtx (REG, SImode, 29));
1452: DONE;
1453: }")
1454:
1455: (define_insn ""
1456: [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
1457: (clobber (match_scratch:SI 0 "=a"))
1458: (clobber (reg:SI 26))
1459: (clobber (reg:SI 25))
1460: (clobber (reg:SI 31))]
1461: ""
1462: "*
1463: return output_mod_insn (0);"
1464: [(set_attr "type" "milli")])
1465:
1466: (define_expand "umodsi3"
1467: [(set (reg:SI 26) (match_operand:SI 1 "general_operand" ""))
1468: (set (reg:SI 25) (match_operand:SI 2 "general_operand" ""))
1469: (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
1470: (clobber (match_scratch:SI 3 ""))
1471: (clobber (reg:SI 26))
1472: (clobber (reg:SI 25))
1473: (clobber (reg:SI 31))])
1474: (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
1475: ""
1476: "
1477: {
1478: emit_move_insn (gen_rtx (REG, SImode, 26), operands[1]);
1479: emit_move_insn (gen_rtx (REG, SImode, 25), operands[2]);
1480: emit
1481: (gen_rtx
1482: (PARALLEL, VOIDmode,
1483: gen_rtvec (5, gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 29),
1484: gen_rtx (UMOD, SImode,
1485: gen_rtx (REG, SImode, 26),
1486: gen_rtx (REG, SImode, 25))),
1487: gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)),
1488: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 26)),
1489: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 25)),
1490: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 31)))));
1491: emit_move_insn (operands[0], gen_rtx (REG, SImode, 29));
1492: DONE;
1493: }")
1494:
1495: (define_insn ""
1496: [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
1497: (clobber (match_scratch:SI 0 "=a"))
1498: (clobber (reg:SI 26))
1499: (clobber (reg:SI 25))
1500: (clobber (reg:SI 31))]
1501: ""
1502: "*
1503: return output_mod_insn (1);"
1504: [(set_attr "type" "milli")])
1505:
1506: ;;- and instructions
1507: ;; We define DImode `and` so with DImode `not` we can get
1508: ;; DImode `andn`. Other combinations are possible.
1509:
1510: (define_expand "anddi3"
1511: [(set (match_operand:DI 0 "register_operand" "")
1512: (and:DI (match_operand:DI 1 "arith_double_operand" "")
1513: (match_operand:DI 2 "arith_double_operand" "")))]
1514: ""
1515: "
1516: {
1517: if (! register_operand (operands[1], DImode)
1518: || ! register_operand (operands[2], DImode))
1519: /* Let GCC break this into word-at-a-time operations. */
1520: FAIL;
1521: }")
1522:
1523: (define_insn ""
1524: [(set (match_operand:DI 0 "register_operand" "=r")
1525: (and:DI (match_operand:DI 1 "register_operand" "%r")
1526: (match_operand:DI 2 "register_operand" "r")))]
1527: ""
1528: "and %1,%2,%0\;and %R1,%R2,%R0"
1529: [(set_attr "length" "2")])
1530:
1531: (define_insn "andsi3"
1532: [(set (match_operand:SI 0 "register_operand" "=r")
1533: (and:SI (match_operand:SI 1 "register_operand" "%r")
1534: (match_operand:SI 2 "register_operand" "r")))]
1535: ""
1536: "and %1,%2,%0")
1537:
1538: (define_insn ""
1539: [(set (match_operand:DI 0 "register_operand" "=r")
1540: (and:DI (match_operand:DI 1 "register_operand" "r")
1541: (not:DI (match_operand:DI 2 "register_operand" "r"))))]
1542: ""
1543: "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
1544: [(set_attr "length" "2")])
1545:
1546: (define_insn ""
1547: [(set (match_operand:SI 0 "register_operand" "=r")
1548: (and:SI (match_operand:SI 1 "register_operand" "%r")
1549: (not:SI (match_operand:SI 2 "register_operand" "r"))))]
1550: ""
1551: "andcm %1,%2,%0")
1552:
1553:
1554: (define_expand "iordi3"
1555: [(set (match_operand:DI 0 "register_operand" "")
1556: (ior:DI (match_operand:DI 1 "arith_double_operand" "")
1557: (match_operand:DI 2 "arith_double_operand" "")))]
1558: ""
1559: "
1560: {
1561: if (! register_operand (operands[1], DImode)
1562: || ! register_operand (operands[2], DImode))
1563: /* Let GCC break this into word-at-a-time operations. */
1564: FAIL;
1565: }")
1566:
1567: (define_insn ""
1568: [(set (match_operand:DI 0 "register_operand" "=r")
1569: (ior:DI (match_operand:DI 1 "register_operand" "%r")
1570: (match_operand:DI 2 "register_operand" "r")))]
1571: ""
1572: "or %1,%2,%0\;or %R1,%R2,%R0"
1573: [(set_attr "length" "2")])
1574:
1575: (define_insn "iorsi3"
1576: [(set (match_operand:SI 0 "register_operand" "=r")
1577: (ior:SI (match_operand:SI 1 "register_operand" "%r")
1578: (match_operand:SI 2 "register_operand" "r")))]
1579: ""
1580: "or %1,%2,%0")
1581:
1582: (define_expand "xordi3"
1583: [(set (match_operand:DI 0 "register_operand" "")
1584: (xor:DI (match_operand:DI 1 "arith_double_operand" "")
1585: (match_operand:DI 2 "arith_double_operand" "")))]
1586: ""
1587: "
1588: {
1589: if (! register_operand (operands[1], DImode)
1590: || ! register_operand (operands[2], DImode))
1591: /* Let GCC break this into word-at-a-time operations. */
1592: FAIL;
1593: }")
1594:
1595: (define_insn ""
1596: [(set (match_operand:DI 0 "register_operand" "=r")
1597: (xor:DI (match_operand:DI 1 "register_operand" "%r")
1598: (match_operand:DI 2 "register_operand" "r")))]
1599: ""
1600: "xor %1,%2,%0\;xor %R1,%R2,%R0"
1601: [(set_attr "length" "2")])
1602:
1603: (define_insn "xorsi3"
1604: [(set (match_operand:SI 0 "register_operand" "=r")
1605: (xor:SI (match_operand:SI 1 "register_operand" "%r")
1606: (match_operand:SI 2 "register_operand" "r")))]
1607: ""
1608: "xor %r1,%2,%0")
1609:
1610: (define_insn "negdi2"
1611: [(set (match_operand:DI 0 "register_operand" "=r")
1612: (neg:DI (match_operand:DI 1 "register_operand" "r")))]
1613: ""
1614: "sub 0,%R1,%R0\;subb 0,%1,%0"
1615: [(set_attr "type" "unary")
1616: (set_attr "length" "2")])
1617:
1618: (define_insn "negsi2"
1619: [(set (match_operand:SI 0 "register_operand" "=r")
1620: (neg:SI (match_operand:SI 1 "register_operand" "r")))]
1621: ""
1622: "@
1623: sub 0,%1,%0"
1624: [(set_attr "type" "unary")])
1625:
1626: (define_expand "one_cmpldi2"
1627: [(set (match_operand:DI 0 "register_operand" "")
1628: (not:DI (match_operand:DI 1 "arith_double_operand" "")))]
1629: ""
1630: "
1631: {
1632: if (! register_operand (operands[1], DImode))
1633: FAIL;
1634: }")
1635:
1636: (define_insn ""
1637: [(set (match_operand:DI 0 "register_operand" "=r")
1638: (not:DI (match_operand:DI 1 "arith_double_operand" "r")))]
1639: ""
1640: "uaddcm 0,%1,%0\;uaddcm 0,%R1,%R0"
1641: [(set_attr "type" "unary")
1642: (set_attr "length" "2")])
1643:
1644: (define_insn "one_cmplsi2"
1645: [(set (match_operand:SI 0 "general_operand" "=r")
1646: (not:SI (match_operand:SI 1 "register_operand" "r")))]
1647: ""
1648: "uaddcm 0,%1,%0"
1649: [(set_attr "type" "unary")])
1650:
1651: ;; Floating point arithmetic instructions.
1652:
1653: (define_insn "adddf3"
1654: [(set (match_operand:DF 0 "register_operand" "=fxy")
1655: (plus:DF (match_operand:DF 1 "register_operand" "fxy")
1656: (match_operand:DF 2 "register_operand" "fxy")))]
1657: ""
1658: "fadd,dbl %1,%2,%0"
1659: [(set_attr "type" "fpalu")])
1660:
1661: (define_insn "addsf3"
1662: [(set (match_operand:SF 0 "register_operand" "=fxy")
1663: (plus:SF (match_operand:SF 1 "register_operand" "fxy")
1664: (match_operand:SF 2 "register_operand" "fxy")))]
1665: ""
1666: "fadd,sgl %1,%2,%0"
1667: [(set_attr "type" "fpalu")])
1668:
1669: (define_insn "subdf3"
1670: [(set (match_operand:DF 0 "register_operand" "=fxy")
1671: (minus:DF (match_operand:DF 1 "register_operand" "fxy")
1672: (match_operand:DF 2 "register_operand" "fxy")))]
1673: ""
1674: "fsub,dbl %1,%2,%0"
1675: [(set_attr "type" "fpalu")])
1676:
1677: (define_insn "subsf3"
1678: [(set (match_operand:SF 0 "register_operand" "=fxy")
1679: (minus:SF (match_operand:SF 1 "register_operand" "fxy")
1680: (match_operand:SF 2 "register_operand" "fxy")))]
1681: ""
1682: "fsub,sgl %1,%2,%0"
1683: [(set_attr "type" "fpalu")])
1684:
1685: (define_insn "muldf3"
1686: [(set (match_operand:DF 0 "register_operand" "=fxy")
1687: (mult:DF (match_operand:DF 1 "register_operand" "fxy")
1688: (match_operand:DF 2 "register_operand" "fxy")))]
1689: ""
1690: "fmpy,dbl %1,%2,%0"
1691: [(set_attr "type" "fpmul")])
1692:
1693: (define_insn "mulsf3"
1694: [(set (match_operand:SF 0 "register_operand" "=fxy")
1695: (mult:SF (match_operand:SF 1 "register_operand" "fxy")
1696: (match_operand:SF 2 "register_operand" "fxy")))]
1697: ""
1698: "fmpy,sgl %1,%2,%0"
1699: [(set_attr "type" "fpmul")])
1700:
1701: (define_insn "divdf3"
1702: [(set (match_operand:DF 0 "register_operand" "=fxy")
1703: (div:DF (match_operand:DF 1 "register_operand" "fxy")
1704: (match_operand:DF 2 "register_operand" "fxy")))]
1705: ""
1706: "fdiv,dbl %1,%2,%0"
1707: [(set_attr "type" "fpdivdbl")])
1708:
1709: (define_insn "divsf3"
1710: [(set (match_operand:SF 0 "register_operand" "=fxy")
1711: (div:SF (match_operand:SF 1 "register_operand" "fxy")
1712: (match_operand:SF 2 "register_operand" "fxy")))]
1713: ""
1714: "fdiv,sgl %1,%2,%0"
1715: [(set_attr "type" "fpdivsgl")])
1716:
1717: (define_insn "negdf2"
1718: [(set (match_operand:DF 0 "register_operand" "=fxy")
1719: (neg:DF (match_operand:DF 1 "register_operand" "fxy")))]
1720: ""
1721: "fsub,dbl 0,%1,%0"
1722: [(set_attr "type" "fpalu")])
1723:
1724: (define_insn "negsf2"
1725: [(set (match_operand:SF 0 "register_operand" "=fxy")
1726: (neg:SF (match_operand:SF 1 "register_operand" "fxy")))]
1727: ""
1728: "fsub,sgl 0, %1,%0"
1729: [(set_attr "type" "fpalu")])
1730:
1731: (define_insn "absdf2"
1732: [(set (match_operand:DF 0 "register_operand" "=fxy")
1733: (abs:DF (match_operand:DF 1 "register_operand" "fxy")))]
1734: ""
1735: "fabs,dbl %0,%0"
1736: [(set_attr "type" "fpalu")])
1737:
1738: (define_insn "abssf2"
1739: [(set (match_operand:SF 0 "register_operand" "=fxy")
1740: (abs:SF (match_operand:SF 1 "register_operand" "fxy")))]
1741: ""
1742: "fabs,sgl %1,%0"
1743: [(set_attr "type" "fpalu")])
1744:
1745: (define_insn "sqrtdf2"
1746: [(set (match_operand:DF 0 "register_operand" "=fxy")
1747: (sqrt:DF (match_operand:DF 1 "register_operand" "fxy")))]
1748: ""
1749: "fsqrt,dbl %1,%0"
1750: [(set_attr "type" "fpsqrtdbl")])
1751:
1752: (define_insn "sqrtsf2"
1753: [(set (match_operand:SF 0 "register_operand" "=f")
1754: (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
1755: ""
1756: "fsqrt,sgl %1,%0"
1757: [(set_attr "type" "fpsqrtsgl")])
1758:
1759: ;;- arithmetic shift instructions
1760:
1761: ;; A safe subtraction insn for values going into the shift register.
1762:
1763: ;; Optimized special case of shifting.
1764: ;; Must precede the general case. ?
1765:
1766: (define_insn ""
1767: [(set (match_operand:SI 0 "register_operand" "=r")
1768: (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
1769: (const_int 24)))]
1770: ""
1771: "ldb%M1 %1,%0")
1772:
1773: (define_insn ""
1774: [(set (match_operand:SI 0 "register_operand" "=r")
1775: (plus:SI (match_operand:SI 1 "register_operand" "r")
1776: (mult:SI (match_operand:SI 2 "register_operand" "r")
1777: (const_int 2))))]
1778: ""
1779: "sh1add %2,%1,%0")
1780:
1781: (define_insn ""
1782: [(set (match_operand:SI 0 "register_operand" "=r")
1783: (plus:SI (match_operand:SI 1 "register_operand" "r")
1784: (mult:SI (match_operand:SI 2 "register_operand" "r")
1785: (const_int 4))))]
1786: ""
1787: "sh2add %2,%1,%0")
1788:
1789: (define_insn ""
1790: [(set (match_operand:SI 0 "register_operand" "=r")
1791: (plus:SI (match_operand:SI 1 "register_operand" "r")
1792: (mult:SI (match_operand:SI 2 "register_operand" "r")
1793: (const_int 8))))]
1794: ""
1795: "sh3add %2,%1,%0")
1796:
1797: (define_insn "sar_sub"
1798: [(set (match_operand:SI 0 "register_operand" "=r")
1799: (if_then_else (gtu:SI (match_operand:SI 2 "register_operand" "r")
1800: (match_operand:SI 1 "int11_operand" "I"))
1801: (const_int 0)
1802: (minus:SI (match_dup 1) (match_dup 2))))]
1803: ""
1804: "subi,>>= %1,%2,%0\;copy 0,%0"
1805: [(set_attr "length" "2" )])
1806:
1807: (define_expand "ashlsi3"
1808: [(set (match_operand:SI 0 "register_operand" "")
1809: (ashift:SI (match_operand:SI 1 "register_operand" "")
1810: (match_operand:SI 2 "arith5_operand" "")))]
1811: ""
1812: "
1813: {
1814: if (GET_CODE (operands[2]) != CONST_INT)
1815: {
1816: rtx temp = gen_reg_rtx (SImode);
1817: emit_insn (gen_sar_sub (temp,
1818: gen_rtx (CONST_INT, VOIDmode, 31),
1819: operands[2]));
1820: emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 112), temp));
1821: emit_insn (gen_rtx (SET, VOIDmode,
1822: operands[0],
1823: gen_rtx (ASHIFT, SImode,
1824: operands[1],
1825: gen_rtx (MINUS, SImode,
1826: gen_rtx (CONST_INT, VOIDmode, 31),
1827: gen_rtx (REG, SImode, 112)))));
1828: DONE;
1829: }
1830: }")
1831:
1832: (define_insn ""
1833: [(set (match_operand:SI 0 "register_operand" "=r")
1834: (ashift:SI (match_operand:SI 1 "register_operand" "r")
1835: (match_operand:SI 2 "int5_operand" "L")))]
1836: ""
1837: "*
1838: {
1839: rtx xoperands[4];
1840: xoperands[0] = operands[0]; xoperands[1] = operands[1];
1841: xoperands[2] = gen_rtx (CONST_INT, VOIDmode,
1842: 31 - INTVAL (operands[2]));
1843: xoperands[3] = gen_rtx (CONST_INT, VOIDmode,
1844: 32 - INTVAL (operands[2]));
1845: output_asm_insn (\"zdep %1,%2,%3,%0\", xoperands);
1846: return \"\";
1847: }")
1848:
1849: (define_insn ""
1850: [(set (match_operand:SI 0 "register_operand" "=r")
1851: (ashift:SI (match_operand:SI 1 "register_operand" "r")
1852: (minus:SI (const_int 31)
1853: (reg:SI 112))))]
1854: ""
1855: "zvdep %1,32,%0")
1856:
1857: (define_expand "ashrsi3"
1858: [(set (match_operand:SI 0 "register_operand" "")
1859: (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
1860: (match_operand:SI 2 "arith5_operand" "")))]
1861: ""
1862: "
1863: {
1864: if (GET_CODE (operands[2]) != CONST_INT)
1865: {
1866: rtx temp = gen_reg_rtx (SImode);
1867: emit_insn (gen_sar_sub (temp,
1868: gen_rtx (CONST_INT, VOIDmode, 31),
1869: operands[2]));
1870: emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 112), temp));
1871: emit_insn (gen_rtx (SET, VOIDmode,
1872: operands[0],
1873: gen_rtx (ASHIFTRT, SImode,
1874: operands[1],
1875: gen_rtx (MINUS, SImode,
1876: gen_rtx (CONST_INT, VOIDmode, 31),
1877: gen_rtx (REG, SImode, 112)))));
1878: DONE;
1879: }
1880: }")
1881:
1882: (define_insn ""
1883: [(set (match_operand:SI 0 "register_operand" "=r")
1884: (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
1885: (match_operand:SI 2 "int5_operand" "L")))]
1886: ""
1887: "*
1888: {
1889: rtx xoperands[4];
1890: xoperands[0] = operands[0]; xoperands[1] = operands[1];
1891: xoperands[2] = gen_rtx (CONST_INT, VOIDmode,
1892: 31 - INTVAL (operands[2]));
1893: xoperands[3] = gen_rtx (CONST_INT, VOIDmode,
1894: 32 - INTVAL (operands[2]));
1895: output_asm_insn (\"extrs %1,%2,%3,%0\", xoperands);
1896: return \"\";
1897: }")
1898:
1899:
1900: (define_insn ""
1901: [(set (match_operand:SI 0 "register_operand" "=r")
1902: (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
1903: (minus:SI (const_int 31)
1904: (reg:SI 112))))]
1905: ""
1906: "vextrs %1,32,%0")
1907:
1908: (define_expand "lshrsi3"
1909: [(set (match_operand:SI 0 "register_operand" "")
1910: (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
1911: (match_operand:SI 2 "arith5_operand" "")))]
1912: ""
1913: "
1914: {
1915: if (GET_CODE (operands[2]) != CONST_INT)
1916: {
1917: rtx temp = gen_reg_rtx (SImode);
1918: emit_insn (gen_sar_sub (temp,
1919: gen_rtx (CONST_INT, VOIDmode, 31),
1920: operands[2]));
1921: emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 112), temp));
1922: emit_insn (gen_rtx (SET, VOIDmode,
1923: operands[0],
1924: gen_rtx (LSHIFTRT, SImode,
1925: operands[1],
1926: gen_rtx (MINUS, SImode,
1927: gen_rtx (CONST_INT, VOIDmode, 31),
1928: gen_rtx (REG, SImode, 112)))));
1929: DONE;
1930: }
1931: }")
1932:
1933: (define_insn ""
1934: [(set (match_operand:SI 0 "register_operand" "=r")
1935: (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
1936: (match_operand:SI 2 "uint5_operand" "K")))]
1937: ""
1938: "*
1939: {
1940: rtx xoperands[4];
1941: xoperands[0] = operands[0]; xoperands[1] = operands[1];
1942: xoperands[2] = gen_rtx (CONST_INT, VOIDmode,
1943: 31 - INTVAL (operands[2]));
1944: xoperands[3] = gen_rtx (CONST_INT, VOIDmode,
1945: 32 - INTVAL (operands[2]));
1946: output_asm_insn (\"extru %1,%2,%3,%0\", xoperands);
1947: return \"\";
1948: }")
1949:
1950: (define_insn ""
1951: [(set (match_operand:SI 0 "register_operand" "=r")
1952: (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
1953: (minus:SI (const_int 31)
1954: (reg:SI 112))))]
1955: ""
1956: "vextru %1,32,%0")
1957:
1958: ;; Unconditional and other jump instructions.
1959:
1960: (define_insn "jump"
1961: [(set (pc) (label_ref (match_operand 0 "" "")))]
1962: ""
1963: "bl%* %l0,0"
1964: [(set_attr "type" "branch")])
1965:
1966: (define_insn "casesi"
1967: [(set (pc)
1968: (if_then_else (leu (minus:SI
1969: (match_operand:SI 0 "general_operand" "r")
1970: (match_operand:SI 1 "general_operand" "rI"))
1971: (match_operand:SI 2 "general_operand" "rI"))
1972: (plus:SI (mem:SI (plus:SI (pc)
1973: (minus:SI (match_dup 0)
1974: (match_dup 1))))
1975: (label_ref (match_operand 3 "" "")))
1976: (pc)))
1977: (use (label_ref (match_operand 4 "" "")))
1978: (clobber (match_scratch:SI 5 "=r"))]
1979: ""
1980: "*
1981: {
1982: if (GET_CODE (operands[1]) == CONST_INT)
1983: {
1984: if (GET_CODE (operands[2]) == CONST_INT)
1985: {
1986: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1987: INTVAL (operands[1]) + INTVAL (operands[2]));
1988: if (!INT_11_BITS (operands[2]))
1989: {
1990: output_asm_insn (\"ldo %2(0),%5\", operands);
1991: operands[2] = operands[5];
1992: }
1993: }
1994: else
1995: output_asm_insn (\"ldo %1(%2),%2\", operands);
1996: output_asm_insn (\"addi,< %n1,%0,0\", operands);
1997: }
1998: else
1999: {
2000: if (GET_CODE (operands[2]) == CONST_INT)
2001: {
2002: output_asm_insn (\"ldo %2(%1),%5\", operands);
2003: operands[2] = operands[5];
2004: }
2005: output_asm_insn (\"sub,< %0,%1,0\", operands);
2006: }
2007: if (GET_CODE (operands[2]) == CONST_INT)
2008: output_asm_insn (\"addi,<= %n2,%0,0\", operands);
2009: else
2010: output_asm_insn (\"sub,<= %0,%2,0\", operands);
2011: output_asm_insn (\"b,n %l4\", operands);
2012: if (GET_CODE (operands[1]) == CONST_INT)
2013: output_asm_insn (\"ldo %n1(%0),%5\", operands);
2014: else output_asm_insn (\"sub %0,%1,%5\", operands);
2015: return \"blr %5,0\;nop\";
2016: }"
2017: [(set_attr "length" "7")])
2018:
2019: ;; Need nops for the calls because execution is supposed to continue
2020: ;; past; we don't want to nullify an instruction that we need.
2021: ;;- jump to subroutine
2022:
2023: (define_expand "call"
2024: [(parallel [(call (match_operand:SI 0 "" "")
2025: (match_operand 1 "" ""))
2026: (clobber (reg:SI 31))
2027: (clobber (reg:SI 2))])]
2028: ""
2029: "
2030: {
2031: operands[0] = gen_rtx (MEM, SImode, XEXP (operands[0], 0));
2032: }")
2033:
2034: (define_insn ""
2035: [(call (mem:SI (match_operand:SI 0 "call_operand_address" "r,S"))
2036: (match_operand 1 "" "i,i"))
2037: (clobber (reg:SI 31))
2038: (clobber (reg:SI 2))]
2039: ""
2040: "*
2041: {
2042: if (which_alternative == 0)
2043: return \"copy %0,22\;.CALL\\tARGW0=GR\;bl $$dyncall,31\;copy 31,2\";
2044: else
2045: {
2046: output_arg_descriptor (insn);
2047: return \"bl %0,2%#\";
2048: }
2049: }"
2050: [(set_attr "type" "dyncall,call")
2051: (set_attr "length" "3,1")])
2052:
2053: (define_expand "call_value"
2054: [(parallel [(set (match_operand 0 "" "")
2055: (call (match_operand:SI 1 "" "")
2056: (match_operand 2 "" "")))
2057: (clobber (reg:SI 31))
2058: (clobber (reg:SI 2))])]
2059: ;;- Don't use operand 1 for most machines.
2060: ""
2061: "
2062: {
2063: operands[1] = gen_rtx (MEM, SImode, XEXP (operands[1], 0));
2064: }")
2065:
2066: (define_insn ""
2067: [(set (match_operand 0 "" "=rf,rf")
2068: (call (mem:SI (match_operand:SI 1 "call_operand_address" "r,S"))
2069: (match_operand 2 "" "i,i")))
2070: (clobber (reg:SI 31))
2071: (clobber (reg:SI 2))]
2072: ;;- Don't use operand 1 for most machines.
2073: ""
2074: "*
2075: {
2076: if (which_alternative == 0)
2077: return \"copy %1,22\;.CALL\\tARGW0=GR\;bl $$dyncall,31\;copy 31,2\";
2078: else
2079: {
2080: output_arg_descriptor (insn);
2081: return \"bl %1,2\;nop\";
2082: }
2083: }"
2084: [(set_attr "type" "dyncall")
2085: (set_attr "length" "3,2")])
2086:
2087: (define_insn "nop"
2088: [(const_int 0)]
2089: ""
2090: "nop")
2091:
2092: ;;; Hope this is only within a function...
2093: (define_insn "indirect_jump"
2094: [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
2095: ""
2096: "bv 0(%0)%#"
2097: [(set_attr "type" "branch")])
2098:
2099: (define_insn "extzv"
2100: [(set (match_operand:SI 0 "register_operand" "=r")
2101: (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2102: (match_operand:SI 2 "uint5_operand" "")
2103: (match_operand:SI 3 "uint5_operand" "")))]
2104: ""
2105: "extru %1,%3+%2-1,%2,%0")
2106:
2107: (define_insn "extv"
2108: [(set (match_operand:SI 0 "register_operand" "=r")
2109: (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
2110: (match_operand:SI 2 "uint5_operand" "")
2111: (match_operand:SI 3 "uint5_operand" "")))]
2112: ""
2113: "extrs %1,%3+%2-1,%2,%0")
2114:
2115: (define_insn "insv"
2116: [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "=r")
2117: (match_operand:SI 1 "uint5_operand" "")
2118: (match_operand:SI 2 "uint5_operand" ""))
2119: (match_operand:SI 3 "register_operand" "r"))]
2120: ""
2121: "dep %3,%2+%1-1,%1,%0")
2122:
2123: ;;- Local variables:
2124: ;;- mode:emacs-lisp
2125: ;;- comment-start: ";;- "
2126: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
2127: ;;- eval: (modify-syntax-entry ?[ "(]")
2128: ;;- eval: (modify-syntax-entry ?] ")[")
2129: ;;- eval: (modify-syntax-entry ?{ "(}")
2130: ;;- eval: (modify-syntax-entry ?} "){")
2131: ;;- End:
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