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1.1 root 1: ;;- Machine description for HP PA-RISC architecture for GNU C compiler
2: ;; Copyright (C) 1992 Free Software Foundation, Inc.
3: ;; Contributed by the Center for Software Science at the University
4: ;; of Utah.
5:
6: ;; This file is part of GNU CC.
7:
8: ;; GNU CC is free software; you can redistribute it and/or modify
9: ;; it under the terms of the GNU General Public License as published by
10: ;; the Free Software Foundation; either version 2, or (at your option)
11: ;; any later version.
12:
13: ;; GNU CC is distributed in the hope that it will be useful,
14: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16: ;; GNU General Public License for more details.
17:
18: ;; You should have received a copy of the GNU General Public License
19: ;; along with GNU CC; see the file COPYING. If not, write to
20: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21:
22: ;; This gcc Version 2 machine description is inspired by sparc.md and
23: ;; mips.md.
24:
25: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
26:
27: ;; Insn type. Used to default other attribute values.
28:
29: ;; type "unary" insns have one input operand (1) and one output operand (0)
30: ;; type "binary" insns have two input operands (1,2) and one output (0)
31:
32: (define_attr "type"
33: "move,unary,binary,compare,load,store,branch,cbranch,call,dyncall,address,fpload,fpstore,fpalu,fpcc,fpmul,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,misc,milli"
34: (const_string "binary"))
35:
36: ;; Set true if insn uses call-clobbered intermediate register.
37: (define_attr "use_clobbered" "false,true"
38: (if_then_else (and (eq_attr "type" "address")
39: (match_operand 0 "clobbered_register" ""))
40: (const_string "true")
41: (const_string "false")))
42:
43: ;; Length (in # of insns).
44: (define_attr "length" ""
45: (cond [(eq_attr "type" "load,fpload")
46: (if_then_else (match_operand 1 "symbolic_memory_operand" "")
47: (const_int 2) (const_int 1))
48:
49: (eq_attr "type" "store,fpstore")
50: (if_then_else (match_operand 0 "symbolic_memory_operand" "")
51: (const_int 2) (const_int 1))
52:
53: (eq_attr "type" "address") (const_int 2)
54:
55: (eq_attr "type" "binary")
56: (if_then_else (match_operand 2 "arith_operand" "")
57: (const_int 1) (const_int 3))
58:
59: (eq_attr "type" "move,unary")
60: (if_then_else (match_operand 1 "arith_operand" "")
61: (const_int 1) (const_int 2))]
62:
63: (const_int 1)))
64:
65: (define_asm_attributes
66: [(set_attr "length" "1")
67: (set_attr "type" "multi")])
68:
69: ;; Attributes for instruction and branch scheduling
70:
71: (define_attr "in_call_delay" "false,true"
72: (cond [(eq_attr "type" "branch,cbranch,call,dyncall,multi,milli")
73: (const_string "false")
74:
75: (eq_attr "type" "load,fpload,store,fpstore")
76: (if_then_else (eq_attr "length" "1")
77: (const_string "true")
78: (const_string "false"))
79:
80: (eq_attr "type" "address")
81: (if_then_else (eq_attr "use_clobbered" "false")
82: (const_string "true")
83: (const_string "false"))]
84:
85: (if_then_else (eq_attr "length" "1")
86: (const_string "true")
87: (const_string "false"))))
88:
89: (define_attr "in_milli_delay" "false,true"
90: (cond [(eq_attr "length" "!1")
91: (const_string "false")
92:
93: (eq_attr "type" "branch,cbranch,call,dyncall,milli")
94: (const_string "false")
95:
96: (ne (symbol_ref "use_milli_regs (insn)") (const_int 0))
97: (const_string "false")]
98: (const_string "true")))
99:
100: (define_delay (eq_attr "type" "call")
101: [(eq_attr "in_call_delay" "true") (nil) (nil)])
102:
103: (define_attr "in_branch_delay" "false,true"
104: (if_then_else (and (eq_attr "type" "!branch,cbranch,call,multi,milli")
105: (eq_attr "length" "1"))
106: (const_string "true")
107: (const_string "false")))
108:
109: (define_delay (eq_attr "type" "branch")
110: [(eq_attr "in_branch_delay" "true")
111: (eq_attr "in_branch_delay" "true") (nil)])
112:
113: (define_delay (eq_attr "type" "cbranch")
114: [(eq_attr "in_branch_delay" "true") (nil) (nil)])
115:
116: (define_delay (eq_attr "type" "milli")
117: [(eq_attr "in_milli_delay" "true") (nil) (nil)])
118:
119: ;; Function units of the HPPA. The following data is for the "Snake"
120: ;; (Mustang CPU + Timex FPU) because that's what I have the docs for.
121: ;; Scheduling instructions for PA-83 machines according to the Snake
122: ;; constraints shouldn't hurt.
123:
124: ;; (define_function_unit {name} {num-units} {n-users} {test}
125: ;; {ready-delay} {busy-delay} [{conflict-list}])
126:
127: ;; The integer ALU.
128: ;; (Noted only for documentation; units that take one cycle do not need to
129: ;; be specified.)
130:
131: ;; (define_function_unit "alu" 1 0
132: ;; (eq_attr "type" "unary,binary,move,address") 1 0)
133:
134:
135: ;; Memory. Disregarding Cache misses, the Mustang memory times are:
136: ;; load: 1
137: ;; store, fpstore: 3, no D-cache operations should be scheduled.
138: ;; fpload: 3 (really 2 for flops, but I don't think we can specify that).
139:
140: (define_function_unit "memory" 1 1 (eq_attr "type" "load") 1 0)
141: (define_function_unit "memory" 1 1 (eq_attr "type" "store,fpstore") 3 0)
142: (define_function_unit "memory" 1 1 (eq_attr "type" "fpload") 3 0)
143:
144: ;; The Timex has two floating-point units: ALU, and MUL/DIV/SQRT unit.
145: ;; Timings:
146: ;; Instruction Time Unit Minimum Distance (unit contention)
147: ;; fcpy 3 ALU 2
148: ;; fabs 3 ALU 2
149: ;; fadd 3 ALU 2
150: ;; fsub 3 ALU 2
151: ;; fcmp 3 ALU 2
152: ;; fcnv 3 ALU 2
153: ;; fmpyadd 3 ALU,MPY 2
154: ;; fmpysub 3 ALU,MPY 2
155: ;; fmpycfxt 3 ALU,MPY 2
156: ;; fmpy 3 MPY 2
157: ;; fmpyi 3 MPY 2
158: ;; fdiv,sgl 10 MPY 10
159: ;; fdiv,dbl 12 MPY 12
160: ;; fsqrt,sgl 14 MPY 14
161: ;; fsqrt,dbl 18 MPY 18
162:
163: (define_function_unit "fp_alu" 1 0 (eq_attr "type" "fpalu") 3 2)
164: (define_function_unit "fp_mpy" 1 0 (eq_attr "type" "fpmul") 3 2)
165: (define_function_unit "fp_mpy" 1 0 (eq_attr "type" "fpdivsgl") 10 10)
166: (define_function_unit "fp_mpy" 1 0 (eq_attr "type" "fpdivdbl") 12 12)
167: (define_function_unit "fp_mpy" 1 0 (eq_attr "type" "fpsqrtsgl") 14 14)
168: (define_function_unit "fp_mpy" 1 0 (eq_attr "type" "fpsqrtdbl") 18 18)
169:
170: ;; Compare instructions.
171: ;; This controls RTL generation and register allocation.
172:
173: ;; We generate RTL for comparisons and branches by having the cmpxx
174: ;; patterns store away the operands. Then, the scc and bcc patterns
175: ;; emit RTL for both the compare and the branch.
176: ;;
177:
178: (define_expand "cmpsi"
179: [(set (reg:CC 0)
180: (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
181: (match_operand:SI 1 "arith5_operand" "")))]
182: ""
183: "
184: {
185: hppa_compare_op0 = operands[0];
186: hppa_compare_op1 = operands[1];
187: hppa_branch_type = CMP_SI;
188: DONE;
189: }")
190:
191: (define_expand "cmpsf"
192: [(set (reg:CCFP 0)
193: (compare:CCFP (match_operand:SF 0 "register_operand" "")
194: (match_operand:SF 1 "register_operand" "")))]
195: ""
196: "
197: {
198: hppa_compare_op0 = operands[0];
199: hppa_compare_op1 = operands[1];
200: hppa_branch_type = CMP_SF;
201: DONE;
202: }")
203:
204: (define_expand "cmpdf"
205: [(set (reg:CCFP 0)
206: (compare:CCFP (match_operand:DF 0 "register_operand" "")
207: (match_operand:DF 1 "register_operand" "")))]
208: ""
209: "
210: {
211: hppa_compare_op0 = operands[0];
212: hppa_compare_op1 = operands[1];
213: hppa_branch_type = CMP_DF;
214: DONE;
215: }")
216:
217: (define_insn ""
218: [(set (reg:CCFP 0)
219: (match_operator:CCFP 2 "comparison_operator"
220: [(match_operand:SF 0 "register_operand" "fxy")
221: (match_operand:SF 1 "register_operand" "fxy")]))]
222: ""
223: "fcmp,sgl,%Y2 %0,%1"
224: [(set_attr "type" "fpcc")])
225:
226: (define_insn ""
227: [(set (reg:CCFP 0)
228: (match_operator:CCFP 2 "comparison_operator"
229: [(match_operand:DF 0 "register_operand" "fxy")
230: (match_operand:DF 1 "register_operand" "fxy")]))]
231: ""
232: "fcmp,dbl,%Y2 %0,%1"
233: [(set_attr "type" "fpcc")])
234:
235: ;; scc insns.
236:
237: (define_insn ""
238: [(set (match_operand:SI 0 "register_operand" "=r")
239: (match_operator:CCFP 1 "comparison_operator" [(reg:CCFP 0)
240: (const_int 0)]))]
241: ""
242: "copy 0,%0\;ftest\;ldi 1,%0"
243: [(set_attr "type" "unary")
244: (set_attr "length" "3")])
245:
246: (define_expand "seq"
247: [(set (match_operand:SI 0 "register_operand" "")
248: (eq:CC (match_dup 1)
249: (match_dup 2)))]
250: ""
251: "
252: {
253: if (hppa_branch_type != CMP_SI)
254: {
255: emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
256: emit_insn (gen_scond_fp (EQ, operands[0]));
257: DONE;
258: }
259: /* set up operands from compare. */
260: operands[1] = hppa_compare_op0;
261: operands[2] = hppa_compare_op1;
262: /* fall through and generate default code */
263: }")
264:
265: (define_expand "sne"
266: [(set (match_operand:SI 0 "register_operand" "=r")
267: (ne:CC (match_dup 1)
268: (match_dup 2)))]
269: ""
270: "
271: {
272: if (hppa_branch_type != CMP_SI)
273: {
274: emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
275: emit_insn (gen_scond_fp (NE, operands[0]));
276: DONE;
277: }
278: operands[1] = hppa_compare_op0;
279: operands[2] = hppa_compare_op1;
280: }")
281:
282: (define_expand "slt"
283: [(set (match_operand:SI 0 "register_operand" "=r")
284: (lt:CC (match_dup 1)
285: (match_dup 2)))]
286: ""
287: "
288: {
289: if (hppa_branch_type != CMP_SI)
290: {
291: emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
292: emit_insn (gen_scond_fp (LT, operands[0]));
293: DONE;
294: }
295: operands[1] = hppa_compare_op0;
296: operands[2] = hppa_compare_op1;
297: }")
298:
299: (define_expand "sgt"
300: [(set (match_operand:SI 0 "register_operand" "=r")
301: (gt:CC (match_dup 1)
302: (match_dup 2)))]
303: ""
304: "
305: {
306: if (hppa_branch_type != CMP_SI)
307: {
308: emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
309: emit_insn (gen_scond_fp (GT, operands[0]));
310: DONE;
311: }
312: operands[1] = hppa_compare_op0;
313: operands[2] = hppa_compare_op1;
314: }")
315:
316: (define_expand "sle"
317: [(set (match_operand:SI 0 "register_operand" "=r")
318: (le:CC (match_dup 1)
319: (match_dup 2)))]
320: ""
321: "
322: {
323: if (hppa_branch_type != CMP_SI)
324: {
325: emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
326: emit_insn (gen_scond_fp (LE, operands[0]));
327: DONE;
328: }
329: operands[1] = hppa_compare_op0;
330: operands[2] = hppa_compare_op1;
331: }")
332:
333: (define_expand "sge"
334: [(set (match_operand:SI 0 "register_operand" "=r")
335: (ge:CC (match_dup 1)
336: (match_dup 2)))]
337: ""
338: "
339: {
340: if (hppa_branch_type != CMP_SI)
341: {
342: emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
343: emit_insn (gen_scond_fp (GE, operands[0]));
344: DONE;
345: }
346: operands[1] = hppa_compare_op0;
347: operands[2] = hppa_compare_op1;
348: }")
349:
350: (define_expand "sltu"
351: [(set (match_operand:SI 0 "register_operand" "=r")
352: (ltu:CC (match_dup 1)
353: (match_dup 2)))]
354: ""
355: "
356: {
357: if (hppa_branch_type != CMP_SI)
358: FAIL;
359: operands[1] = hppa_compare_op0;
360: operands[2] = hppa_compare_op1;
361: }")
362:
363: (define_expand "sgtu"
364: [(set (match_operand:SI 0 "register_operand" "=r")
365: (gtu:CC (match_dup 1)
366: (match_dup 2)))]
367: ""
368: "
369: {
370: if (hppa_branch_type != CMP_SI)
371: FAIL;
372: operands[1] = hppa_compare_op0;
373: operands[2] = hppa_compare_op1;
374: }")
375:
376: (define_expand "sleu"
377: [(set (match_operand:SI 0 "register_operand" "=r")
378: (leu:CC (match_dup 1)
379: (match_dup 2)))]
380: ""
381: "
382: {
383: if (hppa_branch_type != CMP_SI)
384: FAIL;
385: operands[1] = hppa_compare_op0;
386: operands[2] = hppa_compare_op1;
387: }")
388:
389: (define_expand "sgeu"
390: [(set (match_operand:SI 0 "register_operand" "=r")
391: (geu:CC (match_dup 1)
392: (match_dup 2)))]
393: ""
394: "
395: {
396: if (hppa_branch_type != CMP_SI)
397: FAIL;
398: operands[1] = hppa_compare_op0;
399: operands[2] = hppa_compare_op1;
400: }")
401:
402: ;; Instruction canonicalization puts immediate operands second, which
403: ;; is the reverse of what we want.
404:
405: (define_insn ""
406: [(set (match_operand:SI 0 "register_operand" "=r,r")
407: (match_operator:CC 3 "comparison_operator"
408: [(match_operand:SI 1 "register_operand" "r,r")
1.1.1.2 ! root 409: (match_operand:SI 2 "arith11_operand" "r,I")]))]
1.1 root 410: ""
411: "*
412: {
413: if (which_alternative == 0)
414: return \"comclr,%N3 %1,%2,%0\;ldi 1,%0\";
415: else
416: {
417: if (!(GET_CODE (operands[3]) == EQ || GET_CODE (operands[3]) == NE))
418: PUT_CODE (operands[3], reverse_relop (GET_CODE (operands[3])));
419: output_asm_insn (\"comiclr,%N3 %2,%1,%0\;ldi 1,%0\", operands);
420: return \"\";
421: }
422: }"
423: [(set_attr "type" "binary")
424: (set_attr "length" "2")])
425:
426: ;; Conditionals
427:
428: (define_expand "beq"
429: [(set (pc)
430: (if_then_else (eq (match_dup 1) (match_dup 2))
431: (label_ref (match_operand 0 "" ""))
432: (pc)))]
433: ""
434: "
435: {
436: if (hppa_branch_type != CMP_SI)
437: {
438: emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
439: emit_bcond_fp (NE, operands[0]);
440: DONE;
441: }
442: /* set up operands from compare. */
443: operands[1] = hppa_compare_op0;
444: operands[2] = hppa_compare_op1;
445: /* fall through and generate default code */
446: }")
447:
448: (define_expand "bne"
449: [(set (pc)
450: (if_then_else (ne (match_dup 1) (match_dup 2))
451: (label_ref (match_operand 0 "" ""))
452: (pc)))]
453: ""
454: "
455: {
456: if (hppa_branch_type != CMP_SI)
457: {
458: emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
459: emit_bcond_fp (NE, operands[0]);
460: DONE;
461: }
462: operands[1] = hppa_compare_op0;
463: operands[2] = hppa_compare_op1;
464: }")
465:
466: (define_expand "bgt"
467: [(set (pc)
468: (if_then_else (gt (match_dup 1) (match_dup 2))
469: (label_ref (match_operand 0 "" ""))
470: (pc)))]
471: ""
472: "
473: {
474: if (hppa_branch_type != CMP_SI)
475: {
476: emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
477: emit_bcond_fp (NE, operands[0]);
478: DONE;
479: }
480: operands[1] = hppa_compare_op0;
481: operands[2] = hppa_compare_op1;
482: }")
483:
484: (define_expand "blt"
485: [(set (pc)
486: (if_then_else (lt (match_dup 1) (match_dup 2))
487: (label_ref (match_operand 0 "" ""))
488: (pc)))]
489: ""
490: "
491: {
492: if (hppa_branch_type != CMP_SI)
493: {
494: emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
495: emit_bcond_fp (NE, operands[0]);
496: DONE;
497: }
498: operands[1] = hppa_compare_op0;
499: operands[2] = hppa_compare_op1;
500: }")
501:
502: (define_expand "bge"
503: [(set (pc)
504: (if_then_else (ge (match_dup 1) (match_dup 2))
505: (label_ref (match_operand 0 "" ""))
506: (pc)))]
507: ""
508: "
509: {
510: if (hppa_branch_type != CMP_SI)
511: {
512: emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
513: emit_bcond_fp (NE, operands[0]);
514: DONE;
515: }
516: operands[1] = hppa_compare_op0;
517: operands[2] = hppa_compare_op1;
518: }")
519:
520: (define_expand "ble"
521: [(set (pc)
522: (if_then_else (le (match_dup 1) (match_dup 2))
523: (label_ref (match_operand 0 "" ""))
524: (pc)))]
525: ""
526: "
527: {
528: if (hppa_branch_type != CMP_SI)
529: {
530: emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
531: emit_bcond_fp (NE, operands[0]);
532: DONE;
533: }
534: operands[1] = hppa_compare_op0;
535: operands[2] = hppa_compare_op1;
536: }")
537:
538: (define_expand "bgtu"
539: [(set (pc)
540: (if_then_else (gtu (match_dup 1) (match_dup 2))
541: (label_ref (match_operand 0 "" ""))
542: (pc)))]
543: ""
544: "
545: {
546: if (hppa_branch_type != CMP_SI)
547: FAIL;
548: operands[1] = hppa_compare_op0;
549: operands[2] = hppa_compare_op1;
550: }")
551:
552: (define_expand "bltu"
553: [(set (pc)
554: (if_then_else (ltu (match_dup 1) (match_dup 2))
555: (label_ref (match_operand 0 "" ""))
556: (pc)))]
557: ""
558: "
559: {
560: if (hppa_branch_type != CMP_SI)
561: FAIL;
562: operands[1] = hppa_compare_op0;
563: operands[2] = hppa_compare_op1;
564: }")
565:
566: (define_expand "bgeu"
567: [(set (pc)
568: (if_then_else (geu (match_dup 1) (match_dup 2))
569: (label_ref (match_operand 0 "" ""))
570: (pc)))]
571: ""
572: "
573: {
574: if (hppa_branch_type != CMP_SI)
575: FAIL;
576: operands[1] = hppa_compare_op0;
577: operands[2] = hppa_compare_op1;
578: }")
579:
580: (define_expand "bleu"
581: [(set (pc)
582: (if_then_else (leu (match_dup 1) (match_dup 2))
583: (label_ref (match_operand 0 "" ""))
584: (pc)))]
585: ""
586: "
587: {
588: if (hppa_branch_type != CMP_SI)
589: FAIL;
590: operands[1] = hppa_compare_op0;
591: operands[2] = hppa_compare_op1;
592: }")
593:
594: ;; Match the branch patterns.
595:
596: (define_insn ""
597: [(set (pc)
598: (if_then_else
599: (match_operator 3 "comparison_operator"
600: [(match_operand:SI 1 "register_operand" "r,r")
601: (match_operand:SI 2 "arith5_operand" "r,L")])
602: (label_ref (match_operand 0 "" ""))
603: (pc)))]
604: ""
605: "*
606: {
607: if (which_alternative == 0)
608: return (get_attr_length (insn) == 1
609: ? \"comb,%C3 %1,%2,%0%#\" : \"comclr,%N3 %1,%2,0\;bl %0,0%#\");
610: {
611: enum rtx_code comp_code = GET_CODE (operands[3]);
612: if (!(comp_code == EQ || comp_code == NE))
613: PUT_CODE (operands[3], reverse_relop (comp_code));
614: if (get_attr_length (insn) == 1)
615: output_asm_insn (\"comib,%C3 %2,%1,%0%#\", operands);
616: else
617: output_asm_insn (\"comiclr,%N3 %2,%1,0\;bl %0,0%#\", operands);
618: return \"\";
619: }
620: }"
621: [(set_attr "type" "cbranch")
622: (set (attr "length") (if_then_else (lt (abs (minus (match_dup 0)
623: (plus (pc) (const_int 2))))
624: (const_int 1023))
625: (const_int 1)
626: (const_int 2)))])
627:
628: ;; Match the negated branch.
629:
630: (define_insn ""
631: [(set (pc)
632: (if_then_else
633: (match_operator 3 "comparison_operator"
634: [(match_operand:SI 1 "register_operand" "r,r")
635: (match_operand:SI 2 "arith5_operand" "r,L")])
636: (pc)
637: (label_ref (match_operand 0 "" ""))))]
638: ""
639: "*
640: {
641: if (which_alternative == 0)
642: return (get_attr_length (insn) == 1
643: ? \"comb,%N3 %1,%2,%0%#\" : \"comclr,%C3 %1,%2,0\;bl %0,0%#\");
644: {
645: enum rtx_code comp_code = GET_CODE (operands[3]);
646: if (!(comp_code == EQ || comp_code == NE))
647: PUT_CODE (operands[3], reverse_relop (comp_code));
648: if (get_attr_length (insn) == 1)
649: output_asm_insn (\"comib,%N3 %2,%1,%0%#\", operands);
650: else
651: output_asm_insn (\"comiclr,%C3 %2,%1,0%#\;bl %0,0%#\", operands);
652: return \"\";
653: }
654: }"
655: [(set_attr "type" "cbranch")
656: (set (attr "length") (if_then_else (lt (abs (minus (match_dup 0)
657: (plus (pc) (const_int 2))))
658: (const_int 1023))
659: (const_int 1)
660: (const_int 2)))])
661:
662: ;; Floating point branches
663:
664: (define_insn ""
665: [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
666: (label_ref (match_operand 0 "" ""))
667: (pc)))]
668: ""
669: "ftest\;bl%* %0,0"
670: [(set_attr "type" "cbranch")
671: (set_attr "length" "2")])
672:
673: (define_insn ""
674: [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
675: (pc)
676: (label_ref (match_operand 0 "" ""))))]
677: ""
678: "ftest\;add,tr 0,0,0\;bl%* %0,0"
679: [(set_attr "type" "cbranch")
680: (set_attr "length" "3")])
681:
682: ;; Move instructions
683:
684: (define_expand "movsi"
685: [(set (match_operand:SI 0 "general_operand" "")
686: (match_operand:SI 1 "general_operand" ""))]
687: ""
688: "
689: {
690: if (emit_move_sequence (operands, SImode))
691: DONE;
692: }")
693:
694: ;; Moves to and from the shift register.
695:
696: (define_insn ""
697: [(set (reg:SI 112)
698: (match_operand:SI 0 "register_operand" "r"))]
699: ""
700: "mtsar %0"
701: [(set_attr "type" "move")])
702:
703: (define_insn ""
704: [(set (match_operand:SI 0 "register_operand" "=r")
705: (reg:SI 112))]
706: ""
707: "mfctl 11,%0"
708: [(set_attr "type" "move")])
709:
710: (define_insn ""
711: [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand" "=r,r,Q,!r,!*f*x*y,!*f")
712: (match_operand:SI 1 "move_operand" "rM,Q,rM,!*f*x*y,!r,!*f"))]
713: ""
714: "@
715: copy %r1,%0
716: ldw%M1 %1,%0
717: stw%M0 %r1,%0
718: fstws %1,-16(30)\;ldw -16(30),%0
719: stw %1,-16(30)\;fldws -16(30),%0
720: fcpy,sgl %1,%0"
721: [(set_attr "type" "move,load,store,move,move,fpalu")
722: (set_attr "length" "1,1,1,2,2,1")])
723:
724: ;; For pic
725: (define_insn ""
726: [(set (match_operand:SI 0 "register_operand" "=r")
727: (match_operand:SI 1 "pic_operand" "i"))
728: (clobber (match_scratch:SI 2 "=a"))]
729: ""
730: "*
731: {
732: rtx label_rtx = gen_label_rtx ();
733: rtx xoperands[3];
734: extern FILE *asm_out_file;
735:
736: xoperands[0] = operands[0];
737: xoperands[1] = operands[1];
738: xoperands[2] = label_rtx;
739: output_asm_insn (\"bl .+8,%0\;addil L'%1-%2,%0\", xoperands);
740: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", CODE_LABEL_NUMBER (label_rtx));
741: output_asm_insn (\"ldo R'%1(1),%0\", xoperands);
742: return \"\";
743: }
744: "
745: [(set_attr "type" "multi")
746: (set_attr "length" "3")])
747:
748: (define_insn ""
749: [(set (match_operand:SI 0 "register_operand" "=r")
750: (match_operand:SI 1 "immediate_operand" "n"))]
751: "(GET_CODE (operands[1]) == CONST_INT) &&
752: (INT_14_BITS (operands[1]) || !(INTVAL (operands[1]) & 0x7ff))"
753: "*
754: {
755: if (INT_14_BITS (operands[1]))
756: return \"ldo %1(0),%0\";
757: else
758: return \"ldil L'%1,%0\";
759: }"
760: [(set_attr "type" "move")
761: (set_attr "length" "1")])
762:
763: (define_insn ""
764: [(set (match_operand:SI 0 "register_operand" "=a")
765: (plus:SI (match_operand:SI 1 "register_operand" "r")
766: (high:SI (match_operand 2 "" ""))))]
767: ""
768: "addil L'%G2,%1"
769: [(set_attr "type" "binary")
770: (set_attr "length" "1")])
771:
772: (define_insn ""
773: [(set (match_operand:SI 0 "register_operand" "=r")
774: (high:SI (match_operand 1 "" "")))]
775: "check_pic (1)"
776: "ldil L'%G1,%0"
777: [(set_attr "type" "move")
778: (set_attr "length" "1")])
779:
780: (define_insn ""
781: [(set (match_operand:HI 0 "register_operand" "=r")
782: (high:HI (match_operand 1 "" "")))]
783: "check_pic (1)"
784: "ldil L'%G1,%0"
785: [(set_attr "type" "move")
786: (set_attr "length" "1")])
787:
788: (define_insn ""
789: [(set (match_operand:SI 0 "register_operand" "=r")
790: (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
791: (match_operand:SI 2 "immediate_operand" "in")))]
792: ""
793: "ldo R'%G2(%1),%0"
794: ;; Need to set length for this arith insn because operand2
795: ;; is not an "arith_operand".
796: [(set_attr "length" "1")])
797:
798: ;;; Experimental
799:
800: (define_insn ""
1.1.1.2 ! root 801: [(set (match_operand:SI 0 "fp_reg_operand" "*f*x*y")
1.1 root 802: (match_operand:SI 1 "short_memory_operand" "T"))]
803: ""
804: "fldws%F1 %1,%0"
805: [(set_attr "type" "fpload")
806: (set_attr "length" "1")])
807:
808: (define_insn ""
809: [(set (match_operand:SI 0 "short_memory_operand" "T")
1.1.1.2 ! root 810: (match_operand:SI 1 "fp_reg_operand" "*f*x*y"))]
1.1 root 811: ""
812: "fstws%F0 %1,%0"
813: [(set_attr "type" "fpstore")
814: (set_attr "length" "1")])
815:
816: (define_expand "movhi"
817: [(set (match_operand:HI 0 "general_operand" "")
818: (match_operand:HI 1 "general_operand" ""))]
819: ""
820: "
821: {
822: if (emit_move_sequence (operands, HImode))
823: DONE;
824: }")
825:
826: (define_insn ""
827: [(set (match_operand:HI 0 "reg_or_nonsymb_mem_operand" "=r,r,Q")
828: (match_operand:HI 1 "move_operand" "rM,Q,rM"))]
829: ""
830: "@
831: copy %r1,%0
832: ldh%M1 %1,%0
833: sth%M0 %r1,%0"
834: [(set_attr "type" "move,load,store")
835: (set_attr "length" "1,1,1")])
836:
837: (define_insn ""
838: [(set (match_operand:HI 0 "register_operand" "=r")
839: (match_operand:HI 1 "immediate_operand" "n"))]
840: "(GET_CODE (operands[1]) == CONST_INT) &&
841: (INT_14_BITS (operands[1]) || !(INTVAL (operands[1]) & 0x7ff))"
842: "*
843: {
844: if (INT_14_BITS (operands[1]))
845: return \"ldo %1(0),%0\";
846: else
847: return \"ldil L'%1,%0\";
848: }"
849: [(set_attr "type" "move")
850: (set_attr "length" "1")])
851:
852: (define_insn ""
853: [(set (match_operand:HI 0 "register_operand" "=r")
854: (lo_sum:HI (match_operand:HI 1 "register_operand" "r")
855: (match_operand 2 "immediate_operand" "in")))]
856: ""
857: "ldo R'%G2(%1),%0"
858: [(set_attr "length" "1")])
859:
860: (define_expand "movqi"
861: [(set (match_operand:QI 0 "general_operand" "")
862: (match_operand:QI 1 "general_operand" ""))]
863: ""
864: "
865: {
866: if (emit_move_sequence (operands, QImode))
867: DONE;
868: }")
869:
870: (define_insn ""
871: [(set (match_operand:QI 0 "reg_or_nonsymb_mem_operand" "=r,r,Q")
872: (match_operand:QI 1 "move_operand" "rM,Q,rM"))]
873: ""
874: "@
875: copy %r1,%0
876: ldb%M1 %1,%0
877: stb%M0 %r1,%0"
878: [(set_attr "type" "move,load,store")
879: (set_attr "length" "1,1,1")])
880:
881: (define_insn ""
882: [(set (match_operand:QI 0 "register_operand" "=r")
883: (match_operand:QI 1 "immediate_operand" "J"))]
884: ""
885: "ldo %1(0),%0"
886: [(set_attr "type" "move")
887: (set_attr "length" "1")])
888:
889: (define_insn ""
890: [(set (match_operand:QI 0 "register_operand" "=r")
891: (subreg:QI (lo_sum:SI (match_operand:QI 1 "register_operand" "r")
892: (match_operand 2 "immediate_operand" "in")) 0))]
893: ""
894: "ldo R'%G2(%1),%0"
895: [(set_attr "length" "1")])
896:
897: ;; The definition of this insn does not really explain what it does,
898: ;; but it should suffice
899: ;; that anything generated as this insn will be recognized as one
900: ;; and that it will not successfully combine with anything.
901: (define_expand "movstrsi"
902: [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" ""))
903: (mem:BLK (match_operand:BLK 1 "general_operand" "")))
904: (clobber (match_dup 0))
905: (clobber (match_dup 1))
906: (clobber (match_scratch:SI 4 ""))
1.1.1.2 ! root 907: (clobber (match_scratch:SI 5 ""))
! 908: (use (match_operand:SI 2 "arith_operand" ""))
! 909: (use (match_operand:SI 3 "const_int_operand" ""))])]
1.1 root 910: ""
911: "
912: {
1.1.1.2 ! root 913: /* If the blocks are not word-aligned and rather big (>16 items),
! 914: or the size is indeterminate, don't inline the copy code. A
! 915: procedure call is better since it can check the alignment at
! 916: runtime and make the optimal decisions. */
! 917: if (INTVAL (operands[3]) != 4
! 918: && (GET_CODE (operands[2]) != CONST_INT
! 919: || (INTVAL (operands[2]) / INTVAL (operands[3]) > 16)))
! 920: FAIL;
! 921:
1.1 root 922: operands[0] = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
923: operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
924: operands[2] = force_not_mem (operands[2]);
925: }")
926:
1.1.1.2 ! root 927: ;; The operand constraints are written like this to support both compile-time
! 928: ;; and run-time determined byte count. If the count is run-time determined,
! 929: ;; the register with the byte count is clobbered by the copying code, and
! 930: ;; therefore it is forced to operand 2. If the count is compile-time
! 931: ;; determined, we need two scratch registers for the unrolled code.
1.1 root 932: (define_insn ""
1.1.1.2 ! root 933: [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
! 934: (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
1.1 root 935: (clobber (match_dup 0))
936: (clobber (match_dup 1))
1.1.1.2 ! root 937: (clobber (match_scratch:SI 2 "=r,r")) ;loop cnt/item tmp
! 938: (clobber (match_scratch:SI 3 "=r,r")) ;item tmp
! 939: (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
! 940: (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
1.1 root 941: ""
1.1.1.2 ! root 942: "* return output_block_move (operands, !which_alternative);"
1.1 root 943: [(set_attr "type" "multi")])
944:
945: ;; Floating point move insns
946:
947: ;; This pattern forces (set (reg:DF ...) (const_double ...))
948: ;; to be reloaded by putting the constant into memory.
949: ;; It must come before the more general movdf pattern.
950: (define_insn ""
951: [(set (match_operand:DF 0 "general_operand" "=?r,r,f")
952: (match_operand:DF 1 "" "?E,G,m"))]
953: "GET_CODE (operands[1]) == CONST_DOUBLE"
954: "*
955: {
956: switch (which_alternative)
957: {
958: case 0:
959: return output_move_double (operands);
960: case 1:
961: return \"copy 0,%0\;copy 0,%R0\";
962: case 2:
963: return output_fp_move_double (operands);
964: }
965: }"
966: [(set_attr "type" "load,move,fpload")
967: (set_attr "length" "3,2,3")])
968:
969: (define_expand "movdf"
970: [(set (match_operand:DF 0 "general_operand" "")
971: (match_operand:DF 1 "general_operand" ""))]
972: ""
973: "
974: {
975: if (emit_move_sequence (operands, DFmode))
976: DONE;
977: }")
978:
979: (define_insn ""
980: [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
981: "=fxy,r,Q,Q,fxy,&r,?fxy,?r")
982: (match_operand:DF 1 "reg_or_nonsymb_mem_operand"
983: "fxy,r,fxy,r,Q,Q,r,fxy"))]
984: ""
985: "*
986: {
987: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
988: return output_fp_move_double (operands);
989: return output_move_double (operands);
990: }"
991: [(set_attr "type" "fpalu,move,fpstore,store,fpload,load,multi,multi")
992: (set_attr "length" "1,2,1,2,1,2,3,3")])
993:
994: (define_expand "movdi"
995: [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
996: (match_operand:DI 1 "general_operand" ""))]
997: ""
998: "
999: {
1000: if (emit_move_sequence (operands, DImode))
1001: DONE;
1002: }")
1003:
1004: (define_insn ""
1005: [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
1006: "=r,Q,&r,&r,*f*x*y,*f*x*y,*f*x*y,r,Q")
1.1.1.2 ! root 1007: (match_operand:DI 1 "general_operand"
! 1008: "r,r,Q,i,r,*f*x*y,Q,*f*x*y,*f*x*y"))]
1.1 root 1009: ""
1010: "*
1011: {
1012: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
1013: return output_fp_move_double (operands);
1014: return output_move_double (operands);
1015: }"
1016: [(set_attr "type" "move,store,load,misc,multi,fpalu,fpload,multi,fpstore")
1017: (set_attr "length" "2,3,3,3,3,2,3,3,3")])
1018:
1019: (define_expand "movsf"
1020: [(set (match_operand:SF 0 "general_operand" "")
1021: (match_operand:SF 1 "general_operand" ""))]
1022: ""
1023: "
1024: {
1025: if (emit_move_sequence (operands, SFmode))
1026: DONE;
1027: }")
1028:
1029: (define_insn ""
1030: [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand"
1031: "=fxy,r,r,fxy,fxy,r,Q,Q")
1032: (match_operand:SF 1 "reg_or_nonsymb_mem_operand"
1033: "fxy,r,!fxy,!r,Q,Q,fxy,r"))]
1034: ""
1035: "@
1036: fcpy %1,%0
1037: copy %1,%0
1038: fstws %1,-16(0,30)\;ldw -16(0,30),%0
1039: stw %r1,-16(0,30)\;fldws -16(0,30),%0
1040: fldws%F1 %1,%0
1041: ldw%M1 %1,%0
1042: fstws%F0 %r1,%0
1043: stw%M0 %r1,%0"
1044: [(set_attr "type" "fpalu,move,multi,multi,fpload,load,fpstore,store")
1045: (set_attr "length" "1,1,2,2,1,1,1,1")])
1046:
1047:
1048: ;;- zero extension instructions
1049:
1050: ;; Note that the one starting from HImode comes before those for QImode
1051: ;; so that a constant operand will match HImode, not QImode.
1052:
1053: (define_expand "zero_extendhisi2"
1054: [(set (match_operand:SI 0 "register_operand" "")
1055: (zero_extend:SI
1056: (match_operand:HI 1 "general_operand" "")))]
1057: ""
1058: "
1059: {
1060: if (GET_CODE (operand1) == MEM
1061: && symbolic_operand (XEXP (operand1, 0), Pmode))
1062: {
1063: rtx temp = copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode,
1064: XEXP (operand1, 0)));
1065: operands[1] = gen_rtx (MEM, HImode,
1066: gen_rtx (LO_SUM, Pmode,
1067: temp, XEXP (operand1, 0)));
1068: }
1069: }")
1070:
1071: (define_insn ""
1072: [(set (match_operand:SI 0 "register_operand" "=r,r")
1073: (zero_extend:SI
1074: (match_operand:HI 1 "reg_or_nonsymb_mem_operand" "r,Q")))]
1075: ""
1076: "@
1077: extru %1,31,16,%0
1078: ldh%M1 %1,%0"
1079: [(set_attr "type" "unary,load")])
1080:
1081: (define_expand "zero_extendqihi2"
1082: [(set (match_operand:HI 0 "register_operand" "")
1083: (zero_extend:HI
1084: (match_operand:QI 1 "general_operand" "")))]
1085: ""
1086: "
1087: {
1088: if (GET_CODE (operand1) == MEM
1089: && symbolic_operand (XEXP (operand1, 0), Pmode))
1090: {
1091: rtx temp = copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode,
1092: XEXP (operand1, 0)));
1093: operands[1] = gen_rtx (MEM, QImode,
1094: gen_rtx (LO_SUM, Pmode,
1095: temp, XEXP (operand1, 0)));
1096: }
1097: }")
1098:
1099: (define_insn ""
1100: [(set (match_operand:HI 0 "register_operand" "=r,r")
1101: (zero_extend:HI
1102: (match_operand:QI 1 "reg_or_nonsymb_mem_operand" "r,Q")))]
1103: ""
1104: "@
1105: extru %1,31,8,%0
1106: ldb%M1 %1,%0"
1107: [(set_attr "type" "unary,load")
1108: (set_attr "length" "1")])
1109:
1110: (define_expand "zero_extendqisi2"
1111: [(set (match_operand:SI 0 "register_operand" "")
1112: (zero_extend:SI
1113: (match_operand:QI 1 "general_operand" "")))]
1114: ""
1115: "
1116: {
1117: if (GET_CODE (operand1) == MEM
1118: && symbolic_operand (XEXP (operand1, 0), Pmode))
1119: {
1120: rtx temp = copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode,
1121: XEXP (operand1, 0)));
1122: operand1 = gen_rtx (MEM, QImode,
1123: gen_rtx (LO_SUM, Pmode,
1124: temp, XEXP (operand1, 0)));
1125: emit_insn (gen_rtx (SET, VOIDmode, operand0,
1126: gen_rtx (ZERO_EXTEND, SImode, operand1)));
1127: DONE;
1128: }
1129: }")
1130:
1131: (define_insn ""
1132: [(set (match_operand:SI 0 "register_operand" "=r,r")
1133: (zero_extend:SI
1134: (match_operand:QI 1 "reg_or_nonsymb_mem_operand" "r,Q")))]
1135: ""
1136: "@
1137: extru %1,31,8,%0
1138: ldb%M1 %1,%0"
1139: [(set_attr "type" "unary,load")
1140: (set_attr "length" "1")])
1141:
1142: ;;- sign extension instructions
1143: ;; Note that the one starting from HImode comes before those for QImode
1144: ;; so that a constant operand will match HImode, not QImode.
1145:
1146: (define_insn "extendhisi2"
1147: [(set (match_operand:SI 0 "register_operand" "=r")
1148: (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1149: ""
1150: "extrs %1,31,16,%0"
1151: [(set_attr "type" "unary")])
1152:
1153: (define_insn "extendqihi2"
1154: [(set (match_operand:HI 0 "register_operand" "=r")
1155: (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1156: ""
1157: "extrs %1,31,8,%0"
1158: [(set_attr "type" "unary")])
1159:
1160: (define_insn "extendqisi2"
1161: [(set (match_operand:SI 0 "register_operand" "=r")
1162: (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1163: ""
1164: "extrs %1,31,8,%0"
1165: [(set_attr "type" "unary")])
1166:
1167: ;; Conversions between float and double.
1168:
1169: (define_insn "extendsfdf2"
1170: [(set (match_operand:DF 0 "register_operand" "=fxy")
1171: (float_extend:DF
1172: (match_operand:SF 1 "register_operand" "fxy")))]
1173: ""
1174: "fcnvff,sgl,dbl %1,%0"
1175: [(set_attr "type" "fpalu")])
1176:
1177: (define_insn "truncdfsf2"
1178: [(set (match_operand:SF 0 "register_operand" "=fxy")
1179: (float_truncate:SF
1180: (match_operand:DF 1 "register_operand" "fxy")))]
1181: ""
1182: "fcnvff,dbl,sgl %1,%0"
1183: [(set_attr "type" "fpalu")])
1184:
1185: ;; Conversion between fixed point and floating point.
1186: ;; Note that among the fix-to-float insns
1187: ;; the ones that start with SImode come first.
1188: ;; That is so that an operand that is a CONST_INT
1189: ;; (and therefore lacks a specific machine mode).
1190: ;; will be recognized as SImode (which is always valid)
1191: ;; rather than as QImode or HImode.
1192:
1193: ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
1194: ;; to be reloaded by putting the constant into memory.
1195: ;; It must come before the more general floatsisf2 pattern.
1196: (define_insn ""
1197: [(set (match_operand:SF 0 "general_operand" "=fxy")
1198: (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
1199: ""
1200: "* return output_floatsisf2 (operands);"
1201: [(set_attr "type" "fpalu")
1202: (set_attr "length" "3")])
1203:
1204: (define_insn "floatsisf2"
1205: [(set (match_operand:SF 0 "general_operand" "=fxy")
1206: (float:SF (match_operand:SI 1 "register_operand" "fxyr")))]
1207: ""
1208: "* return output_floatsisf2 (operands);"
1209: [(set_attr "type" "fpalu")
1210: (set_attr "length" "3")])
1211:
1212: ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
1213: ;; to be reloaded by putting the constant into memory.
1214: ;; It must come before the more general floatsidf2 pattern.
1215: (define_insn ""
1216: [(set (match_operand:DF 0 "general_operand" "=fxy")
1217: (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
1218: ""
1219: "* return output_floatsidf2 (operands);"
1220: [(set_attr "type" "fpalu")
1221: (set_attr "length" "3")])
1222:
1223: (define_insn "floatsidf2"
1224: [(set (match_operand:DF 0 "general_operand" "=fxy")
1225: (float:DF (match_operand:SI 1 "register_operand" "fxyr")))]
1226: ""
1227: "* return output_floatsidf2 (operands);"
1228: [(set_attr "type" "fpalu")
1229: (set_attr "length" "3")])
1230:
1231: ;; Convert a float to an actual integer.
1232: ;; Truncation is performed as part of the conversion.
1233:
1234: (define_insn "fix_truncsfsi2"
1.1.1.2 ! root 1235: [(set (match_operand:SI 0 "register_operand" "=r,fxy")
! 1236: (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "fxy,fxy"))))
! 1237: (clobber (match_scratch:SI 2 "=&fxy,X"))]
1.1 root 1238: ""
1.1.1.2 ! root 1239: "@
! 1240: fcnvfxt,sgl,sgl %1,%2\;fstws %2,-16(30)\;ldw -16(30),%0
! 1241: fcnvfxt,sgl,sgl %1,%0"
! 1242: [(set_attr "type" "fpalu,fpalu")
! 1243: (set_attr "length" "3,1")])
1.1 root 1244:
1245: (define_insn "fix_truncdfsi2"
1.1.1.2 ! root 1246: [(set (match_operand:SI 0 "register_operand" "=r,fxy")
! 1247: (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "fxy,fxy"))))
! 1248: (clobber (match_scratch:SI 2 "=&fxy,X"))]
1.1 root 1249: ""
1.1.1.2 ! root 1250: "@
! 1251: fcnvfxt,dbl,sgl %1,%2\;fstws %2,-16(30)\;ldw -16(30),%0
! 1252: fcnvfxt,dbl,sgl %1,%0"
! 1253: [(set_attr "type" "fpalu,fpalu")
! 1254: (set_attr "length" "3,1")])
1.1 root 1255:
1256:
1257: ;;- arithmetic instructions
1258:
1259: (define_insn "adddi3"
1260: [(set (match_operand:DI 0 "register_operand" "=r")
1261: (plus:DI (match_operand:DI 1 "register_operand" "%r")
1262: (match_operand:DI 2 "register_operand" "r")))]
1263: ""
1264: "add %R1,%R2,%R0\;addc %1,%2,%0"
1265: [(set_attr "type" "binary")
1266: (set_attr "length" "2")])
1267:
1268: (define_insn "addsi3"
1269: [(set (match_operand:SI 0 "register_operand" "=r,r")
1.1.1.2 ! root 1270: (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
1.1 root 1271: (match_operand:SI 2 "arith_operand" "r,J")))]
1272: ""
1273: "@
1274: add %1,%2,%0
1275: ldo %2(%1),%0")
1276:
1277: (define_insn "subdi3"
1278: [(set (match_operand:DI 0 "register_operand" "=r")
1279: (minus:DI (match_operand:DI 1 "register_operand" "r")
1280: (match_operand:DI 2 "register_operand" "r")))]
1281: ""
1282: "sub %R1,%R2,%R0\;subb %1,%2,%0"
1283: [(set_attr "length" "2")])
1284:
1.1.1.2 ! root 1285: ;(define_insn "subsi3"
! 1286: ; [(set (match_operand:SI 0 "register_operand" "=r,r,r")
! 1287: ; (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,r")
! 1288: ; (match_operand:SI 2 "arith_operand" "r,r,J")))]
! 1289: ; ""
! 1290: ; "@
! 1291: ; sub %1,%2,%0
! 1292: ; subi %1,%2,%0
! 1293: ; ldo %n2(%1),%0")
! 1294:
1.1 root 1295: (define_insn "subsi3"
1296: [(set (match_operand:SI 0 "register_operand" "=r,r")
1.1.1.2 ! root 1297: (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
! 1298: (match_operand:SI 2 "register_operand" "r,r")))]
1.1 root 1299: ""
1300: "@
1301: sub %1,%2,%0
1.1.1.2 ! root 1302: subi %1,%2,%0")
1.1 root 1303:
1.1.1.2 ! root 1304: ;; The mulsi3 insns set up registers for the millicode call.
1.1 root 1305:
1306: (define_expand "mulsi3"
1307: [(set (reg:SI 26) (match_operand:SI 1 "general_operand" ""))
1308: (set (reg:SI 25) (match_operand:SI 2 "general_operand" ""))
1309: (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
1310: (clobber (match_scratch:SI 3 ""))
1311: (clobber (reg:SI 26))
1312: (clobber (reg:SI 25))
1313: (clobber (reg:SI 31))])
1314: (set (match_operand:SI 0 "register_operand" "") (reg:SI 29))]
1315: ""
1.1.1.2 ! root 1316: "")
1.1 root 1317:
1318: (define_insn ""
1319: [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
1320: (clobber (match_scratch:SI 0 "=a"))
1321: (clobber (reg:SI 26))
1322: (clobber (reg:SI 25))
1323: (clobber (reg:SI 31))]
1324: ""
1325: "* return output_mul_insn (0);"
1326: [(set_attr "type" "milli")])
1327:
1328: ;;; Division and mod.
1329:
1330: (define_expand "divsi3"
1331: [(set (reg:SI 26) (match_operand:SI 1 "general_operand" ""))
1332: (set (reg:SI 25) (match_operand:SI 2 "general_operand" ""))
1333: (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
1334: (clobber (match_scratch:SI 3 ""))
1335: (clobber (reg:SI 26))
1336: (clobber (reg:SI 25))
1337: (clobber (reg:SI 31))])
1.1.1.2 ! root 1338: (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
1.1 root 1339: ""
1340: "
1341: {
1342: if (!(GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const(operands, 0)))
1343: {
1344: emit_move_insn (gen_rtx (REG, SImode, 26), operands[1]);
1345: emit_move_insn (gen_rtx (REG, SImode, 25), operands[2]);
1346: emit
1347: (gen_rtx
1348: (PARALLEL, VOIDmode,
1349: gen_rtvec (5, gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 29),
1350: gen_rtx (DIV, SImode,
1351: gen_rtx (REG, SImode, 26),
1352: gen_rtx (REG, SImode, 25))),
1353: gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)),
1354: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 26)),
1355: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 25)),
1356: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 31)))));
1357: emit_move_insn (operands[0], gen_rtx (REG, SImode, 29));
1358: }
1359: DONE;
1360: }")
1361:
1362: (define_insn ""
1363: [(set (reg:SI 29)
1364: (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
1365: (clobber (match_scratch:SI 1 "=a"))
1366: (clobber (reg:SI 26))
1367: (clobber (reg:SI 25))
1368: (clobber (reg:SI 31))]
1369: ""
1370: "*
1371: return output_div_insn (operands, 0);"
1372: [(set_attr "type" "milli")])
1373:
1374: (define_expand "udivsi3"
1375: [(set (reg:SI 26) (match_operand:SI 1 "general_operand" ""))
1376: (set (reg:SI 25) (match_operand:SI 2 "general_operand" ""))
1377: (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
1378: (clobber (match_scratch:SI 3 ""))
1379: (clobber (reg:SI 26))
1380: (clobber (reg:SI 25))
1381: (clobber (reg:SI 31))])
1.1.1.2 ! root 1382: (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
1.1 root 1383: ""
1384: "
1385: {
1386: if (!(GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const(operands, 1)))
1387: {
1388: emit_move_insn (gen_rtx (REG, SImode, 26), operands[1]);
1389: emit_move_insn (gen_rtx (REG, SImode, 25), operands[2]);
1390: emit
1391: (gen_rtx
1392: (PARALLEL, VOIDmode,
1393: gen_rtvec (5, gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 29),
1394: gen_rtx (UDIV, SImode,
1395: gen_rtx (REG, SImode, 26),
1396: gen_rtx (REG, SImode, 25))),
1397: gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)),
1398: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 26)),
1399: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 25)),
1400: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 31)))));
1401: emit_move_insn (operands[0], gen_rtx (REG, SImode, 29));
1402: }
1403: DONE;
1404: }")
1405:
1406: (define_insn ""
1407: [(set (reg:SI 29)
1408: (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
1409: (clobber (match_scratch:SI 1 "=a"))
1410: (clobber (reg:SI 26))
1411: (clobber (reg:SI 25))
1412: (clobber (reg:SI 31))]
1413: ""
1414: "*
1415: return output_div_insn (operands, 1);"
1416: [(set_attr "type" "milli")])
1417:
1418: (define_expand "modsi3"
1419: [(set (reg:SI 26) (match_operand:SI 1 "general_operand" ""))
1420: (set (reg:SI 25) (match_operand:SI 2 "general_operand" ""))
1421: (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
1422: (clobber (match_scratch:SI 3 ""))
1423: (clobber (reg:SI 26))
1424: (clobber (reg:SI 25))
1425: (clobber (reg:SI 31))])
1426: (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
1427: ""
1428: "
1429: {
1430: emit_move_insn (gen_rtx (REG, SImode, 26), operands[1]);
1431: emit_move_insn (gen_rtx (REG, SImode, 25), operands[2]);
1432: emit
1433: (gen_rtx
1434: (PARALLEL, VOIDmode,
1435: gen_rtvec (5, gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 29),
1436: gen_rtx (MOD, SImode,
1437: gen_rtx (REG, SImode, 26),
1438: gen_rtx (REG, SImode, 25))),
1439: gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)),
1440: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 26)),
1441: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 25)),
1442: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 31)))));
1443: emit_move_insn (operands[0], gen_rtx (REG, SImode, 29));
1444: DONE;
1445: }")
1446:
1447: (define_insn ""
1448: [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
1449: (clobber (match_scratch:SI 0 "=a"))
1450: (clobber (reg:SI 26))
1451: (clobber (reg:SI 25))
1452: (clobber (reg:SI 31))]
1453: ""
1454: "*
1455: return output_mod_insn (0);"
1456: [(set_attr "type" "milli")])
1457:
1458: (define_expand "umodsi3"
1459: [(set (reg:SI 26) (match_operand:SI 1 "general_operand" ""))
1460: (set (reg:SI 25) (match_operand:SI 2 "general_operand" ""))
1461: (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
1462: (clobber (match_scratch:SI 3 ""))
1463: (clobber (reg:SI 26))
1464: (clobber (reg:SI 25))
1465: (clobber (reg:SI 31))])
1466: (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
1467: ""
1468: "
1469: {
1470: emit_move_insn (gen_rtx (REG, SImode, 26), operands[1]);
1471: emit_move_insn (gen_rtx (REG, SImode, 25), operands[2]);
1472: emit
1473: (gen_rtx
1474: (PARALLEL, VOIDmode,
1475: gen_rtvec (5, gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 29),
1476: gen_rtx (UMOD, SImode,
1477: gen_rtx (REG, SImode, 26),
1478: gen_rtx (REG, SImode, 25))),
1479: gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)),
1480: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 26)),
1481: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 25)),
1482: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 31)))));
1483: emit_move_insn (operands[0], gen_rtx (REG, SImode, 29));
1484: DONE;
1485: }")
1486:
1487: (define_insn ""
1488: [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
1489: (clobber (match_scratch:SI 0 "=a"))
1490: (clobber (reg:SI 26))
1491: (clobber (reg:SI 25))
1492: (clobber (reg:SI 31))]
1493: ""
1494: "*
1495: return output_mod_insn (1);"
1496: [(set_attr "type" "milli")])
1497:
1498: ;;- and instructions
1499: ;; We define DImode `and` so with DImode `not` we can get
1500: ;; DImode `andn`. Other combinations are possible.
1501:
1502: (define_expand "anddi3"
1503: [(set (match_operand:DI 0 "register_operand" "")
1504: (and:DI (match_operand:DI 1 "arith_double_operand" "")
1505: (match_operand:DI 2 "arith_double_operand" "")))]
1506: ""
1507: "
1508: {
1509: if (! register_operand (operands[1], DImode)
1510: || ! register_operand (operands[2], DImode))
1511: /* Let GCC break this into word-at-a-time operations. */
1512: FAIL;
1513: }")
1514:
1515: (define_insn ""
1516: [(set (match_operand:DI 0 "register_operand" "=r")
1517: (and:DI (match_operand:DI 1 "register_operand" "%r")
1518: (match_operand:DI 2 "register_operand" "r")))]
1519: ""
1520: "and %1,%2,%0\;and %R1,%R2,%R0"
1521: [(set_attr "length" "2")])
1522:
1523: (define_insn "andsi3"
1524: [(set (match_operand:SI 0 "register_operand" "=r")
1525: (and:SI (match_operand:SI 1 "register_operand" "%r")
1526: (match_operand:SI 2 "register_operand" "r")))]
1527: ""
1528: "and %1,%2,%0")
1529:
1530: (define_insn ""
1531: [(set (match_operand:DI 0 "register_operand" "=r")
1532: (and:DI (match_operand:DI 1 "register_operand" "r")
1533: (not:DI (match_operand:DI 2 "register_operand" "r"))))]
1534: ""
1535: "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
1536: [(set_attr "length" "2")])
1537:
1538: (define_insn ""
1539: [(set (match_operand:SI 0 "register_operand" "=r")
1540: (and:SI (match_operand:SI 1 "register_operand" "%r")
1541: (not:SI (match_operand:SI 2 "register_operand" "r"))))]
1542: ""
1543: "andcm %1,%2,%0")
1544:
1545:
1546: (define_expand "iordi3"
1547: [(set (match_operand:DI 0 "register_operand" "")
1548: (ior:DI (match_operand:DI 1 "arith_double_operand" "")
1549: (match_operand:DI 2 "arith_double_operand" "")))]
1550: ""
1551: "
1552: {
1553: if (! register_operand (operands[1], DImode)
1554: || ! register_operand (operands[2], DImode))
1555: /* Let GCC break this into word-at-a-time operations. */
1556: FAIL;
1557: }")
1558:
1559: (define_insn ""
1560: [(set (match_operand:DI 0 "register_operand" "=r")
1561: (ior:DI (match_operand:DI 1 "register_operand" "%r")
1562: (match_operand:DI 2 "register_operand" "r")))]
1563: ""
1564: "or %1,%2,%0\;or %R1,%R2,%R0"
1565: [(set_attr "length" "2")])
1566:
1567: (define_insn "iorsi3"
1568: [(set (match_operand:SI 0 "register_operand" "=r")
1569: (ior:SI (match_operand:SI 1 "register_operand" "%r")
1570: (match_operand:SI 2 "register_operand" "r")))]
1571: ""
1572: "or %1,%2,%0")
1573:
1574: (define_expand "xordi3"
1575: [(set (match_operand:DI 0 "register_operand" "")
1576: (xor:DI (match_operand:DI 1 "arith_double_operand" "")
1577: (match_operand:DI 2 "arith_double_operand" "")))]
1578: ""
1579: "
1580: {
1581: if (! register_operand (operands[1], DImode)
1582: || ! register_operand (operands[2], DImode))
1583: /* Let GCC break this into word-at-a-time operations. */
1584: FAIL;
1585: }")
1586:
1587: (define_insn ""
1588: [(set (match_operand:DI 0 "register_operand" "=r")
1589: (xor:DI (match_operand:DI 1 "register_operand" "%r")
1590: (match_operand:DI 2 "register_operand" "r")))]
1591: ""
1592: "xor %1,%2,%0\;xor %R1,%R2,%R0"
1593: [(set_attr "length" "2")])
1594:
1595: (define_insn "xorsi3"
1596: [(set (match_operand:SI 0 "register_operand" "=r")
1597: (xor:SI (match_operand:SI 1 "register_operand" "%r")
1598: (match_operand:SI 2 "register_operand" "r")))]
1599: ""
1600: "xor %r1,%2,%0")
1601:
1602: (define_insn "negdi2"
1603: [(set (match_operand:DI 0 "register_operand" "=r")
1604: (neg:DI (match_operand:DI 1 "register_operand" "r")))]
1605: ""
1606: "sub 0,%R1,%R0\;subb 0,%1,%0"
1607: [(set_attr "type" "unary")
1608: (set_attr "length" "2")])
1609:
1610: (define_insn "negsi2"
1611: [(set (match_operand:SI 0 "register_operand" "=r")
1612: (neg:SI (match_operand:SI 1 "register_operand" "r")))]
1613: ""
1614: "@
1615: sub 0,%1,%0"
1616: [(set_attr "type" "unary")])
1617:
1618: (define_expand "one_cmpldi2"
1619: [(set (match_operand:DI 0 "register_operand" "")
1620: (not:DI (match_operand:DI 1 "arith_double_operand" "")))]
1621: ""
1622: "
1623: {
1624: if (! register_operand (operands[1], DImode))
1625: FAIL;
1626: }")
1627:
1628: (define_insn ""
1629: [(set (match_operand:DI 0 "register_operand" "=r")
1630: (not:DI (match_operand:DI 1 "arith_double_operand" "r")))]
1631: ""
1632: "uaddcm 0,%1,%0\;uaddcm 0,%R1,%R0"
1633: [(set_attr "type" "unary")
1634: (set_attr "length" "2")])
1635:
1636: (define_insn "one_cmplsi2"
1637: [(set (match_operand:SI 0 "general_operand" "=r")
1638: (not:SI (match_operand:SI 1 "register_operand" "r")))]
1639: ""
1640: "uaddcm 0,%1,%0"
1641: [(set_attr "type" "unary")])
1642:
1643: ;; Floating point arithmetic instructions.
1644:
1645: (define_insn "adddf3"
1646: [(set (match_operand:DF 0 "register_operand" "=fxy")
1647: (plus:DF (match_operand:DF 1 "register_operand" "fxy")
1648: (match_operand:DF 2 "register_operand" "fxy")))]
1649: ""
1650: "fadd,dbl %1,%2,%0"
1651: [(set_attr "type" "fpalu")])
1652:
1653: (define_insn "addsf3"
1654: [(set (match_operand:SF 0 "register_operand" "=fxy")
1655: (plus:SF (match_operand:SF 1 "register_operand" "fxy")
1656: (match_operand:SF 2 "register_operand" "fxy")))]
1657: ""
1658: "fadd,sgl %1,%2,%0"
1659: [(set_attr "type" "fpalu")])
1660:
1661: (define_insn "subdf3"
1662: [(set (match_operand:DF 0 "register_operand" "=fxy")
1663: (minus:DF (match_operand:DF 1 "register_operand" "fxy")
1664: (match_operand:DF 2 "register_operand" "fxy")))]
1665: ""
1666: "fsub,dbl %1,%2,%0"
1667: [(set_attr "type" "fpalu")])
1668:
1669: (define_insn "subsf3"
1670: [(set (match_operand:SF 0 "register_operand" "=fxy")
1671: (minus:SF (match_operand:SF 1 "register_operand" "fxy")
1672: (match_operand:SF 2 "register_operand" "fxy")))]
1673: ""
1674: "fsub,sgl %1,%2,%0"
1675: [(set_attr "type" "fpalu")])
1676:
1677: (define_insn "muldf3"
1678: [(set (match_operand:DF 0 "register_operand" "=fxy")
1679: (mult:DF (match_operand:DF 1 "register_operand" "fxy")
1680: (match_operand:DF 2 "register_operand" "fxy")))]
1681: ""
1682: "fmpy,dbl %1,%2,%0"
1683: [(set_attr "type" "fpmul")])
1684:
1685: (define_insn "mulsf3"
1686: [(set (match_operand:SF 0 "register_operand" "=fxy")
1687: (mult:SF (match_operand:SF 1 "register_operand" "fxy")
1688: (match_operand:SF 2 "register_operand" "fxy")))]
1689: ""
1690: "fmpy,sgl %1,%2,%0"
1691: [(set_attr "type" "fpmul")])
1692:
1693: (define_insn "divdf3"
1694: [(set (match_operand:DF 0 "register_operand" "=fxy")
1695: (div:DF (match_operand:DF 1 "register_operand" "fxy")
1696: (match_operand:DF 2 "register_operand" "fxy")))]
1697: ""
1698: "fdiv,dbl %1,%2,%0"
1699: [(set_attr "type" "fpdivdbl")])
1700:
1701: (define_insn "divsf3"
1702: [(set (match_operand:SF 0 "register_operand" "=fxy")
1703: (div:SF (match_operand:SF 1 "register_operand" "fxy")
1704: (match_operand:SF 2 "register_operand" "fxy")))]
1705: ""
1706: "fdiv,sgl %1,%2,%0"
1707: [(set_attr "type" "fpdivsgl")])
1708:
1709: (define_insn "negdf2"
1710: [(set (match_operand:DF 0 "register_operand" "=fxy")
1711: (neg:DF (match_operand:DF 1 "register_operand" "fxy")))]
1712: ""
1713: "fsub,dbl 0,%1,%0"
1714: [(set_attr "type" "fpalu")])
1715:
1716: (define_insn "negsf2"
1717: [(set (match_operand:SF 0 "register_operand" "=fxy")
1718: (neg:SF (match_operand:SF 1 "register_operand" "fxy")))]
1719: ""
1720: "fsub,sgl 0, %1,%0"
1721: [(set_attr "type" "fpalu")])
1722:
1723: (define_insn "absdf2"
1724: [(set (match_operand:DF 0 "register_operand" "=fxy")
1725: (abs:DF (match_operand:DF 1 "register_operand" "fxy")))]
1726: ""
1727: "fabs,dbl %0,%0"
1728: [(set_attr "type" "fpalu")])
1729:
1730: (define_insn "abssf2"
1731: [(set (match_operand:SF 0 "register_operand" "=fxy")
1732: (abs:SF (match_operand:SF 1 "register_operand" "fxy")))]
1733: ""
1734: "fabs,sgl %1,%0"
1735: [(set_attr "type" "fpalu")])
1736:
1737: (define_insn "sqrtdf2"
1738: [(set (match_operand:DF 0 "register_operand" "=fxy")
1739: (sqrt:DF (match_operand:DF 1 "register_operand" "fxy")))]
1740: ""
1741: "fsqrt,dbl %1,%0"
1742: [(set_attr "type" "fpsqrtdbl")])
1743:
1744: (define_insn "sqrtsf2"
1745: [(set (match_operand:SF 0 "register_operand" "=f")
1746: (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
1747: ""
1748: "fsqrt,sgl %1,%0"
1749: [(set_attr "type" "fpsqrtsgl")])
1750:
1.1.1.2 ! root 1751: ;;- Shift instructions
1.1 root 1752:
1753: ;; Optimized special case of shifting.
1754:
1755: (define_insn ""
1756: [(set (match_operand:SI 0 "register_operand" "=r")
1757: (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
1758: (const_int 24)))]
1759: ""
1760: "ldb%M1 %1,%0")
1761:
1762: (define_insn ""
1763: [(set (match_operand:SI 0 "register_operand" "=r")
1.1.1.2 ! root 1764: (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
! 1765: (const_int 2))
! 1766: (match_operand:SI 1 "register_operand" "r")))]
1.1 root 1767: ""
1768: "sh1add %2,%1,%0")
1769:
1770: (define_insn ""
1771: [(set (match_operand:SI 0 "register_operand" "=r")
1.1.1.2 ! root 1772: (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
! 1773: (const_int 4))
! 1774: (match_operand:SI 1 "register_operand" "r")))]
1.1 root 1775: ""
1776: "sh2add %2,%1,%0")
1777:
1778: (define_insn ""
1779: [(set (match_operand:SI 0 "register_operand" "=r")
1.1.1.2 ! root 1780: (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
! 1781: (const_int 8))
! 1782: (match_operand:SI 1 "register_operand" "r")))]
1.1 root 1783: ""
1784: "sh3add %2,%1,%0")
1785:
1786: (define_insn "sar_sub"
1787: [(set (match_operand:SI 0 "register_operand" "=r")
1788: (if_then_else (gtu:SI (match_operand:SI 2 "register_operand" "r")
1789: (match_operand:SI 1 "int11_operand" "I"))
1790: (const_int 0)
1791: (minus:SI (match_dup 1) (match_dup 2))))]
1792: ""
1793: "subi,>>= %1,%2,%0\;copy 0,%0"
1794: [(set_attr "length" "2" )])
1795:
1796: (define_expand "ashlsi3"
1797: [(set (match_operand:SI 0 "register_operand" "")
1798: (ashift:SI (match_operand:SI 1 "register_operand" "")
1799: (match_operand:SI 2 "arith5_operand" "")))]
1800: ""
1801: "
1802: {
1803: if (GET_CODE (operands[2]) != CONST_INT)
1804: {
1805: rtx temp = gen_reg_rtx (SImode);
1806: emit_insn (gen_sar_sub (temp,
1807: gen_rtx (CONST_INT, VOIDmode, 31),
1808: operands[2]));
1809: emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 112), temp));
1810: emit_insn (gen_rtx (SET, VOIDmode,
1811: operands[0],
1812: gen_rtx (ASHIFT, SImode,
1813: operands[1],
1814: gen_rtx (MINUS, SImode,
1815: gen_rtx (CONST_INT, VOIDmode, 31),
1816: gen_rtx (REG, SImode, 112)))));
1817: DONE;
1818: }
1819: }")
1820:
1821: (define_insn ""
1822: [(set (match_operand:SI 0 "register_operand" "=r")
1823: (ashift:SI (match_operand:SI 1 "register_operand" "r")
1824: (match_operand:SI 2 "int5_operand" "L")))]
1825: ""
1826: "*
1827: {
1828: rtx xoperands[4];
1829: xoperands[0] = operands[0]; xoperands[1] = operands[1];
1830: xoperands[2] = gen_rtx (CONST_INT, VOIDmode,
1831: 31 - INTVAL (operands[2]));
1832: xoperands[3] = gen_rtx (CONST_INT, VOIDmode,
1833: 32 - INTVAL (operands[2]));
1834: output_asm_insn (\"zdep %1,%2,%3,%0\", xoperands);
1835: return \"\";
1836: }")
1837:
1838: (define_insn ""
1839: [(set (match_operand:SI 0 "register_operand" "=r")
1840: (ashift:SI (match_operand:SI 1 "register_operand" "r")
1841: (minus:SI (const_int 31)
1842: (reg:SI 112))))]
1843: ""
1844: "zvdep %1,32,%0")
1845:
1846: (define_expand "ashrsi3"
1847: [(set (match_operand:SI 0 "register_operand" "")
1848: (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
1849: (match_operand:SI 2 "arith5_operand" "")))]
1850: ""
1851: "
1852: {
1853: if (GET_CODE (operands[2]) != CONST_INT)
1854: {
1855: rtx temp = gen_reg_rtx (SImode);
1856: emit_insn (gen_sar_sub (temp,
1857: gen_rtx (CONST_INT, VOIDmode, 31),
1858: operands[2]));
1859: emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 112), temp));
1860: emit_insn (gen_rtx (SET, VOIDmode,
1861: operands[0],
1862: gen_rtx (ASHIFTRT, SImode,
1863: operands[1],
1864: gen_rtx (MINUS, SImode,
1865: gen_rtx (CONST_INT, VOIDmode, 31),
1866: gen_rtx (REG, SImode, 112)))));
1867: DONE;
1868: }
1869: }")
1870:
1871: (define_insn ""
1872: [(set (match_operand:SI 0 "register_operand" "=r")
1873: (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
1874: (match_operand:SI 2 "int5_operand" "L")))]
1875: ""
1876: "*
1877: {
1878: rtx xoperands[4];
1879: xoperands[0] = operands[0]; xoperands[1] = operands[1];
1880: xoperands[2] = gen_rtx (CONST_INT, VOIDmode,
1881: 31 - INTVAL (operands[2]));
1882: xoperands[3] = gen_rtx (CONST_INT, VOIDmode,
1883: 32 - INTVAL (operands[2]));
1884: output_asm_insn (\"extrs %1,%2,%3,%0\", xoperands);
1885: return \"\";
1886: }")
1887:
1888:
1889: (define_insn ""
1890: [(set (match_operand:SI 0 "register_operand" "=r")
1891: (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
1892: (minus:SI (const_int 31)
1893: (reg:SI 112))))]
1894: ""
1895: "vextrs %1,32,%0")
1896:
1897: (define_expand "lshrsi3"
1898: [(set (match_operand:SI 0 "register_operand" "")
1899: (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
1900: (match_operand:SI 2 "arith5_operand" "")))]
1901: ""
1902: "
1903: {
1904: if (GET_CODE (operands[2]) != CONST_INT)
1905: {
1906: rtx temp = gen_reg_rtx (SImode);
1907: emit_insn (gen_sar_sub (temp,
1908: gen_rtx (CONST_INT, VOIDmode, 31),
1909: operands[2]));
1910: emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 112), temp));
1911: emit_insn (gen_rtx (SET, VOIDmode,
1912: operands[0],
1913: gen_rtx (LSHIFTRT, SImode,
1914: operands[1],
1915: gen_rtx (MINUS, SImode,
1916: gen_rtx (CONST_INT, VOIDmode, 31),
1917: gen_rtx (REG, SImode, 112)))));
1918: DONE;
1919: }
1920: }")
1921:
1922: (define_insn ""
1923: [(set (match_operand:SI 0 "register_operand" "=r")
1924: (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
1925: (match_operand:SI 2 "uint5_operand" "K")))]
1926: ""
1927: "*
1928: {
1929: rtx xoperands[4];
1930: xoperands[0] = operands[0]; xoperands[1] = operands[1];
1931: xoperands[2] = gen_rtx (CONST_INT, VOIDmode,
1932: 31 - INTVAL (operands[2]));
1933: xoperands[3] = gen_rtx (CONST_INT, VOIDmode,
1934: 32 - INTVAL (operands[2]));
1935: output_asm_insn (\"extru %1,%2,%3,%0\", xoperands);
1936: return \"\";
1937: }")
1938:
1939: (define_insn ""
1940: [(set (match_operand:SI 0 "register_operand" "=r")
1941: (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
1942: (minus:SI (const_int 31)
1943: (reg:SI 112))))]
1944: ""
1945: "vextru %1,32,%0")
1946:
1947: ;; Unconditional and other jump instructions.
1948:
1949: (define_insn "jump"
1950: [(set (pc) (label_ref (match_operand 0 "" "")))]
1951: ""
1952: "bl%* %l0,0"
1953: [(set_attr "type" "branch")])
1954:
1955: (define_insn "casesi"
1956: [(set (pc)
1957: (if_then_else (leu (minus:SI
1958: (match_operand:SI 0 "general_operand" "r")
1959: (match_operand:SI 1 "general_operand" "rI"))
1960: (match_operand:SI 2 "general_operand" "rI"))
1961: (plus:SI (mem:SI (plus:SI (pc)
1962: (minus:SI (match_dup 0)
1963: (match_dup 1))))
1964: (label_ref (match_operand 3 "" "")))
1965: (pc)))
1966: (use (label_ref (match_operand 4 "" "")))
1967: (clobber (match_scratch:SI 5 "=r"))]
1968: ""
1969: "*
1970: {
1971: if (GET_CODE (operands[1]) == CONST_INT)
1972: {
1973: if (GET_CODE (operands[2]) == CONST_INT)
1974: {
1975: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1976: INTVAL (operands[1]) + INTVAL (operands[2]));
1977: if (!INT_11_BITS (operands[2]))
1978: {
1979: output_asm_insn (\"ldo %2(0),%5\", operands);
1980: operands[2] = operands[5];
1981: }
1982: }
1983: else
1984: output_asm_insn (\"ldo %1(%2),%2\", operands);
1985: output_asm_insn (\"addi,< %n1,%0,0\", operands);
1986: }
1987: else
1988: {
1989: if (GET_CODE (operands[2]) == CONST_INT)
1990: {
1991: output_asm_insn (\"ldo %2(%1),%5\", operands);
1992: operands[2] = operands[5];
1993: }
1994: output_asm_insn (\"sub,< %0,%1,0\", operands);
1995: }
1996: if (GET_CODE (operands[2]) == CONST_INT)
1997: output_asm_insn (\"addi,<= %n2,%0,0\", operands);
1998: else
1999: output_asm_insn (\"sub,<= %0,%2,0\", operands);
2000: output_asm_insn (\"b,n %l4\", operands);
2001: if (GET_CODE (operands[1]) == CONST_INT)
2002: output_asm_insn (\"ldo %n1(%0),%5\", operands);
2003: else output_asm_insn (\"sub %0,%1,%5\", operands);
2004: return \"blr %5,0\;nop\";
2005: }"
2006: [(set_attr "length" "7")])
2007:
2008: ;; Need nops for the calls because execution is supposed to continue
2009: ;; past; we don't want to nullify an instruction that we need.
2010: ;;- jump to subroutine
2011:
2012: (define_expand "call"
2013: [(parallel [(call (match_operand:SI 0 "" "")
2014: (match_operand 1 "" ""))
2015: (clobber (reg:SI 31))
2016: (clobber (reg:SI 2))])]
2017: ""
2018: "
2019: {
2020: operands[0] = gen_rtx (MEM, SImode, XEXP (operands[0], 0));
2021: }")
2022:
2023: (define_insn ""
2024: [(call (mem:SI (match_operand:SI 0 "call_operand_address" "r,S"))
2025: (match_operand 1 "" "i,i"))
2026: (clobber (reg:SI 31))
2027: (clobber (reg:SI 2))]
2028: ""
2029: "*
2030: {
2031: if (which_alternative == 0)
2032: return \"copy %0,22\;.CALL\\tARGW0=GR\;bl $$dyncall,31\;copy 31,2\";
2033: else
2034: {
2035: output_arg_descriptor (insn);
2036: return \"bl %0,2%#\";
2037: }
2038: }"
2039: [(set_attr "type" "dyncall,call")
2040: (set_attr "length" "3,1")])
2041:
2042: (define_expand "call_value"
2043: [(parallel [(set (match_operand 0 "" "")
2044: (call (match_operand:SI 1 "" "")
2045: (match_operand 2 "" "")))
2046: (clobber (reg:SI 31))
2047: (clobber (reg:SI 2))])]
2048: ;;- Don't use operand 1 for most machines.
2049: ""
2050: "
2051: {
2052: operands[1] = gen_rtx (MEM, SImode, XEXP (operands[1], 0));
2053: }")
2054:
2055: (define_insn ""
2056: [(set (match_operand 0 "" "=rf,rf")
2057: (call (mem:SI (match_operand:SI 1 "call_operand_address" "r,S"))
2058: (match_operand 2 "" "i,i")))
2059: (clobber (reg:SI 31))
2060: (clobber (reg:SI 2))]
2061: ;;- Don't use operand 1 for most machines.
2062: ""
2063: "*
2064: {
2065: if (which_alternative == 0)
2066: return \"copy %1,22\;.CALL\\tARGW0=GR\;bl $$dyncall,31\;copy 31,2\";
2067: else
2068: {
2069: output_arg_descriptor (insn);
2070: return \"bl %1,2\;nop\";
2071: }
2072: }"
2073: [(set_attr "type" "dyncall")
2074: (set_attr "length" "3,2")])
2075:
2076: (define_insn "nop"
2077: [(const_int 0)]
2078: ""
2079: "nop")
2080:
2081: ;;; Hope this is only within a function...
2082: (define_insn "indirect_jump"
2083: [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
2084: ""
2085: "bv 0(%0)%#"
2086: [(set_attr "type" "branch")])
2087:
2088: (define_insn "extzv"
2089: [(set (match_operand:SI 0 "register_operand" "=r")
2090: (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2091: (match_operand:SI 2 "uint5_operand" "")
2092: (match_operand:SI 3 "uint5_operand" "")))]
2093: ""
2094: "extru %1,%3+%2-1,%2,%0")
2095:
2096: (define_insn "extv"
2097: [(set (match_operand:SI 0 "register_operand" "=r")
2098: (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
2099: (match_operand:SI 2 "uint5_operand" "")
2100: (match_operand:SI 3 "uint5_operand" "")))]
2101: ""
2102: "extrs %1,%3+%2-1,%2,%0")
2103:
2104: (define_insn "insv"
2105: [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "=r")
2106: (match_operand:SI 1 "uint5_operand" "")
2107: (match_operand:SI 2 "uint5_operand" ""))
2108: (match_operand:SI 3 "register_operand" "r"))]
2109: ""
2110: "dep %3,%2+%1-1,%1,%0")
2111:
2112: ;;- Local variables:
2113: ;;- mode:emacs-lisp
2114: ;;- comment-start: ";;- "
2115: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
2116: ;;- eval: (modify-syntax-entry ?[ "(]")
2117: ;;- eval: (modify-syntax-entry ?] ")[")
2118: ;;- eval: (modify-syntax-entry ?{ "(}")
2119: ;;- eval: (modify-syntax-entry ?} "){")
2120: ;;- End:
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