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1.1 root 1: ;;- Machine description for GNU compiler -- System/370 version. 1.1.1.3 ! root 2: ;; Copyright (C) 1989, 1993, 1994, 1995 Free Software Foundation, Inc. 1.1.1.2 root 3: ;; Contributed by Jan Stein ([email protected]). 1.1.1.3 ! root 4: ;; Modified for MVS C/370 by Dave Pitts ([email protected]) 1.1 root 5: 6: ;; This file is part of GNU CC. 7: 8: ;; GNU CC is free software; you can redistribute it and/or modify 9: ;; it under the terms of the GNU General Public License as published by 10: ;; the Free Software Foundation; either version 2, or (at your option) 11: ;; any later version. 12: 13: ;; GNU CC is distributed in the hope that it will be useful, 14: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 15: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16: ;; GNU General Public License for more details. 17: 18: ;; You should have received a copy of the GNU General Public License 19: ;; along with GNU CC; see the file COPYING. If not, write to 1.1.1.3 ! root 20: ;; the Free Software Foundation, 59 Temple Place - Suite 330, ! 21: ;; Boston, MA 02111-1307, USA. 1.1 root 22: 23: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code 24: ;;- updates for most instructions. 25: 26: ;; 27: ;; Special constraints for 370 machine description: 28: ;; 29: ;; a -- Any address register from 1 to 15. 30: ;; d -- Any register from 0 to 15. 31: ;; I -- An 8-bit constant (0..255). 32: ;; J -- A 12-bit constant (0..4095). 33: ;; K -- A 16-bit constant (-32768..32767). 34: ;; 35: ;; Special formats used for outputting 370 instructions. 36: ;; 37: ;; %B -- Print a constant byte integer. 38: ;; %H -- Print a signed 16-bit constant. 39: ;; %L -- Print least significant word of a CONST_DOUBLE. 40: ;; %M -- Print most significant word of a CONST_DOUBLE. 41: ;; %N -- Print next register (second word of a DImode reg). 42: ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)). 43: ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)). 44: ;; %X -- Print a constant byte integer in hex. 45: ;; 1.1.1.3 ! root 46: ;; We have a special constraint for pattern matching. 1.1 root 47: ;; 48: ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. 49: ;; 50: ;; r_or_s_operand -- Matches a register or a valid S operand in a RS, SI 51: ;; or SS type instruction or a register 52: ;; 53: ;; For MVS C/370 we use the following stack locations for: 54: ;; 55: ;; 136 - internal function result buffer 56: ;; 140 - numeric conversion buffer 57: ;; 144 - pointer to internal function result buffer 58: ;; 148 - start of automatic variables and function arguments 59: ;; 60: ;; To support programs larger than a page, 4096 bytes, PAGE_REGISTER points 61: ;; to a page origin table, all internal labels are generated to reload the 62: ;; BASE_REGISTER knowing what page it is on and all branch instructions go 63: ;; directly to the target if it is known that the target is on the current 64: ;; page (essentially backward references). All forward references and off 65: ;; page references are handled by loading the address of target into a 66: ;; register and branching indirectly. 67: ;; 68: ;; Some *di patterns have been commented out per advice from RMS, as gcc 69: ;; will generate the right things to do. 70: ;; 71: 72: ;; 73: ;;- Test instructions. 74: ;; 75: 76: ; 77: ; tstdi instruction pattern(s). 78: ; 79: 80: (define_insn "tstdi" 81: [(set (cc0) 82: (match_operand:DI 0 "register_operand" "d"))] 83: "" 84: "* 85: { 86: check_label_emit (); 87: mvs_check_page (0, 4, 0); 88: return \"SRDA %0,0\"; 89: }") 90: 91: ; 92: ; tstsi instruction pattern(s). 93: ; 94: 95: (define_insn "tstsi" 96: [(set (cc0) 97: (match_operand:SI 0 "register_operand" "d"))] 98: "" 99: "* 100: { 101: check_label_emit (); 102: mvs_check_page (0, 2, 0); 103: return \"LTR %0,%0\"; 104: }") 105: 106: ; 107: ; tsthi instruction pattern(s). 108: ; 109: 110: (define_insn "tsthi" 111: [(set (cc0) 112: (match_operand:HI 0 "register_operand" "d"))] 113: "" 114: "* 115: { 116: check_label_emit (); 117: mvs_check_page (0, 4, 2); 118: return \"CH %0,=H'0'\"; 119: }") 120: 121: ; 122: ; tstqi instruction pattern(s). 123: ; 124: 125: (define_insn "" 126: [(set (cc0) 127: (match_operand:QI 0 "r_or_s_operand" "dm"))] 128: "unsigned_jump_follows_p (insn)" 129: "* 130: { 131: check_label_emit (); 132: if (REG_P (operands[0])) 133: { 134: mvs_check_page (0, 4, 4); 135: return \"N %0,=X'000000FF'\"; 136: } 137: mvs_check_page (0, 4, 0); 138: return \"CLI %0,0\"; 139: }") 140: 141: (define_insn "tstqi" 142: [(set (cc0) 143: (match_operand:QI 0 "register_operand" "d"))] 144: "" 145: "* 146: { 147: check_label_emit (); 148: if (unsigned_jump_follows_p (insn)) 149: { 150: mvs_check_page (0, 4, 4); 151: return \"N %0,=X'000000FF'\"; 152: } 153: mvs_check_page (0, 8, 0); 154: return \"SLL %0,24\;SRA %0,24\"; 155: }") 156: 157: ; 158: ; tstdf instruction pattern(s). 159: ; 160: 161: (define_insn "tstdf" 162: [(set (cc0) 163: (match_operand:DF 0 "general_operand" "f"))] 164: "" 165: "* 166: { 167: check_label_emit (); 168: mvs_check_page (0, 2, 0); 169: return \"LTDR %0,%0\"; 170: }") 171: 172: ; 173: ; tstsf instruction pattern(s). 174: ; 175: 176: (define_insn "tstsf" 177: [(set (cc0) 178: (match_operand:SF 0 "general_operand" "f"))] 179: "" 180: "* 181: { 182: check_label_emit (); 183: mvs_check_page (0, 2, 0); 184: return \"LTER %0,%0\"; 185: }") 186: 187: ;; 188: ;;- Compare instructions. 189: ;; 190: 191: ; 192: ; cmpdi instruction pattern(s). 193: ; 194: 195: ;(define_insn "cmpdi" 196: ; [(set (cc0) 197: ; (compare (match_operand:DI 0 "register_operand" "d") 198: ; (match_operand:DI 1 "general_operand" "")))] 199: ; "" 200: ; "* 201: ;{ 202: ; check_label_emit (); 203: ; if (REG_P (operands[1])) 204: ; { 205: ; mvs_check_page (0, 8, 0); 206: ; if (unsigned_jump_follows_p (insn)) 207: ; return \"CLR %0,%1\;BNE *+6\;CLR %N0,%N1\"; 208: ; return \"CR %0,%1\;BNE *+6\;CLR %N0,%N1\"; 209: ; } 210: ; mvs_check_page (0, 12, 0); 211: ; if (unsigned_jump_follows_p (insn)) 212: ; return \"CL %0,%M1\;BNE *+8\;CL %N0,%L1\"; 213: ; return \"C %0,%M1\;BNE *+8\;CL %N0,%L1\"; 214: ;}") 215: 216: ; 217: ; cmpsi instruction pattern(s). 218: ; 219: 220: (define_insn "cmpsi" 221: [(set (cc0) 222: (compare (match_operand:SI 0 "register_operand" "d") 1.1.1.3 ! root 223: (match_operand:SI 1 "general_operand" "md")))] 1.1 root 224: "" 225: "* 226: { 227: check_label_emit (); 228: if (REG_P (operands[1])) 229: { 230: mvs_check_page (0, 2, 0); 231: if (unsigned_jump_follows_p (insn)) 232: return \"CLR %0,%1\"; 233: return \"CR %0,%1\"; 234: } 235: if (GET_CODE (operands[1]) == CONST_INT) 236: { 237: mvs_check_page (0, 4, 4); 238: if (unsigned_jump_follows_p (insn)) 239: return \"CL %0,=F'%c1'\"; 240: return \"C %0,=F'%c1'\"; 241: } 242: mvs_check_page (0, 4, 0); 243: if (unsigned_jump_follows_p (insn)) 244: return \"CL %0,%1\"; 245: return \"C %0,%1\"; 246: }") 247: 248: ; 249: ; cmphi instruction pattern(s). 250: ; 251: 252: (define_insn "cmphi" 253: [(set (cc0) 254: (compare (match_operand:HI 0 "register_operand" "d") 255: (match_operand:HI 1 "general_operand" "")))] 256: "" 257: "* 258: { 259: check_label_emit (); 260: if (REG_P (operands[1])) 261: { 262: mvs_check_page (0, 8, 0); 263: if (unsigned_jump_follows_p (insn)) 264: return \"STH %1,140(,13)\;CLM %0,3,140(13)\"; 265: return \"STH %1,140(,13)\;CH %0,140(,13)\"; 266: } 267: if (GET_CODE (operands[1]) == CONST_INT) 268: { 1.1.1.3 ! root 269: mvs_check_page (0, 4, 0); ! 270: return \"CH %0,%H1\"; 1.1 root 271: } 272: mvs_check_page (0, 4, 0); 273: return \"CH %0,%1\"; 274: }") 275: 276: ; 277: ; cmpqi instruction pattern(s). 278: ; 279: 280: (define_insn "" 281: [(set (cc0) 282: (compare (match_operand:QI 0 "r_or_s_operand" "g") 283: (match_operand:QI 1 "r_or_s_operand" "g")))] 284: "unsigned_jump_follows_p (insn)" 285: "* 286: { 287: check_label_emit (); 288: if (REG_P (operands[0])) 289: { 290: if (REG_P (operands[1])) 291: { 292: mvs_check_page (0, 8, 0); 293: return \"STC %1,140(,13)\;CLM %0,1,140(13)\"; 294: } 295: if (GET_CODE (operands[1]) == CONST_INT) 296: { 297: mvs_check_page (0, 4, 1); 298: return \"CLM %0,1,=X'%X1'\"; 299: } 300: mvs_check_page (0, 4, 0); 301: return \"CLM %0,1,%1\"; 302: } 303: else if (GET_CODE (operands[0]) == CONST_INT) 304: { 305: cc_status.flags |= CC_REVERSED; 306: if (REG_P (operands[1])) 307: { 308: mvs_check_page (0, 4, 1); 309: return \"CLM %1,1,=X'%X0'\"; 310: } 311: mvs_check_page (0, 4, 0); 312: return \"CLI %1,%B0\"; 313: } 314: if (GET_CODE (operands[1]) == CONST_INT) 315: { 316: mvs_check_page (0, 4, 0); 317: return \"CLI %0,%B1\"; 318: } 319: if (GET_CODE (operands[1]) == MEM) 320: { 321: mvs_check_page (0, 6, 0); 322: return \"CLC %O0(1,%R0),%1\"; 323: } 324: cc_status.flags |= CC_REVERSED; 325: mvs_check_page (0, 4, 0); 326: return \"CLM %1,1,%0\"; 327: }") 328: 329: (define_insn "cmpqi" 330: [(set (cc0) 331: (compare (match_operand:QI 0 "register_operand" "d") 332: (match_operand:QI 1 "general_operand" "di")))] 333: "" 334: "* 335: { 336: check_label_emit (); 337: if (unsigned_jump_follows_p (insn)) 338: { 339: if (REG_P (operands[1])) 340: { 341: mvs_check_page (0, 4, 0); 342: return \"CLM %0,1,%1\"; 343: } 344: if (GET_CODE (operands[1]) == CONST_INT) 345: { 346: mvs_check_page (0, 4, 1); 347: return \"CLM %0,1,=X'%X1'\"; 348: } 349: mvs_check_page (0, 8, 0); 350: return \"STC %1,140(,13)\;CLM %0,1,140(13)\"; 351: } 352: if (REG_P (operands[1])) 353: { 354: mvs_check_page (0, 18, 0); 355: return \"SLL %0,24\;SRA %0,24\;SLL %1,24\;SRA %1,24\;CR %0,%1\"; 356: } 357: mvs_check_page (0, 12, 0); 358: return \"SLL %0,24\;SRA %0,24\;C %0,%1\"; 359: }") 360: 361: ; 362: ; cmpdf instruction pattern(s). 363: ; 364: 365: (define_insn "cmpdf" 366: [(set (cc0) 367: (compare (match_operand:DF 0 "general_operand" "f,mF") 368: (match_operand:DF 1 "general_operand" "fmF,f")))] 369: "" 370: "* 371: { 372: check_label_emit (); 373: if (FP_REG_P (operands[0])) 374: { 375: if (FP_REG_P (operands[1])) 376: { 377: mvs_check_page (0, 2, 0); 378: return \"CDR %0,%1\"; 379: } 380: mvs_check_page (0, 4, 0); 381: return \"CD %0,%1\"; 382: } 383: cc_status.flags |= CC_REVERSED; 384: mvs_check_page (0, 4, 0); 385: return \"CD %1,%0\"; 386: }") 387: 388: ; 389: ; cmpsf instruction pattern(s). 390: ; 391: 392: (define_insn "cmpsf" 393: [(set (cc0) 394: (compare (match_operand:SF 0 "general_operand" "f,mF") 395: (match_operand:SF 1 "general_operand" "fmF,f")))] 396: "" 397: "* 398: { 399: check_label_emit (); 400: if (FP_REG_P (operands[0])) 401: { 402: if (FP_REG_P (operands[1])) 403: { 404: mvs_check_page (0, 2, 0); 405: return \"CER %0,%1\"; 406: } 407: mvs_check_page (0, 4, 0); 408: return \"CE %0,%1\"; 409: } 410: cc_status.flags |= CC_REVERSED; 411: mvs_check_page (0, 4, 0); 412: return \"CE %1,%0\"; 413: }") 414: 415: ; 416: ; cmpstrsi instruction pattern(s). 417: ; 418: 419: (define_expand "cmpstrsi" 420: [(set (match_operand:SI 0 "general_operand" "") 421: (compare (match_operand:BLK 1 "general_operand" "") 422: (match_operand:BLK 2 "general_operand" ""))) 423: (use (match_operand:SI 3 "general_operand" "")) 424: (use (match_operand:SI 4 "" ""))] 425: "" 426: " 427: { 428: rtx op1, op2; 429: 430: op1 = XEXP (operands[1], 0); 431: if (GET_CODE (op1) == REG 432: || (GET_CODE (op1) == PLUS && GET_CODE (XEXP (op1, 0)) == REG 433: && GET_CODE (XEXP (op1, 1)) == CONST_INT 434: && (unsigned) INTVAL (XEXP (op1, 1)) < 4096)) 435: { 436: op1 = operands[1]; 437: } 438: else 439: { 440: op1 = gen_rtx (MEM, BLKmode, copy_to_mode_reg (SImode, op1)); 441: } 442: 443: op2 = XEXP (operands[2], 0); 444: if (GET_CODE (op2) == REG 445: || (GET_CODE (op2) == PLUS && GET_CODE (XEXP (op2, 0)) == REG 446: && GET_CODE (XEXP (op2, 1)) == CONST_INT 447: && (unsigned) INTVAL (XEXP (op2, 1)) < 4096)) 448: { 449: op2 = operands[2]; 450: } 451: else 452: { 453: op2 = gen_rtx (MEM, BLKmode, copy_to_mode_reg (SImode, op2)); 454: } 455: 456: if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256) 457: { 458: emit_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, 459: gen_rtx (SET, VOIDmode, operands[0], 460: gen_rtx (COMPARE, VOIDmode, op1, op2)), 461: gen_rtx (USE, VOIDmode, operands[3])))); 462: } 463: else 464: { 465: rtx reg1 = gen_reg_rtx (DImode); 466: rtx reg2 = gen_reg_rtx (DImode); 467: rtx subreg = gen_rtx (SUBREG, SImode, reg1, 1); 468: 469: emit_insn (gen_rtx (SET, VOIDmode, subreg, operands[3])); 470: emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode, reg2, 1), 471: subreg)); 472: emit_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (5, 473: gen_rtx (SET, VOIDmode, operands[0], 474: gen_rtx (COMPARE, VOIDmode, op1, op2)), 475: gen_rtx (USE, VOIDmode, reg1), 476: gen_rtx (USE, VOIDmode, reg2), 477: gen_rtx (CLOBBER, VOIDmode, reg1), 478: gen_rtx (CLOBBER, VOIDmode, reg2)))); 479: } 480: DONE; 481: }") 482: 483: ; Compare a block that is less than 256 bytes in length. 484: 485: (define_insn "" 486: [(set (match_operand:SI 0 "register_operand" "d") 487: (compare (match_operand:BLK 1 "s_operand" "m") 488: (match_operand:BLK 2 "s_operand" "m"))) 489: (use (match_operand:QI 3 "immediate_operand" "I"))] 490: "((unsigned) INTVAL (operands[3]) < 256)" 491: "* 492: { 493: check_label_emit (); 494: mvs_check_page (0, 22, 0); 495: return \"LA %0,1\;CLC %O1(%c3,%R1),%2\;BH *+12\;BL *+6\;SLR %0,%0\;LNR %0,%0\"; 496: }") 497: 498: ; Compare a block that is larger than 255 bytes in length. 499: 500: (define_insn "" 501: [(set (match_operand:SI 0 "register_operand" "d") 502: (compare (match_operand:BLK 1 "general_operand" "m") 503: (match_operand:BLK 2 "general_operand" "m"))) 504: (use (match_operand:DI 3 "register_operand" "d")) 505: (use (match_operand:DI 4 "register_operand" "d")) 506: (clobber (match_dup 3)) 507: (clobber (match_dup 4))] 508: "" 509: "* 510: { 511: check_label_emit (); 512: mvs_check_page (0, 26, 0); 513: return \"LA %3,%1\;LA %4,%2\;LA %0,1\;CLCL %3,%4\;BH *+12\;BL *+6\;SLR %0,%0\;LNR %0,%0\"; 514: }") 515: 516: ;; 517: ;;- Move instructions. 518: ;; 519: 520: ; 521: ; movdi instruction pattern(s). 522: ; 523: 524: (define_insn "" 525: [(set (match_operand:DI 0 "r_or_s_operand" "=dm") 526: (match_operand:DI 1 "r_or_s_operand" "dim*fF"))] 527: "TARGET_CHAR_INSTRUCTIONS" 528: "* 529: { 530: check_label_emit (); 531: if (REG_P (operands[0])) 532: { 533: if (FP_REG_P (operands[1])) 534: { 535: mvs_check_page (0, 8, 0); 536: return \"STD %1,140(,13)\;LM %0,%N0,140(13)\"; 537: } 538: if (REG_P (operands[1])) 539: { 540: mvs_check_page (0, 4, 0); 541: return \"LR %0,%1\;LR %N0,%N1\"; 542: } 543: if (operands[1] == const0_rtx) 544: { 545: CC_STATUS_INIT; 546: mvs_check_page (0, 4, 0); 547: return \"SLR %0,%0\;SLR %N0,%N0\"; 548: } 549: if (GET_CODE (operands[1]) == CONST_INT 550: && (unsigned) INTVAL (operands[1]) < 4096) 551: { 552: CC_STATUS_INIT; 553: mvs_check_page (0, 6, 0); 554: return \"SLR %0,%0\;LA %N0,%c1\"; 555: } 556: if (GET_CODE (operands[1]) == CONST_INT) 557: { 558: CC_STATUS_SET (operands[0], operands[1]); 559: mvs_check_page (0, 8, 0); 560: return \"L %0,%1\;SRDA %0,32\"; 561: } 562: mvs_check_page (0, 4, 0); 563: return \"LM %0,%N0,%1\"; 564: } 565: else if (FP_REG_P (operands[1])) 566: { 567: mvs_check_page (0, 4, 0); 568: return \"STD %1,%0\"; 569: } 570: else if (REG_P (operands[1])) 571: { 572: mvs_check_page (0, 4, 0); 573: return \"STM %1,%N1,%0\"; 574: } 575: mvs_check_page (0, 6, 0); 576: return \"MVC %O0(8,%R0),%1\"; 577: }") 578: 579: (define_insn "movdi" 580: [(set (match_operand:DI 0 "general_operand" "=dm") 581: (match_operand:DI 1 "general_operand" "dim*fF"))] 582: "" 583: "* 584: { 585: check_label_emit (); 586: if (REG_P (operands[0])) 587: { 588: if (FP_REG_P (operands[1])) 589: { 590: mvs_check_page (0, 8, 0); 591: return \"STD %1,140(,13)\;LM %0,%N0,140(13)\"; 592: } 593: if (REG_P (operands[1])) 594: { 595: mvs_check_page (0, 4, 0); 596: return \"LR %0,%1\;LR %N0,%N1\"; 597: } 598: if (operands[1] == const0_rtx) 599: { 600: CC_STATUS_INIT; 601: mvs_check_page (0, 4, 0); 602: return \"SLR %0,%0\;SLR %N0,%N0\"; 603: } 604: if (GET_CODE (operands[1]) == CONST_INT 605: && (unsigned) INTVAL (operands[1]) < 4096) 606: { 607: CC_STATUS_INIT; 608: mvs_check_page (0, 6, 0); 609: return \"SLR %0,%0\;LA %N0,%c1\"; 610: } 611: if (GET_CODE (operands[1]) == CONST_INT) 612: { 613: CC_STATUS_SET (operands[0], operands[1]); 614: mvs_check_page (0, 8, 0); 615: return \"L %0,%1\;SRDA %0,32\"; 616: } 617: mvs_check_page (0, 4, 0); 618: return \"LM %0,%N0,%1\"; 619: } 620: else if (FP_REG_P (operands[1])) 621: { 622: mvs_check_page (0, 4, 0); 623: return \"STD %1,%0\"; 624: } 625: mvs_check_page (0, 4, 0); 626: return \"STM %1,%N1,%0\"; 627: }") 628: 629: ; 630: ; movsi instruction pattern(s). 631: ; 632: 633: (define_insn "" 634: [(set (match_operand:SI 0 "r_or_s_operand" "=dm,dm") 635: (match_operand:SI 1 "r_or_s_operand" "dim,*fF"))] 636: "TARGET_CHAR_INSTRUCTIONS" 637: "* 638: { 639: check_label_emit (); 640: if (REG_P (operands[0])) 641: { 642: if (FP_REG_P (operands[1])) 643: { 644: mvs_check_page (0, 8, 0); 645: return \"STE %1,140(,13)\;L %0,140(,13)\"; 646: } 647: if (REG_P (operands[1])) 648: { 649: mvs_check_page (0, 2, 0); 650: return \"LR %0,%1\"; 651: } 652: if (operands[1] == const0_rtx) 653: { 654: CC_STATUS_INIT; 655: mvs_check_page (0, 2, 0); 656: return \"SLR %0,%0\"; 657: } 658: if (GET_CODE (operands[1]) == CONST_INT 659: && (unsigned) INTVAL (operands[1]) < 4096) 660: { 661: mvs_check_page (0, 4, 0); 662: return \"LA %0,%c1\"; 663: } 664: mvs_check_page (0, 4, 0); 665: return \"L %0,%1\"; 666: } 667: else if (FP_REG_P (operands[1])) 668: { 669: mvs_check_page (0, 4, 0); 670: return \"STE %1,%0\"; 671: } 672: else if (REG_P (operands[1])) 673: { 674: mvs_check_page (0, 4, 0); 675: return \"ST %1,%0\"; 676: } 677: mvs_check_page (0, 6, 0); 678: return \"MVC %O0(4,%R0),%1\"; 679: }") 680: 681: (define_insn "movsi" 682: [(set (match_operand:SI 0 "general_operand" "=d,dm") 683: (match_operand:SI 1 "general_operand" "dimF,*fd"))] 684: "" 685: "* 686: { 687: check_label_emit (); 688: if (REG_P (operands[0])) 689: { 690: if (FP_REG_P (operands[1])) 691: { 692: mvs_check_page (0, 8, 0); 693: return \"STE %1,140(,13)\;L %0,140(,13)\"; 694: } 695: if (REG_P (operands[1])) 696: { 697: mvs_check_page (0, 2, 0); 698: return \"LR %0,%1\"; 699: } 700: if (operands[1] == const0_rtx) 701: { 702: CC_STATUS_INIT; 703: mvs_check_page (0, 2, 0); 704: return \"SLR %0,%0\"; 705: } 706: if (GET_CODE (operands[1]) == CONST_INT 707: && (unsigned) INTVAL (operands[1]) < 4096) 708: { 709: mvs_check_page (0, 4, 0); 710: return \"LA %0,%c1\"; 711: } 712: mvs_check_page (0, 4, 0); 713: return \"L %0,%1\"; 714: } 715: else if (FP_REG_P (operands[1])) 716: { 717: mvs_check_page (0, 4, 0); 718: return \"STE %1,%0\"; 719: } 720: mvs_check_page (0, 4, 0); 721: return \"ST %1,%0\"; 722: }") 723: 724: ;(define_expand "movsi" 725: ; [(set (match_operand:SI 0 "general_operand" "=d,dm") 726: ; (match_operand:SI 1 "general_operand" "dimF,*fd"))] 727: ; "" 728: ; " 729: ;{ 730: ; rtx op0, op1; 731: ; 732: ; op0 = operands[0]; 733: ; if (GET_CODE (op0) == CONST 734: ; && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SYMBOL_REF 735: ; && SYMBOL_REF_FLAG (XEXP (XEXP (op0, 0), 0))) 736: ; { 737: ; op0 = gen_rtx (MEM, SImode, copy_to_mode_reg (SImode, XEXP (op0, 0))); 738: ; } 739: ; 740: ; op1 = operands[1]; 741: ; if (GET_CODE (op1) == CONST 742: ; && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF 743: ; && SYMBOL_REF_FLAG (XEXP (XEXP (op1, 0), 0))) 744: ; { 745: ; op1 = gen_rtx (MEM, SImode, copy_to_mode_reg (SImode, XEXP (op1, 0))); 746: ; } 747: ; 748: ; emit_insn (gen_rtx (SET, VOIDmode, op0, op1)); 749: ; DONE; 750: ;}") 751: 752: ; 753: ; movhi instruction pattern(s). 754: ; 755: 756: (define_insn "" 757: [(set (match_operand:HI 0 "r_or_s_operand" "=g") 758: (match_operand:HI 1 "r_or_s_operand" "g"))] 759: "TARGET_CHAR_INSTRUCTIONS" 760: "* 761: { 762: check_label_emit (); 763: if (REG_P (operands[0])) 764: { 765: if (REG_P (operands[1])) 766: { 767: mvs_check_page (0, 2, 0); 768: return \"LR %0,%1\"; 769: } 770: if (operands[1] == const0_rtx) 771: { 772: CC_STATUS_INIT; 773: mvs_check_page (0, 2, 0); 774: return \"SLR %0,%0\"; 775: } 776: if (GET_CODE (operands[1]) == CONST_INT 777: && (unsigned) INTVAL (operands[1]) < 4096) 778: { 779: mvs_check_page (0, 4, 0); 780: return \"LA %0,%c1\"; 781: } 782: if (GET_CODE (operands[1]) == CONST_INT) 783: { 1.1.1.3 ! root 784: mvs_check_page (0, 4, 0); ! 785: return \"LH %0,%H1\"; 1.1 root 786: } 787: mvs_check_page (0, 4, 0); 788: return \"LH %0,%1\"; 789: } 790: else if (REG_P (operands[1])) 791: { 792: mvs_check_page (0, 4, 0); 793: return \"STH %1,%0\"; 794: } 795: if (GET_CODE (operands[1]) == CONST_INT) 796: { 797: mvs_check_page (0, 6, 0); 1.1.1.3 ! root 798: return \"MVC %O0(2,%R0),%H1\"; 1.1 root 799: } 800: mvs_check_page (0, 6, 0); 801: return \"MVC %O0(2,%R0),%1\"; 802: }") 803: 804: (define_insn "movhi" 805: [(set (match_operand:HI 0 "general_operand" "=d,m") 806: (match_operand:HI 1 "general_operand" "g,d"))] 807: "" 808: "* 809: { 810: check_label_emit (); 811: if (REG_P (operands[0])) 812: { 813: if (REG_P (operands[1])) 814: { 815: mvs_check_page (0, 2, 0); 816: return \"LR %0,%1\"; 817: } 818: if (operands[1] == const0_rtx) 819: { 820: CC_STATUS_INIT; 821: mvs_check_page (0, 2, 0); 822: return \"SLR %0,%0\"; 823: } 824: if (GET_CODE (operands[1]) == CONST_INT 825: && (unsigned) INTVAL (operands[1]) < 4096) 826: { 827: mvs_check_page (0, 4, 0); 828: return \"LA %0,%c1\"; 829: } 830: if (GET_CODE (operands[1]) == CONST_INT) 831: { 1.1.1.3 ! root 832: mvs_check_page (0, 4, 0); ! 833: return \"LH %0,%H1\"; 1.1 root 834: } 835: mvs_check_page (0, 4, 0); 836: return \"LH %0,%1\"; 837: } 838: mvs_check_page (0, 4, 0); 839: return \"STH %1,%0\"; 840: }") 841: 842: ; 843: ; movqi instruction pattern(s). 844: ; 845: 846: (define_insn "" 847: [(set (match_operand:QI 0 "r_or_s_operand" "=g") 848: (match_operand:QI 1 "r_or_s_operand" "g"))] 849: "TARGET_CHAR_INSTRUCTIONS" 850: "* 851: { 852: check_label_emit (); 853: if (REG_P (operands[0])) 854: { 855: if (REG_P (operands[1])) 856: { 857: mvs_check_page (0, 2, 0); 858: return \"LR %0,%1\"; 859: } 860: if (operands[1] == const0_rtx) 861: { 862: CC_STATUS_INIT; 863: mvs_check_page (0, 2, 0); 864: return \"SLR %0,%0\"; 865: } 866: if (GET_CODE (operands[1]) == CONST_INT) 867: { 868: if (INTVAL (operands[1]) >= 0) 869: { 870: mvs_check_page (0, 4, 0); 871: return \"LA %0,%c1\"; 872: } 873: mvs_check_page (0, 4, 0); 874: return \"L %0,=F'%c1'\"; 875: } 876: mvs_check_page (0, 4, 0); 877: return \"IC %0,%1\"; 878: } 879: else if (REG_P (operands[1])) 880: { 881: mvs_check_page (0, 4, 0); 882: return \"STC %1,%0\"; 883: } 884: else if (GET_CODE (operands[1]) == CONST_INT) 885: { 886: mvs_check_page (0, 4, 0); 887: return \"MVI %0,%B1\"; 888: } 889: mvs_check_page (0, 6, 0); 890: return \"MVC %O0(1,%R0),%1\"; 891: }") 892: 893: (define_insn "movqi" 894: [(set (match_operand:QI 0 "general_operand" "=d,m") 895: (match_operand:QI 1 "general_operand" "g,d"))] 896: "" 897: "* 898: { 899: check_label_emit (); 900: if (REG_P (operands[0])) 901: { 902: if (REG_P (operands[1])) 903: { 904: mvs_check_page (0, 2, 0); 905: return \"LR %0,%1\"; 906: } 907: if (operands[1] == const0_rtx) 908: { 909: CC_STATUS_INIT; 910: mvs_check_page (0, 2, 0); 911: return \"SLR %0,%0\"; 912: } 913: if (GET_CODE (operands[1]) == CONST_INT) 914: { 915: if (INTVAL (operands[1]) >= 0) 916: { 917: mvs_check_page (0, 4, 0); 918: return \"LA %0,%c1\"; 919: } 920: mvs_check_page (0, 4, 0); 921: return \"L %0,=F'%c1'\"; 922: } 923: mvs_check_page (0, 4, 0); 924: return \"IC %0,%1\"; 925: } 926: mvs_check_page (0, 4, 0); 927: return \"STC %1,%0\"; 928: }") 929: 930: ; 931: ; movestrictqi instruction pattern(s). 932: ; 933: 934: (define_insn "movestrictqi" 935: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=d")) 936: (match_operand:QI 1 "general_operand" "g"))] 937: "" 938: "* 939: { 940: check_label_emit (); 941: if (REG_P (operands[1])) 942: { 943: mvs_check_page (0, 8, 0); 944: return \"STC %1,140(,13)\;IC %0,140(,13)\"; 945: } 946: mvs_check_page (0, 4, 0); 947: return \"IC %0,%1\"; 948: }") 949: 950: ; 951: ; movstricthi instruction pattern(s). 952: ; 953: 954: (define_insn "" 955: [(set (strict_low_part (match_operand:HI 0 "register_operand" "=d")) 956: (match_operand:HI 1 "r_or_s_operand" "g"))] 957: "" 958: "* 959: { 960: check_label_emit (); 961: if (REG_P (operands[1])) 962: { 963: mvs_check_page (0, 8, 0); 964: return \"STH %1,140(,13)\;ICM %0,3,140(13)\"; 965: } 966: else if (GET_CODE (operands[1]) == CONST_INT) 967: { 1.1.1.3 ! root 968: mvs_check_page (0, 4, 0); ! 969: return \"ICM %0,3,%H1\"; 1.1 root 970: } 971: mvs_check_page (0, 4, 0); 972: return \"ICM %0,3,%1\"; 973: }") 974: 975: (define_insn "movestricthi" 976: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=dm")) 977: (match_operand:HI 1 "general_operand" "d"))] 978: "" 979: "* 980: { 981: check_label_emit (); 982: if (REG_P (operands[0])) 983: { 984: mvs_check_page (0, 8, 0); 985: return \"STH %1,140(,13)\;ICM %0,3,140(13)\"; 986: } 987: mvs_check_page (0, 4, 0); 988: return \"STH %1,%0\"; 989: }") 990: 991: ; 992: ; movdf instruction pattern(s). 993: ; 994: 995: (define_insn "" 996: [(set (match_operand:DF 0 "r_or_s_operand" "=fm,fm,*dm") 997: (match_operand:DF 1 "r_or_s_operand" "fmF,*dm,fmF"))] 998: "TARGET_CHAR_INSTRUCTIONS" 999: "* 1000: { 1001: check_label_emit (); 1002: if (FP_REG_P (operands[0])) 1003: { 1004: if (FP_REG_P (operands[1])) 1005: { 1006: mvs_check_page (0, 2, 0); 1007: return \"LDR %0,%1\"; 1008: } 1009: if (REG_P (operands[1])) 1010: { 1011: mvs_check_page (0, 8, 0); 1012: return \"STM %1,%N1,140(13)\;LD %0,140(,13)\"; 1013: } 1014: if (operands[1] == const0_rtx) 1015: { 1016: CC_STATUS_SET (operands[0], operands[1]); 1017: mvs_check_page (0, 2, 0); 1018: return \"SDR %0,%0\"; 1019: } 1020: mvs_check_page (0, 4, 0); 1021: return \"LD %0,%1\"; 1022: } 1023: if (REG_P (operands[0])) 1024: { 1025: if (FP_REG_P (operands[1])) 1026: { 1027: mvs_check_page (0, 12, 0); 1028: return \"STD %1,140(,13)\;LM %0,%N0,140(13)\"; 1029: } 1030: mvs_check_page (0, 4, 0); 1031: return \"LM %0,%N0,%1\"; 1032: } 1033: else if (FP_REG_P (operands[1])) 1034: { 1035: mvs_check_page (0, 4, 0); 1036: return \"STD %1,%0\"; 1037: } 1038: else if (REG_P (operands[1])) 1039: { 1040: mvs_check_page (0, 4, 0); 1041: return \"STM %1,%N1,%0\"; 1042: } 1043: mvs_check_page (0, 6, 0); 1044: return \"MVC %O0(8,%R0),%1\"; 1045: }") 1046: 1047: (define_insn "movdf" 1048: [(set (match_operand:DF 0 "general_operand" "=f,fm,m,*d") 1049: (match_operand:DF 1 "general_operand" "fmF,*d,f,fmF"))] 1050: "" 1051: "* 1052: { 1053: check_label_emit (); 1054: if (FP_REG_P (operands[0])) 1055: { 1056: if (FP_REG_P (operands[1])) 1057: { 1058: mvs_check_page (0, 2, 0); 1059: return \"LDR %0,%1\"; 1060: } 1061: if (REG_P (operands[1])) 1062: { 1063: mvs_check_page (0, 8, 0); 1064: return \"STM %1,%N1,140(13)\;LD %0,140(,13)\"; 1065: } 1066: if (operands[1] == const0_rtx) 1067: { 1068: CC_STATUS_SET (operands[0], operands[1]); 1069: mvs_check_page (0, 2, 0); 1070: return \"SDR %0,%0\"; 1071: } 1072: mvs_check_page (0, 4, 0); 1073: return \"LD %0,%1\"; 1074: } 1075: else if (REG_P (operands[0])) 1076: { 1077: if (FP_REG_P (operands[1])) 1078: { 1079: mvs_check_page (0, 12, 0); 1080: return \"STD %1,140(,13)\;LM %0,%N0,140(13)\"; 1081: } 1082: mvs_check_page (0, 4, 0); 1083: return \"LM %0,%N0,%1\"; 1084: } 1085: else if (FP_REG_P (operands[1])) 1086: { 1087: mvs_check_page (0, 4, 0); 1088: return \"STD %1,%0\"; 1089: } 1090: mvs_check_page (0, 4, 0); 1091: return \"STM %1,%N1,%0\"; 1092: }") 1093: 1094: ; 1095: ; movsf instruction pattern(s). 1096: ; 1097: 1098: (define_insn "" 1099: [(set (match_operand:SF 0 "r_or_s_operand" "=fm,fm,*dm") 1100: (match_operand:SF 1 "r_or_s_operand" "fmF,*dm,fmF"))] 1101: "TARGET_CHAR_INSTRUCTIONS" 1102: "* 1103: { 1104: check_label_emit (); 1105: if (FP_REG_P (operands[0])) 1106: { 1107: if (FP_REG_P (operands[1])) 1108: { 1109: mvs_check_page (0, 2, 0); 1110: return \"LER %0,%1\"; 1111: } 1112: if (REG_P (operands[1])) 1113: { 1114: mvs_check_page (0, 8, 0); 1115: return \"ST %1,140(,13)\;LE %0,140(,13)\"; 1116: } 1117: if (operands[1] == const0_rtx) 1118: { 1119: CC_STATUS_SET (operands[0], operands[1]); 1120: mvs_check_page (0, 2, 0); 1121: return \"SER %0,%0\"; 1122: } 1123: mvs_check_page (0, 4, 0); 1124: return \"LE %0,%1\"; 1125: } 1126: else if (REG_P (operands[0])) 1127: { 1128: if (FP_REG_P (operands[1])) 1129: { 1130: mvs_check_page (0, 8, 0); 1131: return \"STE %1,140(,13)\;L %0,140(,13)\"; 1132: } 1133: mvs_check_page (0, 4, 0); 1134: return \"L %0,%1\"; 1135: } 1136: else if (FP_REG_P (operands[1])) 1137: { 1138: mvs_check_page (0, 4, 0); 1139: return \"STE %1,%0\"; 1140: } 1141: else if (REG_P (operands[1])) 1142: { 1143: mvs_check_page (0, 4, 0); 1144: return \"ST %1,%0\"; 1145: } 1146: mvs_check_page (0, 6, 0); 1147: return \"MVC %O0(4,%R0),%1\"; 1148: }") 1149: 1150: (define_insn "movsf" 1151: [(set (match_operand:SF 0 "general_operand" "=f,fm,m,*d") 1152: (match_operand:SF 1 "general_operand" "fmF,*d,f,fmF"))] 1153: "" 1154: "* 1155: { 1156: check_label_emit (); 1157: if (FP_REG_P (operands[0])) 1158: { 1159: if (FP_REG_P (operands[1])) 1160: { 1161: mvs_check_page (0, 2, 0); 1162: return \"LER %0,%1\"; 1163: } 1164: if (REG_P (operands[1])) 1165: { 1166: mvs_check_page (0, 8, 0); 1167: return \"ST %1,140(,13)\;LE %0,140(,13)\"; 1168: } 1169: if (operands[1] == const0_rtx) 1170: { 1171: CC_STATUS_SET (operands[0], operands[1]); 1172: mvs_check_page (0, 2, 0); 1173: return \"SER %0,%0\"; 1174: } 1175: mvs_check_page (0, 4, 0); 1176: return \"LE %0,%1\"; 1177: } 1178: else if (REG_P (operands[0])) 1179: { 1180: if (FP_REG_P (operands[1])) 1181: { 1182: mvs_check_page (0, 8, 0); 1183: return \"STE %1,140(,13)\;L %0,140(,13)\"; 1184: } 1185: mvs_check_page (0, 4, 0); 1186: return \"L %0,%1\"; 1187: } 1188: else if (FP_REG_P (operands[1])) 1189: { 1190: mvs_check_page (0, 4, 0); 1191: return \"STE %1,%0\"; 1192: } 1193: mvs_check_page (0, 4, 0); 1194: return \"ST %1,%0\"; 1195: }") 1196: 1197: ; 1198: ; movstrsi instruction pattern(s). 1199: ; 1200: 1201: (define_expand "movstrsi" 1202: [(set (match_operand:BLK 0 "general_operand" "") 1203: (match_operand:BLK 1 "general_operand" "")) 1204: (use (match_operand:SI 2 "general_operand" "")) 1205: (match_operand 3 "" "")] 1206: "" 1207: " 1208: { 1209: rtx op0, op1; 1210: 1211: op0 = XEXP (operands[0], 0); 1212: if (GET_CODE (op0) == REG 1213: || (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 0)) == REG 1214: && GET_CODE (XEXP (op0, 1)) == CONST_INT 1215: && (unsigned) INTVAL (XEXP (op0, 1)) < 4096)) 1216: { 1217: op0 = operands[0]; 1218: } 1219: else 1220: { 1221: op0 = gen_rtx (MEM, BLKmode, copy_to_mode_reg (SImode, op0)); 1222: } 1223: 1224: op1 = XEXP (operands[1], 0); 1225: if (GET_CODE (op1) == REG 1226: || (GET_CODE (op1) == PLUS && GET_CODE (XEXP (op1, 0)) == REG 1227: && GET_CODE (XEXP (op1, 1)) == CONST_INT 1228: && (unsigned) INTVAL (XEXP (op1, 1)) < 4096)) 1229: { 1230: op1 = operands[1]; 1231: } 1232: else 1233: { 1234: op1 = gen_rtx (MEM, BLKmode, copy_to_mode_reg (SImode, op1)); 1235: } 1236: 1237: if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 256) 1238: { 1239: emit_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, 1240: gen_rtx (SET, VOIDmode, op0, op1), 1241: gen_rtx (USE, VOIDmode, operands[2])))); 1242: } 1243: else 1244: { 1245: rtx reg1 = gen_reg_rtx (DImode); 1246: rtx reg2 = gen_reg_rtx (DImode); 1247: rtx subreg = gen_rtx (SUBREG, SImode, reg1, 1); 1248: 1249: emit_insn (gen_rtx (SET, VOIDmode, subreg, operands[2])); 1250: emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode, reg2, 1), 1251: subreg)); 1252: emit_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (5, 1253: gen_rtx (SET, VOIDmode, op0, op1), 1254: gen_rtx (USE, VOIDmode, reg1), 1255: gen_rtx (USE, VOIDmode, reg2), 1256: gen_rtx (CLOBBER, VOIDmode, reg1), 1257: gen_rtx (CLOBBER, VOIDmode, reg2)))); 1258: } 1259: DONE; 1260: }") 1261: 1262: ; Move a block that is less than 256 bytes in length. 1263: 1264: (define_insn "" 1265: [(set (match_operand:BLK 0 "s_operand" "=m") 1266: (match_operand:BLK 1 "s_operand" "m")) 1267: (use (match_operand 2 "immediate_operand" "I"))] 1268: "((unsigned) INTVAL (operands[2]) < 256)" 1269: "* 1270: { 1271: check_label_emit (); 1272: mvs_check_page (0, 6, 0); 1273: return \"MVC %O0(%c2,%R0),%1\"; 1274: }") 1275: 1276: ; Move a block that is larger than 255 bytes in length. 1277: 1278: (define_insn "" 1279: [(set (match_operand:BLK 0 "general_operand" "=m") 1280: (match_operand:BLK 1 "general_operand" "m")) 1281: (use (match_operand:DI 2 "register_operand" "d")) 1282: (use (match_operand:DI 3 "register_operand" "d")) 1283: (clobber (match_dup 2)) 1284: (clobber (match_dup 3))] 1285: "" 1286: "* 1287: { 1288: check_label_emit (); 1289: mvs_check_page (0, 10, 0); 1290: return \"LA %2,%0\;LA %3,%1\;MVCL %2,%3\"; 1291: }") 1292: 1293: ;; 1294: ;;- Conversion instructions. 1295: ;; 1296: 1297: ; 1298: ; extendsidi2 instruction pattern(s). 1299: ; 1300: 1301: (define_expand "extendsidi2" 1302: [(set (match_operand:DI 0 "general_operand" "") 1303: (sign_extend:DI (match_operand:SI 1 "general_operand" "")))] 1304: "" 1305: " 1306: { 1307: if (GET_CODE (operands[1]) != CONST_INT) 1308: { 1309: emit_insn (gen_rtx (SET, VOIDmode, 1310: operand_subword (operands[0], 0, 1, DImode), operands[1])); 1311: emit_insn (gen_rtx (SET, VOIDmode, operands[0], 1312: gen_rtx (ASHIFTRT, DImode, operands[0], 1313: gen_rtx (CONST_INT, SImode, 32)))); 1314: } 1315: else 1316: { 1317: if (INTVAL (operands[1]) < 0) 1318: { 1319: emit_insn (gen_rtx (SET, VOIDmode, 1320: operand_subword (operands[0], 0, 1, DImode), 1321: gen_rtx (CONST_INT, SImode, -1))); 1322: } 1323: else 1324: { 1325: emit_insn (gen_rtx (SET, VOIDmode, 1326: operand_subword (operands[0], 0, 1, DImode), 1327: gen_rtx (CONST_INT, SImode, 0))); 1328: } 1329: emit_insn (gen_rtx (SET, VOIDmode, gen_lowpart (SImode, operands[0]), 1330: operands[1])); 1331: } 1332: DONE; 1333: }") 1334: 1335: ; 1336: ; extendhisi2 instruction pattern(s). 1337: ; 1338: 1339: (define_insn "extendhisi2" 1340: [(set (match_operand:SI 0 "general_operand" "=d,m") 1341: (sign_extend:SI (match_operand:HI 1 "general_operand" "g,d")))] 1342: "" 1343: "* 1344: { 1345: check_label_emit (); 1346: if (REG_P (operands[0])) 1347: { 1348: if (REG_P (operands[1])) 1349: if (REGNO (operands[0]) != REGNO (operands[1])) 1350: { 1351: mvs_check_page (0, 2, 0); 1352: return \"LR %0,%1\;SLL %0,16\;SRA %0,16\"; 1353: } 1354: else 1355: return \"\"; /* Should be empty. 16-bits regs are always 32-bits. */ 1356: if (operands[1] == const0_rtx) 1357: { 1358: CC_STATUS_INIT; 1359: mvs_check_page (0, 2, 0); 1360: return \"SLR %0,%0\"; 1361: } 1362: if (GET_CODE (operands[1]) == CONST_INT 1363: && (unsigned) INTVAL (operands[1]) < 4096) 1364: { 1365: mvs_check_page (0, 4, 0); 1366: return \"LA %0,%c1\"; 1367: } 1368: if (GET_CODE (operands[1]) == CONST_INT) 1369: { 1.1.1.3 ! root 1370: mvs_check_page (0, 4, 0); ! 1371: return \"LH %0,%H1\"; 1.1 root 1372: } 1373: mvs_check_page (0, 4, 0); 1374: return \"LH %0,%1\"; 1375: } 1376: mvs_check_page (0, 4, 0); 1.1.1.3 ! root 1377: return \"SLL %1,16\;SRA %1,16\;ST %1,%0\"; 1.1 root 1378: }") 1379: 1380: ; 1381: ; extendqisi2 instruction pattern(s). 1382: ; 1383: 1384: (define_insn "extendqisi2" 1385: [(set (match_operand:SI 0 "general_operand" "=d") 1386: (sign_extend:SI (match_operand:QI 1 "general_operand" "0mi")))] 1387: "" 1388: "* 1389: { 1390: check_label_emit (); 1391: CC_STATUS_SET (operands[0], operands[1]); 1392: if (REG_P (operands[1])) 1393: { 1394: mvs_check_page (0, 8, 0); 1395: return \"SLL %0,24\;SRA %0,24\"; 1396: } 1397: if (s_operand (operands[1])) 1398: { 1399: mvs_check_page (0, 8, 0); 1400: return \"ICM %0,8,%1\;SRA %0,24\"; 1401: } 1402: mvs_check_page (0, 12, 0); 1403: return \"IC %0,%1\;SLL %0,24\;SRA %0,24\"; 1404: }") 1405: 1406: ; 1407: ; extendqihi2 instruction pattern(s). 1408: ; 1409: 1410: (define_insn "extendqihi2" 1411: [(set (match_operand:HI 0 "general_operand" "=d") 1412: (sign_extend:HI (match_operand:QI 1 "general_operand" "0m")))] 1413: "" 1414: "* 1415: { 1416: check_label_emit (); 1417: CC_STATUS_SET (operands[0], operands[1]); 1418: if (REG_P (operands[1])) 1419: { 1420: mvs_check_page (0, 8, 0); 1421: return \"SLL %0,24\;SRA %0,24\"; 1422: } 1423: if (s_operand (operands[1])) 1424: { 1425: mvs_check_page (0, 8, 0); 1426: return \"ICM %0,8,%1\;SRA %0,24\"; 1427: } 1428: mvs_check_page (0, 12, 0); 1429: return \"IC %0,%1\;SLL %0,24\;SRA %0,24\"; 1430: }") 1431: 1432: ; 1433: ; zero_extendsidi2 instruction pattern(s). 1434: ; 1435: 1436: (define_expand "zero_extendsidi2" 1437: [(set (match_operand:DI 0 "general_operand" "") 1438: (zero_extend:DI (match_operand:SI 1 "general_operand" "")))] 1439: "" 1440: " 1441: { 1442: emit_insn (gen_rtx (SET, VOIDmode, 1443: operand_subword (operands[0], 0, 1, DImode), operands[1])); 1444: emit_insn (gen_rtx (SET, VOIDmode, operands[0], 1445: gen_rtx (LSHIFTRT, DImode, operands[0], 1446: gen_rtx (CONST_INT, SImode, 32)))); 1447: DONE; 1448: }") 1449: 1450: ; 1451: ; zero_extendhisi2 instruction pattern(s). 1452: ; 1453: 1454: (define_insn "zero_extendhisi2" 1455: [(set (match_operand:SI 0 "general_operand" "=d") 1456: (zero_extend:SI (match_operand:HI 1 "general_operand" "0")))] 1457: "" 1458: "* 1459: { 1460: check_label_emit (); 1461: CC_STATUS_SET (operands[0], operands[1]); 1462: mvs_check_page (0, 4, 4); 1463: return \"N %1,=X'0000FFFF'\"; 1464: }") 1465: 1466: ; 1467: ; zero_extendqisi2 instruction pattern(s). 1468: ; 1469: 1470: (define_insn "zero_extendqisi2" 1471: [(set (match_operand:SI 0 "general_operand" "=d,&d") 1472: (zero_extend:SI (match_operand:QI 1 "general_operand" "0i,m")))] 1473: "" 1474: "* 1475: { 1476: check_label_emit (); 1477: if (REG_P (operands[1])) 1478: { 1479: CC_STATUS_SET (operands[0], operands[1]); 1480: mvs_check_page (0, 4, 4); 1481: return \"N %0,=X'000000FF'\"; 1482: } 1483: if (GET_CODE (operands[1]) == CONST_INT) 1484: { 1485: mvs_check_page (0, 4, 0); 1486: return \"LA %0,%c1\"; 1487: } 1488: CC_STATUS_INIT; 1489: mvs_check_page (0, 8, 0); 1490: return \"SLR %0,%0\;IC %0,%1\"; 1491: }") 1492: 1493: ; 1494: ; zero_extendqihi2 instruction pattern(s). 1495: ; 1496: 1497: (define_insn "zero_extendqihi2" 1498: [(set (match_operand:HI 0 "general_operand" "=d,&d") 1499: (zero_extend:HI (match_operand:QI 1 "general_operand" "0i,m")))] 1500: "" 1501: "* 1502: { 1503: check_label_emit (); 1504: if (REG_P (operands[1])) 1505: { 1506: CC_STATUS_SET (operands[0], operands[1]); 1507: mvs_check_page (0, 4, 4); 1508: return \"N %0,=X'000000FF'\"; 1509: } 1510: if (GET_CODE (operands[1]) == CONST_INT) 1511: { 1512: mvs_check_page (0, 4, 0); 1513: return \"LA %0,%c1\"; 1514: } 1515: CC_STATUS_INIT; 1516: mvs_check_page (0, 8, 0); 1517: return \"SLR %0,%0\;IC %0,%1\"; 1518: }") 1519: 1520: ; 1521: ; truncsihi2 instruction pattern(s). 1522: ; 1523: 1524: (define_insn "truncsihi2" 1525: [(set (match_operand:HI 0 "general_operand" "=d,m") 1526: (truncate:HI (match_operand:SI 1 "general_operand" "0,d")))] 1527: "" 1528: "* 1529: { 1530: check_label_emit (); 1531: if (REG_P (operands[0])) 1532: { 1533: CC_STATUS_SET (operands[0], operands[1]); 1534: mvs_check_page (0, 8, 0); 1535: return \"SLL %0,16\;SRA %0,16\"; 1536: } 1537: mvs_check_page (0, 4, 0); 1538: return \"STH %1,%0\"; 1539: }") 1540: 1541: ; 1542: ; fix_truncdfsi2 instruction pattern(s). 1543: ; 1544: 1545: (define_insn "fix_truncdfsi2" 1546: [(set (match_operand:SI 0 "general_operand" "=d") 1547: (fix:SI (truncate:DF (match_operand:DF 1 "general_operand" "f")))) 1548: (clobber (reg:DF 16))] 1549: "" 1550: "* 1551: { 1552: check_label_emit (); 1553: CC_STATUS_INIT; 1554: if (REGNO (operands[1]) == 16) 1555: { 1556: mvs_check_page (0, 12, 8); 1557: return \"AD 0,=XL8'4F08000000000000'\;STD 0,140(,13)\;L %0,144(,13)\"; 1558: } 1559: mvs_check_page (0, 14, 8); 1560: return \"LDR 0,%1\;AD 0,=XL8'4F08000000000000'\;STD 0,140(,13)\;L %0,144(,13)\"; 1561: }") 1562: 1563: ; 1564: ; floatsidf2 instruction pattern(s). 1565: ; 1566: ; Uses the float field of the TCA. 1567: ; 1568: 1569: (define_insn "floatsidf2" 1570: [(set (match_operand:DF 0 "general_operand" "=f") 1571: (float:DF (match_operand:SI 1 "general_operand" "d")))] 1572: "" 1573: "* 1574: { 1575: check_label_emit (); 1576: CC_STATUS_INIT; 1577: mvs_check_page (0, 16, 8); 1578: return \"ST %1,508(,12)\;XI 508(12),128\;LD %0,504(,12)\;SD %0,=XL8'4E00000080000000'\"; 1579: }") 1580: 1581: ; 1582: ; truncdfsf2 instruction pattern(s). 1583: ; 1584: 1585: (define_insn "truncdfsf2" 1586: [(set (match_operand:SF 0 "general_operand" "=f") 1587: (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))] 1588: "" 1589: "* 1590: { 1591: check_label_emit (); 1592: mvs_check_page (0, 2, 0); 1593: return \"LRER %0,%1\"; 1594: }") 1595: 1596: ; 1597: ; extendsfdf2 instruction pattern(s). 1598: ; 1599: 1600: (define_insn "extendsfdf2" 1601: [(set (match_operand:DF 0 "general_operand" "=f") 1602: (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))] 1603: "" 1604: "* 1605: { 1606: check_label_emit (); 1607: CC_STATUS_SET (0, const0_rtx); 1608: if (FP_REG_P (operands[1])) 1609: { 1610: if (REGNO (operands[0]) == REGNO (operands[1])) 1611: { 1612: mvs_check_page (0, 10, 0); 1613: return \"STE %1,140(,13)\;SDR %0,%0\;LE %0,140(,13)\"; 1614: } 1615: mvs_check_page (0, 4, 0); 1616: return \"SDR %0,%0\;LER %0,%1\"; 1617: } 1618: mvs_check_page (0, 6, 0); 1619: return \"SDR %0,%0\;LE %0,%1\"; 1620: }") 1621: 1622: ;; 1623: ;;- Add instructions. 1624: ;; 1625: 1626: ; 1627: ; adddi3 instruction pattern(s). 1628: ; 1629: 1630: (define_expand "adddi3" 1631: [(set (match_operand:DI 0 "general_operand" "") 1632: (plus:DI (match_operand:DI 1 "general_operand" "") 1633: (match_operand:DI 2 "general_operand" "")))] 1634: "" 1635: " 1636: { 1637: rtx label = gen_label_rtx (); 1638: rtx op0_high = operand_subword (operands[0], 0, 1, DImode); 1639: rtx op0_low = gen_lowpart (SImode, operands[0]); 1640: 1641: emit_insn (gen_rtx (SET, VOIDmode, op0_high, 1642: gen_rtx (PLUS, SImode, 1643: operand_subword (operands[1], 0, 1, DImode), 1644: operand_subword (operands[2], 0, 1, DImode)))); 1645: emit_jump_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, 1646: gen_rtx (SET, VOIDmode, op0_low, 1647: gen_rtx (PLUS, SImode, gen_lowpart (SImode, operands[1]), 1648: gen_lowpart (SImode, operands[2]))), 1649: gen_rtx (USE, VOIDmode, gen_rtx (LABEL_REF, VOIDmode, label))))); 1650: emit_insn (gen_rtx (SET, VOIDmode, op0_high, 1651: gen_rtx (PLUS, SImode, op0_high, 1652: gen_rtx (CONST_INT, SImode, 1)))); 1653: emit_label (label); 1654: DONE; 1655: }") 1656: 1657: (define_insn "" 1658: [(set (match_operand:SI 0 "general_operand" "=d") 1659: (plus:SI (match_operand:SI 1 "general_operand" "%0") 1660: (match_operand:SI 2 "general_operand" "g"))) 1661: (use (label_ref (match_operand 3 "" "")))] 1662: "" 1663: "* 1664: { 1665: int onpage; 1666: 1667: check_label_emit (); 1668: onpage = mvs_check_label (CODE_LABEL_NUMBER (operands[3])); 1669: if (REG_P (operands[2])) 1670: { 1671: if (!onpage) 1672: { 1673: mvs_check_page (0, 8, 4); 1674: return \"ALR %0,%2\;L 14,=A(%l3)\;BCR 12,14\"; 1675: } 1676: if (mvs_check_page (0, 6, 0)) 1677: { 1678: mvs_check_page (0, 2, 4); 1679: return \"ALR %0,%2\;L 14,=A(%l3)\;BCR 12,14\"; 1680: } 1681: return \"ALR %0,%2\;BC 12,%l3\"; 1682: } 1683: if (!onpage) 1684: { 1685: mvs_check_page (0, 10, 4); 1686: return \"AL %0,%2\;L 14,=A(%l3)\;BCR 12,14\"; 1687: } 1688: if (mvs_check_page (0, 8 ,0)) 1689: { 1690: mvs_check_page (0, 2, 4); 1691: return \"AL %0,%2\;L 14,=A(%l3)\;BCR 12,14\"; 1692: } 1693: return \"AL %0,%2\;BC 12,%l3\"; 1694: }") 1695: 1696: ; 1697: ; addsi3 instruction pattern(s). 1698: ; 1699: ; The following insn is used when it is known that operand one is an address, 1700: ; frame, stack or argument pointer, and operand two is a constant that is 1701: ; small enough to fit in the displacement field. 1702: ; Notice that we can't allow the frame pointer to used as a normal register 1703: ; because of this insn. 1704: ; 1705: 1706: (define_insn "" 1707: [(set (match_operand:SI 0 "register_operand" "=d") 1708: (plus:SI (match_operand:SI 1 "general_operand" "%a") 1709: (match_operand:SI 2 "immediate_operand" "J")))] 1710: "((REGNO (operands[1]) == FRAME_POINTER_REGNUM || REGNO (operands[1]) == ARG_POINTER_REGNUM || REGNO (operands[1]) == STACK_POINTER_REGNUM) && (unsigned) INTVAL (operands[2]) < 4096)" 1711: "* 1712: { 1713: check_label_emit (); 1714: CC_STATUS_INIT; 1715: mvs_check_page (0, 4, 0); 1716: return \"LA %0,%c2(,%1)\"; 1717: }") 1718: 1719: ; This insn handles additions that are relative to the frame pointer. 1720: 1721: (define_insn "" 1722: [(set (match_operand:SI 0 "register_operand" "=d") 1723: (plus:SI (match_operand:SI 1 "register_operand" "%a") 1724: (match_operand:SI 2 "immediate_operand" "i")))] 1725: "REGNO (operands[1]) == FRAME_POINTER_REGNUM" 1726: "* 1727: { 1728: check_label_emit (); 1729: if ((unsigned) INTVAL (operands[2]) < 4096) 1730: { 1731: mvs_check_page (0, 4, 0); 1732: return \"LA %0,%c2(,%1)\"; 1733: } 1734: if (REGNO (operands[1]) == REGNO (operands[0])) 1735: { 1736: mvs_check_page (0, 4, 0); 1737: return \"A %0,%2\"; 1738: } 1739: mvs_check_page (0, 6, 0); 1740: return \"L %0,%2\;AR %0,%1\"; 1741: }") 1742: 1743: (define_insn "addsi3" 1744: [(set (match_operand:SI 0 "general_operand" "=d") 1745: (plus:SI (match_operand:SI 1 "general_operand" "%0") 1746: (match_operand:SI 2 "general_operand" "g")))] 1747: "" 1748: "* 1749: { 1750: check_label_emit (); 1751: if (REG_P (operands[2])) 1752: { 1753: mvs_check_page (0, 2, 0); 1754: return \"AR %0,%2\"; 1755: } 1756: if (GET_CODE (operands[2]) == CONST_INT) 1757: { 1758: if (INTVAL (operands[2]) == -1) 1759: { 1760: CC_STATUS_INIT; 1761: mvs_check_page (0, 2, 0); 1762: return \"BCTR %0,0\"; 1763: } 1764: } 1765: mvs_check_page (0, 4, 0); 1766: return \"A %0,%2\"; 1767: }") 1768: 1769: ; 1770: ; addhi3 instruction pattern(s). 1771: ; 1772: 1773: (define_insn "addhi3" 1774: [(set (match_operand:HI 0 "general_operand" "=d") 1775: (plus:HI (match_operand:HI 1 "general_operand" "%0") 1776: (match_operand:HI 2 "general_operand" "dmi")))] 1777: "" 1778: "* 1779: { 1780: check_label_emit (); 1781: if (REG_P (operands[2])) 1782: { 1.1.1.3 ! root 1783: mvs_check_page (0, 8, 0); 1.1 root 1784: return \"STH %2,140(,13)\;AH %0,140(,13)\"; 1785: } 1786: if (GET_CODE (operands[2]) == CONST_INT) 1787: { 1788: if (INTVAL (operands[2]) == -1) 1789: { 1790: CC_STATUS_INIT; 1791: mvs_check_page (0, 2, 0); 1792: return \"BCTR %0,0\"; 1793: } 1.1.1.3 ! root 1794: mvs_check_page (0, 4, 0); ! 1795: return \"AH %0,%H2\"; 1.1 root 1796: } 1797: mvs_check_page (0, 4, 0); 1798: return \"AH %0,%2\"; 1799: }") 1800: 1801: ; 1802: ; addqi3 instruction pattern(s). 1803: ; 1804: 1805: (define_insn "addqi3" 1806: [(set (match_operand:QI 0 "general_operand" "=d") 1807: (plus:QI (match_operand:QI 1 "general_operand" "%a") 1808: (match_operand:QI 2 "general_operand" "ai")))] 1809: "" 1810: "* 1811: { 1812: check_label_emit (); 1813: CC_STATUS_INIT; 1814: mvs_check_page (0, 4, 0); 1815: if (REG_P (operands[2])) 1816: return \"LA %0,0(%1,%2)\"; 1817: return \"LA %0,%B2(,%1)\"; 1818: }") 1819: 1820: ; 1821: ; adddf3 instruction pattern(s). 1822: ; 1823: 1824: (define_insn "adddf3" 1825: [(set (match_operand:DF 0 "general_operand" "=f") 1826: (plus:DF (match_operand:DF 1 "general_operand" "%0") 1827: (match_operand:DF 2 "general_operand" "fmF")))] 1828: "" 1829: "* 1830: { 1831: check_label_emit (); 1832: if (FP_REG_P (operands[2])) 1833: { 1834: mvs_check_page (0, 2, 0); 1835: return \"ADR %0,%2\"; 1836: } 1837: mvs_check_page (0, 4, 0); 1838: return \"AD %0,%2\"; 1839: }") 1840: 1841: ; 1842: ; addsf3 instruction pattern(s). 1843: ; 1844: 1845: (define_insn "addsf3" 1846: [(set (match_operand:SF 0 "general_operand" "=f") 1847: (plus:SF (match_operand:SF 1 "general_operand" "%0") 1848: (match_operand:SF 2 "general_operand" "fmF")))] 1849: "" 1850: "* 1851: { 1852: check_label_emit (); 1853: if (FP_REG_P (operands[2])) 1854: { 1855: mvs_check_page (0, 2, 0); 1856: return \"AER %0,%2\"; 1857: } 1858: mvs_check_page (0, 4, 0); 1859: return \"AE %0,%2\"; 1860: }") 1861: 1862: ;; 1863: ;;- Subtract instructions. 1864: ;; 1865: 1866: ; 1867: ; subdi3 instruction pattern(s). 1868: ; 1869: 1870: (define_expand "subdi3" 1871: [(set (match_operand:DI 0 "general_operand" "") 1872: (minus:DI (match_operand:DI 1 "general_operand" "") 1873: (match_operand:DI 2 "general_operand" "")))] 1874: "" 1875: " 1876: { 1877: rtx label = gen_label_rtx (); 1878: rtx op0_high = operand_subword (operands[0], 0, 1, DImode); 1879: rtx op0_low = gen_lowpart (SImode, operands[0]); 1880: 1881: emit_insn (gen_rtx (SET, VOIDmode, op0_high, 1882: gen_rtx (MINUS, SImode, 1883: operand_subword (operands[1], 0, 1, DImode), 1884: operand_subword (operands[2], 0, 1, DImode)))); 1885: emit_jump_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, 1886: gen_rtx (SET, VOIDmode, op0_low, 1887: gen_rtx (MINUS, SImode, 1888: gen_lowpart (SImode, operands[1]), 1889: gen_lowpart (SImode, operands[2]))), 1890: gen_rtx (USE, VOIDmode, 1891: gen_rtx (LABEL_REF, VOIDmode, label))))); 1892: emit_insn (gen_rtx (SET, VOIDmode, op0_high, 1893: gen_rtx (MINUS, SImode, op0_high, 1894: gen_rtx (CONST_INT, SImode, 1)))); 1895: emit_label (label); 1896: DONE; 1897: }") 1898: 1899: (define_insn "" 1900: [(set (match_operand:SI 0 "general_operand" "=d") 1901: (minus:SI (match_operand:SI 1 "general_operand" "0") 1902: (match_operand:SI 2 "general_operand" "g"))) 1903: (use (label_ref (match_operand 3 "" "")))] 1904: "" 1905: "* 1906: { 1907: int onpage; 1908: 1909: check_label_emit (); 1910: CC_STATUS_INIT; 1911: onpage = mvs_check_label (CODE_LABEL_NUMBER (operands[3])); 1912: if (REG_P (operands[2])) 1913: { 1914: if (!onpage) 1915: { 1916: mvs_check_page (0, 8, 4); 1917: return \"SLR %0,%2\;L 14,=A(%l3)\;BCR 12,14\"; 1918: } 1919: if (mvs_check_page (0, 6, 0)) 1920: { 1921: mvs_check_page (0, 2, 4); 1922: return \"SLR %0,%2\;L 14,=A(%l3)\;BCR 12,14\"; 1923: } 1924: return \"SLR %0,%2\;BC 12,%l3\"; 1925: } 1926: if (!onpage) 1927: { 1928: mvs_check_page (0, 10, 4); 1929: return \"SL %0,%2\;L 14,=A(%l3)\;BCR 12,14\"; 1930: } 1931: if (mvs_check_page (0, 8, 0)) 1932: { 1933: mvs_check_page (0, 2, 4); 1934: return \"SL %0,%2\;L 14,=A(%l3)\;BCR 12,14\"; 1935: } 1936: return \"SL %0,%2\;BC 12,%l3\"; 1937: }") 1938: 1939: ; 1940: ; subsi3 instruction pattern(s). 1941: ; 1942: 1943: (define_insn "subsi3" 1944: [(set (match_operand:SI 0 "general_operand" "=d") 1945: (minus:SI (match_operand:SI 1 "general_operand" "0") 1946: (match_operand:SI 2 "general_operand" "g")))] 1947: "" 1948: "* 1949: { 1950: check_label_emit (); 1951: if (REG_P (operands[2])) 1952: { 1953: mvs_check_page (0, 2, 0); 1954: return \"SR %0,%2\"; 1955: } 1956: if (operands[2] == const1_rtx) 1957: { 1958: CC_STATUS_INIT; 1959: mvs_check_page (0, 2, 0); 1960: return \"BCTR %0,0\"; 1961: } 1962: mvs_check_page (0, 4, 0); 1963: return \"S %0,%2\"; 1964: }") 1965: 1966: ; 1967: ; subhi3 instruction pattern(s). 1968: ; 1969: 1970: (define_insn "subhi3" 1971: [(set (match_operand:HI 0 "general_operand" "=d") 1972: (minus:HI (match_operand:HI 1 "general_operand" "0") 1973: (match_operand:HI 2 "general_operand" "g")))] 1974: "" 1975: "* 1976: { 1977: check_label_emit (); 1978: if (REG_P (operands[2])) 1979: { 1.1.1.3 ! root 1980: mvs_check_page (0, 8, 0); 1.1 root 1981: return \"STH %2,140(,13)\;SH %0,140(,13)\"; 1982: } 1983: if (operands[2] == const1_rtx) 1984: { 1985: CC_STATUS_INIT; 1986: mvs_check_page (0, 2, 0); 1987: return \"BCTR %0,0\"; 1988: } 1989: if (GET_CODE (operands[2]) == CONST_INT) 1990: { 1.1.1.3 ! root 1991: mvs_check_page (0, 4, 0); ! 1992: return \"SH %0,%H2\"; 1.1 root 1993: } 1994: mvs_check_page (0, 4, 0); 1995: return \"SH %0,%2\"; 1996: }") 1997: 1998: ; 1999: ; subqi3 instruction pattern(s). 2000: ; 2001: 2002: (define_expand "subqi3" 2003: [(set (match_operand:QI 0 "general_operand" "=d") 1.1.1.2 root 2004: (minus:QI (match_operand:QI 1 "general_operand" "0") 1.1 root 2005: (match_operand:QI 2 "general_operand" "di")))] 2006: "" 2007: " 2008: { 2009: if (REG_P (operands[2])) 2010: { 2011: emit_insn (gen_rtx (SET, VOIDmode, operands[0], 2012: gen_rtx (MINUS, QImode, operands[1], operands[2]))); 2013: } 2014: else 2015: { 2016: emit_insn (gen_rtx (SET, VOIDmode, operands[0], 2017: gen_rtx (PLUS, QImode, operands[1], 2018: negate_rtx (QImode, operands[2])))); 2019: } 2020: DONE; 2021: }") 2022: 2023: (define_insn "" 2024: [(set (match_operand:QI 0 "register_operand" "=d") 1.1.1.2 root 2025: (minus:QI (match_operand:QI 1 "register_operand" "0") 1.1 root 2026: (match_operand:QI 2 "register_operand" "d")))] 2027: "" 2028: "* 2029: { 2030: check_label_emit (); 2031: CC_STATUS_INIT; 2032: mvs_check_page (0, 2, 0); 2033: return \"SR %0,%2\"; 2034: }") 2035: 2036: ; 2037: ; subdf3 instruction pattern(s). 2038: ; 2039: 2040: (define_insn "subdf3" 2041: [(set (match_operand:DF 0 "general_operand" "=f") 2042: (minus:DF (match_operand:DF 1 "general_operand" "0") 2043: (match_operand:DF 2 "general_operand" "fmF")))] 2044: "" 2045: "* 2046: { 2047: check_label_emit (); 2048: if (FP_REG_P (operands[2])) 2049: { 2050: mvs_check_page (0, 2, 0); 2051: return \"SDR %0,%2\"; 2052: } 2053: mvs_check_page (0, 4, 0); 2054: return \"SD %0,%2\"; 2055: }") 2056: 2057: ; 2058: ; subsf3 instruction pattern(s). 2059: ; 2060: 2061: (define_insn "subsf3" 2062: [(set (match_operand:SF 0 "general_operand" "=f") 2063: (minus:SF (match_operand:SF 1 "general_operand" "0") 2064: (match_operand:SF 2 "general_operand" "fmF")))] 2065: "" 2066: "* 2067: { 2068: check_label_emit (); 2069: if (FP_REG_P (operands[2])) 2070: { 2071: mvs_check_page (0, 2, 0); 2072: return \"SER %0,%2\"; 2073: } 2074: mvs_check_page (0, 4, 0); 2075: return \"SE %0,%2\"; 2076: }") 2077: 2078: ;; 2079: ;;- Multiply instructions. 2080: ;; 2081: 2082: ; 2083: ; mulsi3 instruction pattern(s). 2084: ; 2085: 2086: (define_expand "mulsi3" 2087: [(set (match_operand:SI 0 "general_operand" "") 2088: (mult:SI (match_operand:SI 1 "general_operand" "") 2089: (match_operand:SI 2 "general_operand" "")))] 2090: "" 2091: " 2092: { 2093: if (GET_CODE (operands[1]) == CONST_INT 2094: && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')) 2095: { 2096: emit_insn (gen_rtx (SET, VOIDmode, operands[0], 2097: gen_rtx (MULT, SImode, operands[2], operands[1]))); 2098: } 2099: else if (GET_CODE (operands[2]) == CONST_INT 2100: && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')) 2101: { 2102: emit_insn (gen_rtx (SET, VOIDmode, operands[0], 2103: gen_rtx (MULT, SImode, operands[1], operands[2]))); 2104: } 2105: else 2106: { 2107: rtx r = gen_reg_rtx (DImode); 2108: 2109: emit_insn (gen_rtx (SET, VOIDmode, 2110: gen_rtx (SUBREG, SImode, r, 1), operands[1])); 2111: emit_insn (gen_rtx (SET, VOIDmode, r, 2112: gen_rtx (MULT, SImode, r, operands[2]))); 2113: emit_insn (gen_rtx (SET, VOIDmode, operands[0], 2114: gen_rtx (SUBREG, SImode, r, 1))); 2115: } 2116: DONE; 2117: }") 2118: 2119: (define_insn "" 2120: [(set (match_operand:SI 0 "register_operand" "=d") 2121: (mult:SI (match_operand:SI 1 "general_operand" "%0") 2122: (match_operand:SI 2 "immediate_operand" "K")))] 2123: "" 2124: "* 2125: { 2126: check_label_emit (); 2127: mvs_check_page (0, 4, 0); 1.1.1.3 ! root 2128: return \"MH %0,%H2\"; 1.1 root 2129: }") 2130: 2131: (define_insn "" 2132: [(set (match_operand:DI 0 "register_operand" "=d") 2133: (mult:SI (match_operand:DI 1 "general_operand" "%0") 2134: (match_operand:SI 2 "general_operand" "g")))] 2135: "" 2136: "* 2137: { 2138: check_label_emit (); 2139: if (REG_P (operands[2])) 2140: { 2141: mvs_check_page (0, 2, 0); 2142: return \"MR %0,%2\"; 2143: } 2144: mvs_check_page (0, 4, 0); 2145: return \"M %0,%2\"; 2146: }") 2147: 2148: ; 2149: ; muldf3 instruction pattern(s). 2150: ; 2151: 2152: (define_insn "muldf3" 2153: [(set (match_operand:DF 0 "general_operand" "=f") 2154: (mult:DF (match_operand:DF 1 "general_operand" "%0") 2155: (match_operand:DF 2 "general_operand" "fmF")))] 2156: "" 2157: "* 2158: { 2159: check_label_emit (); 2160: if (FP_REG_P (operands[2])) 2161: { 2162: mvs_check_page (0, 2, 0); 2163: return \"MDR %0,%2\"; 2164: } 2165: mvs_check_page (0, 4, 0); 2166: return \"MD %0,%2\"; 2167: }") 2168: 2169: ; 2170: ; mulsf3 instruction pattern(s). 2171: ; 2172: 2173: (define_insn "mulsf3" 2174: [(set (match_operand:SF 0 "general_operand" "=f") 2175: (mult:SF (match_operand:SF 1 "general_operand" "%0") 2176: (match_operand:SF 2 "general_operand" "fmF")))] 2177: "" 2178: "* 2179: { 2180: check_label_emit (); 2181: if (FP_REG_P (operands[2])) 2182: { 2183: mvs_check_page (0, 2, 0); 2184: return \"MER %0,%2\"; 2185: } 2186: mvs_check_page (0, 4, 0); 2187: return \"ME %0,%2\"; 2188: }") 2189: 2190: ;; 2191: ;;- Divide instructions. 2192: ;; 2193: 2194: ; 2195: ; divsi3 instruction pattern(s). 2196: ; 2197: 2198: (define_expand "divsi3" 2199: [(set (match_operand:SI 0 "general_operand" "") 2200: (div:SI (match_operand:SI 1 "general_operand" "") 2201: (match_operand:SI 2 "general_operand" "")))] 2202: "" 2203: " 2204: { 2205: rtx r = gen_reg_rtx (DImode); 2206: 2207: emit_insn (gen_extendsidi2 (r, operands[1])); 2208: emit_insn (gen_rtx (SET, VOIDmode, r, 2209: gen_rtx (DIV, SImode, r, operands[2]))); 2210: emit_insn (gen_rtx (SET, VOIDmode, operands[0], 2211: gen_rtx (SUBREG, SImode, r, 1))); 2212: DONE; 2213: }") 2214: 2215: 2216: ; 2217: ; udivsi3 instruction pattern(s). 2218: ; 2219: 2220: (define_expand "udivsi3" 2221: [(set (match_operand:SI 0 "general_operand" "") 2222: (udiv:SI (match_operand:SI 1 "general_operand" "") 2223: (match_operand:SI 2 "general_operand" "")))] 2224: "" 2225: " 2226: { 2227: rtx dr = gen_reg_rtx (DImode); 2228: rtx dr_0 = gen_rtx (SUBREG, SImode, dr, 0); 2229: rtx dr_1 = gen_rtx (SUBREG, SImode, dr, 1); 2230: 2231: 2232: if (GET_CODE (operands[2]) == CONST_INT) 2233: { 2234: if (INTVAL (operands[2]) > 0) 2235: { 2236: emit_insn (gen_zero_extendsidi2 (dr, operands[1])); 2237: emit_insn (gen_rtx (SET, VOIDmode, dr, 2238: gen_rtx (DIV, SImode, dr, operands[2]))); 2239: } 2240: else 2241: { 2242: rtx label1 = gen_label_rtx (); 2243: 2244: emit_insn (gen_rtx (SET, VOIDmode, dr_0, operands[1])); 2245: emit_insn (gen_rtx (SET, VOIDmode, dr_1, const0_rtx)); 2246: emit_insn (gen_cmpsi (dr_0, operands[2])); 2247: emit_jump_insn (gen_bltu (label1)); 2248: emit_insn (gen_rtx (SET, VOIDmode, dr_1, const1_rtx)); 2249: emit_label (label1); 2250: } 2251: } 2252: else 2253: { 2254: rtx label1 = gen_label_rtx (); 2255: rtx label2 = gen_label_rtx (); 2256: rtx label3 = gen_label_rtx (); 2257: rtx sr = gen_reg_rtx (SImode); 2258: 2259: emit_insn (gen_rtx (SET, VOIDmode, dr_0, operands[1])); 2260: emit_insn (gen_rtx (SET, VOIDmode, sr, operands[2])); 2261: emit_insn (gen_rtx (SET, VOIDmode, dr_1, const0_rtx)); 2262: emit_insn (gen_cmpsi (sr, dr_0)); 2263: emit_jump_insn (gen_bgtu (label3)); 2264: emit_insn (gen_cmpsi (sr, const1_rtx)); 2265: emit_jump_insn (gen_blt (label2)); 2266: emit_jump_insn (gen_beq (label1)); 2267: emit_insn (gen_rtx (SET, VOIDmode, dr, 2268: gen_rtx (LSHIFTRT, DImode, dr, 2269: gen_rtx (CONST_INT, SImode, 32)))); 2270: emit_insn (gen_rtx (SET, VOIDmode, dr, 2271: gen_rtx (DIV, SImode, dr, sr))); 2272: emit_jump_insn (gen_jump (label3)); 2273: emit_label (label1); 2274: emit_insn (gen_rtx (SET, VOIDmode, dr_1, dr_0)); 2275: emit_jump_insn (gen_jump (label3)); 2276: emit_label (label2); 2277: emit_insn (gen_rtx (SET, VOIDmode, dr_1, const1_rtx)); 2278: emit_label (label3); 2279: } 2280: emit_insn (gen_rtx (SET, VOIDmode, operands[0], dr_1)); 2281: 2282: DONE; 2283: }") 2284: 2285: ; This is used by divsi3 & udivsi3. 2286: 2287: (define_insn "" 2288: [(set (match_operand:DI 0 "register_operand" "=d") 2289: (div:SI (match_operand:DI 1 "register_operand" "0") 2290: (match_operand:SI 2 "general_operand" "")))] 2291: "" 2292: "* 2293: { 2294: check_label_emit (); 2295: if (REG_P (operands[2])) 2296: { 2297: mvs_check_page (0, 2, 0); 2298: return \"DR %0,%2\"; 2299: } 2300: mvs_check_page (0, 4, 0); 2301: return \"D %0,%2\"; 2302: }") 2303: 2304: ; 2305: ; divdf3 instruction pattern(s). 2306: ; 2307: 2308: (define_insn "divdf3" 2309: [(set (match_operand:DF 0 "general_operand" "=f") 2310: (div:DF (match_operand:DF 1 "general_operand" "0") 2311: (match_operand:DF 2 "general_operand" "fmF")))] 2312: "" 2313: "* 2314: { 2315: check_label_emit (); 2316: if (FP_REG_P (operands[2])) 2317: { 2318: mvs_check_page (0, 2, 0); 2319: return \"DDR %0,%2\"; 2320: } 2321: mvs_check_page (0, 4, 0); 2322: return \"DD %0,%2\"; 2323: }") 2324: 2325: ; 2326: ; divsf3 instruction pattern(s). 2327: ; 2328: 2329: (define_insn "divsf3" 2330: [(set (match_operand:SF 0 "general_operand" "=f") 2331: (div:SF (match_operand:SF 1 "general_operand" "0") 2332: (match_operand:SF 2 "general_operand" "fmF")))] 2333: "" 2334: "* 2335: { 2336: check_label_emit (); 2337: if (FP_REG_P (operands[2])) 2338: { 2339: mvs_check_page (0, 2, 0); 2340: return \"DER %0,%2\"; 2341: } 2342: mvs_check_page (0, 4, 0); 2343: return \"DE %0,%2\"; 2344: }") 2345: 2346: ;; 2347: ;;- Modulo instructions. 2348: ;; 2349: 2350: ; 2351: ; modsi3 instruction pattern(s). 2352: ; 2353: 2354: (define_expand "modsi3" 2355: [(set (match_operand:SI 0 "general_operand" "") 2356: (mod:SI (match_operand:SI 1 "general_operand" "") 2357: (match_operand:SI 2 "general_operand" "")))] 2358: "" 2359: " 2360: { 2361: rtx r = gen_reg_rtx (DImode); 2362: 2363: emit_insn (gen_extendsidi2 (r, operands[1])); 2364: emit_insn (gen_rtx (SET, VOIDmode, r, 2365: gen_rtx (MOD, SImode, r, operands[2]))); 2366: emit_insn (gen_rtx (SET, VOIDmode, operands[0], 2367: gen_rtx (SUBREG, SImode, r, 0))); 2368: DONE; 2369: }") 2370: 2371: ; 2372: ; umodsi3 instruction pattern(s). 2373: ; 2374: 2375: (define_expand "umodsi3" 2376: [(set (match_operand:SI 0 "general_operand" "") 2377: (umod:SI (match_operand:SI 1 "general_operand" "") 2378: (match_operand:SI 2 "general_operand" "")))] 2379: "" 2380: " 2381: { 2382: rtx dr = gen_reg_rtx (DImode); 2383: rtx dr_0 = gen_rtx (SUBREG, SImode, dr, 0); 2384: rtx dr_1 = gen_rtx (SUBREG, SImode, dr, 1); 2385: 2386: emit_insn (gen_rtx (SET, VOIDmode, dr_0, operands[1])); 2387: 2388: if (GET_CODE (operands[2]) == CONST_INT) 2389: { 2390: if (INTVAL (operands[2]) > 0) 2391: { 2392: emit_insn (gen_rtx (SET, VOIDmode, dr, 2393: gen_rtx (LSHIFTRT, DImode, dr, 2394: gen_rtx (CONST_INT, SImode, 32)))); 2395: emit_insn (gen_rtx (SET, VOIDmode, dr, 2396: gen_rtx (MOD, SImode, dr, operands[2]))); 2397: } 2398: else 2399: { 2400: rtx label1 = gen_label_rtx (); 2401: rtx sr = gen_reg_rtx (SImode); 2402: 2403: emit_insn (gen_rtx (SET, VOIDmode, sr, operands[2])); 2404: emit_insn (gen_cmpsi (dr_0, sr)); 2405: emit_jump_insn (gen_bltu (label1)); 2406: emit_insn (gen_rtx (SET, VOIDmode, sr, gen_rtx (ABS, SImode, sr))); 2407: emit_insn (gen_rtx (SET, VOIDmode, dr_0, 2408: gen_rtx (PLUS, SImode, dr_0, sr))); 2409: emit_label (label1); 2410: } 2411: } 2412: else 2413: { 2414: rtx label1 = gen_label_rtx (); 2415: rtx label2 = gen_label_rtx (); 2416: rtx label3 = gen_label_rtx (); 2417: rtx sr = gen_reg_rtx (SImode); 2418: 2419: emit_insn (gen_rtx (SET, VOIDmode, dr_0, operands[1])); 2420: emit_insn (gen_rtx (SET, VOIDmode, sr, operands[2])); 2421: emit_insn (gen_cmpsi (sr, dr_0)); 2422: emit_jump_insn (gen_bgtu (label3)); 2423: emit_insn (gen_cmpsi (sr, const1_rtx)); 2424: emit_jump_insn (gen_blt (label2)); 2425: emit_jump_insn (gen_beq (label1)); 2426: emit_insn (gen_rtx (SET, VOIDmode, dr, 2427: gen_rtx (LSHIFTRT, DImode, dr, 2428: gen_rtx (CONST_INT, SImode, 32)))); 2429: emit_insn (gen_rtx (SET, VOIDmode, dr, gen_rtx (MOD, SImode, dr, sr))); 2430: emit_jump_insn (gen_jump (label3)); 2431: emit_label (label1); 2432: emit_insn (gen_rtx (SET, VOIDmode, dr_0, const0_rtx)); 2433: emit_jump_insn (gen_jump (label3)); 2434: emit_label (label2); 2435: emit_insn (gen_rtx (SET, VOIDmode, dr_0, 2436: gen_rtx (MINUS, SImode, dr_0, sr))); 2437: emit_label (label3); 2438: 2439: } 2440: emit_insn (gen_rtx (SET, VOIDmode, operands[0], dr_0)); 2441: 2442: DONE; 2443: }") 2444: 2445: ; This is used by modsi3 & umodsi3. 2446: 2447: (define_insn "" 2448: [(set (match_operand:DI 0 "register_operand" "=d") 2449: (mod:SI (match_operand:DI 1 "register_operand" "0") 2450: (match_operand:SI 2 "general_operand" "")))] 2451: "" 2452: "* 2453: { 2454: check_label_emit (); 2455: if (REG_P (operands[2])) 2456: { 2457: mvs_check_page (0, 2, 0); 2458: return \"DR %0,%2\"; 2459: } 2460: mvs_check_page (0, 4, 0); 2461: return \"D %0,%2\"; 2462: }") 2463: 2464: ;; 2465: ;;- And instructions. 2466: ;; 2467: 2468: ; 2469: ; anddi3 instruction pattern(s). 2470: ; 2471: 2472: ;(define_expand "anddi3" 2473: ; [(set (match_operand:DI 0 "general_operand" "") 2474: ; (and:DI (match_operand:DI 1 "general_operand" "") 2475: ; (match_operand:DI 2 "general_operand" "")))] 2476: ; "" 2477: ; " 2478: ;{ 2479: ; rtx gen_andsi3(); 2480: ; 2481: ; emit_insn (gen_andsi3 (operand_subword (operands[0], 0, 1, DImode), 2482: ; operand_subword (operands[1], 0, 1, DImode), 2483: ; operand_subword (operands[2], 0, 1, DImode))); 2484: ; emit_insn (gen_andsi3 (gen_lowpart (SImode, operands[0]), 2485: ; gen_lowpart (SImode, operands[1]), 2486: ; gen_lowpart (SImode, operands[2]))); 2487: ; DONE; 2488: ;}") 2489: 2490: ; 2491: ; andsi3 instruction pattern(s). 2492: ; 2493: 2494: (define_insn "" 2495: [(set (match_operand:SI 0 "r_or_s_operand" "=d,m") 2496: (and:SI (match_operand:SI 1 "r_or_s_operand" "%0,0") 2497: (match_operand:SI 2 "r_or_s_operand" "g,mi")))] 2498: "TARGET_CHAR_INSTRUCTIONS" 2499: "* 2500: { 2501: check_label_emit (); 2502: if (REG_P (operands[2])) 2503: { 2504: mvs_check_page (0, 2, 0); 2505: return \"NR %0,%2\"; 2506: } 2507: if (REG_P (operands[0])) 2508: { 2509: mvs_check_page (0, 4, 0); 2510: return \"N %0,%2\"; 2511: } 2512: CC_STATUS_INIT; 2513: mvs_check_page (0, 6, 0); 2514: return \"NC %O0(4,%R0),%2\"; 2515: }") 2516: 2517: (define_insn "andsi3" 2518: [(set (match_operand:SI 0 "general_operand" "=d") 2519: (and:SI (match_operand:SI 1 "general_operand" "%0") 2520: (match_operand:SI 2 "general_operand" "g")))] 2521: "" 2522: "* 2523: { 2524: check_label_emit (); 2525: if (REG_P (operands[2])) 2526: { 2527: mvs_check_page (0, 2, 0); 2528: return \"NR %0,%2\"; 2529: } 2530: mvs_check_page (0, 4, 0); 2531: return \"N %0,%2\"; 2532: }") 2533: 2534: ; 2535: ; andhi3 instruction pattern(s). 2536: ; 2537: 2538: (define_insn "" 2539: [(set (match_operand:HI 0 "r_or_s_operand" "=d,m") 2540: (and:HI (match_operand:HI 1 "r_or_s_operand" "%0,0") 2541: (match_operand:HI 2 "r_or_s_operand" "di,mi")))] 2542: "TARGET_CHAR_INSTRUCTIONS" 2543: "* 2544: { 2545: check_label_emit (); 2546: if (REG_P (operands[2])) 2547: { 2548: mvs_check_page (0, 2, 0); 2549: return \"NR %0,%2\"; 2550: } 2551: if (REG_P (operands[0])) 2552: { 2553: mvs_check_page (0, 4, 0); 1.1.1.3 ! root 2554: return \"N %0,%2\"; 1.1 root 2555: } 2556: CC_STATUS_INIT; 2557: if (GET_CODE (operands[2]) == CONST_INT) 2558: { 1.1.1.3 ! root 2559: mvs_check_page (0, 6, 0); ! 2560: return \"NC %O0(2,%R0),%H2\"; 1.1 root 2561: } 2562: mvs_check_page (0, 6, 0); 2563: return \"NC %O0(2,%R0),%2\"; 2564: }") 2565: 2566: (define_insn "andhi3" 2567: [(set (match_operand:HI 0 "general_operand" "=d") 2568: (and:HI (match_operand:HI 1 "general_operand" "%0") 2569: (match_operand:HI 2 "general_operand" "di")))] 2570: "" 2571: "* 2572: { 2573: check_label_emit (); 2574: if (GET_CODE (operands[2]) == CONST_INT) 2575: { 2576: mvs_check_page (0, 4, 0); 1.1.1.3 ! root 2577: return \"N %0,%2\"; 1.1 root 2578: } 2579: mvs_check_page (0, 2, 0); 2580: return \"NR %0,%2\"; 2581: }") 2582: 2583: ; 2584: ; andqi3 instruction pattern(s). 2585: ; 2586: 2587: (define_insn "" 2588: [(set (match_operand:QI 0 "r_or_s_operand" "=d,m") 2589: (and:QI (match_operand:QI 1 "r_or_s_operand" "%0,0") 2590: (match_operand:QI 2 "r_or_s_operand" "di,mi")))] 2591: "TARGET_CHAR_INSTRUCTIONS" 2592: "* 2593: { 2594: check_label_emit (); 2595: CC_STATUS_INIT; 2596: if (REG_P (operands[2])) 2597: { 2598: mvs_check_page (0, 2, 0); 2599: return \"NR %0,%2\"; 2600: } 2601: if (REG_P (operands[0])) 2602: { 2603: mvs_check_page (0, 4, 0); 2604: return \"N %0,%2\"; 2605: } 2606: if (GET_CODE (operands[2]) == CONST_INT) 2607: { 2608: mvs_check_page (0, 4, 0); 2609: return \"NI %0,%B2\"; 2610: } 2611: mvs_check_page (0, 6, 0); 2612: return \"NC %O0(1,%R0),%2\"; 2613: }") 2614: 2615: (define_insn "andqi3" 2616: [(set (match_operand:QI 0 "general_operand" "=d") 2617: (and:QI (match_operand:QI 1 "general_operand" "%0") 2618: (match_operand:QI 2 "general_operand" "di")))] 2619: "" 2620: "* 2621: { 2622: check_label_emit (); 2623: CC_STATUS_INIT; 2624: if (GET_CODE (operands[2]) == CONST_INT) 2625: { 2626: mvs_check_page (0, 4, 0); 2627: return \"N %0,%2\"; 2628: } 2629: mvs_check_page (0, 2, 0); 2630: return \"NR %0,%2\"; 2631: }") 2632: 2633: ;; 2634: ;;- Bit set (inclusive or) instructions. 2635: ;; 2636: 2637: ; 2638: ; iordi3 instruction pattern(s). 2639: ; 2640: 2641: ;(define_expand "iordi3" 2642: ; [(set (match_operand:DI 0 "general_operand" "") 2643: ; (ior:DI (match_operand:DI 1 "general_operand" "") 2644: ; (match_operand:DI 2 "general_operand" "")))] 2645: ; "" 2646: ; " 2647: ;{ 2648: ; rtx gen_iorsi3(); 2649: ; 2650: ; emit_insn (gen_iorsi3 (operand_subword (operands[0], 0, 1, DImode), 2651: ; operand_subword (operands[1], 0, 1, DImode), 2652: ; operand_subword (operands[2], 0, 1, DImode))); 2653: ; emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]), 2654: ; gen_lowpart (SImode, operands[1]), 2655: ; gen_lowpart (SImode, operands[2]))); 2656: ; DONE; 2657: ;}") 2658: 2659: ; 2660: ; iorsi3 instruction pattern(s). 2661: ; 2662: 2663: (define_insn "" 2664: [(set (match_operand:SI 0 "r_or_s_operand" "=d,m") 2665: (ior:SI (match_operand:SI 1 "r_or_s_operand" "%0,0") 2666: (match_operand:SI 2 "r_or_s_operand" "g,mi")))] 2667: "TARGET_CHAR_INSTRUCTIONS" 2668: "* 2669: { 2670: check_label_emit (); 2671: if (REG_P (operands[2])) 2672: { 2673: mvs_check_page (0, 2, 0); 2674: return \"OR %0,%2\"; 2675: } 2676: if (REG_P (operands[0])) 2677: { 2678: mvs_check_page (0, 4, 0); 2679: return \"O %0,%2\"; 2680: } 2681: CC_STATUS_INIT; 2682: mvs_check_page (0, 6, 0); 2683: return \"OC %O0(4,%R0),%2\"; 2684: }") 2685: 2686: (define_insn "iorsi3" 2687: [(set (match_operand:SI 0 "general_operand" "=d") 2688: (ior:SI (match_operand:SI 1 "general_operand" "%0") 2689: (match_operand:SI 2 "general_operand" "g")))] 2690: "" 2691: "* 2692: { 2693: check_label_emit (); 2694: if (REG_P (operands[2])) 2695: { 2696: mvs_check_page (0, 2, 0); 2697: return \"OR %0,%2\"; 2698: } 2699: mvs_check_page (0, 4, 0); 2700: return \"O %0,%2\"; 2701: }") 2702: 2703: ; 2704: ; iorhi3 instruction pattern(s). 2705: ; 2706: 2707: (define_insn "" 2708: [(set (match_operand:HI 0 "r_or_s_operand" "=d,m") 2709: (ior:HI (match_operand:HI 1 "r_or_s_operand" "%0,0") 2710: (match_operand:HI 2 "r_or_s_operand" "di,mi")))] 2711: "TARGET_CHAR_INSTRUCTIONS" 2712: "* 2713: { 2714: check_label_emit (); 2715: if (REG_P (operands[2])) 2716: { 2717: mvs_check_page (0, 2, 0); 2718: return \"OR %0,%2\"; 2719: } 2720: if (REG_P (operands[0])) 2721: { 2722: mvs_check_page (0, 4, 0); 1.1.1.3 ! root 2723: return \"O %0,%2\"; 1.1 root 2724: } 2725: CC_STATUS_INIT; 2726: if (GET_CODE (operands[2]) == CONST_INT) 2727: { 1.1.1.3 ! root 2728: mvs_check_page (0, 6, 0); ! 2729: return \"OC %O0(2,%R0),%H2\"; 1.1 root 2730: } 2731: mvs_check_page (0, 6, 0); 2732: return \"OC %O0(2,%R0),%2\"; 2733: }") 2734: 2735: (define_insn "iorhi3" 2736: [(set (match_operand:HI 0 "general_operand" "=d") 2737: (ior:HI (match_operand:HI 1 "general_operand" "%0") 2738: (match_operand:HI 2 "general_operand" "di")))] 2739: "" 2740: "* 2741: { 2742: check_label_emit (); 2743: if (GET_CODE (operands[2]) == CONST_INT) 2744: { 2745: mvs_check_page (0, 4, 0); 1.1.1.3 ! root 2746: return \"O %0,%2\"; 1.1 root 2747: } 2748: mvs_check_page (0, 2, 0); 2749: return \"OR %0,%2\"; 2750: }") 2751: 2752: ; 2753: ; iorqi3 instruction pattern(s). 2754: ; 2755: 2756: (define_insn "" 2757: [(set (match_operand:QI 0 "r_or_s_operand" "=d,m") 2758: (ior:QI (match_operand:QI 1 "r_or_s_operand" "%0,0") 2759: (match_operand:QI 2 "r_or_s_operand" "di,mi")))] 2760: "TARGET_CHAR_INSTRUCTIONS" 2761: "* 2762: { 2763: check_label_emit (); 2764: CC_STATUS_INIT; 2765: if (REG_P (operands[2])) 2766: { 2767: mvs_check_page (0, 2, 0); 2768: return \"OR %0,%2\"; 2769: } 2770: if (REG_P (operands[0])) 2771: { 2772: mvs_check_page (0, 4, 0); 2773: return \"O %0,%2\"; 2774: } 2775: CC_STATUS_INIT; 2776: if (GET_CODE (operands[2]) == CONST_INT) 2777: { 2778: mvs_check_page (0, 4, 0); 2779: return \"OI %0,%B2\"; 2780: } 2781: mvs_check_page (0, 6, 0); 2782: return \"OC %O0(1,%R0),%2\"; 2783: }") 2784: 2785: (define_insn "iorqi3" 2786: [(set (match_operand:QI 0 "general_operand" "=d") 2787: (ior:QI (match_operand:QI 1 "general_operand" "%0") 2788: (match_operand:QI 2 "general_operand" "di")))] 2789: "" 2790: "* 2791: { 2792: check_label_emit (); 2793: CC_STATUS_INIT; 2794: if (GET_CODE (operands[2]) == CONST_INT) 2795: { 2796: mvs_check_page (0, 4, 0); 2797: return \"O %0,%2\"; 2798: } 2799: mvs_check_page (0, 2, 0); 2800: return \"OR %0,%2\"; 2801: }") 2802: 2803: ;; 2804: ;;- Xor instructions. 2805: ;; 2806: 2807: ; 2808: ; xordi3 instruction pattern(s). 2809: ; 2810: 2811: ;(define_expand "xordi3" 2812: ; [(set (match_operand:DI 0 "general_operand" "") 2813: ; (xor:DI (match_operand:DI 1 "general_operand" "") 2814: ; (match_operand:DI 2 "general_operand" "")))] 2815: ; "" 2816: ; " 2817: ;{ 2818: ; rtx gen_xorsi3(); 2819: ; 2820: ; emit_insn (gen_xorsi3 (operand_subword (operands[0], 0, 1, DImode), 2821: ; operand_subword (operands[1], 0, 1, DImode), 2822: ; operand_subword (operands[2], 0, 1, DImode))); 2823: ; emit_insn (gen_xorsi3 (gen_lowpart (SImode, operands[0]), 2824: ; gen_lowpart (SImode, operands[1]), 2825: ; gen_lowpart (SImode, operands[2]))); 2826: ; DONE; 2827: ;}") 2828: 2829: ; 2830: ; xorsi3 instruction pattern(s). 2831: ; 2832: 2833: (define_insn "" 2834: [(set (match_operand:SI 0 "r_or_s_operand" "=d,m") 2835: (xor:SI (match_operand:SI 1 "r_or_s_operand" "%0,0") 2836: (match_operand:SI 2 "r_or_s_operand" "g,mi")))] 2837: "TARGET_CHAR_INSTRUCTIONS" 2838: "* 2839: { 2840: check_label_emit (); 2841: if (REG_P (operands[2])) 2842: { 2843: mvs_check_page (0, 2, 0); 2844: return \"XR %0,%2\"; 2845: } 2846: if (REG_P (operands[0])) 2847: { 2848: mvs_check_page (0, 4, 0); 2849: return \"X %0,%2\"; 2850: } 2851: CC_STATUS_INIT; 2852: mvs_check_page (0, 6, 0); 2853: return \"XC %O0(4,%R0),%2\"; 2854: }") 2855: 2856: (define_insn "xorsi3" 2857: [(set (match_operand:SI 0 "general_operand" "=d") 2858: (xor:SI (match_operand:SI 1 "general_operand" "%0") 2859: (match_operand:SI 2 "general_operand" "g")))] 2860: "" 2861: "* 2862: { 2863: check_label_emit (); 2864: if (REG_P (operands[2])) 2865: { 2866: mvs_check_page (0, 2, 0); 2867: return \"XR %0,%2\"; 2868: } 2869: mvs_check_page (0, 4, 0); 2870: return \"X %0,%2\"; 2871: }") 2872: 2873: ; 2874: ; xorhi3 instruction pattern(s). 2875: ; 2876: 2877: (define_insn "" 2878: [(set (match_operand:HI 0 "r_or_s_operand" "=d,m") 2879: (xor:HI (match_operand:HI 1 "r_or_s_operand" "%0,0") 2880: (match_operand:HI 2 "r_or_s_operand" "di,mi")))] 2881: "TARGET_CHAR_INSTRUCTIONS" 2882: "* 2883: { 2884: check_label_emit (); 2885: if (REG_P (operands[2])) 2886: { 2887: mvs_check_page (0, 2, 0); 2888: return \"XR %0,%2\"; 2889: } 2890: if (REG_P (operands[0])) 2891: { 2892: mvs_check_page (0, 4, 0); 1.1.1.3 ! root 2893: return \"X %0,%2\"; 1.1 root 2894: } 2895: CC_STATUS_INIT; 2896: if (GET_CODE (operands[2]) == CONST_INT) 2897: { 1.1.1.3 ! root 2898: mvs_check_page (0, 6, 0); ! 2899: return \"XC %O0(2,%R0),%H2\"; 1.1 root 2900: } 2901: mvs_check_page (0, 6, 0); 2902: return \"XC %O0(2,%R0),%2\"; 2903: }") 2904: 2905: (define_insn "xorhi3" 2906: [(set (match_operand:HI 0 "general_operand" "=d") 2907: (xor:HI (match_operand:HI 1 "general_operand" "%0") 2908: (match_operand:HI 2 "general_operand" "di")))] 2909: "" 2910: "* 2911: { 2912: check_label_emit (); 2913: if (GET_CODE (operands[2]) == CONST_INT) 2914: { 2915: mvs_check_page (0, 4, 0); 2916: return \"X %0,%2\"; 2917: } 2918: mvs_check_page (0, 2, 0); 2919: return \"XR %0,%2\"; 2920: }") 2921: 2922: ; 2923: ; xorqi3 instruction pattern(s). 2924: ; 2925: 2926: (define_insn "" 2927: [(set (match_operand:QI 0 "r_or_s_operand" "=d,m") 2928: (xor:QI (match_operand:QI 1 "r_or_s_operand" "%0,0") 2929: (match_operand:QI 2 "r_or_s_operand" "di,mi")))] 2930: "TARGET_CHAR_INSTRUCTIONS" 2931: "* 2932: { 2933: check_label_emit (); 2934: CC_STATUS_INIT; 2935: if (REG_P (operands[2])) 2936: { 2937: mvs_check_page (0, 2, 0); 2938: return \"XR %0,%2\"; 2939: } 2940: if (REG_P (operands[0])) 2941: { 2942: mvs_check_page (0, 4, 0); 2943: return \"X %0,%2\"; 2944: } 2945: if (GET_CODE (operands[2]) == CONST_INT) 2946: { 2947: mvs_check_page (0, 4, 0); 2948: return \"XI %0,%B2\"; 2949: } 2950: mvs_check_page (0, 6, 0); 2951: return \"XC %O0(1,%R0),%2\"; 2952: }") 2953: 2954: (define_insn "xorqi3" 2955: [(set (match_operand:QI 0 "general_operand" "=d") 2956: (xor:QI (match_operand:QI 1 "general_operand" "%0") 2957: (match_operand:QI 2 "general_operand" "di")))] 2958: "" 2959: "* 2960: { 2961: check_label_emit (); 2962: CC_STATUS_INIT; 2963: if (GET_CODE (operands[2]) == CONST_INT) 2964: { 2965: mvs_check_page (0, 4, 0); 2966: return \"X %0,%2\"; 2967: } 2968: mvs_check_page (0, 2, 0); 2969: return \"XR %0,%2\"; 2970: }") 2971: 2972: ;; 2973: ;;- Negate instructions. 2974: ;; 2975: 2976: ; 2977: ; negsi2 instruction pattern(s). 2978: ; 2979: 2980: (define_insn "negsi2" 2981: [(set (match_operand:SI 0 "general_operand" "=d") 2982: (neg:SI (match_operand:SI 1 "general_operand" "d")))] 2983: "" 2984: "* 2985: { 2986: check_label_emit (); 2987: mvs_check_page (0, 2, 0); 2988: return \"LCR %0,%1\"; 2989: }") 2990: 2991: ; 2992: ; neghi2 instruction pattern(s). 2993: ; 2994: 2995: (define_insn "neghi2" 2996: [(set (match_operand:HI 0 "general_operand" "=d") 2997: (neg:HI (match_operand:HI 1 "general_operand" "d")))] 2998: "" 2999: "* 3000: { 3001: check_label_emit (); 3002: mvs_check_page (0, 10, 0); 3003: return \"SLL %1,16\;SRA %1,16\;LCR %0,%1\"; 3004: }") 3005: 3006: ; 3007: ; negdf2 instruction pattern(s). 3008: ; 3009: 3010: (define_insn "negdf2" 3011: [(set (match_operand:DF 0 "general_operand" "=f") 3012: (neg:DF (match_operand:DF 1 "general_operand" "f")))] 3013: "" 3014: "* 3015: { 3016: check_label_emit (); 3017: mvs_check_page (0, 2, 0); 3018: return \"LCDR %0,%1\"; 3019: }") 3020: 3021: ; 3022: ; negsf2 instruction pattern(s). 3023: ; 3024: 3025: (define_insn "negsf2" 3026: [(set (match_operand:SF 0 "general_operand" "=f") 3027: (neg:SF (match_operand:SF 1 "general_operand" "f")))] 3028: "" 3029: "* 3030: { 3031: check_label_emit (); 3032: mvs_check_page (0, 2, 0); 3033: return \"LCER %0,%1\"; 3034: }") 3035: 3036: ;; 3037: ;;- Absolute value instructions. 3038: ;; 3039: 3040: ; 3041: ; abssi2 instruction pattern(s). 3042: ; 3043: 3044: (define_insn "abssi2" 3045: [(set (match_operand:SI 0 "general_operand" "=d") 3046: (abs:SI (match_operand:SI 1 "general_operand" "d")))] 3047: "" 3048: "* 3049: { 3050: check_label_emit (); 3051: mvs_check_page (0, 2, 0); 3052: return \"LPR %0,%1\"; 3053: }") 3054: 3055: ; 3056: ; abshi2 instruction pattern(s). 3057: ; 3058: 3059: (define_insn "abshi2" 3060: [(set (match_operand:HI 0 "general_operand" "=d") 3061: (abs:HI (match_operand:HI 1 "general_operand" "d")))] 3062: "" 3063: "* 3064: { 3065: check_label_emit (); 3066: mvs_check_page (0, 10, 0); 3067: return \"SLL %1,16\;SRA %1,16\;LPR %0,%1\"; 3068: }") 3069: 3070: ; 3071: ; absdf2 instruction pattern(s). 3072: ; 3073: 3074: (define_insn "absdf2" 3075: [(set (match_operand:DF 0 "general_operand" "=f") 3076: (abs:DF (match_operand:DF 1 "general_operand" "f")))] 3077: "" 3078: "* 3079: { 3080: check_label_emit (); 3081: mvs_check_page (0, 2, 0); 3082: return \"LPDR %0,%1\"; 3083: }") 3084: 3085: ; 3086: ; abssf2 instruction pattern(s). 3087: ; 3088: 3089: (define_insn "abssf2" 3090: [(set (match_operand:SF 0 "general_operand" "=f") 3091: (abs:SF (match_operand:SF 1 "general_operand" "f")))] 3092: "" 3093: "* 3094: { 3095: check_label_emit (); 3096: mvs_check_page (0, 2, 0); 3097: return \"LPER %0,%1\"; 3098: }") 3099: 3100: ;; 3101: ;;- One complement instructions. 3102: ;; 3103: 3104: ; 3105: ; one_cmpldi2 instruction pattern(s). 3106: ; 3107: 3108: ;(define_expand "one_cmpldi2" 3109: ; [(set (match_operand:DI 0 "general_operand" "") 3110: ; (not:DI (match_operand:DI 1 "general_operand" "")))] 3111: ; "" 3112: ; " 3113: ;{ 3114: ; rtx gen_one_cmplsi2(); 3115: ; 3116: ; emit_insn (gen_one_cmplsi2 (operand_subword (operands[0], 0, 1, DImode), 3117: ; operand_subword (operands[1], 0, 1, DImode))); 3118: ; emit_insn (gen_one_cmplsi2 (gen_lowpart (SImode, operands[0]), 3119: ; gen_lowpart (SImode, operands[1]))); 3120: ; DONE; 3121: ;}") 3122: 3123: ; 3124: ; one_cmplsi2 instruction pattern(s). 3125: ; 3126: 3127: (define_insn "" 3128: [(set (match_operand:SI 0 "r_or_s_operand" "=dm") 3129: (not:SI (match_operand:SI 1 "r_or_s_operand" "0")))] 3130: "TARGET_CHAR_INSTRUCTIONS" 3131: "* 3132: { 3133: check_label_emit (); 3134: if (REG_P (operands[0])) 3135: { 3136: mvs_check_page (0, 4, 4); 3137: return \"X %0,=F'-1'\"; 3138: } 3139: CC_STATUS_INIT; 3140: mvs_check_page (0, 6, 4); 3141: return \"XC %O0(4,%R0),=F'-1'\"; 3142: }") 3143: 3144: (define_insn "one_cmplsi2" 3145: [(set (match_operand:SI 0 "general_operand" "=d") 3146: (not:SI (match_operand:SI 1 "general_operand" "0")))] 3147: "" 3148: "* 3149: { 3150: check_label_emit (); 3151: mvs_check_page (0, 4, 4); 3152: return \"X %0,=F'-1'\"; 3153: }") 3154: 3155: ; 3156: ; one_cmplhi2 instruction pattern(s). 3157: ; 3158: 3159: (define_insn "" 3160: [(set (match_operand:HI 0 "r_or_s_operand" "=dm") 3161: (not:HI (match_operand:HI 1 "r_or_s_operand" "0")))] 3162: "TARGET_CHAR_INSTRUCTIONS" 3163: "* 3164: { 3165: check_label_emit (); 3166: if (REG_P (operands[0])) 3167: { 3168: mvs_check_page (0, 4, 4); 3169: return \"X %0,=F'-1'\"; 3170: } 3171: CC_STATUS_INIT; 3172: mvs_check_page (0, 6, 4); 3173: return \"XC %O0(2,%R0),=X'FFFF'\"; 3174: }") 3175: 3176: (define_insn "one_cmplhi2" 3177: [(set (match_operand:HI 0 "general_operand" "=d") 3178: (not:HI (match_operand:HI 1 "general_operand" "0")))] 3179: "" 3180: "* 3181: { 3182: check_label_emit (); 3183: mvs_check_page (0, 4, 4); 3184: return \"X %0,=F'-1'\"; 3185: }") 3186: 3187: ; 3188: ; one_cmplqi2 instruction pattern(s). 3189: ; 3190: 3191: (define_insn "" 3192: [(set (match_operand:QI 0 "r_or_s_operand" "=dm") 3193: (not:QI (match_operand:QI 1 "r_or_s_operand" "0")))] 3194: "TARGET_CHAR_INSTRUCTIONS" 3195: "* 3196: { 3197: check_label_emit (); 3198: CC_STATUS_INIT; 3199: if (REG_P (operands[0])) 3200: { 3201: mvs_check_page (0, 4, 4); 3202: return \"X %0,=F'-1'\"; 3203: } 3204: mvs_check_page (0, 4, 0); 3205: return \"XI %0,255\"; 3206: }") 3207: 3208: (define_insn "one_cmplqi2" 3209: [(set (match_operand:QI 0 "general_operand" "=d") 3210: (not:QI (match_operand:QI 1 "general_operand" "0")))] 3211: "" 3212: "* 3213: { 3214: check_label_emit (); 3215: CC_STATUS_INIT; 3216: mvs_check_page (0, 4, 4); 3217: return \"X %0,=F'-1'\"; 3218: }") 3219: 3220: ;; 3221: ;;- Arithmetic shift instructions. 3222: ;; 3223: 3224: ; 3225: ; ashldi3 instruction pattern(s). 3226: ; 3227: 3228: (define_insn "ashldi3" 3229: [(set (match_operand:DI 0 "general_operand" "=d") 3230: (ashift:DI (match_operand:DI 1 "general_operand" "0") 3231: (match_operand:SI 2 "general_operand" "Ja")))] 3232: "" 3233: "* 3234: { 3235: check_label_emit (); 3236: CC_STATUS_INIT; 3237: mvs_check_page (0, 4, 0); 3238: if (REG_P (operands[2])) 3239: return \"SLDA %0,0(%2)\"; 3240: return \"SLDA %0,%c2\"; 3241: }") 3242: 3243: ; 3244: ; ashrdi3 instruction pattern(s). 3245: ; 3246: 3247: (define_insn "ashrdi3" 3248: [(set (match_operand:DI 0 "register_operand" "=d") 3249: (ashiftrt:DI (match_operand:DI 1 "general_operand" "0") 3250: (match_operand:SI 2 "general_operand" "Ja")))] 3251: "" 3252: "* 3253: { 3254: check_label_emit (); 3255: mvs_check_page (0, 4, 0); 3256: if (REG_P (operands[2])) 3257: return \"SRDA %0,0(%2)\"; 3258: return \"SRDA %0,%c2\"; 3259: }") 3260: 3261: ; 3262: ; ashlsi3 instruction pattern(s). 3263: ; 3264: 3265: (define_insn "ashlsi3" 3266: [(set (match_operand:SI 0 "general_operand" "=d") 3267: (ashift:SI (match_operand:SI 1 "general_operand" "0") 3268: (match_operand:SI 2 "general_operand" "Ja")))] 3269: "" 3270: "* 3271: { 3272: check_label_emit (); 3273: CC_STATUS_INIT; 3274: mvs_check_page (0, 4, 0); 3275: if (REG_P (operands[2])) 3276: return \"SLL %0,0(%2)\"; 3277: return \"SLL %0,%c2\"; 3278: }") 3279: 3280: ; 3281: ; ashrsi3 instruction pattern(s). 3282: ; 3283: 3284: (define_insn "ashrsi3" 3285: [(set (match_operand:SI 0 "general_operand" "=d") 3286: (ashiftrt:SI (match_operand:SI 1 "general_operand" "0") 3287: (match_operand:SI 2 "general_operand" "Ja")))] 3288: "" 3289: "* 3290: { 3291: check_label_emit (); 3292: mvs_check_page (0, 4, 0); 3293: if (REG_P (operands[2])) 3294: return \"SRA %0,0(%2)\"; 3295: return \"SRA %0,%c2\"; 3296: }") 3297: 3298: ; 3299: ; ashlhi3 instruction pattern(s). 3300: ; 3301: 3302: (define_insn "ashlhi3" 3303: [(set (match_operand:HI 0 "general_operand" "=d") 3304: (ashift:HI (match_operand:HI 1 "general_operand" "0") 3305: (match_operand:SI 2 "general_operand" "Ja")))] 3306: "" 3307: "* 3308: { 3309: check_label_emit (); 3310: mvs_check_page (0, 8, 0); 3311: if (REG_P (operands[2])) 3312: return \"SLL %0,16(%2)\;SRA %0,16\"; 3313: return \"SLL %0,16+%c2\;SRA %0,16\"; 3314: }") 3315: 3316: ; 3317: ; ashrhi3 instruction pattern(s). 3318: ; 3319: 3320: (define_insn "ashrhi3" 3321: [(set (match_operand:HI 0 "general_operand" "=d") 3322: (ashiftrt:HI (match_operand:HI 1 "general_operand" "0") 3323: (match_operand:SI 2 "general_operand" "Ja")))] 3324: "" 3325: "* 3326: { 3327: check_label_emit (); 3328: mvs_check_page (0, 4, 0); 3329: if (REG_P (operands[2])) 3330: return \"SLL %0,16\;SRA %0,16(%2)\"; 3331: return \"SLL %0,16\;SRA %0,16+%c2\"; 3332: }") 3333: 3334: ; 3335: ; ashlqi3 instruction pattern(s). 3336: ; 3337: 3338: (define_insn "ashlqi3" 3339: [(set (match_operand:QI 0 "general_operand" "=d") 3340: (ashift:QI (match_operand:QI 1 "general_operand" "0") 3341: (match_operand:SI 2 "general_operand" "Ja")))] 3342: "" 3343: "* 3344: { 3345: check_label_emit (); 3346: CC_STATUS_INIT; 3347: mvs_check_page (0, 4, 0); 3348: if (REG_P (operands[2])) 3349: return \"SLL %0,0(%2)\"; 3350: return \"SLL %0,%c2\"; 3351: }") 3352: 3353: ; 3354: ; ashrqi3 instruction pattern(s). 3355: ; 3356: 3357: (define_insn "ashrqi3" 3358: [(set (match_operand:QI 0 "general_operand" "=d") 3359: (ashiftrt:QI (match_operand:QI 1 "general_operand" "0") 3360: (match_operand:SI 2 "general_operand" "Ja")))] 3361: "" 3362: "* 3363: { 3364: check_label_emit (); 3365: mvs_check_page (0, 8, 0); 3366: if (REG_P (operands[2])) 3367: return \"SLL %0,24\;SRA %0,24(%2)\"; 3368: return \"SLL %0,24\;SRA %0,24+%c2\"; 3369: }") 3370: 3371: ;; 3372: ;;- Logical shift instructions. 3373: ;; 3374: 3375: ; 3376: ; lshrdi3 instruction pattern(s). 3377: ; 3378: 3379: (define_insn "lshrdi3" 3380: [(set (match_operand:DI 0 "general_operand" "=d") 3381: (lshiftrt:DI (match_operand:DI 1 "general_operand" "0") 3382: (match_operand:SI 2 "general_operand" "Ja")))] 3383: "" 3384: "* 3385: { 3386: check_label_emit (); 3387: mvs_check_page (0, 4, 0); 3388: if (REG_P (operands[2])) 3389: return \"SRDL %0,0(%2)\"; 3390: return \"SRDL %0,%c2\"; 3391: }") 3392: 3393: 3394: ; 3395: ; lshrsi3 instruction pattern(s). 3396: ; 3397: 3398: (define_insn "lshrsi3" 3399: [(set (match_operand:SI 0 "general_operand" "=d") 3400: (lshiftrt:SI (match_operand:SI 1 "general_operand" "0") 3401: (match_operand:SI 2 "general_operand" "Ja")))] 3402: "" 3403: "* 3404: { 3405: check_label_emit (); 3406: mvs_check_page (0, 4, 0); 3407: if (REG_P (operands[2])) 3408: return \"SRL %0,0(%2)\"; 3409: return \"SRL %0,%c2\"; 3410: }") 3411: 3412: ; 3413: ; lshrhi3 instruction pattern(s). 3414: ; 3415: 3416: (define_insn "lshrhi3" 3417: [(set (match_operand:HI 0 "general_operand" "=d") 3418: (lshiftrt:HI (match_operand:HI 1 "general_operand" "0") 3419: (match_operand:SI 2 "general_operand" "Ja")))] 3420: "" 3421: "* 3422: { 3423: check_label_emit (); 3424: CC_STATUS_INIT; 3425: if (REG_P (operands[2])) 3426: { 3427: mvs_check_page (0, 8, 4); 3428: return \"N %0,=X'0000FFFF'\;SRL %0,0(%2)\"; 3429: } 3430: mvs_check_page (0, 8, 4); 3431: return \"N %0,=X'0000FFFF'\;SRL %0,%c2\"; 3432: }") 3433: 3434: ; 3435: ; lshrqi3 instruction pattern(s). 3436: ; 3437: 3438: (define_insn "lshrqi3" 3439: [(set (match_operand:QI 0 "general_operand" "=d") 3440: (lshiftrt:QI (match_operand:QI 1 "general_operand" "0") 3441: (match_operand:SI 2 "general_operand" "Ja")))] 3442: "" 3443: "* 3444: { 3445: check_label_emit (); 3446: CC_STATUS_INIT; 3447: mvs_check_page (0, 8, 4); 3448: if (REG_P (operands[2])) 3449: return \"N %0,=X'000000FF'\;SRL %0,0(%2)\"; 3450: return \"N %0,=X'000000FF'\;SRL %0,%c2\"; 3451: }") 3452: 3453: ;; 3454: ;;- Conditional jump instructions. 3455: ;; 3456: 3457: ; 3458: ; beq instruction pattern(s). 3459: ; 3460: 3461: (define_insn "beq" 3462: [(set (pc) 3463: (if_then_else (eq (cc0) 3464: (const_int 0)) 3465: (label_ref (match_operand 0 "" "")) 3466: (pc)))] 3467: "" 3468: "* 3469: { 3470: check_label_emit (); 3471: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) 3472: { 3473: mvs_check_page (0, 6, 4); 3474: return \"L 14,=A(%l0)\;BER 14\"; 3475: } 3476: if (mvs_check_page (0, 4, 0)) 3477: { 3478: mvs_check_page (0, 2, 4); 3479: return \"L 14,=A(%l0)\;BER 14\"; 3480: } 3481: return \"BE %l0\"; 3482: }") 3483: 3484: ; 3485: ; bne instruction pattern(s). 3486: ; 3487: 3488: (define_insn "bne" 3489: [(set (pc) 3490: (if_then_else (ne (cc0) 3491: (const_int 0)) 3492: (label_ref (match_operand 0 "" "")) 3493: (pc)))] 3494: "" 3495: "* 3496: { 3497: check_label_emit (); 3498: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) 3499: { 3500: mvs_check_page (0, 6, 4); 3501: return \"L 14,=A(%l0)\;BNER 14\"; 3502: } 3503: if (mvs_check_page (0, 4, 0)) 3504: { 3505: mvs_check_page (0, 2, 4); 3506: return \"L 14,=A(%l0)\;BNER 14\"; 3507: } 3508: return \"BNE %l0\"; 3509: }") 3510: 3511: ; 3512: ; bgt instruction pattern(s). 3513: ; 3514: 3515: (define_insn "bgt" 3516: [(set (pc) 3517: (if_then_else (gt (cc0) 3518: (const_int 0)) 3519: (label_ref (match_operand 0 "" "")) 3520: (pc)))] 3521: "" 3522: "* 3523: { 3524: check_label_emit (); 3525: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) 3526: { 3527: mvs_check_page (0, 6, 4); 3528: return \"L 14,=A(%l0)\;BHR 14\"; 3529: } 3530: if (mvs_check_page (0, 4, 0)) 3531: { 3532: mvs_check_page (0, 2, 4); 3533: return \"L 14,=A(%l0)\;BHR 14\"; 3534: } 3535: return \"BH %l0\"; 3536: }") 3537: 3538: ; 3539: ; bgtu instruction pattern(s). 3540: ; 3541: 3542: (define_insn "bgtu" 3543: [(set (pc) 3544: (if_then_else (gtu (cc0) 3545: (const_int 0)) 3546: (label_ref (match_operand 0 "" "")) 3547: (pc)))] 3548: "" 3549: "* 3550: { 3551: check_label_emit (); 3552: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) 3553: { 3554: mvs_check_page (0, 6, 4); 3555: return \"L 14,=A(%l0)\;BHR 14\"; 3556: } 3557: if (mvs_check_page (0, 4, 0)) 3558: { 3559: mvs_check_page (0, 2, 4); 3560: return \"L 14,=A(%l0)\;BHR 14\"; 3561: } 3562: return \"BH %l0\"; 3563: }") 3564: 3565: ; 3566: ; blt instruction pattern(s). 3567: ; 3568: 3569: (define_insn "blt" 3570: [(set (pc) 3571: (if_then_else (lt (cc0) 3572: (const_int 0)) 3573: (label_ref (match_operand 0 "" "")) 3574: (pc)))] 3575: "" 3576: "* 3577: { 3578: check_label_emit (); 3579: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) 3580: { 3581: mvs_check_page (0, 6, 4); 3582: return \"L 14,=A(%l0)\;BLR 14\"; 3583: } 3584: if (mvs_check_page (0, 4, 0)) 3585: { 3586: mvs_check_page (0, 2, 4); 3587: return \"L 14,=A(%l0)\;BLR 14\"; 3588: } 3589: return \"BL %l0\"; 3590: }") 3591: 3592: ; 3593: ; bltu instruction pattern(s). 3594: ; 3595: 3596: (define_insn "bltu" 3597: [(set (pc) 3598: (if_then_else (ltu (cc0) 3599: (const_int 0)) 3600: (label_ref (match_operand 0 "" "")) 3601: (pc)))] 3602: "" 3603: "* 3604: { 3605: check_label_emit (); 3606: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) 3607: { 3608: mvs_check_page (0, 6, 4); 3609: return \"L 14,=A(%l0)\;BLR 14\"; 3610: } 3611: if (mvs_check_page (0, 4, 0)) 3612: { 3613: mvs_check_page (0, 2, 4); 3614: return \"L 14,=A(%l0)\;BLR 14\"; 3615: } 3616: return \"BL %l0\"; 3617: }") 3618: 3619: ; 3620: ; bge instruction pattern(s). 3621: ; 3622: 3623: (define_insn "bge" 3624: [(set (pc) 3625: (if_then_else (ge (cc0) 3626: (const_int 0)) 3627: (label_ref (match_operand 0 "" "")) 3628: (pc)))] 3629: "" 3630: "* 3631: { 3632: check_label_emit (); 3633: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) 3634: { 3635: mvs_check_page (0, 6, 4); 3636: return \"L 14,=A(%l0)\;BNLR 14\"; 3637: } 3638: if (mvs_check_page (0, 4, 0)) 3639: { 3640: mvs_check_page (0, 2, 4); 3641: return \"L 14,=A(%l0)\;BNLR 14\"; 3642: } 3643: return \"BNL %l0\"; 3644: }") 3645: 3646: ; 3647: ; bgeu instruction pattern(s). 3648: ; 3649: 3650: (define_insn "bgeu" 3651: [(set (pc) 3652: (if_then_else (geu (cc0) 3653: (const_int 0)) 3654: (label_ref (match_operand 0 "" "")) 3655: (pc)))] 3656: "" 3657: "* 3658: { 3659: check_label_emit (); 3660: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) 3661: { 3662: mvs_check_page (0, 6, 4); 3663: return \"L 14,=A(%l0)\;BNLR 14\"; 3664: } 3665: if (mvs_check_page (0, 4, 0)) 3666: { 3667: mvs_check_page (0, 2, 4); 3668: return \"L 14,=A(%l0)\;BNLR 14\"; 3669: } 3670: return \"BNL %l0\"; 3671: }") 3672: 3673: ; 3674: ; ble instruction pattern(s). 3675: ; 3676: 3677: (define_insn "ble" 3678: [(set (pc) 3679: (if_then_else (le (cc0) 3680: (const_int 0)) 3681: (label_ref (match_operand 0 "" "")) 3682: (pc)))] 3683: "" 3684: "* 3685: { 3686: check_label_emit (); 3687: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) 3688: { 3689: mvs_check_page (0, 6, 4); 3690: return \"L 14,=A(%l0)\;BNHR 14\"; 3691: } 3692: if (mvs_check_page (0, 4, 0)) 3693: { 3694: mvs_check_page (0, 2, 4); 3695: return \"L 14,=A(%l0)\;BNHR 14\"; 3696: } 3697: return \"BNH %l0\"; 3698: }") 3699: 3700: ; 3701: ; bleu instruction pattern(s). 3702: ; 3703: 3704: (define_insn "bleu" 3705: [(set (pc) 3706: (if_then_else (leu (cc0) 3707: (const_int 0)) 3708: (label_ref (match_operand 0 "" "")) 3709: (pc)))] 3710: "" 3711: "* 3712: { 3713: check_label_emit (); 3714: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) 3715: { 3716: mvs_check_page (0, 6, 4); 3717: return \"L 14,=A(%l0)\;BNHR 14\"; 3718: } 3719: if (mvs_check_page (0, 4, 0)) 3720: { 3721: mvs_check_page (0, 2, 4); 3722: return \"L 14,=A(%l0)\;BNHR 14\"; 3723: } 3724: return \"BNH %l0\"; 3725: }") 3726: 3727: ;; 3728: ;;- Negated conditional jump instructions. 3729: ;; 3730: 3731: (define_insn "" 3732: [(set (pc) 3733: (if_then_else (eq (cc0) 3734: (const_int 0)) 3735: (pc) 3736: (label_ref (match_operand 0 "" ""))))] 3737: "" 3738: "* 3739: { 3740: check_label_emit (); 3741: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) 3742: { 3743: mvs_check_page (0, 6, 4); 3744: return \"L 14,=A(%l0)\;BNER 14\"; 3745: } 3746: if (mvs_check_page (0, 4, 0)) 3747: { 3748: mvs_check_page (0, 2, 4); 3749: return \"L 14,=A(%l0)\;BNER 14\"; 3750: } 3751: return \"BNE %l0\"; 3752: }") 3753: 3754: (define_insn "" 3755: [(set (pc) 3756: (if_then_else (ne (cc0) 3757: (const_int 0)) 3758: (pc) 3759: (label_ref (match_operand 0 "" ""))))] 3760: "" 3761: "* 3762: { 3763: check_label_emit (); 3764: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) 3765: { 3766: mvs_check_page (0, 6, 4); 3767: return \"L 14,=A(%l0)\;BER 14\"; 3768: } 3769: if (mvs_check_page (0, 4, 0)) 3770: { 3771: mvs_check_page (0, 2, 4); 3772: return \"L 14,=A(%l0)\;BER 14\"; 3773: } 3774: return \"BE %l0\"; 3775: }") 3776: 3777: (define_insn "" 3778: [(set (pc) 3779: (if_then_else (gt (cc0) 3780: (const_int 0)) 3781: (pc) 3782: (label_ref (match_operand 0 "" ""))))] 3783: "" 3784: "* 3785: { 3786: check_label_emit (); 3787: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) 3788: { 3789: mvs_check_page (0, 6, 4); 3790: return \"L 14,=A(%l0)\;BNHR 14\"; 3791: } 3792: if (mvs_check_page (0, 4, 0)) 3793: { 3794: mvs_check_page (0, 2, 4); 3795: return \"L 14,=A(%l0)\;BNHR 14\"; 3796: } 3797: return \"BNH %l0\"; 3798: }") 3799: 3800: (define_insn "" 3801: [(set (pc) 3802: (if_then_else (gtu (cc0) 3803: (const_int 0)) 3804: (pc) 3805: (label_ref (match_operand 0 "" ""))))] 3806: "" 3807: "* 3808: { 3809: check_label_emit (); 3810: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) 3811: { 3812: mvs_check_page (0, 6, 4); 3813: return \"L 14,=A(%l0)\;BNHR 14\"; 3814: } 3815: if (mvs_check_page (0, 4, 0)) 3816: { 3817: mvs_check_page (0, 2, 4); 3818: return \"L 14,=A(%l0)\;BNHR 14\"; 3819: } 3820: return \"BNH %l0\"; 3821: }") 3822: 3823: (define_insn "" 3824: [(set (pc) 3825: (if_then_else (lt (cc0) 3826: (const_int 0)) 3827: (pc) 3828: (label_ref (match_operand 0 "" ""))))] 3829: "" 3830: "* 3831: { 3832: check_label_emit (); 3833: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) 3834: { 3835: mvs_check_page (0, 6, 4); 3836: return \"L 14,=A(%l0)\;BNLR 14\"; 3837: } 3838: if (mvs_check_page (0, 4, 0)) 3839: { 3840: mvs_check_page (0, 2, 4); 3841: return \"L 14,=A(%l0)\;BNLR 14\"; 3842: } 3843: return \"BNL %l0\"; 3844: }") 3845: 3846: (define_insn "" 3847: [(set (pc) 3848: (if_then_else (ltu (cc0) 3849: (const_int 0)) 3850: (pc) 3851: (label_ref (match_operand 0 "" ""))))] 3852: "" 3853: "* 3854: { 3855: check_label_emit (); 3856: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) 3857: { 3858: mvs_check_page (0, 6, 4); 3859: return \"L 14,=A(%l0)\;BNLR 14\"; 3860: } 3861: if (mvs_check_page (0, 4, 0)) 3862: { 3863: mvs_check_page (0, 2, 4); 3864: return \"L 14,=A(%l0)\;BNLR 14\"; 3865: } 3866: return \"BNL %l0\"; 3867: }") 3868: 3869: (define_insn "" 3870: [(set (pc) 3871: (if_then_else (ge (cc0) 3872: (const_int 0)) 3873: (pc) 3874: (label_ref (match_operand 0 "" ""))))] 3875: "" 3876: "* 3877: { 3878: check_label_emit (); 3879: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) 3880: { 3881: mvs_check_page (0, 6, 4); 3882: return \"L 14,=A(%l0)\;BLR 14\"; 3883: } 3884: if (mvs_check_page (0, 4, 0)) 3885: { 3886: mvs_check_page (0, 2, 4); 3887: return \"L 14,=A(%l0)\;BLR 14\"; 3888: } 3889: return \"BL %l0\"; 3890: }") 3891: 3892: (define_insn "" 3893: [(set (pc) 3894: (if_then_else (geu (cc0) 3895: (const_int 0)) 3896: (pc) 3897: (label_ref (match_operand 0 "" ""))))] 3898: "" 3899: "* 3900: { 3901: check_label_emit (); 3902: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) 3903: { 3904: mvs_check_page (0, 6, 4); 3905: return \"L 14,=A(%l0)\;BLR 14\"; 3906: } 3907: if (mvs_check_page (0, 4, 0)) 3908: { 3909: mvs_check_page (0, 2, 4); 3910: return \"L 14,=A(%l0)\;BLR 14\"; 3911: } 3912: return \"BL %l0\"; 3913: }") 3914: 3915: (define_insn "" 3916: [(set (pc) 3917: (if_then_else (le (cc0) 3918: (const_int 0)) 3919: (pc) 3920: (label_ref (match_operand 0 "" ""))))] 3921: "" 3922: "* 3923: { 3924: check_label_emit (); 3925: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) 3926: { 3927: mvs_check_page (0, 6, 4); 3928: return \"L 14,=A(%l0)\;BHR 14\"; 3929: } 3930: if (mvs_check_page (0, 4, 0)) 3931: { 3932: mvs_check_page (0, 2, 4); 3933: return \"L 14,=A(%l0)\;BHR 14\"; 3934: } 3935: return \"BH %l0\"; 3936: }") 3937: 3938: (define_insn "" 3939: [(set (pc) 3940: (if_then_else (leu (cc0) 3941: (const_int 0)) 3942: (pc) 3943: (label_ref (match_operand 0 "" ""))))] 3944: "" 3945: "* 3946: { 3947: check_label_emit (); 3948: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) 3949: { 3950: mvs_check_page (0, 6, 4); 3951: return \"L 14,=A(%l0)\;BHR 14\"; 3952: } 3953: if (mvs_check_page (0, 4, 0)) 3954: { 3955: mvs_check_page (0, 2, 4); 3956: return \"L 14,=A(%l0)\;BHR 14\"; 3957: } 3958: return \"BH %l0\"; 3959: }") 3960: 3961: ;; 3962: ;;- Subtract one and jump if not zero. 3963: ;; 3964: 3965: (define_insn "" 3966: [(set (pc) 3967: (if_then_else 3968: (ne (plus:SI (match_operand:SI 0 "register_operand" "+d") 3969: (const_int -1)) 3970: (const_int 0)) 3971: (label_ref (match_operand 1 "" "")) 3972: (pc))) 3973: (set (match_dup 0) 3974: (plus:SI (match_dup 0) 3975: (const_int -1)))] 3976: "" 3977: "* 3978: { 3979: check_label_emit (); 3980: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[1]))) 3981: { 3982: mvs_check_page (0, 6, 4); 3983: return \"L 14,=A(%l1)\;BCTR %0,14\"; 3984: } 3985: if (mvs_check_page (0, 4, 0)) 3986: { 3987: mvs_check_page (0, 2, 4); 3988: return \"L 14,=A(%l1)\;BCTR %0,14\"; 3989: } 3990: return \"BCT %0,%l1\"; 3991: }") 3992: 3993: (define_insn "" 3994: [(set (pc) 3995: (if_then_else 3996: (eq (plus:SI (match_operand:SI 0 "register_operand" "+d") 3997: (const_int -1)) 3998: (const_int 0)) 3999: (pc) 4000: (label_ref (match_operand 1 "" "")))) 4001: (set (match_dup 0) 4002: (plus:SI (match_dup 0) 4003: (const_int -1)))] 4004: "" 4005: "* 4006: { 4007: check_label_emit (); 4008: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[1]))) 4009: { 4010: mvs_check_page (0, 6, 4); 4011: return \"L 14,=A(%l1)\;BCTR %0,14\"; 4012: } 4013: if (mvs_check_page (0, 4, 0)) 4014: { 4015: mvs_check_page (0, 2, 4); 4016: return \"L 14,=A(%l1)\;BCTR %0,14\"; 4017: } 4018: return \"BCT %0,%l1\"; 4019: }") 4020: 4021: ;; 4022: ;;- Unconditional jump instructions. 4023: ;; 4024: 4025: ; 4026: ; jump instruction pattern(s). 4027: ; 4028: 4029: (define_insn "jump" 4030: [(set (pc) 4031: (label_ref (match_operand 0 "" "")))] 4032: "" 4033: "* 4034: { 4035: check_label_emit (); 4036: if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0]))) 4037: { 4038: mvs_check_page (0, 6, 4); 4039: return \"L 14,=A(%l0)\;BR 14\"; 4040: } 4041: if (mvs_check_page (0, 4, 0)) 4042: { 4043: mvs_check_page (0, 2, 4); 4044: return \"L 14,=A(%l0)\;BR 14\"; 4045: } 4046: return \"B %l0\"; 4047: }") 4048: 4049: ; 4050: ; indirect-jump instruction pattern(s). 4051: ; 4052: 4053: (define_insn "indirect_jump" 4054: [(set (pc) (match_operand:SI 0 "general_operand" "r"))] 4055: "(GET_CODE (operands[0]) != MEM )" 4056: "* 4057: { 4058: check_label_emit (); 4059: mvs_check_page (0, 2, 0); 4060: return \"BR %0\"; 4061: }") 4062: 4063: ; 4064: ; tablejump instruction pattern(s). 4065: ; 4066: 4067: (define_insn "tablejump" 4068: [(set (pc) 4069: (match_operand:SI 0 "general_operand" "am")) 4070: (use (label_ref (match_operand 1 "" "")))] 4071: "" 4072: "* 4073: { 4074: check_label_emit (); 4075: if (REG_P (operands[0])) 4076: { 4077: mvs_check_page (0, 6, 0); 4078: return \"BR %0\;DS 0F\"; 4079: } 4080: mvs_check_page (0, 10, 0); 4081: return \"L 14,%0\;BR 14\;DS 0F\"; 4082: }") 4083: 4084: ;; 4085: ;;- Jump to subroutine. 4086: ;; 4087: ;; For the C/370 environment the internal functions, ie. sqrt, are called with 4088: ;; a non-standard form. So, we must fix it here. There's no BM like IBM. 4089: ;; 4090: 4091: ; 4092: ; call instruction pattern(s). 4093: ; 4094: 4095: (define_insn "call" 4096: [(call (match_operand:QI 0 "memory_operand" "m") 4097: (match_operand:SI 1 "immediate_operand" "i"))] 4098: "" 4099: "* 4100: { 4101: static char temp[128]; 4102: int i = STACK_POINTER_OFFSET; 4103: 4104: check_label_emit (); 4105: if (mvs_function_check (XSTR (operands[0], 0))) 4106: { 4107: mvs_check_page (0, 22, 4); 4108: sprintf ( temp, \"LA 1,136(,13)\;ST 1,%d(,13)\;LA 1,%d(,13)\;L 15,%%0\;BALR 14,15\;LD 0,136(,13)\", 4109: i - 4, i - 4 ); 4110: } 4111: else 4112: { 4113: mvs_check_page (0, 10, 4); 4114: sprintf ( temp, \"LA 1,%d(,13)\;L 15,%%0\;BALR 14,15\", i ); 4115: } 4116: return temp; 4117: }") 4118: 4119: ; 4120: ; call_value instruction pattern(s). 4121: ; 4122: 4123: (define_insn "call_value" 4124: [(set (match_operand 0 "" "rf") 4125: (call (match_operand:QI 1 "memory_operand" "m") 4126: (match_operand:SI 2 "general_operand" "i")))] 4127: "" 4128: "* 4129: { 4130: static char temp[128]; 4131: int i = STACK_POINTER_OFFSET; 4132: 4133: check_label_emit (); 4134: if (mvs_function_check (XSTR (operands[1], 0))) 4135: { 4136: mvs_check_page (0, 22, 4); 4137: sprintf ( temp, \"LA 1,136(,13)\;ST 1,%d(,13)\;LA 1,%d(,13)\;L 15,%%1\;BALR 14,15\;LD 0,136(,13)\", 4138: i - 4, i - 4 ); 4139: } 4140: else 4141: { 4142: mvs_check_page (0, 10, 4); 4143: sprintf ( temp, \"LA 1,%d(,13)\;L 15,%%1\;BALR 14,15\", i ); 4144: } 4145: return temp; 4146: }") 4147: 4148: (define_insn "" 4149: [(call (mem:QI (match_operand:SI 0 "" "i")) 4150: (match_operand:SI 1 "general_operand" "g"))] 4151: "GET_CODE (operands[0]) == SYMBOL_REF" 4152: "* 4153: { 4154: static char temp[128]; 4155: int i = STACK_POINTER_OFFSET; 4156: 4157: check_label_emit (); 4158: if (mvs_function_check (XSTR (operands[0], 0))) 4159: { 4160: mvs_check_page (0, 22, 4); 4161: sprintf ( temp, \"LA 1,136(,13)\;ST 1,%d(,13)\;LA 1,%d(,13)\;L 15,%%0\;BALR 14,15\;LD 0,136(,13)\", 4162: i - 4, i - 4 ); 4163: } 4164: else 4165: { 4166: mvs_check_page (0, 10, 4); 4167: sprintf ( temp, \"LA 1,%d(,13)\;L 15,%%0\;BALR 14,15\", i ); 4168: } 4169: return temp; 4170: }") 4171: 4172: (define_insn "" 4173: [(set (match_operand 0 "" "rf") 4174: (call (mem:QI (match_operand:SI 1 "" "i")) 4175: (match_operand:SI 2 "general_operand" "g")))] 4176: "GET_CODE (operands[1]) == SYMBOL_REF" 4177: "* 4178: { 4179: static char temp[128]; 4180: int i = STACK_POINTER_OFFSET; 4181: 4182: check_label_emit (); 4183: if (mvs_function_check (XSTR (operands[1], 0))) 4184: { 4185: mvs_check_page (0, 22, 4); 4186: sprintf ( temp, \"LA 1,136(,13)\;ST 1,%d(,13)\;LA 1,%d(,13)\;L 15,%%1\;BALR 14,15\;LD 0,136(,13)\", 4187: i - 4, i - 4 ); 4188: } 4189: else 4190: { 4191: mvs_check_page (0, 10, 4); 4192: sprintf ( temp, \"LA 1,%d(,13)\;L 15,%%1\;BALR 14,15\", i ); 4193: } 4194: return temp; 4195: }") 4196: 4197: 4198: ;; 4199: ;;- Miscellaneous instructions. 4200: ;; 4201: 4202: ; 4203: ; nop instruction pattern(s). 4204: ; 4205: 4206: (define_insn "nop" 4207: [(const_int 0)] 4208: "" 4209: "* 4210: { 4211: check_label_emit (); 4212: mvs_check_page (0, 2, 0); 4213: return \"LR 0,0\"; 4214: }") 4215:
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