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1.1 root 1: /* Definitions of target machine for GNU compiler for Intel 80386.
2: Copyright (C) 1988, 1992 Free Software Foundation, Inc.
3:
4: This file is part of GNU CC.
5:
6: GNU CC is free software; you can redistribute it and/or modify
7: it under the terms of the GNU General Public License as published by
8: the Free Software Foundation; either version 2, or (at your option)
9: any later version.
10:
11: GNU CC is distributed in the hope that it will be useful,
12: but WITHOUT ANY WARRANTY; without even the implied warranty of
13: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14: GNU General Public License for more details.
15:
16: You should have received a copy of the GNU General Public License
17: along with GNU CC; see the file COPYING. If not, write to
18: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
19:
20:
21: /* The purpose of this file is to define the characteristics of the i386,
22: independant of assembler syntax or operating system.
23:
24: Three other files build on this one to describe a specific assembler syntax:
25: bsd386.h, att386.h, and sun386.h.
26:
27: The actual tm.h file for a particular system should include
28: this file, and then the file for the appropriate assembler syntax.
29:
30: Many macros that specify assembler syntax are omitted entirely from
31: this file because they really belong in the files for particular
32: assemblers. These include AS1, AS2, AS3, RP, IP, LPREFIX, L_SIZE,
33: PUT_OP_SIZE, USE_STAR, ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE,
34: PRINT_B_I_S, and many that start with ASM_ or end in ASM_OP. */
35:
36: /* Names to predefine in the preprocessor for this target machine. */
37:
38: #define I386 1
39:
40: /* Run-time compilation parameters selecting different hardware subsets. */
41:
42: extern int target_flags;
43:
44: /* Macros used in the machine description to test the flags. */
45:
46: /* Compile 80387 insns for floating point (not library calls). */
47: #define TARGET_80387 (target_flags & 1)
48: /* Compile code for an i486. */
49: #define TARGET_486 (target_flags & 2)
50: /* Compile using ret insn that pops args.
51: This will not work unless you use prototypes at least
52: for all functions that can take varying numbers of args. */
53: #define TARGET_RTD (target_flags & 8)
54: /* Compile passing first two args in regs 0 and 1.
55: This exists only to test compiler features that will
56: be needed for RISC chips. It is not usable
57: and is not intended to be usable on this cpu. */
58: #define TARGET_REGPARM (target_flags & 020)
59:
60: /* Macro to define tables used to set the flags.
61: This is a list in braces of pairs in braces,
62: each pair being { "NAME", VALUE }
63: where VALUE is the bits to set or minus the bits to clear.
64: An empty string NAME is used to identify the default VALUE. */
65:
66: #define TARGET_SWITCHES \
67: { { "80387", 1}, \
68: { "soft-float", -1}, \
69: { "486", 2}, \
70: { "no486", -2}, \
71: { "386", -2}, \
72: { "rtd", 8}, \
73: { "nortd", -8}, \
74: { "regparm", 020}, \
75: { "noregparm", -020}, \
76: { "", TARGET_DEFAULT}}
77:
78: /* target machine storage layout */
79:
80: /* Define this if most significant byte of a word is the lowest numbered. */
81: /* That is true on the 80386. */
82:
83: #define BITS_BIG_ENDIAN 0
84:
85: /* Define this if most significant byte of a word is the lowest numbered. */
86: /* That is not true on the 80386. */
87: #define BYTES_BIG_ENDIAN 0
88:
89: /* Define this if most significant word of a multiword number is the lowest
90: numbered. */
91: /* Not true for 80386 */
92: #define WORDS_BIG_ENDIAN 0
93:
94: /* number of bits in an addressible storage unit */
95: #define BITS_PER_UNIT 8
96:
97: /* Width in bits of a "word", which is the contents of a machine register.
98: Note that this is not necessarily the width of data type `int';
99: if using 16-bit ints on a 80386, this would still be 32.
100: But on a machine with 16-bit registers, this would be 16. */
101: #define BITS_PER_WORD 32
102:
103: /* Width of a word, in units (bytes). */
104: #define UNITS_PER_WORD 4
105:
106: /* Width in bits of a pointer.
107: See also the macro `Pmode' defined below. */
108: #define POINTER_SIZE 32
109:
110: /* Allocation boundary (in *bits*) for storing arguments in argument list. */
111: #define PARM_BOUNDARY 32
112:
113: /* Boundary (in *bits*) on which stack pointer should be aligned. */
114: #define STACK_BOUNDARY 32
115:
116: /* Allocation boundary (in *bits*) for the code of a function.
117: For i486, we get better performance by aligning to a cache
118: line (i.e. 16 byte) boundary. */
119: #define FUNCTION_BOUNDARY (TARGET_486 ? 128 : 32)
120:
121: /* Alignment of field after `int : 0' in a structure. */
122:
123: #define EMPTY_FIELD_BOUNDARY 32
124:
125: /* Minimum size in bits of the largest boundary to which any
126: and all fundamental data types supported by the hardware
127: might need to be aligned. No data type wants to be aligned
128: rounder than this. The i386 supports 64-bit floating point
129: quantities, but these can be aligned on any 32-bit boundary. */
130: #define BIGGEST_ALIGNMENT 32
131:
132: /* Define this if move instructions will actually fail to work
133: when given unaligned data. */
134: /* #define STRICT_ALIGNMENT */
135:
136: /* If bit field type is int, don't let it cross an int,
137: and give entire struct the alignment of an int. */
138: /* Required on the 386 since it doesn't have bitfield insns. */
139: #define PCC_BITFIELD_TYPE_MATTERS 1
140:
141: /* Align loop starts for optimal branching. */
142: #define ASM_OUTPUT_LOOP_ALIGN(FILE) \
143: ASM_OUTPUT_ALIGN (FILE, 2)
144:
145: /* This is how to align an instruction for optimal branching.
146: On i486 we'll get better performance by aligning on a
147: cache line (i.e. 16 byte) boundary. */
148: #define ASM_OUTPUT_ALIGN_CODE(FILE) \
149: ASM_OUTPUT_ALIGN ((FILE), (TARGET_486 ? 4 : 2))
150:
151: /* Standard register usage. */
152:
153: /* This processor has special stack-like registers. See reg-stack.c
154: for details. */
155:
156: #define STACK_REGS
157:
158: /* Number of actual hardware registers.
159: The hardware registers are assigned numbers for the compiler
160: from 0 to just below FIRST_PSEUDO_REGISTER.
161: All registers that the compiler knows about must be given numbers,
162: even those that are not normally considered general registers.
163:
164: In the 80386 we give the 8 general purpose registers the numbers 0-7.
165: We number the floating point registers 8-15.
166: Note that registers 0-7 can be accessed as a short or int,
167: while only 0-3 may be used with byte `mov' instructions.
168:
169: Reg 16 does not correspond to any hardware register, but instead
170: appears in the RTL as an argument pointer prior to reload, and is
171: eliminated during reloading in favor of either the stack or frame
172: pointer. */
173:
174: #define FIRST_PSEUDO_REGISTER 17
175:
176: /* 1 for registers that have pervasive standard uses
177: and are not available for the register allocator.
178: On the 80386, the stack pointer is such, as is the arg pointer. */
179: #define FIXED_REGISTERS \
180: /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \
181: { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 }
182:
183: /* 1 for registers not available across function calls.
184: These must include the FIXED_REGISTERS and also any
185: registers that can be used without being saved.
186: The latter must include the registers where values are returned
187: and the register where structure-value addresses are passed.
188: Aside from that, you can include as many other registers as you like. */
189:
190: #define CALL_USED_REGISTERS \
191: /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \
192: { 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
193:
194: /* Macro to conditionally modify fixed_regs/call_used_regs. */
195: #define CONDITIONAL_REGISTER_USAGE \
196: { \
197: if (flag_pic) \
198: { \
199: fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
200: call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
201: } \
202: }
203:
204: /* Return number of consecutive hard regs needed starting at reg REGNO
205: to hold something of mode MODE.
206: This is ordinarily the length in words of a value of mode MODE
207: but can be less for certain modes in special long registers.
208:
209: Actually there are no two word move instructions for consecutive
210: registers. And only registers 0-3 may have mov byte instructions
211: applied to them.
212: */
213:
214: #define HARD_REGNO_NREGS(REGNO, MODE) \
215: (FP_REGNO_P (REGNO) ? 1 \
216: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
217:
218: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
219: On the 80386, the first 4 cpu registers can hold any mode
220: while the floating point registers may hold only floating point.
221: Make it clear that the fp regs could not hold a 16-byte float. */
222:
223: #define HARD_REGNO_MODE_OK(REGNO, MODE) \
224: ((REGNO) < 2 ? 1 \
225: : (REGNO) < 4 ? 1 \
226: : (REGNO) >= 8 ? ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
227: || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
228: && GET_MODE_UNIT_SIZE (MODE) <= 8) \
229: : (MODE) != QImode)
230:
231: /* Value is 1 if it is a good idea to tie two pseudo registers
232: when one has mode MODE1 and one has mode MODE2.
233: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
234: for any hard reg, then this must be 0 for correct output. */
235:
236: #define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) == (MODE2))
237:
238: /* A C expression returning the cost of moving data from a register of class
239: CLASS1 to one of CLASS2.
240:
241: On the i386, copying between floating-point and fixed-point
242: registers is expensive. */
243:
244: #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
245: ((((CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS) \
246: || ((CLASS2) == FLOAT_REGS && (CLASS1) != FLOAT_REGS)) \
247: ? 10 : 2)
248:
249: /* Specify the registers used for certain standard purposes.
250: The values of these macros are register numbers. */
251:
252: /* on the 386 the pc register is %eip, and is not usable as a general
253: register. The ordinary mov instructions won't work */
254: /* #define PC_REGNUM */
255:
256: /* Register to use for pushing function arguments. */
257: #define STACK_POINTER_REGNUM 7
258:
259: /* Base register for access to local variables of the function. */
260: #define FRAME_POINTER_REGNUM 6
261:
262: /* First floating point reg */
263: #define FIRST_FLOAT_REG 8
264:
265: /* First & last stack-like regs */
266: #define FIRST_STACK_REG FIRST_FLOAT_REG
267: #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
268:
269: /* Value should be nonzero if functions must have frame pointers.
270: Zero means the frame pointer need not be set up (and parms
271: may be accessed via the stack pointer) in functions that seem suitable.
272: This is computed in `reload', in reload1.c. */
273: #define FRAME_POINTER_REQUIRED 0
274:
275: /* Base register for access to arguments of the function. */
276: #define ARG_POINTER_REGNUM 16
277:
278: /* Register in which static-chain is passed to a function. */
279: #define STATIC_CHAIN_REGNUM 2
280:
281: /* Register to hold the addressing base for position independent
282: code access to data items. */
283: #define PIC_OFFSET_TABLE_REGNUM 3
284:
285: /* Register in which address to store a structure value
286: arrives in the function. On the 386, the prologue
287: copies this from the stack to register %eax. */
288: #define STRUCT_VALUE_INCOMING 0
289:
290: /* Place in which caller passes the structure value address.
291: 0 means push the value on the stack like an argument. */
292: #define STRUCT_VALUE 0
293:
294: /* Define the classes of registers for register constraints in the
295: machine description. Also define ranges of constants.
296:
297: One of the classes must always be named ALL_REGS and include all hard regs.
298: If there is more than one class, another class must be named NO_REGS
299: and contain no registers.
300:
301: The name GENERAL_REGS must be the name of a class (or an alias for
302: another name such as ALL_REGS). This is the class of registers
303: that is allowed by "g" or "r" in a register constraint.
304: Also, registers outside this class are allocated only when
305: instructions express preferences for them.
306:
307: The classes must be numbered in nondecreasing order; that is,
308: a larger-numbered class must never be contained completely
309: in a smaller-numbered class.
310:
311: For any two classes, it is very desirable that there be another
312: class that represents their union. */
313:
314:
315: enum reg_class
316: {
317: NO_REGS,
318: AREG, DREG, CREG,
319: Q_REGS, /* %eax %ebx %ecx %edx */
320: SIREG, DIREG,
321: INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
322: GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
323: FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
324: FLOAT_REGS,
325: ALL_REGS, LIM_REG_CLASSES
326: };
327:
328: #define N_REG_CLASSES (int) LIM_REG_CLASSES
329:
330: /* Give names of register classes as strings for dump file. */
331:
332: #define REG_CLASS_NAMES \
333: { "NO_REGS", \
334: "AREG", "DREG", "CREG", \
335: "Q_REGS", \
336: "SIREG", "DIREG", \
337: "INDEX_REGS", \
338: "GENERAL_REGS", \
339: "FP_TOP_REG", "FP_SECOND_REG", \
340: "FLOAT_REGS", \
341: "ALL_REGS" }
342:
343: /* Define which registers fit in which classes.
344: This is an initializer for a vector of HARD_REG_SET
345: of length N_REG_CLASSES. */
346:
347: #define REG_CLASS_CONTENTS \
348: { 0, \
349: 0x1, 0x2, 0x4, /* AREG, DREG, CREG */ \
350: 0xf, /* Q_REGS */ \
351: 0x10, 0x20, /* SIREG, DIREG */ \
352: 0x1007f, /* INDEX_REGS */ \
353: 0x100ff, /* GENERAL_REGS */ \
354: 0x0100, 0x0200, /* FP_TOP_REG, FP_SECOND_REG */ \
355: 0xff00, /* FLOAT_REGS */ \
356: 0x1ffff }
357:
358: /* The same information, inverted:
359: Return the class number of the smallest class containing
360: reg number REGNO. This could be a conditional expression
361: or could index an array. */
362:
363: extern enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
364: #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
365:
366: /* When defined, the compiler allows registers explicitly used in the
367: rtl to be used as spill registers but prevents the compiler from
368: extending the lifetime of these registers. */
369:
370: #define SMALL_REGISTER_CLASSES
371:
372: #define QI_REG_P(X) \
373: (REG_P (X) && REGNO (X) < 4)
374: #define NON_QI_REG_P(X) \
375: (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
376:
377: #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
378: #define FP_REGNO_P(n) ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG)
379:
380: #define STACK_REG_P(xop) (REG_P (xop) && \
381: REGNO (xop) >= FIRST_STACK_REG && \
382: REGNO (xop) <= LAST_STACK_REG)
383:
384: #define NON_STACK_REG_P(xop) (REG_P (xop) && ! STACK_REG_P (xop))
385:
386: #define STACK_TOP_P(xop) (REG_P (xop) && REGNO (xop) == FIRST_STACK_REG)
387:
388: /* Try to maintain the accuracy of the death notes for regs satisfying the
389: following. Important for stack like regs, to know when to pop. */
390:
391: /* #define PRESERVE_DEATH_INFO_REGNO_P(x) FP_REGNO_P(x) */
392:
393: /* 1 if register REGNO can magically overlap other regs.
394: Note that nonzero values work only in very special circumstances. */
395:
396: /* #define OVERLAPPING_REGNO_P(REGNO) FP_REGNO_P (REGNO) */
397:
398: /* The class value for index registers, and the one for base regs. */
399:
400: #define INDEX_REG_CLASS INDEX_REGS
401: #define BASE_REG_CLASS GENERAL_REGS
402:
403: /* Get reg_class from a letter such as appears in the machine description. */
404:
405: #define REG_CLASS_FROM_LETTER(C) \
406: ((C) == 'r' ? GENERAL_REGS : \
407: (C) == 'q' ? Q_REGS : \
408: (C) == 'f' ? FLOAT_REGS : \
409: (C) == 't' ? FP_TOP_REG : \
410: (C) == 'u' ? FP_SECOND_REG : \
411: (C) == 'a' ? AREG : \
412: (C) == 'c' ? CREG : \
413: (C) == 'd' ? DREG : \
414: (C) == 'D' ? DIREG : \
415: (C) == 'S' ? SIREG : NO_REGS)
416:
417: /* The letters I, J, K, L and M in a register constraint string
418: can be used to stand for particular ranges of immediate operands.
419: This macro defines what the ranges are.
420: C is the letter, and VALUE is a constant value.
421: Return 1 if VALUE is in the range specified by C.
422:
423: I is for non-DImode shifts.
424: J is for DImode shifts.
425: K and L are for an `andsi' optimization.
426: M is for shifts that can be executed by the "lea" opcode.
427: */
428:
429: #define CONST_OK_FOR_LETTER_P(VALUE, C) \
430: ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 : \
431: (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 : \
432: (C) == 'K' ? (VALUE) == 0xff : \
433: (C) == 'L' ? (VALUE) == 0xffff : \
434: (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 : \
435: 0)
436:
437: /* Similar, but for floating constants, and defining letters G and H.
438: Here VALUE is the CONST_DOUBLE rtx itself. */
439:
440: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
441: ((C) == 'G' ? (TARGET_80387 && standard_80387_constant_p (VALUE)) : 0)
442:
443: /* Place additional restrictions on the register class to use when it
444: is necessary to be able to hold a value of mode @var{mode} in a reload
445: register for which class @var{class} would ordinarily be used. */
446:
447: #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
448: ((MODE) == QImode && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS) \
449: ? Q_REGS : (CLASS))
450:
451: /* Given an rtx X being reloaded into a reg required to be
452: in class CLASS, return the class of reg to actually use.
453: In general this is just CLASS; but on some machines
454: in some cases it is preferable to use a more restrictive class.
455: On the 80386 series, we prevent floating constants from being
456: reloaded into floating registers (since no move-insn can do that)
457: and we ensure that QImodes aren't reloaded into the esi or edi reg. */
458:
459: /* Don't put CONST_DOUBLE into FLOAT_REGS.
460: QImode must go into class Q_REGS.
461: MODE_INT must not go into FLOAT_REGS. */
462:
463: #define PREFERRED_RELOAD_CLASS(X,CLASS) \
464: (GET_CODE (X) == CONST_DOUBLE \
465: ? (reg_class_subset_p ((CLASS), GENERAL_REGS) || (CLASS) == ALL_REGS \
466: ? (CLASS) : NO_REGS) \
467: : GET_MODE (X) == QImode \
468: ? (! reg_class_subset_p ((CLASS), Q_REGS) ? Q_REGS : (CLASS)) \
469: : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT && (CLASS) == FLOAT_REGS ? \
470: GENERAL_REGS : (CLASS)))
471:
472: /* Return the maximum number of consecutive registers
473: needed to represent mode MODE in a register of class CLASS. */
474: /* On the 80386, this is the size of MODE in words,
475: except in the FP regs, where a single reg is always enough. */
476: #define CLASS_MAX_NREGS(CLASS, MODE) \
477: ((CLASS) == FLOAT_REGS ? 1 : \
478: (CLASS) == FP_TOP_REG ? 1 : \
479: (CLASS) == FP_SECOND_REG ? 1 : \
480: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
481:
482: /* Stack layout; function entry, exit and calling. */
483:
484: /* Define this if pushing a word on the stack
485: makes the stack pointer a smaller address. */
486: #define STACK_GROWS_DOWNWARD
487:
488: /* Define this if the nominal address of the stack frame
489: is at the high-address end of the local variables;
490: that is, each additional local variable allocated
491: goes at a more negative offset in the frame. */
492: #define FRAME_GROWS_DOWNWARD
493:
494: /* Offset within stack frame to start allocating local variables at.
495: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
496: first local allocated. Otherwise, it is the offset to the BEGINNING
497: of the first local allocated. */
498: #define STARTING_FRAME_OFFSET 0
499:
500: /* If we generate an insn to push BYTES bytes,
501: this says how many the stack pointer really advances by.
502: On 386 pushw decrements by exactly 2 no matter what the position was.
503: On the 386 there is no pushb; we use pushw instead, and this
504: has the effect of rounding up to 2. */
505:
506: #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & (-2))
507:
508: /* Offset of first parameter from the argument pointer register value. */
509: #define FIRST_PARM_OFFSET(FNDECL) 0
510:
511: /* Value is the number of bytes of arguments automatically
512: popped when returning from a subroutine call.
513: FUNTYPE is the data type of the function (as a tree),
514: or for a library call it is an identifier node for the subroutine name.
515: SIZE is the number of bytes of arguments passed on the stack.
516:
517: On the 80386, the RTD insn may be used to pop them if the number
518: of args is fixed, but if the number is variable then the caller
519: must pop them all. RTD can't be used for library calls now
520: because the library is compiled with the Unix compiler.
521: Use of RTD is a selectable option, since it is incompatible with
522: standard Unix calling sequences. If the option is not selected,
523: the caller must always pop the args. */
524:
525: #define RETURN_POPS_ARGS(FUNTYPE,SIZE) \
526: (TREE_CODE (FUNTYPE) == IDENTIFIER_NODE ? 0 \
527: : (TARGET_RTD \
528: && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
529: || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
530: == void_type_node))) ? (SIZE) \
531: : (aggregate_value_p (FUNTYPE)) ? GET_MODE_SIZE (Pmode) : 0)
532:
533: #define FUNCTION_VALUE(VALTYPE, FUNC) \
534: gen_rtx (REG, TYPE_MODE (VALTYPE), \
535: VALUE_REGNO (TYPE_MODE (VALTYPE)))
536:
537: /* Define how to find the value returned by a library function
538: assuming the value has mode MODE. */
539:
540: #define LIBCALL_VALUE(MODE) \
541: gen_rtx (REG, MODE, VALUE_REGNO (MODE))
542:
543: /* 1 if N is a possible register number for function argument passing.
544: On the 80386, no registers are used in this way.
545: *NOTE* -mregparm does not work.
546: It exists only to test register calling conventions. */
547:
548: #define FUNCTION_ARG_REGNO_P(N) 0
549:
550: /* Define a data type for recording info about an argument list
551: during the scan of that argument list. This data type should
552: hold all necessary information about the function itself
553: and about the args processed so far, enough to enable macros
554: such as FUNCTION_ARG to determine where the next arg should go.
555:
556: On the 80386, this is a single integer, which is a number of bytes
557: of arguments scanned so far. */
558:
559: #define CUMULATIVE_ARGS int
560:
561: /* Initialize a variable CUM of type CUMULATIVE_ARGS
562: for a call to a function whose data type is FNTYPE.
563: For a library call, FNTYPE is 0.
564:
565: On the 80386, the offset starts at 0. */
566:
567: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \
568: ((CUM) = 0)
569:
570: /* Update the data in CUM to advance over an argument
571: of mode MODE and data type TYPE.
572: (TYPE is null for libcalls where that information may not be available.) */
573:
574: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
575: ((CUM) += ((MODE) != BLKmode \
576: ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
577: : (int_size_in_bytes (TYPE) + 3) & ~3))
578:
579: /* Define where to put the arguments to a function.
580: Value is zero to push the argument on the stack,
581: or a hard register in which to store the argument.
582:
583: MODE is the argument's machine mode.
584: TYPE is the data type of the argument (as a tree).
585: This is null for libcalls where that information may
586: not be available.
587: CUM is a variable of type CUMULATIVE_ARGS which gives info about
588: the preceding args and about the function being called.
589: NAMED is nonzero if this argument is a named parameter
590: (otherwise it is an extra parameter matching an ellipsis). */
591:
592:
593: /* On the 80386 all args are pushed, except if -mregparm is specified
594: then the first two words of arguments are passed in EAX, EDX.
595: *NOTE* -mregparm does not work.
596: It exists only to test register calling conventions. */
597:
598: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
599: ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx (REG, (MODE), (CUM) / 4) : 0)
600:
601: /* For an arg passed partly in registers and partly in memory,
602: this is the number of registers used.
603: For args passed entirely in registers or entirely in memory, zero. */
604:
605:
606: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
607: ((TARGET_REGPARM && (CUM) < 8 \
608: && 8 < ((CUM) + ((MODE) == BLKmode \
609: ? int_size_in_bytes (TYPE) \
610: : GET_MODE_SIZE (MODE)))) \
611: ? 2 - (CUM) / 4 : 0)
612:
613: /* This macro generates the assembly code for function entry.
614: FILE is a stdio stream to output the code to.
615: SIZE is an int: how many units of temporary storage to allocate.
616: Refer to the array `regs_ever_live' to determine which registers
617: to save; `regs_ever_live[I]' is nonzero if register number I
618: is ever used in the function. This macro is responsible for
619: knowing which registers should not be saved even if used. */
620:
621: #define FUNCTION_PROLOGUE(FILE, SIZE) \
622: function_prologue (FILE, SIZE)
623:
624: /* Output assembler code to FILE to increment profiler label # LABELNO
625: for profiling a function entry. */
626:
627: #define FUNCTION_PROFILER(FILE, LABELNO) \
628: { \
629: if (flag_pic) \
630: { \
631: fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n", \
632: LPREFIX, (LABELNO)); \
633: fprintf (FILE, "\tcall *_mcount@GOT(%%ebx)\n"); \
634: } \
635: else \
636: { \
637: fprintf (FILE, "\tmovl $%sP%d,%%edx\n", LPREFIX, (LABELNO)); \
638: fprintf (FILE, "\tcall _mcount\n"); \
639: } \
640: }
641:
642: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
643: the stack pointer does not matter. The value is tested only in
644: functions that have frame pointers.
645: No definition is equivalent to always zero. */
646: /* Note on the 386 it might be more efficient not to define this since
647: we have to restore it ourselves from the frame pointer, in order to
648: use pop */
649:
650: #define EXIT_IGNORE_STACK 1
651:
652: /* This macro generates the assembly code for function exit,
653: on machines that need it. If FUNCTION_EPILOGUE is not defined
654: then individual return instructions are generated for each
655: return statement. Args are same as for FUNCTION_PROLOGUE.
656:
657: The function epilogue should not depend on the current stack pointer!
658: It should use the frame pointer only. This is mandatory because
659: of alloca; we also take advantage of it to omit stack adjustments
660: before returning.
661:
662: If the last non-note insn in the function is a BARRIER, then there
663: is no need to emit a function prologue, because control does not fall
664: off the end. This happens if the function ends in an "exit" call, or
665: if a `return' insn is emitted directly into the function. */
666:
667: #define FUNCTION_EPILOGUE(FILE, SIZE) \
668: do { \
669: rtx last = get_last_insn (); \
670: if (last && GET_CODE (last) == NOTE) \
671: last = prev_nonnote_insn (last); \
672: if (! last || GET_CODE (last) != BARRIER) \
673: function_epilogue (FILE, SIZE); \
674: } while (0)
675:
676: /* Output assembler code for a block containing the constant parts
677: of a trampoline, leaving space for the variable parts. */
678:
679: /* On the 386, the trampoline contains three instructions:
680: mov #STATIC,ecx
681: mov #FUNCTION,eax
682: jmp @eax */
683: #define TRAMPOLINE_TEMPLATE(FILE) \
684: { \
685: ASM_OUTPUT_CHAR (FILE, gen_rtx (CONST_INT, VOIDmode, 0xb9)); \
686: ASM_OUTPUT_SHORT (FILE, const0_rtx); \
687: ASM_OUTPUT_SHORT (FILE, const0_rtx); \
688: ASM_OUTPUT_CHAR (FILE, gen_rtx (CONST_INT, VOIDmode, 0xb8)); \
689: ASM_OUTPUT_SHORT (FILE, const0_rtx); \
690: ASM_OUTPUT_SHORT (FILE, const0_rtx); \
691: ASM_OUTPUT_CHAR (FILE, gen_rtx (CONST_INT, VOIDmode, 0xff)); \
692: ASM_OUTPUT_CHAR (FILE, gen_rtx (CONST_INT, VOIDmode, 0xe0)); \
693: }
694:
695: /* Length in units of the trampoline for entering a nested function. */
696:
697: #define TRAMPOLINE_SIZE 12
698:
699: /* Emit RTL insns to initialize the variable parts of a trampoline.
700: FNADDR is an RTX for the address of the function's pure code.
701: CXT is an RTX for the static chain value for the function. */
702:
703: #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
704: { \
705: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 1)), CXT); \
706: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 6)), FNADDR); \
707: }
708:
709: /* Definitions for register eliminations.
710:
711: This is an array of structures. Each structure initializes one pair
712: of eliminable registers. The "from" register number is given first,
713: followed by "to". Eliminations of the same "from" register are listed
714: in order of preference.
715:
716: We have two registers that can be eliminated on the i386. First, the
717: frame pointer register can often be eliminated in favor of the stack
718: pointer register. Secondly, the argument pointer register can always be
719: eliminated; it is replaced with either the stack or frame pointer. */
720:
721: #define ELIMINABLE_REGS \
722: {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
723: { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
724: { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
725:
726: /* Given FROM and TO register numbers, say whether this elimination is allowed.
727: Frame pointer elimination is automatically handled.
728:
729: For the i386, if frame pointer elimination is being done, we would like to
730: convert ap into sp, not fp.
731:
732: All other eliminations are valid. */
733:
734: #define CAN_ELIMINATE(FROM, TO) \
735: ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
736: ? ! frame_pointer_needed \
737: : 1)
738:
739: /* Define the offset between two registers, one to be eliminated, and the other
740: its replacement, at the start of a routine. */
741:
742: #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
743: { \
744: if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
745: (OFFSET) = 8; /* Skip saved PC and previous frame pointer */ \
746: else \
747: { \
748: int regno; \
749: int offset = 0; \
750: \
751: for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
752: if ((regs_ever_live[regno] && ! call_used_regs[regno]) \
753: || (current_function_uses_pic_offset_table \
754: && regno == PIC_OFFSET_TABLE_REGNUM)) \
755: offset += 4; \
756: \
757: (OFFSET) = offset + get_frame_size (); \
758: \
759: if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
760: (OFFSET) += 4; /* Skip saved PC */ \
761: } \
762: }
763:
764: /* Addressing modes, and classification of registers for them. */
765:
766: /* #define HAVE_POST_INCREMENT */
767: /* #define HAVE_POST_DECREMENT */
768:
769: /* #define HAVE_PRE_DECREMENT */
770: /* #define HAVE_PRE_INCREMENT */
771:
772: /* Macros to check register numbers against specific register classes. */
773:
774: /* These assume that REGNO is a hard or pseudo reg number.
775: They give nonzero only if REGNO is a hard reg of the suitable class
776: or a pseudo reg currently allocated to a suitable hard reg.
777: Since they use reg_renumber, they are safe only once reg_renumber
778: has been allocated, which happens in local-alloc.c. */
779:
780: #define REGNO_OK_FOR_INDEX_P(REGNO) \
781: ((REGNO) < STACK_POINTER_REGNUM \
782: || (unsigned) reg_renumber[REGNO] < STACK_POINTER_REGNUM)
783:
784: #define REGNO_OK_FOR_BASE_P(REGNO) \
785: ((REGNO) <= STACK_POINTER_REGNUM \
786: || (REGNO) == ARG_POINTER_REGNUM \
787: || (unsigned) reg_renumber[REGNO] <= STACK_POINTER_REGNUM)
788:
789: #define REGNO_OK_FOR_SIREG_P(REGNO) ((REGNO) == 4 || reg_renumber[REGNO] == 4)
790: #define REGNO_OK_FOR_DIREG_P(REGNO) ((REGNO) == 5 || reg_renumber[REGNO] == 5)
791:
792: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
793: and check its validity for a certain class.
794: We have two alternate definitions for each of them.
795: The usual definition accepts all pseudo regs; the other rejects
796: them unless they have been allocated suitable hard regs.
797: The symbol REG_OK_STRICT causes the latter definition to be used.
798:
799: Most source files want to accept pseudo regs in the hope that
800: they will get allocated to the class that the insn wants them to be in.
801: Source files for reload pass need to be strict.
802: After reload, it makes no difference, since pseudo regs have
803: been eliminated by then. */
804:
805: #ifndef REG_OK_STRICT
806:
807: /* Nonzero if X is a hard reg that can be used as an index or if
808: it is a pseudo reg. */
809:
810: #define REG_OK_FOR_INDEX_P(X) \
811: (REGNO (X) < STACK_POINTER_REGNUM \
812: || REGNO (X) >= FIRST_PSEUDO_REGISTER)
813:
814: /* Nonzero if X is a hard reg that can be used as a base reg
815: of if it is a pseudo reg. */
816: /* ?wfs */
817:
818: #define REG_OK_FOR_BASE_P(X) \
819: (REGNO (X) <= STACK_POINTER_REGNUM \
820: || REGNO (X) == ARG_POINTER_REGNUM \
821: || REGNO(X) >= FIRST_PSEUDO_REGISTER)
822:
823: #define REG_OK_FOR_STRREG_P(X) \
824: (REGNO (X) == 4 || REGNO (X) == 5 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
825:
826: #else
827:
828: /* Nonzero if X is a hard reg that can be used as an index. */
829: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
830: /* Nonzero if X is a hard reg that can be used as a base reg. */
831: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
832: #define REG_OK_FOR_STRREG_P(X) \
833: (REGNO_OK_FOR_DIREG_P (REGNO (X)) || REGNO_OK_FOR_SIREG_P (REGNO (X)))
834:
835: #endif
836:
837: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
838: that is a valid memory address for an instruction.
839: The MODE argument is the machine mode for the MEM expression
840: that wants to use this address.
841:
842: The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
843: except for CONSTANT_ADDRESS_P which is usually machine-independent.
844:
845: See legitimize_pic_address in i386.c for details as to what
846: constitutes a legitimate address when -fpic is used. */
847:
848: #define MAX_REGS_PER_ADDRESS 2
849:
850: #define CONSTANT_ADDRESS_P(X) CONSTANT_P (X)
851:
852: /* Nonzero if the constant value X is a legitimate general operand.
853: It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
854:
855: #define LEGITIMATE_CONSTANT_P(X) 1
856:
857: #define GO_IF_INDEXABLE_BASE(X, ADDR) \
858: if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) goto ADDR
859:
860: #define LEGITIMATE_INDEX_REG_P(X) \
861: (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
862:
863: /* Return 1 if X is an index or an index times a scale. */
864:
865: #define LEGITIMATE_INDEX_P(X) \
866: (LEGITIMATE_INDEX_REG_P (X) \
867: || (GET_CODE (X) == MULT \
868: && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
869: && GET_CODE (XEXP (X, 1)) == CONST_INT \
870: && (INTVAL (XEXP (X, 1)) == 2 \
871: || INTVAL (XEXP (X, 1)) == 4 \
872: || INTVAL (XEXP (X, 1)) == 8)))
873:
874: /* Go to ADDR if X is an index term, a base reg, or a sum of those. */
875:
876: #define GO_IF_INDEXING(X, ADDR) \
877: { if (LEGITIMATE_INDEX_P (X)) goto ADDR; \
878: GO_IF_INDEXABLE_BASE (X, ADDR); \
879: if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
880: { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
881: if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
882: { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
883:
884: /* We used to allow this, but it isn't ever used.
885: || ((GET_CODE (X) == POST_DEC || GET_CODE (X) == POST_INC) \
886: && REG_P (XEXP (X, 0)) \
887: && REG_OK_FOR_STRREG_P (XEXP (X, 0))) \
888: */
889:
890: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
891: { \
892: if (CONSTANT_ADDRESS_P (X) \
893: && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
894: goto ADDR; \
895: GO_IF_INDEXING (X, ADDR); \
896: if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
897: { \
898: rtx x0 = XEXP (X, 0); \
899: if (! flag_pic || ! SYMBOLIC_CONST (XEXP (X, 1))) \
900: { GO_IF_INDEXING (x0, ADDR); } \
901: else if (x0 == pic_offset_table_rtx) \
902: goto ADDR; \
903: else if (GET_CODE (x0) == PLUS) \
904: { \
905: if (XEXP (x0, 0) == pic_offset_table_rtx) \
906: { GO_IF_INDEXABLE_BASE (XEXP (x0, 1), ADDR); } \
907: if (XEXP (x0, 1) == pic_offset_table_rtx) \
908: { GO_IF_INDEXABLE_BASE (XEXP (x0, 0), ADDR); } \
909: } \
910: } \
911: }
912:
913: /* Try machine-dependent ways of modifying an illegitimate address
914: to be legitimate. If we find one, return the new, valid address.
915: This macro is used in only one place: `memory_address' in explow.c.
916:
917: OLDX is the address as it was before break_out_memory_refs was called.
918: In some cases it is useful to look at this to decide what needs to be done.
919:
920: MODE and WIN are passed so that this macro can use
921: GO_IF_LEGITIMATE_ADDRESS.
922:
923: It is always safe for this macro to do nothing. It exists to recognize
924: opportunities to optimize the output.
925:
926: For the 80386, we handle X+REG by loading X into a register R and
927: using R+REG. R will go in a general reg and indexing will be used.
928: However, if REG is a broken-out memory address or multiplication,
929: nothing needs to be done because REG can certainly go in a general reg.
930:
931: When -fpic is used, special handling is needed for symbolic references.
932: See comments by legitimize_pic_address in i386.c for details. */
933:
934: #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
935: { extern rtx legitimize_pic_address (); \
936: int ch = (X) != (OLDX); \
937: if (flag_pic && SYMBOLIC_CONST (X)) \
938: { \
939: (X) = legitimize_pic_address (X, 0); \
940: if (memory_address_p (MODE, X)) \
941: goto WIN; \
942: } \
943: if (GET_CODE (X) == PLUS) \
944: { if (GET_CODE (XEXP (X, 0)) == MULT) \
945: ch = 1, XEXP (X, 0) = force_operand (XEXP (X, 0), 0); \
946: if (GET_CODE (XEXP (X, 1)) == MULT) \
947: ch = 1, XEXP (X, 1) = force_operand (XEXP (X, 1), 0); \
948: if (ch && GET_CODE (XEXP (X, 1)) == REG \
949: && GET_CODE (XEXP (X, 0)) == REG) \
950: goto WIN; \
951: if (flag_pic && SYMBOLIC_CONST (XEXP (X, 1))) \
952: ch = 1, (X) = legitimize_pic_address (X, 0); \
953: if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
954: if (GET_CODE (XEXP (X, 0)) == REG) \
955: { register rtx temp = gen_reg_rtx (Pmode); \
956: register rtx val = force_operand (XEXP (X, 1), temp); \
957: if (val != temp) emit_move_insn (temp, val, 0); \
958: XEXP (X, 1) = temp; \
959: goto WIN; } \
960: else if (GET_CODE (XEXP (X, 1)) == REG) \
961: { register rtx temp = gen_reg_rtx (Pmode); \
962: register rtx val = force_operand (XEXP (X, 0), temp); \
963: if (val != temp) emit_move_insn (temp, val, 0); \
964: XEXP (X, 0) = temp; \
965: goto WIN; }}}
966:
967: /* Nonzero if the constant value X is a legitimate general operand
968: when generating PIC code. It is given that flag_pic is on and
969: that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
970:
971: #define LEGITIMATE_PIC_OPERAND_P(X) \
972: (! SYMBOLIC_CONST (X) \
973: || (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)))
974:
975: #define SYMBOLIC_CONST(X) \
976: (GET_CODE (X) == SYMBOL_REF \
977: || GET_CODE (X) == LABEL_REF \
978: || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
979:
980: /* Go to LABEL if ADDR (a legitimate address expression)
981: has an effect that depends on the machine mode it is used for.
982: On the 80386, only postdecrement and postincrement address depend thus
983: (the amount of decrement or increment being the length of the operand). */
984: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
985: if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == POST_DEC) goto LABEL
986:
987: /* Define this macro if references to a symbol must be treated
988: differently depending on something about the variable or
989: function named by the symbol (such as what section it is in).
990:
991: On i386, if using PIC, mark a SYMBOL_REF for a static declaration
992: so that we may access it directly in the GOT. */
993:
994: #define ENCODE_SECTION_INFO(DECL) \
995: do \
996: { \
997: if (flag_pic) \
998: { \
999: rtx decl_rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) == 'c' \
1000: ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \
1001: SYMBOL_REF_FLAG (XEXP (decl_rtl, 0)) = ! TREE_PUBLIC (DECL); \
1002: } \
1003: } \
1004: while (0)
1005:
1006: /* Specify the machine mode that this machine uses
1007: for the index in the tablejump instruction. */
1008: #define CASE_VECTOR_MODE Pmode
1009:
1010: /* Define this if the tablejump instruction expects the table
1011: to contain offsets from the address of the table.
1012: Do not define this if the table should contain absolute addresses. */
1013: /* #define CASE_VECTOR_PC_RELATIVE */
1014:
1015: /* Specify the tree operation to be used to convert reals to integers.
1016: This should be changed to take advantage of fist --wfs ??
1017: */
1018: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1019:
1020: /* This is the kind of divide that is easiest to do in the general case. */
1021: #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1022:
1023: /* Define this as 1 if `char' should by default be signed; else as 0. */
1024: #define DEFAULT_SIGNED_CHAR 1
1025:
1026: /* Max number of bytes we can move from memory to memory
1027: in one reasonably fast instruction. */
1028: #define MOVE_MAX 4
1029:
1030: /* MOVE_RATIO is the number of move instructions that is better than a
1031: block move. Make this large on i386, since the block move is very
1032: inefficient with small blocks, and the hard register needs of the
1033: block move require much reload work. */
1034: #define MOVE_RATIO 5
1035:
1036: /* Define this if zero-extension is slow (more than one real instruction). */
1037: /* #define SLOW_ZERO_EXTEND */
1038:
1039: /* Nonzero if access to memory by bytes is slow and undesirable. */
1040: #define SLOW_BYTE_ACCESS 0
1041:
1042: /* Define if shifts truncate the shift count
1043: which implies one can omit a sign-extension or zero-extension
1044: of a shift count. */
1045: /* One i386, shifts do truncate the count. But bit opcodes don't. */
1046:
1047: /* #define SHIFT_COUNT_TRUNCATED */
1048:
1049: /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1050: is done just by pretending it is already truncated. */
1051: #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1052:
1053: /* We assume that the store-condition-codes instructions store 0 for false
1054: and some other value for true. This is the value stored for true. */
1055:
1056: #define STORE_FLAG_VALUE 1
1057:
1058: /* When a prototype says `char' or `short', really pass an `int'.
1059: (The 386 can't easily push less than an int.) */
1060:
1061: #define PROMOTE_PROTOTYPES
1062:
1063: /* Specify the machine mode that pointers have.
1064: After generation of rtl, the compiler makes no further distinction
1065: between pointers and any other objects of this machine mode. */
1066: #define Pmode SImode
1067:
1068: /* A function address in a call instruction
1069: is a byte address (for indexing purposes)
1070: so give the MEM rtx a byte's mode. */
1071: #define FUNCTION_MODE QImode
1072:
1073: /* Define this if addresses of constant functions
1074: shouldn't be put through pseudo regs where they can be cse'd.
1075: Desirable on the 386 because a CALL with a constant address is
1076: not much slower than one with a register address. */
1077: #define NO_FUNCTION_CSE
1078:
1079: /* Provide the costs of a rtl expression. This is in the body of a
1080: switch on CODE. */
1081:
1082: #define RTX_COSTS(X,CODE) \
1083: case MULT: \
1084: return COSTS_N_INSNS (10); \
1085: case DIV: \
1086: case UDIV: \
1087: case MOD: \
1088: case UMOD: \
1089: return COSTS_N_INSNS (40);
1090:
1091:
1092: /* Compute the cost of computing a constant rtl expression RTX
1093: whose rtx-code is CODE. The body of this macro is a portion
1094: of a switch statement. If the code is computed here,
1095: return it with a return statement. Otherwise, break from the switch. */
1096:
1097: #define CONST_COSTS(RTX,CODE) \
1098: case CONST_INT: \
1099: case CONST: \
1100: case LABEL_REF: \
1101: case SYMBOL_REF: \
1102: return flag_pic && SYMBOLIC_CONST (RTX) ? 2 : 0; \
1103: case CONST_DOUBLE: \
1104: { \
1105: int code = standard_80387_constant_p (RTX); \
1106: return code == 1 ? 0 : \
1107: code == 2 ? 1 : \
1108: 2; \
1109: } \
1110: case PLUS: \
1111: if (GET_CODE (XEXP (RTX, 0)) == REG \
1112: && GET_CODE (XEXP (RTX, 1)) == CONST_INT) \
1113: return 1;
1114:
1115: /* Compute the cost of an address. This is meant to approximate the size
1116: and/or execution delay of an insn using that address. If the cost is
1117: approximated by the RTL complexity, including CONST_COSTS above, as
1118: is usually the case for CISC machines, this macro should not be defined.
1119: For aggressively RISCy machines, only one insn format is allowed, so
1120: this macro should be a constant. The value of this macro only matters
1121: for valid addresses.
1122:
1123: For i386, it is better to use a complex address than let gcc copy
1124: the address into a reg and make a new pseudo. But not if the address
1125: requires to two regs - that would mean more pseudos with longer
1126: lifetimes. */
1127:
1128: #define ADDRESS_COST(RTX) \
1129: ((CONSTANT_P (RTX) \
1130: || (GET_CODE (RTX) == PLUS && CONSTANT_P (XEXP (RTX, 1)) \
1131: && REG_P (XEXP (RTX, 0)))) ? 0 \
1132: : REG_P (RTX) ? 1 \
1133: : 2)
1134:
1135: /* Tell final.c how to eliminate redundant test instructions. */
1136:
1137: /* Here we define machine-dependent flags and fields in cc_status
1138: (see `conditions.h'). */
1139:
1140: /* Set if the cc value is actually in the 80387, so a floating point
1141: conditional branch must be output. */
1142: #define CC_IN_80387 04000
1143:
1144: /* Set if the CC value was stored in a nonstandard way, so that
1145: the state of equality is indicated by zero in the carry bit. */
1146: #define CC_Z_IN_NOT_C 010000
1147:
1148: /* Store in cc_status the expressions
1149: that the condition codes will describe
1150: after execution of an instruction whose pattern is EXP.
1151: Do not alter them if the instruction would not alter the cc's. */
1152:
1153: #define NOTICE_UPDATE_CC(EXP, INSN) \
1154: notice_update_cc((EXP))
1155:
1156: /* Output a signed jump insn. Use template NORMAL ordinarily, or
1157: FLOAT following a floating point comparison.
1158: Use NO_OV following an arithmetic insn that set the cc's
1159: before a test insn that was deleted.
1160: NO_OV may be zero, meaning final should reinsert the test insn
1161: because the jump cannot be handled properly without it. */
1162:
1163: #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1164: { \
1165: if (cc_prev_status.flags & CC_IN_80387) \
1166: return FLOAT; \
1167: if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1168: return NO_OV; \
1169: return NORMAL; \
1170: }
1171:
1172: /* Control the assembler format that we output, to the extent
1173: this does not vary between assemblers. */
1174:
1175: /* How to refer to registers in assembler output.
1176: This sequence is indexed by compiler's hard-register-number (see above). */
1177:
1178: /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
1179: For non floating point regs, the following are the HImode names.
1180:
1181: For float regs, the stack top is sometimes referred to as "%st(0)"
1182: instead of just "%st". PRINT_REG in i386.c handles with with the
1183: "y" code. */
1184:
1185: #define HI_REGISTER_NAMES \
1186: {"ax","dx","cx","bx","si","di","bp","sp", \
1187: "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","" }
1188:
1189: #define REGISTER_NAMES HI_REGISTER_NAMES
1190:
1191: /* Table of additional register names to use in user input. */
1192:
1193: #define ADDITIONAL_REGISTER_NAMES \
1194: { "eax", 0, "edx", 1, "ecx", 2, "ebx", 3, \
1195: "esi", 4, "edi", 5, "ebp", 6, "esp", 7, \
1196: "al", 0, "dl", 1, "cl", 2, "bl", 3, \
1197: "ah", 0, "dh", 1, "ch", 2, "bh", 3 }
1198:
1199: /* Note we are omitting these since currently I don't know how
1200: to get gcc to use these, since they want the same but different
1201: number as al, and ax.
1202: */
1203:
1204: /* note the last four are not really qi_registsers, but
1205: the md will have to never output movb into one of them
1206: only a movw . There is no movb into the last four regs */
1207:
1208: #define QI_REGISTER_NAMES \
1209: {"al", "dl", "cl", "bl", "si", "di", "bp", "sp",}
1210:
1211: /* These parallel the array above, and can be used to access bits 8:15
1212: of regs 0 through 3. */
1213:
1214: #define QI_HIGH_REGISTER_NAMES \
1215: {"ah", "dh", "ch", "bh", }
1216:
1217: /* How to renumber registers for dbx and gdb. */
1218:
1219: /* {0,2,1,3,6,7,4,5,12,13,14,15,16,17} */
1220: #define DBX_REGISTER_NUMBER(n) \
1221: ((n) == 0 ? 0 : \
1222: (n) == 1 ? 2 : \
1223: (n) == 2 ? 1 : \
1224: (n) == 3 ? 3 : \
1225: (n) == 4 ? 6 : \
1226: (n) == 5 ? 7 : \
1227: (n) == 6 ? 4 : \
1228: (n) == 7 ? 5 : \
1229: (n) + 4)
1230:
1231: /* This is how to output the definition of a user-level label named NAME,
1232: such as the label on a static function or variable NAME. */
1233:
1234: #define ASM_OUTPUT_LABEL(FILE,NAME) \
1235: (assemble_name (FILE, NAME), fputs (":\n", FILE))
1236:
1237: /* This is how to output an assembler line defining a `double' constant. */
1238:
1239: #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1240: fprintf (FILE, "%s %.22e\n", ASM_DOUBLE, (VALUE))
1241:
1242:
1243: /* This is how to output an assembler line defining a `float' constant. */
1244:
1245: #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1246: do { union { float f; long l;} tem; \
1247: tem.f = (VALUE); \
1248: fprintf((FILE), "%s 0x%x\n", ASM_LONG, tem.l); \
1249: } while (0)
1250:
1251:
1252: /* Store in OUTPUT a string (made with alloca) containing
1253: an assembler-name for a local static variable named NAME.
1254: LABELNO is an integer which is different for each call. */
1255:
1256: #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1257: ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1258: sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1259:
1260:
1261:
1262: /* This is how to output an assembler line defining an `int' constant. */
1263:
1264: #define ASM_OUTPUT_INT(FILE,VALUE) \
1265: ( fprintf (FILE, "%s ", ASM_LONG), \
1266: output_addr_const (FILE,(VALUE)), \
1267: putc('\n',FILE))
1268:
1269: /* Likewise for `char' and `short' constants. */
1270: /* is this supposed to do align too?? */
1271:
1272: #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1273: ( fprintf (FILE, "%s ", ASM_SHORT), \
1274: output_addr_const (FILE,(VALUE)), \
1275: putc('\n',FILE))
1276:
1277: /*
1278: #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1279: ( fprintf (FILE, "%s ", ASM_BYTE_OP), \
1280: output_addr_const (FILE,(VALUE)), \
1281: fputs (",", FILE), \
1282: output_addr_const (FILE,(VALUE)), \
1283: fputs (" >> 8\n",FILE))
1284: */
1285:
1286:
1287: #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1288: ( fprintf (FILE, "%s ", ASM_BYTE_OP), \
1289: output_addr_const (FILE, (VALUE)), \
1290: putc ('\n', FILE))
1291:
1292: /* This is how to output an assembler line for a numeric constant byte. */
1293:
1294: #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1295: fprintf ((FILE), "%s 0x%x\n", ASM_BYTE_OP, (VALUE))
1296:
1297: /* This is how to output an insn to push a register on the stack.
1298: It need not be very fast code. */
1299:
1300: #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1301: fprintf (FILE, "\tpushl e%s\n", reg_names[REGNO])
1302:
1303: /* This is how to output an insn to pop a register from the stack.
1304: It need not be very fast code. */
1305:
1306: #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1307: fprintf (FILE, "\tpopl e%s\n", reg_names[REGNO])
1308:
1309: /* This is how to output an element of a case-vector that is absolute.
1310: */
1311:
1312: #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1313: fprintf (FILE, "%s %s%d\n", ASM_LONG, LPREFIX, VALUE)
1314:
1315: /* This is how to output an element of a case-vector that is relative.
1316: We don't use these on the 386 yet, because the ATT assembler can't do
1317: forward reference the differences.
1318: */
1319:
1320: #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1321: fprintf (FILE, "\t.word %s%d-%s%d\n",LPREFIX, VALUE,LPREFIX, REL)
1322:
1323: /* Define the parentheses used to group arithmetic operations
1324: in assembler code. */
1325:
1326: #define ASM_OPEN_PAREN ""
1327: #define ASM_CLOSE_PAREN ""
1328:
1329: /* Define results of standard character escape sequences. */
1330: #define TARGET_BELL 007
1331: #define TARGET_BS 010
1332: #define TARGET_TAB 011
1333: #define TARGET_NEWLINE 012
1334: #define TARGET_VT 013
1335: #define TARGET_FF 014
1336: #define TARGET_CR 015
1337:
1338: /* Print operand X (an rtx) in assembler syntax to file FILE.
1339: CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1340: The CODE z takes the size of operand from the following digit, and
1341: outputs b,w,or l respectively.
1342:
1343: On the 80386, we use several such letters:
1344: f -- float insn (print a CONST_DOUBLE as a float rather than in hex).
1345: L,W,B,Q,S -- print the opcode suffix for specified size of operand.
1346: R -- print the prefix for register names.
1347: z -- print the opcode suffix for the size of the current operand.
1348: * -- print a star (in certain assembler syntax)
1349: w -- print the operand as if it's a "word" (HImode) even if it isn't.
1350: b -- print the operand as if it's a byte (QImode) even if it isn't.
1351: c -- don't print special prefixes before constant operands. */
1352:
1353: #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1354: ((CODE) == '*')
1355:
1356: #define PRINT_OPERAND(FILE, X, CODE) \
1357: print_operand (FILE, X, CODE)
1358:
1359:
1360: #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1361: print_operand_address (FILE, ADDR)
1362:
1363: /* Output the prefix for an immediate operand, or for an offset operand. */
1364: #define PRINT_IMMED_PREFIX(FILE) fputs (IP, (FILE))
1365: #define PRINT_OFFSET_PREFIX(FILE) fputs (IP, (FILE))
1366:
1367: /* Routines in libgcc that return floats must return them in an fp reg,
1368: just as other functions do which return such values.
1369: These macros make that happen. */
1370:
1371: #define FLOAT_VALUE_TYPE float
1372: #define INTIFY(FLOATVAL) FLOATVAL
1373:
1374: /* Nonzero if INSN magically clobbers register REGNO. */
1375:
1376: /* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) \
1377: (FP_REGNO_P (REGNO) \
1378: && (GET_CODE (INSN) == JUMP_INSN || GET_CODE (INSN) == BARRIER))
1379: */
1380:
1381: /* a letter which is not needed by the normal asm syntax, which
1382: we can use for operand syntax in the extended asm */
1383:
1384: #define ASM_OPERAND_LETTER '#'
1385:
1386: #define RET return ""
1387: #define AT_SP(mode) (gen_rtx (MEM, (mode), stack_pointer_rtx))
1388:
1389: /*
1390: Local variables:
1391: version-control: t
1392: End:
1393: */
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